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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.50 96.97 92.87 97.88 100.00 98.37 98.03 98.37


Total test records in report: 457
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T306 /workspace/coverage/default/30.rom_ctrl_stress_all.3138498382 May 07 03:30:42 PM PDT 24 May 07 03:32:09 PM PDT 24 36466370301 ps
T307 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3036403529 May 07 03:29:36 PM PDT 24 May 07 03:29:55 PM PDT 24 1319080988 ps
T308 /workspace/coverage/default/42.rom_ctrl_alert_test.1444425334 May 07 03:31:26 PM PDT 24 May 07 03:31:58 PM PDT 24 8371667694 ps
T309 /workspace/coverage/default/16.rom_ctrl_stress_all.3453570784 May 07 03:29:54 PM PDT 24 May 07 03:30:18 PM PDT 24 368876065 ps
T310 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2825666366 May 07 03:31:23 PM PDT 24 May 07 03:31:50 PM PDT 24 11482536468 ps
T311 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2785518054 May 07 03:29:49 PM PDT 24 May 07 03:30:10 PM PDT 24 349863598 ps
T312 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1936480400 May 07 03:30:26 PM PDT 24 May 07 03:30:57 PM PDT 24 6044474275 ps
T313 /workspace/coverage/default/8.rom_ctrl_alert_test.2193132831 May 07 03:29:45 PM PDT 24 May 07 03:29:54 PM PDT 24 170831459 ps
T314 /workspace/coverage/default/39.rom_ctrl_smoke.2748464143 May 07 03:31:05 PM PDT 24 May 07 03:31:25 PM PDT 24 1545714952 ps
T315 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.377726973 May 07 03:30:58 PM PDT 24 May 07 03:45:36 PM PDT 24 88623404972 ps
T316 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2965137222 May 07 03:29:59 PM PDT 24 May 07 03:30:32 PM PDT 24 21310988985 ps
T317 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.959619060 May 07 03:29:49 PM PDT 24 May 07 03:30:15 PM PDT 24 2362718073 ps
T318 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3921903217 May 07 03:30:58 PM PDT 24 May 07 03:31:41 PM PDT 24 3759672245 ps
T319 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2080684634 May 07 03:29:24 PM PDT 24 May 07 03:29:44 PM PDT 24 704201905 ps
T320 /workspace/coverage/default/31.rom_ctrl_stress_all.263245813 May 07 03:30:44 PM PDT 24 May 07 03:31:53 PM PDT 24 22434299674 ps
T321 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.790319093 May 07 03:29:32 PM PDT 24 May 07 03:30:04 PM PDT 24 7567932606 ps
T322 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1407631540 May 07 03:30:51 PM PDT 24 May 07 03:38:37 PM PDT 24 147702258789 ps
T323 /workspace/coverage/default/37.rom_ctrl_alert_test.1367922887 May 07 03:31:05 PM PDT 24 May 07 03:31:20 PM PDT 24 1481648031 ps
T324 /workspace/coverage/default/37.rom_ctrl_stress_all.4174965538 May 07 03:30:58 PM PDT 24 May 07 03:32:12 PM PDT 24 64364910848 ps
T325 /workspace/coverage/default/34.rom_ctrl_alert_test.2011238618 May 07 03:30:52 PM PDT 24 May 07 03:31:09 PM PDT 24 1351246070 ps
T326 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1247716495 May 07 03:29:58 PM PDT 24 May 07 03:30:59 PM PDT 24 27644080342 ps
T327 /workspace/coverage/default/38.rom_ctrl_smoke.971718155 May 07 03:31:04 PM PDT 24 May 07 03:31:48 PM PDT 24 17859850514 ps
T328 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.68066890 May 07 03:31:26 PM PDT 24 May 07 03:33:17 PM PDT 24 1257182972 ps
T329 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2990202469 May 07 03:30:26 PM PDT 24 May 07 03:30:43 PM PDT 24 1874243304 ps
T330 /workspace/coverage/default/0.rom_ctrl_smoke.86103929 May 07 03:29:22 PM PDT 24 May 07 03:30:19 PM PDT 24 22553882610 ps
T331 /workspace/coverage/default/1.rom_ctrl_alert_test.2128440509 May 07 03:29:25 PM PDT 24 May 07 03:29:40 PM PDT 24 852371059 ps
T332 /workspace/coverage/default/6.rom_ctrl_stress_all.2392213755 May 07 03:29:38 PM PDT 24 May 07 03:29:56 PM PDT 24 6101815390 ps
T333 /workspace/coverage/default/34.rom_ctrl_stress_all.1438460727 May 07 03:30:51 PM PDT 24 May 07 03:31:44 PM PDT 24 865913884 ps
T334 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4216502855 May 07 03:30:13 PM PDT 24 May 07 03:36:38 PM PDT 24 49608983310 ps
T335 /workspace/coverage/default/21.rom_ctrl_alert_test.733410258 May 07 03:30:18 PM PDT 24 May 07 03:30:28 PM PDT 24 338831086 ps
T336 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.637380011 May 07 03:29:54 PM PDT 24 May 07 03:34:23 PM PDT 24 15154676793 ps
T337 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3277739932 May 07 03:31:28 PM PDT 24 May 07 03:36:55 PM PDT 24 129375791748 ps
T338 /workspace/coverage/default/24.rom_ctrl_alert_test.155458202 May 07 03:30:28 PM PDT 24 May 07 03:30:57 PM PDT 24 3359818324 ps
T339 /workspace/coverage/default/44.rom_ctrl_alert_test.983422230 May 07 03:31:23 PM PDT 24 May 07 03:31:55 PM PDT 24 16608372367 ps
T340 /workspace/coverage/default/22.rom_ctrl_alert_test.2418602885 May 07 03:30:18 PM PDT 24 May 07 03:30:48 PM PDT 24 3815381703 ps
T341 /workspace/coverage/default/49.rom_ctrl_stress_all.1295331059 May 07 03:31:31 PM PDT 24 May 07 03:32:09 PM PDT 24 6549809918 ps
T342 /workspace/coverage/default/24.rom_ctrl_smoke.2135633848 May 07 03:30:25 PM PDT 24 May 07 03:30:52 PM PDT 24 3489508556 ps
T343 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.288799213 May 07 03:31:19 PM PDT 24 May 07 03:37:26 PM PDT 24 26072866865 ps
T344 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2301274269 May 07 03:31:11 PM PDT 24 May 07 03:31:30 PM PDT 24 1268434644 ps
T345 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3905858693 May 07 03:31:29 PM PDT 24 May 07 03:32:04 PM PDT 24 11620591948 ps
T346 /workspace/coverage/default/48.rom_ctrl_alert_test.2039565206 May 07 03:31:30 PM PDT 24 May 07 03:32:01 PM PDT 24 27190029694 ps
T347 /workspace/coverage/default/29.rom_ctrl_smoke.4006885501 May 07 03:30:36 PM PDT 24 May 07 03:31:41 PM PDT 24 61201368794 ps
T348 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3040265412 May 07 03:30:33 PM PDT 24 May 07 03:30:52 PM PDT 24 3957026845 ps
T349 /workspace/coverage/default/5.rom_ctrl_stress_all.786287172 May 07 03:29:40 PM PDT 24 May 07 03:33:29 PM PDT 24 23034384426 ps
T350 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1849189941 May 07 03:29:40 PM PDT 24 May 07 03:30:09 PM PDT 24 1386173288 ps
T351 /workspace/coverage/default/39.rom_ctrl_alert_test.1982218385 May 07 03:31:10 PM PDT 24 May 07 03:31:20 PM PDT 24 345555778 ps
T352 /workspace/coverage/default/35.rom_ctrl_smoke.2656392241 May 07 03:30:50 PM PDT 24 May 07 03:31:11 PM PDT 24 754531996 ps
T53 /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1915411070 May 07 03:30:18 PM PDT 24 May 07 03:55:59 PM PDT 24 154766977854 ps
T353 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2470472679 May 07 03:29:27 PM PDT 24 May 07 03:29:49 PM PDT 24 1825064398 ps
T354 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.507797176 May 07 03:31:20 PM PDT 24 May 07 03:38:00 PM PDT 24 182609541553 ps
T355 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1792583001 May 07 03:29:49 PM PDT 24 May 07 03:30:26 PM PDT 24 2638833216 ps
T356 /workspace/coverage/default/7.rom_ctrl_stress_all.3391941871 May 07 03:29:40 PM PDT 24 May 07 03:31:06 PM PDT 24 5837048346 ps
T357 /workspace/coverage/default/21.rom_ctrl_stress_all.912797369 May 07 03:30:33 PM PDT 24 May 07 03:30:45 PM PDT 24 412226791 ps
T358 /workspace/coverage/default/40.rom_ctrl_smoke.3368612867 May 07 03:31:08 PM PDT 24 May 07 03:32:00 PM PDT 24 17780061727 ps
T359 /workspace/coverage/default/3.rom_ctrl_alert_test.2790405363 May 07 03:29:32 PM PDT 24 May 07 03:30:01 PM PDT 24 3396380448 ps
T360 /workspace/coverage/default/26.rom_ctrl_alert_test.1664941949 May 07 03:30:33 PM PDT 24 May 07 03:30:50 PM PDT 24 4111815245 ps
T361 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3364101866 May 07 03:31:26 PM PDT 24 May 07 03:32:16 PM PDT 24 5233823049 ps
T362 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1558437968 May 07 03:30:27 PM PDT 24 May 07 03:30:58 PM PDT 24 7706679434 ps
T363 /workspace/coverage/default/15.rom_ctrl_stress_all.2077637207 May 07 03:29:59 PM PDT 24 May 07 03:30:54 PM PDT 24 5999415883 ps
T364 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1740850779 May 07 03:30:54 PM PDT 24 May 07 03:31:16 PM PDT 24 3783270454 ps
T365 /workspace/coverage/default/21.rom_ctrl_smoke.2022425484 May 07 03:30:11 PM PDT 24 May 07 03:30:45 PM PDT 24 5323993742 ps
T366 /workspace/coverage/default/45.rom_ctrl_smoke.817137888 May 07 03:31:26 PM PDT 24 May 07 03:32:36 PM PDT 24 7056230812 ps
T54 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2201116988 May 07 03:09:11 PM PDT 24 May 07 03:09:41 PM PDT 24 13773695317 ps
T65 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3240183094 May 07 03:09:27 PM PDT 24 May 07 03:09:38 PM PDT 24 688573334 ps
T66 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1557581470 May 07 03:09:18 PM PDT 24 May 07 03:09:28 PM PDT 24 168996484 ps
T69 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1194394913 May 07 03:09:12 PM PDT 24 May 07 03:09:28 PM PDT 24 2009020369 ps
T70 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1619840916 May 07 03:09:09 PM PDT 24 May 07 03:10:05 PM PDT 24 3308815197 ps
T114 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.818794704 May 07 03:09:03 PM PDT 24 May 07 03:09:23 PM PDT 24 3416029403 ps
T71 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.305723503 May 07 03:09:01 PM PDT 24 May 07 03:09:19 PM PDT 24 5212789118 ps
T72 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4192050769 May 07 03:09:17 PM PDT 24 May 07 03:09:33 PM PDT 24 1020802691 ps
T108 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1675659203 May 07 03:09:04 PM PDT 24 May 07 03:12:27 PM PDT 24 104592636302 ps
T73 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2312201395 May 07 03:09:06 PM PDT 24 May 07 03:09:19 PM PDT 24 699467310 ps
T367 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3558352008 May 07 03:09:12 PM PDT 24 May 07 03:09:31 PM PDT 24 1677186938 ps
T109 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3843991741 May 07 03:09:15 PM PDT 24 May 07 03:09:47 PM PDT 24 7073673058 ps
T55 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3576636111 May 07 03:09:22 PM PDT 24 May 07 03:09:51 PM PDT 24 2434763540 ps
T368 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.823106703 May 07 03:09:04 PM PDT 24 May 07 03:09:28 PM PDT 24 4781367064 ps
T74 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4211106535 May 07 03:09:19 PM PDT 24 May 07 03:10:12 PM PDT 24 2019126064 ps
T369 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2410572099 May 07 03:09:20 PM PDT 24 May 07 03:09:49 PM PDT 24 3550423784 ps
T370 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1579507554 May 07 03:09:21 PM PDT 24 May 07 03:09:31 PM PDT 24 180187335 ps
T110 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.133394692 May 07 03:09:19 PM PDT 24 May 07 03:10:39 PM PDT 24 28917710862 ps
T75 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2952920665 May 07 03:09:02 PM PDT 24 May 07 03:09:11 PM PDT 24 174335964 ps
T76 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2654218479 May 07 03:09:15 PM PDT 24 May 07 03:10:13 PM PDT 24 2057424388 ps
T61 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.644591912 May 07 03:09:24 PM PDT 24 May 07 03:11:02 PM PDT 24 6855212638 ps
T62 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.174561164 May 07 03:09:15 PM PDT 24 May 07 03:10:38 PM PDT 24 929937483 ps
T371 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1644567547 May 07 03:09:09 PM PDT 24 May 07 03:09:21 PM PDT 24 1171381134 ps
T372 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.648894876 May 07 03:09:10 PM PDT 24 May 07 03:09:34 PM PDT 24 2553609415 ps
T77 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1344059950 May 07 03:09:14 PM PDT 24 May 07 03:09:44 PM PDT 24 15402852665 ps
T63 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.540731405 May 07 03:09:10 PM PDT 24 May 07 03:10:33 PM PDT 24 540427633 ps
T373 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1065550362 May 07 03:09:19 PM PDT 24 May 07 03:09:32 PM PDT 24 174361757 ps
T374 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2647324918 May 07 03:09:16 PM PDT 24 May 07 03:09:40 PM PDT 24 2407839926 ps
T375 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3168682197 May 07 03:09:28 PM PDT 24 May 07 03:09:57 PM PDT 24 21592299282 ps
T376 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.144894791 May 07 03:09:03 PM PDT 24 May 07 03:09:32 PM PDT 24 3372379365 ps
T377 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3116889175 May 07 03:09:17 PM PDT 24 May 07 03:09:41 PM PDT 24 2031648685 ps
T378 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2860511978 May 07 03:09:20 PM PDT 24 May 07 03:09:57 PM PDT 24 8447028799 ps
T379 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1305872221 May 07 03:09:02 PM PDT 24 May 07 03:09:25 PM PDT 24 6149740348 ps
T111 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3517000354 May 07 03:08:57 PM PDT 24 May 07 03:11:00 PM PDT 24 43391209078 ps
T380 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2754659416 May 07 03:09:12 PM PDT 24 May 07 03:09:47 PM PDT 24 17190387566 ps
T381 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.649345437 May 07 03:09:17 PM PDT 24 May 07 03:09:41 PM PDT 24 34459413985 ps
T382 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.637967736 May 07 03:09:10 PM PDT 24 May 07 03:09:40 PM PDT 24 2862768269 ps
T78 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3080272589 May 07 03:09:09 PM PDT 24 May 07 03:09:18 PM PDT 24 332108131 ps
T383 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.10861387 May 07 03:09:01 PM PDT 24 May 07 03:09:26 PM PDT 24 10671175993 ps
T384 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3452538058 May 07 03:09:06 PM PDT 24 May 07 03:09:24 PM PDT 24 6862948027 ps
T112 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.488133876 May 07 03:09:15 PM PDT 24 May 07 03:09:46 PM PDT 24 6822179281 ps
T385 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1259046969 May 07 03:09:19 PM PDT 24 May 07 03:09:32 PM PDT 24 1975661584 ps
T386 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1945729634 May 07 03:09:04 PM PDT 24 May 07 03:09:13 PM PDT 24 1647946186 ps
T83 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2535857131 May 07 03:09:24 PM PDT 24 May 07 03:09:45 PM PDT 24 1813973688 ps
T387 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1211056199 May 07 03:09:16 PM PDT 24 May 07 03:09:26 PM PDT 24 1203430549 ps
T125 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.509690802 May 07 03:09:14 PM PDT 24 May 07 03:10:43 PM PDT 24 2450783047 ps
T84 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1720095462 May 07 03:09:00 PM PDT 24 May 07 03:09:21 PM PDT 24 2090448905 ps
T85 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2229686945 May 07 03:09:14 PM PDT 24 May 07 03:09:40 PM PDT 24 3110719270 ps
T388 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3183602218 May 07 03:09:03 PM PDT 24 May 07 03:09:35 PM PDT 24 35805470037 ps
T113 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3407752924 May 07 03:09:24 PM PDT 24 May 07 03:09:54 PM PDT 24 3801332141 ps
T389 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1575194204 May 07 03:09:02 PM PDT 24 May 07 03:09:59 PM PDT 24 1079455919 ps
T390 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1211103278 May 07 03:09:18 PM PDT 24 May 07 03:09:48 PM PDT 24 3680074239 ps
T391 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.416457224 May 07 03:09:22 PM PDT 24 May 07 03:09:53 PM PDT 24 15706162904 ps
T392 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2920253159 May 07 03:09:16 PM PDT 24 May 07 03:09:46 PM PDT 24 7827929390 ps
T393 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1285150272 May 07 03:09:15 PM PDT 24 May 07 03:09:27 PM PDT 24 1311607394 ps
T126 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2977657516 May 07 03:09:22 PM PDT 24 May 07 03:12:18 PM PDT 24 8309615289 ps
T394 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3275487987 May 07 03:09:15 PM PDT 24 May 07 03:09:24 PM PDT 24 661946145 ps
T395 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3275329941 May 07 03:09:14 PM PDT 24 May 07 03:09:31 PM PDT 24 2052367459 ps
T86 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1733092567 May 07 03:09:10 PM PDT 24 May 07 03:10:26 PM PDT 24 12513556590 ps
T396 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3883839432 May 07 03:09:09 PM PDT 24 May 07 03:09:27 PM PDT 24 1680749022 ps
T397 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1980230961 May 07 03:09:02 PM PDT 24 May 07 03:09:24 PM PDT 24 4368531149 ps
T121 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3638798912 May 07 03:09:20 PM PDT 24 May 07 03:10:40 PM PDT 24 812421087 ps
T116 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2813455248 May 07 03:09:13 PM PDT 24 May 07 03:12:01 PM PDT 24 14027528954 ps
T87 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.359727394 May 07 03:09:09 PM PDT 24 May 07 03:10:16 PM PDT 24 1556287159 ps
T398 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1777041684 May 07 03:09:01 PM PDT 24 May 07 03:09:20 PM PDT 24 5793740270 ps
T122 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1298972784 May 07 03:09:17 PM PDT 24 May 07 03:10:37 PM PDT 24 478845189 ps
T399 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2077894934 May 07 03:09:00 PM PDT 24 May 07 03:09:30 PM PDT 24 7659008693 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1688885235 May 07 03:09:16 PM PDT 24 May 07 03:09:26 PM PDT 24 3295343541 ps
T401 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3694241410 May 07 03:09:12 PM PDT 24 May 07 03:09:22 PM PDT 24 714597855 ps
T402 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1403203799 May 07 03:09:26 PM PDT 24 May 07 03:09:58 PM PDT 24 7150913579 ps
T403 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3422929879 May 07 03:09:16 PM PDT 24 May 07 03:09:42 PM PDT 24 2082102573 ps
T404 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3164201228 May 07 03:09:17 PM PDT 24 May 07 03:09:48 PM PDT 24 14850883369 ps
T405 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1951264109 May 07 03:09:16 PM PDT 24 May 07 03:09:38 PM PDT 24 1294960355 ps
T88 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2090995564 May 07 03:09:14 PM PDT 24 May 07 03:10:10 PM PDT 24 6059055843 ps
T130 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2772711784 May 07 03:09:26 PM PDT 24 May 07 03:11:03 PM PDT 24 4766920766 ps
T406 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.35650146 May 07 03:09:05 PM PDT 24 May 07 03:09:35 PM PDT 24 14422169977 ps
T407 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3024324499 May 07 03:09:21 PM PDT 24 May 07 03:09:37 PM PDT 24 1067490675 ps
T408 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3395099269 May 07 03:09:18 PM PDT 24 May 07 03:09:50 PM PDT 24 4240491327 ps
T409 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4004595940 May 07 03:09:17 PM PDT 24 May 07 03:09:31 PM PDT 24 172605461 ps
T410 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4098460744 May 07 03:09:16 PM PDT 24 May 07 03:09:51 PM PDT 24 7209118527 ps
T411 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.321113383 May 07 03:09:17 PM PDT 24 May 07 03:09:27 PM PDT 24 169055161 ps
T118 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1193459020 May 07 03:09:05 PM PDT 24 May 07 03:10:31 PM PDT 24 714672052 ps
T412 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1253272864 May 07 03:08:59 PM PDT 24 May 07 03:09:11 PM PDT 24 346180473 ps
T119 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1371327261 May 07 03:09:04 PM PDT 24 May 07 03:11:39 PM PDT 24 418351849 ps
T413 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1043968448 May 07 03:09:20 PM PDT 24 May 07 03:09:54 PM PDT 24 17159284395 ps
T414 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1027025803 May 07 03:09:15 PM PDT 24 May 07 03:09:39 PM PDT 24 2144137191 ps
T90 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2745108464 May 07 03:09:14 PM PDT 24 May 07 03:10:51 PM PDT 24 45736757865 ps
T415 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1270273969 May 07 03:09:16 PM PDT 24 May 07 03:11:26 PM PDT 24 65576288250 ps
T120 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.401583502 May 07 03:09:03 PM PDT 24 May 07 03:11:58 PM PDT 24 21115957261 ps
T416 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3461207839 May 07 03:09:26 PM PDT 24 May 07 03:09:41 PM PDT 24 2624601970 ps
T117 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2843050484 May 07 03:09:05 PM PDT 24 May 07 03:10:29 PM PDT 24 286959342 ps
T417 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2510790170 May 07 03:09:23 PM PDT 24 May 07 03:09:55 PM PDT 24 7675121694 ps
T418 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.317451960 May 07 03:09:12 PM PDT 24 May 07 03:09:27 PM PDT 24 595264743 ps
T419 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1624776732 May 07 03:09:22 PM PDT 24 May 07 03:09:50 PM PDT 24 3045325326 ps
T420 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1429283663 May 07 03:09:19 PM PDT 24 May 07 03:09:43 PM PDT 24 2475249814 ps
T421 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1653717883 May 07 03:09:15 PM PDT 24 May 07 03:09:35 PM PDT 24 2062720046 ps
T422 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2498120069 May 07 03:09:27 PM PDT 24 May 07 03:10:00 PM PDT 24 3041922563 ps
T423 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3009278738 May 07 03:09:16 PM PDT 24 May 07 03:09:28 PM PDT 24 185764384 ps
T424 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3225647395 May 07 03:09:15 PM PDT 24 May 07 03:09:48 PM PDT 24 3235532883 ps
T425 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1737210176 May 07 03:09:02 PM PDT 24 May 07 03:09:12 PM PDT 24 174373243 ps
T426 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2858275179 May 07 03:09:17 PM PDT 24 May 07 03:10:44 PM PDT 24 47392142831 ps
T427 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2668337326 May 07 03:09:21 PM PDT 24 May 07 03:09:34 PM PDT 24 4580846063 ps
T123 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1772166228 May 07 03:09:17 PM PDT 24 May 07 03:12:13 PM PDT 24 16251817165 ps
T428 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1980714520 May 07 03:09:16 PM PDT 24 May 07 03:09:29 PM PDT 24 913235330 ps
T429 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.883415841 May 07 03:09:21 PM PDT 24 May 07 03:09:44 PM PDT 24 8621685140 ps
T129 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.198394189 May 07 03:09:24 PM PDT 24 May 07 03:11:08 PM PDT 24 8051821905 ps
T430 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2389673133 May 07 03:09:16 PM PDT 24 May 07 03:10:44 PM PDT 24 15794018977 ps
T89 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3029134641 May 07 03:09:03 PM PDT 24 May 07 03:09:27 PM PDT 24 10623910059 ps
T431 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4026146595 May 07 03:09:20 PM PDT 24 May 07 03:09:33 PM PDT 24 1679251991 ps
T432 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.500514491 May 07 03:09:06 PM PDT 24 May 07 03:09:27 PM PDT 24 7853353705 ps
T433 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1835893870 May 07 03:09:03 PM PDT 24 May 07 03:09:28 PM PDT 24 3225472822 ps
T434 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.722232800 May 07 03:09:03 PM PDT 24 May 07 03:09:13 PM PDT 24 969642741 ps
T91 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.870727088 May 07 03:09:17 PM PDT 24 May 07 03:12:24 PM PDT 24 23490464246 ps
T94 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.417835343 May 07 03:09:14 PM PDT 24 May 07 03:09:23 PM PDT 24 634926298 ps
T92 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.418763634 May 07 03:09:27 PM PDT 24 May 07 03:11:41 PM PDT 24 16081092414 ps
T435 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2169324037 May 07 03:09:14 PM PDT 24 May 07 03:09:23 PM PDT 24 613977922 ps
T436 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3600687557 May 07 03:09:04 PM PDT 24 May 07 03:09:39 PM PDT 24 4041827652 ps
T437 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2856549507 May 07 03:09:06 PM PDT 24 May 07 03:09:37 PM PDT 24 3266564729 ps
T438 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1307411705 May 07 03:09:02 PM PDT 24 May 07 03:09:16 PM PDT 24 3679764783 ps
T439 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2696408862 May 07 03:09:18 PM PDT 24 May 07 03:09:43 PM PDT 24 11968311909 ps
T440 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3969693106 May 07 03:09:18 PM PDT 24 May 07 03:09:38 PM PDT 24 1190749996 ps
T124 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1500863315 May 07 03:09:11 PM PDT 24 May 07 03:10:53 PM PDT 24 41157628608 ps
T441 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.510630218 May 07 03:09:07 PM PDT 24 May 07 03:09:36 PM PDT 24 13858365383 ps
T95 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2348946831 May 07 03:09:18 PM PDT 24 May 07 03:10:40 PM PDT 24 6893347536 ps
T93 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1160498061 May 07 03:09:15 PM PDT 24 May 07 03:11:26 PM PDT 24 128248900060 ps
T442 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.235448990 May 07 03:09:18 PM PDT 24 May 07 03:10:42 PM PDT 24 5502160529 ps
T443 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2013837302 May 07 03:09:10 PM PDT 24 May 07 03:09:37 PM PDT 24 17364471593 ps
T444 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4213727834 May 07 03:09:07 PM PDT 24 May 07 03:09:30 PM PDT 24 9196931455 ps
T127 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3177028690 May 07 03:09:19 PM PDT 24 May 07 03:11:53 PM PDT 24 2510704550 ps
T445 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2263611101 May 07 03:09:16 PM PDT 24 May 07 03:09:29 PM PDT 24 493754648 ps
T128 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3759355371 May 07 03:09:26 PM PDT 24 May 07 03:12:24 PM PDT 24 8079846603 ps
T446 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1059730591 May 07 03:09:16 PM PDT 24 May 07 03:09:48 PM PDT 24 18959550617 ps
T447 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.943816379 May 07 03:09:18 PM PDT 24 May 07 03:09:43 PM PDT 24 10192853233 ps
T448 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2309118022 May 07 03:09:03 PM PDT 24 May 07 03:09:24 PM PDT 24 7841196705 ps
T449 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.464937709 May 07 03:09:16 PM PDT 24 May 07 03:11:50 PM PDT 24 913532126 ps
T96 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3498548754 May 07 03:09:25 PM PDT 24 May 07 03:12:05 PM PDT 24 63929604124 ps
T450 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2090616965 May 07 03:09:27 PM PDT 24 May 07 03:09:50 PM PDT 24 2064765334 ps
T451 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.336752659 May 07 03:09:10 PM PDT 24 May 07 03:09:31 PM PDT 24 1913413625 ps
T452 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3264736283 May 07 03:09:01 PM PDT 24 May 07 03:09:14 PM PDT 24 436002413 ps
T453 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.512757743 May 07 03:09:27 PM PDT 24 May 07 03:09:56 PM PDT 24 3093096313 ps
T454 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.498053805 May 07 03:09:12 PM PDT 24 May 07 03:10:18 PM PDT 24 6081469395 ps
T97 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2423092048 May 07 03:09:04 PM PDT 24 May 07 03:09:36 PM PDT 24 15786252279 ps
T455 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1808818097 May 07 03:09:18 PM PDT 24 May 07 03:09:31 PM PDT 24 661837561 ps
T456 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1592089584 May 07 03:09:17 PM PDT 24 May 07 03:09:45 PM PDT 24 2484784048 ps
T457 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1694367916 May 07 03:09:12 PM PDT 24 May 07 03:09:28 PM PDT 24 6014995931 ps

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1788919742
Short name T3
Test name
Test status
Simulation time 21165625263 ps
CPU time 185.89 seconds
Started May 07 03:29:47 PM PDT 24
Finished May 07 03:32:54 PM PDT 24
Peak memory 222580 kb
Host smart-0f824cc7-c119-449e-b769-4fdf7dcf0d2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788919742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1788919742
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3065903797
Short name T13
Test name
Test status
Simulation time 30735083810 ps
CPU time 1196.12 seconds
Started May 07 03:29:54 PM PDT 24
Finished May 07 03:49:51 PM PDT 24
Peak memory 234508 kb
Host smart-ba527f54-6462-4455-9119-50b5d42bdd4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065903797 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.3065903797
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3935473599
Short name T23
Test name
Test status
Simulation time 59826712088 ps
CPU time 734.23 seconds
Started May 07 03:30:59 PM PDT 24
Finished May 07 03:43:14 PM PDT 24
Peak memory 238804 kb
Host smart-1d3dc5fe-45eb-46b6-a75b-a0bc72aa05d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935473599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3935473599
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2977657516
Short name T126
Test name
Test status
Simulation time 8309615289 ps
CPU time 174.66 seconds
Started May 07 03:09:22 PM PDT 24
Finished May 07 03:12:18 PM PDT 24
Peak memory 214696 kb
Host smart-f57b47b9-766e-4555-a299-68f59aba06c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977657516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2977657516
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2389276483
Short name T30
Test name
Test status
Simulation time 14737395425 ps
CPU time 247.17 seconds
Started May 07 03:29:31 PM PDT 24
Finished May 07 03:33:40 PM PDT 24
Peak memory 237348 kb
Host smart-0824739d-7ab7-4124-9481-6bd27969ce7f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389276483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2389276483
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.790319291
Short name T57
Test name
Test status
Simulation time 34485830706 ps
CPU time 93.92 seconds
Started May 07 03:29:45 PM PDT 24
Finished May 07 03:31:20 PM PDT 24
Peak memory 218312 kb
Host smart-e9e2eb83-cca0-4e33-8dbd-d74fa3e9fc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790319291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.790319291
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1772166228
Short name T123
Test name
Test status
Simulation time 16251817165 ps
CPU time 174.63 seconds
Started May 07 03:09:17 PM PDT 24
Finished May 07 03:12:13 PM PDT 24
Peak memory 218868 kb
Host smart-2f0d398d-7548-48ec-ac0b-14f84cb9f4a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772166228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1772166228
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1619840916
Short name T70
Test name
Test status
Simulation time 3308815197 ps
CPU time 55.01 seconds
Started May 07 03:09:09 PM PDT 24
Finished May 07 03:10:05 PM PDT 24
Peak memory 212680 kb
Host smart-3f1dbf82-a0dc-4176-90c7-f17b8b28e2ff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619840916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1619840916
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.17444111
Short name T6
Test name
Test status
Simulation time 174455121 ps
CPU time 8.33 seconds
Started May 07 03:31:19 PM PDT 24
Finished May 07 03:31:28 PM PDT 24
Peak memory 211824 kb
Host smart-df04e0c2-f195-46bf-9efb-c538b30b7f34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17444111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.17444111
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1948465322
Short name T20
Test name
Test status
Simulation time 5312154960 ps
CPU time 51.13 seconds
Started May 07 03:29:52 PM PDT 24
Finished May 07 03:30:43 PM PDT 24
Peak memory 215680 kb
Host smart-dfe15e52-2c33-4491-9670-283152c6a937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948465322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1948465322
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3070505330
Short name T18
Test name
Test status
Simulation time 335313261 ps
CPU time 19.36 seconds
Started May 07 03:29:27 PM PDT 24
Finished May 07 03:29:47 PM PDT 24
Peak memory 215216 kb
Host smart-2e50168f-4c8c-4272-8ee4-868833999528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070505330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3070505330
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1193459020
Short name T118
Test name
Test status
Simulation time 714672052 ps
CPU time 84.47 seconds
Started May 07 03:09:05 PM PDT 24
Finished May 07 03:10:31 PM PDT 24
Peak memory 212644 kb
Host smart-d6bf98a2-34cd-4de3-9707-33071ac8c782
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193459020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1193459020
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1733092567
Short name T86
Test name
Test status
Simulation time 12513556590 ps
CPU time 74.94 seconds
Started May 07 03:09:10 PM PDT 24
Finished May 07 03:10:26 PM PDT 24
Peak memory 213748 kb
Host smart-7694fecb-6e19-4e16-afe1-c578ae8ac03e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733092567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1733092567
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.174561164
Short name T62
Test name
Test status
Simulation time 929937483 ps
CPU time 81.59 seconds
Started May 07 03:09:15 PM PDT 24
Finished May 07 03:10:38 PM PDT 24
Peak memory 212912 kb
Host smart-dbd4656e-e196-4a77-a07a-066c61a27798
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174561164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.174561164
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3664391088
Short name T98
Test name
Test status
Simulation time 45422885193 ps
CPU time 32.01 seconds
Started May 07 03:30:47 PM PDT 24
Finished May 07 03:31:20 PM PDT 24
Peak memory 212364 kb
Host smart-76cba8d9-314e-4adc-b076-5c6dbc076dfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3664391088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3664391088
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.305723503
Short name T71
Test name
Test status
Simulation time 5212789118 ps
CPU time 16.86 seconds
Started May 07 03:09:01 PM PDT 24
Finished May 07 03:09:19 PM PDT 24
Peak memory 210656 kb
Host smart-0aad7e2f-0b40-4cb6-90ef-7e040a7671de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305723503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.305723503
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.722232800
Short name T434
Test name
Test status
Simulation time 969642741 ps
CPU time 8.59 seconds
Started May 07 03:09:03 PM PDT 24
Finished May 07 03:09:13 PM PDT 24
Peak memory 210564 kb
Host smart-21d4ec43-92d2-4b72-b7ad-9aa412f75077
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722232800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.722232800
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2312201395
Short name T73
Test name
Test status
Simulation time 699467310 ps
CPU time 11.78 seconds
Started May 07 03:09:06 PM PDT 24
Finished May 07 03:09:19 PM PDT 24
Peak memory 211104 kb
Host smart-5561630c-bf0b-4340-8df3-5f94b709c471
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312201395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2312201395
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4213727834
Short name T444
Test name
Test status
Simulation time 9196931455 ps
CPU time 22.18 seconds
Started May 07 03:09:07 PM PDT 24
Finished May 07 03:09:30 PM PDT 24
Peak memory 218768 kb
Host smart-2f58c5f5-3a4a-4312-9ccf-27827b5236e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213727834 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.4213727834
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1720095462
Short name T84
Test name
Test status
Simulation time 2090448905 ps
CPU time 20.12 seconds
Started May 07 03:09:00 PM PDT 24
Finished May 07 03:09:21 PM PDT 24
Peak memory 211120 kb
Host smart-dccf252d-5ae0-4cd7-b793-a3c596b43555
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720095462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1720095462
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2309118022
Short name T448
Test name
Test status
Simulation time 7841196705 ps
CPU time 19.63 seconds
Started May 07 03:09:03 PM PDT 24
Finished May 07 03:09:24 PM PDT 24
Peak memory 210556 kb
Host smart-8869c897-7614-43ff-a0e3-a5f77f792b05
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309118022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2309118022
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2077894934
Short name T399
Test name
Test status
Simulation time 7659008693 ps
CPU time 29.6 seconds
Started May 07 03:09:00 PM PDT 24
Finished May 07 03:09:30 PM PDT 24
Peak memory 210556 kb
Host smart-b8fda3e2-ff0b-4423-a5f8-a0098df8d41b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077894934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2077894934
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3517000354
Short name T111
Test name
Test status
Simulation time 43391209078 ps
CPU time 122.23 seconds
Started May 07 03:08:57 PM PDT 24
Finished May 07 03:11:00 PM PDT 24
Peak memory 218868 kb
Host smart-c3c409cd-df66-4b73-9a09-57e3ea28fb2b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517000354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3517000354
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1737210176
Short name T425
Test name
Test status
Simulation time 174373243 ps
CPU time 8.45 seconds
Started May 07 03:09:02 PM PDT 24
Finished May 07 03:09:12 PM PDT 24
Peak memory 210484 kb
Host smart-53aa63e3-895c-4eb5-9bee-8ebb83725ab0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737210176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1737210176
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3264736283
Short name T452
Test name
Test status
Simulation time 436002413 ps
CPU time 11.83 seconds
Started May 07 03:09:01 PM PDT 24
Finished May 07 03:09:14 PM PDT 24
Peak memory 216676 kb
Host smart-5e195731-6293-46d8-8601-2dc1510385e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264736283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3264736283
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2843050484
Short name T117
Test name
Test status
Simulation time 286959342 ps
CPU time 83.03 seconds
Started May 07 03:09:05 PM PDT 24
Finished May 07 03:10:29 PM PDT 24
Peak memory 213132 kb
Host smart-fb1fca5c-836b-4921-a896-14a3f8460301
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843050484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2843050484
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2423092048
Short name T97
Test name
Test status
Simulation time 15786252279 ps
CPU time 30.95 seconds
Started May 07 03:09:04 PM PDT 24
Finished May 07 03:09:36 PM PDT 24
Peak memory 211748 kb
Host smart-56338448-9442-409b-aded-5721786a6494
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423092048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2423092048
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.818794704
Short name T114
Test name
Test status
Simulation time 3416029403 ps
CPU time 18.9 seconds
Started May 07 03:09:03 PM PDT 24
Finished May 07 03:09:23 PM PDT 24
Peak memory 210824 kb
Host smart-dc914271-f9e8-41fd-9178-0ad704b8473b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818794704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.818794704
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.823106703
Short name T368
Test name
Test status
Simulation time 4781367064 ps
CPU time 22.65 seconds
Started May 07 03:09:04 PM PDT 24
Finished May 07 03:09:28 PM PDT 24
Peak memory 211532 kb
Host smart-1419197a-8fa0-4a06-ac50-dd73ad4523d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823106703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.823106703
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1777041684
Short name T398
Test name
Test status
Simulation time 5793740270 ps
CPU time 18.24 seconds
Started May 07 03:09:01 PM PDT 24
Finished May 07 03:09:20 PM PDT 24
Peak memory 218900 kb
Host smart-e09ac967-01a7-4959-a407-e41a69a2f30d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777041684 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1777041684
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1945729634
Short name T386
Test name
Test status
Simulation time 1647946186 ps
CPU time 8.23 seconds
Started May 07 03:09:04 PM PDT 24
Finished May 07 03:09:13 PM PDT 24
Peak memory 210532 kb
Host smart-ff1a14d8-fe03-47de-85f1-18068d8a589b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945729634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1945729634
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.35650146
Short name T406
Test name
Test status
Simulation time 14422169977 ps
CPU time 29.68 seconds
Started May 07 03:09:05 PM PDT 24
Finished May 07 03:09:35 PM PDT 24
Peak memory 210468 kb
Host smart-a6146684-3823-4c47-922c-f634cd74224c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35650146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_
mem_partial_access.35650146
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.500514491
Short name T432
Test name
Test status
Simulation time 7853353705 ps
CPU time 19.95 seconds
Started May 07 03:09:06 PM PDT 24
Finished May 07 03:09:27 PM PDT 24
Peak memory 210600 kb
Host smart-f0a5de95-eaee-4c58-b9b0-aee8a49e1f72
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500514491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
500514491
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1575194204
Short name T389
Test name
Test status
Simulation time 1079455919 ps
CPU time 56.4 seconds
Started May 07 03:09:02 PM PDT 24
Finished May 07 03:09:59 PM PDT 24
Peak memory 214620 kb
Host smart-661b16e2-83f7-4ac1-a6cb-a339ff871779
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575194204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1575194204
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2952920665
Short name T75
Test name
Test status
Simulation time 174335964 ps
CPU time 8.61 seconds
Started May 07 03:09:02 PM PDT 24
Finished May 07 03:09:11 PM PDT 24
Peak memory 210740 kb
Host smart-27e278d2-97b0-4a98-8888-f5108187133f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952920665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2952920665
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1253272864
Short name T412
Test name
Test status
Simulation time 346180473 ps
CPU time 10.82 seconds
Started May 07 03:08:59 PM PDT 24
Finished May 07 03:09:11 PM PDT 24
Peak memory 215988 kb
Host smart-360fa117-02da-4fb2-b9ea-c7a4330789f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253272864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1253272864
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.401583502
Short name T120
Test name
Test status
Simulation time 21115957261 ps
CPU time 173.91 seconds
Started May 07 03:09:03 PM PDT 24
Finished May 07 03:11:58 PM PDT 24
Peak memory 213536 kb
Host smart-3fbfa0d8-675c-41e0-98ca-13947adcec17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401583502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.401583502
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2668337326
Short name T427
Test name
Test status
Simulation time 4580846063 ps
CPU time 12.3 seconds
Started May 07 03:09:21 PM PDT 24
Finished May 07 03:09:34 PM PDT 24
Peak memory 215204 kb
Host smart-39aa2090-a1f1-4eb7-9a83-4994dcb0bcc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668337326 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2668337326
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2229686945
Short name T85
Test name
Test status
Simulation time 3110719270 ps
CPU time 25.53 seconds
Started May 07 03:09:14 PM PDT 24
Finished May 07 03:09:40 PM PDT 24
Peak memory 210980 kb
Host smart-92763c1e-ba61-487f-92dc-bf488c8ba66e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229686945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2229686945
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1270273969
Short name T415
Test name
Test status
Simulation time 65576288250 ps
CPU time 128.08 seconds
Started May 07 03:09:16 PM PDT 24
Finished May 07 03:11:26 PM PDT 24
Peak memory 213848 kb
Host smart-b424dde7-f56e-4190-a3ab-c3f9a6f4e84e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270273969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1270273969
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.321113383
Short name T411
Test name
Test status
Simulation time 169055161 ps
CPU time 8.33 seconds
Started May 07 03:09:17 PM PDT 24
Finished May 07 03:09:27 PM PDT 24
Peak memory 210812 kb
Host smart-425197b0-1009-4bcc-94c6-f376d4c12385
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321113383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.321113383
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1059730591
Short name T446
Test name
Test status
Simulation time 18959550617 ps
CPU time 30.38 seconds
Started May 07 03:09:16 PM PDT 24
Finished May 07 03:09:48 PM PDT 24
Peak memory 218060 kb
Host smart-aab4c8bf-4a8f-450b-8490-43687d920560
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059730591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1059730591
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1429283663
Short name T420
Test name
Test status
Simulation time 2475249814 ps
CPU time 23.11 seconds
Started May 07 03:09:19 PM PDT 24
Finished May 07 03:09:43 PM PDT 24
Peak memory 218784 kb
Host smart-c1a7e1ef-1da1-4d3b-b4ca-88696ef32181
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429283663 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1429283663
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.512757743
Short name T453
Test name
Test status
Simulation time 3093096313 ps
CPU time 26.08 seconds
Started May 07 03:09:27 PM PDT 24
Finished May 07 03:09:56 PM PDT 24
Peak memory 210896 kb
Host smart-bfd1ea2f-1de7-4311-b9dd-4599306f2f96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512757743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.512757743
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2090995564
Short name T88
Test name
Test status
Simulation time 6059055843 ps
CPU time 55.44 seconds
Started May 07 03:09:14 PM PDT 24
Finished May 07 03:10:10 PM PDT 24
Peak memory 214796 kb
Host smart-e1fa862f-73c0-4d14-b897-4dfab307ab40
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090995564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2090995564
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4098460744
Short name T410
Test name
Test status
Simulation time 7209118527 ps
CPU time 33.3 seconds
Started May 07 03:09:16 PM PDT 24
Finished May 07 03:09:51 PM PDT 24
Peak memory 211980 kb
Host smart-3c4357ba-e74f-4ffe-a81f-2e7467c72f6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098460744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.4098460744
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1808818097
Short name T455
Test name
Test status
Simulation time 661837561 ps
CPU time 12.61 seconds
Started May 07 03:09:18 PM PDT 24
Finished May 07 03:09:31 PM PDT 24
Peak memory 218808 kb
Host smart-563d865b-5e54-413f-bd73-8017bab829b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808818097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1808818097
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2772711784
Short name T130
Test name
Test status
Simulation time 4766920766 ps
CPU time 93.23 seconds
Started May 07 03:09:26 PM PDT 24
Finished May 07 03:11:03 PM PDT 24
Peak memory 214184 kb
Host smart-e5dbda2a-78ea-4641-97d0-50ad994a25a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772711784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2772711784
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3395099269
Short name T408
Test name
Test status
Simulation time 4240491327 ps
CPU time 30.7 seconds
Started May 07 03:09:18 PM PDT 24
Finished May 07 03:09:50 PM PDT 24
Peak memory 216508 kb
Host smart-414c9c41-8712-4dc7-b79a-af4e35590836
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395099269 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3395099269
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1259046969
Short name T385
Test name
Test status
Simulation time 1975661584 ps
CPU time 11.37 seconds
Started May 07 03:09:19 PM PDT 24
Finished May 07 03:09:32 PM PDT 24
Peak memory 210488 kb
Host smart-90891b89-9f0a-43cd-9c54-18ad50254277
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259046969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1259046969
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.870727088
Short name T91
Test name
Test status
Simulation time 23490464246 ps
CPU time 185.9 seconds
Started May 07 03:09:17 PM PDT 24
Finished May 07 03:12:24 PM PDT 24
Peak memory 214128 kb
Host smart-455c0f4b-4cba-4aa9-a1e4-10ca48c9b14f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870727088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.870727088
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1624776732
Short name T419
Test name
Test status
Simulation time 3045325326 ps
CPU time 25.91 seconds
Started May 07 03:09:22 PM PDT 24
Finished May 07 03:09:50 PM PDT 24
Peak memory 211656 kb
Host smart-d0d7be30-03ea-4e09-99c4-bcbde484dcfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624776732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1624776732
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4004595940
Short name T409
Test name
Test status
Simulation time 172605461 ps
CPU time 12.52 seconds
Started May 07 03:09:17 PM PDT 24
Finished May 07 03:09:31 PM PDT 24
Peak memory 216764 kb
Host smart-7cfb9ca2-617f-4880-96d5-5352bda5167d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004595940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.4004595940
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1298972784
Short name T122
Test name
Test status
Simulation time 478845189 ps
CPU time 78.89 seconds
Started May 07 03:09:17 PM PDT 24
Finished May 07 03:10:37 PM PDT 24
Peak memory 212984 kb
Host smart-f99956c4-b23b-42bb-a630-97091d0d3e0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298972784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1298972784
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2920253159
Short name T392
Test name
Test status
Simulation time 7827929390 ps
CPU time 29.45 seconds
Started May 07 03:09:16 PM PDT 24
Finished May 07 03:09:46 PM PDT 24
Peak memory 215720 kb
Host smart-f083f176-a4cf-4d9f-ab7f-02733aa20e50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920253159 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2920253159
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3275487987
Short name T394
Test name
Test status
Simulation time 661946145 ps
CPU time 8.02 seconds
Started May 07 03:09:15 PM PDT 24
Finished May 07 03:09:24 PM PDT 24
Peak memory 210512 kb
Host smart-4bf76b5a-f013-4166-aa96-e12ed2d5a1ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275487987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3275487987
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2348946831
Short name T95
Test name
Test status
Simulation time 6893347536 ps
CPU time 80.5 seconds
Started May 07 03:09:18 PM PDT 24
Finished May 07 03:10:40 PM PDT 24
Peak memory 214028 kb
Host smart-6fb11603-34a3-4763-9d2a-ff7fe45f68d3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348946831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2348946831
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3225647395
Short name T424
Test name
Test status
Simulation time 3235532883 ps
CPU time 31.6 seconds
Started May 07 03:09:15 PM PDT 24
Finished May 07 03:09:48 PM PDT 24
Peak memory 211768 kb
Host smart-76d6b234-badc-454b-a57e-93a8a4f5bc92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225647395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3225647395
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3116889175
Short name T377
Test name
Test status
Simulation time 2031648685 ps
CPU time 22.76 seconds
Started May 07 03:09:17 PM PDT 24
Finished May 07 03:09:41 PM PDT 24
Peak memory 218808 kb
Host smart-9673d17b-eec2-43ef-abd9-66fedbc5ce9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116889175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3116889175
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.464937709
Short name T449
Test name
Test status
Simulation time 913532126 ps
CPU time 152.53 seconds
Started May 07 03:09:16 PM PDT 24
Finished May 07 03:11:50 PM PDT 24
Peak memory 218732 kb
Host smart-101c1268-0a1d-4883-b5bf-0071adc08113
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464937709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.464937709
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2410572099
Short name T369
Test name
Test status
Simulation time 3550423784 ps
CPU time 27.35 seconds
Started May 07 03:09:20 PM PDT 24
Finished May 07 03:09:49 PM PDT 24
Peak memory 218836 kb
Host smart-bfd31412-8702-4e9e-8c1f-2861e111a856
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410572099 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2410572099
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.417835343
Short name T94
Test name
Test status
Simulation time 634926298 ps
CPU time 7.92 seconds
Started May 07 03:09:14 PM PDT 24
Finished May 07 03:09:23 PM PDT 24
Peak memory 210488 kb
Host smart-907b8fe4-acb9-4d17-bc80-09059b12a501
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417835343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.417835343
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2389673133
Short name T430
Test name
Test status
Simulation time 15794018977 ps
CPU time 86.15 seconds
Started May 07 03:09:16 PM PDT 24
Finished May 07 03:10:44 PM PDT 24
Peak memory 213948 kb
Host smart-a82ad5f6-e457-46f9-b332-81fab0eb5e0a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389673133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2389673133
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1027025803
Short name T414
Test name
Test status
Simulation time 2144137191 ps
CPU time 23.76 seconds
Started May 07 03:09:15 PM PDT 24
Finished May 07 03:09:39 PM PDT 24
Peak memory 211436 kb
Host smart-ac7d9f50-48a2-4524-8621-9c4481d7c8d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027025803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1027025803
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.649345437
Short name T381
Test name
Test status
Simulation time 34459413985 ps
CPU time 22.15 seconds
Started May 07 03:09:17 PM PDT 24
Finished May 07 03:09:41 PM PDT 24
Peak memory 216708 kb
Host smart-819ddd0e-90f7-4ab8-b1bb-98645912509e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649345437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.649345437
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2813455248
Short name T116
Test name
Test status
Simulation time 14027528954 ps
CPU time 166.85 seconds
Started May 07 03:09:13 PM PDT 24
Finished May 07 03:12:01 PM PDT 24
Peak memory 218796 kb
Host smart-5711c540-018c-4f9b-9a56-3bd27ba23901
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813455248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2813455248
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1980714520
Short name T428
Test name
Test status
Simulation time 913235330 ps
CPU time 11.63 seconds
Started May 07 03:09:16 PM PDT 24
Finished May 07 03:09:29 PM PDT 24
Peak memory 213764 kb
Host smart-bbb046f5-bc7e-4bcf-a1f1-69244002cef8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980714520 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1980714520
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2647324918
Short name T374
Test name
Test status
Simulation time 2407839926 ps
CPU time 22.34 seconds
Started May 07 03:09:16 PM PDT 24
Finished May 07 03:09:40 PM PDT 24
Peak memory 211208 kb
Host smart-27c8e901-b7cd-4f55-a3c4-4ce1289f9914
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647324918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2647324918
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1160498061
Short name T93
Test name
Test status
Simulation time 128248900060 ps
CPU time 129.71 seconds
Started May 07 03:09:15 PM PDT 24
Finished May 07 03:11:26 PM PDT 24
Peak memory 213736 kb
Host smart-7491b05b-1ab9-4ae6-90ef-da87c7749bdc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160498061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1160498061
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2090616965
Short name T450
Test name
Test status
Simulation time 2064765334 ps
CPU time 20.76 seconds
Started May 07 03:09:27 PM PDT 24
Finished May 07 03:09:50 PM PDT 24
Peak memory 211356 kb
Host smart-e7c1e367-c9bb-4371-ac56-36e8c9d67626
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090616965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2090616965
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3969693106
Short name T440
Test name
Test status
Simulation time 1190749996 ps
CPU time 18.99 seconds
Started May 07 03:09:18 PM PDT 24
Finished May 07 03:09:38 PM PDT 24
Peak memory 218808 kb
Host smart-0309313e-1b21-440a-9332-169aa76aaf77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969693106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3969693106
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.235448990
Short name T442
Test name
Test status
Simulation time 5502160529 ps
CPU time 83.36 seconds
Started May 07 03:09:18 PM PDT 24
Finished May 07 03:10:42 PM PDT 24
Peak memory 213080 kb
Host smart-da10f95e-fd34-472d-a32f-528c1df502b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235448990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.235448990
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4026146595
Short name T431
Test name
Test status
Simulation time 1679251991 ps
CPU time 11.57 seconds
Started May 07 03:09:20 PM PDT 24
Finished May 07 03:09:33 PM PDT 24
Peak memory 214804 kb
Host smart-c2568c8e-02a8-45f1-b35b-84cd89d13afe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026146595 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.4026146595
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3240183094
Short name T65
Test name
Test status
Simulation time 688573334 ps
CPU time 8.09 seconds
Started May 07 03:09:27 PM PDT 24
Finished May 07 03:09:38 PM PDT 24
Peak memory 210460 kb
Host smart-ee27e5db-cb30-4455-81a3-9d5136434e33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240183094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3240183094
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2654218479
Short name T76
Test name
Test status
Simulation time 2057424388 ps
CPU time 56.15 seconds
Started May 07 03:09:15 PM PDT 24
Finished May 07 03:10:13 PM PDT 24
Peak memory 212768 kb
Host smart-fd56781a-75f4-4ecf-9833-2ab5e967017b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654218479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2654218479
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3164201228
Short name T404
Test name
Test status
Simulation time 14850883369 ps
CPU time 29.11 seconds
Started May 07 03:09:17 PM PDT 24
Finished May 07 03:09:48 PM PDT 24
Peak memory 211908 kb
Host smart-4099c87d-32c2-441a-8bcb-d20723da1aac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164201228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3164201228
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1592089584
Short name T456
Test name
Test status
Simulation time 2484784048 ps
CPU time 26.38 seconds
Started May 07 03:09:17 PM PDT 24
Finished May 07 03:09:45 PM PDT 24
Peak memory 217604 kb
Host smart-2671e24b-677c-47b8-b978-7873cb0d61e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592089584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1592089584
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2696408862
Short name T439
Test name
Test status
Simulation time 11968311909 ps
CPU time 24.52 seconds
Started May 07 03:09:18 PM PDT 24
Finished May 07 03:09:43 PM PDT 24
Peak memory 215496 kb
Host smart-e159ebbb-cb12-48c5-8f43-f48d690aa243
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696408862 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2696408862
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3024324499
Short name T407
Test name
Test status
Simulation time 1067490675 ps
CPU time 15.04 seconds
Started May 07 03:09:21 PM PDT 24
Finished May 07 03:09:37 PM PDT 24
Peak memory 210600 kb
Host smart-48ec1b4d-b4a0-4c23-a715-3c13be4b0645
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024324499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3024324499
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4211106535
Short name T74
Test name
Test status
Simulation time 2019126064 ps
CPU time 51.25 seconds
Started May 07 03:09:19 PM PDT 24
Finished May 07 03:10:12 PM PDT 24
Peak memory 212916 kb
Host smart-29c6248e-41fc-4a56-804c-1226142b6cfa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211106535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.4211106535
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4192050769
Short name T72
Test name
Test status
Simulation time 1020802691 ps
CPU time 14.92 seconds
Started May 07 03:09:17 PM PDT 24
Finished May 07 03:09:33 PM PDT 24
Peak memory 211680 kb
Host smart-636c2ee0-367e-4fe8-84d0-4164a8c47b4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192050769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.4192050769
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1065550362
Short name T373
Test name
Test status
Simulation time 174361757 ps
CPU time 12.25 seconds
Started May 07 03:09:19 PM PDT 24
Finished May 07 03:09:32 PM PDT 24
Peak memory 218780 kb
Host smart-ff9975e4-ed71-4d1f-86fa-d9f576e43162
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065550362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1065550362
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3638798912
Short name T121
Test name
Test status
Simulation time 812421087 ps
CPU time 78.95 seconds
Started May 07 03:09:20 PM PDT 24
Finished May 07 03:10:40 PM PDT 24
Peak memory 212824 kb
Host smart-40fbb516-8021-410e-8929-82a44f853a03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638798912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3638798912
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3168682197
Short name T375
Test name
Test status
Simulation time 21592299282 ps
CPU time 26.33 seconds
Started May 07 03:09:28 PM PDT 24
Finished May 07 03:09:57 PM PDT 24
Peak memory 216428 kb
Host smart-f4265cde-9fc6-4c3e-80ac-64d7cd90c327
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168682197 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3168682197
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3461207839
Short name T416
Test name
Test status
Simulation time 2624601970 ps
CPU time 12.95 seconds
Started May 07 03:09:26 PM PDT 24
Finished May 07 03:09:41 PM PDT 24
Peak memory 210608 kb
Host smart-e1d63a82-a373-4b02-9167-58245de4fdbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461207839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3461207839
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.418763634
Short name T92
Test name
Test status
Simulation time 16081092414 ps
CPU time 131.06 seconds
Started May 07 03:09:27 PM PDT 24
Finished May 07 03:11:41 PM PDT 24
Peak memory 214152 kb
Host smart-00d7ed14-23f4-4966-b82f-ad70499cb200
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418763634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.418763634
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2510790170
Short name T417
Test name
Test status
Simulation time 7675121694 ps
CPU time 30.42 seconds
Started May 07 03:09:23 PM PDT 24
Finished May 07 03:09:55 PM PDT 24
Peak memory 211976 kb
Host smart-d1a374fa-f6fa-48bd-b6b5-de7c92b04cdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510790170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2510790170
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3576636111
Short name T55
Test name
Test status
Simulation time 2434763540 ps
CPU time 27.7 seconds
Started May 07 03:09:22 PM PDT 24
Finished May 07 03:09:51 PM PDT 24
Peak memory 218032 kb
Host smart-fb62c2c4-3a5e-4e01-bcd0-220b97633cd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576636111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3576636111
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.644591912
Short name T61
Test name
Test status
Simulation time 6855212638 ps
CPU time 95.98 seconds
Started May 07 03:09:24 PM PDT 24
Finished May 07 03:11:02 PM PDT 24
Peak memory 213196 kb
Host smart-766db082-0ee3-4847-b35f-a0945f024847
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644591912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.644591912
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.416457224
Short name T391
Test name
Test status
Simulation time 15706162904 ps
CPU time 30.16 seconds
Started May 07 03:09:22 PM PDT 24
Finished May 07 03:09:53 PM PDT 24
Peak memory 217204 kb
Host smart-bc811049-96f9-400d-9820-4f08e87c2013
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416457224 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.416457224
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2535857131
Short name T83
Test name
Test status
Simulation time 1813973688 ps
CPU time 18.62 seconds
Started May 07 03:09:24 PM PDT 24
Finished May 07 03:09:45 PM PDT 24
Peak memory 211140 kb
Host smart-1e69a2e2-7842-48f8-92a7-07d236f40080
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535857131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2535857131
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3498548754
Short name T96
Test name
Test status
Simulation time 63929604124 ps
CPU time 158.12 seconds
Started May 07 03:09:25 PM PDT 24
Finished May 07 03:12:05 PM PDT 24
Peak memory 214832 kb
Host smart-4ad310e1-fd06-4f37-b9c7-95e7e9422283
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498548754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3498548754
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3407752924
Short name T113
Test name
Test status
Simulation time 3801332141 ps
CPU time 27.6 seconds
Started May 07 03:09:24 PM PDT 24
Finished May 07 03:09:54 PM PDT 24
Peak memory 211180 kb
Host smart-542d7e5b-441e-47d7-965d-ea3e41ccd8b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407752924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3407752924
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2498120069
Short name T422
Test name
Test status
Simulation time 3041922563 ps
CPU time 29.94 seconds
Started May 07 03:09:27 PM PDT 24
Finished May 07 03:10:00 PM PDT 24
Peak memory 217904 kb
Host smart-91331b8f-215b-476c-b079-d14d16fe2696
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498120069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2498120069
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.198394189
Short name T129
Test name
Test status
Simulation time 8051821905 ps
CPU time 101.67 seconds
Started May 07 03:09:24 PM PDT 24
Finished May 07 03:11:08 PM PDT 24
Peak memory 212976 kb
Host smart-a4e9e91e-41b7-4b12-9e69-925c003fce03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198394189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.198394189
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3029134641
Short name T89
Test name
Test status
Simulation time 10623910059 ps
CPU time 23.45 seconds
Started May 07 03:09:03 PM PDT 24
Finished May 07 03:09:27 PM PDT 24
Peak memory 211328 kb
Host smart-e9f2085b-f37a-423b-b5f6-f783777629ee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029134641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3029134641
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1980230961
Short name T397
Test name
Test status
Simulation time 4368531149 ps
CPU time 21.82 seconds
Started May 07 03:09:02 PM PDT 24
Finished May 07 03:09:24 PM PDT 24
Peak memory 218776 kb
Host smart-e47d070f-4e56-4034-925d-113011f13932
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980230961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1980230961
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2856549507
Short name T437
Test name
Test status
Simulation time 3266564729 ps
CPU time 31.16 seconds
Started May 07 03:09:06 PM PDT 24
Finished May 07 03:09:37 PM PDT 24
Peak memory 211044 kb
Host smart-bcc52669-e9c0-41b1-88de-9ead932526b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856549507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2856549507
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.144894791
Short name T376
Test name
Test status
Simulation time 3372379365 ps
CPU time 28.19 seconds
Started May 07 03:09:03 PM PDT 24
Finished May 07 03:09:32 PM PDT 24
Peak memory 218864 kb
Host smart-5d2e5659-9ef8-4ee3-929f-bbdb8b049b81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144894791 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.144894791
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1307411705
Short name T438
Test name
Test status
Simulation time 3679764783 ps
CPU time 13.67 seconds
Started May 07 03:09:02 PM PDT 24
Finished May 07 03:09:16 PM PDT 24
Peak memory 210572 kb
Host smart-dc87e748-bf27-4bdd-b687-3ad25e1a4607
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307411705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1307411705
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3452538058
Short name T384
Test name
Test status
Simulation time 6862948027 ps
CPU time 18.02 seconds
Started May 07 03:09:06 PM PDT 24
Finished May 07 03:09:24 PM PDT 24
Peak memory 210536 kb
Host smart-e8edfa5c-842d-4690-8865-37ea65f99af0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452538058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3452538058
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3183602218
Short name T388
Test name
Test status
Simulation time 35805470037 ps
CPU time 31.18 seconds
Started May 07 03:09:03 PM PDT 24
Finished May 07 03:09:35 PM PDT 24
Peak memory 210604 kb
Host smart-5600c56c-54f1-45d7-b765-db5fbf642bb6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183602218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3183602218
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1835893870
Short name T433
Test name
Test status
Simulation time 3225472822 ps
CPU time 24.19 seconds
Started May 07 03:09:03 PM PDT 24
Finished May 07 03:09:28 PM PDT 24
Peak memory 211488 kb
Host smart-51725968-f145-4bfe-8643-e1be49bfaf76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835893870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1835893870
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3600687557
Short name T436
Test name
Test status
Simulation time 4041827652 ps
CPU time 34.21 seconds
Started May 07 03:09:04 PM PDT 24
Finished May 07 03:09:39 PM PDT 24
Peak memory 217540 kb
Host smart-65c0663d-2218-4009-966b-edda6ef14ffc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600687557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3600687557
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3080272589
Short name T78
Test name
Test status
Simulation time 332108131 ps
CPU time 8.11 seconds
Started May 07 03:09:09 PM PDT 24
Finished May 07 03:09:18 PM PDT 24
Peak memory 210512 kb
Host smart-3f9d61bf-f195-4c9e-88bc-bf3030864ec3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080272589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3080272589
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1344059950
Short name T77
Test name
Test status
Simulation time 15402852665 ps
CPU time 29.94 seconds
Started May 07 03:09:14 PM PDT 24
Finished May 07 03:09:44 PM PDT 24
Peak memory 211260 kb
Host smart-ccbbe46a-ab77-4901-a973-0eeea171abe4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344059950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1344059950
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1043968448
Short name T413
Test name
Test status
Simulation time 17159284395 ps
CPU time 32.38 seconds
Started May 07 03:09:20 PM PDT 24
Finished May 07 03:09:54 PM PDT 24
Peak memory 211604 kb
Host smart-e5ae0ae5-fbc7-4c41-bdda-36ab60e7cc7b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043968448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1043968448
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2754659416
Short name T380
Test name
Test status
Simulation time 17190387566 ps
CPU time 33.87 seconds
Started May 07 03:09:12 PM PDT 24
Finished May 07 03:09:47 PM PDT 24
Peak memory 216632 kb
Host smart-76878732-34bc-4ab2-98d5-e03421da2ea3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754659416 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2754659416
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1194394913
Short name T69
Test name
Test status
Simulation time 2009020369 ps
CPU time 14.72 seconds
Started May 07 03:09:12 PM PDT 24
Finished May 07 03:09:28 PM PDT 24
Peak memory 210396 kb
Host smart-5c4d82fd-abd6-4cbc-a33b-8ce4feb4aa7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194394913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1194394913
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.10861387
Short name T383
Test name
Test status
Simulation time 10671175993 ps
CPU time 24.44 seconds
Started May 07 03:09:01 PM PDT 24
Finished May 07 03:09:26 PM PDT 24
Peak memory 210540 kb
Host smart-31a15059-952d-4af0-93ab-f7dd8734a345
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10861387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_
mem_partial_access.10861387
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.510630218
Short name T441
Test name
Test status
Simulation time 13858365383 ps
CPU time 28.35 seconds
Started May 07 03:09:07 PM PDT 24
Finished May 07 03:09:36 PM PDT 24
Peak memory 210448 kb
Host smart-13c54c81-d279-41ca-a0b3-78e32ad0e163
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510630218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
510630218
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1675659203
Short name T108
Test name
Test status
Simulation time 104592636302 ps
CPU time 201.67 seconds
Started May 07 03:09:04 PM PDT 24
Finished May 07 03:12:27 PM PDT 24
Peak memory 214792 kb
Host smart-f6a313e5-0047-4e68-ba36-f948310478e1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675659203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1675659203
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1688885235
Short name T400
Test name
Test status
Simulation time 3295343541 ps
CPU time 8.26 seconds
Started May 07 03:09:16 PM PDT 24
Finished May 07 03:09:26 PM PDT 24
Peak memory 210592 kb
Host smart-2a66b34a-54d2-4776-b73a-3f07b9719510
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688885235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1688885235
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1305872221
Short name T379
Test name
Test status
Simulation time 6149740348 ps
CPU time 22.08 seconds
Started May 07 03:09:02 PM PDT 24
Finished May 07 03:09:25 PM PDT 24
Peak memory 218292 kb
Host smart-b0039aeb-188d-40f3-ae4f-4b4fa6baa5e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305872221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1305872221
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1371327261
Short name T119
Test name
Test status
Simulation time 418351849 ps
CPU time 153.75 seconds
Started May 07 03:09:04 PM PDT 24
Finished May 07 03:11:39 PM PDT 24
Peak memory 213236 kb
Host smart-dc21e032-904a-424b-a49b-38d0bc1d9330
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371327261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1371327261
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.336752659
Short name T451
Test name
Test status
Simulation time 1913413625 ps
CPU time 19.86 seconds
Started May 07 03:09:10 PM PDT 24
Finished May 07 03:09:31 PM PDT 24
Peak memory 210640 kb
Host smart-6b6aee37-7513-474e-b07c-20c4742b395b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336752659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.336752659
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1557581470
Short name T66
Test name
Test status
Simulation time 168996484 ps
CPU time 8.42 seconds
Started May 07 03:09:18 PM PDT 24
Finished May 07 03:09:28 PM PDT 24
Peak memory 210552 kb
Host smart-13c60ba1-b8aa-4613-9012-6bbdb0021c08
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557581470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1557581470
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.317451960
Short name T418
Test name
Test status
Simulation time 595264743 ps
CPU time 13.89 seconds
Started May 07 03:09:12 PM PDT 24
Finished May 07 03:09:27 PM PDT 24
Peak memory 210532 kb
Host smart-7d479333-a3f5-4127-b590-7009851f2898
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317451960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.317451960
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2201116988
Short name T54
Test name
Test status
Simulation time 13773695317 ps
CPU time 28.93 seconds
Started May 07 03:09:11 PM PDT 24
Finished May 07 03:09:41 PM PDT 24
Peak memory 216032 kb
Host smart-546860ab-833a-49ee-b024-99bd8502ca85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201116988 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2201116988
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1644567547
Short name T371
Test name
Test status
Simulation time 1171381134 ps
CPU time 11.54 seconds
Started May 07 03:09:09 PM PDT 24
Finished May 07 03:09:21 PM PDT 24
Peak memory 210536 kb
Host smart-627cf325-9ff3-4ce6-8439-385d444b6d7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644567547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1644567547
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.648894876
Short name T372
Test name
Test status
Simulation time 2553609415 ps
CPU time 22.15 seconds
Started May 07 03:09:10 PM PDT 24
Finished May 07 03:09:34 PM PDT 24
Peak memory 210464 kb
Host smart-57d732ce-50e3-4519-b797-9b46ea487e2b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648894876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.648894876
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3558352008
Short name T367
Test name
Test status
Simulation time 1677186938 ps
CPU time 18.41 seconds
Started May 07 03:09:12 PM PDT 24
Finished May 07 03:09:31 PM PDT 24
Peak memory 210500 kb
Host smart-82b6743c-cb3c-41bf-9b88-3f73fe7bf0d3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558352008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3558352008
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.498053805
Short name T454
Test name
Test status
Simulation time 6081469395 ps
CPU time 65.01 seconds
Started May 07 03:09:12 PM PDT 24
Finished May 07 03:10:18 PM PDT 24
Peak memory 218828 kb
Host smart-5d4ad978-1a17-4b2f-a9dd-97bfe556eacc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498053805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.498053805
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3843991741
Short name T109
Test name
Test status
Simulation time 7073673058 ps
CPU time 31.38 seconds
Started May 07 03:09:15 PM PDT 24
Finished May 07 03:09:47 PM PDT 24
Peak memory 212120 kb
Host smart-3de80aeb-7fed-4812-ae50-172aa5ccc9d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843991741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3843991741
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3275329941
Short name T395
Test name
Test status
Simulation time 2052367459 ps
CPU time 15.97 seconds
Started May 07 03:09:14 PM PDT 24
Finished May 07 03:09:31 PM PDT 24
Peak memory 216960 kb
Host smart-691b59f3-d865-4e4e-b1e8-1f0040b2f2d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275329941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3275329941
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1500863315
Short name T124
Test name
Test status
Simulation time 41157628608 ps
CPU time 100.86 seconds
Started May 07 03:09:11 PM PDT 24
Finished May 07 03:10:53 PM PDT 24
Peak memory 218788 kb
Host smart-e6c38f6a-2609-46ac-b52c-bcc9d9915372
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500863315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1500863315
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1211056199
Short name T387
Test name
Test status
Simulation time 1203430549 ps
CPU time 8.33 seconds
Started May 07 03:09:16 PM PDT 24
Finished May 07 03:09:26 PM PDT 24
Peak memory 212720 kb
Host smart-6f01fcf3-511a-4429-a85d-f92452404d19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211056199 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1211056199
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1694367916
Short name T457
Test name
Test status
Simulation time 6014995931 ps
CPU time 14.42 seconds
Started May 07 03:09:12 PM PDT 24
Finished May 07 03:09:28 PM PDT 24
Peak memory 210852 kb
Host smart-d08876a7-5134-454f-8007-afa642289cd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694367916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1694367916
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3422929879
Short name T403
Test name
Test status
Simulation time 2082102573 ps
CPU time 24.1 seconds
Started May 07 03:09:16 PM PDT 24
Finished May 07 03:09:42 PM PDT 24
Peak memory 211748 kb
Host smart-f3815a22-4225-4c4b-a0bd-e960fb08076f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422929879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3422929879
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.637967736
Short name T382
Test name
Test status
Simulation time 2862768269 ps
CPU time 28.77 seconds
Started May 07 03:09:10 PM PDT 24
Finished May 07 03:09:40 PM PDT 24
Peak memory 217764 kb
Host smart-6e99e365-9c6c-40a9-9c02-4cb9e4e35fef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637967736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.637967736
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.509690802
Short name T125
Test name
Test status
Simulation time 2450783047 ps
CPU time 87.98 seconds
Started May 07 03:09:14 PM PDT 24
Finished May 07 03:10:43 PM PDT 24
Peak memory 211492 kb
Host smart-9b398303-262a-4679-beb8-33e70e92789d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509690802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.509690802
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3694241410
Short name T401
Test name
Test status
Simulation time 714597855 ps
CPU time 8.77 seconds
Started May 07 03:09:12 PM PDT 24
Finished May 07 03:09:22 PM PDT 24
Peak memory 215760 kb
Host smart-bc00951c-19df-4a9e-9f74-7ca3653f5355
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694241410 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3694241410
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1579507554
Short name T370
Test name
Test status
Simulation time 180187335 ps
CPU time 8.31 seconds
Started May 07 03:09:21 PM PDT 24
Finished May 07 03:09:31 PM PDT 24
Peak memory 210536 kb
Host smart-09608a16-6d3c-46b0-bdb1-133ab26a4839
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579507554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1579507554
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.359727394
Short name T87
Test name
Test status
Simulation time 1556287159 ps
CPU time 66.46 seconds
Started May 07 03:09:09 PM PDT 24
Finished May 07 03:10:16 PM PDT 24
Peak memory 214664 kb
Host smart-eb131433-08f0-46ec-852b-5b19e9073e5f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359727394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.359727394
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2013837302
Short name T443
Test name
Test status
Simulation time 17364471593 ps
CPU time 25.89 seconds
Started May 07 03:09:10 PM PDT 24
Finished May 07 03:09:37 PM PDT 24
Peak memory 211968 kb
Host smart-b63e2a21-fea5-4967-8315-8ead9233644c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013837302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2013837302
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3883839432
Short name T396
Test name
Test status
Simulation time 1680749022 ps
CPU time 16.81 seconds
Started May 07 03:09:09 PM PDT 24
Finished May 07 03:09:27 PM PDT 24
Peak memory 218796 kb
Host smart-a03c064f-2313-4b6c-b5ef-3cc6cf9d1290
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883839432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3883839432
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.540731405
Short name T63
Test name
Test status
Simulation time 540427633 ps
CPU time 82.06 seconds
Started May 07 03:09:10 PM PDT 24
Finished May 07 03:10:33 PM PDT 24
Peak memory 213016 kb
Host smart-55bc3ff5-b5e0-4b17-9977-363bb39fa44f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540731405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.540731405
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.883415841
Short name T429
Test name
Test status
Simulation time 8621685140 ps
CPU time 21.7 seconds
Started May 07 03:09:21 PM PDT 24
Finished May 07 03:09:44 PM PDT 24
Peak memory 218956 kb
Host smart-64d4cbc3-fdac-4424-88b2-fd2002602a3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883415841 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.883415841
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1285150272
Short name T393
Test name
Test status
Simulation time 1311607394 ps
CPU time 10.56 seconds
Started May 07 03:09:15 PM PDT 24
Finished May 07 03:09:27 PM PDT 24
Peak memory 210476 kb
Host smart-abc11b2a-a6b4-44ab-b451-f5b16a85313f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285150272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1285150272
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2745108464
Short name T90
Test name
Test status
Simulation time 45736757865 ps
CPU time 96.2 seconds
Started May 07 03:09:14 PM PDT 24
Finished May 07 03:10:51 PM PDT 24
Peak memory 214792 kb
Host smart-d1f0dafb-163a-4031-948f-69c2382f86cd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745108464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2745108464
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2263611101
Short name T445
Test name
Test status
Simulation time 493754648 ps
CPU time 11.98 seconds
Started May 07 03:09:16 PM PDT 24
Finished May 07 03:09:29 PM PDT 24
Peak memory 211616 kb
Host smart-4b7ec7ac-2d10-4588-81f0-21bb7415af4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263611101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2263611101
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3009278738
Short name T423
Test name
Test status
Simulation time 185764384 ps
CPU time 10.96 seconds
Started May 07 03:09:16 PM PDT 24
Finished May 07 03:09:28 PM PDT 24
Peak memory 216552 kb
Host smart-12ed16ed-4d36-4696-88c7-fc71118b72fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009278738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3009278738
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.943816379
Short name T447
Test name
Test status
Simulation time 10192853233 ps
CPU time 23.74 seconds
Started May 07 03:09:18 PM PDT 24
Finished May 07 03:09:43 PM PDT 24
Peak memory 216896 kb
Host smart-43cdaaab-84ae-4bdd-9e70-54a033ddba32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943816379 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.943816379
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1403203799
Short name T402
Test name
Test status
Simulation time 7150913579 ps
CPU time 28.42 seconds
Started May 07 03:09:26 PM PDT 24
Finished May 07 03:09:58 PM PDT 24
Peak memory 211540 kb
Host smart-db44e34d-8bfa-4bb9-9151-a889212861f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403203799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1403203799
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2858275179
Short name T426
Test name
Test status
Simulation time 47392142831 ps
CPU time 85.88 seconds
Started May 07 03:09:17 PM PDT 24
Finished May 07 03:10:44 PM PDT 24
Peak memory 213056 kb
Host smart-c8367d88-60af-4198-8090-256d5abd4583
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858275179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2858275179
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1211103278
Short name T390
Test name
Test status
Simulation time 3680074239 ps
CPU time 28.91 seconds
Started May 07 03:09:18 PM PDT 24
Finished May 07 03:09:48 PM PDT 24
Peak memory 211500 kb
Host smart-8d3412c5-898f-495c-b7ad-5f03d0b87e73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211103278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1211103278
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2860511978
Short name T378
Test name
Test status
Simulation time 8447028799 ps
CPU time 35.07 seconds
Started May 07 03:09:20 PM PDT 24
Finished May 07 03:09:57 PM PDT 24
Peak memory 216796 kb
Host smart-3c7ef709-50c7-466d-b0d4-c113edd1152d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860511978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2860511978
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3177028690
Short name T127
Test name
Test status
Simulation time 2510704550 ps
CPU time 152.95 seconds
Started May 07 03:09:19 PM PDT 24
Finished May 07 03:11:53 PM PDT 24
Peak memory 213420 kb
Host smart-94ed21a1-93ee-4942-8610-aea36061805a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177028690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3177028690
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2169324037
Short name T435
Test name
Test status
Simulation time 613977922 ps
CPU time 8.53 seconds
Started May 07 03:09:14 PM PDT 24
Finished May 07 03:09:23 PM PDT 24
Peak memory 214944 kb
Host smart-be127a8d-34da-439e-842a-93fb6ef1cd14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169324037 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2169324037
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1653717883
Short name T421
Test name
Test status
Simulation time 2062720046 ps
CPU time 19.61 seconds
Started May 07 03:09:15 PM PDT 24
Finished May 07 03:09:35 PM PDT 24
Peak memory 211032 kb
Host smart-d5f2828c-eb88-41df-ae23-d0e52d452202
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653717883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1653717883
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.133394692
Short name T110
Test name
Test status
Simulation time 28917710862 ps
CPU time 79.42 seconds
Started May 07 03:09:19 PM PDT 24
Finished May 07 03:10:39 PM PDT 24
Peak memory 213156 kb
Host smart-8db16d5a-64f3-4d22-826b-9da4e735950d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133394692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.133394692
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.488133876
Short name T112
Test name
Test status
Simulation time 6822179281 ps
CPU time 29.75 seconds
Started May 07 03:09:15 PM PDT 24
Finished May 07 03:09:46 PM PDT 24
Peak memory 211892 kb
Host smart-eb113ffb-e013-4555-bcbd-74d15fc5c6a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488133876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.488133876
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1951264109
Short name T405
Test name
Test status
Simulation time 1294960355 ps
CPU time 20.86 seconds
Started May 07 03:09:16 PM PDT 24
Finished May 07 03:09:38 PM PDT 24
Peak memory 218796 kb
Host smart-98c00d35-3841-4fa0-98e0-3ad2bf093f01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951264109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1951264109
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3759355371
Short name T128
Test name
Test status
Simulation time 8079846603 ps
CPU time 175.27 seconds
Started May 07 03:09:26 PM PDT 24
Finished May 07 03:12:24 PM PDT 24
Peak memory 214548 kb
Host smart-b70a1aa1-7b11-4781-8f08-ad41a03dbcdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759355371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3759355371
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1507669955
Short name T145
Test name
Test status
Simulation time 6584844163 ps
CPU time 18.63 seconds
Started May 07 03:29:24 PM PDT 24
Finished May 07 03:29:44 PM PDT 24
Peak memory 212744 kb
Host smart-ccf1fbfb-135a-4f81-8f72-66b92876d77c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507669955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1507669955
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2068916027
Short name T210
Test name
Test status
Simulation time 113063788422 ps
CPU time 516.64 seconds
Started May 07 03:30:33 PM PDT 24
Finished May 07 03:39:10 PM PDT 24
Peak memory 237280 kb
Host smart-d36ed1cb-52b0-4111-b159-126e15a2ad6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068916027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2068916027
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2470472679
Short name T353
Test name
Test status
Simulation time 1825064398 ps
CPU time 21.07 seconds
Started May 07 03:29:27 PM PDT 24
Finished May 07 03:29:49 PM PDT 24
Peak memory 213112 kb
Host smart-3f0b9fc3-920f-4355-b763-d10a380cfb10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2470472679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2470472679
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1091168984
Short name T28
Test name
Test status
Simulation time 828490686 ps
CPU time 126.43 seconds
Started May 07 03:29:32 PM PDT 24
Finished May 07 03:31:39 PM PDT 24
Peak memory 239304 kb
Host smart-bd2d13e5-a1fb-4421-8778-821e66b14121
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091168984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1091168984
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.86103929
Short name T330
Test name
Test status
Simulation time 22553882610 ps
CPU time 56.47 seconds
Started May 07 03:29:22 PM PDT 24
Finished May 07 03:30:19 PM PDT 24
Peak memory 218512 kb
Host smart-fc89188b-0c34-47ca-ac2f-40a1312fc0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86103929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.86103929
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.162134616
Short name T183
Test name
Test status
Simulation time 30296216302 ps
CPU time 95.78 seconds
Started May 07 03:29:23 PM PDT 24
Finished May 07 03:31:00 PM PDT 24
Peak memory 221296 kb
Host smart-0f20e8b4-4a60-4751-8dac-67c2268e0ab8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162134616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.162134616
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2128440509
Short name T331
Test name
Test status
Simulation time 852371059 ps
CPU time 13.24 seconds
Started May 07 03:29:25 PM PDT 24
Finished May 07 03:29:40 PM PDT 24
Peak memory 211832 kb
Host smart-612d375e-1eef-4b62-8c6b-5ea1e81fa9ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128440509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2128440509
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2261495203
Short name T45
Test name
Test status
Simulation time 82692871578 ps
CPU time 365.16 seconds
Started May 07 03:29:26 PM PDT 24
Finished May 07 03:35:32 PM PDT 24
Peak memory 229468 kb
Host smart-96285d32-8478-4da6-ac96-87e5a592d585
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261495203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2261495203
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2080684634
Short name T319
Test name
Test status
Simulation time 704201905 ps
CPU time 19.19 seconds
Started May 07 03:29:24 PM PDT 24
Finished May 07 03:29:44 PM PDT 24
Peak memory 215192 kb
Host smart-92a91fa8-182e-4954-b4f0-3f05203d8ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080684634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2080684634
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1295594688
Short name T132
Test name
Test status
Simulation time 1236205372 ps
CPU time 10.54 seconds
Started May 07 03:29:30 PM PDT 24
Finished May 07 03:29:42 PM PDT 24
Peak memory 213008 kb
Host smart-d789cca2-26c7-4aab-9fe7-9180a340f9a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1295594688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1295594688
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2519424544
Short name T34
Test name
Test status
Simulation time 15335182010 ps
CPU time 140.48 seconds
Started May 07 03:29:25 PM PDT 24
Finished May 07 03:31:47 PM PDT 24
Peak memory 239140 kb
Host smart-0e9e2c9a-9c0c-424d-ac11-ba66cc07a1b6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519424544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2519424544
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2492287204
Short name T271
Test name
Test status
Simulation time 25953954049 ps
CPU time 57.85 seconds
Started May 07 03:29:32 PM PDT 24
Finished May 07 03:30:31 PM PDT 24
Peak memory 218856 kb
Host smart-aa4732f1-c3ca-4b39-9fb6-00aebf5841a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492287204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2492287204
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3430369314
Short name T297
Test name
Test status
Simulation time 1727867670 ps
CPU time 51.9 seconds
Started May 07 03:29:27 PM PDT 24
Finished May 07 03:30:19 PM PDT 24
Peak memory 219840 kb
Host smart-bfc0ba79-f4e5-4c4d-b9f3-3f1de9628670
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430369314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3430369314
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3559219710
Short name T68
Test name
Test status
Simulation time 3598730464 ps
CPU time 21.76 seconds
Started May 07 03:29:46 PM PDT 24
Finished May 07 03:30:09 PM PDT 24
Peak memory 211448 kb
Host smart-cfc9eb8e-0194-4d20-a53a-ccd86e15b22f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559219710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3559219710
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2834228858
Short name T298
Test name
Test status
Simulation time 82720995856 ps
CPU time 341.51 seconds
Started May 07 03:29:48 PM PDT 24
Finished May 07 03:35:30 PM PDT 24
Peak memory 237416 kb
Host smart-541901e5-c51a-4671-b8f2-8ee387a9581d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834228858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2834228858
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2632375886
Short name T179
Test name
Test status
Simulation time 16039270788 ps
CPU time 63.39 seconds
Started May 07 03:29:49 PM PDT 24
Finished May 07 03:30:53 PM PDT 24
Peak memory 215828 kb
Host smart-42db975a-8c83-4e27-892f-100ef999252a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632375886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2632375886
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1088802223
Short name T213
Test name
Test status
Simulation time 12021322181 ps
CPU time 27.28 seconds
Started May 07 03:29:49 PM PDT 24
Finished May 07 03:30:17 PM PDT 24
Peak memory 213492 kb
Host smart-bb6160b6-d426-4a9d-b749-c90cabc7fa5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088802223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1088802223
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3213367770
Short name T159
Test name
Test status
Simulation time 7214631029 ps
CPU time 70.99 seconds
Started May 07 03:29:44 PM PDT 24
Finished May 07 03:30:55 PM PDT 24
Peak memory 216012 kb
Host smart-fd591ea9-8330-47e0-ae2e-6e651d1f49a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213367770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3213367770
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.355769935
Short name T230
Test name
Test status
Simulation time 4989881929 ps
CPU time 28.21 seconds
Started May 07 03:29:45 PM PDT 24
Finished May 07 03:30:14 PM PDT 24
Peak memory 214636 kb
Host smart-18ff25b6-2c93-47cf-ae98-c5e4c44f26ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355769935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.355769935
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.618266020
Short name T50
Test name
Test status
Simulation time 108117572472 ps
CPU time 2089.48 seconds
Started May 07 03:29:47 PM PDT 24
Finished May 07 04:04:38 PM PDT 24
Peak memory 252828 kb
Host smart-899ec339-8987-464f-b06b-edb329da7201
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618266020 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.618266020
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.441955305
Short name T103
Test name
Test status
Simulation time 17610600320 ps
CPU time 33.5 seconds
Started May 07 03:29:52 PM PDT 24
Finished May 07 03:30:26 PM PDT 24
Peak memory 212824 kb
Host smart-9ff22a69-9e64-42f0-87b7-8d27bd68f7d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441955305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.441955305
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.719721020
Short name T302
Test name
Test status
Simulation time 71279026171 ps
CPU time 305.4 seconds
Started May 07 03:29:53 PM PDT 24
Finished May 07 03:35:00 PM PDT 24
Peak memory 216312 kb
Host smart-c933c209-73e5-4c1e-a4df-838584b705ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719721020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.719721020
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.272935165
Short name T99
Test name
Test status
Simulation time 12252411931 ps
CPU time 38.7 seconds
Started May 07 03:29:48 PM PDT 24
Finished May 07 03:30:28 PM PDT 24
Peak memory 214588 kb
Host smart-1941092e-b94f-48a1-9ee5-42d131cd0dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272935165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.272935165
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.959619060
Short name T317
Test name
Test status
Simulation time 2362718073 ps
CPU time 24.6 seconds
Started May 07 03:29:49 PM PDT 24
Finished May 07 03:30:15 PM PDT 24
Peak memory 211936 kb
Host smart-60e6ee20-a809-4749-8ad9-5c3a8fbbf6ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=959619060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.959619060
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3874695708
Short name T41
Test name
Test status
Simulation time 24592937707 ps
CPU time 65.47 seconds
Started May 07 03:29:47 PM PDT 24
Finished May 07 03:30:54 PM PDT 24
Peak memory 219940 kb
Host smart-78e0e5c1-bd4d-48eb-8944-b8f638916dd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874695708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3874695708
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2792943145
Short name T228
Test name
Test status
Simulation time 167492339 ps
CPU time 8.32 seconds
Started May 07 03:29:49 PM PDT 24
Finished May 07 03:29:58 PM PDT 24
Peak memory 211860 kb
Host smart-cadcce1e-15f2-43f0-b33e-8639a4001ea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792943145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2792943145
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1721200527
Short name T263
Test name
Test status
Simulation time 90191577649 ps
CPU time 820.95 seconds
Started May 07 03:29:51 PM PDT 24
Finished May 07 03:43:33 PM PDT 24
Peak memory 238576 kb
Host smart-7dd2957a-5857-41f0-9c2d-e76331e0602d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721200527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1721200527
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1792583001
Short name T355
Test name
Test status
Simulation time 2638833216 ps
CPU time 35.79 seconds
Started May 07 03:29:49 PM PDT 24
Finished May 07 03:30:26 PM PDT 24
Peak memory 215500 kb
Host smart-b5fb943a-4d32-4b84-a2f3-7c643c71ee35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792583001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1792583001
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1144809469
Short name T171
Test name
Test status
Simulation time 1727392434 ps
CPU time 20.2 seconds
Started May 07 03:29:53 PM PDT 24
Finished May 07 03:30:14 PM PDT 24
Peak memory 211812 kb
Host smart-ebaed6c9-30bf-431d-bd9d-a872e12bd4ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1144809469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1144809469
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2232666308
Short name T241
Test name
Test status
Simulation time 431108375 ps
CPU time 19.7 seconds
Started May 07 03:29:59 PM PDT 24
Finished May 07 03:30:19 PM PDT 24
Peak memory 218232 kb
Host smart-acd15c2c-9ee1-4c2f-9a06-162f1369302f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232666308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2232666308
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2535278603
Short name T299
Test name
Test status
Simulation time 46944269853 ps
CPU time 134.27 seconds
Started May 07 03:29:51 PM PDT 24
Finished May 07 03:32:06 PM PDT 24
Peak memory 221596 kb
Host smart-0c9b457c-3a7c-418f-94a4-d4785db21f99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535278603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2535278603
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1512618748
Short name T209
Test name
Test status
Simulation time 339011487 ps
CPU time 8.15 seconds
Started May 07 03:29:54 PM PDT 24
Finished May 07 03:30:03 PM PDT 24
Peak memory 211848 kb
Host smart-5f710e00-c8c8-499d-bf4b-5a617301ee0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512618748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1512618748
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1432166301
Short name T19
Test name
Test status
Simulation time 268606442112 ps
CPU time 731.56 seconds
Started May 07 03:29:51 PM PDT 24
Finished May 07 03:42:04 PM PDT 24
Peak memory 226008 kb
Host smart-9a160922-5935-46a9-9086-d625f4a3ef60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432166301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1432166301
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2785518054
Short name T311
Test name
Test status
Simulation time 349863598 ps
CPU time 18.88 seconds
Started May 07 03:29:49 PM PDT 24
Finished May 07 03:30:10 PM PDT 24
Peak memory 215204 kb
Host smart-17a22d64-ab63-4a71-9993-8e5ddecde52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785518054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2785518054
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3553121116
Short name T137
Test name
Test status
Simulation time 7099282460 ps
CPU time 25.07 seconds
Started May 07 03:29:50 PM PDT 24
Finished May 07 03:30:16 PM PDT 24
Peak memory 212372 kb
Host smart-15e66e1e-804d-4aa1-9a16-15f681a24dae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3553121116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3553121116
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1819382338
Short name T105
Test name
Test status
Simulation time 9929247212 ps
CPU time 40.6 seconds
Started May 07 03:29:49 PM PDT 24
Finished May 07 03:30:31 PM PDT 24
Peak memory 218180 kb
Host smart-7aaf17b8-da93-4f6a-a121-4f780e707a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819382338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1819382338
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2883573076
Short name T201
Test name
Test status
Simulation time 20427012300 ps
CPU time 75.58 seconds
Started May 07 03:29:49 PM PDT 24
Finished May 07 03:31:06 PM PDT 24
Peak memory 219304 kb
Host smart-27a9da79-948f-418a-a973-67517ade32ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883573076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2883573076
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2455050960
Short name T304
Test name
Test status
Simulation time 8609542939 ps
CPU time 21.79 seconds
Started May 07 03:29:52 PM PDT 24
Finished May 07 03:30:14 PM PDT 24
Peak memory 212712 kb
Host smart-d66d6908-e73d-44b2-8833-b3f946c06823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455050960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2455050960
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.997817164
Short name T217
Test name
Test status
Simulation time 14589366251 ps
CPU time 250.16 seconds
Started May 07 03:29:51 PM PDT 24
Finished May 07 03:34:02 PM PDT 24
Peak memory 240648 kb
Host smart-81d29312-f6c7-40bc-bb4f-f71f81d7133f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997817164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.997817164
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1159086734
Short name T11
Test name
Test status
Simulation time 670137912 ps
CPU time 10.27 seconds
Started May 07 03:29:49 PM PDT 24
Finished May 07 03:30:01 PM PDT 24
Peak memory 213024 kb
Host smart-b55c7002-ce31-41b1-afa8-a1acb2602b7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1159086734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1159086734
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2648796541
Short name T56
Test name
Test status
Simulation time 12066033706 ps
CPU time 60.95 seconds
Started May 07 03:29:52 PM PDT 24
Finished May 07 03:30:54 PM PDT 24
Peak memory 217796 kb
Host smart-8ed66820-dd8f-4154-81ac-b1a8c6228974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648796541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2648796541
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.4119237695
Short name T160
Test name
Test status
Simulation time 11002817301 ps
CPU time 65.07 seconds
Started May 07 03:29:51 PM PDT 24
Finished May 07 03:30:57 PM PDT 24
Peak memory 217700 kb
Host smart-f5dfb46d-b58e-44b3-aa4e-ad1e096c96e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119237695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.4119237695
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1395484070
Short name T36
Test name
Test status
Simulation time 345384905 ps
CPU time 8.42 seconds
Started May 07 03:29:53 PM PDT 24
Finished May 07 03:30:03 PM PDT 24
Peak memory 211952 kb
Host smart-ebac19b4-4893-44d1-8153-aef50a76b2ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395484070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1395484070
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.637380011
Short name T336
Test name
Test status
Simulation time 15154676793 ps
CPU time 267.6 seconds
Started May 07 03:29:54 PM PDT 24
Finished May 07 03:34:23 PM PDT 24
Peak memory 241448 kb
Host smart-f8050ded-4bcd-47a0-b060-479970c747b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637380011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.637380011
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1401255529
Short name T199
Test name
Test status
Simulation time 26156960906 ps
CPU time 56.93 seconds
Started May 07 03:29:59 PM PDT 24
Finished May 07 03:30:57 PM PDT 24
Peak memory 215628 kb
Host smart-f7c5d5a1-db88-456f-af21-e85b4ce975a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401255529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1401255529
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.504833953
Short name T236
Test name
Test status
Simulation time 3009371922 ps
CPU time 26.78 seconds
Started May 07 03:29:54 PM PDT 24
Finished May 07 03:30:22 PM PDT 24
Peak memory 212124 kb
Host smart-ec437e56-1882-4a00-8226-03443b0110e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=504833953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.504833953
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.270997463
Short name T232
Test name
Test status
Simulation time 73929732481 ps
CPU time 56.25 seconds
Started May 07 03:29:52 PM PDT 24
Finished May 07 03:30:49 PM PDT 24
Peak memory 218316 kb
Host smart-170e72e0-8325-47dc-b376-7e0ab5d4efc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270997463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.270997463
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2077637207
Short name T363
Test name
Test status
Simulation time 5999415883 ps
CPU time 53.94 seconds
Started May 07 03:29:59 PM PDT 24
Finished May 07 03:30:54 PM PDT 24
Peak memory 221804 kb
Host smart-89825a5a-75c0-4734-add7-6087b9c4488e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077637207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2077637207
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.82932054
Short name T101
Test name
Test status
Simulation time 18320505173 ps
CPU time 32.65 seconds
Started May 07 03:29:58 PM PDT 24
Finished May 07 03:30:31 PM PDT 24
Peak memory 212684 kb
Host smart-c896b316-cf9e-4c6a-b620-80f2a756bed8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82932054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.82932054
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1390928876
Short name T219
Test name
Test status
Simulation time 1965925509 ps
CPU time 158.91 seconds
Started May 07 03:29:54 PM PDT 24
Finished May 07 03:32:34 PM PDT 24
Peak memory 237768 kb
Host smart-8807a0eb-e8df-4acf-8751-843d76907b42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390928876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1390928876
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1247716495
Short name T326
Test name
Test status
Simulation time 27644080342 ps
CPU time 61.28 seconds
Started May 07 03:29:58 PM PDT 24
Finished May 07 03:30:59 PM PDT 24
Peak memory 215660 kb
Host smart-f9aef68e-4481-4787-bd34-fda8619b4676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247716495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1247716495
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3705318818
Short name T186
Test name
Test status
Simulation time 17261234127 ps
CPU time 34.75 seconds
Started May 07 03:29:59 PM PDT 24
Finished May 07 03:30:34 PM PDT 24
Peak memory 213448 kb
Host smart-d84c9d60-d1a3-4ec7-87f5-6c59b3858fc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3705318818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3705318818
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2657591362
Short name T8
Test name
Test status
Simulation time 12326043979 ps
CPU time 54.66 seconds
Started May 07 03:29:52 PM PDT 24
Finished May 07 03:30:48 PM PDT 24
Peak memory 218668 kb
Host smart-0ad67258-9f13-499f-95c4-35a9e29b55f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657591362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2657591362
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3453570784
Short name T309
Test name
Test status
Simulation time 368876065 ps
CPU time 23.67 seconds
Started May 07 03:29:54 PM PDT 24
Finished May 07 03:30:18 PM PDT 24
Peak memory 218124 kb
Host smart-9b7305ef-723d-4aba-8447-938eec8d084e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453570784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3453570784
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2387951497
Short name T51
Test name
Test status
Simulation time 49881916787 ps
CPU time 3953.04 seconds
Started May 07 03:29:52 PM PDT 24
Finished May 07 04:35:46 PM PDT 24
Peak memory 235900 kb
Host smart-0dfbcc65-9524-4429-b6b9-f51a11bdba28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387951497 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2387951497
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.4183565420
Short name T284
Test name
Test status
Simulation time 4229285280 ps
CPU time 32.38 seconds
Started May 07 03:30:01 PM PDT 24
Finished May 07 03:30:34 PM PDT 24
Peak memory 211920 kb
Host smart-a5b01c4a-dfb6-4bd6-9acb-389eb5ff982f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183565420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.4183565420
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2921760252
Short name T172
Test name
Test status
Simulation time 64580689682 ps
CPU time 482.3 seconds
Started May 07 03:29:55 PM PDT 24
Finished May 07 03:37:58 PM PDT 24
Peak memory 235036 kb
Host smart-7424a5fa-ed6a-403c-b4c3-8334b52be7d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921760252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2921760252
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2545158207
Short name T235
Test name
Test status
Simulation time 47885109073 ps
CPU time 53.69 seconds
Started May 07 03:30:00 PM PDT 24
Finished May 07 03:30:54 PM PDT 24
Peak memory 213592 kb
Host smart-efda327a-ff6c-47c6-9859-abf6f73cf93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545158207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2545158207
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1356172372
Short name T185
Test name
Test status
Simulation time 8354277233 ps
CPU time 34.53 seconds
Started May 07 03:29:59 PM PDT 24
Finished May 07 03:30:34 PM PDT 24
Peak memory 212300 kb
Host smart-f6d9c7d1-49e4-4c9e-bca2-9c7184143a3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1356172372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1356172372
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3021013331
Short name T60
Test name
Test status
Simulation time 2009131752 ps
CPU time 19.59 seconds
Started May 07 03:29:53 PM PDT 24
Finished May 07 03:30:14 PM PDT 24
Peak memory 217184 kb
Host smart-5fe0543a-d132-424e-b53e-0296982e5222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021013331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3021013331
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2560098884
Short name T218
Test name
Test status
Simulation time 8240458721 ps
CPU time 72.2 seconds
Started May 07 03:29:59 PM PDT 24
Finished May 07 03:31:12 PM PDT 24
Peak memory 219216 kb
Host smart-c35ff49b-1344-479e-b43b-065366ba50b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560098884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2560098884
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.281974861
Short name T48
Test name
Test status
Simulation time 22510778167 ps
CPU time 23.97 seconds
Started May 07 03:30:00 PM PDT 24
Finished May 07 03:30:25 PM PDT 24
Peak memory 211980 kb
Host smart-f121e789-6d53-492f-abba-568b74d0c8b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281974861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.281974861
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3968244109
Short name T198
Test name
Test status
Simulation time 71795414944 ps
CPU time 328.75 seconds
Started May 07 03:29:59 PM PDT 24
Finished May 07 03:35:29 PM PDT 24
Peak memory 217712 kb
Host smart-8e482417-cc99-4d71-a568-804dc6bc6cfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968244109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3968244109
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.4023443704
Short name T102
Test name
Test status
Simulation time 8057829748 ps
CPU time 64.84 seconds
Started May 07 03:29:59 PM PDT 24
Finished May 07 03:31:05 PM PDT 24
Peak memory 214636 kb
Host smart-f96b5dd2-12d8-4da3-9247-67f5834222df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023443704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.4023443704
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2965137222
Short name T316
Test name
Test status
Simulation time 21310988985 ps
CPU time 31.86 seconds
Started May 07 03:29:59 PM PDT 24
Finished May 07 03:30:32 PM PDT 24
Peak memory 211948 kb
Host smart-798188ab-15c2-4a94-a1bc-150fb4b3e7b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2965137222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2965137222
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1971856688
Short name T134
Test name
Test status
Simulation time 18575536880 ps
CPU time 47.8 seconds
Started May 07 03:29:59 PM PDT 24
Finished May 07 03:30:47 PM PDT 24
Peak memory 215424 kb
Host smart-bd95899f-15e2-41f4-8594-838edc4b5678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971856688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1971856688
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.357035726
Short name T12
Test name
Test status
Simulation time 13058940597 ps
CPU time 58.58 seconds
Started May 07 03:29:58 PM PDT 24
Finished May 07 03:30:58 PM PDT 24
Peak memory 218780 kb
Host smart-183df5d7-f8f1-42af-a074-871177ea3485
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357035726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.357035726
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3180212068
Short name T176
Test name
Test status
Simulation time 3422026578 ps
CPU time 28.08 seconds
Started May 07 03:30:05 PM PDT 24
Finished May 07 03:30:34 PM PDT 24
Peak memory 212444 kb
Host smart-53a1513b-47b4-4b5c-8571-6b2786ea3c64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180212068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3180212068
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2518927326
Short name T254
Test name
Test status
Simulation time 88228530371 ps
CPU time 852.67 seconds
Started May 07 03:30:02 PM PDT 24
Finished May 07 03:44:15 PM PDT 24
Peak memory 234760 kb
Host smart-70ebe273-59bb-4af0-bfc0-1356a3411808
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518927326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2518927326
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1095088940
Short name T279
Test name
Test status
Simulation time 8201711516 ps
CPU time 66.18 seconds
Started May 07 03:30:03 PM PDT 24
Finished May 07 03:31:10 PM PDT 24
Peak memory 215888 kb
Host smart-2d8f516b-919a-4b82-a2ad-b5b3ae85e8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095088940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1095088940
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.45438077
Short name T10
Test name
Test status
Simulation time 4909019048 ps
CPU time 17.16 seconds
Started May 07 03:30:00 PM PDT 24
Finished May 07 03:30:18 PM PDT 24
Peak memory 213432 kb
Host smart-f56d9eef-2dd0-4dea-81f0-7452cc88d014
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=45438077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.45438077
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2797546615
Short name T184
Test name
Test status
Simulation time 399756312 ps
CPU time 20.39 seconds
Started May 07 03:29:59 PM PDT 24
Finished May 07 03:30:20 PM PDT 24
Peak memory 216404 kb
Host smart-4b2a038a-ae65-4941-91eb-b00d38e8acd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797546615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2797546615
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2488289216
Short name T288
Test name
Test status
Simulation time 2307613888 ps
CPU time 34.16 seconds
Started May 07 03:29:58 PM PDT 24
Finished May 07 03:30:33 PM PDT 24
Peak memory 219932 kb
Host smart-ef1f66c7-2fd3-4113-90ae-c64ec5dc40a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488289216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2488289216
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2359477714
Short name T155
Test name
Test status
Simulation time 2472876537 ps
CPU time 23.1 seconds
Started May 07 03:29:27 PM PDT 24
Finished May 07 03:29:51 PM PDT 24
Peak memory 211992 kb
Host smart-841e5756-3ef3-41ff-98df-fb39658cb7eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359477714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2359477714
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4265940426
Short name T167
Test name
Test status
Simulation time 35644361282 ps
CPU time 259.8 seconds
Started May 07 03:29:26 PM PDT 24
Finished May 07 03:33:47 PM PDT 24
Peak memory 239516 kb
Host smart-82573f9c-cde6-457b-aa35-24ac9945eed0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265940426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.4265940426
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1659774299
Short name T229
Test name
Test status
Simulation time 2997626539 ps
CPU time 19.42 seconds
Started May 07 03:29:32 PM PDT 24
Finished May 07 03:29:52 PM PDT 24
Peak memory 215576 kb
Host smart-a09b99b2-10f5-423e-adac-de7817076262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659774299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1659774299
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.4254668690
Short name T204
Test name
Test status
Simulation time 6124322703 ps
CPU time 18.98 seconds
Started May 07 03:29:32 PM PDT 24
Finished May 07 03:29:52 PM PDT 24
Peak memory 212472 kb
Host smart-6f683f7f-0628-436a-98f3-c463ff23012c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4254668690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.4254668690
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2433471629
Short name T205
Test name
Test status
Simulation time 55149103073 ps
CPU time 66.37 seconds
Started May 07 03:29:25 PM PDT 24
Finished May 07 03:30:32 PM PDT 24
Peak memory 217652 kb
Host smart-6242db96-e538-4384-bfbd-c3cff1c63398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433471629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2433471629
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.251820931
Short name T193
Test name
Test status
Simulation time 39003907519 ps
CPU time 61.68 seconds
Started May 07 03:29:31 PM PDT 24
Finished May 07 03:30:34 PM PDT 24
Peak memory 218836 kb
Host smart-a1aac47f-2027-416a-89b7-c1254d081354
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251820931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.251820931
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3885764606
Short name T31
Test name
Test status
Simulation time 634943046 ps
CPU time 8.25 seconds
Started May 07 03:30:13 PM PDT 24
Finished May 07 03:30:23 PM PDT 24
Peak memory 211824 kb
Host smart-f8a15525-c72d-49ec-a8cb-84e28043851e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885764606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3885764606
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4216502855
Short name T334
Test name
Test status
Simulation time 49608983310 ps
CPU time 383.14 seconds
Started May 07 03:30:13 PM PDT 24
Finished May 07 03:36:38 PM PDT 24
Peak memory 240512 kb
Host smart-571ac3bf-4dcf-423a-8724-7a82e6cd3ac7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216502855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.4216502855
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1750989734
Short name T283
Test name
Test status
Simulation time 49258509100 ps
CPU time 38.26 seconds
Started May 07 03:30:15 PM PDT 24
Finished May 07 03:30:55 PM PDT 24
Peak memory 215612 kb
Host smart-46e6b9e1-4b68-4607-91ed-f8cc475a392f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750989734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1750989734
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2044668214
Short name T165
Test name
Test status
Simulation time 13832537393 ps
CPU time 29.4 seconds
Started May 07 03:30:07 PM PDT 24
Finished May 07 03:30:37 PM PDT 24
Peak memory 213460 kb
Host smart-01397f41-8f0d-48e5-8bee-b6365c6f6e82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2044668214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2044668214
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.788542079
Short name T79
Test name
Test status
Simulation time 1406683257 ps
CPU time 25.09 seconds
Started May 07 03:30:08 PM PDT 24
Finished May 07 03:30:34 PM PDT 24
Peak memory 217964 kb
Host smart-93cf65e3-4d36-41c4-b5d9-c6cd3b810d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788542079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.788542079
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2408540843
Short name T157
Test name
Test status
Simulation time 922042113 ps
CPU time 17.26 seconds
Started May 07 03:30:07 PM PDT 24
Finished May 07 03:30:25 PM PDT 24
Peak memory 213904 kb
Host smart-3b8264fa-6fcb-4127-ab6e-9768829219c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408540843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2408540843
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1799576736
Short name T49
Test name
Test status
Simulation time 82152246250 ps
CPU time 1647.2 seconds
Started May 07 03:30:13 PM PDT 24
Finished May 07 03:57:42 PM PDT 24
Peak memory 237328 kb
Host smart-a1b84251-9e05-4a6f-941e-0887539ba103
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799576736 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1799576736
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.733410258
Short name T335
Test name
Test status
Simulation time 338831086 ps
CPU time 8.27 seconds
Started May 07 03:30:18 PM PDT 24
Finished May 07 03:30:28 PM PDT 24
Peak memory 211840 kb
Host smart-44388fa1-63a3-4643-a640-0ec2934e438a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733410258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.733410258
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1053542320
Short name T192
Test name
Test status
Simulation time 8957082959 ps
CPU time 199.16 seconds
Started May 07 03:30:17 PM PDT 24
Finished May 07 03:33:38 PM PDT 24
Peak memory 218136 kb
Host smart-d27c556e-b25e-4eb6-a8ac-e7909fbe92b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053542320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1053542320
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3593642379
Short name T212
Test name
Test status
Simulation time 11985774751 ps
CPU time 54.05 seconds
Started May 07 03:30:17 PM PDT 24
Finished May 07 03:31:13 PM PDT 24
Peak memory 215676 kb
Host smart-c93716cd-1568-4509-a0e0-015af6f52ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593642379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3593642379
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1733069111
Short name T154
Test name
Test status
Simulation time 1348951564 ps
CPU time 12.47 seconds
Started May 07 03:30:13 PM PDT 24
Finished May 07 03:30:27 PM PDT 24
Peak memory 211784 kb
Host smart-99a43519-e03d-42ab-a702-e06c0c19264f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1733069111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1733069111
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2022425484
Short name T365
Test name
Test status
Simulation time 5323993742 ps
CPU time 32.47 seconds
Started May 07 03:30:11 PM PDT 24
Finished May 07 03:30:45 PM PDT 24
Peak memory 217288 kb
Host smart-53ddefea-4ba3-49cc-b134-1d7aafadca6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022425484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2022425484
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.912797369
Short name T357
Test name
Test status
Simulation time 412226791 ps
CPU time 11.04 seconds
Started May 07 03:30:33 PM PDT 24
Finished May 07 03:30:45 PM PDT 24
Peak memory 214080 kb
Host smart-c7023072-a2bd-4df4-982c-ab348d525d1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912797369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.912797369
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2418602885
Short name T340
Test name
Test status
Simulation time 3815381703 ps
CPU time 29.21 seconds
Started May 07 03:30:18 PM PDT 24
Finished May 07 03:30:48 PM PDT 24
Peak memory 212520 kb
Host smart-8400718c-36b1-4aed-ae1f-65f5a65fc2c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418602885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2418602885
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1975849628
Short name T27
Test name
Test status
Simulation time 42617433169 ps
CPU time 470.63 seconds
Started May 07 03:30:18 PM PDT 24
Finished May 07 03:38:10 PM PDT 24
Peak memory 239420 kb
Host smart-367f3b7e-4b16-497f-aaac-92e984c7525f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975849628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1975849628
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.932713972
Short name T143
Test name
Test status
Simulation time 32710942057 ps
CPU time 52.89 seconds
Started May 07 03:30:22 PM PDT 24
Finished May 07 03:31:16 PM PDT 24
Peak memory 214568 kb
Host smart-70485b76-5c1c-4a06-9911-85e8de9f0d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932713972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.932713972
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.488230284
Short name T37
Test name
Test status
Simulation time 19526778222 ps
CPU time 23.1 seconds
Started May 07 03:30:17 PM PDT 24
Finished May 07 03:30:41 PM PDT 24
Peak memory 211908 kb
Host smart-8cf69e39-5fae-446e-af93-69d33a9ac259
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=488230284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.488230284
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2395689757
Short name T249
Test name
Test status
Simulation time 8450176557 ps
CPU time 74.18 seconds
Started May 07 03:30:19 PM PDT 24
Finished May 07 03:31:34 PM PDT 24
Peak memory 218608 kb
Host smart-8e93c7e2-6511-4986-86e5-4653dce76032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395689757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2395689757
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2474931818
Short name T107
Test name
Test status
Simulation time 4155937527 ps
CPU time 34.52 seconds
Started May 07 03:30:22 PM PDT 24
Finished May 07 03:30:58 PM PDT 24
Peak memory 214200 kb
Host smart-19d45024-f221-45a2-86f7-790e8a066fb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474931818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2474931818
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1915411070
Short name T53
Test name
Test status
Simulation time 154766977854 ps
CPU time 1538.62 seconds
Started May 07 03:30:18 PM PDT 24
Finished May 07 03:55:59 PM PDT 24
Peak memory 237256 kb
Host smart-071f2032-9436-4bcb-a5a3-6df0e2eab8b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915411070 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.1915411070
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1236442504
Short name T58
Test name
Test status
Simulation time 10506753310 ps
CPU time 18.11 seconds
Started May 07 03:30:20 PM PDT 24
Finished May 07 03:30:40 PM PDT 24
Peak memory 212860 kb
Host smart-0d0f534d-78b9-444f-9785-e718ffc04cff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236442504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1236442504
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2025316013
Short name T256
Test name
Test status
Simulation time 17923102145 ps
CPU time 222.02 seconds
Started May 07 03:30:22 PM PDT 24
Finished May 07 03:34:05 PM PDT 24
Peak memory 240424 kb
Host smart-74603ce9-9618-4910-b100-7e00c1359a54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025316013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2025316013
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2753114106
Short name T208
Test name
Test status
Simulation time 1981959786 ps
CPU time 30.73 seconds
Started May 07 03:30:21 PM PDT 24
Finished May 07 03:30:53 PM PDT 24
Peak memory 215356 kb
Host smart-dfb53f90-b3f6-4df1-8f4d-66d7f8f39d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753114106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2753114106
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2990202469
Short name T329
Test name
Test status
Simulation time 1874243304 ps
CPU time 16.42 seconds
Started May 07 03:30:26 PM PDT 24
Finished May 07 03:30:43 PM PDT 24
Peak memory 213172 kb
Host smart-fce39f5f-7536-4271-988e-651d3feb1a1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2990202469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2990202469
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.4223127775
Short name T221
Test name
Test status
Simulation time 1374235941 ps
CPU time 28.84 seconds
Started May 07 03:30:25 PM PDT 24
Finished May 07 03:30:54 PM PDT 24
Peak memory 217664 kb
Host smart-bd29a8e6-4d10-446e-8174-68af5e7e0a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223127775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.4223127775
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2544527178
Short name T80
Test name
Test status
Simulation time 32245244565 ps
CPU time 74.36 seconds
Started May 07 03:30:27 PM PDT 24
Finished May 07 03:31:42 PM PDT 24
Peak memory 217592 kb
Host smart-fcce041c-06b0-4594-aa92-cbc1e8482c9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544527178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2544527178
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.155458202
Short name T338
Test name
Test status
Simulation time 3359818324 ps
CPU time 28.57 seconds
Started May 07 03:30:28 PM PDT 24
Finished May 07 03:30:57 PM PDT 24
Peak memory 212416 kb
Host smart-8b79c029-d7fd-4097-90b8-ee969850bbdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155458202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.155458202
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3989141457
Short name T265
Test name
Test status
Simulation time 42308736080 ps
CPU time 192.53 seconds
Started May 07 03:30:23 PM PDT 24
Finished May 07 03:33:37 PM PDT 24
Peak memory 225164 kb
Host smart-5cefd10c-3c2b-4aec-ba64-62b085cceff9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989141457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3989141457
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1936480400
Short name T312
Test name
Test status
Simulation time 6044474275 ps
CPU time 30.84 seconds
Started May 07 03:30:26 PM PDT 24
Finished May 07 03:30:57 PM PDT 24
Peak memory 216040 kb
Host smart-b7a26730-22b7-4eb8-9d37-31bbcb70241c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936480400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1936480400
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1492573794
Short name T42
Test name
Test status
Simulation time 3791971748 ps
CPU time 31.11 seconds
Started May 07 03:30:25 PM PDT 24
Finished May 07 03:30:57 PM PDT 24
Peak memory 212180 kb
Host smart-e7dd8149-380f-4600-90f9-e193d09ec41f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1492573794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1492573794
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2135633848
Short name T342
Test name
Test status
Simulation time 3489508556 ps
CPU time 26.01 seconds
Started May 07 03:30:25 PM PDT 24
Finished May 07 03:30:52 PM PDT 24
Peak memory 218080 kb
Host smart-18113a65-8264-4af4-8fb8-b6404733199d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135633848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2135633848
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.731086081
Short name T82
Test name
Test status
Simulation time 550825711 ps
CPU time 40.28 seconds
Started May 07 03:30:23 PM PDT 24
Finished May 07 03:31:04 PM PDT 24
Peak memory 219828 kb
Host smart-43483089-2783-4d06-8fbe-d9985b86c46b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731086081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.731086081
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2836699476
Short name T52
Test name
Test status
Simulation time 148519320727 ps
CPU time 1373.37 seconds
Started May 07 03:30:29 PM PDT 24
Finished May 07 03:53:23 PM PDT 24
Peak memory 236796 kb
Host smart-e177f76b-7e82-453f-8ccd-b8ca856a5c26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836699476 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.2836699476
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.744198000
Short name T142
Test name
Test status
Simulation time 13068098733 ps
CPU time 28.03 seconds
Started May 07 03:30:28 PM PDT 24
Finished May 07 03:30:57 PM PDT 24
Peak memory 212700 kb
Host smart-04d6e75f-d713-49aa-a7b4-c402e38ec1bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744198000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.744198000
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.383492568
Short name T268
Test name
Test status
Simulation time 232972941743 ps
CPU time 365.58 seconds
Started May 07 03:30:28 PM PDT 24
Finished May 07 03:36:34 PM PDT 24
Peak memory 217348 kb
Host smart-4ef71a4f-28e1-4fba-99cc-5c957c1557a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383492568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.383492568
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1307626434
Short name T175
Test name
Test status
Simulation time 7864173080 ps
CPU time 32.91 seconds
Started May 07 03:30:28 PM PDT 24
Finished May 07 03:31:02 PM PDT 24
Peak memory 216816 kb
Host smart-12ce174e-b0a6-4071-b68b-48227fb0550d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307626434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1307626434
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1558437968
Short name T362
Test name
Test status
Simulation time 7706679434 ps
CPU time 30.14 seconds
Started May 07 03:30:27 PM PDT 24
Finished May 07 03:30:58 PM PDT 24
Peak memory 212116 kb
Host smart-a121bfbb-f2bd-4a5e-a334-01e210a5a6c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1558437968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1558437968
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3795815111
Short name T163
Test name
Test status
Simulation time 4605420717 ps
CPU time 46.37 seconds
Started May 07 03:30:27 PM PDT 24
Finished May 07 03:31:14 PM PDT 24
Peak memory 215840 kb
Host smart-eedd1be9-c911-4ff0-b532-2807ea95064e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795815111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3795815111
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.815055408
Short name T243
Test name
Test status
Simulation time 8595177213 ps
CPU time 112.73 seconds
Started May 07 03:30:28 PM PDT 24
Finished May 07 03:32:21 PM PDT 24
Peak memory 222032 kb
Host smart-ae5191dc-6290-41fe-b0c2-273dbe392bfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815055408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.815055408
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1664941949
Short name T360
Test name
Test status
Simulation time 4111815245 ps
CPU time 15.39 seconds
Started May 07 03:30:33 PM PDT 24
Finished May 07 03:30:50 PM PDT 24
Peak memory 211892 kb
Host smart-e375b3ab-2b1c-41e9-bbd2-5952810bbd65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664941949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1664941949
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.607837390
Short name T285
Test name
Test status
Simulation time 48551973454 ps
CPU time 334.49 seconds
Started May 07 03:30:27 PM PDT 24
Finished May 07 03:36:02 PM PDT 24
Peak memory 238456 kb
Host smart-ba85f5a7-fb66-4e18-a71f-e0095e20bb20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607837390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.607837390
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.528254142
Short name T266
Test name
Test status
Simulation time 5249310062 ps
CPU time 28.97 seconds
Started May 07 03:30:29 PM PDT 24
Finished May 07 03:30:59 PM PDT 24
Peak memory 214576 kb
Host smart-85df1bc8-d848-4734-97d1-6ad191e4737f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528254142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.528254142
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.606634510
Short name T141
Test name
Test status
Simulation time 182138618 ps
CPU time 10.41 seconds
Started May 07 03:30:26 PM PDT 24
Finished May 07 03:30:37 PM PDT 24
Peak memory 212908 kb
Host smart-da823ecc-cbb4-474f-a367-ac2dc5d83a20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=606634510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.606634510
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.61038790
Short name T166
Test name
Test status
Simulation time 8428905555 ps
CPU time 73.15 seconds
Started May 07 03:30:27 PM PDT 24
Finished May 07 03:31:41 PM PDT 24
Peak memory 217452 kb
Host smart-25143741-b6a8-495c-b196-c9aec2a09bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61038790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.61038790
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1347305130
Short name T220
Test name
Test status
Simulation time 79797032372 ps
CPU time 75.38 seconds
Started May 07 03:30:29 PM PDT 24
Finished May 07 03:31:45 PM PDT 24
Peak memory 221268 kb
Host smart-6fe1d8d0-038c-42a5-bfb2-0b0aa8fda543
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347305130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1347305130
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1416952564
Short name T180
Test name
Test status
Simulation time 3184583587 ps
CPU time 27.28 seconds
Started May 07 03:30:32 PM PDT 24
Finished May 07 03:31:00 PM PDT 24
Peak memory 212488 kb
Host smart-abd6ca9a-d7d0-41f5-9b29-7132d6f96efe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416952564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1416952564
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3886009103
Short name T44
Test name
Test status
Simulation time 34305742128 ps
CPU time 228.11 seconds
Started May 07 03:30:34 PM PDT 24
Finished May 07 03:34:23 PM PDT 24
Peak memory 216596 kb
Host smart-602ad4cd-8dc7-4add-b0fd-ab361d88d3a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886009103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3886009103
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2468291802
Short name T162
Test name
Test status
Simulation time 1376928942 ps
CPU time 18.9 seconds
Started May 07 03:30:33 PM PDT 24
Finished May 07 03:30:53 PM PDT 24
Peak memory 215280 kb
Host smart-eb1bf1c2-2514-48b5-8ea6-9676d91b7fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468291802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2468291802
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3040265412
Short name T348
Test name
Test status
Simulation time 3957026845 ps
CPU time 17.01 seconds
Started May 07 03:30:33 PM PDT 24
Finished May 07 03:30:52 PM PDT 24
Peak memory 211948 kb
Host smart-75237b48-6380-460a-aa72-29b31ec5717f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3040265412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3040265412
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1237213446
Short name T274
Test name
Test status
Simulation time 2325907650 ps
CPU time 23.47 seconds
Started May 07 03:30:33 PM PDT 24
Finished May 07 03:30:57 PM PDT 24
Peak memory 217736 kb
Host smart-b3bf22a9-0402-48d5-bff6-658371b2290a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237213446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1237213446
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.814099610
Short name T273
Test name
Test status
Simulation time 1787772019 ps
CPU time 61.12 seconds
Started May 07 03:30:33 PM PDT 24
Finished May 07 03:31:35 PM PDT 24
Peak memory 219852 kb
Host smart-c3a7d55c-f70e-49de-9f9a-bfa57b8283e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814099610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.814099610
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.612920608
Short name T169
Test name
Test status
Simulation time 14213972214 ps
CPU time 30.12 seconds
Started May 07 03:30:38 PM PDT 24
Finished May 07 03:31:09 PM PDT 24
Peak memory 212716 kb
Host smart-0ab0263a-ee75-49a1-abf7-07b56753219d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612920608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.612920608
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1840551091
Short name T26
Test name
Test status
Simulation time 39187239302 ps
CPU time 381.4 seconds
Started May 07 03:30:36 PM PDT 24
Finished May 07 03:36:58 PM PDT 24
Peak memory 216304 kb
Host smart-792e6e04-0bd8-4d9f-b047-8f6f3e739210
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840551091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1840551091
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.334414424
Short name T182
Test name
Test status
Simulation time 342728389 ps
CPU time 19.03 seconds
Started May 07 03:30:37 PM PDT 24
Finished May 07 03:30:57 PM PDT 24
Peak memory 215212 kb
Host smart-5ab9b16f-c5f8-4636-9ebb-92a54d913bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334414424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.334414424
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1210716009
Short name T233
Test name
Test status
Simulation time 14835252598 ps
CPU time 29.12 seconds
Started May 07 03:30:37 PM PDT 24
Finished May 07 03:31:07 PM PDT 24
Peak memory 212216 kb
Host smart-e7b32ab4-d794-4688-96eb-41ea589ae4b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1210716009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1210716009
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2852276875
Short name T216
Test name
Test status
Simulation time 33432950124 ps
CPU time 66.49 seconds
Started May 07 03:30:35 PM PDT 24
Finished May 07 03:31:42 PM PDT 24
Peak memory 217504 kb
Host smart-9016e08c-aaa0-4240-90fb-79ac4cd310a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852276875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2852276875
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3274595092
Short name T245
Test name
Test status
Simulation time 10911945138 ps
CPU time 124.01 seconds
Started May 07 03:30:42 PM PDT 24
Finished May 07 03:32:46 PM PDT 24
Peak memory 220984 kb
Host smart-24a3ba17-87ef-401e-aa2f-28615e05ada7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274595092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3274595092
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2992488322
Short name T231
Test name
Test status
Simulation time 688647423 ps
CPU time 8.18 seconds
Started May 07 03:30:44 PM PDT 24
Finished May 07 03:30:53 PM PDT 24
Peak memory 211912 kb
Host smart-56963b55-0010-408d-b0bb-6e01d1cbbd7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992488322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2992488322
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.818396112
Short name T189
Test name
Test status
Simulation time 182964411441 ps
CPU time 228.29 seconds
Started May 07 03:30:38 PM PDT 24
Finished May 07 03:34:27 PM PDT 24
Peak memory 240196 kb
Host smart-a47b2198-d5c8-4c0c-8690-43fdfaf2dada
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818396112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.818396112
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1183488119
Short name T257
Test name
Test status
Simulation time 27365295904 ps
CPU time 57.12 seconds
Started May 07 03:30:37 PM PDT 24
Finished May 07 03:31:35 PM PDT 24
Peak memory 216012 kb
Host smart-cdaae81e-9d4b-4ad3-99f7-9c1d3e1bae8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183488119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1183488119
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2159541629
Short name T100
Test name
Test status
Simulation time 7575701048 ps
CPU time 21.6 seconds
Started May 07 03:30:41 PM PDT 24
Finished May 07 03:31:03 PM PDT 24
Peak memory 212436 kb
Host smart-361b91fc-505a-4809-96ca-bd4861e0d6e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2159541629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2159541629
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.4006885501
Short name T347
Test name
Test status
Simulation time 61201368794 ps
CPU time 63.81 seconds
Started May 07 03:30:36 PM PDT 24
Finished May 07 03:31:41 PM PDT 24
Peak memory 218728 kb
Host smart-c7f5a89f-7a96-48d2-a08f-529661fb1afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006885501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.4006885501
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2505133577
Short name T277
Test name
Test status
Simulation time 393687416 ps
CPU time 24.65 seconds
Started May 07 03:30:38 PM PDT 24
Finished May 07 03:31:03 PM PDT 24
Peak memory 218748 kb
Host smart-33b812ed-75e4-4ab4-9404-ea5c20a83884
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505133577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2505133577
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2790405363
Short name T359
Test name
Test status
Simulation time 3396380448 ps
CPU time 27.34 seconds
Started May 07 03:29:32 PM PDT 24
Finished May 07 03:30:01 PM PDT 24
Peak memory 212528 kb
Host smart-674ce89f-0e77-46bb-a7d1-392d39c67869
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790405363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2790405363
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1575018853
Short name T225
Test name
Test status
Simulation time 40347437557 ps
CPU time 679.04 seconds
Started May 07 03:29:32 PM PDT 24
Finished May 07 03:40:52 PM PDT 24
Peak memory 226204 kb
Host smart-898ba0be-fade-4970-84a6-9eba086b517a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575018853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1575018853
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4263912161
Short name T281
Test name
Test status
Simulation time 5097631205 ps
CPU time 41.45 seconds
Started May 07 03:29:31 PM PDT 24
Finished May 07 03:30:13 PM PDT 24
Peak memory 213676 kb
Host smart-547bcc78-aa40-4a44-a6b0-a6c7bea41f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263912161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4263912161
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.790319093
Short name T321
Test name
Test status
Simulation time 7567932606 ps
CPU time 31.62 seconds
Started May 07 03:29:32 PM PDT 24
Finished May 07 03:30:04 PM PDT 24
Peak memory 211944 kb
Host smart-42f957bf-5156-4321-bb2a-99d95fc7ecf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=790319093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.790319093
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3580238628
Short name T33
Test name
Test status
Simulation time 14031574001 ps
CPU time 135.5 seconds
Started May 07 03:29:33 PM PDT 24
Finished May 07 03:31:50 PM PDT 24
Peak memory 239232 kb
Host smart-4cc6fff9-593e-4ce5-adf7-84dbcf180b34
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580238628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3580238628
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.374752472
Short name T161
Test name
Test status
Simulation time 348145686 ps
CPU time 20.68 seconds
Started May 07 03:29:32 PM PDT 24
Finished May 07 03:29:54 PM PDT 24
Peak memory 215796 kb
Host smart-1685148c-c01f-4571-bbef-14ea68315582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374752472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.374752472
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2968570601
Short name T151
Test name
Test status
Simulation time 6175302830 ps
CPU time 80.53 seconds
Started May 07 03:29:33 PM PDT 24
Finished May 07 03:30:55 PM PDT 24
Peak memory 219972 kb
Host smart-54bd67ec-d8d7-4944-95ae-8c66865f2c79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968570601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2968570601
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1206906075
Short name T178
Test name
Test status
Simulation time 636590476 ps
CPU time 8.24 seconds
Started May 07 03:30:45 PM PDT 24
Finished May 07 03:30:54 PM PDT 24
Peak memory 211840 kb
Host smart-02325722-57f0-42f4-b58e-32f73fed759f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206906075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1206906075
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1657168215
Short name T286
Test name
Test status
Simulation time 338597118241 ps
CPU time 859.68 seconds
Started May 07 03:30:43 PM PDT 24
Finished May 07 03:45:03 PM PDT 24
Peak memory 225752 kb
Host smart-3bf3f318-1c03-4dfd-a1c3-a34cff24bb18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657168215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1657168215
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3671399462
Short name T136
Test name
Test status
Simulation time 2636089926 ps
CPU time 28.61 seconds
Started May 07 03:30:45 PM PDT 24
Finished May 07 03:31:14 PM PDT 24
Peak memory 215488 kb
Host smart-f4ccc8ad-9785-464f-9ecd-b148715f4c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671399462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3671399462
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.631432889
Short name T222
Test name
Test status
Simulation time 744852956 ps
CPU time 10.3 seconds
Started May 07 03:30:43 PM PDT 24
Finished May 07 03:30:54 PM PDT 24
Peak memory 212076 kb
Host smart-b3457697-0ac6-44c1-be09-9b96152b6cc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=631432889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.631432889
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3609963236
Short name T239
Test name
Test status
Simulation time 5774411800 ps
CPU time 52.94 seconds
Started May 07 03:30:45 PM PDT 24
Finished May 07 03:31:39 PM PDT 24
Peak memory 218580 kb
Host smart-e03d7a63-9961-4e65-9d55-00f4b1019f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609963236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3609963236
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3138498382
Short name T306
Test name
Test status
Simulation time 36466370301 ps
CPU time 86.27 seconds
Started May 07 03:30:42 PM PDT 24
Finished May 07 03:32:09 PM PDT 24
Peak memory 220764 kb
Host smart-fc53dc6e-a590-4a00-8c75-183082c20f52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138498382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3138498382
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.4125124667
Short name T15
Test name
Test status
Simulation time 54133188877 ps
CPU time 10123.6 seconds
Started May 07 03:30:43 PM PDT 24
Finished May 07 06:19:28 PM PDT 24
Peak memory 234668 kb
Host smart-efef8de4-04f0-4166-8edc-7c68ef8e7b5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125124667 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.4125124667
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2939399470
Short name T237
Test name
Test status
Simulation time 3619259120 ps
CPU time 29.43 seconds
Started May 07 03:30:48 PM PDT 24
Finished May 07 03:31:18 PM PDT 24
Peak memory 211940 kb
Host smart-ba050931-6211-49dd-a61d-4a768e92106a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939399470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2939399470
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.982614208
Short name T260
Test name
Test status
Simulation time 8243554928 ps
CPU time 183.09 seconds
Started May 07 03:30:48 PM PDT 24
Finished May 07 03:33:53 PM PDT 24
Peak memory 241368 kb
Host smart-8be4b2b2-3fb6-4e34-a6aa-761d2d302e87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982614208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.982614208
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1170149031
Short name T191
Test name
Test status
Simulation time 342725072 ps
CPU time 19.24 seconds
Started May 07 03:30:48 PM PDT 24
Finished May 07 03:31:08 PM PDT 24
Peak memory 215288 kb
Host smart-7b5d0aa9-3abe-4435-ba8b-d04cc310019c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170149031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1170149031
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3487506606
Short name T152
Test name
Test status
Simulation time 4545155800 ps
CPU time 24.04 seconds
Started May 07 03:30:43 PM PDT 24
Finished May 07 03:31:08 PM PDT 24
Peak memory 217200 kb
Host smart-28746baf-2316-483e-a65a-f2a2b3e714b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487506606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3487506606
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.263245813
Short name T320
Test name
Test status
Simulation time 22434299674 ps
CPU time 68.62 seconds
Started May 07 03:30:44 PM PDT 24
Finished May 07 03:31:53 PM PDT 24
Peak memory 219432 kb
Host smart-71bb9c77-389c-4f64-836d-7136d6452cbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263245813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.263245813
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.4149078193
Short name T247
Test name
Test status
Simulation time 6119122560 ps
CPU time 17.79 seconds
Started May 07 03:30:48 PM PDT 24
Finished May 07 03:31:07 PM PDT 24
Peak memory 212788 kb
Host smart-8a7ddbe2-8a5c-4155-bfb7-074175a4cc33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149078193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.4149078193
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1376920285
Short name T181
Test name
Test status
Simulation time 17497169015 ps
CPU time 279.61 seconds
Started May 07 03:30:47 PM PDT 24
Finished May 07 03:35:28 PM PDT 24
Peak memory 240860 kb
Host smart-da3c0533-bc52-4ef5-8355-84d53d1dd138
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376920285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1376920285
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2084486760
Short name T244
Test name
Test status
Simulation time 8040054250 ps
CPU time 65.58 seconds
Started May 07 03:30:50 PM PDT 24
Finished May 07 03:31:57 PM PDT 24
Peak memory 215596 kb
Host smart-e614cfb6-0ebc-4380-9682-202a6439634e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084486760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2084486760
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3885577613
Short name T140
Test name
Test status
Simulation time 5168611954 ps
CPU time 18.26 seconds
Started May 07 03:30:48 PM PDT 24
Finished May 07 03:31:07 PM PDT 24
Peak memory 213428 kb
Host smart-7e5d456a-f043-49b7-9ca5-69632c41d8ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3885577613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3885577613
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3837746723
Short name T200
Test name
Test status
Simulation time 18118269142 ps
CPU time 68.87 seconds
Started May 07 03:30:48 PM PDT 24
Finished May 07 03:31:58 PM PDT 24
Peak memory 218580 kb
Host smart-681cc704-2467-4830-83b8-9055349c9dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837746723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3837746723
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.612943579
Short name T14
Test name
Test status
Simulation time 18209379883 ps
CPU time 2086.99 seconds
Started May 07 03:30:50 PM PDT 24
Finished May 07 04:05:38 PM PDT 24
Peak memory 229340 kb
Host smart-4b01a210-5aa8-461b-a5f8-76c6d05cbe07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612943579 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.612943579
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3093184800
Short name T144
Test name
Test status
Simulation time 414746956 ps
CPU time 11.19 seconds
Started May 07 03:30:53 PM PDT 24
Finished May 07 03:31:05 PM PDT 24
Peak memory 211848 kb
Host smart-1bcde9df-8ff3-4b00-a8ca-13a8105b8225
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093184800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3093184800
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.704478264
Short name T131
Test name
Test status
Simulation time 163577785905 ps
CPU time 720.17 seconds
Started May 07 03:30:48 PM PDT 24
Finished May 07 03:42:49 PM PDT 24
Peak memory 240440 kb
Host smart-f9f59be3-30a9-4f7b-a498-154bd90a10cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704478264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.704478264
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3706758236
Short name T21
Test name
Test status
Simulation time 24292573895 ps
CPU time 58.56 seconds
Started May 07 03:30:47 PM PDT 24
Finished May 07 03:31:46 PM PDT 24
Peak memory 214708 kb
Host smart-364017fe-fa72-4da7-a773-1cd52a12407b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706758236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3706758236
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1583176315
Short name T150
Test name
Test status
Simulation time 352833111 ps
CPU time 12.99 seconds
Started May 07 03:30:48 PM PDT 24
Finished May 07 03:31:02 PM PDT 24
Peak memory 211872 kb
Host smart-bd8fc412-3fab-4a26-984b-daf0a33c8974
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1583176315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1583176315
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.550402663
Short name T276
Test name
Test status
Simulation time 8047173159 ps
CPU time 66.16 seconds
Started May 07 03:30:50 PM PDT 24
Finished May 07 03:31:57 PM PDT 24
Peak memory 217864 kb
Host smart-3810f884-05a3-4d89-ba7c-c8dae6ec22f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550402663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.550402663
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1069973356
Short name T16
Test name
Test status
Simulation time 2834767918 ps
CPU time 61.38 seconds
Started May 07 03:30:47 PM PDT 24
Finished May 07 03:31:50 PM PDT 24
Peak memory 222328 kb
Host smart-bea90f98-45da-4b6f-a6ed-9833e7c9e50d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069973356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1069973356
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2011238618
Short name T325
Test name
Test status
Simulation time 1351246070 ps
CPU time 15.81 seconds
Started May 07 03:30:52 PM PDT 24
Finished May 07 03:31:09 PM PDT 24
Peak memory 211872 kb
Host smart-86f0ffaf-66fc-4de6-8459-a50a2d1b83ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011238618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2011238618
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1407631540
Short name T322
Test name
Test status
Simulation time 147702258789 ps
CPU time 465.41 seconds
Started May 07 03:30:51 PM PDT 24
Finished May 07 03:38:37 PM PDT 24
Peak memory 229244 kb
Host smart-cad973a9-eee8-40f9-8fa7-70292a1ea6fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407631540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1407631540
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3835755340
Short name T290
Test name
Test status
Simulation time 3450127675 ps
CPU time 31.86 seconds
Started May 07 03:30:52 PM PDT 24
Finished May 07 03:31:25 PM PDT 24
Peak memory 214392 kb
Host smart-8366e07c-573d-4ff1-868d-028f927f2758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835755340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3835755340
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.4293431241
Short name T242
Test name
Test status
Simulation time 4123039386 ps
CPU time 16.95 seconds
Started May 07 03:30:53 PM PDT 24
Finished May 07 03:31:11 PM PDT 24
Peak memory 212324 kb
Host smart-95a8c6fe-67fc-48a9-9114-9c201d89864a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4293431241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.4293431241
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1029376761
Short name T64
Test name
Test status
Simulation time 3367821781 ps
CPU time 32.51 seconds
Started May 07 03:30:51 PM PDT 24
Finished May 07 03:31:25 PM PDT 24
Peak memory 217928 kb
Host smart-f7c5c090-36c2-47b5-bfdb-48e8e17c7f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029376761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1029376761
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1438460727
Short name T333
Test name
Test status
Simulation time 865913884 ps
CPU time 51.77 seconds
Started May 07 03:30:51 PM PDT 24
Finished May 07 03:31:44 PM PDT 24
Peak memory 219836 kb
Host smart-597c04e6-6482-4e57-b04a-f8c7b126e61a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438460727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1438460727
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3396431968
Short name T293
Test name
Test status
Simulation time 2058640564 ps
CPU time 8.34 seconds
Started May 07 03:30:53 PM PDT 24
Finished May 07 03:31:02 PM PDT 24
Peak memory 211840 kb
Host smart-ace62a4b-2a1b-4337-9176-274ebfae06d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396431968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3396431968
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.531442685
Short name T280
Test name
Test status
Simulation time 714123703044 ps
CPU time 932.44 seconds
Started May 07 03:30:51 PM PDT 24
Finished May 07 03:46:24 PM PDT 24
Peak memory 238352 kb
Host smart-c8ef7e2a-f6e3-4c55-8e3c-e371d8f9711a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531442685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.531442685
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.551097512
Short name T305
Test name
Test status
Simulation time 1183998632 ps
CPU time 27.24 seconds
Started May 07 03:30:51 PM PDT 24
Finished May 07 03:31:19 PM PDT 24
Peak memory 215328 kb
Host smart-c74e4849-0ad5-4357-b9d6-0fb732f88020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551097512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.551097512
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1740850779
Short name T364
Test name
Test status
Simulation time 3783270454 ps
CPU time 21.65 seconds
Started May 07 03:30:54 PM PDT 24
Finished May 07 03:31:16 PM PDT 24
Peak memory 211968 kb
Host smart-37ff1c25-b521-46fb-b636-d8c35e225a9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1740850779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1740850779
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2656392241
Short name T352
Test name
Test status
Simulation time 754531996 ps
CPU time 19.84 seconds
Started May 07 03:30:50 PM PDT 24
Finished May 07 03:31:11 PM PDT 24
Peak memory 218224 kb
Host smart-c656b5fc-6f1a-4a53-b2db-e05375360af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656392241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2656392241
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1859546637
Short name T81
Test name
Test status
Simulation time 1484001210 ps
CPU time 47.71 seconds
Started May 07 03:30:53 PM PDT 24
Finished May 07 03:31:42 PM PDT 24
Peak memory 219836 kb
Host smart-b6d4cc52-9263-4959-989c-3d6f093677d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859546637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1859546637
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2796917427
Short name T67
Test name
Test status
Simulation time 1956104681 ps
CPU time 20.26 seconds
Started May 07 03:31:00 PM PDT 24
Finished May 07 03:31:20 PM PDT 24
Peak memory 212336 kb
Host smart-a604ea6d-ea80-4bae-82a8-8c2a9b4af74d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796917427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2796917427
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.377726973
Short name T315
Test name
Test status
Simulation time 88623404972 ps
CPU time 876.73 seconds
Started May 07 03:30:58 PM PDT 24
Finished May 07 03:45:36 PM PDT 24
Peak memory 238372 kb
Host smart-5d6c0c45-addf-4ba2-b857-9f00b5f6a2a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377726973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.377726973
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3921903217
Short name T318
Test name
Test status
Simulation time 3759672245 ps
CPU time 43.17 seconds
Started May 07 03:30:58 PM PDT 24
Finished May 07 03:31:41 PM PDT 24
Peak memory 215336 kb
Host smart-40595cd7-e3d2-4e55-be5b-c4dd80a780bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921903217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3921903217
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.943201287
Short name T170
Test name
Test status
Simulation time 2314467302 ps
CPU time 21.05 seconds
Started May 07 03:30:57 PM PDT 24
Finished May 07 03:31:19 PM PDT 24
Peak memory 212164 kb
Host smart-2757a72f-c4e2-43ec-a44e-312be3b8b1dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=943201287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.943201287
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1892498636
Short name T149
Test name
Test status
Simulation time 7074767146 ps
CPU time 46.09 seconds
Started May 07 03:30:58 PM PDT 24
Finished May 07 03:31:45 PM PDT 24
Peak memory 218564 kb
Host smart-3a806eb1-27be-47a4-8a60-5696b349f566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892498636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1892498636
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.131134065
Short name T238
Test name
Test status
Simulation time 77539712152 ps
CPU time 142.43 seconds
Started May 07 03:30:59 PM PDT 24
Finished May 07 03:33:22 PM PDT 24
Peak memory 222784 kb
Host smart-9d1476cd-fa38-4047-893e-e73ff3684c24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131134065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.131134065
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1367922887
Short name T323
Test name
Test status
Simulation time 1481648031 ps
CPU time 13.8 seconds
Started May 07 03:31:05 PM PDT 24
Finished May 07 03:31:20 PM PDT 24
Peak memory 211872 kb
Host smart-6e60ad91-2dd9-47bf-86d1-99b492214b98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367922887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1367922887
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2779112146
Short name T278
Test name
Test status
Simulation time 14134474157 ps
CPU time 64 seconds
Started May 07 03:30:57 PM PDT 24
Finished May 07 03:32:02 PM PDT 24
Peak memory 215824 kb
Host smart-41ba8a71-6f68-4f44-ad25-0ee02d3950db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779112146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2779112146
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.317215564
Short name T203
Test name
Test status
Simulation time 9321346112 ps
CPU time 19.19 seconds
Started May 07 03:30:58 PM PDT 24
Finished May 07 03:31:18 PM PDT 24
Peak memory 212360 kb
Host smart-410f956e-8a01-476f-9f75-ef795e9aa584
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=317215564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.317215564
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.4266532661
Short name T215
Test name
Test status
Simulation time 2730473608 ps
CPU time 44.48 seconds
Started May 07 03:30:59 PM PDT 24
Finished May 07 03:31:44 PM PDT 24
Peak memory 218384 kb
Host smart-4b42f666-a1ff-4b0a-a405-18e835a55629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266532661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.4266532661
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.4174965538
Short name T324
Test name
Test status
Simulation time 64364910848 ps
CPU time 73.64 seconds
Started May 07 03:30:58 PM PDT 24
Finished May 07 03:32:12 PM PDT 24
Peak memory 219508 kb
Host smart-f4670fb2-da8a-4f5f-b6ab-3f5834defafe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174965538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.4174965538
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.115556479
Short name T261
Test name
Test status
Simulation time 3309496651 ps
CPU time 27.74 seconds
Started May 07 03:31:03 PM PDT 24
Finished May 07 03:31:32 PM PDT 24
Peak memory 212504 kb
Host smart-723400a0-01a0-4df0-81e7-7f38239cfd6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115556479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.115556479
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3610698019
Short name T195
Test name
Test status
Simulation time 4639023753 ps
CPU time 280.61 seconds
Started May 07 03:31:03 PM PDT 24
Finished May 07 03:35:45 PM PDT 24
Peak memory 238424 kb
Host smart-0a4d627e-2e21-4963-ab07-d945eb986cf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610698019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3610698019
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1849138883
Short name T2
Test name
Test status
Simulation time 339773811 ps
CPU time 19.2 seconds
Started May 07 03:31:04 PM PDT 24
Finished May 07 03:31:25 PM PDT 24
Peak memory 216400 kb
Host smart-1993c979-f022-434e-9691-910310c43cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849138883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1849138883
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4065222048
Short name T1
Test name
Test status
Simulation time 2804861448 ps
CPU time 26.67 seconds
Started May 07 03:31:04 PM PDT 24
Finished May 07 03:31:31 PM PDT 24
Peak memory 213204 kb
Host smart-8c9f6404-9c18-4dd9-84d6-81ac3b110466
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4065222048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.4065222048
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.971718155
Short name T327
Test name
Test status
Simulation time 17859850514 ps
CPU time 43.43 seconds
Started May 07 03:31:04 PM PDT 24
Finished May 07 03:31:48 PM PDT 24
Peak memory 217612 kb
Host smart-c3a36e80-9bd9-4f0a-b335-172a1f7955a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971718155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.971718155
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.206984265
Short name T115
Test name
Test status
Simulation time 14105386640 ps
CPU time 51.21 seconds
Started May 07 03:31:03 PM PDT 24
Finished May 07 03:31:55 PM PDT 24
Peak memory 218396 kb
Host smart-a3e58b0b-14f6-4db3-ba8d-1cc5b07632e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206984265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.206984265
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1982218385
Short name T351
Test name
Test status
Simulation time 345555778 ps
CPU time 8.56 seconds
Started May 07 03:31:10 PM PDT 24
Finished May 07 03:31:20 PM PDT 24
Peak memory 211872 kb
Host smart-f68d1773-82e9-48f5-b28f-b1f059ea4040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982218385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1982218385
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.811310535
Short name T207
Test name
Test status
Simulation time 107692768611 ps
CPU time 594.58 seconds
Started May 07 03:31:09 PM PDT 24
Finished May 07 03:41:05 PM PDT 24
Peak memory 234648 kb
Host smart-2f373af8-8f75-412c-8145-2d795537c6f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811310535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.811310535
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.650597080
Short name T22
Test name
Test status
Simulation time 22948668002 ps
CPU time 54.11 seconds
Started May 07 03:31:09 PM PDT 24
Finished May 07 03:32:05 PM PDT 24
Peak memory 214656 kb
Host smart-01e6152c-66da-4361-9f76-445838cd5c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650597080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.650597080
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2301274269
Short name T344
Test name
Test status
Simulation time 1268434644 ps
CPU time 17.77 seconds
Started May 07 03:31:11 PM PDT 24
Finished May 07 03:31:30 PM PDT 24
Peak memory 211820 kb
Host smart-d0a4c1ac-1229-405a-9223-b8fa12ffa763
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2301274269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2301274269
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2748464143
Short name T314
Test name
Test status
Simulation time 1545714952 ps
CPU time 19.78 seconds
Started May 07 03:31:05 PM PDT 24
Finished May 07 03:31:25 PM PDT 24
Peak memory 216900 kb
Host smart-ae177b26-d2df-410e-b824-495dd7a5db69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748464143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2748464143
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2192161381
Short name T40
Test name
Test status
Simulation time 19317614215 ps
CPU time 52.07 seconds
Started May 07 03:31:09 PM PDT 24
Finished May 07 03:32:03 PM PDT 24
Peak memory 218848 kb
Host smart-5d4f5064-742b-4991-9423-90a2cb5e0b56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192161381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2192161381
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1599225735
Short name T32
Test name
Test status
Simulation time 12243100255 ps
CPU time 23.63 seconds
Started May 07 03:29:40 PM PDT 24
Finished May 07 03:30:04 PM PDT 24
Peak memory 211880 kb
Host smart-1adc3598-feb3-4f00-b580-f7954986af38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599225735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1599225735
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3264676487
Short name T269
Test name
Test status
Simulation time 36574870565 ps
CPU time 378.87 seconds
Started May 07 03:29:37 PM PDT 24
Finished May 07 03:35:57 PM PDT 24
Peak memory 217320 kb
Host smart-2273f0ce-f8e9-4d6f-b316-39eb9921987d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264676487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3264676487
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1849189941
Short name T350
Test name
Test status
Simulation time 1386173288 ps
CPU time 28.6 seconds
Started May 07 03:29:40 PM PDT 24
Finished May 07 03:30:09 PM PDT 24
Peak memory 214296 kb
Host smart-55d3e1eb-0b4d-4bec-ae96-17947bbb6528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849189941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1849189941
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3925578472
Short name T139
Test name
Test status
Simulation time 28911920082 ps
CPU time 24.42 seconds
Started May 07 03:29:31 PM PDT 24
Finished May 07 03:29:56 PM PDT 24
Peak memory 212268 kb
Host smart-44e87bea-be73-44df-9917-9dfa0cb4b9b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3925578472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3925578472
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.4248349620
Short name T29
Test name
Test status
Simulation time 1407388339 ps
CPU time 232.27 seconds
Started May 07 03:29:37 PM PDT 24
Finished May 07 03:33:31 PM PDT 24
Peak memory 237516 kb
Host smart-c2cc74b3-1a58-459c-97b0-38b033509fdf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248349620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.4248349620
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3899722821
Short name T153
Test name
Test status
Simulation time 3302690566 ps
CPU time 43 seconds
Started May 07 03:29:32 PM PDT 24
Finished May 07 03:30:16 PM PDT 24
Peak memory 217464 kb
Host smart-f340f8af-59f8-453e-980e-bdc4e3909e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899722821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3899722821
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.4231330912
Short name T303
Test name
Test status
Simulation time 356401918 ps
CPU time 23.68 seconds
Started May 07 03:29:32 PM PDT 24
Finished May 07 03:29:57 PM PDT 24
Peak memory 217604 kb
Host smart-187a01f7-ad9a-4c26-b6e1-dad21af9f36b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231330912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.4231330912
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1542419064
Short name T146
Test name
Test status
Simulation time 8537924508 ps
CPU time 21.1 seconds
Started May 07 03:31:10 PM PDT 24
Finished May 07 03:31:33 PM PDT 24
Peak memory 211968 kb
Host smart-a2df3065-8875-4605-a547-090d6c1ff978
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542419064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1542419064
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1641264144
Short name T194
Test name
Test status
Simulation time 44470395609 ps
CPU time 461.9 seconds
Started May 07 03:31:10 PM PDT 24
Finished May 07 03:38:53 PM PDT 24
Peak memory 225172 kb
Host smart-01c252e1-4f7a-4cae-ae49-a16c7c2d2941
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641264144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1641264144
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1839352207
Short name T177
Test name
Test status
Simulation time 6069282296 ps
CPU time 27.4 seconds
Started May 07 03:31:09 PM PDT 24
Finished May 07 03:31:37 PM PDT 24
Peak memory 213912 kb
Host smart-7e9179f6-0ce2-4a45-8c5f-811d3dfcbe39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839352207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1839352207
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1390160969
Short name T301
Test name
Test status
Simulation time 1355936229 ps
CPU time 12.55 seconds
Started May 07 03:31:10 PM PDT 24
Finished May 07 03:31:24 PM PDT 24
Peak memory 211776 kb
Host smart-f5bf3ebe-66f7-415f-ac3a-dc28938aaf26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1390160969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1390160969
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3368612867
Short name T358
Test name
Test status
Simulation time 17780061727 ps
CPU time 50.91 seconds
Started May 07 03:31:08 PM PDT 24
Finished May 07 03:32:00 PM PDT 24
Peak memory 218100 kb
Host smart-f69fa9c8-bbf3-462c-b238-5d1d31b84e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368612867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3368612867
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2494398194
Short name T135
Test name
Test status
Simulation time 16836429835 ps
CPU time 37.34 seconds
Started May 07 03:31:09 PM PDT 24
Finished May 07 03:31:47 PM PDT 24
Peak memory 213364 kb
Host smart-8896a218-a331-4ada-8e61-7cbbb84c0d9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494398194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2494398194
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.288799213
Short name T343
Test name
Test status
Simulation time 26072866865 ps
CPU time 366.91 seconds
Started May 07 03:31:19 PM PDT 24
Finished May 07 03:37:26 PM PDT 24
Peak memory 241328 kb
Host smart-df1834a2-eba8-4bc5-9bae-7e24374c40c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288799213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.288799213
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.577209081
Short name T258
Test name
Test status
Simulation time 658256121 ps
CPU time 23.43 seconds
Started May 07 03:31:14 PM PDT 24
Finished May 07 03:31:38 PM PDT 24
Peak memory 214220 kb
Host smart-297bc507-5070-4a30-a5ae-f51a04d875fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577209081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.577209081
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1697169372
Short name T214
Test name
Test status
Simulation time 1070167212 ps
CPU time 11.72 seconds
Started May 07 03:31:18 PM PDT 24
Finished May 07 03:31:30 PM PDT 24
Peak memory 213060 kb
Host smart-70d4e3f8-46f7-4e4d-9f61-650c5e0f7b57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1697169372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1697169372
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2190180279
Short name T158
Test name
Test status
Simulation time 6285859027 ps
CPU time 68.59 seconds
Started May 07 03:31:11 PM PDT 24
Finished May 07 03:32:21 PM PDT 24
Peak memory 215852 kb
Host smart-36da8ad1-c4b6-41f1-b28c-a11456e9f0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190180279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2190180279
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1046628204
Short name T197
Test name
Test status
Simulation time 1058162972 ps
CPU time 39.6 seconds
Started May 07 03:31:12 PM PDT 24
Finished May 07 03:31:52 PM PDT 24
Peak memory 219816 kb
Host smart-23d8258c-acca-476c-a925-c4f9cee11b4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046628204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1046628204
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1444425334
Short name T308
Test name
Test status
Simulation time 8371667694 ps
CPU time 31.18 seconds
Started May 07 03:31:26 PM PDT 24
Finished May 07 03:31:58 PM PDT 24
Peak memory 212712 kb
Host smart-2b6404c1-5825-4206-9735-b3b27b36d532
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444425334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1444425334
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.507797176
Short name T354
Test name
Test status
Simulation time 182609541553 ps
CPU time 398.95 seconds
Started May 07 03:31:20 PM PDT 24
Finished May 07 03:38:00 PM PDT 24
Peak memory 234392 kb
Host smart-a0bf7fc3-e128-4031-86c3-490b4ba6ecf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507797176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.507797176
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.804761021
Short name T300
Test name
Test status
Simulation time 16425084856 ps
CPU time 68.59 seconds
Started May 07 03:31:20 PM PDT 24
Finished May 07 03:32:30 PM PDT 24
Peak memory 214576 kb
Host smart-0fdaec73-4393-4919-bf32-431073352d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804761021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.804761021
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1646683409
Short name T164
Test name
Test status
Simulation time 636734527 ps
CPU time 9.89 seconds
Started May 07 03:31:19 PM PDT 24
Finished May 07 03:31:29 PM PDT 24
Peak memory 212972 kb
Host smart-49e54613-0815-472a-9d32-1597edc60785
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1646683409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1646683409
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1331472007
Short name T147
Test name
Test status
Simulation time 509148524 ps
CPU time 20.17 seconds
Started May 07 03:31:15 PM PDT 24
Finished May 07 03:31:36 PM PDT 24
Peak memory 217748 kb
Host smart-a3c1d6e2-fa21-4093-92ef-7e1de8238649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331472007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1331472007
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3551087783
Short name T206
Test name
Test status
Simulation time 3426371749 ps
CPU time 54.06 seconds
Started May 07 03:31:25 PM PDT 24
Finished May 07 03:32:19 PM PDT 24
Peak memory 219952 kb
Host smart-0cb952cc-ef5c-477f-b817-9533d5b80329
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551087783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3551087783
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.635324192
Short name T282
Test name
Test status
Simulation time 2302062482 ps
CPU time 16.24 seconds
Started May 07 03:31:20 PM PDT 24
Finished May 07 03:31:37 PM PDT 24
Peak memory 211976 kb
Host smart-7c4c9f78-9c65-48e8-8cd4-438cc6e26f22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635324192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.635324192
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1384503412
Short name T272
Test name
Test status
Simulation time 16197397904 ps
CPU time 220.86 seconds
Started May 07 03:31:21 PM PDT 24
Finished May 07 03:35:02 PM PDT 24
Peak memory 239632 kb
Host smart-fe965793-026f-466c-99bb-13a2038f4848
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384503412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1384503412
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3364101866
Short name T361
Test name
Test status
Simulation time 5233823049 ps
CPU time 49.01 seconds
Started May 07 03:31:26 PM PDT 24
Finished May 07 03:32:16 PM PDT 24
Peak memory 215760 kb
Host smart-8a6c1798-2256-4139-a0fd-747b32c74618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364101866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3364101866
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3510669429
Short name T133
Test name
Test status
Simulation time 3130721581 ps
CPU time 28.45 seconds
Started May 07 03:31:26 PM PDT 24
Finished May 07 03:31:55 PM PDT 24
Peak memory 211924 kb
Host smart-11b6cad4-11d1-4927-ac70-8ea8f9eac070
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3510669429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3510669429
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.756050443
Short name T226
Test name
Test status
Simulation time 687392997 ps
CPU time 19.74 seconds
Started May 07 03:31:17 PM PDT 24
Finished May 07 03:31:38 PM PDT 24
Peak memory 214244 kb
Host smart-d30a55b0-c757-4cf7-810d-e0ba0ac2dd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756050443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.756050443
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3723227532
Short name T275
Test name
Test status
Simulation time 12070865558 ps
CPU time 38.73 seconds
Started May 07 03:31:21 PM PDT 24
Finished May 07 03:32:01 PM PDT 24
Peak memory 219412 kb
Host smart-8f1f2e06-69b8-4b57-b87b-9755fcb3ad9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723227532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3723227532
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.983422230
Short name T339
Test name
Test status
Simulation time 16608372367 ps
CPU time 31.76 seconds
Started May 07 03:31:23 PM PDT 24
Finished May 07 03:31:55 PM PDT 24
Peak memory 212760 kb
Host smart-69cab690-064f-4b4f-b0d5-3e60af6ba583
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983422230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.983422230
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.68066890
Short name T328
Test name
Test status
Simulation time 1257182972 ps
CPU time 110.62 seconds
Started May 07 03:31:26 PM PDT 24
Finished May 07 03:33:17 PM PDT 24
Peak memory 240488 kb
Host smart-be290e37-a99d-4f64-be3a-179a4be9b3e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68066890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_co
rrupt_sig_fatal_chk.68066890
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3581219835
Short name T255
Test name
Test status
Simulation time 5176744351 ps
CPU time 52.14 seconds
Started May 07 03:31:23 PM PDT 24
Finished May 07 03:32:16 PM PDT 24
Peak memory 213544 kb
Host smart-a90e5eb7-cb50-45b7-8350-d6699c878c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581219835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3581219835
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3016419697
Short name T106
Test name
Test status
Simulation time 14213275399 ps
CPU time 31.77 seconds
Started May 07 03:31:26 PM PDT 24
Finished May 07 03:31:59 PM PDT 24
Peak memory 211856 kb
Host smart-d99fb53c-d9ee-49b7-87ef-3cb48d82c52c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3016419697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3016419697
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.450928427
Short name T138
Test name
Test status
Simulation time 12581610322 ps
CPU time 49.35 seconds
Started May 07 03:31:26 PM PDT 24
Finished May 07 03:32:16 PM PDT 24
Peak memory 217968 kb
Host smart-1dcdfe31-528b-430f-8a04-bae663cd194b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450928427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.450928427
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.169252246
Short name T47
Test name
Test status
Simulation time 3006951052 ps
CPU time 29.52 seconds
Started May 07 03:31:23 PM PDT 24
Finished May 07 03:31:53 PM PDT 24
Peak memory 219968 kb
Host smart-13c70d69-4ff6-4401-a93a-4a3825e262f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169252246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.169252246
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3048320147
Short name T292
Test name
Test status
Simulation time 2865086006 ps
CPU time 25 seconds
Started May 07 03:31:23 PM PDT 24
Finished May 07 03:31:49 PM PDT 24
Peak memory 212444 kb
Host smart-a5b6fe2b-57c2-46cb-9e1f-30acd50634c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048320147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3048320147
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.872346353
Short name T43
Test name
Test status
Simulation time 10823932279 ps
CPU time 362.37 seconds
Started May 07 03:31:24 PM PDT 24
Finished May 07 03:37:27 PM PDT 24
Peak memory 217636 kb
Host smart-5e6dcb20-98ce-4f8e-a21c-fb9aa56b8886
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872346353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.872346353
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3009161574
Short name T168
Test name
Test status
Simulation time 30128471633 ps
CPU time 41.71 seconds
Started May 07 03:31:24 PM PDT 24
Finished May 07 03:32:07 PM PDT 24
Peak memory 215724 kb
Host smart-49460fc9-f4bd-48f8-b3e4-8468cae30a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009161574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3009161574
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2825666366
Short name T310
Test name
Test status
Simulation time 11482536468 ps
CPU time 26.61 seconds
Started May 07 03:31:23 PM PDT 24
Finished May 07 03:31:50 PM PDT 24
Peak memory 211916 kb
Host smart-d6c8465b-bc98-4c86-82eb-3aa1c2a66359
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2825666366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2825666366
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.817137888
Short name T366
Test name
Test status
Simulation time 7056230812 ps
CPU time 69.28 seconds
Started May 07 03:31:26 PM PDT 24
Finished May 07 03:32:36 PM PDT 24
Peak memory 218392 kb
Host smart-573d1715-3641-4ffe-abea-e0b3332a1a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817137888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.817137888
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.4141757456
Short name T253
Test name
Test status
Simulation time 70393067642 ps
CPU time 145.29 seconds
Started May 07 03:31:25 PM PDT 24
Finished May 07 03:33:51 PM PDT 24
Peak memory 220872 kb
Host smart-3ae7eeef-f2f1-48af-b279-8d74437810b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141757456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.4141757456
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.4119807416
Short name T248
Test name
Test status
Simulation time 688360921 ps
CPU time 8.44 seconds
Started May 07 03:31:29 PM PDT 24
Finished May 07 03:31:38 PM PDT 24
Peak memory 211844 kb
Host smart-1e72ace7-26ff-40f3-ab73-fbf2aafb523c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119807416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.4119807416
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1051020802
Short name T188
Test name
Test status
Simulation time 209506600036 ps
CPU time 566.01 seconds
Started May 07 03:31:29 PM PDT 24
Finished May 07 03:40:56 PM PDT 24
Peak memory 239384 kb
Host smart-bf62b697-d577-43ff-8186-9dd09a2bfe6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051020802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1051020802
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2026974723
Short name T39
Test name
Test status
Simulation time 4001306960 ps
CPU time 44.58 seconds
Started May 07 03:31:29 PM PDT 24
Finished May 07 03:32:15 PM PDT 24
Peak memory 215372 kb
Host smart-d5812078-2402-4cf7-9caa-3021a3a24dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026974723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2026974723
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3905858693
Short name T345
Test name
Test status
Simulation time 11620591948 ps
CPU time 33.11 seconds
Started May 07 03:31:29 PM PDT 24
Finished May 07 03:32:04 PM PDT 24
Peak memory 212376 kb
Host smart-a78304a3-cd91-4dec-a2b9-08cd98297a29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3905858693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3905858693
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.791211173
Short name T296
Test name
Test status
Simulation time 7543865153 ps
CPU time 65.38 seconds
Started May 07 03:31:29 PM PDT 24
Finished May 07 03:32:35 PM PDT 24
Peak memory 217772 kb
Host smart-2c7d84be-2341-43d5-b4c6-a91950a7a167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791211173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.791211173
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1530702652
Short name T35
Test name
Test status
Simulation time 27605873764 ps
CPU time 99.76 seconds
Started May 07 03:31:29 PM PDT 24
Finished May 07 03:33:10 PM PDT 24
Peak memory 228520 kb
Host smart-fe8e5ab4-dfe8-476b-a92d-f30f6c19a280
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530702652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1530702652
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1462680850
Short name T267
Test name
Test status
Simulation time 2339766631 ps
CPU time 21.49 seconds
Started May 07 03:31:28 PM PDT 24
Finished May 07 03:31:51 PM PDT 24
Peak memory 212440 kb
Host smart-adc5c70c-e110-4641-a218-99f503597350
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462680850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1462680850
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3054413381
Short name T259
Test name
Test status
Simulation time 191387847576 ps
CPU time 401.87 seconds
Started May 07 03:31:32 PM PDT 24
Finished May 07 03:38:14 PM PDT 24
Peak memory 216288 kb
Host smart-cb4edb5a-3dcf-41d2-9abf-ea2db726b974
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054413381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3054413381
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.324034256
Short name T287
Test name
Test status
Simulation time 17711294221 ps
CPU time 69.06 seconds
Started May 07 03:31:31 PM PDT 24
Finished May 07 03:32:41 PM PDT 24
Peak memory 215336 kb
Host smart-63cf4fb9-1001-4578-b552-c036007028e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324034256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.324034256
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2857066814
Short name T7
Test name
Test status
Simulation time 4249737386 ps
CPU time 34.42 seconds
Started May 07 03:31:28 PM PDT 24
Finished May 07 03:32:03 PM PDT 24
Peak memory 211928 kb
Host smart-c98fc31e-033b-4f2b-8917-ff0a6dc5b64c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2857066814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2857066814
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2460139579
Short name T9
Test name
Test status
Simulation time 46709653144 ps
CPU time 62.61 seconds
Started May 07 03:31:31 PM PDT 24
Finished May 07 03:32:34 PM PDT 24
Peak memory 216296 kb
Host smart-baf73922-8a56-4c5d-94af-30182438686f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460139579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2460139579
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1698308881
Short name T187
Test name
Test status
Simulation time 23370207953 ps
CPU time 62.88 seconds
Started May 07 03:31:28 PM PDT 24
Finished May 07 03:32:32 PM PDT 24
Peak memory 218620 kb
Host smart-8fc63089-7bfd-49b3-a5e6-ad42fbb43fb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698308881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1698308881
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2039565206
Short name T346
Test name
Test status
Simulation time 27190029694 ps
CPU time 29.64 seconds
Started May 07 03:31:30 PM PDT 24
Finished May 07 03:32:01 PM PDT 24
Peak memory 212832 kb
Host smart-5916abf0-fa90-40f7-8ed6-bdbd780c096c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039565206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2039565206
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3277739932
Short name T337
Test name
Test status
Simulation time 129375791748 ps
CPU time 325.82 seconds
Started May 07 03:31:28 PM PDT 24
Finished May 07 03:36:55 PM PDT 24
Peak memory 237364 kb
Host smart-96bab8fa-fda5-4aa8-8cc9-7b4fe067540d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277739932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3277739932
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.811877604
Short name T38
Test name
Test status
Simulation time 7474610085 ps
CPU time 63.44 seconds
Started May 07 03:31:31 PM PDT 24
Finished May 07 03:32:36 PM PDT 24
Peak memory 215568 kb
Host smart-8ef89010-3e89-4e8b-b032-b785c962890d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811877604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.811877604
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1827216921
Short name T240
Test name
Test status
Simulation time 2419969795 ps
CPU time 14.18 seconds
Started May 07 03:31:31 PM PDT 24
Finished May 07 03:31:46 PM PDT 24
Peak memory 212996 kb
Host smart-14e110fe-0ddd-4b4a-a37d-17857852662c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1827216921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1827216921
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.65310249
Short name T173
Test name
Test status
Simulation time 14933785185 ps
CPU time 35.96 seconds
Started May 07 03:31:28 PM PDT 24
Finished May 07 03:32:05 PM PDT 24
Peak memory 218820 kb
Host smart-be96b9ae-80c8-448c-a4a8-48d287dacf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65310249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.65310249
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3300569014
Short name T5
Test name
Test status
Simulation time 2900937754 ps
CPU time 42.12 seconds
Started May 07 03:31:28 PM PDT 24
Finished May 07 03:32:11 PM PDT 24
Peak memory 218588 kb
Host smart-a570cfbf-a9ca-4eb7-8a54-9c10c40a6923
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300569014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3300569014
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2345265403
Short name T291
Test name
Test status
Simulation time 514823135 ps
CPU time 9.98 seconds
Started May 07 03:31:36 PM PDT 24
Finished May 07 03:31:47 PM PDT 24
Peak memory 211824 kb
Host smart-66292d6e-4b3e-4873-854b-de13606c550f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345265403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2345265403
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1780813251
Short name T252
Test name
Test status
Simulation time 96180024755 ps
CPU time 451.91 seconds
Started May 07 03:31:34 PM PDT 24
Finished May 07 03:39:06 PM PDT 24
Peak memory 229324 kb
Host smart-5869e6b2-aec8-417b-a4ff-e8eed351b200
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780813251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1780813251
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2302953243
Short name T289
Test name
Test status
Simulation time 81653524374 ps
CPU time 52.34 seconds
Started May 07 03:31:33 PM PDT 24
Finished May 07 03:32:26 PM PDT 24
Peak memory 216536 kb
Host smart-c83597b7-ab08-4a90-88a9-7461aa400bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302953243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2302953243
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3279019189
Short name T227
Test name
Test status
Simulation time 12199534844 ps
CPU time 23.96 seconds
Started May 07 03:31:33 PM PDT 24
Finished May 07 03:31:58 PM PDT 24
Peak memory 212392 kb
Host smart-2ec30f80-4522-436c-9529-7cbb4cc6cc42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3279019189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3279019189
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3032168400
Short name T156
Test name
Test status
Simulation time 14008479719 ps
CPU time 32.38 seconds
Started May 07 03:31:31 PM PDT 24
Finished May 07 03:32:04 PM PDT 24
Peak memory 218580 kb
Host smart-e87239c8-942f-4220-8e1f-7614304d0ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032168400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3032168400
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1295331059
Short name T341
Test name
Test status
Simulation time 6549809918 ps
CPU time 36.55 seconds
Started May 07 03:31:31 PM PDT 24
Finished May 07 03:32:09 PM PDT 24
Peak memory 219820 kb
Host smart-2b0e5fcd-e6d0-44ca-a1ec-95796b24fe4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295331059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1295331059
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.212308116
Short name T251
Test name
Test status
Simulation time 5022796549 ps
CPU time 24.99 seconds
Started May 07 03:29:39 PM PDT 24
Finished May 07 03:30:05 PM PDT 24
Peak memory 212792 kb
Host smart-2c27d12f-d302-4679-9826-ba8c58cd8ae6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212308116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.212308116
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3567733472
Short name T246
Test name
Test status
Simulation time 19181554817 ps
CPU time 129.26 seconds
Started May 07 03:29:40 PM PDT 24
Finished May 07 03:31:50 PM PDT 24
Peak memory 216796 kb
Host smart-7677f81c-a064-4f1b-a994-32187bd00d63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567733472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3567733472
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2018500521
Short name T17
Test name
Test status
Simulation time 1435327419 ps
CPU time 19.1 seconds
Started May 07 03:29:37 PM PDT 24
Finished May 07 03:29:57 PM PDT 24
Peak memory 215436 kb
Host smart-5f6c3b15-785e-4740-8ddc-3502519ce85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018500521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2018500521
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3036403529
Short name T307
Test name
Test status
Simulation time 1319080988 ps
CPU time 18.07 seconds
Started May 07 03:29:36 PM PDT 24
Finished May 07 03:29:55 PM PDT 24
Peak memory 212008 kb
Host smart-c941a266-e71a-449b-9cbe-9fac497f1c7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3036403529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3036403529
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2612602935
Short name T46
Test name
Test status
Simulation time 8576162366 ps
CPU time 45.2 seconds
Started May 07 03:29:36 PM PDT 24
Finished May 07 03:30:22 PM PDT 24
Peak memory 218988 kb
Host smart-61560118-583a-47a5-b729-a76c7e0740ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612602935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2612602935
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.786287172
Short name T349
Test name
Test status
Simulation time 23034384426 ps
CPU time 228.48 seconds
Started May 07 03:29:40 PM PDT 24
Finished May 07 03:33:29 PM PDT 24
Peak memory 228084 kb
Host smart-3f437e57-030b-459e-8d3f-c660f25d2a08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786287172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.786287172
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1077401171
Short name T202
Test name
Test status
Simulation time 9809194997 ps
CPU time 22.83 seconds
Started May 07 03:29:41 PM PDT 24
Finished May 07 03:30:05 PM PDT 24
Peak memory 211952 kb
Host smart-e06c80af-5dfe-454c-a2e0-2af80b382d9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077401171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1077401171
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3052160530
Short name T25
Test name
Test status
Simulation time 118103283047 ps
CPU time 730.22 seconds
Started May 07 03:29:39 PM PDT 24
Finished May 07 03:41:50 PM PDT 24
Peak memory 238856 kb
Host smart-5de04e96-9bb6-4649-9d6c-04c693b95819
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052160530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3052160530
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1377515843
Short name T223
Test name
Test status
Simulation time 8252552331 ps
CPU time 64.57 seconds
Started May 07 03:29:40 PM PDT 24
Finished May 07 03:30:46 PM PDT 24
Peak memory 216148 kb
Host smart-588fb648-c7b1-407f-867c-83ede667a87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377515843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1377515843
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1661379492
Short name T104
Test name
Test status
Simulation time 8514727430 ps
CPU time 34.38 seconds
Started May 07 03:29:40 PM PDT 24
Finished May 07 03:30:15 PM PDT 24
Peak memory 211980 kb
Host smart-64a26de4-cdf7-42c5-b9e9-e166abe1553a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1661379492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1661379492
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.235487569
Short name T148
Test name
Test status
Simulation time 752739497 ps
CPU time 19.26 seconds
Started May 07 03:29:36 PM PDT 24
Finished May 07 03:29:56 PM PDT 24
Peak memory 217396 kb
Host smart-df524b9e-623d-40b9-bdf1-517e9ec74268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235487569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.235487569
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2392213755
Short name T332
Test name
Test status
Simulation time 6101815390 ps
CPU time 17.43 seconds
Started May 07 03:29:38 PM PDT 24
Finished May 07 03:29:56 PM PDT 24
Peak memory 214584 kb
Host smart-223c61b7-de8a-4fd4-b7f9-abe3210ec0f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392213755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2392213755
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.4200450937
Short name T190
Test name
Test status
Simulation time 6248598579 ps
CPU time 18.44 seconds
Started May 07 03:29:39 PM PDT 24
Finished May 07 03:29:59 PM PDT 24
Peak memory 211984 kb
Host smart-734a09b7-9ad8-4a68-8612-263d032cd06a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200450937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.4200450937
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2678295734
Short name T264
Test name
Test status
Simulation time 21083090485 ps
CPU time 191.29 seconds
Started May 07 03:29:38 PM PDT 24
Finished May 07 03:32:50 PM PDT 24
Peak memory 237320 kb
Host smart-e0924d4c-d9cb-42d4-b083-c1e620a84f9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678295734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2678295734
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1486009225
Short name T295
Test name
Test status
Simulation time 72921196625 ps
CPU time 58.86 seconds
Started May 07 03:29:41 PM PDT 24
Finished May 07 03:30:41 PM PDT 24
Peak memory 215744 kb
Host smart-b68dd2ad-1e85-4afd-b56f-b191f75afb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486009225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1486009225
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3358345593
Short name T270
Test name
Test status
Simulation time 262268651 ps
CPU time 11.96 seconds
Started May 07 03:29:42 PM PDT 24
Finished May 07 03:29:54 PM PDT 24
Peak memory 212832 kb
Host smart-a45dd4ab-7543-4ab5-8787-0d48464a3c04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3358345593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3358345593
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3798267901
Short name T262
Test name
Test status
Simulation time 692183191 ps
CPU time 19.77 seconds
Started May 07 03:29:41 PM PDT 24
Finished May 07 03:30:02 PM PDT 24
Peak memory 217556 kb
Host smart-ed9f6771-232a-4136-9661-8b9ce07e8f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798267901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3798267901
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3391941871
Short name T356
Test name
Test status
Simulation time 5837048346 ps
CPU time 84.9 seconds
Started May 07 03:29:40 PM PDT 24
Finished May 07 03:31:06 PM PDT 24
Peak memory 228700 kb
Host smart-03457b0a-c1cd-4ba7-8900-a271cf4792b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391941871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3391941871
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2193132831
Short name T313
Test name
Test status
Simulation time 170831459 ps
CPU time 8.42 seconds
Started May 07 03:29:45 PM PDT 24
Finished May 07 03:29:54 PM PDT 24
Peak memory 211812 kb
Host smart-36da25cd-01bc-4827-bc74-def26321c18d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193132831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2193132831
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2277718331
Short name T24
Test name
Test status
Simulation time 34281531888 ps
CPU time 390.2 seconds
Started May 07 03:29:44 PM PDT 24
Finished May 07 03:36:14 PM PDT 24
Peak memory 240404 kb
Host smart-0868d715-b2c8-435a-9d53-55b26473a0ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277718331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2277718331
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1637879336
Short name T294
Test name
Test status
Simulation time 31981719844 ps
CPU time 65.11 seconds
Started May 07 03:29:47 PM PDT 24
Finished May 07 03:30:53 PM PDT 24
Peak memory 215640 kb
Host smart-d75b8d69-dbfa-45ad-9eb1-67212eceaaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637879336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1637879336
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3631921140
Short name T4
Test name
Test status
Simulation time 3557075654 ps
CPU time 30.38 seconds
Started May 07 03:29:39 PM PDT 24
Finished May 07 03:30:10 PM PDT 24
Peak memory 212996 kb
Host smart-89637262-bae6-4fe7-8bc1-26a782d34023
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3631921140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3631921140
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3135960517
Short name T59
Test name
Test status
Simulation time 695270742 ps
CPU time 20.63 seconds
Started May 07 03:29:39 PM PDT 24
Finished May 07 03:30:00 PM PDT 24
Peak memory 217676 kb
Host smart-41a8137a-7920-4541-ae0e-2e2be64d4f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135960517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3135960517
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3627926936
Short name T234
Test name
Test status
Simulation time 1643025877 ps
CPU time 11.22 seconds
Started May 07 03:29:46 PM PDT 24
Finished May 07 03:29:58 PM PDT 24
Peak memory 211848 kb
Host smart-98f0339b-7d4a-4110-bd36-9380117239a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627926936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3627926936
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1030764162
Short name T196
Test name
Test status
Simulation time 115910690824 ps
CPU time 549.59 seconds
Started May 07 03:29:44 PM PDT 24
Finished May 07 03:38:55 PM PDT 24
Peak memory 226328 kb
Host smart-e0789b3a-1718-4359-9a5f-0b0c65aae16b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030764162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1030764162
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2071097316
Short name T174
Test name
Test status
Simulation time 42726613929 ps
CPU time 57.1 seconds
Started May 07 03:29:47 PM PDT 24
Finished May 07 03:30:44 PM PDT 24
Peak memory 216816 kb
Host smart-da4c8444-d11d-4c94-8697-d3941c5c0097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071097316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2071097316
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4123164053
Short name T224
Test name
Test status
Simulation time 666963881 ps
CPU time 10.29 seconds
Started May 07 03:29:47 PM PDT 24
Finished May 07 03:29:58 PM PDT 24
Peak memory 213096 kb
Host smart-94a80d99-897e-4b38-a8f4-e69ab6013908
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4123164053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4123164053
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2632994989
Short name T250
Test name
Test status
Simulation time 21204013783 ps
CPU time 52.02 seconds
Started May 07 03:29:44 PM PDT 24
Finished May 07 03:30:37 PM PDT 24
Peak memory 218792 kb
Host smart-da7e95a1-ff87-4712-9204-4f5caeaba3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632994989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2632994989
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.960114352
Short name T211
Test name
Test status
Simulation time 361643836 ps
CPU time 19.9 seconds
Started May 07 03:29:44 PM PDT 24
Finished May 07 03:30:05 PM PDT 24
Peak memory 218080 kb
Host smart-61bc7655-2227-449a-b3fe-322820449020
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960114352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.960114352
Directory /workspace/9.rom_ctrl_stress_all/latest
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