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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.54 96.97 93.01 97.88 100.00 98.69 97.88 98.37


Total test records in report: 455
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T309 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3793931049 May 09 02:44:31 PM PDT 24 May 09 02:52:54 PM PDT 24 51194758502 ps
T310 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2948655656 May 09 02:44:43 PM PDT 24 May 09 02:53:25 PM PDT 24 112206372005 ps
T311 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.38525069 May 09 02:45:27 PM PDT 24 May 09 02:45:49 PM PDT 24 1376223770 ps
T312 /workspace/coverage/default/17.rom_ctrl_alert_test.1695388691 May 09 02:44:21 PM PDT 24 May 09 02:44:44 PM PDT 24 2341690619 ps
T313 /workspace/coverage/default/8.rom_ctrl_stress_all.135403067 May 09 02:43:55 PM PDT 24 May 09 02:45:11 PM PDT 24 2508927527 ps
T314 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2933592395 May 09 02:44:47 PM PDT 24 May 09 02:49:12 PM PDT 24 11675265115 ps
T315 /workspace/coverage/default/18.rom_ctrl_alert_test.170900365 May 09 02:44:13 PM PDT 24 May 09 02:44:25 PM PDT 24 2352917122 ps
T316 /workspace/coverage/default/23.rom_ctrl_stress_all.3302253100 May 09 02:44:22 PM PDT 24 May 09 02:46:23 PM PDT 24 10650813772 ps
T317 /workspace/coverage/default/13.rom_ctrl_stress_all.1099478117 May 09 02:44:09 PM PDT 24 May 09 02:44:40 PM PDT 24 3660198873 ps
T318 /workspace/coverage/default/1.rom_ctrl_stress_all.2059819117 May 09 02:43:33 PM PDT 24 May 09 02:45:33 PM PDT 24 28877012122 ps
T319 /workspace/coverage/default/27.rom_ctrl_smoke.1114958890 May 09 02:44:34 PM PDT 24 May 09 02:45:10 PM PDT 24 1820527119 ps
T34 /workspace/coverage/default/0.rom_ctrl_sec_cm.24581428 May 09 02:43:34 PM PDT 24 May 09 02:47:48 PM PDT 24 16914046814 ps
T320 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1981957348 May 09 02:44:47 PM PDT 24 May 09 02:48:35 PM PDT 24 12582220622 ps
T321 /workspace/coverage/default/32.rom_ctrl_alert_test.2214819498 May 09 02:44:46 PM PDT 24 May 09 02:45:02 PM PDT 24 1169795313 ps
T322 /workspace/coverage/default/32.rom_ctrl_stress_all.505072091 May 09 02:44:46 PM PDT 24 May 09 02:46:25 PM PDT 24 31739326799 ps
T323 /workspace/coverage/default/5.rom_ctrl_stress_all.3121245918 May 09 02:43:50 PM PDT 24 May 09 02:44:29 PM PDT 24 524819950 ps
T324 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3248957744 May 09 02:43:45 PM PDT 24 May 09 02:44:48 PM PDT 24 31309091738 ps
T325 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.155495408 May 09 02:44:21 PM PDT 24 May 09 02:44:39 PM PDT 24 5531585954 ps
T326 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1937412127 May 09 02:43:46 PM PDT 24 May 09 02:48:30 PM PDT 24 60375099859 ps
T51 /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2521473070 May 09 02:44:22 PM PDT 24 May 09 04:20:01 PM PDT 24 19539061849 ps
T327 /workspace/coverage/default/25.rom_ctrl_smoke.1253053111 May 09 02:44:22 PM PDT 24 May 09 02:45:08 PM PDT 24 6466107350 ps
T328 /workspace/coverage/default/47.rom_ctrl_smoke.1706913934 May 09 02:45:27 PM PDT 24 May 09 02:45:50 PM PDT 24 707239607 ps
T329 /workspace/coverage/default/30.rom_ctrl_smoke.3226457192 May 09 02:44:47 PM PDT 24 May 09 02:45:11 PM PDT 24 1322413981 ps
T330 /workspace/coverage/default/48.rom_ctrl_smoke.3700408246 May 09 02:45:27 PM PDT 24 May 09 02:46:31 PM PDT 24 18389761918 ps
T331 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.942383334 May 09 02:44:53 PM PDT 24 May 09 02:45:46 PM PDT 24 5468343637 ps
T332 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3147747117 May 09 02:45:29 PM PDT 24 May 09 02:47:45 PM PDT 24 1719113852 ps
T333 /workspace/coverage/default/44.rom_ctrl_alert_test.1018124069 May 09 02:45:17 PM PDT 24 May 09 02:45:39 PM PDT 24 3785082505 ps
T334 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3557949932 May 09 02:44:19 PM PDT 24 May 09 02:44:35 PM PDT 24 875049053 ps
T335 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3803229876 May 09 02:44:13 PM PDT 24 May 09 02:44:35 PM PDT 24 1464595218 ps
T336 /workspace/coverage/default/39.rom_ctrl_alert_test.574388076 May 09 02:45:06 PM PDT 24 May 09 02:45:42 PM PDT 24 8710970444 ps
T337 /workspace/coverage/default/5.rom_ctrl_smoke.557096519 May 09 02:43:43 PM PDT 24 May 09 02:44:38 PM PDT 24 18310884812 ps
T338 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3608764863 May 09 02:45:06 PM PDT 24 May 09 02:45:26 PM PDT 24 4287196286 ps
T339 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3477923580 May 09 02:44:53 PM PDT 24 May 09 02:51:56 PM PDT 24 54470616714 ps
T340 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3658927925 May 09 02:43:43 PM PDT 24 May 09 02:44:19 PM PDT 24 2389792075 ps
T341 /workspace/coverage/default/28.rom_ctrl_alert_test.3083763079 May 09 02:44:35 PM PDT 24 May 09 02:45:11 PM PDT 24 8425991044 ps
T342 /workspace/coverage/default/30.rom_ctrl_stress_all.3195165250 May 09 02:44:45 PM PDT 24 May 09 02:46:52 PM PDT 24 25848144674 ps
T343 /workspace/coverage/default/43.rom_ctrl_smoke.4254997170 May 09 02:45:19 PM PDT 24 May 09 02:46:12 PM PDT 24 18772938220 ps
T344 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3597423248 May 09 02:43:59 PM PDT 24 May 09 02:44:49 PM PDT 24 9674661796 ps
T345 /workspace/coverage/default/26.rom_ctrl_smoke.2563714037 May 09 02:44:22 PM PDT 24 May 09 02:45:10 PM PDT 24 17084335495 ps
T346 /workspace/coverage/default/44.rom_ctrl_smoke.3689562051 May 09 02:45:15 PM PDT 24 May 09 02:46:26 PM PDT 24 7317859139 ps
T347 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.530867470 May 09 02:45:16 PM PDT 24 May 09 02:45:57 PM PDT 24 12214974547 ps
T348 /workspace/coverage/default/17.rom_ctrl_smoke.2089236613 May 09 02:44:09 PM PDT 24 May 09 02:44:51 PM PDT 24 4118541486 ps
T349 /workspace/coverage/default/36.rom_ctrl_smoke.3141073019 May 09 02:44:55 PM PDT 24 May 09 02:45:55 PM PDT 24 25582368062 ps
T350 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.10830229 May 09 02:43:58 PM PDT 24 May 09 02:44:51 PM PDT 24 10209943669 ps
T351 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3031860446 May 09 02:43:59 PM PDT 24 May 09 02:52:35 PM PDT 24 52160959763 ps
T352 /workspace/coverage/default/45.rom_ctrl_smoke.2887194237 May 09 02:45:19 PM PDT 24 May 09 02:46:16 PM PDT 24 26927444291 ps
T52 /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2232343539 May 09 02:44:51 PM PDT 24 May 09 03:10:27 PM PDT 24 39549471454 ps
T53 /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2003940861 May 09 02:45:05 PM PDT 24 May 09 03:36:23 PM PDT 24 724376371599 ps
T353 /workspace/coverage/default/9.rom_ctrl_smoke.1391327748 May 09 02:43:56 PM PDT 24 May 09 02:44:19 PM PDT 24 349174842 ps
T354 /workspace/coverage/default/27.rom_ctrl_alert_test.3050354441 May 09 02:44:32 PM PDT 24 May 09 02:45:03 PM PDT 24 3332996608 ps
T355 /workspace/coverage/default/33.rom_ctrl_alert_test.398783541 May 09 02:44:52 PM PDT 24 May 09 02:45:23 PM PDT 24 23209956999 ps
T356 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.412426079 May 09 02:44:43 PM PDT 24 May 09 02:45:10 PM PDT 24 4660941170 ps
T357 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4036318635 May 09 02:44:11 PM PDT 24 May 09 02:53:27 PM PDT 24 58396171189 ps
T358 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.563302059 May 09 02:44:31 PM PDT 24 May 09 02:45:08 PM PDT 24 17916714246 ps
T359 /workspace/coverage/default/9.rom_ctrl_stress_all.2950856043 May 09 02:43:58 PM PDT 24 May 09 02:45:27 PM PDT 24 7708684844 ps
T360 /workspace/coverage/default/40.rom_ctrl_alert_test.3421291679 May 09 02:45:05 PM PDT 24 May 09 02:45:17 PM PDT 24 661090209 ps
T361 /workspace/coverage/default/13.rom_ctrl_smoke.2202629858 May 09 02:44:09 PM PDT 24 May 09 02:45:00 PM PDT 24 3975322269 ps
T362 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.603587603 May 09 02:44:45 PM PDT 24 May 09 02:45:09 PM PDT 24 346023100 ps
T363 /workspace/coverage/default/1.rom_ctrl_smoke.1062343859 May 09 02:43:36 PM PDT 24 May 09 02:44:55 PM PDT 24 15671008854 ps
T364 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1552674385 May 09 02:45:30 PM PDT 24 May 09 02:46:40 PM PDT 24 17073585615 ps
T63 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4223704475 May 09 02:43:34 PM PDT 24 May 09 02:45:22 PM PDT 24 7505255573 ps
T64 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2648511999 May 09 02:43:31 PM PDT 24 May 09 02:43:47 PM PDT 24 5072462489 ps
T65 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.168876150 May 09 02:43:01 PM PDT 24 May 09 02:45:58 PM PDT 24 20434089588 ps
T101 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3927982790 May 09 02:42:51 PM PDT 24 May 09 02:43:21 PM PDT 24 3253346369 ps
T71 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.591863415 May 09 02:43:22 PM PDT 24 May 09 02:45:52 PM PDT 24 31326841601 ps
T365 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1919765747 May 09 02:42:50 PM PDT 24 May 09 02:43:10 PM PDT 24 21734533286 ps
T93 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1243567989 May 09 02:43:22 PM PDT 24 May 09 02:43:33 PM PDT 24 345784585 ps
T54 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3714766732 May 09 02:42:53 PM PDT 24 May 09 02:44:20 PM PDT 24 3005173324 ps
T102 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2976413808 May 09 02:42:51 PM PDT 24 May 09 02:43:03 PM PDT 24 1024800195 ps
T103 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2388873506 May 09 02:43:34 PM PDT 24 May 09 02:46:29 PM PDT 24 82123902218 ps
T104 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1371432557 May 09 02:43:10 PM PDT 24 May 09 02:45:13 PM PDT 24 62722269636 ps
T366 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1775840572 May 09 02:43:31 PM PDT 24 May 09 02:43:58 PM PDT 24 10766529106 ps
T94 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1039261925 May 09 02:42:54 PM PDT 24 May 09 02:43:26 PM PDT 24 3192008436 ps
T367 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1967058947 May 09 02:43:05 PM PDT 24 May 09 02:43:33 PM PDT 24 5599414905 ps
T55 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.93045255 May 09 02:43:31 PM PDT 24 May 09 02:44:04 PM PDT 24 4004424838 ps
T95 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2839767805 May 09 02:43:11 PM PDT 24 May 09 02:43:25 PM PDT 24 501635348 ps
T72 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2925625568 May 09 02:42:59 PM PDT 24 May 09 02:43:10 PM PDT 24 170897349 ps
T96 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2097305023 May 09 02:42:59 PM PDT 24 May 09 02:43:26 PM PDT 24 3010778464 ps
T368 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3552260382 May 09 02:43:31 PM PDT 24 May 09 02:44:00 PM PDT 24 2950240956 ps
T369 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.103513730 May 09 02:43:11 PM PDT 24 May 09 02:44:47 PM PDT 24 47582281060 ps
T61 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2304517535 May 09 02:43:33 PM PDT 24 May 09 02:45:20 PM PDT 24 4080960506 ps
T370 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.945114661 May 09 02:42:54 PM PDT 24 May 09 02:43:33 PM PDT 24 3542234558 ps
T97 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2976149691 May 09 02:43:34 PM PDT 24 May 09 02:44:10 PM PDT 24 16755644645 ps
T69 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.815836813 May 09 02:43:22 PM PDT 24 May 09 02:43:36 PM PDT 24 868030108 ps
T371 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2244727471 May 09 02:43:01 PM PDT 24 May 09 02:43:34 PM PDT 24 3194803791 ps
T372 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.315544629 May 09 02:42:54 PM PDT 24 May 09 02:43:27 PM PDT 24 3448577875 ps
T62 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.773231789 May 09 02:42:53 PM PDT 24 May 09 02:44:32 PM PDT 24 5390449848 ps
T73 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2166385986 May 09 02:43:22 PM PDT 24 May 09 02:43:49 PM PDT 24 2924300158 ps
T98 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2090041971 May 09 02:42:53 PM PDT 24 May 09 02:43:12 PM PDT 24 1419885089 ps
T373 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3759940341 May 09 02:43:00 PM PDT 24 May 09 02:43:39 PM PDT 24 4436238996 ps
T374 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1395941309 May 09 02:43:12 PM PDT 24 May 09 02:43:43 PM PDT 24 19361889820 ps
T375 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3210392903 May 09 02:42:51 PM PDT 24 May 09 02:43:13 PM PDT 24 1928211038 ps
T74 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2404337159 May 09 02:43:00 PM PDT 24 May 09 02:43:24 PM PDT 24 1982853365 ps
T376 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.516800371 May 09 02:42:59 PM PDT 24 May 09 02:43:14 PM PDT 24 1375065569 ps
T99 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2543683323 May 09 02:43:36 PM PDT 24 May 09 02:44:00 PM PDT 24 4577205836 ps
T377 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2671462507 May 09 02:43:36 PM PDT 24 May 09 02:44:11 PM PDT 24 4175346245 ps
T75 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1517561824 May 09 02:43:12 PM PDT 24 May 09 02:43:22 PM PDT 24 332438342 ps
T76 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2096518221 May 09 02:43:11 PM PDT 24 May 09 02:43:28 PM PDT 24 3953657916 ps
T378 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4151185948 May 09 02:43:01 PM PDT 24 May 09 02:43:25 PM PDT 24 12254098230 ps
T379 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3675482966 May 09 02:42:52 PM PDT 24 May 09 02:43:26 PM PDT 24 6701514375 ps
T100 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2330923002 May 09 02:43:33 PM PDT 24 May 09 02:44:04 PM PDT 24 19646033995 ps
T380 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2524903527 May 09 02:42:59 PM PDT 24 May 09 02:43:24 PM PDT 24 9164834176 ps
T381 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1329312803 May 09 02:43:22 PM PDT 24 May 09 02:43:41 PM PDT 24 3552980510 ps
T77 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2663056880 May 09 02:42:51 PM PDT 24 May 09 02:44:46 PM PDT 24 12463383982 ps
T382 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2780456731 May 09 02:42:53 PM PDT 24 May 09 02:43:04 PM PDT 24 1101227088 ps
T110 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2294172732 May 09 02:43:12 PM PDT 24 May 09 02:45:48 PM PDT 24 364100240 ps
T383 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3248106619 May 09 02:43:10 PM PDT 24 May 09 02:43:27 PM PDT 24 433289016 ps
T78 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2514958153 May 09 02:43:09 PM PDT 24 May 09 02:44:41 PM PDT 24 98904457180 ps
T118 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3934069096 May 09 02:43:31 PM PDT 24 May 09 02:45:09 PM PDT 24 21485566401 ps
T79 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2179195317 May 09 02:43:38 PM PDT 24 May 09 02:43:52 PM PDT 24 1522602703 ps
T384 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1013879495 May 09 02:43:01 PM PDT 24 May 09 02:43:18 PM PDT 24 2338206398 ps
T385 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1020578248 May 09 02:43:22 PM PDT 24 May 09 02:43:37 PM PDT 24 687636356 ps
T113 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3393521639 May 09 02:43:10 PM PDT 24 May 09 02:44:46 PM PDT 24 9786750421 ps
T112 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2965033436 May 09 02:43:32 PM PDT 24 May 09 02:46:16 PM PDT 24 1723287714 ps
T386 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2011408214 May 09 02:43:34 PM PDT 24 May 09 02:44:12 PM PDT 24 8473613759 ps
T387 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3426883684 May 09 02:43:22 PM PDT 24 May 09 02:43:34 PM PDT 24 169296202 ps
T388 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3326432465 May 09 02:42:55 PM PDT 24 May 09 02:43:18 PM PDT 24 2624249206 ps
T80 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2096749011 May 09 02:43:32 PM PDT 24 May 09 02:44:12 PM PDT 24 16278351544 ps
T389 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1861810021 May 09 02:43:34 PM PDT 24 May 09 02:45:12 PM PDT 24 52891717475 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2631011514 May 09 02:43:02 PM PDT 24 May 09 02:43:41 PM PDT 24 4216314626 ps
T391 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3057637286 May 09 02:43:21 PM PDT 24 May 09 02:43:43 PM PDT 24 6326991420 ps
T392 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1013735830 May 09 02:43:38 PM PDT 24 May 09 02:44:02 PM PDT 24 1366119694 ps
T393 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4188594357 May 09 02:43:37 PM PDT 24 May 09 02:44:00 PM PDT 24 28628506386 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2273530866 May 09 02:42:55 PM PDT 24 May 09 02:43:53 PM PDT 24 10246803467 ps
T395 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.158994621 May 09 02:43:10 PM PDT 24 May 09 02:43:21 PM PDT 24 180102486 ps
T396 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2616634203 May 09 02:43:33 PM PDT 24 May 09 02:43:46 PM PDT 24 184502866 ps
T397 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.437913527 May 09 02:43:13 PM PDT 24 May 09 02:45:12 PM PDT 24 28118111289 ps
T111 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.151511161 May 09 02:43:02 PM PDT 24 May 09 02:46:00 PM PDT 24 8182485183 ps
T123 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2241332655 May 09 02:43:33 PM PDT 24 May 09 02:46:24 PM PDT 24 6841140385 ps
T85 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3390413685 May 09 02:43:35 PM PDT 24 May 09 02:43:56 PM PDT 24 6028763961 ps
T398 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.503527534 May 09 02:43:23 PM PDT 24 May 09 02:43:34 PM PDT 24 167515961 ps
T399 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1981835644 May 09 02:43:30 PM PDT 24 May 09 02:43:50 PM PDT 24 10975025086 ps
T116 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4131155197 May 09 02:43:09 PM PDT 24 May 09 02:46:05 PM PDT 24 5877939602 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1292378875 May 09 02:43:02 PM PDT 24 May 09 02:43:20 PM PDT 24 2044276388 ps
T401 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.857497447 May 09 02:43:02 PM PDT 24 May 09 02:43:36 PM PDT 24 13651767577 ps
T86 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.829168206 May 09 02:42:51 PM PDT 24 May 09 02:44:58 PM PDT 24 30290978842 ps
T402 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.134023279 May 09 02:43:12 PM PDT 24 May 09 02:43:35 PM PDT 24 11806480096 ps
T403 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1505112399 May 09 02:43:10 PM PDT 24 May 09 02:43:33 PM PDT 24 1940546114 ps
T404 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3106124041 May 09 02:43:00 PM PDT 24 May 09 02:43:35 PM PDT 24 3689820396 ps
T405 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.390792040 May 09 02:43:33 PM PDT 24 May 09 02:43:46 PM PDT 24 167490156 ps
T406 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2370063703 May 09 02:43:01 PM PDT 24 May 09 02:43:35 PM PDT 24 3680012995 ps
T407 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4228949162 May 09 02:43:31 PM PDT 24 May 09 02:43:44 PM PDT 24 186430487 ps
T87 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1813274799 May 09 02:43:30 PM PDT 24 May 09 02:44:19 PM PDT 24 7884607072 ps
T408 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2370022872 May 09 02:43:36 PM PDT 24 May 09 02:44:14 PM PDT 24 8516560504 ps
T121 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2298201151 May 09 02:43:33 PM PDT 24 May 09 02:46:27 PM PDT 24 7098074380 ps
T125 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.164544832 May 09 02:43:00 PM PDT 24 May 09 02:44:28 PM PDT 24 1635640175 ps
T409 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2529202154 May 09 02:43:08 PM PDT 24 May 09 02:43:40 PM PDT 24 3767183747 ps
T410 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3312034328 May 09 02:43:31 PM PDT 24 May 09 02:43:49 PM PDT 24 1878706895 ps
T411 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1595420556 May 09 02:43:22 PM PDT 24 May 09 02:43:33 PM PDT 24 460611373 ps
T114 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4149704157 May 09 02:43:01 PM PDT 24 May 09 02:45:47 PM PDT 24 22652080299 ps
T412 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4017083954 May 09 02:43:11 PM PDT 24 May 09 02:43:45 PM PDT 24 8361926863 ps
T413 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3315683834 May 09 02:43:31 PM PDT 24 May 09 02:44:01 PM PDT 24 10227544121 ps
T414 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3131677835 May 09 02:43:31 PM PDT 24 May 09 02:44:00 PM PDT 24 9968507495 ps
T415 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2788574521 May 09 02:43:11 PM PDT 24 May 09 02:43:22 PM PDT 24 183885984 ps
T416 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2783941379 May 09 02:43:05 PM PDT 24 May 09 02:43:16 PM PDT 24 346197907 ps
T417 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.703561844 May 09 02:42:52 PM PDT 24 May 09 02:43:23 PM PDT 24 2845261300 ps
T418 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2508722054 May 09 02:43:01 PM PDT 24 May 09 02:43:21 PM PDT 24 1197172187 ps
T419 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1638799636 May 09 02:42:53 PM PDT 24 May 09 02:43:06 PM PDT 24 3209605218 ps
T88 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.25880373 May 09 02:43:30 PM PDT 24 May 09 02:43:40 PM PDT 24 244624321 ps
T420 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1826439194 May 09 02:43:11 PM PDT 24 May 09 02:43:25 PM PDT 24 174235875 ps
T421 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3530339781 May 09 02:43:14 PM PDT 24 May 09 02:44:12 PM PDT 24 3821292977 ps
T422 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2628997292 May 09 02:43:34 PM PDT 24 May 09 02:43:59 PM PDT 24 4889226879 ps
T423 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3662037061 May 09 02:43:01 PM PDT 24 May 09 02:43:17 PM PDT 24 1334357699 ps
T424 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3520340655 May 09 02:42:54 PM PDT 24 May 09 02:43:24 PM PDT 24 14973474796 ps
T425 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3691080822 May 09 02:43:11 PM PDT 24 May 09 02:43:22 PM PDT 24 331592491 ps
T119 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2848547598 May 09 02:43:10 PM PDT 24 May 09 02:45:46 PM PDT 24 335445151 ps
T426 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.743205690 May 09 02:43:32 PM PDT 24 May 09 02:43:48 PM PDT 24 338816417 ps
T89 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3065254242 May 09 02:43:31 PM PDT 24 May 09 02:46:32 PM PDT 24 43236767470 ps
T427 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2505270958 May 09 02:43:31 PM PDT 24 May 09 02:43:42 PM PDT 24 789524492 ps
T428 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.363657651 May 09 02:43:38 PM PDT 24 May 09 02:43:56 PM PDT 24 4455466236 ps
T429 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2092983905 May 09 02:43:33 PM PDT 24 May 09 02:44:06 PM PDT 24 3127130442 ps
T430 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2355404205 May 09 02:42:52 PM PDT 24 May 09 02:43:05 PM PDT 24 1650619299 ps
T115 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2563000688 May 09 02:43:23 PM PDT 24 May 09 02:46:14 PM PDT 24 3097707202 ps
T117 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2783331318 May 09 02:43:34 PM PDT 24 May 09 02:44:58 PM PDT 24 2125582779 ps
T431 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1011557972 May 09 02:43:33 PM PDT 24 May 09 02:44:05 PM PDT 24 3108473618 ps
T90 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.247380023 May 09 02:43:33 PM PDT 24 May 09 02:45:14 PM PDT 24 40823063445 ps
T432 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.448224448 May 09 02:43:03 PM PDT 24 May 09 02:43:14 PM PDT 24 345798392 ps
T433 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3308418096 May 09 02:43:30 PM PDT 24 May 09 02:45:03 PM PDT 24 9229060967 ps
T434 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1051221002 May 09 02:43:22 PM PDT 24 May 09 02:43:38 PM PDT 24 686078835 ps
T120 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3047882802 May 09 02:43:31 PM PDT 24 May 09 02:45:08 PM PDT 24 5855679483 ps
T435 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3737821148 May 09 02:43:34 PM PDT 24 May 09 02:44:03 PM PDT 24 3615154934 ps
T436 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3060411397 May 09 02:43:12 PM PDT 24 May 09 02:43:22 PM PDT 24 719489207 ps
T437 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.229810992 May 09 02:43:33 PM PDT 24 May 09 02:44:03 PM PDT 24 2988255996 ps
T438 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3342423012 May 09 02:43:02 PM PDT 24 May 09 02:43:37 PM PDT 24 4136363546 ps
T91 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3983006418 May 09 02:43:11 PM PDT 24 May 09 02:43:36 PM PDT 24 12942878422 ps
T439 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2069053903 May 09 02:43:02 PM PDT 24 May 09 02:43:14 PM PDT 24 1832323823 ps
T440 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.979879659 May 09 02:42:52 PM PDT 24 May 09 02:43:07 PM PDT 24 1397946443 ps
T122 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3843607038 May 09 02:43:14 PM PDT 24 May 09 02:44:55 PM PDT 24 7243191318 ps
T441 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2180279569 May 09 02:42:54 PM PDT 24 May 09 02:43:25 PM PDT 24 13674758061 ps
T442 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2860826349 May 09 02:43:10 PM PDT 24 May 09 02:43:43 PM PDT 24 13193138268 ps
T124 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2394751048 May 09 02:43:35 PM PDT 24 May 09 02:46:13 PM PDT 24 373053601 ps
T443 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.111994129 May 09 02:43:37 PM PDT 24 May 09 02:44:59 PM PDT 24 7407068276 ps
T444 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2321618469 May 09 02:43:23 PM PDT 24 May 09 02:44:01 PM PDT 24 38197303378 ps
T445 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1576376044 May 09 02:43:10 PM PDT 24 May 09 02:43:40 PM PDT 24 2914884391 ps
T92 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1854526665 May 09 02:43:32 PM PDT 24 May 09 02:45:15 PM PDT 24 92492935823 ps
T446 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2508108882 May 09 02:43:05 PM PDT 24 May 09 02:43:33 PM PDT 24 6513174930 ps
T447 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3943224953 May 09 02:43:09 PM PDT 24 May 09 02:43:45 PM PDT 24 54774675114 ps
T448 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3192682031 May 09 02:43:01 PM PDT 24 May 09 02:43:17 PM PDT 24 2049853934 ps
T449 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4141124537 May 09 02:42:51 PM PDT 24 May 09 02:43:20 PM PDT 24 5750618687 ps
T450 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2429475545 May 09 02:43:02 PM PDT 24 May 09 02:45:52 PM PDT 24 21697307356 ps
T451 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.585314726 May 09 02:43:02 PM PDT 24 May 09 02:43:35 PM PDT 24 11610200896 ps
T452 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3145706789 May 09 02:42:59 PM PDT 24 May 09 02:43:27 PM PDT 24 9280075785 ps
T453 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4143326128 May 09 02:42:59 PM PDT 24 May 09 02:43:21 PM PDT 24 5818942766 ps
T454 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1116770313 May 09 02:43:01 PM PDT 24 May 09 02:43:21 PM PDT 24 5562770280 ps
T455 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.63372811 May 09 02:43:23 PM PDT 24 May 09 02:44:50 PM PDT 24 735273566 ps

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2126242933
Short name T7
Test name
Test status
Simulation time 161362852148 ps
CPU time 630.01 seconds
Started May 09 02:44:52 PM PDT 24
Finished May 09 02:55:25 PM PDT 24
Peak memory 239060 kb
Host smart-f8747cb4-9031-4f8b-9134-8234d0f3123a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126242933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2126242933
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.307278960
Short name T20
Test name
Test status
Simulation time 148169146744 ps
CPU time 1048.83 seconds
Started May 09 02:45:16 PM PDT 24
Finished May 09 03:02:47 PM PDT 24
Peak memory 236780 kb
Host smart-d0098112-54bd-41ec-a952-6d1a441c5795
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307278960 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.307278960
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.967167892
Short name T11
Test name
Test status
Simulation time 7493595161 ps
CPU time 84.64 seconds
Started May 09 02:44:21 PM PDT 24
Finished May 09 02:45:48 PM PDT 24
Peak memory 219552 kb
Host smart-bbae7d1c-6051-4903-ab35-14a80d95ef02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967167892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.967167892
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1201972990
Short name T145
Test name
Test status
Simulation time 169235948860 ps
CPU time 469.47 seconds
Started May 09 02:43:44 PM PDT 24
Finished May 09 02:51:37 PM PDT 24
Peak memory 218400 kb
Host smart-f2560b38-9db2-4e2c-b7f6-b95873b289bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201972990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1201972990
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2304517535
Short name T61
Test name
Test status
Simulation time 4080960506 ps
CPU time 102.91 seconds
Started May 09 02:43:33 PM PDT 24
Finished May 09 02:45:20 PM PDT 24
Peak memory 213216 kb
Host smart-59cc4e73-e078-48f3-92c0-9194fb35f985
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304517535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2304517535
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.591863415
Short name T71
Test name
Test status
Simulation time 31326841601 ps
CPU time 147.06 seconds
Started May 09 02:43:22 PM PDT 24
Finished May 09 02:45:52 PM PDT 24
Peak memory 215152 kb
Host smart-6f1db44a-8a89-4c6b-93b2-bd907f163330
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591863415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.591863415
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2710288771
Short name T29
Test name
Test status
Simulation time 2597367557 ps
CPU time 238.54 seconds
Started May 09 02:43:46 PM PDT 24
Finished May 09 02:47:47 PM PDT 24
Peak memory 238956 kb
Host smart-703c1d75-c7ee-47fd-9286-ff5328215e15
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710288771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2710288771
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.151511161
Short name T111
Test name
Test status
Simulation time 8182485183 ps
CPU time 174.34 seconds
Started May 09 02:43:02 PM PDT 24
Finished May 09 02:46:00 PM PDT 24
Peak memory 213912 kb
Host smart-11f474f1-38e3-4b9c-9ea2-3bd3c59ea585
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151511161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.151511161
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4149704157
Short name T114
Test name
Test status
Simulation time 22652080299 ps
CPU time 162.36 seconds
Started May 09 02:43:01 PM PDT 24
Finished May 09 02:45:47 PM PDT 24
Peak memory 214000 kb
Host smart-5cea53d9-750b-4730-951f-7d41c37a8110
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149704157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.4149704157
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2132276170
Short name T32
Test name
Test status
Simulation time 10625782412 ps
CPU time 24.12 seconds
Started May 09 02:43:57 PM PDT 24
Finished May 09 02:44:24 PM PDT 24
Peak memory 212752 kb
Host smart-a94aed75-8863-4194-828c-f0b4fc25fbe0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132276170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2132276170
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.836507006
Short name T133
Test name
Test status
Simulation time 1801798829 ps
CPU time 31.84 seconds
Started May 09 02:44:21 PM PDT 24
Finished May 09 02:44:55 PM PDT 24
Peak memory 215196 kb
Host smart-1653bab8-9781-45ef-b731-864ccdbd07d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836507006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.836507006
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3235455208
Short name T24
Test name
Test status
Simulation time 2197623901 ps
CPU time 19.25 seconds
Started May 09 02:44:09 PM PDT 24
Finished May 09 02:44:31 PM PDT 24
Peak memory 215336 kb
Host smart-23c71d1f-32ce-49a5-ab8e-b10cde7e409a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235455208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3235455208
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2134362054
Short name T5
Test name
Test status
Simulation time 14583383922 ps
CPU time 51.34 seconds
Started May 09 02:45:17 PM PDT 24
Finished May 09 02:46:11 PM PDT 24
Peak memory 215708 kb
Host smart-bdfc4f23-8af8-4a13-b2d7-17cab82dc22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134362054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2134362054
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2241332655
Short name T123
Test name
Test status
Simulation time 6841140385 ps
CPU time 166.05 seconds
Started May 09 02:43:33 PM PDT 24
Finished May 09 02:46:24 PM PDT 24
Peak memory 213848 kb
Host smart-6281e51c-6a8c-4345-b8a8-97d440b46fde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241332655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2241332655
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.27431773
Short name T1
Test name
Test status
Simulation time 3879654157 ps
CPU time 259.84 seconds
Started May 09 02:44:27 PM PDT 24
Finished May 09 02:48:48 PM PDT 24
Peak memory 225848 kb
Host smart-5f4207ab-b3f6-4511-89f9-3d2ea76a153b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27431773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_co
rrupt_sig_fatal_chk.27431773
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3822869038
Short name T105
Test name
Test status
Simulation time 14627425788 ps
CPU time 30.21 seconds
Started May 09 02:44:22 PM PDT 24
Finished May 09 02:44:55 PM PDT 24
Peak memory 212092 kb
Host smart-fd816d31-a79d-4572-8f3b-7024f0f2ee2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3822869038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3822869038
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2273530866
Short name T394
Test name
Test status
Simulation time 10246803467 ps
CPU time 55.23 seconds
Started May 09 02:42:55 PM PDT 24
Finished May 09 02:43:53 PM PDT 24
Peak memory 215596 kb
Host smart-84327261-16c9-41ab-8585-0d9d9396adf0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273530866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2273530866
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2298201151
Short name T121
Test name
Test status
Simulation time 7098074380 ps
CPU time 169.32 seconds
Started May 09 02:43:33 PM PDT 24
Finished May 09 02:46:27 PM PDT 24
Peak memory 213960 kb
Host smart-7946bd0e-1919-474e-be3b-38a1530eb9d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298201151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2298201151
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.4114485756
Short name T22
Test name
Test status
Simulation time 11257310570 ps
CPU time 1320.44 seconds
Started May 09 02:43:53 PM PDT 24
Finished May 09 03:05:56 PM PDT 24
Peak memory 228148 kb
Host smart-d7bb09ef-dd46-4433-b7ee-315337a575a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114485756 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.4114485756
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3142501003
Short name T35
Test name
Test status
Simulation time 17021356576 ps
CPU time 47.03 seconds
Started May 09 02:43:58 PM PDT 24
Finished May 09 02:44:48 PM PDT 24
Peak memory 218544 kb
Host smart-afa2ed6f-3275-4739-b742-f2a534be9bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142501003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3142501003
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2976413808
Short name T102
Test name
Test status
Simulation time 1024800195 ps
CPU time 9.7 seconds
Started May 09 02:42:51 PM PDT 24
Finished May 09 02:43:03 PM PDT 24
Peak memory 210944 kb
Host smart-fa874327-dbf5-42c9-9ca5-e622e5138426
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976413808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2976413808
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2780456731
Short name T382
Test name
Test status
Simulation time 1101227088 ps
CPU time 8.29 seconds
Started May 09 02:42:53 PM PDT 24
Finished May 09 02:43:04 PM PDT 24
Peak memory 210892 kb
Host smart-390230f5-29b5-42f7-ad26-1dda6ee645ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780456731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2780456731
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.945114661
Short name T370
Test name
Test status
Simulation time 3542234558 ps
CPU time 36.52 seconds
Started May 09 02:42:54 PM PDT 24
Finished May 09 02:43:33 PM PDT 24
Peak memory 211296 kb
Host smart-c6fe605c-955b-4f7e-9f4f-eec268cd5b48
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945114661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.945114661
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4141124537
Short name T449
Test name
Test status
Simulation time 5750618687 ps
CPU time 26.46 seconds
Started May 09 02:42:51 PM PDT 24
Finished May 09 02:43:20 PM PDT 24
Peak memory 219236 kb
Host smart-134721c4-0d92-4172-b230-7a661c56e852
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141124537 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.4141124537
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.979879659
Short name T440
Test name
Test status
Simulation time 1397946443 ps
CPU time 12.98 seconds
Started May 09 02:42:52 PM PDT 24
Finished May 09 02:43:07 PM PDT 24
Peak memory 210888 kb
Host smart-e6f87c44-ae03-4bd3-a42f-33c055b67504
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979879659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.979879659
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3210392903
Short name T375
Test name
Test status
Simulation time 1928211038 ps
CPU time 19.92 seconds
Started May 09 02:42:51 PM PDT 24
Finished May 09 02:43:13 PM PDT 24
Peak memory 210720 kb
Host smart-8bdfee99-ef1e-4b1d-9135-d839a03e73ea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210392903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3210392903
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1919765747
Short name T365
Test name
Test status
Simulation time 21734533286 ps
CPU time 17.37 seconds
Started May 09 02:42:50 PM PDT 24
Finished May 09 02:43:10 PM PDT 24
Peak memory 210940 kb
Host smart-08a7925b-502e-4880-bdd4-21bea1eec5f0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919765747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1919765747
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.829168206
Short name T86
Test name
Test status
Simulation time 30290978842 ps
CPU time 124.64 seconds
Started May 09 02:42:51 PM PDT 24
Finished May 09 02:44:58 PM PDT 24
Peak memory 211624 kb
Host smart-cdd25536-ed86-486c-8b2c-9306ae700562
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829168206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.829168206
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3520340655
Short name T424
Test name
Test status
Simulation time 14973474796 ps
CPU time 27.84 seconds
Started May 09 02:42:54 PM PDT 24
Finished May 09 02:43:24 PM PDT 24
Peak memory 212484 kb
Host smart-f9363629-58aa-42dc-a733-332378fb743b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520340655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3520340655
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3675482966
Short name T379
Test name
Test status
Simulation time 6701514375 ps
CPU time 32.11 seconds
Started May 09 02:42:52 PM PDT 24
Finished May 09 02:43:26 PM PDT 24
Peak memory 218476 kb
Host smart-36048512-0850-4c0f-9c39-876a4a708cb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675482966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3675482966
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.773231789
Short name T62
Test name
Test status
Simulation time 5390449848 ps
CPU time 96.68 seconds
Started May 09 02:42:53 PM PDT 24
Finished May 09 02:44:32 PM PDT 24
Peak memory 219176 kb
Host smart-ff304aa1-efe4-42fe-acde-99fbbe9e1e86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773231789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.773231789
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2180279569
Short name T441
Test name
Test status
Simulation time 13674758061 ps
CPU time 28.25 seconds
Started May 09 02:42:54 PM PDT 24
Finished May 09 02:43:25 PM PDT 24
Peak memory 211392 kb
Host smart-3b3c03fe-812a-4413-afbf-b06cb240b365
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180279569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2180279569
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3927982790
Short name T101
Test name
Test status
Simulation time 3253346369 ps
CPU time 27.64 seconds
Started May 09 02:42:51 PM PDT 24
Finished May 09 02:43:21 PM PDT 24
Peak memory 211292 kb
Host smart-2604e38c-d665-4e58-9fd3-c3a1fbd7a653
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927982790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3927982790
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.703561844
Short name T417
Test name
Test status
Simulation time 2845261300 ps
CPU time 28.36 seconds
Started May 09 02:42:52 PM PDT 24
Finished May 09 02:43:23 PM PDT 24
Peak memory 211568 kb
Host smart-c46a7eb9-3542-4c31-9cef-a18c0e9b96ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703561844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.703561844
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1638799636
Short name T419
Test name
Test status
Simulation time 3209605218 ps
CPU time 11.33 seconds
Started May 09 02:42:53 PM PDT 24
Finished May 09 02:43:06 PM PDT 24
Peak memory 219252 kb
Host smart-24f99fff-70a1-45cf-8ad6-1ed7e6007cf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638799636 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1638799636
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2090041971
Short name T98
Test name
Test status
Simulation time 1419885089 ps
CPU time 16.96 seconds
Started May 09 02:42:53 PM PDT 24
Finished May 09 02:43:12 PM PDT 24
Peak memory 211720 kb
Host smart-d889718e-45d9-4270-b438-80aa502085b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090041971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2090041971
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2355404205
Short name T430
Test name
Test status
Simulation time 1650619299 ps
CPU time 11.05 seconds
Started May 09 02:42:52 PM PDT 24
Finished May 09 02:43:05 PM PDT 24
Peak memory 210792 kb
Host smart-e2123196-5494-4fba-8013-bbdb45f74cce
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355404205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2355404205
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3326432465
Short name T388
Test name
Test status
Simulation time 2624249206 ps
CPU time 21.49 seconds
Started May 09 02:42:55 PM PDT 24
Finished May 09 02:43:18 PM PDT 24
Peak memory 210916 kb
Host smart-bb21f690-ebd0-4abf-bb74-bfd77f682fb7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326432465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3326432465
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1039261925
Short name T94
Test name
Test status
Simulation time 3192008436 ps
CPU time 29.45 seconds
Started May 09 02:42:54 PM PDT 24
Finished May 09 02:43:26 PM PDT 24
Peak memory 212024 kb
Host smart-69c1d5b4-c698-4cf1-80a2-29a6d6a8f2b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039261925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1039261925
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.315544629
Short name T372
Test name
Test status
Simulation time 3448577875 ps
CPU time 31.06 seconds
Started May 09 02:42:54 PM PDT 24
Finished May 09 02:43:27 PM PDT 24
Peak memory 217052 kb
Host smart-a64d3ec6-0cf8-4eb1-8e29-2e3601eab53a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315544629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.315544629
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3714766732
Short name T54
Test name
Test status
Simulation time 3005173324 ps
CPU time 84.36 seconds
Started May 09 02:42:53 PM PDT 24
Finished May 09 02:44:20 PM PDT 24
Peak memory 219208 kb
Host smart-7a0af33c-134a-4289-bdf0-aa95832b0557
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714766732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3714766732
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1051221002
Short name T434
Test name
Test status
Simulation time 686078835 ps
CPU time 13.02 seconds
Started May 09 02:43:22 PM PDT 24
Finished May 09 02:43:38 PM PDT 24
Peak memory 219156 kb
Host smart-8933fdb1-b1ac-4f63-b106-1f6e197d7488
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051221002 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1051221002
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.503527534
Short name T398
Test name
Test status
Simulation time 167515961 ps
CPU time 8.11 seconds
Started May 09 02:43:23 PM PDT 24
Finished May 09 02:43:34 PM PDT 24
Peak memory 210928 kb
Host smart-2c96aa2f-7a3f-4c7b-b267-7ddbfba93b5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503527534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.503527534
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1813274799
Short name T87
Test name
Test status
Simulation time 7884607072 ps
CPU time 46.96 seconds
Started May 09 02:43:30 PM PDT 24
Finished May 09 02:44:19 PM PDT 24
Peak memory 213916 kb
Host smart-ced3f246-4123-438f-be24-9342750a15bb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813274799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1813274799
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3426883684
Short name T387
Test name
Test status
Simulation time 169296202 ps
CPU time 8.26 seconds
Started May 09 02:43:22 PM PDT 24
Finished May 09 02:43:34 PM PDT 24
Peak memory 210956 kb
Host smart-09500d38-8c45-43eb-ae86-396559ff73cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426883684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3426883684
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3315683834
Short name T413
Test name
Test status
Simulation time 10227544121 ps
CPU time 26.38 seconds
Started May 09 02:43:31 PM PDT 24
Finished May 09 02:44:01 PM PDT 24
Peak memory 218420 kb
Host smart-d22828bf-bffd-4670-bdac-b35b33feacfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315683834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3315683834
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2505270958
Short name T427
Test name
Test status
Simulation time 789524492 ps
CPU time 8.41 seconds
Started May 09 02:43:31 PM PDT 24
Finished May 09 02:43:42 PM PDT 24
Peak memory 219148 kb
Host smart-004c2be4-e1b1-4aa9-bee7-da81ca7d7a72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505270958 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2505270958
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2648511999
Short name T64
Test name
Test status
Simulation time 5072462489 ps
CPU time 12.49 seconds
Started May 09 02:43:31 PM PDT 24
Finished May 09 02:43:47 PM PDT 24
Peak memory 210888 kb
Host smart-e5bb3355-d2ab-45e5-af28-e8756d2f774e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648511999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2648511999
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.390792040
Short name T405
Test name
Test status
Simulation time 167490156 ps
CPU time 8.22 seconds
Started May 09 02:43:33 PM PDT 24
Finished May 09 02:43:46 PM PDT 24
Peak memory 210936 kb
Host smart-f1e5072a-d195-4a56-9d89-32340196abfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390792040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.390792040
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3131677835
Short name T414
Test name
Test status
Simulation time 9968507495 ps
CPU time 26.36 seconds
Started May 09 02:43:31 PM PDT 24
Finished May 09 02:44:00 PM PDT 24
Peak memory 219240 kb
Host smart-b4b43f24-c8cf-4993-9029-646f9bd37927
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131677835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3131677835
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2563000688
Short name T115
Test name
Test status
Simulation time 3097707202 ps
CPU time 167.49 seconds
Started May 09 02:43:23 PM PDT 24
Finished May 09 02:46:14 PM PDT 24
Peak memory 213532 kb
Host smart-6180748a-2549-443c-ad94-b5520b4dcb10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563000688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2563000688
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3057637286
Short name T391
Test name
Test status
Simulation time 6326991420 ps
CPU time 18.84 seconds
Started May 09 02:43:21 PM PDT 24
Finished May 09 02:43:43 PM PDT 24
Peak memory 219300 kb
Host smart-d15ed9a3-7982-40ac-be44-2e1706f2992d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057637286 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3057637286
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1011557972
Short name T431
Test name
Test status
Simulation time 3108473618 ps
CPU time 27.62 seconds
Started May 09 02:43:33 PM PDT 24
Finished May 09 02:44:05 PM PDT 24
Peak memory 211212 kb
Host smart-8d4e2520-cf98-4745-9d0b-8d996ee7bd19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011557972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1011557972
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4223704475
Short name T63
Test name
Test status
Simulation time 7505255573 ps
CPU time 103.37 seconds
Started May 09 02:43:34 PM PDT 24
Finished May 09 02:45:22 PM PDT 24
Peak memory 215456 kb
Host smart-0a5d1031-e95c-4682-b7f9-b754cd1bb252
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223704475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.4223704475
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1243567989
Short name T93
Test name
Test status
Simulation time 345784585 ps
CPU time 8.23 seconds
Started May 09 02:43:22 PM PDT 24
Finished May 09 02:43:33 PM PDT 24
Peak memory 210940 kb
Host smart-bc633249-3734-4280-8476-496a9220e148
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243567989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1243567989
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.815836813
Short name T69
Test name
Test status
Simulation time 868030108 ps
CPU time 11.29 seconds
Started May 09 02:43:22 PM PDT 24
Finished May 09 02:43:36 PM PDT 24
Peak memory 219120 kb
Host smart-c6721cc2-d734-4b4e-9248-87ab3ae0efcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815836813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.815836813
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3934069096
Short name T118
Test name
Test status
Simulation time 21485566401 ps
CPU time 95.5 seconds
Started May 09 02:43:31 PM PDT 24
Finished May 09 02:45:09 PM PDT 24
Peak memory 213272 kb
Host smart-b37198b7-3960-472e-9095-8e31eb357d93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934069096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3934069096
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1329312803
Short name T381
Test name
Test status
Simulation time 3552980510 ps
CPU time 15.63 seconds
Started May 09 02:43:22 PM PDT 24
Finished May 09 02:43:41 PM PDT 24
Peak memory 219220 kb
Host smart-6444af73-b221-431f-b06b-d41ec68735b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329312803 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1329312803
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1775840572
Short name T366
Test name
Test status
Simulation time 10766529106 ps
CPU time 24.74 seconds
Started May 09 02:43:31 PM PDT 24
Finished May 09 02:43:58 PM PDT 24
Peak memory 211612 kb
Host smart-c547a1d0-07ce-4896-9580-4ae104e68da0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775840572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1775840572
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3308418096
Short name T433
Test name
Test status
Simulation time 9229060967 ps
CPU time 91.59 seconds
Started May 09 02:43:30 PM PDT 24
Finished May 09 02:45:03 PM PDT 24
Peak memory 215096 kb
Host smart-38d5c123-0dea-44b5-8180-86c91961dc68
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308418096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3308418096
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2096749011
Short name T80
Test name
Test status
Simulation time 16278351544 ps
CPU time 35.39 seconds
Started May 09 02:43:32 PM PDT 24
Finished May 09 02:44:12 PM PDT 24
Peak memory 212236 kb
Host smart-dd5dd487-7600-4b6c-9592-61df11e8660b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096749011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2096749011
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2321618469
Short name T444
Test name
Test status
Simulation time 38197303378 ps
CPU time 35.47 seconds
Started May 09 02:43:23 PM PDT 24
Finished May 09 02:44:01 PM PDT 24
Peak memory 219292 kb
Host smart-ec055db5-715d-41c5-9d3b-591e61a1fb34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321618469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2321618469
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4228949162
Short name T407
Test name
Test status
Simulation time 186430487 ps
CPU time 8.82 seconds
Started May 09 02:43:31 PM PDT 24
Finished May 09 02:43:44 PM PDT 24
Peak memory 215564 kb
Host smart-78272da5-79ea-4bb9-933e-cfcb1d2c9357
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228949162 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4228949162
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1595420556
Short name T411
Test name
Test status
Simulation time 460611373 ps
CPU time 8.16 seconds
Started May 09 02:43:22 PM PDT 24
Finished May 09 02:43:33 PM PDT 24
Peak memory 210916 kb
Host smart-c5e76a24-ed1e-43b0-b0d5-71c23b127de9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595420556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1595420556
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3065254242
Short name T89
Test name
Test status
Simulation time 43236767470 ps
CPU time 178.53 seconds
Started May 09 02:43:31 PM PDT 24
Finished May 09 02:46:32 PM PDT 24
Peak memory 215120 kb
Host smart-cbbb3cdf-f2a0-4e6d-bb0e-dedbd2cf52e0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065254242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3065254242
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2166385986
Short name T73
Test name
Test status
Simulation time 2924300158 ps
CPU time 24.7 seconds
Started May 09 02:43:22 PM PDT 24
Finished May 09 02:43:49 PM PDT 24
Peak memory 212040 kb
Host smart-4443c2eb-33e1-4664-87b3-5a8975027bb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166385986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2166385986
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1981835644
Short name T399
Test name
Test status
Simulation time 10975025086 ps
CPU time 18.62 seconds
Started May 09 02:43:30 PM PDT 24
Finished May 09 02:43:50 PM PDT 24
Peak memory 219248 kb
Host smart-6922a92b-4b54-4743-bdce-91bb05657d3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981835644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1981835644
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.63372811
Short name T455
Test name
Test status
Simulation time 735273566 ps
CPU time 84.39 seconds
Started May 09 02:43:23 PM PDT 24
Finished May 09 02:44:50 PM PDT 24
Peak memory 213484 kb
Host smart-524ba149-9e5f-4a14-849a-c3dc739c2d44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63372811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_int
g_err.63372811
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3312034328
Short name T410
Test name
Test status
Simulation time 1878706895 ps
CPU time 16.45 seconds
Started May 09 02:43:31 PM PDT 24
Finished May 09 02:43:49 PM PDT 24
Peak memory 215964 kb
Host smart-900236e2-db3f-4b39-ac53-e121a4f65acf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312034328 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3312034328
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.25880373
Short name T88
Test name
Test status
Simulation time 244624321 ps
CPU time 8.19 seconds
Started May 09 02:43:30 PM PDT 24
Finished May 09 02:43:40 PM PDT 24
Peak memory 210872 kb
Host smart-fe304b60-0bfe-49dc-9ee9-0909bd29e883
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25880373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.25880373
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1854526665
Short name T92
Test name
Test status
Simulation time 92492935823 ps
CPU time 98.95 seconds
Started May 09 02:43:32 PM PDT 24
Finished May 09 02:45:15 PM PDT 24
Peak memory 214108 kb
Host smart-846ee4f6-26d0-4498-98d5-567377fce895
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854526665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1854526665
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3737821148
Short name T435
Test name
Test status
Simulation time 3615154934 ps
CPU time 25.26 seconds
Started May 09 02:43:34 PM PDT 24
Finished May 09 02:44:03 PM PDT 24
Peak memory 211716 kb
Host smart-7d2ef817-f710-40cc-8697-dd88218b7ae8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737821148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3737821148
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1020578248
Short name T385
Test name
Test status
Simulation time 687636356 ps
CPU time 11.75 seconds
Started May 09 02:43:22 PM PDT 24
Finished May 09 02:43:37 PM PDT 24
Peak memory 216948 kb
Host smart-f38880db-4a50-4e99-b96e-a3e45607fe50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020578248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1020578248
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3047882802
Short name T120
Test name
Test status
Simulation time 5855679483 ps
CPU time 94.96 seconds
Started May 09 02:43:31 PM PDT 24
Finished May 09 02:45:08 PM PDT 24
Peak memory 214568 kb
Host smart-4054d871-9cb0-4120-900b-18036b8d7d18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047882802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3047882802
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2370022872
Short name T408
Test name
Test status
Simulation time 8516560504 ps
CPU time 33.88 seconds
Started May 09 02:43:36 PM PDT 24
Finished May 09 02:44:14 PM PDT 24
Peak memory 218548 kb
Host smart-a41dd3e5-7d9f-41c5-adc6-396caed5867b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370022872 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2370022872
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.229810992
Short name T437
Test name
Test status
Simulation time 2988255996 ps
CPU time 25.57 seconds
Started May 09 02:43:33 PM PDT 24
Finished May 09 02:44:03 PM PDT 24
Peak memory 211608 kb
Host smart-5e34e452-0baa-46c0-a395-a38db4888b6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229810992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.229810992
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.247380023
Short name T90
Test name
Test status
Simulation time 40823063445 ps
CPU time 96.26 seconds
Started May 09 02:43:33 PM PDT 24
Finished May 09 02:45:14 PM PDT 24
Peak memory 214436 kb
Host smart-3af51d36-6863-4426-89b3-cceb0005b91a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247380023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.247380023
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2011408214
Short name T386
Test name
Test status
Simulation time 8473613759 ps
CPU time 33.65 seconds
Started May 09 02:43:34 PM PDT 24
Finished May 09 02:44:12 PM PDT 24
Peak memory 211996 kb
Host smart-1bb8a724-c199-43b7-b217-86e90b5d84f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011408214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2011408214
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.743205690
Short name T426
Test name
Test status
Simulation time 338816417 ps
CPU time 11.24 seconds
Started May 09 02:43:32 PM PDT 24
Finished May 09 02:43:48 PM PDT 24
Peak memory 217208 kb
Host smart-c31ed32b-7e8b-4360-bb5e-99f1350af3bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743205690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.743205690
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2965033436
Short name T112
Test name
Test status
Simulation time 1723287714 ps
CPU time 159.47 seconds
Started May 09 02:43:32 PM PDT 24
Finished May 09 02:46:16 PM PDT 24
Peak memory 213544 kb
Host smart-5ce8e522-d837-4fce-ad22-de2cbc6ce1e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965033436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2965033436
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2671462507
Short name T377
Test name
Test status
Simulation time 4175346245 ps
CPU time 31.24 seconds
Started May 09 02:43:36 PM PDT 24
Finished May 09 02:44:11 PM PDT 24
Peak memory 217016 kb
Host smart-4e3f67fd-6fb5-4b1f-9f3d-48a7cb2c993c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671462507 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2671462507
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3390413685
Short name T85
Test name
Test status
Simulation time 6028763961 ps
CPU time 17.39 seconds
Started May 09 02:43:35 PM PDT 24
Finished May 09 02:43:56 PM PDT 24
Peak memory 212232 kb
Host smart-6c2c7638-00dc-4601-b220-6d8cabaeaff2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390413685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3390413685
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2388873506
Short name T103
Test name
Test status
Simulation time 82123902218 ps
CPU time 171.08 seconds
Started May 09 02:43:34 PM PDT 24
Finished May 09 02:46:29 PM PDT 24
Peak memory 215296 kb
Host smart-6831d0c4-f5f8-4ccd-ae95-7f294c047658
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388873506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2388873506
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2179195317
Short name T79
Test name
Test status
Simulation time 1522602703 ps
CPU time 11 seconds
Started May 09 02:43:38 PM PDT 24
Finished May 09 02:43:52 PM PDT 24
Peak memory 210828 kb
Host smart-a974b944-1bd2-4acb-9363-1318bb968be2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179195317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2179195317
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2092983905
Short name T429
Test name
Test status
Simulation time 3127130442 ps
CPU time 29.09 seconds
Started May 09 02:43:33 PM PDT 24
Finished May 09 02:44:06 PM PDT 24
Peak memory 217152 kb
Host smart-9915c5b3-dd68-45d6-b652-446179937afa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092983905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2092983905
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2394751048
Short name T124
Test name
Test status
Simulation time 373053601 ps
CPU time 154.49 seconds
Started May 09 02:43:35 PM PDT 24
Finished May 09 02:46:13 PM PDT 24
Peak memory 213388 kb
Host smart-783bcbee-5458-49e9-81e6-ee1c11bc323d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394751048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2394751048
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.363657651
Short name T428
Test name
Test status
Simulation time 4455466236 ps
CPU time 15.34 seconds
Started May 09 02:43:38 PM PDT 24
Finished May 09 02:43:56 PM PDT 24
Peak memory 215256 kb
Host smart-d3163338-d560-4772-b43c-2dc7218d77ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363657651 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.363657651
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4188594357
Short name T393
Test name
Test status
Simulation time 28628506386 ps
CPU time 19.42 seconds
Started May 09 02:43:37 PM PDT 24
Finished May 09 02:44:00 PM PDT 24
Peak memory 211968 kb
Host smart-c0b5ecdd-8677-4ca4-9b90-f25234af56e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188594357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.4188594357
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.111994129
Short name T443
Test name
Test status
Simulation time 7407068276 ps
CPU time 79.13 seconds
Started May 09 02:43:37 PM PDT 24
Finished May 09 02:44:59 PM PDT 24
Peak memory 214128 kb
Host smart-f36773c2-9872-453e-acb6-c655a06d5641
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111994129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.111994129
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2543683323
Short name T99
Test name
Test status
Simulation time 4577205836 ps
CPU time 20.44 seconds
Started May 09 02:43:36 PM PDT 24
Finished May 09 02:44:00 PM PDT 24
Peak memory 212276 kb
Host smart-ae7a7927-0464-4d99-9481-3c662db55744
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543683323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2543683323
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2628997292
Short name T422
Test name
Test status
Simulation time 4889226879 ps
CPU time 20.91 seconds
Started May 09 02:43:34 PM PDT 24
Finished May 09 02:43:59 PM PDT 24
Peak memory 218660 kb
Host smart-7a772920-30f1-4324-b6c8-3f86a31b48ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628997292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2628997292
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2783331318
Short name T117
Test name
Test status
Simulation time 2125582779 ps
CPU time 79.22 seconds
Started May 09 02:43:34 PM PDT 24
Finished May 09 02:44:58 PM PDT 24
Peak memory 212996 kb
Host smart-ca954381-0adc-4ab5-b698-27bd39b028d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783331318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2783331318
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2616634203
Short name T396
Test name
Test status
Simulation time 184502866 ps
CPU time 8.75 seconds
Started May 09 02:43:33 PM PDT 24
Finished May 09 02:43:46 PM PDT 24
Peak memory 215412 kb
Host smart-3f9528b4-d31a-4d34-949f-97ae33f1f52b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616634203 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2616634203
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3552260382
Short name T368
Test name
Test status
Simulation time 2950240956 ps
CPU time 26.25 seconds
Started May 09 02:43:31 PM PDT 24
Finished May 09 02:44:00 PM PDT 24
Peak memory 211556 kb
Host smart-f765963c-d02b-48cf-8598-b385abf598a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552260382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3552260382
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1861810021
Short name T389
Test name
Test status
Simulation time 52891717475 ps
CPU time 93.88 seconds
Started May 09 02:43:34 PM PDT 24
Finished May 09 02:45:12 PM PDT 24
Peak memory 214056 kb
Host smart-24ed5226-3f9e-4b43-b205-5f786719ad78
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861810021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1861810021
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2976149691
Short name T97
Test name
Test status
Simulation time 16755644645 ps
CPU time 32.29 seconds
Started May 09 02:43:34 PM PDT 24
Finished May 09 02:44:10 PM PDT 24
Peak memory 211720 kb
Host smart-6d3abaff-db0d-474e-9cde-00afb9818b15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976149691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2976149691
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1013735830
Short name T392
Test name
Test status
Simulation time 1366119694 ps
CPU time 21.5 seconds
Started May 09 02:43:38 PM PDT 24
Finished May 09 02:44:02 PM PDT 24
Peak memory 218220 kb
Host smart-1194e056-8c66-48a7-9da0-94d3d29816d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013735830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1013735830
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2404337159
Short name T74
Test name
Test status
Simulation time 1982853365 ps
CPU time 20.85 seconds
Started May 09 02:43:00 PM PDT 24
Finished May 09 02:43:24 PM PDT 24
Peak memory 211248 kb
Host smart-535a31d7-9c8e-414c-9224-0d241ef526da
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404337159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2404337159
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3106124041
Short name T404
Test name
Test status
Simulation time 3689820396 ps
CPU time 30.63 seconds
Started May 09 02:43:00 PM PDT 24
Finished May 09 02:43:35 PM PDT 24
Peak memory 211280 kb
Host smart-4ad02acc-dc99-4d03-9b7c-2be4bf4fd465
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106124041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3106124041
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.585314726
Short name T451
Test name
Test status
Simulation time 11610200896 ps
CPU time 29.06 seconds
Started May 09 02:43:02 PM PDT 24
Finished May 09 02:43:35 PM PDT 24
Peak memory 211656 kb
Host smart-d366c1da-db8e-45b1-8aac-d7c7c3f6cf47
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585314726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.585314726
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3759940341
Short name T373
Test name
Test status
Simulation time 4436238996 ps
CPU time 34.85 seconds
Started May 09 02:43:00 PM PDT 24
Finished May 09 02:43:39 PM PDT 24
Peak memory 219276 kb
Host smart-0a53a89f-f9ef-413a-ba57-002acb71cf5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759940341 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3759940341
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3192682031
Short name T448
Test name
Test status
Simulation time 2049853934 ps
CPU time 12.06 seconds
Started May 09 02:43:01 PM PDT 24
Finished May 09 02:43:17 PM PDT 24
Peak memory 210984 kb
Host smart-7fc3a933-d635-4f6e-bdca-329f2d221c8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192682031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3192682031
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2783941379
Short name T416
Test name
Test status
Simulation time 346197907 ps
CPU time 8.05 seconds
Started May 09 02:43:05 PM PDT 24
Finished May 09 02:43:16 PM PDT 24
Peak memory 210696 kb
Host smart-94f1463e-f9a2-4b87-976d-9129513ea988
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783941379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2783941379
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1116770313
Short name T454
Test name
Test status
Simulation time 5562770280 ps
CPU time 16.4 seconds
Started May 09 02:43:01 PM PDT 24
Finished May 09 02:43:21 PM PDT 24
Peak memory 210872 kb
Host smart-b4416ae7-68b1-4526-8a13-33dcae7698ae
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116770313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1116770313
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2663056880
Short name T77
Test name
Test status
Simulation time 12463383982 ps
CPU time 113.18 seconds
Started May 09 02:42:51 PM PDT 24
Finished May 09 02:44:46 PM PDT 24
Peak memory 214012 kb
Host smart-c4bf546c-490c-42a6-9aff-5b683cb40ddb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663056880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2663056880
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3662037061
Short name T423
Test name
Test status
Simulation time 1334357699 ps
CPU time 12.1 seconds
Started May 09 02:43:01 PM PDT 24
Finished May 09 02:43:17 PM PDT 24
Peak memory 212252 kb
Host smart-b3428744-a593-4f42-9650-bf607f8e55e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662037061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3662037061
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.516800371
Short name T376
Test name
Test status
Simulation time 1375065569 ps
CPU time 12.13 seconds
Started May 09 02:42:59 PM PDT 24
Finished May 09 02:43:14 PM PDT 24
Peak memory 219160 kb
Host smart-f733bd64-4239-4bf9-9ba9-d011eafba611
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516800371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.516800371
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.164544832
Short name T125
Test name
Test status
Simulation time 1635640175 ps
CPU time 84.44 seconds
Started May 09 02:43:00 PM PDT 24
Finished May 09 02:44:28 PM PDT 24
Peak memory 219120 kb
Host smart-38cf4079-40a0-43a5-9f32-75117eeb382a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164544832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.164544832
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2925625568
Short name T72
Test name
Test status
Simulation time 170897349 ps
CPU time 8.63 seconds
Started May 09 02:42:59 PM PDT 24
Finished May 09 02:43:10 PM PDT 24
Peak memory 210880 kb
Host smart-4da7ae85-2370-4a42-a7ce-e04a774b4b5f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925625568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2925625568
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1967058947
Short name T367
Test name
Test status
Simulation time 5599414905 ps
CPU time 25.72 seconds
Started May 09 02:43:05 PM PDT 24
Finished May 09 02:43:33 PM PDT 24
Peak memory 211856 kb
Host smart-93428626-b4b3-47d8-93e3-2a2a03ce6dc1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967058947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1967058947
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2244727471
Short name T371
Test name
Test status
Simulation time 3194803791 ps
CPU time 28.88 seconds
Started May 09 02:43:01 PM PDT 24
Finished May 09 02:43:34 PM PDT 24
Peak memory 211188 kb
Host smart-0f08cb5f-4aa2-46b1-aa68-35eaa487fda9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244727471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2244727471
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3342423012
Short name T438
Test name
Test status
Simulation time 4136363546 ps
CPU time 32 seconds
Started May 09 02:43:02 PM PDT 24
Finished May 09 02:43:37 PM PDT 24
Peak memory 217804 kb
Host smart-13f18e87-904e-40fd-bd71-8abcad7e34ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342423012 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3342423012
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1292378875
Short name T400
Test name
Test status
Simulation time 2044276388 ps
CPU time 14.22 seconds
Started May 09 02:43:02 PM PDT 24
Finished May 09 02:43:20 PM PDT 24
Peak memory 211096 kb
Host smart-abfd124b-7c3a-489e-9dac-274865cfa0b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292378875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1292378875
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2508722054
Short name T418
Test name
Test status
Simulation time 1197172187 ps
CPU time 15.75 seconds
Started May 09 02:43:01 PM PDT 24
Finished May 09 02:43:21 PM PDT 24
Peak memory 210792 kb
Host smart-209637e7-816b-48fe-af13-623be8f44d2e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508722054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2508722054
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2524903527
Short name T380
Test name
Test status
Simulation time 9164834176 ps
CPU time 22.15 seconds
Started May 09 02:42:59 PM PDT 24
Finished May 09 02:43:24 PM PDT 24
Peak memory 210932 kb
Host smart-382d98b8-3478-4196-87d4-39633b44b98c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524903527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2524903527
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.168876150
Short name T65
Test name
Test status
Simulation time 20434089588 ps
CPU time 173.34 seconds
Started May 09 02:43:01 PM PDT 24
Finished May 09 02:45:58 PM PDT 24
Peak memory 215196 kb
Host smart-f66904e2-3a56-421d-8e79-cd91ae08dc75
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168876150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.168876150
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.448224448
Short name T432
Test name
Test status
Simulation time 345798392 ps
CPU time 8.14 seconds
Started May 09 02:43:03 PM PDT 24
Finished May 09 02:43:14 PM PDT 24
Peak memory 210932 kb
Host smart-07f3eb0b-ad52-45c6-801c-566b268bbd5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448224448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.448224448
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3145706789
Short name T452
Test name
Test status
Simulation time 9280075785 ps
CPU time 25.53 seconds
Started May 09 02:42:59 PM PDT 24
Finished May 09 02:43:27 PM PDT 24
Peak memory 219308 kb
Host smart-6fb101ee-604e-4b39-9277-df2b9ec7c397
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145706789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3145706789
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4143326128
Short name T453
Test name
Test status
Simulation time 5818942766 ps
CPU time 19.93 seconds
Started May 09 02:42:59 PM PDT 24
Finished May 09 02:43:21 PM PDT 24
Peak memory 211884 kb
Host smart-040267fb-09ec-4654-8584-eb47013ea79a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143326128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.4143326128
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1013879495
Short name T384
Test name
Test status
Simulation time 2338206398 ps
CPU time 13.16 seconds
Started May 09 02:43:01 PM PDT 24
Finished May 09 02:43:18 PM PDT 24
Peak memory 210984 kb
Host smart-f41d19c2-0176-4a14-ae75-faea0f3e0d8c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013879495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1013879495
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2631011514
Short name T390
Test name
Test status
Simulation time 4216314626 ps
CPU time 35.44 seconds
Started May 09 02:43:02 PM PDT 24
Finished May 09 02:43:41 PM PDT 24
Peak memory 211168 kb
Host smart-485f7407-4f61-49d7-8d94-954af07be802
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631011514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2631011514
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2370063703
Short name T406
Test name
Test status
Simulation time 3680012995 ps
CPU time 30.07 seconds
Started May 09 02:43:01 PM PDT 24
Finished May 09 02:43:35 PM PDT 24
Peak memory 219196 kb
Host smart-638d2771-80a4-4f3f-bf41-45276df63b25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370063703 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2370063703
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.857497447
Short name T401
Test name
Test status
Simulation time 13651767577 ps
CPU time 30.28 seconds
Started May 09 02:43:02 PM PDT 24
Finished May 09 02:43:36 PM PDT 24
Peak memory 212268 kb
Host smart-68e384c3-31e8-4a92-b302-5e335e8f80f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857497447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.857497447
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2069053903
Short name T439
Test name
Test status
Simulation time 1832323823 ps
CPU time 7.9 seconds
Started May 09 02:43:02 PM PDT 24
Finished May 09 02:43:14 PM PDT 24
Peak memory 210796 kb
Host smart-d0ba2d01-fabb-4391-a032-0f43f3093fcb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069053903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2069053903
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4151185948
Short name T378
Test name
Test status
Simulation time 12254098230 ps
CPU time 20.52 seconds
Started May 09 02:43:01 PM PDT 24
Finished May 09 02:43:25 PM PDT 24
Peak memory 210956 kb
Host smart-dee68def-5f81-42bb-b455-df9cd13b3571
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151185948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.4151185948
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2429475545
Short name T450
Test name
Test status
Simulation time 21697307356 ps
CPU time 166.52 seconds
Started May 09 02:43:02 PM PDT 24
Finished May 09 02:45:52 PM PDT 24
Peak memory 215256 kb
Host smart-6c7151e6-62b7-4c2b-9ebe-8a93332946f3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429475545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2429475545
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2097305023
Short name T96
Test name
Test status
Simulation time 3010778464 ps
CPU time 24.69 seconds
Started May 09 02:42:59 PM PDT 24
Finished May 09 02:43:26 PM PDT 24
Peak memory 212104 kb
Host smart-617df3fc-40c9-442e-aa48-8a1a613be040
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097305023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2097305023
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2508108882
Short name T446
Test name
Test status
Simulation time 6513174930 ps
CPU time 25.47 seconds
Started May 09 02:43:05 PM PDT 24
Finished May 09 02:43:33 PM PDT 24
Peak memory 219184 kb
Host smart-ced81f04-2007-4936-b58c-be0dc264535a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508108882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2508108882
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4017083954
Short name T412
Test name
Test status
Simulation time 8361926863 ps
CPU time 31.61 seconds
Started May 09 02:43:11 PM PDT 24
Finished May 09 02:43:45 PM PDT 24
Peak memory 217408 kb
Host smart-ba1e2434-156c-422b-a8bb-eab0ca9f721b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017083954 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.4017083954
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2860826349
Short name T442
Test name
Test status
Simulation time 13193138268 ps
CPU time 30.49 seconds
Started May 09 02:43:10 PM PDT 24
Finished May 09 02:43:43 PM PDT 24
Peak memory 212176 kb
Host smart-ee9e5be9-4c33-4fa2-820e-8536bd824300
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860826349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2860826349
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.437913527
Short name T397
Test name
Test status
Simulation time 28118111289 ps
CPU time 116.63 seconds
Started May 09 02:43:13 PM PDT 24
Finished May 09 02:45:12 PM PDT 24
Peak memory 213104 kb
Host smart-15216d1f-6f64-4534-9006-26ebc9e250ce
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437913527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.437913527
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1505112399
Short name T403
Test name
Test status
Simulation time 1940546114 ps
CPU time 20.4 seconds
Started May 09 02:43:10 PM PDT 24
Finished May 09 02:43:33 PM PDT 24
Peak memory 211752 kb
Host smart-665211a7-f237-4d49-95c9-2543f9ca870d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505112399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1505112399
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1826439194
Short name T420
Test name
Test status
Simulation time 174235875 ps
CPU time 11.29 seconds
Started May 09 02:43:11 PM PDT 24
Finished May 09 02:43:25 PM PDT 24
Peak memory 219420 kb
Host smart-9778eb84-091d-4e99-b671-c140fa05aacf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826439194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1826439194
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2294172732
Short name T110
Test name
Test status
Simulation time 364100240 ps
CPU time 153.47 seconds
Started May 09 02:43:12 PM PDT 24
Finished May 09 02:45:48 PM PDT 24
Peak memory 213536 kb
Host smart-57b40569-1777-4cb3-9823-9a4c6a2edc80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294172732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2294172732
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.158994621
Short name T395
Test name
Test status
Simulation time 180102486 ps
CPU time 8.77 seconds
Started May 09 02:43:10 PM PDT 24
Finished May 09 02:43:21 PM PDT 24
Peak memory 219152 kb
Host smart-fbe84ac3-c577-4859-81fe-14c2b30bafce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158994621 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.158994621
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1517561824
Short name T75
Test name
Test status
Simulation time 332438342 ps
CPU time 7.92 seconds
Started May 09 02:43:12 PM PDT 24
Finished May 09 02:43:22 PM PDT 24
Peak memory 210880 kb
Host smart-f212cf6a-f444-42f1-80f8-06fb09569ead
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517561824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1517561824
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3530339781
Short name T421
Test name
Test status
Simulation time 3821292977 ps
CPU time 56.39 seconds
Started May 09 02:43:14 PM PDT 24
Finished May 09 02:44:12 PM PDT 24
Peak memory 214300 kb
Host smart-97730d5a-a363-402a-ab4b-761d3d101540
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530339781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3530339781
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2529202154
Short name T409
Test name
Test status
Simulation time 3767183747 ps
CPU time 30.42 seconds
Started May 09 02:43:08 PM PDT 24
Finished May 09 02:43:40 PM PDT 24
Peak memory 212020 kb
Host smart-f615658d-d866-4867-a9e1-03de75493ffd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529202154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2529202154
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3943224953
Short name T447
Test name
Test status
Simulation time 54774675114 ps
CPU time 34.1 seconds
Started May 09 02:43:09 PM PDT 24
Finished May 09 02:43:45 PM PDT 24
Peak memory 217588 kb
Host smart-c2b1f338-82e6-476a-b9f9-e59a24fcc560
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943224953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3943224953
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2848547598
Short name T119
Test name
Test status
Simulation time 335445151 ps
CPU time 153.74 seconds
Started May 09 02:43:10 PM PDT 24
Finished May 09 02:45:46 PM PDT 24
Peak memory 213348 kb
Host smart-7de0ecbe-e7e2-401a-aa72-947334918565
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848547598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2848547598
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2788574521
Short name T415
Test name
Test status
Simulation time 183885984 ps
CPU time 8.57 seconds
Started May 09 02:43:11 PM PDT 24
Finished May 09 02:43:22 PM PDT 24
Peak memory 215824 kb
Host smart-fd7c6187-5990-4d7f-8583-ca2d2afc5489
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788574521 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2788574521
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2096518221
Short name T76
Test name
Test status
Simulation time 3953657916 ps
CPU time 14.28 seconds
Started May 09 02:43:11 PM PDT 24
Finished May 09 02:43:28 PM PDT 24
Peak memory 210968 kb
Host smart-efb95f01-7e9f-4d7a-9998-5a2cc9e5aa98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096518221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2096518221
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2514958153
Short name T78
Test name
Test status
Simulation time 98904457180 ps
CPU time 90.46 seconds
Started May 09 02:43:09 PM PDT 24
Finished May 09 02:44:41 PM PDT 24
Peak memory 213472 kb
Host smart-3f113ead-9ff6-48a6-8dc2-40fd7697a929
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514958153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2514958153
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2839767805
Short name T95
Test name
Test status
Simulation time 501635348 ps
CPU time 11.54 seconds
Started May 09 02:43:11 PM PDT 24
Finished May 09 02:43:25 PM PDT 24
Peak memory 210864 kb
Host smart-6ca3c971-ea66-4a5d-82b2-2b045b8d6840
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839767805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2839767805
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.134023279
Short name T402
Test name
Test status
Simulation time 11806480096 ps
CPU time 20.75 seconds
Started May 09 02:43:12 PM PDT 24
Finished May 09 02:43:35 PM PDT 24
Peak memory 218520 kb
Host smart-11c968e6-9202-4068-bf98-9be640d96346
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134023279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.134023279
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3843607038
Short name T122
Test name
Test status
Simulation time 7243191318 ps
CPU time 99.47 seconds
Started May 09 02:43:14 PM PDT 24
Finished May 09 02:44:55 PM PDT 24
Peak memory 219168 kb
Host smart-6942ce83-b41d-449a-895e-87b711c88f7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843607038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3843607038
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1576376044
Short name T445
Test name
Test status
Simulation time 2914884391 ps
CPU time 27.44 seconds
Started May 09 02:43:10 PM PDT 24
Finished May 09 02:43:40 PM PDT 24
Peak memory 219192 kb
Host smart-6667df53-e2f5-43d4-8c62-a15bf31f52f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576376044 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1576376044
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3983006418
Short name T91
Test name
Test status
Simulation time 12942878422 ps
CPU time 22.12 seconds
Started May 09 02:43:11 PM PDT 24
Finished May 09 02:43:36 PM PDT 24
Peak memory 212160 kb
Host smart-59cb9660-2785-4bb7-aca7-a1c0d84b7f58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983006418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3983006418
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.103513730
Short name T369
Test name
Test status
Simulation time 47582281060 ps
CPU time 93.52 seconds
Started May 09 02:43:11 PM PDT 24
Finished May 09 02:44:47 PM PDT 24
Peak memory 213452 kb
Host smart-6fe37849-fa4c-45cf-a53f-3dd64228abe7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103513730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.103513730
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3060411397
Short name T436
Test name
Test status
Simulation time 719489207 ps
CPU time 8.15 seconds
Started May 09 02:43:12 PM PDT 24
Finished May 09 02:43:22 PM PDT 24
Peak memory 210868 kb
Host smart-701cfc02-45d8-44d6-ba40-3dd02aa7c28a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060411397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3060411397
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1395941309
Short name T374
Test name
Test status
Simulation time 19361889820 ps
CPU time 28.24 seconds
Started May 09 02:43:12 PM PDT 24
Finished May 09 02:43:43 PM PDT 24
Peak memory 218720 kb
Host smart-9d7f0822-4a6d-4b34-8a34-26bdc1ae18ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395941309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1395941309
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4131155197
Short name T116
Test name
Test status
Simulation time 5877939602 ps
CPU time 173.91 seconds
Started May 09 02:43:09 PM PDT 24
Finished May 09 02:46:05 PM PDT 24
Peak memory 218984 kb
Host smart-8c26f4ed-884d-446f-953e-31ac1cebf349
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131155197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.4131155197
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.93045255
Short name T55
Test name
Test status
Simulation time 4004424838 ps
CPU time 31.05 seconds
Started May 09 02:43:31 PM PDT 24
Finished May 09 02:44:04 PM PDT 24
Peak memory 218372 kb
Host smart-53508d74-a054-49b4-bfe5-7f5b20ce28ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93045255 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.93045255
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3691080822
Short name T425
Test name
Test status
Simulation time 331592491 ps
CPU time 8.18 seconds
Started May 09 02:43:11 PM PDT 24
Finished May 09 02:43:22 PM PDT 24
Peak memory 210940 kb
Host smart-4d474b18-308c-4769-9da9-b997438ca399
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691080822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3691080822
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1371432557
Short name T104
Test name
Test status
Simulation time 62722269636 ps
CPU time 120.41 seconds
Started May 09 02:43:10 PM PDT 24
Finished May 09 02:45:13 PM PDT 24
Peak memory 211704 kb
Host smart-cef98970-4e68-40a6-b20e-0872e43556a7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371432557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1371432557
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2330923002
Short name T100
Test name
Test status
Simulation time 19646033995 ps
CPU time 26.73 seconds
Started May 09 02:43:33 PM PDT 24
Finished May 09 02:44:04 PM PDT 24
Peak memory 212084 kb
Host smart-9c5c3b11-9693-4c61-ad3d-d33900300ac4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330923002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2330923002
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3248106619
Short name T383
Test name
Test status
Simulation time 433289016 ps
CPU time 14.73 seconds
Started May 09 02:43:10 PM PDT 24
Finished May 09 02:43:27 PM PDT 24
Peak memory 219180 kb
Host smart-ea393713-beca-4f12-beee-74c3961f74bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248106619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3248106619
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3393521639
Short name T113
Test name
Test status
Simulation time 9786750421 ps
CPU time 92.86 seconds
Started May 09 02:43:10 PM PDT 24
Finished May 09 02:44:46 PM PDT 24
Peak memory 213496 kb
Host smart-13561c77-8ede-43ae-9541-46b9a5c9332d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393521639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3393521639
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.4231836183
Short name T187
Test name
Test status
Simulation time 1269093969 ps
CPU time 8.14 seconds
Started May 09 02:43:35 PM PDT 24
Finished May 09 02:43:47 PM PDT 24
Peak memory 211844 kb
Host smart-c31a26a4-b5da-48d1-b8fd-06a530f83a06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231836183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.4231836183
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3996428631
Short name T242
Test name
Test status
Simulation time 165063426653 ps
CPU time 830.26 seconds
Started May 09 02:43:32 PM PDT 24
Finished May 09 02:57:28 PM PDT 24
Peak memory 231140 kb
Host smart-d520a6f5-2b53-419f-8a44-274361a53326
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996428631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3996428631
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1407382673
Short name T42
Test name
Test status
Simulation time 5609357560 ps
CPU time 35.24 seconds
Started May 09 02:43:38 PM PDT 24
Finished May 09 02:44:16 PM PDT 24
Peak memory 214416 kb
Host smart-d40bfeb2-4fce-42a4-9ff8-04364cad440e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407382673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1407382673
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3967442069
Short name T57
Test name
Test status
Simulation time 5793405038 ps
CPU time 26.14 seconds
Started May 09 02:43:35 PM PDT 24
Finished May 09 02:44:05 PM PDT 24
Peak memory 213344 kb
Host smart-404f0ff2-a8fe-4ced-bb0d-ee15185d2f9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3967442069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3967442069
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.24581428
Short name T34
Test name
Test status
Simulation time 16914046814 ps
CPU time 249.69 seconds
Started May 09 02:43:34 PM PDT 24
Finished May 09 02:47:48 PM PDT 24
Peak memory 237316 kb
Host smart-accc5646-0b4c-4dd5-9cda-6de295418341
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24581428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.24581428
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1188941494
Short name T268
Test name
Test status
Simulation time 31525788974 ps
CPU time 73.54 seconds
Started May 09 02:43:32 PM PDT 24
Finished May 09 02:44:51 PM PDT 24
Peak memory 218228 kb
Host smart-19d5aa8c-726d-40cd-a7db-8c8f30d156f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188941494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1188941494
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1914864650
Short name T289
Test name
Test status
Simulation time 7279743497 ps
CPU time 101.27 seconds
Started May 09 02:43:34 PM PDT 24
Finished May 09 02:45:20 PM PDT 24
Peak memory 220140 kb
Host smart-9b6b5446-8b62-45eb-b4a2-06ac570c6225
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914864650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1914864650
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4140890376
Short name T246
Test name
Test status
Simulation time 11793815473 ps
CPU time 29.77 seconds
Started May 09 02:43:45 PM PDT 24
Finished May 09 02:44:17 PM PDT 24
Peak memory 212792 kb
Host smart-ac01e573-068e-4f63-8aa1-64b8fccacf01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140890376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4140890376
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3658927925
Short name T340
Test name
Test status
Simulation time 2389792075 ps
CPU time 34.52 seconds
Started May 09 02:43:43 PM PDT 24
Finished May 09 02:44:19 PM PDT 24
Peak memory 215384 kb
Host smart-2c4ea491-97b7-442f-883c-9ca4b7664d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658927925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3658927925
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3224144617
Short name T264
Test name
Test status
Simulation time 213150600 ps
CPU time 10.39 seconds
Started May 09 02:43:44 PM PDT 24
Finished May 09 02:43:57 PM PDT 24
Peak memory 212796 kb
Host smart-12480810-c7e0-481a-bc72-ab9f878a8cf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3224144617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3224144617
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.558328653
Short name T31
Test name
Test status
Simulation time 10142700875 ps
CPU time 239.39 seconds
Started May 09 02:43:46 PM PDT 24
Finished May 09 02:47:48 PM PDT 24
Peak memory 239076 kb
Host smart-2cf3248d-5e7b-4e42-bd2e-601f48b16fa2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558328653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.558328653
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1062343859
Short name T363
Test name
Test status
Simulation time 15671008854 ps
CPU time 75.56 seconds
Started May 09 02:43:36 PM PDT 24
Finished May 09 02:44:55 PM PDT 24
Peak memory 216968 kb
Host smart-3f5201db-226a-4fa1-990b-36ecec62892a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062343859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1062343859
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2059819117
Short name T318
Test name
Test status
Simulation time 28877012122 ps
CPU time 115.65 seconds
Started May 09 02:43:33 PM PDT 24
Finished May 09 02:45:33 PM PDT 24
Peak memory 228136 kb
Host smart-2753bdb4-bed4-45d2-92c6-a3711bc3bddd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059819117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2059819117
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2273438908
Short name T44
Test name
Test status
Simulation time 127375033090 ps
CPU time 330.27 seconds
Started May 09 02:43:56 PM PDT 24
Finished May 09 02:49:30 PM PDT 24
Peak memory 238256 kb
Host smart-6978bf66-9725-463c-b4fe-595d66de0dcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273438908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2273438908
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3361291144
Short name T139
Test name
Test status
Simulation time 6169219832 ps
CPU time 49.69 seconds
Started May 09 02:43:54 PM PDT 24
Finished May 09 02:44:46 PM PDT 24
Peak memory 215924 kb
Host smart-add196d0-a27e-4268-ae73-0552a8d81451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361291144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3361291144
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.4085961170
Short name T162
Test name
Test status
Simulation time 8606638007 ps
CPU time 33.99 seconds
Started May 09 02:43:59 PM PDT 24
Finished May 09 02:44:37 PM PDT 24
Peak memory 213240 kb
Host smart-d633efe1-2254-4cd7-a2c1-fd89634b750c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4085961170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.4085961170
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2357278858
Short name T173
Test name
Test status
Simulation time 30151160605 ps
CPU time 90.16 seconds
Started May 09 02:43:53 PM PDT 24
Finished May 09 02:45:25 PM PDT 24
Peak memory 220004 kb
Host smart-f73dc859-b5ac-4505-afb4-2905aff79b93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357278858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2357278858
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1653955879
Short name T160
Test name
Test status
Simulation time 823213727 ps
CPU time 11.23 seconds
Started May 09 02:44:02 PM PDT 24
Finished May 09 02:44:16 PM PDT 24
Peak memory 211900 kb
Host smart-f6dc94c0-a98c-4c1b-b7a2-40cd17f18af3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653955879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1653955879
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3874571438
Short name T28
Test name
Test status
Simulation time 301597019971 ps
CPU time 936.53 seconds
Started May 09 02:44:00 PM PDT 24
Finished May 09 02:59:40 PM PDT 24
Peak memory 238652 kb
Host smart-0d63741a-30e0-4166-94ac-485b5ec1019d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874571438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3874571438
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.551880281
Short name T226
Test name
Test status
Simulation time 1002722995 ps
CPU time 23.79 seconds
Started May 09 02:43:56 PM PDT 24
Finished May 09 02:44:22 PM PDT 24
Peak memory 215368 kb
Host smart-0f43bb02-8ca1-461b-b426-093331d4d998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551880281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.551880281
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1463522270
Short name T294
Test name
Test status
Simulation time 4435671629 ps
CPU time 34.78 seconds
Started May 09 02:43:56 PM PDT 24
Finished May 09 02:44:33 PM PDT 24
Peak memory 212036 kb
Host smart-19f44223-8a57-489b-be7e-797769fcb816
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1463522270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1463522270
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.4074984301
Short name T84
Test name
Test status
Simulation time 10949582063 ps
CPU time 48.11 seconds
Started May 09 02:43:58 PM PDT 24
Finished May 09 02:44:50 PM PDT 24
Peak memory 218732 kb
Host smart-a32bfd7f-6c9c-4fde-817d-080009f1639a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074984301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.4074984301
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.80886511
Short name T269
Test name
Test status
Simulation time 8589787549 ps
CPU time 92.65 seconds
Started May 09 02:43:54 PM PDT 24
Finished May 09 02:45:29 PM PDT 24
Peak memory 220012 kb
Host smart-d0bdb4ce-8a63-4a9a-b1a8-c5abac3987e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80886511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 11.rom_ctrl_stress_all.80886511
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2639589516
Short name T49
Test name
Test status
Simulation time 42545763800 ps
CPU time 1761.75 seconds
Started May 09 02:43:58 PM PDT 24
Finished May 09 03:13:24 PM PDT 24
Peak memory 236920 kb
Host smart-6505eb04-5378-4a06-802e-23372f787596
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639589516 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2639589516
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2130104847
Short name T189
Test name
Test status
Simulation time 2141725714 ps
CPU time 21.47 seconds
Started May 09 02:44:11 PM PDT 24
Finished May 09 02:44:37 PM PDT 24
Peak memory 212448 kb
Host smart-5d197bc8-a248-46f2-94f8-627d6a076c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130104847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2130104847
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1603491958
Short name T178
Test name
Test status
Simulation time 173081284577 ps
CPU time 497.7 seconds
Started May 09 02:44:10 PM PDT 24
Finished May 09 02:52:32 PM PDT 24
Peak memory 238284 kb
Host smart-a9b106f8-45f4-4d60-bc5b-195d50856426
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603491958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1603491958
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.4012792212
Short name T136
Test name
Test status
Simulation time 2000719684 ps
CPU time 29.08 seconds
Started May 09 02:44:10 PM PDT 24
Finished May 09 02:44:43 PM PDT 24
Peak memory 216000 kb
Host smart-c19c0581-9e57-4694-8ebb-da6f4b713399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012792212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.4012792212
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3517924274
Short name T305
Test name
Test status
Simulation time 7942317627 ps
CPU time 29.95 seconds
Started May 09 02:44:10 PM PDT 24
Finished May 09 02:44:44 PM PDT 24
Peak memory 213196 kb
Host smart-901ab165-2800-41df-984b-fe20e14377ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3517924274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3517924274
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.538426353
Short name T82
Test name
Test status
Simulation time 6560002338 ps
CPU time 66.37 seconds
Started May 09 02:44:08 PM PDT 24
Finished May 09 02:45:17 PM PDT 24
Peak memory 217864 kb
Host smart-cbfeae50-25fb-4e22-be01-c1dd4d51612f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538426353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.538426353
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2684339726
Short name T129
Test name
Test status
Simulation time 12098397984 ps
CPU time 54.74 seconds
Started May 09 02:44:11 PM PDT 24
Finished May 09 02:45:10 PM PDT 24
Peak memory 218960 kb
Host smart-a4f006b1-c96f-4ba2-aa92-6e594a3063ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684339726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2684339726
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3568099993
Short name T155
Test name
Test status
Simulation time 2598903396 ps
CPU time 23.84 seconds
Started May 09 02:44:09 PM PDT 24
Finished May 09 02:44:36 PM PDT 24
Peak memory 211952 kb
Host smart-32030774-3879-4da0-b730-4e0e23597c3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568099993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3568099993
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1955367607
Short name T48
Test name
Test status
Simulation time 7302178384 ps
CPU time 155.79 seconds
Started May 09 02:44:11 PM PDT 24
Finished May 09 02:46:51 PM PDT 24
Peak memory 238440 kb
Host smart-3c57dcaf-f996-4247-9608-56dd4e08d971
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955367607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1955367607
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.499864348
Short name T161
Test name
Test status
Simulation time 22447878045 ps
CPU time 65.57 seconds
Started May 09 02:44:09 PM PDT 24
Finished May 09 02:45:18 PM PDT 24
Peak memory 215768 kb
Host smart-e6689635-b196-4de6-86d5-2f792bbe65a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499864348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.499864348
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2896410484
Short name T204
Test name
Test status
Simulation time 3356750028 ps
CPU time 29.53 seconds
Started May 09 02:44:10 PM PDT 24
Finished May 09 02:44:44 PM PDT 24
Peak memory 211968 kb
Host smart-b62e9600-8079-4f02-a9c6-ef0b6771adfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2896410484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2896410484
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2202629858
Short name T361
Test name
Test status
Simulation time 3975322269 ps
CPU time 46.3 seconds
Started May 09 02:44:09 PM PDT 24
Finished May 09 02:45:00 PM PDT 24
Peak memory 216456 kb
Host smart-1e0c5560-e6bd-47a0-8db3-0df2cd9226c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202629858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2202629858
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1099478117
Short name T317
Test name
Test status
Simulation time 3660198873 ps
CPU time 27.47 seconds
Started May 09 02:44:09 PM PDT 24
Finished May 09 02:44:40 PM PDT 24
Peak memory 214044 kb
Host smart-9230c0d0-a994-4e40-ae56-42e40b8dced0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099478117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1099478117
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1985543487
Short name T273
Test name
Test status
Simulation time 3424239141 ps
CPU time 14.12 seconds
Started May 09 02:44:09 PM PDT 24
Finished May 09 02:44:28 PM PDT 24
Peak memory 212000 kb
Host smart-c33d8f84-aa65-46e2-8645-cbf61925083f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985543487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1985543487
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1969398062
Short name T207
Test name
Test status
Simulation time 215526839591 ps
CPU time 561.48 seconds
Started May 09 02:44:09 PM PDT 24
Finished May 09 02:53:34 PM PDT 24
Peak memory 228616 kb
Host smart-485179eb-bf8e-4314-bf79-1d7d7c3a137d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969398062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1969398062
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3544075185
Short name T236
Test name
Test status
Simulation time 8267667261 ps
CPU time 66.41 seconds
Started May 09 02:44:09 PM PDT 24
Finished May 09 02:45:20 PM PDT 24
Peak memory 215732 kb
Host smart-01fd5a27-59a1-406b-9a52-3e44928b2528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544075185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3544075185
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4135729248
Short name T290
Test name
Test status
Simulation time 17398286336 ps
CPU time 35.8 seconds
Started May 09 02:44:13 PM PDT 24
Finished May 09 02:44:52 PM PDT 24
Peak memory 211792 kb
Host smart-48d8e1a7-216f-488f-a026-7432a4054a39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4135729248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4135729248
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2047376517
Short name T254
Test name
Test status
Simulation time 2091636752 ps
CPU time 33.08 seconds
Started May 09 02:44:11 PM PDT 24
Finished May 09 02:44:48 PM PDT 24
Peak memory 219804 kb
Host smart-bc4fff45-516f-4521-87f9-7e8459cd88b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047376517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2047376517
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3908349921
Short name T248
Test name
Test status
Simulation time 1851497598 ps
CPU time 12.37 seconds
Started May 09 02:44:09 PM PDT 24
Finished May 09 02:44:26 PM PDT 24
Peak memory 211876 kb
Host smart-64edcce9-67b9-4728-ace3-f98cc61a1de3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908349921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3908349921
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4036318635
Short name T357
Test name
Test status
Simulation time 58396171189 ps
CPU time 551.42 seconds
Started May 09 02:44:11 PM PDT 24
Finished May 09 02:53:27 PM PDT 24
Peak memory 240556 kb
Host smart-7335e342-3073-4817-ba0d-96f790d55427
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036318635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.4036318635
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2616793881
Short name T206
Test name
Test status
Simulation time 28998189055 ps
CPU time 64.28 seconds
Started May 09 02:44:10 PM PDT 24
Finished May 09 02:45:19 PM PDT 24
Peak memory 215604 kb
Host smart-7c02d75b-a06a-46f5-b797-601c6188ca31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616793881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2616793881
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3959369884
Short name T249
Test name
Test status
Simulation time 1675810257 ps
CPU time 13.21 seconds
Started May 09 02:44:10 PM PDT 24
Finished May 09 02:44:28 PM PDT 24
Peak memory 211824 kb
Host smart-bdc95a75-7da6-4629-8b31-05b9cad76d79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3959369884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3959369884
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3644546821
Short name T16
Test name
Test status
Simulation time 5293573793 ps
CPU time 59.2 seconds
Started May 09 02:44:14 PM PDT 24
Finished May 09 02:45:16 PM PDT 24
Peak memory 216896 kb
Host smart-d38b0d85-2ca8-45e5-b421-1a16bce6770a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644546821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3644546821
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2310408222
Short name T279
Test name
Test status
Simulation time 44163181831 ps
CPU time 134.78 seconds
Started May 09 02:44:09 PM PDT 24
Finished May 09 02:46:28 PM PDT 24
Peak memory 219996 kb
Host smart-4584431c-f921-456e-bef5-caf348612529
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310408222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2310408222
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.4000861128
Short name T152
Test name
Test status
Simulation time 6397860881 ps
CPU time 19.07 seconds
Started May 09 02:44:08 PM PDT 24
Finished May 09 02:44:29 PM PDT 24
Peak memory 211992 kb
Host smart-9b3eb417-31a1-4898-be94-75692bdfc7cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000861128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.4000861128
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.237418840
Short name T156
Test name
Test status
Simulation time 330103094657 ps
CPU time 674.18 seconds
Started May 09 02:44:09 PM PDT 24
Finished May 09 02:55:28 PM PDT 24
Peak memory 238428 kb
Host smart-908ba06d-0f4f-4d9a-858c-702e5b859c30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237418840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.237418840
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1904444277
Short name T306
Test name
Test status
Simulation time 4104556837 ps
CPU time 26 seconds
Started May 09 02:44:10 PM PDT 24
Finished May 09 02:44:41 PM PDT 24
Peak memory 215372 kb
Host smart-dd56e59c-c3cd-4d8e-8cf3-f2b541eb5d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904444277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1904444277
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.242013784
Short name T231
Test name
Test status
Simulation time 1222211718 ps
CPU time 14.93 seconds
Started May 09 02:44:10 PM PDT 24
Finished May 09 02:44:29 PM PDT 24
Peak memory 212048 kb
Host smart-8a01bc9c-faa0-4000-b049-3d9531933f82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=242013784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.242013784
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3034778917
Short name T252
Test name
Test status
Simulation time 1261423652 ps
CPU time 19.13 seconds
Started May 09 02:44:10 PM PDT 24
Finished May 09 02:44:34 PM PDT 24
Peak memory 217776 kb
Host smart-a9533ea8-8020-48bf-8ba2-0407ef87c545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034778917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3034778917
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3079225253
Short name T243
Test name
Test status
Simulation time 2082627514 ps
CPU time 40.03 seconds
Started May 09 02:44:10 PM PDT 24
Finished May 09 02:44:55 PM PDT 24
Peak memory 219860 kb
Host smart-6764f6c6-9f94-4362-ad82-5d9335b878d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079225253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3079225253
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1695388691
Short name T312
Test name
Test status
Simulation time 2341690619 ps
CPU time 22.39 seconds
Started May 09 02:44:21 PM PDT 24
Finished May 09 02:44:44 PM PDT 24
Peak memory 212352 kb
Host smart-6c51a351-8bce-4da7-aba8-eb6c3d12b545
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695388691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1695388691
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4244665747
Short name T208
Test name
Test status
Simulation time 27543131417 ps
CPU time 322.05 seconds
Started May 09 02:44:10 PM PDT 24
Finished May 09 02:49:36 PM PDT 24
Peak memory 241452 kb
Host smart-49688ac5-f239-40e6-bdf9-49e2f4b39bd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244665747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.4244665747
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2171151739
Short name T285
Test name
Test status
Simulation time 26868214956 ps
CPU time 33.8 seconds
Started May 09 02:44:09 PM PDT 24
Finished May 09 02:44:47 PM PDT 24
Peak memory 213396 kb
Host smart-c150d096-abee-4079-b5fa-63cfcb8544cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2171151739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2171151739
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2089236613
Short name T348
Test name
Test status
Simulation time 4118541486 ps
CPU time 37.6 seconds
Started May 09 02:44:09 PM PDT 24
Finished May 09 02:44:51 PM PDT 24
Peak memory 217244 kb
Host smart-97f73b29-e572-426a-8f48-650fa385d6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089236613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2089236613
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1972437581
Short name T164
Test name
Test status
Simulation time 4110046755 ps
CPU time 61.3 seconds
Started May 09 02:44:11 PM PDT 24
Finished May 09 02:45:16 PM PDT 24
Peak memory 219876 kb
Host smart-21ee2604-64f5-4beb-9cd2-54b359d424e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972437581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1972437581
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.170900365
Short name T315
Test name
Test status
Simulation time 2352917122 ps
CPU time 8.34 seconds
Started May 09 02:44:13 PM PDT 24
Finished May 09 02:44:25 PM PDT 24
Peak memory 212040 kb
Host smart-fe073ad6-c888-4375-88a4-5a59373549b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170900365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.170900365
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.4124046149
Short name T263
Test name
Test status
Simulation time 3744069476 ps
CPU time 268.4 seconds
Started May 09 02:44:13 PM PDT 24
Finished May 09 02:48:45 PM PDT 24
Peak memory 238352 kb
Host smart-3dca074d-6b56-4ecf-ab39-1a6e91d660fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124046149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.4124046149
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.724738341
Short name T38
Test name
Test status
Simulation time 65600908147 ps
CPU time 66.63 seconds
Started May 09 02:44:16 PM PDT 24
Finished May 09 02:45:26 PM PDT 24
Peak memory 215604 kb
Host smart-66bee7bd-2b47-42a7-a9a1-b23d01440843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724738341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.724738341
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3803229876
Short name T335
Test name
Test status
Simulation time 1464595218 ps
CPU time 18.93 seconds
Started May 09 02:44:13 PM PDT 24
Finished May 09 02:44:35 PM PDT 24
Peak memory 212736 kb
Host smart-55a1de5e-09b4-404e-8b8f-1a50dc503108
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3803229876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3803229876
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.357616922
Short name T126
Test name
Test status
Simulation time 6139709085 ps
CPU time 54.37 seconds
Started May 09 02:44:13 PM PDT 24
Finished May 09 02:45:11 PM PDT 24
Peak memory 215668 kb
Host smart-ade205df-7de2-42a1-a603-a52f704ed339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357616922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.357616922
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1381764403
Short name T159
Test name
Test status
Simulation time 80342207807 ps
CPU time 185.94 seconds
Started May 09 02:44:21 PM PDT 24
Finished May 09 02:47:29 PM PDT 24
Peak memory 230580 kb
Host smart-0dc23481-062b-47fb-aaab-40ad6b6277d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381764403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1381764403
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3103325395
Short name T59
Test name
Test status
Simulation time 3692151130 ps
CPU time 30.04 seconds
Started May 09 02:44:19 PM PDT 24
Finished May 09 02:44:51 PM PDT 24
Peak memory 212468 kb
Host smart-951c0f3d-7e91-4b11-a4aa-040d8dd8017b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103325395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3103325395
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3275414199
Short name T241
Test name
Test status
Simulation time 60689310321 ps
CPU time 308.68 seconds
Started May 09 02:44:11 PM PDT 24
Finished May 09 02:49:24 PM PDT 24
Peak memory 240788 kb
Host smart-54223594-1280-4177-a8ad-c0950ae3f219
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275414199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3275414199
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.502881942
Short name T143
Test name
Test status
Simulation time 8358321034 ps
CPU time 65.42 seconds
Started May 09 02:44:09 PM PDT 24
Finished May 09 02:45:18 PM PDT 24
Peak memory 215884 kb
Host smart-ffce2e6c-a303-4fae-be22-d728168a8a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502881942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.502881942
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1172469402
Short name T179
Test name
Test status
Simulation time 43452721316 ps
CPU time 34.5 seconds
Started May 09 02:44:15 PM PDT 24
Finished May 09 02:44:53 PM PDT 24
Peak memory 213296 kb
Host smart-49f37b40-6db7-4659-add5-798b27c3c4e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1172469402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1172469402
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3251119726
Short name T194
Test name
Test status
Simulation time 31601944952 ps
CPU time 71.62 seconds
Started May 09 02:44:13 PM PDT 24
Finished May 09 02:45:28 PM PDT 24
Peak memory 218508 kb
Host smart-79ebcdbb-0d7b-4f81-b60e-2e3d702333a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251119726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3251119726
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.31630224
Short name T288
Test name
Test status
Simulation time 5741212421 ps
CPU time 77.18 seconds
Started May 09 02:44:13 PM PDT 24
Finished May 09 02:45:34 PM PDT 24
Peak memory 215816 kb
Host smart-fc3d8775-9515-4ced-ad7d-22fa2f7293dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31630224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 19.rom_ctrl_stress_all.31630224
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3945587710
Short name T168
Test name
Test status
Simulation time 14355338113 ps
CPU time 30.86 seconds
Started May 09 02:43:45 PM PDT 24
Finished May 09 02:44:19 PM PDT 24
Peak memory 212740 kb
Host smart-9d92e007-d93b-4acf-9115-5e45bad04dfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945587710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3945587710
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3854539723
Short name T172
Test name
Test status
Simulation time 171931976957 ps
CPU time 338.47 seconds
Started May 09 02:43:45 PM PDT 24
Finished May 09 02:49:27 PM PDT 24
Peak memory 239848 kb
Host smart-9ef5090b-612e-4809-8339-09ae482afd2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854539723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3854539723
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3956890937
Short name T295
Test name
Test status
Simulation time 4617023446 ps
CPU time 46.39 seconds
Started May 09 02:43:47 PM PDT 24
Finished May 09 02:44:36 PM PDT 24
Peak memory 215756 kb
Host smart-6fdf5d96-f3bb-4bda-aef6-42c639c0b67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956890937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3956890937
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.413026080
Short name T257
Test name
Test status
Simulation time 5835157131 ps
CPU time 19.24 seconds
Started May 09 02:43:46 PM PDT 24
Finished May 09 02:44:08 PM PDT 24
Peak memory 212332 kb
Host smart-e13187b7-323b-4299-a51c-d99dae2e1e43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=413026080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.413026080
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3228361356
Short name T33
Test name
Test status
Simulation time 1024031757 ps
CPU time 123.8 seconds
Started May 09 02:43:44 PM PDT 24
Finished May 09 02:45:51 PM PDT 24
Peak memory 238868 kb
Host smart-8de44e16-d23c-42cc-8330-de187e1bcd10
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228361356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3228361356
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2798414085
Short name T150
Test name
Test status
Simulation time 2958005038 ps
CPU time 38.8 seconds
Started May 09 02:43:43 PM PDT 24
Finished May 09 02:44:25 PM PDT 24
Peak memory 217708 kb
Host smart-3448bedf-c9f9-4b99-b491-4fc8e2220d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798414085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2798414085
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.990676294
Short name T192
Test name
Test status
Simulation time 728031502 ps
CPU time 43.36 seconds
Started May 09 02:43:45 PM PDT 24
Finished May 09 02:44:32 PM PDT 24
Peak memory 219868 kb
Host smart-848b65e3-257f-49ed-bb07-ccf3b87962f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990676294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.990676294
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3960903687
Short name T185
Test name
Test status
Simulation time 338445372 ps
CPU time 8.29 seconds
Started May 09 02:44:21 PM PDT 24
Finished May 09 02:44:32 PM PDT 24
Peak memory 211876 kb
Host smart-c1499de7-14b1-4ac7-9ef8-5245627024ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960903687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3960903687
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.314145884
Short name T25
Test name
Test status
Simulation time 7261412811 ps
CPU time 237.93 seconds
Started May 09 02:44:17 PM PDT 24
Finished May 09 02:48:18 PM PDT 24
Peak memory 234416 kb
Host smart-96a45b2c-da61-43b7-b49f-5542eab55538
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314145884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.314145884
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2766008425
Short name T255
Test name
Test status
Simulation time 13201164976 ps
CPU time 28.91 seconds
Started May 09 02:44:12 PM PDT 24
Finished May 09 02:44:45 PM PDT 24
Peak memory 211936 kb
Host smart-360639b8-c804-4095-8e29-f376e043a558
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2766008425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2766008425
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2845183775
Short name T83
Test name
Test status
Simulation time 27751372036 ps
CPU time 61.25 seconds
Started May 09 02:44:12 PM PDT 24
Finished May 09 02:45:17 PM PDT 24
Peak memory 218324 kb
Host smart-31e48d8a-2033-4eba-a627-cca071164c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845183775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2845183775
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.267743847
Short name T58
Test name
Test status
Simulation time 387787385 ps
CPU time 20.41 seconds
Started May 09 02:44:14 PM PDT 24
Finished May 09 02:44:38 PM PDT 24
Peak memory 218656 kb
Host smart-1e4e7a68-c286-4266-a727-cd232c9ef119
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267743847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.267743847
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3469866095
Short name T50
Test name
Test status
Simulation time 63709072944 ps
CPU time 1034.13 seconds
Started May 09 02:44:21 PM PDT 24
Finished May 09 03:01:36 PM PDT 24
Peak memory 232420 kb
Host smart-b0ff902d-d7ac-4d6c-9ba4-75c9f3c4815c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469866095 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.3469866095
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3341022117
Short name T148
Test name
Test status
Simulation time 13192336183 ps
CPU time 25.2 seconds
Started May 09 02:44:13 PM PDT 24
Finished May 09 02:44:42 PM PDT 24
Peak memory 212040 kb
Host smart-53b4b860-977e-4f39-8139-2d7337ab55a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341022117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3341022117
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2781821330
Short name T220
Test name
Test status
Simulation time 103239038198 ps
CPU time 714.07 seconds
Started May 09 02:44:17 PM PDT 24
Finished May 09 02:56:14 PM PDT 24
Peak memory 240780 kb
Host smart-6e3b21fe-40e7-4e2b-8484-304433acb262
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781821330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2781821330
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3566349835
Short name T70
Test name
Test status
Simulation time 3412112650 ps
CPU time 24.72 seconds
Started May 09 02:44:21 PM PDT 24
Finished May 09 02:44:47 PM PDT 24
Peak memory 214248 kb
Host smart-64e4a22e-db8f-4b7b-bfe5-8c8d8c250235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566349835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3566349835
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3557949932
Short name T334
Test name
Test status
Simulation time 875049053 ps
CPU time 13.39 seconds
Started May 09 02:44:19 PM PDT 24
Finished May 09 02:44:35 PM PDT 24
Peak memory 212012 kb
Host smart-202c9537-272a-4e31-b96e-41ed3d527fe8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3557949932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3557949932
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3440517224
Short name T177
Test name
Test status
Simulation time 12385517587 ps
CPU time 55.57 seconds
Started May 09 02:44:14 PM PDT 24
Finished May 09 02:45:13 PM PDT 24
Peak memory 218644 kb
Host smart-e6762115-13e9-4c91-b656-5f88f0684c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440517224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3440517224
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2753026887
Short name T174
Test name
Test status
Simulation time 898663495 ps
CPU time 14.78 seconds
Started May 09 02:44:23 PM PDT 24
Finished May 09 02:44:40 PM PDT 24
Peak memory 211876 kb
Host smart-1149eb00-4099-4fb1-89b4-2e9fd7d73b2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753026887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2753026887
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.539595317
Short name T283
Test name
Test status
Simulation time 91460200730 ps
CPU time 569.48 seconds
Started May 09 02:44:21 PM PDT 24
Finished May 09 02:53:54 PM PDT 24
Peak memory 239704 kb
Host smart-338c34fc-670c-4ff9-a610-e55e920f55a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539595317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.539595317
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2845612906
Short name T183
Test name
Test status
Simulation time 1376461044 ps
CPU time 19.22 seconds
Started May 09 02:44:23 PM PDT 24
Finished May 09 02:44:45 PM PDT 24
Peak memory 215212 kb
Host smart-ba0ab868-adeb-4dcb-a5a4-ce0c2080188f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845612906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2845612906
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1985314129
Short name T235
Test name
Test status
Simulation time 348005778 ps
CPU time 20.94 seconds
Started May 09 02:44:17 PM PDT 24
Finished May 09 02:44:41 PM PDT 24
Peak memory 218168 kb
Host smart-f54ea348-78ef-40db-bacd-36cfc0c72780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985314129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1985314129
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.449402398
Short name T142
Test name
Test status
Simulation time 41102869842 ps
CPU time 163.96 seconds
Started May 09 02:44:22 PM PDT 24
Finished May 09 02:47:09 PM PDT 24
Peak memory 222960 kb
Host smart-274e38c1-2c78-446b-98b7-7bed8135aa78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449402398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.449402398
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2521473070
Short name T51
Test name
Test status
Simulation time 19539061849 ps
CPU time 5735.37 seconds
Started May 09 02:44:22 PM PDT 24
Finished May 09 04:20:01 PM PDT 24
Peak memory 236476 kb
Host smart-d64baee1-b1db-40ab-b033-1659ed2c93c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521473070 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2521473070
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1245936859
Short name T151
Test name
Test status
Simulation time 2293831579 ps
CPU time 22.69 seconds
Started May 09 02:44:23 PM PDT 24
Finished May 09 02:44:49 PM PDT 24
Peak memory 211932 kb
Host smart-fc03353e-79cf-492f-a191-151449be6ceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245936859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1245936859
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3775091900
Short name T163
Test name
Test status
Simulation time 59345858672 ps
CPU time 248.21 seconds
Started May 09 02:44:26 PM PDT 24
Finished May 09 02:48:36 PM PDT 24
Peak memory 217252 kb
Host smart-ed056537-d5d7-4189-9aac-75990effc928
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775091900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3775091900
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3676767639
Short name T266
Test name
Test status
Simulation time 4882061060 ps
CPU time 47.89 seconds
Started May 09 02:44:23 PM PDT 24
Finished May 09 02:45:13 PM PDT 24
Peak memory 215588 kb
Host smart-706daca7-b5e0-4740-8785-e03c839e54f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676767639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3676767639
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.155495408
Short name T325
Test name
Test status
Simulation time 5531585954 ps
CPU time 14.97 seconds
Started May 09 02:44:21 PM PDT 24
Finished May 09 02:44:39 PM PDT 24
Peak memory 212356 kb
Host smart-de677b49-a126-4763-85af-1e3f4914e1ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=155495408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.155495408
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2444410771
Short name T170
Test name
Test status
Simulation time 17405755735 ps
CPU time 41.77 seconds
Started May 09 02:44:22 PM PDT 24
Finished May 09 02:45:06 PM PDT 24
Peak memory 218748 kb
Host smart-c676c65e-8e68-4563-bd41-0fb5c6f79744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444410771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2444410771
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3302253100
Short name T316
Test name
Test status
Simulation time 10650813772 ps
CPU time 118.28 seconds
Started May 09 02:44:22 PM PDT 24
Finished May 09 02:46:23 PM PDT 24
Peak memory 221940 kb
Host smart-f7ef2cf1-046b-43a5-b8f4-c83531c1729b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302253100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3302253100
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1569232006
Short name T229
Test name
Test status
Simulation time 970723262 ps
CPU time 8.45 seconds
Started May 09 02:44:26 PM PDT 24
Finished May 09 02:44:36 PM PDT 24
Peak memory 211716 kb
Host smart-99c63055-d283-4da8-b5d1-eb94bccb9821
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569232006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1569232006
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4084576288
Short name T4
Test name
Test status
Simulation time 4238834510 ps
CPU time 42.49 seconds
Started May 09 02:44:28 PM PDT 24
Finished May 09 02:45:11 PM PDT 24
Peak memory 215832 kb
Host smart-271ea750-4f81-462e-b3ce-e42e31936f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084576288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4084576288
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.224960794
Short name T198
Test name
Test status
Simulation time 2477394793 ps
CPU time 25.04 seconds
Started May 09 02:44:22 PM PDT 24
Finished May 09 02:44:50 PM PDT 24
Peak memory 212028 kb
Host smart-36e2e0d8-d699-4c27-a37e-7216d637b6d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=224960794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.224960794
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3260742050
Short name T180
Test name
Test status
Simulation time 5305810950 ps
CPU time 56.96 seconds
Started May 09 02:44:29 PM PDT 24
Finished May 09 02:45:26 PM PDT 24
Peak memory 215632 kb
Host smart-83a92b53-4f37-405f-b055-55dffc848068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260742050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3260742050
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2949444272
Short name T130
Test name
Test status
Simulation time 23212756135 ps
CPU time 59.78 seconds
Started May 09 02:44:22 PM PDT 24
Finished May 09 02:45:24 PM PDT 24
Peak memory 218640 kb
Host smart-dc68b3a1-7ed5-46e7-96ef-ee495f791ba9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949444272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2949444272
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1305501813
Short name T292
Test name
Test status
Simulation time 2931754465 ps
CPU time 24.91 seconds
Started May 09 02:44:23 PM PDT 24
Finished May 09 02:44:50 PM PDT 24
Peak memory 212524 kb
Host smart-5fc01c8b-2913-40b9-a436-86776ccdd9f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305501813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1305501813
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2501111453
Short name T108
Test name
Test status
Simulation time 137713901724 ps
CPU time 350.2 seconds
Started May 09 02:44:22 PM PDT 24
Finished May 09 02:50:15 PM PDT 24
Peak memory 238416 kb
Host smart-16b523f6-631a-46fc-896c-4f84da895bca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501111453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2501111453
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3652765765
Short name T211
Test name
Test status
Simulation time 5592528760 ps
CPU time 52.55 seconds
Started May 09 02:44:22 PM PDT 24
Finished May 09 02:45:17 PM PDT 24
Peak memory 216252 kb
Host smart-a4a48be4-53d6-4f15-9d89-e3fc5d093e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652765765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3652765765
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.397855022
Short name T43
Test name
Test status
Simulation time 789626146 ps
CPU time 15.39 seconds
Started May 09 02:44:23 PM PDT 24
Finished May 09 02:44:41 PM PDT 24
Peak memory 212880 kb
Host smart-378ea521-bb29-447b-bda3-427edd62c091
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=397855022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.397855022
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1253053111
Short name T327
Test name
Test status
Simulation time 6466107350 ps
CPU time 43.69 seconds
Started May 09 02:44:22 PM PDT 24
Finished May 09 02:45:08 PM PDT 24
Peak memory 219192 kb
Host smart-7fc974e5-f455-4724-afe4-1637016ceb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253053111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1253053111
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2846469721
Short name T232
Test name
Test status
Simulation time 548349271 ps
CPU time 36.12 seconds
Started May 09 02:44:22 PM PDT 24
Finished May 09 02:45:01 PM PDT 24
Peak memory 219352 kb
Host smart-e2e92302-0f45-447a-b2c5-29ef05e6c663
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846469721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2846469721
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1767996252
Short name T68
Test name
Test status
Simulation time 689124601 ps
CPU time 8.28 seconds
Started May 09 02:44:31 PM PDT 24
Finished May 09 02:44:42 PM PDT 24
Peak memory 211864 kb
Host smart-20925e46-fddf-48fa-912d-7a5dd16dd513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767996252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1767996252
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3459011343
Short name T15
Test name
Test status
Simulation time 336085774468 ps
CPU time 793.1 seconds
Started May 09 02:44:23 PM PDT 24
Finished May 09 02:57:39 PM PDT 24
Peak memory 240832 kb
Host smart-ce8c54b8-0df1-4687-babc-ecadbcaa0477
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459011343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3459011343
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3145335732
Short name T27
Test name
Test status
Simulation time 50810439249 ps
CPU time 50.75 seconds
Started May 09 02:44:32 PM PDT 24
Finished May 09 02:45:25 PM PDT 24
Peak memory 215704 kb
Host smart-57964dda-a7b8-4cc8-933c-7f99e872d1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145335732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3145335732
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1336272114
Short name T275
Test name
Test status
Simulation time 353781295 ps
CPU time 10.55 seconds
Started May 09 02:44:23 PM PDT 24
Finished May 09 02:44:36 PM PDT 24
Peak memory 212124 kb
Host smart-c9e087c3-4a97-40ca-a788-fc88ef12f0cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1336272114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1336272114
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2563714037
Short name T345
Test name
Test status
Simulation time 17084335495 ps
CPU time 45.49 seconds
Started May 09 02:44:22 PM PDT 24
Finished May 09 02:45:10 PM PDT 24
Peak memory 218288 kb
Host smart-c9ac60a6-f0c3-4c3f-9777-ba4554bdb767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563714037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2563714037
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3050354441
Short name T354
Test name
Test status
Simulation time 3332996608 ps
CPU time 28.14 seconds
Started May 09 02:44:32 PM PDT 24
Finished May 09 02:45:03 PM PDT 24
Peak memory 212556 kb
Host smart-ec6ea3f6-8d36-4a01-aa5a-261b48d5e2d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050354441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3050354441
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2315427672
Short name T176
Test name
Test status
Simulation time 91598072699 ps
CPU time 948.73 seconds
Started May 09 02:44:31 PM PDT 24
Finished May 09 03:00:21 PM PDT 24
Peak memory 218520 kb
Host smart-a7a7b82b-4371-4937-b3bf-f74b20b7cda5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315427672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2315427672
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.229895908
Short name T291
Test name
Test status
Simulation time 19290197457 ps
CPU time 50.14 seconds
Started May 09 02:44:33 PM PDT 24
Finished May 09 02:45:25 PM PDT 24
Peak memory 215908 kb
Host smart-9c707ba3-2772-4b22-9738-c631c7439f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229895908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.229895908
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3322538619
Short name T157
Test name
Test status
Simulation time 3713732677 ps
CPU time 33.58 seconds
Started May 09 02:44:34 PM PDT 24
Finished May 09 02:45:10 PM PDT 24
Peak memory 213204 kb
Host smart-41e02e6e-f99a-4a6f-a744-75bd7c2549ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3322538619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3322538619
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1114958890
Short name T319
Test name
Test status
Simulation time 1820527119 ps
CPU time 33.78 seconds
Started May 09 02:44:34 PM PDT 24
Finished May 09 02:45:10 PM PDT 24
Peak memory 214968 kb
Host smart-d0c761b7-57c9-496f-ad5e-4cf6909929c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114958890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1114958890
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1445887187
Short name T81
Test name
Test status
Simulation time 896074124 ps
CPU time 51.8 seconds
Started May 09 02:44:31 PM PDT 24
Finished May 09 02:45:24 PM PDT 24
Peak memory 220364 kb
Host smart-ca9d5553-5258-400f-9b22-a03f6732d0bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445887187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1445887187
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3083763079
Short name T341
Test name
Test status
Simulation time 8425991044 ps
CPU time 33.82 seconds
Started May 09 02:44:35 PM PDT 24
Finished May 09 02:45:11 PM PDT 24
Peak memory 212792 kb
Host smart-71f1837b-e3cf-4784-9844-f08630dc4856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083763079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3083763079
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3793931049
Short name T309
Test name
Test status
Simulation time 51194758502 ps
CPU time 500.88 seconds
Started May 09 02:44:31 PM PDT 24
Finished May 09 02:52:54 PM PDT 24
Peak memory 238216 kb
Host smart-50154f06-d94c-46b4-9ca8-3f480fa8db49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793931049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3793931049
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1055705586
Short name T233
Test name
Test status
Simulation time 1716193367 ps
CPU time 30.28 seconds
Started May 09 02:44:32 PM PDT 24
Finished May 09 02:45:05 PM PDT 24
Peak memory 215432 kb
Host smart-23186ffd-2c46-405a-97ed-462c0b33c4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055705586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1055705586
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.563302059
Short name T358
Test name
Test status
Simulation time 17916714246 ps
CPU time 34.59 seconds
Started May 09 02:44:31 PM PDT 24
Finished May 09 02:45:08 PM PDT 24
Peak memory 211912 kb
Host smart-20d72a50-edff-4af8-a771-88661ccd6d8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=563302059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.563302059
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3212691839
Short name T12
Test name
Test status
Simulation time 16095244725 ps
CPU time 82.58 seconds
Started May 09 02:44:35 PM PDT 24
Finished May 09 02:46:00 PM PDT 24
Peak memory 218968 kb
Host smart-9e9decd6-c456-4a6f-a2a1-7c1a0f6d2969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212691839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3212691839
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1130288997
Short name T131
Test name
Test status
Simulation time 25648779607 ps
CPU time 79.36 seconds
Started May 09 02:44:33 PM PDT 24
Finished May 09 02:45:55 PM PDT 24
Peak memory 217788 kb
Host smart-6a80ea4a-2bb9-4401-b731-3290123672f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130288997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1130288997
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3691351105
Short name T132
Test name
Test status
Simulation time 9908029480 ps
CPU time 22.66 seconds
Started May 09 02:44:45 PM PDT 24
Finished May 09 02:45:12 PM PDT 24
Peak memory 211968 kb
Host smart-c703ae69-7151-46b0-8ec0-56ca90449330
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691351105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3691351105
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2909111268
Short name T267
Test name
Test status
Simulation time 167927131745 ps
CPU time 366.42 seconds
Started May 09 02:44:35 PM PDT 24
Finished May 09 02:50:43 PM PDT 24
Peak memory 240592 kb
Host smart-a80b83e6-6f4e-4fa3-9a1f-f46732573f19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909111268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2909111268
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3927941706
Short name T175
Test name
Test status
Simulation time 34212785666 ps
CPU time 66.24 seconds
Started May 09 02:44:31 PM PDT 24
Finished May 09 02:45:40 PM PDT 24
Peak memory 215688 kb
Host smart-71b03d59-6452-4378-a090-213761b57078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927941706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3927941706
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.954531209
Short name T40
Test name
Test status
Simulation time 3465833401 ps
CPU time 30.15 seconds
Started May 09 02:44:33 PM PDT 24
Finished May 09 02:45:06 PM PDT 24
Peak memory 212888 kb
Host smart-a63bf070-9cda-459f-b08f-2b4f26a67f18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=954531209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.954531209
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3924474776
Short name T60
Test name
Test status
Simulation time 16460040514 ps
CPU time 41.89 seconds
Started May 09 02:44:35 PM PDT 24
Finished May 09 02:45:19 PM PDT 24
Peak memory 218508 kb
Host smart-21e7520a-e49d-4bb0-aab5-cbac7110a571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924474776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3924474776
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.4277068299
Short name T260
Test name
Test status
Simulation time 22405066403 ps
CPU time 62.8 seconds
Started May 09 02:44:32 PM PDT 24
Finished May 09 02:45:37 PM PDT 24
Peak memory 219980 kb
Host smart-7cc8a0c6-a1d1-42c1-b643-0d615b7382db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277068299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.4277068299
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1361895220
Short name T256
Test name
Test status
Simulation time 7728744485 ps
CPU time 31.37 seconds
Started May 09 02:43:45 PM PDT 24
Finished May 09 02:44:19 PM PDT 24
Peak memory 212816 kb
Host smart-1e797f6a-654e-4bec-a18d-98d7dffc3602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361895220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1361895220
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2238832583
Short name T230
Test name
Test status
Simulation time 7740652878 ps
CPU time 243.61 seconds
Started May 09 02:43:44 PM PDT 24
Finished May 09 02:47:50 PM PDT 24
Peak memory 234404 kb
Host smart-bdf04010-6d97-4534-b9b0-5dff9c4646ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238832583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2238832583
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.103818573
Short name T140
Test name
Test status
Simulation time 2242774208 ps
CPU time 33.91 seconds
Started May 09 02:43:47 PM PDT 24
Finished May 09 02:44:24 PM PDT 24
Peak memory 215416 kb
Host smart-e71e3958-9dc4-473f-89ab-20f0660cfb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103818573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.103818573
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3724105548
Short name T186
Test name
Test status
Simulation time 5160234496 ps
CPU time 18.87 seconds
Started May 09 02:43:45 PM PDT 24
Finished May 09 02:44:07 PM PDT 24
Peak memory 213400 kb
Host smart-14454467-50f6-4529-8bf9-87e137ec7446
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3724105548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3724105548
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.532296048
Short name T30
Test name
Test status
Simulation time 6642634448 ps
CPU time 242.36 seconds
Started May 09 02:43:44 PM PDT 24
Finished May 09 02:47:50 PM PDT 24
Peak memory 239116 kb
Host smart-781c6807-d4ac-4367-9509-8e84a92477c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532296048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.532296048
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.305653648
Short name T147
Test name
Test status
Simulation time 2929026145 ps
CPU time 38.3 seconds
Started May 09 02:43:46 PM PDT 24
Finished May 09 02:44:27 PM PDT 24
Peak memory 216392 kb
Host smart-badbe5c8-2d0e-4410-8aa8-9c5deaecdadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305653648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.305653648
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1838687376
Short name T240
Test name
Test status
Simulation time 28804293556 ps
CPU time 160.08 seconds
Started May 09 02:43:43 PM PDT 24
Finished May 09 02:46:26 PM PDT 24
Peak memory 228204 kb
Host smart-d1a57bca-e969-4216-ba52-fa8e0757ea68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838687376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1838687376
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3629860695
Short name T278
Test name
Test status
Simulation time 13989937487 ps
CPU time 28.81 seconds
Started May 09 02:44:44 PM PDT 24
Finished May 09 02:45:17 PM PDT 24
Peak memory 212740 kb
Host smart-2ccc1494-f2cf-4f0e-bf69-844436dcfd0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629860695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3629860695
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2948655656
Short name T310
Test name
Test status
Simulation time 112206372005 ps
CPU time 518.13 seconds
Started May 09 02:44:43 PM PDT 24
Finished May 09 02:53:25 PM PDT 24
Peak memory 217912 kb
Host smart-a2855e9b-7692-4d54-a61e-bffa56a462e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948655656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2948655656
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2912856228
Short name T216
Test name
Test status
Simulation time 677326377 ps
CPU time 19.07 seconds
Started May 09 02:44:46 PM PDT 24
Finished May 09 02:45:08 PM PDT 24
Peak memory 216056 kb
Host smart-ea487066-23d3-4b15-ad74-939b39f0d4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912856228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2912856228
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.412426079
Short name T356
Test name
Test status
Simulation time 4660941170 ps
CPU time 23.62 seconds
Started May 09 02:44:43 PM PDT 24
Finished May 09 02:45:10 PM PDT 24
Peak memory 212372 kb
Host smart-56d11aee-a82d-4c7f-beed-efc50a5ad0e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=412426079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.412426079
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3226457192
Short name T329
Test name
Test status
Simulation time 1322413981 ps
CPU time 20.4 seconds
Started May 09 02:44:47 PM PDT 24
Finished May 09 02:45:11 PM PDT 24
Peak memory 217572 kb
Host smart-942083e6-7025-4f92-bccb-ce529aba7368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226457192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3226457192
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3195165250
Short name T342
Test name
Test status
Simulation time 25848144674 ps
CPU time 122.84 seconds
Started May 09 02:44:45 PM PDT 24
Finished May 09 02:46:52 PM PDT 24
Peak memory 219404 kb
Host smart-e87ef56d-cccf-4967-9f27-f3f8830719b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195165250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3195165250
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.719069317
Short name T158
Test name
Test status
Simulation time 8499181352 ps
CPU time 32.47 seconds
Started May 09 02:44:42 PM PDT 24
Finished May 09 02:45:18 PM PDT 24
Peak memory 212772 kb
Host smart-af89c15d-fa2b-431f-a794-60a19d1274d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719069317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.719069317
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2933592395
Short name T314
Test name
Test status
Simulation time 11675265115 ps
CPU time 262.35 seconds
Started May 09 02:44:47 PM PDT 24
Finished May 09 02:49:12 PM PDT 24
Peak memory 216684 kb
Host smart-db533e82-99e7-458b-8d0b-b6e661b60fcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933592395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2933592395
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.4262185730
Short name T227
Test name
Test status
Simulation time 5118235238 ps
CPU time 46.98 seconds
Started May 09 02:44:48 PM PDT 24
Finished May 09 02:45:39 PM PDT 24
Peak memory 215628 kb
Host smart-93f8c23f-6cf5-43c1-a385-1146f13321f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262185730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.4262185730
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1157186285
Short name T141
Test name
Test status
Simulation time 3526997268 ps
CPU time 29.77 seconds
Started May 09 02:44:45 PM PDT 24
Finished May 09 02:45:18 PM PDT 24
Peak memory 212956 kb
Host smart-49f6fb01-bb2f-4e87-a7a4-fa63309302e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1157186285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1157186285
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2411554743
Short name T13
Test name
Test status
Simulation time 1180026628 ps
CPU time 27.67 seconds
Started May 09 02:44:47 PM PDT 24
Finished May 09 02:45:19 PM PDT 24
Peak memory 217352 kb
Host smart-bc1f0b74-ebc2-434e-8c1c-eab815397e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411554743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2411554743
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3078739775
Short name T200
Test name
Test status
Simulation time 7303567661 ps
CPU time 40.77 seconds
Started May 09 02:44:42 PM PDT 24
Finished May 09 02:45:26 PM PDT 24
Peak memory 214768 kb
Host smart-0e68a9fe-b10c-4504-809d-5b1fb0ab95c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078739775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3078739775
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2214819498
Short name T321
Test name
Test status
Simulation time 1169795313 ps
CPU time 12.36 seconds
Started May 09 02:44:46 PM PDT 24
Finished May 09 02:45:02 PM PDT 24
Peak memory 211852 kb
Host smart-01f443ca-c142-4326-8152-d8517fe0b10f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214819498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2214819498
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2765408138
Short name T224
Test name
Test status
Simulation time 44537928040 ps
CPU time 442.18 seconds
Started May 09 02:44:46 PM PDT 24
Finished May 09 02:52:12 PM PDT 24
Peak memory 217352 kb
Host smart-faf30eb4-873b-41a0-8e70-3141f39970b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765408138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2765408138
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.603587603
Short name T362
Test name
Test status
Simulation time 346023100 ps
CPU time 19.47 seconds
Started May 09 02:44:45 PM PDT 24
Finished May 09 02:45:09 PM PDT 24
Peak memory 215320 kb
Host smart-7aec00f9-3f05-4462-94f8-0a39ee1b46b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603587603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.603587603
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.52457136
Short name T218
Test name
Test status
Simulation time 3875813652 ps
CPU time 31.19 seconds
Started May 09 02:44:43 PM PDT 24
Finished May 09 02:45:18 PM PDT 24
Peak memory 212060 kb
Host smart-bd82c7b9-47c4-45d6-bb6a-a730da5f8bd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=52457136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.52457136
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1592377463
Short name T238
Test name
Test status
Simulation time 11677587457 ps
CPU time 41.15 seconds
Started May 09 02:44:43 PM PDT 24
Finished May 09 02:45:27 PM PDT 24
Peak memory 214892 kb
Host smart-ee2a9b9a-8678-441c-8d71-6ef66ef5c4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592377463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1592377463
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.505072091
Short name T322
Test name
Test status
Simulation time 31739326799 ps
CPU time 95.02 seconds
Started May 09 02:44:46 PM PDT 24
Finished May 09 02:46:25 PM PDT 24
Peak memory 221412 kb
Host smart-07f4824e-98a9-4889-80d2-193552952ac5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505072091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.505072091
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.398783541
Short name T355
Test name
Test status
Simulation time 23209956999 ps
CPU time 26.03 seconds
Started May 09 02:44:52 PM PDT 24
Finished May 09 02:45:23 PM PDT 24
Peak memory 211944 kb
Host smart-0d4462cd-220a-49f8-b78a-1a7c22e3f295
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398783541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.398783541
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1981957348
Short name T320
Test name
Test status
Simulation time 12582220622 ps
CPU time 223.57 seconds
Started May 09 02:44:47 PM PDT 24
Finished May 09 02:48:35 PM PDT 24
Peak memory 234344 kb
Host smart-9460a896-3eec-4702-ae91-b139344a4f4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981957348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1981957348
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.329020274
Short name T134
Test name
Test status
Simulation time 5321158029 ps
CPU time 51.64 seconds
Started May 09 02:44:54 PM PDT 24
Finished May 09 02:45:50 PM PDT 24
Peak memory 215616 kb
Host smart-d44c90e3-6585-4900-a1b1-b10f72f1c0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329020274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.329020274
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.311995401
Short name T234
Test name
Test status
Simulation time 3943117275 ps
CPU time 32.53 seconds
Started May 09 02:44:48 PM PDT 24
Finished May 09 02:45:24 PM PDT 24
Peak memory 211960 kb
Host smart-11063bbd-186e-4843-b6d5-cc5b0d9fb1d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=311995401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.311995401
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3861827254
Short name T304
Test name
Test status
Simulation time 13400696869 ps
CPU time 54.23 seconds
Started May 09 02:44:45 PM PDT 24
Finished May 09 02:45:43 PM PDT 24
Peak memory 217540 kb
Host smart-e0982f8f-02a6-4e5f-a83c-667bab187d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861827254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3861827254
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1313571396
Short name T146
Test name
Test status
Simulation time 946521727 ps
CPU time 12.52 seconds
Started May 09 02:44:46 PM PDT 24
Finished May 09 02:45:02 PM PDT 24
Peak memory 211816 kb
Host smart-bb9fb438-7c52-48c0-aad2-bb277754807b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313571396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1313571396
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4062634642
Short name T223
Test name
Test status
Simulation time 2673101900 ps
CPU time 23.59 seconds
Started May 09 02:44:53 PM PDT 24
Finished May 09 02:45:21 PM PDT 24
Peak memory 212012 kb
Host smart-2a41f843-24a1-4c4b-a7d5-1edbe3c0f427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062634642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4062634642
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3477923580
Short name T339
Test name
Test status
Simulation time 54470616714 ps
CPU time 418.87 seconds
Started May 09 02:44:53 PM PDT 24
Finished May 09 02:51:56 PM PDT 24
Peak memory 238328 kb
Host smart-f945a3c7-5c83-415e-bf7f-38963e888649
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477923580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3477923580
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3356070516
Short name T280
Test name
Test status
Simulation time 16460026664 ps
CPU time 46.24 seconds
Started May 09 02:44:53 PM PDT 24
Finished May 09 02:45:43 PM PDT 24
Peak memory 215580 kb
Host smart-37c37ffc-b15f-4b09-83ad-21f31043e687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356070516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3356070516
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.116649932
Short name T137
Test name
Test status
Simulation time 20447837877 ps
CPU time 31.48 seconds
Started May 09 02:44:52 PM PDT 24
Finished May 09 02:45:28 PM PDT 24
Peak memory 212044 kb
Host smart-ca0aaadc-a5c7-4681-a0cc-8568c342fba0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=116649932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.116649932
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.4181189726
Short name T9
Test name
Test status
Simulation time 340574026 ps
CPU time 20.17 seconds
Started May 09 02:44:55 PM PDT 24
Finished May 09 02:45:19 PM PDT 24
Peak memory 217396 kb
Host smart-d8f94242-1c8a-438d-a47a-d66b58b7f55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181189726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.4181189726
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.4117079204
Short name T18
Test name
Test status
Simulation time 2577305455 ps
CPU time 44.74 seconds
Started May 09 02:44:54 PM PDT 24
Finished May 09 02:45:43 PM PDT 24
Peak memory 220000 kb
Host smart-2d422328-7191-4845-9973-fb465909f7d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117079204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.4117079204
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2232343539
Short name T52
Test name
Test status
Simulation time 39549471454 ps
CPU time 1531.49 seconds
Started May 09 02:44:51 PM PDT 24
Finished May 09 03:10:27 PM PDT 24
Peak memory 237924 kb
Host smart-a8a7ed52-ce2f-4fb1-ae82-61e150f739c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232343539 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2232343539
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1865975278
Short name T66
Test name
Test status
Simulation time 2734719532 ps
CPU time 13.13 seconds
Started May 09 02:44:56 PM PDT 24
Finished May 09 02:45:13 PM PDT 24
Peak memory 211964 kb
Host smart-80ee9ab1-b44d-4517-a0f5-34099513b054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865975278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1865975278
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.4184734878
Short name T46
Test name
Test status
Simulation time 9836745086 ps
CPU time 176.86 seconds
Started May 09 02:44:54 PM PDT 24
Finished May 09 02:47:55 PM PDT 24
Peak memory 241388 kb
Host smart-0ab3b949-8c06-4a1e-82ff-0c458f5cabdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184734878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.4184734878
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2622922180
Short name T274
Test name
Test status
Simulation time 3464847431 ps
CPU time 42.31 seconds
Started May 09 02:44:52 PM PDT 24
Finished May 09 02:45:38 PM PDT 24
Peak memory 215304 kb
Host smart-f62c067f-0e4a-4980-9d63-eac2ab2f544f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622922180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2622922180
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3609087168
Short name T154
Test name
Test status
Simulation time 608312014 ps
CPU time 14.13 seconds
Started May 09 02:44:53 PM PDT 24
Finished May 09 02:45:12 PM PDT 24
Peak memory 212816 kb
Host smart-23ba7458-1b95-49d9-9836-fc094e999459
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3609087168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3609087168
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3842153781
Short name T109
Test name
Test status
Simulation time 1559612210 ps
CPU time 30.74 seconds
Started May 09 02:44:53 PM PDT 24
Finished May 09 02:45:28 PM PDT 24
Peak memory 218128 kb
Host smart-46df86ca-9981-46bc-8590-a9458b196222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842153781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3842153781
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3097543743
Short name T244
Test name
Test status
Simulation time 897057683 ps
CPU time 50.93 seconds
Started May 09 02:44:54 PM PDT 24
Finished May 09 02:45:49 PM PDT 24
Peak memory 219828 kb
Host smart-b08d0906-8c63-48b2-9918-7bfc4eceb773
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097543743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3097543743
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1369544648
Short name T205
Test name
Test status
Simulation time 1032096766 ps
CPU time 8.41 seconds
Started May 09 02:44:56 PM PDT 24
Finished May 09 02:45:08 PM PDT 24
Peak memory 211892 kb
Host smart-ad2507fa-7fae-49c1-aefa-2dc5a10c821d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369544648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1369544648
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.942383334
Short name T331
Test name
Test status
Simulation time 5468343637 ps
CPU time 49.04 seconds
Started May 09 02:44:53 PM PDT 24
Finished May 09 02:45:46 PM PDT 24
Peak memory 213612 kb
Host smart-6ede5efd-7482-476d-98e6-243a034d3f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942383334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.942383334
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3798557320
Short name T106
Test name
Test status
Simulation time 516765299 ps
CPU time 10.47 seconds
Started May 09 02:44:53 PM PDT 24
Finished May 09 02:45:08 PM PDT 24
Peak memory 212916 kb
Host smart-2d3f2d9c-9bf6-4a6c-a0a3-7b2f65d34f30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3798557320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3798557320
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3141073019
Short name T349
Test name
Test status
Simulation time 25582368062 ps
CPU time 56.42 seconds
Started May 09 02:44:55 PM PDT 24
Finished May 09 02:45:55 PM PDT 24
Peak memory 218888 kb
Host smart-f5008150-bf5a-4b80-9572-96415f0a8f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141073019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3141073019
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2005411992
Short name T297
Test name
Test status
Simulation time 30891986948 ps
CPU time 151.92 seconds
Started May 09 02:44:56 PM PDT 24
Finished May 09 02:47:31 PM PDT 24
Peak memory 222204 kb
Host smart-d804b141-1ff5-4b00-aa06-8eda700a1a1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005411992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2005411992
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2088871935
Short name T245
Test name
Test status
Simulation time 5486878668 ps
CPU time 13.48 seconds
Started May 09 02:44:56 PM PDT 24
Finished May 09 02:45:13 PM PDT 24
Peak memory 211956 kb
Host smart-78e1089e-be0b-4bf5-8559-8afaac4c5539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088871935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2088871935
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2597611235
Short name T197
Test name
Test status
Simulation time 46069992974 ps
CPU time 475.81 seconds
Started May 09 02:44:56 PM PDT 24
Finished May 09 02:52:56 PM PDT 24
Peak memory 229464 kb
Host smart-a89a7308-a50d-42fd-80d7-d18bbb74ac19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597611235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2597611235
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1183918710
Short name T144
Test name
Test status
Simulation time 2203075753 ps
CPU time 34.38 seconds
Started May 09 02:44:56 PM PDT 24
Finished May 09 02:45:34 PM PDT 24
Peak memory 215424 kb
Host smart-a0dc6148-bee4-4881-b74a-ee665bacc10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183918710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1183918710
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1094643761
Short name T212
Test name
Test status
Simulation time 2946825577 ps
CPU time 28.04 seconds
Started May 09 02:44:57 PM PDT 24
Finished May 09 02:45:28 PM PDT 24
Peak memory 212944 kb
Host smart-fbcb0425-c6ba-4f08-b7c1-604af869e2cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1094643761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1094643761
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2813882719
Short name T262
Test name
Test status
Simulation time 33552865939 ps
CPU time 79.32 seconds
Started May 09 02:44:53 PM PDT 24
Finished May 09 02:46:16 PM PDT 24
Peak memory 218676 kb
Host smart-4fa2fed5-74b1-4cd3-aa4f-6e236933ba64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813882719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2813882719
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.776014128
Short name T128
Test name
Test status
Simulation time 1914494924 ps
CPU time 25.56 seconds
Started May 09 02:44:54 PM PDT 24
Finished May 09 02:45:24 PM PDT 24
Peak memory 213912 kb
Host smart-d7436127-f73f-4781-b6fd-ab0242aada06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776014128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.776014128
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2304042002
Short name T41
Test name
Test status
Simulation time 15417956858 ps
CPU time 30.97 seconds
Started May 09 02:45:04 PM PDT 24
Finished May 09 02:45:38 PM PDT 24
Peak memory 212660 kb
Host smart-ed8a47d4-5850-414d-a5a4-6b51f23692c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304042002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2304042002
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3295745209
Short name T47
Test name
Test status
Simulation time 6115846109 ps
CPU time 186.96 seconds
Started May 09 02:45:05 PM PDT 24
Finished May 09 02:48:15 PM PDT 24
Peak memory 220232 kb
Host smart-f7573662-b7e3-415b-9704-80436fe2c8a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295745209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3295745209
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.4125442442
Short name T210
Test name
Test status
Simulation time 9979117820 ps
CPU time 46.51 seconds
Started May 09 02:45:06 PM PDT 24
Finished May 09 02:45:56 PM PDT 24
Peak memory 216208 kb
Host smart-e1915fbc-1455-4667-a0c9-3733b5ff67b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125442442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.4125442442
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3608764863
Short name T338
Test name
Test status
Simulation time 4287196286 ps
CPU time 17.15 seconds
Started May 09 02:45:06 PM PDT 24
Finished May 09 02:45:26 PM PDT 24
Peak memory 212240 kb
Host smart-1bdcdf2b-977b-4d70-b272-e6880dae3b9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3608764863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3608764863
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1310670363
Short name T293
Test name
Test status
Simulation time 7991318640 ps
CPU time 65.12 seconds
Started May 09 02:45:03 PM PDT 24
Finished May 09 02:46:10 PM PDT 24
Peak memory 218920 kb
Host smart-7440339d-f983-4eee-8b9d-a283c9b9fedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310670363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1310670363
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.335508865
Short name T209
Test name
Test status
Simulation time 391210027 ps
CPU time 31.99 seconds
Started May 09 02:45:05 PM PDT 24
Finished May 09 02:45:40 PM PDT 24
Peak memory 216144 kb
Host smart-068efcd0-8d90-48a8-8e27-e33e01c9726a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335508865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.335508865
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2003940861
Short name T53
Test name
Test status
Simulation time 724376371599 ps
CPU time 3074.2 seconds
Started May 09 02:45:05 PM PDT 24
Finished May 09 03:36:23 PM PDT 24
Peak memory 252828 kb
Host smart-d2972611-e08a-46d3-bdd4-37678dcae227
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003940861 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.2003940861
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.574388076
Short name T336
Test name
Test status
Simulation time 8710970444 ps
CPU time 32.83 seconds
Started May 09 02:45:06 PM PDT 24
Finished May 09 02:45:42 PM PDT 24
Peak memory 212676 kb
Host smart-a90e86fa-8fbf-44a7-8b10-f2b1710e9ad6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574388076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.574388076
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2246109718
Short name T14
Test name
Test status
Simulation time 156654508185 ps
CPU time 881.69 seconds
Started May 09 02:45:07 PM PDT 24
Finished May 09 02:59:52 PM PDT 24
Peak memory 230072 kb
Host smart-b9f527d1-4f28-485d-a186-8ae20047add6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246109718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2246109718
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1756189814
Short name T23
Test name
Test status
Simulation time 1321112362 ps
CPU time 19.5 seconds
Started May 09 02:45:04 PM PDT 24
Finished May 09 02:45:26 PM PDT 24
Peak memory 215264 kb
Host smart-cfb9d5a9-4bca-48b3-a102-d9aa3a4a0dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756189814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1756189814
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.280159167
Short name T182
Test name
Test status
Simulation time 2241881709 ps
CPU time 17.32 seconds
Started May 09 02:45:05 PM PDT 24
Finished May 09 02:45:25 PM PDT 24
Peak memory 212104 kb
Host smart-548d7c50-26da-4fa5-b37b-7aebca1d6883
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=280159167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.280159167
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3555992986
Short name T196
Test name
Test status
Simulation time 12110438247 ps
CPU time 54.66 seconds
Started May 09 02:45:04 PM PDT 24
Finished May 09 02:46:01 PM PDT 24
Peak memory 218424 kb
Host smart-391aa138-b855-48c9-b739-bfbf622d1e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555992986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3555992986
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2928328162
Short name T201
Test name
Test status
Simulation time 96084201313 ps
CPU time 107.39 seconds
Started May 09 02:45:04 PM PDT 24
Finished May 09 02:46:55 PM PDT 24
Peak memory 216148 kb
Host smart-5ab5e9a8-40eb-4bbb-acdc-8962fd0c989e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928328162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2928328162
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3846462662
Short name T222
Test name
Test status
Simulation time 2478312579 ps
CPU time 23.23 seconds
Started May 09 02:43:45 PM PDT 24
Finished May 09 02:44:12 PM PDT 24
Peak memory 212000 kb
Host smart-be797c0d-1168-4fbc-b949-afcbb1484d10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846462662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3846462662
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.648444647
Short name T303
Test name
Test status
Simulation time 141444506596 ps
CPU time 409.1 seconds
Started May 09 02:43:46 PM PDT 24
Finished May 09 02:50:38 PM PDT 24
Peak memory 241072 kb
Host smart-a131862a-2bc8-4200-8d3e-31a490ae91d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648444647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.648444647
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3248957744
Short name T324
Test name
Test status
Simulation time 31309091738 ps
CPU time 59.87 seconds
Started May 09 02:43:45 PM PDT 24
Finished May 09 02:44:48 PM PDT 24
Peak memory 214536 kb
Host smart-4386ad31-47b4-4f6a-b382-e66c331d58e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248957744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3248957744
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.317454258
Short name T258
Test name
Test status
Simulation time 13755615536 ps
CPU time 29.05 seconds
Started May 09 02:43:47 PM PDT 24
Finished May 09 02:44:19 PM PDT 24
Peak memory 212332 kb
Host smart-c4fa4bf6-5938-4968-90d7-85ec544a493a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=317454258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.317454258
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.739293622
Short name T284
Test name
Test status
Simulation time 16400278767 ps
CPU time 45.36 seconds
Started May 09 02:43:46 PM PDT 24
Finished May 09 02:44:34 PM PDT 24
Peak memory 217404 kb
Host smart-46dcf8b4-b0dd-491a-924d-4a7b1ce69bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739293622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.739293622
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1448161661
Short name T17
Test name
Test status
Simulation time 3047994306 ps
CPU time 72.15 seconds
Started May 09 02:43:47 PM PDT 24
Finished May 09 02:45:02 PM PDT 24
Peak memory 219964 kb
Host smart-2729cf4a-2e79-4bfb-a52c-1558eec0f001
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448161661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1448161661
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3421291679
Short name T360
Test name
Test status
Simulation time 661090209 ps
CPU time 8.35 seconds
Started May 09 02:45:05 PM PDT 24
Finished May 09 02:45:17 PM PDT 24
Peak memory 211848 kb
Host smart-8be88150-ba9d-4280-a476-f646d1f9b2f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421291679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3421291679
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2939236931
Short name T181
Test name
Test status
Simulation time 29004841257 ps
CPU time 319.88 seconds
Started May 09 02:45:08 PM PDT 24
Finished May 09 02:50:31 PM PDT 24
Peak memory 234540 kb
Host smart-67e09362-7159-483e-ab57-8086d3876569
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939236931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2939236931
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3961105278
Short name T56
Test name
Test status
Simulation time 5931889998 ps
CPU time 55.83 seconds
Started May 09 02:45:08 PM PDT 24
Finished May 09 02:46:06 PM PDT 24
Peak memory 215600 kb
Host smart-00d32e97-1912-4fb4-bdc2-943b0844a822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961105278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3961105278
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1452010929
Short name T276
Test name
Test status
Simulation time 3518931306 ps
CPU time 13.52 seconds
Started May 09 02:45:05 PM PDT 24
Finished May 09 02:45:21 PM PDT 24
Peak memory 211924 kb
Host smart-0a768270-6cd6-4c35-ae68-a9a28d4554be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1452010929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1452010929
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.882481327
Short name T247
Test name
Test status
Simulation time 2935645335 ps
CPU time 39.61 seconds
Started May 09 02:45:19 PM PDT 24
Finished May 09 02:46:00 PM PDT 24
Peak memory 216468 kb
Host smart-da7119ec-89f4-42c1-bdd9-adb1a9aedbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882481327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.882481327
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.4219823527
Short name T302
Test name
Test status
Simulation time 4100804185 ps
CPU time 48.25 seconds
Started May 09 02:45:07 PM PDT 24
Finished May 09 02:45:58 PM PDT 24
Peak memory 217976 kb
Host smart-41f6607f-4aad-403d-8433-0d0098f7ad01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219823527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.4219823527
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1744122932
Short name T221
Test name
Test status
Simulation time 2468986033 ps
CPU time 24.09 seconds
Started May 09 02:45:16 PM PDT 24
Finished May 09 02:45:43 PM PDT 24
Peak memory 212012 kb
Host smart-aa20f4a3-2004-4fc4-ad19-b546a00cb9d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744122932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1744122932
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3078147251
Short name T45
Test name
Test status
Simulation time 11649543464 ps
CPU time 207.64 seconds
Started May 09 02:45:08 PM PDT 24
Finished May 09 02:48:38 PM PDT 24
Peak memory 225316 kb
Host smart-66264e7a-d0fa-4934-abc9-da14e1a695f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078147251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3078147251
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.452624880
Short name T169
Test name
Test status
Simulation time 75782929176 ps
CPU time 56.96 seconds
Started May 09 02:45:17 PM PDT 24
Finished May 09 02:46:17 PM PDT 24
Peak memory 214600 kb
Host smart-6da1385b-b84e-4224-8cf6-7abb9fd935f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452624880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.452624880
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3208034874
Short name T193
Test name
Test status
Simulation time 702243909 ps
CPU time 10.61 seconds
Started May 09 02:45:07 PM PDT 24
Finished May 09 02:45:21 PM PDT 24
Peak memory 212872 kb
Host smart-a354b035-460b-4fd5-a904-e45e06a535eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3208034874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3208034874
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1874602570
Short name T36
Test name
Test status
Simulation time 6621620715 ps
CPU time 34.48 seconds
Started May 09 02:45:05 PM PDT 24
Finished May 09 02:45:42 PM PDT 24
Peak memory 219064 kb
Host smart-45ea0bf9-75b4-46ca-b113-859c20b883d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874602570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1874602570
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3439922824
Short name T213
Test name
Test status
Simulation time 59786731130 ps
CPU time 155.1 seconds
Started May 09 02:45:04 PM PDT 24
Finished May 09 02:47:42 PM PDT 24
Peak memory 222196 kb
Host smart-43e42572-100d-4938-9011-218d0163ae80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439922824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3439922824
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2654905276
Short name T37
Test name
Test status
Simulation time 9249566480 ps
CPU time 22.32 seconds
Started May 09 02:45:17 PM PDT 24
Finished May 09 02:45:42 PM PDT 24
Peak memory 212772 kb
Host smart-f73cba68-a27a-4eff-9760-9f766f499b2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654905276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2654905276
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2141967037
Short name T271
Test name
Test status
Simulation time 11143322121 ps
CPU time 351.08 seconds
Started May 09 02:45:15 PM PDT 24
Finished May 09 02:51:07 PM PDT 24
Peak memory 236428 kb
Host smart-2daf4a6f-ad72-420c-a056-93c01340735c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141967037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2141967037
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3280691175
Short name T202
Test name
Test status
Simulation time 20507015061 ps
CPU time 31.08 seconds
Started May 09 02:45:19 PM PDT 24
Finished May 09 02:45:52 PM PDT 24
Peak memory 215612 kb
Host smart-a9c7ef31-43f8-4cc1-acec-c82d267e7d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280691175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3280691175
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2065347621
Short name T259
Test name
Test status
Simulation time 15867232150 ps
CPU time 25.92 seconds
Started May 09 02:45:16 PM PDT 24
Finished May 09 02:45:44 PM PDT 24
Peak memory 212348 kb
Host smart-f2143750-2eaf-40c0-94dd-4cee373889ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2065347621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2065347621
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3439268322
Short name T298
Test name
Test status
Simulation time 33409142279 ps
CPU time 74.41 seconds
Started May 09 02:45:16 PM PDT 24
Finished May 09 02:46:32 PM PDT 24
Peak memory 217956 kb
Host smart-d233764c-2f28-46af-a464-9bb92c3ec2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439268322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3439268322
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1775245348
Short name T307
Test name
Test status
Simulation time 11317846744 ps
CPU time 114.21 seconds
Started May 09 02:45:17 PM PDT 24
Finished May 09 02:47:14 PM PDT 24
Peak memory 219968 kb
Host smart-a2b325ad-f8ea-4d83-b55f-b78d8c7b4abd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775245348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1775245348
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3693681234
Short name T277
Test name
Test status
Simulation time 1744010936 ps
CPU time 18.82 seconds
Started May 09 02:45:17 PM PDT 24
Finished May 09 02:45:39 PM PDT 24
Peak memory 211840 kb
Host smart-5ca8df1a-c112-48bf-87e7-0bca6d2b21df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693681234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3693681234
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3012624709
Short name T272
Test name
Test status
Simulation time 165626509488 ps
CPU time 814 seconds
Started May 09 02:45:16 PM PDT 24
Finished May 09 02:58:53 PM PDT 24
Peak memory 240720 kb
Host smart-ac80df77-cd31-4e19-a9ef-f2e4844ad0e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012624709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3012624709
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.530867470
Short name T347
Test name
Test status
Simulation time 12214974547 ps
CPU time 38 seconds
Started May 09 02:45:16 PM PDT 24
Finished May 09 02:45:57 PM PDT 24
Peak memory 215688 kb
Host smart-206f8b27-cb9c-489f-b8e4-58e50399f777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530867470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.530867470
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1732110024
Short name T107
Test name
Test status
Simulation time 3256801408 ps
CPU time 26.86 seconds
Started May 09 02:45:17 PM PDT 24
Finished May 09 02:45:46 PM PDT 24
Peak memory 212756 kb
Host smart-821e2659-62a2-4893-a2b8-52d8fd99fccd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1732110024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1732110024
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.4254997170
Short name T343
Test name
Test status
Simulation time 18772938220 ps
CPU time 50.82 seconds
Started May 09 02:45:19 PM PDT 24
Finished May 09 02:46:12 PM PDT 24
Peak memory 218552 kb
Host smart-bb5ab391-fdbe-4ef6-8ee5-5b52fa4957bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254997170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.4254997170
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1878170406
Short name T281
Test name
Test status
Simulation time 38430590171 ps
CPU time 104.04 seconds
Started May 09 02:45:16 PM PDT 24
Finished May 09 02:47:03 PM PDT 24
Peak memory 220360 kb
Host smart-0583765a-e24e-4711-a20f-64c201e5e4ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878170406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1878170406
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.80744583
Short name T21
Test name
Test status
Simulation time 403368153383 ps
CPU time 2333.12 seconds
Started May 09 02:45:15 PM PDT 24
Finished May 09 03:24:10 PM PDT 24
Peak memory 252852 kb
Host smart-5a309f18-b468-4be9-8c2b-34453b13f7f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80744583 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.80744583
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1018124069
Short name T333
Test name
Test status
Simulation time 3785082505 ps
CPU time 19.6 seconds
Started May 09 02:45:17 PM PDT 24
Finished May 09 02:45:39 PM PDT 24
Peak memory 212580 kb
Host smart-228c023c-e366-4c50-8bf9-ead4e03d3f21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018124069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1018124069
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3074181952
Short name T191
Test name
Test status
Simulation time 13980530920 ps
CPU time 380.44 seconds
Started May 09 02:45:18 PM PDT 24
Finished May 09 02:51:41 PM PDT 24
Peak memory 241328 kb
Host smart-40ff0482-2061-4b2b-b1a9-b3f20889ee20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074181952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3074181952
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1742184250
Short name T135
Test name
Test status
Simulation time 12813922651 ps
CPU time 55.9 seconds
Started May 09 02:45:16 PM PDT 24
Finished May 09 02:46:15 PM PDT 24
Peak memory 214312 kb
Host smart-90335b40-4ef3-4c54-a57a-a7ab0b7298c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742184250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1742184250
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2792162653
Short name T217
Test name
Test status
Simulation time 732625595 ps
CPU time 10.3 seconds
Started May 09 02:45:17 PM PDT 24
Finished May 09 02:45:30 PM PDT 24
Peak memory 213144 kb
Host smart-258ddbb3-777e-42d0-a318-223bc4c5ea14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2792162653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2792162653
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3689562051
Short name T346
Test name
Test status
Simulation time 7317859139 ps
CPU time 70.03 seconds
Started May 09 02:45:15 PM PDT 24
Finished May 09 02:46:26 PM PDT 24
Peak memory 219116 kb
Host smart-d52e9da6-2f6f-41ba-9683-ec44af46d9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689562051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3689562051
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1494139203
Short name T188
Test name
Test status
Simulation time 1187974673 ps
CPU time 29.63 seconds
Started May 09 02:45:16 PM PDT 24
Finished May 09 02:45:48 PM PDT 24
Peak memory 219860 kb
Host smart-d09c8314-9c43-49ac-82f9-39023bd4cb55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494139203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1494139203
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3532591523
Short name T286
Test name
Test status
Simulation time 8534714102 ps
CPU time 22.39 seconds
Started May 09 02:45:27 PM PDT 24
Finished May 09 02:45:52 PM PDT 24
Peak memory 212212 kb
Host smart-7c1ce3da-fd07-41b5-b4fa-02cbea327e69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532591523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3532591523
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1176964823
Short name T26
Test name
Test status
Simulation time 217743771417 ps
CPU time 383.42 seconds
Started May 09 02:45:15 PM PDT 24
Finished May 09 02:51:41 PM PDT 24
Peak memory 239508 kb
Host smart-19c36ead-ecc3-46ef-9dc2-fefe1ae3bda8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176964823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1176964823
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.549172137
Short name T300
Test name
Test status
Simulation time 356794350 ps
CPU time 10.75 seconds
Started May 09 02:45:14 PM PDT 24
Finished May 09 02:45:27 PM PDT 24
Peak memory 213204 kb
Host smart-632bc8eb-9d94-430e-b304-d39b70a28c52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=549172137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.549172137
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2887194237
Short name T352
Test name
Test status
Simulation time 26927444291 ps
CPU time 55.13 seconds
Started May 09 02:45:19 PM PDT 24
Finished May 09 02:46:16 PM PDT 24
Peak memory 218988 kb
Host smart-b7365ffb-5262-4660-965c-3aca9ba35de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887194237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2887194237
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3295257457
Short name T2
Test name
Test status
Simulation time 6782634760 ps
CPU time 52.71 seconds
Started May 09 02:45:16 PM PDT 24
Finished May 09 02:46:11 PM PDT 24
Peak memory 221448 kb
Host smart-b473b9a3-feda-40de-b1a9-0bc8e95c4de8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295257457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3295257457
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2264274677
Short name T8
Test name
Test status
Simulation time 1866709555 ps
CPU time 19.58 seconds
Started May 09 02:45:28 PM PDT 24
Finished May 09 02:45:51 PM PDT 24
Peak memory 212388 kb
Host smart-08cb3107-49e4-4316-94f1-a37e4498fbcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264274677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2264274677
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1107433768
Short name T166
Test name
Test status
Simulation time 392185727119 ps
CPU time 611.91 seconds
Started May 09 02:45:29 PM PDT 24
Finished May 09 02:55:44 PM PDT 24
Peak memory 241064 kb
Host smart-d70e173f-2072-48f3-9758-43076128ddaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107433768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1107433768
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.38525069
Short name T311
Test name
Test status
Simulation time 1376223770 ps
CPU time 19.17 seconds
Started May 09 02:45:27 PM PDT 24
Finished May 09 02:45:49 PM PDT 24
Peak memory 215416 kb
Host smart-b4220d1a-1b0a-4ed3-b21e-2f4e946b869b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38525069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.38525069
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1808655000
Short name T3
Test name
Test status
Simulation time 8812930233 ps
CPU time 24.32 seconds
Started May 09 02:45:29 PM PDT 24
Finished May 09 02:45:56 PM PDT 24
Peak memory 213388 kb
Host smart-c1c4691c-f48c-4c8c-ac4c-442689d27422
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1808655000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1808655000
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3549023569
Short name T149
Test name
Test status
Simulation time 3596921123 ps
CPU time 44.45 seconds
Started May 09 02:45:30 PM PDT 24
Finished May 09 02:46:18 PM PDT 24
Peak memory 217628 kb
Host smart-66bc5217-e7c2-4c9a-bbae-c33137309a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549023569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3549023569
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3101978111
Short name T239
Test name
Test status
Simulation time 660910491 ps
CPU time 8.45 seconds
Started May 09 02:45:29 PM PDT 24
Finished May 09 02:45:41 PM PDT 24
Peak memory 211848 kb
Host smart-ec6e1067-9743-418e-8d85-ee5774be6518
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101978111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3101978111
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3147747117
Short name T332
Test name
Test status
Simulation time 1719113852 ps
CPU time 133.06 seconds
Started May 09 02:45:29 PM PDT 24
Finished May 09 02:47:45 PM PDT 24
Peak memory 240740 kb
Host smart-e4de81ec-4ca3-42a0-b5fa-1bbc0f34a9ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147747117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3147747117
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.515796535
Short name T225
Test name
Test status
Simulation time 6833519248 ps
CPU time 29.94 seconds
Started May 09 02:45:30 PM PDT 24
Finished May 09 02:46:03 PM PDT 24
Peak memory 215584 kb
Host smart-929d4754-ebee-4b43-8750-aa84d6d26bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515796535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.515796535
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.384368583
Short name T138
Test name
Test status
Simulation time 25234045536 ps
CPU time 27.78 seconds
Started May 09 02:45:28 PM PDT 24
Finished May 09 02:45:59 PM PDT 24
Peak memory 212488 kb
Host smart-9a563f67-d8f0-4278-8fee-9e4ae905e7e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=384368583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.384368583
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1706913934
Short name T328
Test name
Test status
Simulation time 707239607 ps
CPU time 20.59 seconds
Started May 09 02:45:27 PM PDT 24
Finished May 09 02:45:50 PM PDT 24
Peak memory 218024 kb
Host smart-1d6f0514-6b29-4187-ba9b-1c8f14bb74be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706913934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1706913934
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3026913094
Short name T270
Test name
Test status
Simulation time 29924014938 ps
CPU time 82.54 seconds
Started May 09 02:45:27 PM PDT 24
Finished May 09 02:46:52 PM PDT 24
Peak memory 219720 kb
Host smart-f4d8a064-c424-44e0-9bcf-eabb0716ed57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026913094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3026913094
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2962257545
Short name T296
Test name
Test status
Simulation time 10497506479 ps
CPU time 24.31 seconds
Started May 09 02:45:29 PM PDT 24
Finished May 09 02:45:56 PM PDT 24
Peak memory 212832 kb
Host smart-72245fab-f0e3-4c3c-bbd8-6a283d7b577b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962257545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2962257545
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3934108764
Short name T265
Test name
Test status
Simulation time 3170258992 ps
CPU time 211.29 seconds
Started May 09 02:45:29 PM PDT 24
Finished May 09 02:49:03 PM PDT 24
Peak memory 218384 kb
Host smart-9013022d-2ab4-4be6-8c3f-7c65a80589bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934108764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3934108764
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2782499721
Short name T19
Test name
Test status
Simulation time 30154793812 ps
CPU time 63.39 seconds
Started May 09 02:45:31 PM PDT 24
Finished May 09 02:46:37 PM PDT 24
Peak memory 214592 kb
Host smart-8731c0b2-fbfd-4bf5-aa25-441894019099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782499721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2782499721
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1867855569
Short name T253
Test name
Test status
Simulation time 1025349595 ps
CPU time 13.94 seconds
Started May 09 02:45:29 PM PDT 24
Finished May 09 02:45:46 PM PDT 24
Peak memory 212872 kb
Host smart-ead1d574-031d-40ca-be7d-2c613ddbe491
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1867855569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1867855569
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3700408246
Short name T330
Test name
Test status
Simulation time 18389761918 ps
CPU time 61.42 seconds
Started May 09 02:45:27 PM PDT 24
Finished May 09 02:46:31 PM PDT 24
Peak memory 217940 kb
Host smart-ed3ef2b8-b1a0-4df7-9306-430271304025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700408246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3700408246
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.4081492268
Short name T282
Test name
Test status
Simulation time 6878358933 ps
CPU time 92.33 seconds
Started May 09 02:45:32 PM PDT 24
Finished May 09 02:47:07 PM PDT 24
Peak memory 220212 kb
Host smart-8b39ba02-d4b1-48b3-ba6b-5d274be94767
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081492268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.4081492268
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3098363173
Short name T199
Test name
Test status
Simulation time 4214709920 ps
CPU time 33.31 seconds
Started May 09 02:45:28 PM PDT 24
Finished May 09 02:46:04 PM PDT 24
Peak memory 212432 kb
Host smart-3bae6293-759f-4f94-860d-93c292af9e4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098363173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3098363173
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1859295156
Short name T165
Test name
Test status
Simulation time 74002812792 ps
CPU time 340.83 seconds
Started May 09 02:45:29 PM PDT 24
Finished May 09 02:51:13 PM PDT 24
Peak memory 237352 kb
Host smart-29702d5b-9614-49b7-b3e3-8f74cb1f64f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859295156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1859295156
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1552674385
Short name T364
Test name
Test status
Simulation time 17073585615 ps
CPU time 67.44 seconds
Started May 09 02:45:30 PM PDT 24
Finished May 09 02:46:40 PM PDT 24
Peak memory 215512 kb
Host smart-6262514c-c437-4492-aa2b-fe99de3711c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552674385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1552674385
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.771067315
Short name T251
Test name
Test status
Simulation time 8205287850 ps
CPU time 33.29 seconds
Started May 09 02:45:28 PM PDT 24
Finished May 09 02:46:04 PM PDT 24
Peak memory 212192 kb
Host smart-669862d3-591d-48a4-936e-459beeaf610e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=771067315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.771067315
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2669654951
Short name T184
Test name
Test status
Simulation time 5024448503 ps
CPU time 40.57 seconds
Started May 09 02:45:30 PM PDT 24
Finished May 09 02:46:14 PM PDT 24
Peak memory 217800 kb
Host smart-ea340b79-7c3e-4b23-af0e-51f51dae500f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669654951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2669654951
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1925158703
Short name T261
Test name
Test status
Simulation time 34278906142 ps
CPU time 57.55 seconds
Started May 09 02:45:27 PM PDT 24
Finished May 09 02:46:27 PM PDT 24
Peak memory 219416 kb
Host smart-86647b95-decb-43e6-9182-0f2865b3cab0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925158703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1925158703
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3458828860
Short name T6
Test name
Test status
Simulation time 12063270313 ps
CPU time 26.7 seconds
Started May 09 02:43:44 PM PDT 24
Finished May 09 02:44:13 PM PDT 24
Peak memory 212012 kb
Host smart-e9a6b9b0-6ba3-4921-b365-feba068ef119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458828860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3458828860
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1937412127
Short name T326
Test name
Test status
Simulation time 60375099859 ps
CPU time 281.06 seconds
Started May 09 02:43:46 PM PDT 24
Finished May 09 02:48:30 PM PDT 24
Peak memory 237416 kb
Host smart-a2230473-2b12-4781-a494-b10504960631
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937412127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1937412127
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1933166080
Short name T215
Test name
Test status
Simulation time 6064989004 ps
CPU time 55.45 seconds
Started May 09 02:43:46 PM PDT 24
Finished May 09 02:44:44 PM PDT 24
Peak memory 215972 kb
Host smart-8d01d391-5f6f-4e57-85c6-83dde5db70af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933166080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1933166080
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3747223735
Short name T203
Test name
Test status
Simulation time 6585190215 ps
CPU time 28.9 seconds
Started May 09 02:43:43 PM PDT 24
Finished May 09 02:44:15 PM PDT 24
Peak memory 212384 kb
Host smart-be6e475c-f9f6-4589-8589-3455d5981fd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3747223735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3747223735
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.557096519
Short name T337
Test name
Test status
Simulation time 18310884812 ps
CPU time 52.04 seconds
Started May 09 02:43:43 PM PDT 24
Finished May 09 02:44:38 PM PDT 24
Peak memory 218860 kb
Host smart-81a56b8d-1aa1-49bd-82a6-3b3b80d7fe0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557096519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.557096519
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3121245918
Short name T323
Test name
Test status
Simulation time 524819950 ps
CPU time 37.18 seconds
Started May 09 02:43:50 PM PDT 24
Finished May 09 02:44:29 PM PDT 24
Peak memory 219852 kb
Host smart-c5203943-e96a-47a6-a7c0-3d043b0d7fd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121245918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3121245918
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1573343428
Short name T67
Test name
Test status
Simulation time 12855283189 ps
CPU time 27.74 seconds
Started May 09 02:43:53 PM PDT 24
Finished May 09 02:44:23 PM PDT 24
Peak memory 211964 kb
Host smart-7d6fa683-c49d-42c7-b504-978152935e5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573343428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1573343428
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4145827548
Short name T308
Test name
Test status
Simulation time 430491042193 ps
CPU time 375.03 seconds
Started May 09 02:43:44 PM PDT 24
Finished May 09 02:50:02 PM PDT 24
Peak memory 238368 kb
Host smart-3f898f2b-e4c8-4893-bf04-a36c95ecfd84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145827548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.4145827548
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.10830229
Short name T350
Test name
Test status
Simulation time 10209943669 ps
CPU time 49.79 seconds
Started May 09 02:43:58 PM PDT 24
Finished May 09 02:44:51 PM PDT 24
Peak memory 215624 kb
Host smart-d5a32995-0ac3-468c-a8f6-74f263a391ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10830229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.10830229
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.537654628
Short name T167
Test name
Test status
Simulation time 3734421563 ps
CPU time 32.64 seconds
Started May 09 02:43:44 PM PDT 24
Finished May 09 02:44:20 PM PDT 24
Peak memory 212008 kb
Host smart-16db13fb-f23b-4f25-9070-d9a3542fecd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=537654628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.537654628
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3687076138
Short name T299
Test name
Test status
Simulation time 1367617933 ps
CPU time 26.57 seconds
Started May 09 02:43:46 PM PDT 24
Finished May 09 02:44:16 PM PDT 24
Peak memory 218028 kb
Host smart-6cd4bd58-1116-4be7-acc4-885672378fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687076138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3687076138
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.845738755
Short name T127
Test name
Test status
Simulation time 5724243568 ps
CPU time 76.82 seconds
Started May 09 02:43:46 PM PDT 24
Finished May 09 02:45:05 PM PDT 24
Peak memory 220396 kb
Host smart-4255979e-b6b0-4504-a4a7-effa04a5c040
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845738755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.845738755
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.993385694
Short name T214
Test name
Test status
Simulation time 3257634369 ps
CPU time 27.5 seconds
Started May 09 02:43:53 PM PDT 24
Finished May 09 02:44:23 PM PDT 24
Peak memory 212468 kb
Host smart-94b19252-108c-43ef-8475-017b2ab477bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993385694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.993385694
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3031860446
Short name T351
Test name
Test status
Simulation time 52160959763 ps
CPU time 512.12 seconds
Started May 09 02:43:59 PM PDT 24
Finished May 09 02:52:35 PM PDT 24
Peak memory 226304 kb
Host smart-ef6551db-ec81-43fe-bf2b-9e704acb8635
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031860446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3031860446
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2505081779
Short name T301
Test name
Test status
Simulation time 404766153 ps
CPU time 19.77 seconds
Started May 09 02:43:54 PM PDT 24
Finished May 09 02:44:16 PM PDT 24
Peak memory 215312 kb
Host smart-7ca208ce-867b-4dbc-8d70-bcb32a0fc1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505081779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2505081779
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2265682680
Short name T250
Test name
Test status
Simulation time 3599604084 ps
CPU time 30.2 seconds
Started May 09 02:43:59 PM PDT 24
Finished May 09 02:44:32 PM PDT 24
Peak memory 212936 kb
Host smart-c0df8988-be7c-4671-8aa3-ed0a3f252e81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2265682680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2265682680
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3434864436
Short name T228
Test name
Test status
Simulation time 7008876069 ps
CPU time 58.67 seconds
Started May 09 02:43:53 PM PDT 24
Finished May 09 02:44:53 PM PDT 24
Peak memory 218452 kb
Host smart-07c13a1e-82dc-4b26-ae37-2ef3e1714688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434864436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3434864436
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3216216795
Short name T195
Test name
Test status
Simulation time 50122875134 ps
CPU time 122.63 seconds
Started May 09 02:43:55 PM PDT 24
Finished May 09 02:46:01 PM PDT 24
Peak memory 221556 kb
Host smart-e8a16099-c6c4-4bf7-8704-c25ff194c0e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216216795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3216216795
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3256913882
Short name T171
Test name
Test status
Simulation time 394897287 ps
CPU time 8.41 seconds
Started May 09 02:43:55 PM PDT 24
Finished May 09 02:44:06 PM PDT 24
Peak memory 211892 kb
Host smart-abfd9e26-f356-49c4-a46f-2506f34f3cb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256913882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3256913882
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1598901308
Short name T190
Test name
Test status
Simulation time 35578936158 ps
CPU time 283.69 seconds
Started May 09 02:43:54 PM PDT 24
Finished May 09 02:48:40 PM PDT 24
Peak memory 238456 kb
Host smart-77f998c3-7a4b-4d2a-892d-e70476df63be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598901308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1598901308
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3597423248
Short name T344
Test name
Test status
Simulation time 9674661796 ps
CPU time 46.4 seconds
Started May 09 02:43:59 PM PDT 24
Finished May 09 02:44:49 PM PDT 24
Peak memory 215552 kb
Host smart-c8cb7270-c88b-47f4-a1c8-45051df1b7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597423248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3597423248
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.4072494324
Short name T219
Test name
Test status
Simulation time 1910594664 ps
CPU time 10.18 seconds
Started May 09 02:43:55 PM PDT 24
Finished May 09 02:44:07 PM PDT 24
Peak memory 212004 kb
Host smart-414dc148-5926-40e7-aa80-3412d6c59a66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4072494324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.4072494324
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.930758924
Short name T39
Test name
Test status
Simulation time 4974879300 ps
CPU time 54.95 seconds
Started May 09 02:43:54 PM PDT 24
Finished May 09 02:44:52 PM PDT 24
Peak memory 217528 kb
Host smart-749a37eb-8e9d-45db-b4f4-670ba68346fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930758924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.930758924
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.135403067
Short name T313
Test name
Test status
Simulation time 2508927527 ps
CPU time 73.7 seconds
Started May 09 02:43:55 PM PDT 24
Finished May 09 02:45:11 PM PDT 24
Peak memory 219944 kb
Host smart-39411b46-c119-4f72-b32e-8bc4b77df0c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135403067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.135403067
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.537299211
Short name T237
Test name
Test status
Simulation time 5167525670 ps
CPU time 23.43 seconds
Started May 09 02:43:54 PM PDT 24
Finished May 09 02:44:19 PM PDT 24
Peak memory 212040 kb
Host smart-72225ff7-df48-49a3-b283-799e7d6984d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537299211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.537299211
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3641271365
Short name T287
Test name
Test status
Simulation time 81539211041 ps
CPU time 481.42 seconds
Started May 09 02:43:56 PM PDT 24
Finished May 09 02:52:00 PM PDT 24
Peak memory 238308 kb
Host smart-29d0ad09-5de4-4ef7-8f2d-4fef61ad3dc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641271365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3641271365
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1275535551
Short name T10
Test name
Test status
Simulation time 346070544 ps
CPU time 19.2 seconds
Started May 09 02:43:59 PM PDT 24
Finished May 09 02:44:22 PM PDT 24
Peak memory 215104 kb
Host smart-5d51c696-54a6-4db4-87d2-c7f1115f3f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275535551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1275535551
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1007304509
Short name T153
Test name
Test status
Simulation time 2288091918 ps
CPU time 23.86 seconds
Started May 09 02:43:55 PM PDT 24
Finished May 09 02:44:21 PM PDT 24
Peak memory 211956 kb
Host smart-b23946cd-1705-4f64-866e-87892bb562fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1007304509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1007304509
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1391327748
Short name T353
Test name
Test status
Simulation time 349174842 ps
CPU time 19.86 seconds
Started May 09 02:43:56 PM PDT 24
Finished May 09 02:44:19 PM PDT 24
Peak memory 218192 kb
Host smart-7656a276-950f-41cd-9c5b-e63d1ed4682d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391327748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1391327748
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2950856043
Short name T359
Test name
Test status
Simulation time 7708684844 ps
CPU time 86.52 seconds
Started May 09 02:43:58 PM PDT 24
Finished May 09 02:45:27 PM PDT 24
Peak memory 219960 kb
Host smart-e925491a-d07d-4937-9bef-58823c67c902
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950856043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2950856043
Directory /workspace/9.rom_ctrl_stress_all/latest
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