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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.63 96.97 93.15 97.88 100.00 98.69 97.88 98.83


Total test records in report: 453
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T297 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1107262603 May 12 01:19:55 PM PDT 24 May 12 01:21:01 PM PDT 24 15755793263 ps
T298 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1158859737 May 12 01:20:06 PM PDT 24 May 12 01:25:59 PM PDT 24 5388230118 ps
T299 /workspace/coverage/default/29.rom_ctrl_smoke.1458354195 May 12 01:20:23 PM PDT 24 May 12 01:20:43 PM PDT 24 1425982478 ps
T300 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2601008732 May 12 01:20:25 PM PDT 24 May 12 01:20:38 PM PDT 24 686060985 ps
T301 /workspace/coverage/default/23.rom_ctrl_stress_all.3395062625 May 12 01:20:12 PM PDT 24 May 12 01:21:09 PM PDT 24 9285858455 ps
T302 /workspace/coverage/default/36.rom_ctrl_alert_test.1564730341 May 12 01:20:38 PM PDT 24 May 12 01:20:55 PM PDT 24 11995959041 ps
T303 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4116324576 May 12 01:20:25 PM PDT 24 May 12 01:21:33 PM PDT 24 53660961698 ps
T304 /workspace/coverage/default/15.rom_ctrl_stress_all.238417584 May 12 01:19:56 PM PDT 24 May 12 01:23:00 PM PDT 24 80312357990 ps
T305 /workspace/coverage/default/17.rom_ctrl_alert_test.2985876537 May 12 01:20:01 PM PDT 24 May 12 01:20:32 PM PDT 24 8611543499 ps
T306 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.261121082 May 12 01:19:51 PM PDT 24 May 12 01:20:21 PM PDT 24 5879911775 ps
T307 /workspace/coverage/default/33.rom_ctrl_smoke.3263190783 May 12 01:20:24 PM PDT 24 May 12 01:21:04 PM PDT 24 6648973638 ps
T308 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2495796629 May 12 01:19:56 PM PDT 24 May 12 01:27:04 PM PDT 24 157962408872 ps
T309 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1834117413 May 12 01:21:03 PM PDT 24 May 12 01:21:29 PM PDT 24 4705862062 ps
T310 /workspace/coverage/default/8.rom_ctrl_stress_all.429189291 May 12 01:19:35 PM PDT 24 May 12 01:20:09 PM PDT 24 2116850351 ps
T311 /workspace/coverage/default/25.rom_ctrl_alert_test.4048638402 May 12 01:20:17 PM PDT 24 May 12 01:20:38 PM PDT 24 4031712131 ps
T312 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2580364376 May 12 01:20:09 PM PDT 24 May 12 01:20:35 PM PDT 24 987583936 ps
T313 /workspace/coverage/default/48.rom_ctrl_smoke.1983115922 May 12 01:21:04 PM PDT 24 May 12 01:21:49 PM PDT 24 3705007439 ps
T314 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2350163268 May 12 01:19:47 PM PDT 24 May 12 01:19:58 PM PDT 24 177424379 ps
T315 /workspace/coverage/default/9.rom_ctrl_smoke.2911193934 May 12 01:19:33 PM PDT 24 May 12 01:20:09 PM PDT 24 4295657305 ps
T316 /workspace/coverage/default/45.rom_ctrl_stress_all.1897156099 May 12 01:20:54 PM PDT 24 May 12 01:21:15 PM PDT 24 391878038 ps
T317 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.4259426766 May 12 01:19:39 PM PDT 24 May 12 01:20:02 PM PDT 24 1030199405 ps
T318 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.4131344095 May 12 01:19:55 PM PDT 24 May 12 01:20:20 PM PDT 24 10968581791 ps
T319 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3844892247 May 12 01:20:22 PM PDT 24 May 12 01:21:30 PM PDT 24 8852171443 ps
T320 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1601799614 May 12 01:20:24 PM PDT 24 May 12 01:21:31 PM PDT 24 8036512262 ps
T321 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1961093000 May 12 01:19:30 PM PDT 24 May 12 01:31:33 PM PDT 24 110818579777 ps
T322 /workspace/coverage/default/49.rom_ctrl_alert_test.1759611518 May 12 01:21:10 PM PDT 24 May 12 01:21:33 PM PDT 24 10200618269 ps
T323 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.176744052 May 12 01:20:57 PM PDT 24 May 12 01:21:27 PM PDT 24 15954776302 ps
T324 /workspace/coverage/default/29.rom_ctrl_stress_all.1484111955 May 12 01:20:27 PM PDT 24 May 12 01:20:53 PM PDT 24 754841988 ps
T325 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4249211068 May 12 01:20:27 PM PDT 24 May 12 01:20:44 PM PDT 24 1052118731 ps
T326 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2135674876 May 12 01:20:27 PM PDT 24 May 12 01:22:56 PM PDT 24 7486889908 ps
T327 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.88105547 May 12 01:20:59 PM PDT 24 May 12 01:21:10 PM PDT 24 358382287 ps
T328 /workspace/coverage/default/27.rom_ctrl_alert_test.1468526222 May 12 01:20:15 PM PDT 24 May 12 01:20:31 PM PDT 24 4409289902 ps
T329 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3403991492 May 12 01:20:25 PM PDT 24 May 12 01:32:07 PM PDT 24 103628743354 ps
T330 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3647357876 May 12 01:20:17 PM PDT 24 May 12 01:20:39 PM PDT 24 7270133947 ps
T331 /workspace/coverage/default/34.rom_ctrl_smoke.3333780655 May 12 01:20:32 PM PDT 24 May 12 01:21:25 PM PDT 24 31208866171 ps
T332 /workspace/coverage/default/13.rom_ctrl_stress_all.801152283 May 12 01:19:45 PM PDT 24 May 12 01:20:14 PM PDT 24 1499568429 ps
T333 /workspace/coverage/default/42.rom_ctrl_alert_test.1495377746 May 12 01:20:56 PM PDT 24 May 12 01:21:08 PM PDT 24 1452073375 ps
T334 /workspace/coverage/default/14.rom_ctrl_alert_test.1581563301 May 12 01:19:57 PM PDT 24 May 12 01:20:12 PM PDT 24 832659084 ps
T335 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3203230472 May 12 01:20:10 PM PDT 24 May 12 01:20:30 PM PDT 24 674802475 ps
T336 /workspace/coverage/default/45.rom_ctrl_smoke.2946202373 May 12 01:20:54 PM PDT 24 May 12 01:22:03 PM PDT 24 7573487170 ps
T337 /workspace/coverage/default/25.rom_ctrl_stress_all.2344676783 May 12 01:20:10 PM PDT 24 May 12 01:20:29 PM PDT 24 202469605 ps
T338 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2804045255 May 12 01:20:50 PM PDT 24 May 12 01:21:14 PM PDT 24 2086700131 ps
T339 /workspace/coverage/default/2.rom_ctrl_stress_all.2127181040 May 12 01:19:27 PM PDT 24 May 12 01:20:01 PM PDT 24 2269768136 ps
T340 /workspace/coverage/default/12.rom_ctrl_stress_all.3069730000 May 12 01:19:43 PM PDT 24 May 12 01:20:27 PM PDT 24 2635498305 ps
T341 /workspace/coverage/default/41.rom_ctrl_smoke.1165216536 May 12 01:20:54 PM PDT 24 May 12 01:21:14 PM PDT 24 389097314 ps
T342 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4244234381 May 12 01:20:57 PM PDT 24 May 12 01:21:16 PM PDT 24 661766607 ps
T40 /workspace/coverage/default/4.rom_ctrl_sec_cm.2694907038 May 12 01:19:35 PM PDT 24 May 12 01:21:41 PM PDT 24 1610894131 ps
T343 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3117191541 May 12 01:20:27 PM PDT 24 May 12 01:28:21 PM PDT 24 54107550163 ps
T344 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2554383651 May 12 01:20:10 PM PDT 24 May 12 01:20:42 PM PDT 24 24726480855 ps
T345 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1122193809 May 12 01:20:06 PM PDT 24 May 12 01:20:17 PM PDT 24 366594336 ps
T346 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.105378212 May 12 01:20:09 PM PDT 24 May 12 01:20:20 PM PDT 24 1589445961 ps
T347 /workspace/coverage/default/0.rom_ctrl_smoke.1858915646 May 12 01:19:28 PM PDT 24 May 12 01:19:48 PM PDT 24 1358518461 ps
T348 /workspace/coverage/default/43.rom_ctrl_smoke.3980421594 May 12 01:20:54 PM PDT 24 May 12 01:22:30 PM PDT 24 8041121493 ps
T349 /workspace/coverage/default/44.rom_ctrl_stress_all.3959339843 May 12 01:20:58 PM PDT 24 May 12 01:22:38 PM PDT 24 10677000291 ps
T350 /workspace/coverage/default/31.rom_ctrl_stress_all.4096253783 May 12 01:20:27 PM PDT 24 May 12 01:22:22 PM PDT 24 72568100110 ps
T351 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.488132165 May 12 01:19:36 PM PDT 24 May 12 01:26:23 PM PDT 24 125033602441 ps
T352 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2574636474 May 12 01:20:04 PM PDT 24 May 12 01:26:00 PM PDT 24 19306284034 ps
T353 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1544802231 May 12 01:20:02 PM PDT 24 May 12 01:21:08 PM PDT 24 39998132726 ps
T354 /workspace/coverage/default/12.rom_ctrl_alert_test.16036144 May 12 01:19:47 PM PDT 24 May 12 01:20:07 PM PDT 24 1883558886 ps
T54 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.330892547 May 12 01:19:06 PM PDT 24 May 12 01:19:22 PM PDT 24 499142393 ps
T55 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3064122571 May 12 01:19:02 PM PDT 24 May 12 01:21:56 PM PDT 24 16618393310 ps
T65 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3389696913 May 12 01:19:06 PM PDT 24 May 12 01:19:41 PM PDT 24 4171134376 ps
T66 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1393855846 May 12 01:19:16 PM PDT 24 May 12 01:20:48 PM PDT 24 44393223049 ps
T355 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.736829991 May 12 01:19:02 PM PDT 24 May 12 01:19:22 PM PDT 24 2052650822 ps
T105 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1194777894 May 12 01:19:06 PM PDT 24 May 12 01:19:39 PM PDT 24 6869893805 ps
T76 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2565760519 May 12 01:19:18 PM PDT 24 May 12 01:19:53 PM PDT 24 14405728291 ps
T62 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2767348870 May 12 01:19:06 PM PDT 24 May 12 01:21:46 PM PDT 24 853902382 ps
T77 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1235547116 May 12 01:19:01 PM PDT 24 May 12 01:19:32 PM PDT 24 3206036593 ps
T356 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3469348857 May 12 01:19:05 PM PDT 24 May 12 01:19:37 PM PDT 24 17696223421 ps
T63 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.661108583 May 12 01:19:05 PM PDT 24 May 12 01:22:03 PM PDT 24 4504030141 ps
T357 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3539473413 May 12 01:19:18 PM PDT 24 May 12 01:19:51 PM PDT 24 7339489966 ps
T78 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2916829512 May 12 01:19:14 PM PDT 24 May 12 01:19:29 PM PDT 24 2217634795 ps
T79 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.17522425 May 12 01:19:13 PM PDT 24 May 12 01:19:41 PM PDT 24 3379190875 ps
T80 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3414238574 May 12 01:19:14 PM PDT 24 May 12 01:20:09 PM PDT 24 1053669730 ps
T358 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1995898483 May 12 01:19:05 PM PDT 24 May 12 01:19:26 PM PDT 24 7024696591 ps
T359 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.604824892 May 12 01:19:01 PM PDT 24 May 12 01:19:35 PM PDT 24 7056232229 ps
T360 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4064724918 May 12 01:19:18 PM PDT 24 May 12 01:19:33 PM PDT 24 1689290841 ps
T361 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.13174603 May 12 01:19:06 PM PDT 24 May 12 01:19:30 PM PDT 24 2688797160 ps
T362 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3212771284 May 12 01:19:24 PM PDT 24 May 12 01:19:55 PM PDT 24 3997094063 ps
T363 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3288002826 May 12 01:19:02 PM PDT 24 May 12 01:19:24 PM PDT 24 15117201359 ps
T100 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2754717027 May 12 01:19:03 PM PDT 24 May 12 01:19:33 PM PDT 24 15033836385 ps
T106 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.507290100 May 12 01:19:09 PM PDT 24 May 12 01:19:32 PM PDT 24 9573268486 ps
T364 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2743059290 May 12 01:19:05 PM PDT 24 May 12 01:19:32 PM PDT 24 33064024695 ps
T107 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1210346071 May 12 01:19:00 PM PDT 24 May 12 01:19:33 PM PDT 24 3068346682 ps
T81 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3552475983 May 12 01:19:20 PM PDT 24 May 12 01:19:41 PM PDT 24 4962487677 ps
T365 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2380556883 May 12 01:19:04 PM PDT 24 May 12 01:19:28 PM PDT 24 10890706167 ps
T82 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4070979355 May 12 01:19:06 PM PDT 24 May 12 01:22:09 PM PDT 24 90219917890 ps
T101 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4222725873 May 12 01:19:28 PM PDT 24 May 12 01:19:44 PM PDT 24 1666137295 ps
T366 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3137654686 May 12 01:19:21 PM PDT 24 May 12 01:19:55 PM PDT 24 15236943553 ps
T367 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2952244393 May 12 01:19:20 PM PDT 24 May 12 01:19:54 PM PDT 24 3714420429 ps
T368 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3229877693 May 12 01:19:04 PM PDT 24 May 12 01:21:38 PM PDT 24 17139199466 ps
T369 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3659626363 May 12 01:19:12 PM PDT 24 May 12 01:19:32 PM PDT 24 2810438927 ps
T102 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3112065332 May 12 01:19:26 PM PDT 24 May 12 01:19:53 PM PDT 24 3140953237 ps
T83 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1699851103 May 12 01:19:06 PM PDT 24 May 12 01:20:21 PM PDT 24 12918848563 ps
T370 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.940292441 May 12 01:19:01 PM PDT 24 May 12 01:19:27 PM PDT 24 12948622907 ps
T103 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1159044056 May 12 01:19:25 PM PDT 24 May 12 01:19:58 PM PDT 24 4107822250 ps
T84 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1523611410 May 12 01:19:23 PM PDT 24 May 12 01:20:20 PM PDT 24 1081978948 ps
T371 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3152481656 May 12 01:19:17 PM PDT 24 May 12 01:19:49 PM PDT 24 20718827592 ps
T372 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.252982177 May 12 01:19:13 PM PDT 24 May 12 01:19:22 PM PDT 24 1737067861 ps
T85 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2702645950 May 12 01:19:03 PM PDT 24 May 12 01:19:12 PM PDT 24 172425438 ps
T373 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.167367705 May 12 01:19:03 PM PDT 24 May 12 01:21:25 PM PDT 24 27730213629 ps
T91 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.508621473 May 12 01:19:11 PM PDT 24 May 12 01:20:07 PM PDT 24 4485618428 ps
T104 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.146257632 May 12 01:19:00 PM PDT 24 May 12 01:19:29 PM PDT 24 5381339925 ps
T374 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2239503481 May 12 01:19:06 PM PDT 24 May 12 01:19:33 PM PDT 24 12515106193 ps
T375 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3771032282 May 12 01:19:12 PM PDT 24 May 12 01:19:23 PM PDT 24 375935285 ps
T376 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3703022962 May 12 01:19:21 PM PDT 24 May 12 01:19:29 PM PDT 24 689157755 ps
T92 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3713605663 May 12 01:19:05 PM PDT 24 May 12 01:19:14 PM PDT 24 689527863 ps
T377 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2407964328 May 12 01:19:22 PM PDT 24 May 12 01:19:51 PM PDT 24 10547445991 ps
T378 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1605951870 May 12 01:19:08 PM PDT 24 May 12 01:19:21 PM PDT 24 3125097756 ps
T379 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2060365829 May 12 01:19:17 PM PDT 24 May 12 01:19:36 PM PDT 24 3758645672 ps
T380 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.917353641 May 12 01:19:21 PM PDT 24 May 12 01:19:30 PM PDT 24 385691898 ps
T95 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1015902180 May 12 01:19:04 PM PDT 24 May 12 01:19:32 PM PDT 24 6719908411 ps
T381 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1626406010 May 12 01:19:22 PM PDT 24 May 12 01:19:36 PM PDT 24 174235966 ps
T110 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1826401066 May 12 01:19:20 PM PDT 24 May 12 01:20:46 PM PDT 24 2534143482 ps
T382 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3181428857 May 12 01:19:09 PM PDT 24 May 12 01:19:36 PM PDT 24 6692327976 ps
T111 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2850857390 May 12 01:19:06 PM PDT 24 May 12 01:21:47 PM PDT 24 1751536026 ps
T383 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3905380342 May 12 01:19:18 PM PDT 24 May 12 01:20:41 PM PDT 24 6969230025 ps
T384 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.9604672 May 12 01:19:09 PM PDT 24 May 12 01:19:25 PM PDT 24 177319505 ps
T385 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.922622222 May 12 01:19:14 PM PDT 24 May 12 01:19:42 PM PDT 24 3886210298 ps
T386 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3011307381 May 12 01:19:08 PM PDT 24 May 12 01:19:34 PM PDT 24 5698971595 ps
T387 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1699669917 May 12 01:19:24 PM PDT 24 May 12 01:19:33 PM PDT 24 332386956 ps
T388 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3097457224 May 12 01:19:27 PM PDT 24 May 12 01:19:57 PM PDT 24 7698910689 ps
T389 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.46763425 May 12 01:19:19 PM PDT 24 May 12 01:19:41 PM PDT 24 9192719390 ps
T390 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3584429703 May 12 01:19:03 PM PDT 24 May 12 01:19:25 PM PDT 24 2148708270 ps
T97 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1188952377 May 12 01:19:05 PM PDT 24 May 12 01:19:32 PM PDT 24 3083796895 ps
T391 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.693498260 May 12 01:19:18 PM PDT 24 May 12 01:19:47 PM PDT 24 6873581712 ps
T392 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1363451846 May 12 01:19:11 PM PDT 24 May 12 01:19:41 PM PDT 24 10898285337 ps
T393 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1100847160 May 12 01:19:02 PM PDT 24 May 12 01:19:32 PM PDT 24 10811012837 ps
T394 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2647435568 May 12 01:19:18 PM PDT 24 May 12 01:19:44 PM PDT 24 2971981608 ps
T395 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.151717485 May 12 01:19:09 PM PDT 24 May 12 01:20:45 PM PDT 24 10387006011 ps
T93 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3272509048 May 12 01:19:00 PM PDT 24 May 12 01:19:21 PM PDT 24 1920194312 ps
T396 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4217627708 May 12 01:19:24 PM PDT 24 May 12 01:19:43 PM PDT 24 6571095752 ps
T397 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4076079973 May 12 01:19:15 PM PDT 24 May 12 01:19:27 PM PDT 24 601681720 ps
T116 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2370377686 May 12 01:19:03 PM PDT 24 May 12 01:21:48 PM PDT 24 2683534963 ps
T398 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.122798490 May 12 01:19:18 PM PDT 24 May 12 01:19:48 PM PDT 24 3225407610 ps
T399 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3980155949 May 12 01:19:17 PM PDT 24 May 12 01:19:55 PM PDT 24 719061545 ps
T400 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3966344817 May 12 01:19:20 PM PDT 24 May 12 01:19:38 PM PDT 24 1957279585 ps
T401 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2950271490 May 12 01:19:15 PM PDT 24 May 12 01:19:34 PM PDT 24 6834095982 ps
T402 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1587461574 May 12 01:19:03 PM PDT 24 May 12 01:19:12 PM PDT 24 718652360 ps
T403 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3225183850 May 12 01:19:23 PM PDT 24 May 12 01:21:19 PM PDT 24 19538173124 ps
T404 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1135858904 May 12 01:19:02 PM PDT 24 May 12 01:19:30 PM PDT 24 3118375361 ps
T405 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.946427438 May 12 01:19:14 PM PDT 24 May 12 01:19:45 PM PDT 24 4182088544 ps
T406 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2537568567 May 12 01:19:27 PM PDT 24 May 12 01:19:53 PM PDT 24 11651671401 ps
T407 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2965337656 May 12 01:19:18 PM PDT 24 May 12 01:19:27 PM PDT 24 661246020 ps
T408 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4171792897 May 12 01:19:19 PM PDT 24 May 12 01:19:46 PM PDT 24 3835432510 ps
T409 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3908152498 May 12 01:19:09 PM PDT 24 May 12 01:19:38 PM PDT 24 3523767271 ps
T118 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1141138961 May 12 01:19:22 PM PDT 24 May 12 01:22:07 PM PDT 24 805071103 ps
T410 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.788272367 May 12 01:19:18 PM PDT 24 May 12 01:19:27 PM PDT 24 706195492 ps
T411 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1099374200 May 12 01:19:18 PM PDT 24 May 12 01:19:56 PM PDT 24 2748815211 ps
T412 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3798627588 May 12 01:19:06 PM PDT 24 May 12 01:19:33 PM PDT 24 4528841469 ps
T413 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3826526874 May 12 01:19:04 PM PDT 24 May 12 01:19:30 PM PDT 24 7750200074 ps
T414 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3282472082 May 12 01:19:27 PM PDT 24 May 12 01:19:53 PM PDT 24 14801909156 ps
T415 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.929980879 May 12 01:19:18 PM PDT 24 May 12 01:19:45 PM PDT 24 6100735032 ps
T98 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1959191245 May 12 01:19:23 PM PDT 24 May 12 01:20:01 PM PDT 24 692001797 ps
T416 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2351700041 May 12 01:19:21 PM PDT 24 May 12 01:19:30 PM PDT 24 2062919767 ps
T417 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4094564781 May 12 01:19:22 PM PDT 24 May 12 01:22:09 PM PDT 24 3064612134 ps
T418 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3135761287 May 12 01:19:03 PM PDT 24 May 12 01:19:21 PM PDT 24 995648788 ps
T419 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1082877634 May 12 01:19:19 PM PDT 24 May 12 01:19:49 PM PDT 24 3873536717 ps
T420 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.608494630 May 12 01:19:02 PM PDT 24 May 12 01:19:35 PM PDT 24 9847328063 ps
T421 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.427146562 May 12 01:19:05 PM PDT 24 May 12 01:19:39 PM PDT 24 14027184013 ps
T422 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.883605354 May 12 01:19:05 PM PDT 24 May 12 01:19:21 PM PDT 24 4252343903 ps
T423 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1311258157 May 12 01:19:05 PM PDT 24 May 12 01:19:39 PM PDT 24 7465373429 ps
T424 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4193487866 May 12 01:19:01 PM PDT 24 May 12 01:19:30 PM PDT 24 2935988684 ps
T96 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3420452895 May 12 01:19:19 PM PDT 24 May 12 01:20:15 PM PDT 24 1188689316 ps
T425 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3947140638 May 12 01:19:19 PM PDT 24 May 12 01:21:11 PM PDT 24 13631602669 ps
T426 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3258990957 May 12 01:19:21 PM PDT 24 May 12 01:19:52 PM PDT 24 4059858366 ps
T120 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4031702136 May 12 01:19:07 PM PDT 24 May 12 01:21:49 PM PDT 24 2317832410 ps
T427 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3042875634 May 12 01:19:14 PM PDT 24 May 12 01:19:23 PM PDT 24 688973659 ps
T428 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3585319972 May 12 01:19:27 PM PDT 24 May 12 01:19:59 PM PDT 24 3940796911 ps
T429 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.791135579 May 12 01:19:22 PM PDT 24 May 12 01:19:54 PM PDT 24 49240784327 ps
T430 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2421613266 May 12 01:19:24 PM PDT 24 May 12 01:19:52 PM PDT 24 17623467381 ps
T99 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3140166323 May 12 01:19:11 PM PDT 24 May 12 01:22:11 PM PDT 24 47043711643 ps
T431 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3245823427 May 12 01:19:07 PM PDT 24 May 12 01:19:16 PM PDT 24 756953854 ps
T432 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4137622205 May 12 01:19:19 PM PDT 24 May 12 01:21:17 PM PDT 24 100588444392 ps
T121 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4211545323 May 12 01:19:17 PM PDT 24 May 12 01:21:56 PM PDT 24 1326237308 ps
T433 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.930056957 May 12 01:19:04 PM PDT 24 May 12 01:19:18 PM PDT 24 2958217549 ps
T434 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3785194565 May 12 01:19:05 PM PDT 24 May 12 01:19:41 PM PDT 24 3397449501 ps
T435 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.367287099 May 12 01:19:14 PM PDT 24 May 12 01:20:57 PM PDT 24 73460259853 ps
T117 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3863937540 May 12 01:19:21 PM PDT 24 May 12 01:22:11 PM PDT 24 23887032105 ps
T436 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.883785386 May 12 01:19:20 PM PDT 24 May 12 01:19:28 PM PDT 24 167369631 ps
T437 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2926827695 May 12 01:19:13 PM PDT 24 May 12 01:19:34 PM PDT 24 6973662753 ps
T94 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1571082081 May 12 01:19:03 PM PDT 24 May 12 01:19:17 PM PDT 24 1676584943 ps
T438 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2665114594 May 12 01:19:05 PM PDT 24 May 12 01:19:16 PM PDT 24 688190674 ps
T439 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3528251156 May 12 01:19:20 PM PDT 24 May 12 01:19:34 PM PDT 24 170826553 ps
T114 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.431245746 May 12 01:19:16 PM PDT 24 May 12 01:21:54 PM PDT 24 5990318192 ps
T115 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.976257046 May 12 01:19:16 PM PDT 24 May 12 01:21:55 PM PDT 24 525416130 ps
T440 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1742473653 May 12 01:19:16 PM PDT 24 May 12 01:19:50 PM PDT 24 16449577561 ps
T441 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.971365248 May 12 01:19:22 PM PDT 24 May 12 01:19:34 PM PDT 24 661992995 ps
T442 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.157541936 May 12 01:19:09 PM PDT 24 May 12 01:19:18 PM PDT 24 174685020 ps
T443 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4165747292 May 12 01:19:05 PM PDT 24 May 12 01:19:25 PM PDT 24 1734466148 ps
T444 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.134021932 May 12 01:19:19 PM PDT 24 May 12 01:20:51 PM PDT 24 3332078104 ps
T445 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.280408204 May 12 01:19:12 PM PDT 24 May 12 01:19:21 PM PDT 24 688943139 ps
T112 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4000157739 May 12 01:19:20 PM PDT 24 May 12 01:22:12 PM PDT 24 4058106381 ps
T119 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.221386511 May 12 01:19:12 PM PDT 24 May 12 01:20:55 PM PDT 24 4309985561 ps
T446 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2661625305 May 12 01:19:21 PM PDT 24 May 12 01:19:30 PM PDT 24 185902543 ps
T447 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1464042514 May 12 01:19:19 PM PDT 24 May 12 01:19:44 PM PDT 24 3694562710 ps
T448 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2070716329 May 12 01:19:18 PM PDT 24 May 12 01:19:27 PM PDT 24 167712938 ps
T449 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1665987990 May 12 01:19:03 PM PDT 24 May 12 01:19:36 PM PDT 24 3457226277 ps
T450 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1816096821 May 12 01:19:11 PM PDT 24 May 12 01:19:46 PM PDT 24 20812635395 ps
T451 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3236850457 May 12 01:19:22 PM PDT 24 May 12 01:22:05 PM PDT 24 21108189562 ps
T452 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2298517433 May 12 01:19:27 PM PDT 24 May 12 01:20:55 PM PDT 24 2743031333 ps
T113 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.8694763 May 12 01:19:15 PM PDT 24 May 12 01:20:57 PM PDT 24 4262405732 ps
T453 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1701823094 May 12 01:19:05 PM PDT 24 May 12 01:20:26 PM PDT 24 10493478291 ps

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.919184567
Short name T3
Test name
Test status
Simulation time 84248766571 ps
CPU time 200.3 seconds
Started May 12 01:21:02 PM PDT 24
Finished May 12 01:24:23 PM PDT 24
Peak memory 219956 kb
Host smart-527bd948-e437-47e8-8227-94a9a246fcbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919184567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.919184567
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3038475977
Short name T17
Test name
Test status
Simulation time 28562609793 ps
CPU time 9559.21 seconds
Started May 12 01:20:02 PM PDT 24
Finished May 12 03:59:23 PM PDT 24
Peak memory 232588 kb
Host smart-053451f1-2bc5-4485-869a-5018b15baef0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038475977 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.3038475977
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.22017201
Short name T31
Test name
Test status
Simulation time 306822007857 ps
CPU time 668.86 seconds
Started May 12 01:20:01 PM PDT 24
Finished May 12 01:31:10 PM PDT 24
Peak memory 218360 kb
Host smart-4f5467b4-de96-4e2d-be45-9750ad8aa373
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22017201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_co
rrupt_sig_fatal_chk.22017201
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2445352791
Short name T184
Test name
Test status
Simulation time 791806861410 ps
CPU time 756.63 seconds
Started May 12 01:20:17 PM PDT 24
Finished May 12 01:32:54 PM PDT 24
Peak memory 238292 kb
Host smart-532f9f1a-6639-49e8-addc-bd88fa513463
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445352791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2445352791
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2767348870
Short name T62
Test name
Test status
Simulation time 853902382 ps
CPU time 158.96 seconds
Started May 12 01:19:06 PM PDT 24
Finished May 12 01:21:46 PM PDT 24
Peak memory 218988 kb
Host smart-51501d3c-9274-49bf-a23f-cec7d96824b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767348870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2767348870
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.864735930
Short name T37
Test name
Test status
Simulation time 12531233576 ps
CPU time 27.04 seconds
Started May 12 01:20:22 PM PDT 24
Finished May 12 01:20:50 PM PDT 24
Peak memory 212788 kb
Host smart-b5f18383-695f-4a7a-86fe-8e8cabd30138
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864735930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.864735930
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.225196794
Short name T1
Test name
Test status
Simulation time 18534260632 ps
CPU time 115.04 seconds
Started May 12 01:20:03 PM PDT 24
Finished May 12 01:21:59 PM PDT 24
Peak memory 221628 kb
Host smart-c13d5685-bba3-4eae-9300-cb2d982ec43e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225196794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.225196794
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1042169231
Short name T34
Test name
Test status
Simulation time 15476836698 ps
CPU time 248.22 seconds
Started May 12 01:19:27 PM PDT 24
Finished May 12 01:23:36 PM PDT 24
Peak memory 238624 kb
Host smart-a4613b2e-28f2-4d38-8c42-8c5faee13cca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042169231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1042169231
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3414238574
Short name T80
Test name
Test status
Simulation time 1053669730 ps
CPU time 53.94 seconds
Started May 12 01:19:14 PM PDT 24
Finished May 12 01:20:09 PM PDT 24
Peak memory 213384 kb
Host smart-f3bf9235-5c60-4b4b-b512-c8cfbd390d5e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414238574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3414238574
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2798466278
Short name T10
Test name
Test status
Simulation time 3091064977 ps
CPU time 27.34 seconds
Started May 12 01:20:16 PM PDT 24
Finished May 12 01:20:44 PM PDT 24
Peak memory 217952 kb
Host smart-16ef27d9-758d-40a4-803e-c5a0810a10e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798466278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2798466278
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4031702136
Short name T120
Test name
Test status
Simulation time 2317832410 ps
CPU time 161.98 seconds
Started May 12 01:19:07 PM PDT 24
Finished May 12 01:21:49 PM PDT 24
Peak memory 219116 kb
Host smart-331b1d93-64e6-48b2-a121-011d0a8aa535
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031702136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.4031702136
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.403722280
Short name T4
Test name
Test status
Simulation time 17794664950 ps
CPU time 212.26 seconds
Started May 12 01:19:38 PM PDT 24
Finished May 12 01:23:11 PM PDT 24
Peak memory 236760 kb
Host smart-d4c908df-2de7-4562-a588-06f059d8f93b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403722280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.403722280
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1802842293
Short name T139
Test name
Test status
Simulation time 8548073229 ps
CPU time 44.4 seconds
Started May 12 01:19:39 PM PDT 24
Finished May 12 01:20:23 PM PDT 24
Peak memory 215020 kb
Host smart-9aa05bd1-29b3-40ae-b780-f4b5a3a77ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802842293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1802842293
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1999656804
Short name T21
Test name
Test status
Simulation time 662729882 ps
CPU time 19.25 seconds
Started May 12 01:19:46 PM PDT 24
Finished May 12 01:20:06 PM PDT 24
Peak memory 215292 kb
Host smart-8140f6f8-3186-4112-8595-af3cd4ce7f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999656804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1999656804
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.84658771
Short name T27
Test name
Test status
Simulation time 6059314080 ps
CPU time 55.12 seconds
Started May 12 01:20:43 PM PDT 24
Finished May 12 01:21:38 PM PDT 24
Peak memory 215436 kb
Host smart-66490a2d-0bf3-488c-8fe3-eea3e223d243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84658771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.84658771
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4000157739
Short name T112
Test name
Test status
Simulation time 4058106381 ps
CPU time 171.54 seconds
Started May 12 01:19:20 PM PDT 24
Finished May 12 01:22:12 PM PDT 24
Peak memory 213488 kb
Host smart-84b871fa-3be1-4054-9e78-760a8636db79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000157739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.4000157739
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4070979355
Short name T82
Test name
Test status
Simulation time 90219917890 ps
CPU time 182.07 seconds
Started May 12 01:19:06 PM PDT 24
Finished May 12 01:22:09 PM PDT 24
Peak memory 219040 kb
Host smart-5a77e2ec-8536-4928-a673-c1ea2aea6ea1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070979355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.4070979355
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.221386511
Short name T119
Test name
Test status
Simulation time 4309985561 ps
CPU time 102.6 seconds
Started May 12 01:19:12 PM PDT 24
Finished May 12 01:20:55 PM PDT 24
Peak memory 213272 kb
Host smart-8b8e4b0b-1254-48aa-a026-d6cb29853d87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221386511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.221386511
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3272509048
Short name T93
Test name
Test status
Simulation time 1920194312 ps
CPU time 20.57 seconds
Started May 12 01:19:00 PM PDT 24
Finished May 12 01:19:21 PM PDT 24
Peak memory 210892 kb
Host smart-01026b14-86fb-40d3-9c3e-a00930b9684d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272509048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3272509048
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.435832558
Short name T20
Test name
Test status
Simulation time 107044874565 ps
CPU time 2032.8 seconds
Started May 12 01:19:27 PM PDT 24
Finished May 12 01:53:21 PM PDT 24
Peak memory 248968 kb
Host smart-c1296a88-9628-46fe-93d9-0bb015cebab7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435832558 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.435832558
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3288002826
Short name T363
Test name
Test status
Simulation time 15117201359 ps
CPU time 21.83 seconds
Started May 12 01:19:02 PM PDT 24
Finished May 12 01:19:24 PM PDT 24
Peak memory 212020 kb
Host smart-a6826b81-b5a6-401f-a73b-7f83bb0719f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288002826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3288002826
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3785194565
Short name T434
Test name
Test status
Simulation time 3397449501 ps
CPU time 35.11 seconds
Started May 12 01:19:05 PM PDT 24
Finished May 12 01:19:41 PM PDT 24
Peak memory 211376 kb
Host smart-51e453f4-39c8-481f-af2d-543e61a88ef9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785194565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3785194565
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3584429703
Short name T390
Test name
Test status
Simulation time 2148708270 ps
CPU time 21.41 seconds
Started May 12 01:19:03 PM PDT 24
Finished May 12 01:19:25 PM PDT 24
Peak memory 219160 kb
Host smart-8fb98b6a-c1ac-416d-9d4b-cec2930b160c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584429703 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3584429703
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2702645950
Short name T85
Test name
Test status
Simulation time 172425438 ps
CPU time 8.37 seconds
Started May 12 01:19:03 PM PDT 24
Finished May 12 01:19:12 PM PDT 24
Peak memory 210728 kb
Host smart-f5d2e02b-abfd-4c09-a26a-d8a57bb3efc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702645950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2702645950
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.736829991
Short name T355
Test name
Test status
Simulation time 2052650822 ps
CPU time 19.61 seconds
Started May 12 01:19:02 PM PDT 24
Finished May 12 01:19:22 PM PDT 24
Peak memory 210888 kb
Host smart-2dc6c0af-8fa5-4647-9e7e-d073a4016b5b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736829991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.736829991
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.604824892
Short name T359
Test name
Test status
Simulation time 7056232229 ps
CPU time 32.9 seconds
Started May 12 01:19:01 PM PDT 24
Finished May 12 01:19:35 PM PDT 24
Peak memory 210748 kb
Host smart-089ad2a2-716c-4915-865c-e37a321daaa6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604824892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
604824892
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3229877693
Short name T368
Test name
Test status
Simulation time 17139199466 ps
CPU time 153.34 seconds
Started May 12 01:19:04 PM PDT 24
Finished May 12 01:21:38 PM PDT 24
Peak memory 215260 kb
Host smart-3994713b-2421-4e7d-8e2e-eff4241c4a05
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229877693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3229877693
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.146257632
Short name T104
Test name
Test status
Simulation time 5381339925 ps
CPU time 28.13 seconds
Started May 12 01:19:00 PM PDT 24
Finished May 12 01:19:29 PM PDT 24
Peak memory 212208 kb
Host smart-70a66dbd-4087-41bb-8826-3a8dd4dbd739
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146257632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.146257632
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4193487866
Short name T424
Test name
Test status
Simulation time 2935988684 ps
CPU time 28.4 seconds
Started May 12 01:19:01 PM PDT 24
Finished May 12 01:19:30 PM PDT 24
Peak memory 217852 kb
Host smart-e6b99ecf-400a-4853-9f07-8d09f3e2b6d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193487866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.4193487866
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2370377686
Short name T116
Test name
Test status
Simulation time 2683534963 ps
CPU time 164.66 seconds
Started May 12 01:19:03 PM PDT 24
Finished May 12 01:21:48 PM PDT 24
Peak memory 213264 kb
Host smart-e97a6f4a-b8e7-4616-91fe-8e83c826cfab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370377686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2370377686
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3713605663
Short name T92
Test name
Test status
Simulation time 689527863 ps
CPU time 8.23 seconds
Started May 12 01:19:05 PM PDT 24
Finished May 12 01:19:14 PM PDT 24
Peak memory 210808 kb
Host smart-fc314aba-4fc5-4878-b070-f3ddccb2e51e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713605663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3713605663
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.930056957
Short name T433
Test name
Test status
Simulation time 2958217549 ps
CPU time 13.49 seconds
Started May 12 01:19:04 PM PDT 24
Finished May 12 01:19:18 PM PDT 24
Peak memory 219056 kb
Host smart-acecff25-d4db-431d-a4b1-a5e09fddd3ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930056957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.930056957
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1235547116
Short name T77
Test name
Test status
Simulation time 3206036593 ps
CPU time 30.63 seconds
Started May 12 01:19:01 PM PDT 24
Finished May 12 01:19:32 PM PDT 24
Peak memory 211104 kb
Host smart-91f960bf-03c0-436e-84e9-45774a1041d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235547116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1235547116
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.608494630
Short name T420
Test name
Test status
Simulation time 9847328063 ps
CPU time 32.52 seconds
Started May 12 01:19:02 PM PDT 24
Finished May 12 01:19:35 PM PDT 24
Peak memory 219188 kb
Host smart-7afba498-2fb9-4da5-b632-da119bb90387
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608494630 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.608494630
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1571082081
Short name T94
Test name
Test status
Simulation time 1676584943 ps
CPU time 13.55 seconds
Started May 12 01:19:03 PM PDT 24
Finished May 12 01:19:17 PM PDT 24
Peak memory 210860 kb
Host smart-ac4efd4b-bc3b-40e2-b92a-9f7341106ae2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571082081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1571082081
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1587461574
Short name T402
Test name
Test status
Simulation time 718652360 ps
CPU time 8.14 seconds
Started May 12 01:19:03 PM PDT 24
Finished May 12 01:19:12 PM PDT 24
Peak memory 210644 kb
Host smart-04a0cdd1-07d5-4b15-984d-6ff0a7d32465
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587461574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1587461574
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2380556883
Short name T365
Test name
Test status
Simulation time 10890706167 ps
CPU time 24.01 seconds
Started May 12 01:19:04 PM PDT 24
Finished May 12 01:19:28 PM PDT 24
Peak memory 210848 kb
Host smart-f1d981a8-54f4-43fc-adfc-6e98b25ab942
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380556883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2380556883
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.167367705
Short name T373
Test name
Test status
Simulation time 27730213629 ps
CPU time 140.63 seconds
Started May 12 01:19:03 PM PDT 24
Finished May 12 01:21:25 PM PDT 24
Peak memory 215000 kb
Host smart-bd9c8058-a1ff-496e-bb02-3ca538e5cee6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167367705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.167367705
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2754717027
Short name T100
Test name
Test status
Simulation time 15033836385 ps
CPU time 30.22 seconds
Started May 12 01:19:03 PM PDT 24
Finished May 12 01:19:33 PM PDT 24
Peak memory 212140 kb
Host smart-bfe73e2a-1cc5-40eb-9660-4d3670dc4386
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754717027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2754717027
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1100847160
Short name T393
Test name
Test status
Simulation time 10811012837 ps
CPU time 29.04 seconds
Started May 12 01:19:02 PM PDT 24
Finished May 12 01:19:32 PM PDT 24
Peak memory 219208 kb
Host smart-446af70f-f60f-43a3-940a-6d6d59f63420
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100847160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1100847160
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.693498260
Short name T391
Test name
Test status
Simulation time 6873581712 ps
CPU time 28.21 seconds
Started May 12 01:19:18 PM PDT 24
Finished May 12 01:19:47 PM PDT 24
Peak memory 219188 kb
Host smart-a3325898-b58f-4483-b8f3-1bc08d6702a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693498260 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.693498260
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2965337656
Short name T407
Test name
Test status
Simulation time 661246020 ps
CPU time 8.07 seconds
Started May 12 01:19:18 PM PDT 24
Finished May 12 01:19:27 PM PDT 24
Peak memory 210776 kb
Host smart-010d224e-920c-4c7b-b644-1916b40c765c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965337656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2965337656
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3420452895
Short name T96
Test name
Test status
Simulation time 1188689316 ps
CPU time 55.4 seconds
Started May 12 01:19:19 PM PDT 24
Finished May 12 01:20:15 PM PDT 24
Peak memory 213948 kb
Host smart-e53e501b-08f9-48b9-93bf-a73b9dab7c79
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420452895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3420452895
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2647435568
Short name T394
Test name
Test status
Simulation time 2971981608 ps
CPU time 25.3 seconds
Started May 12 01:19:18 PM PDT 24
Finished May 12 01:19:44 PM PDT 24
Peak memory 211760 kb
Host smart-29093da7-67a9-439e-bf01-4bd57b91d51d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647435568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2647435568
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3528251156
Short name T439
Test name
Test status
Simulation time 170826553 ps
CPU time 13.13 seconds
Started May 12 01:19:20 PM PDT 24
Finished May 12 01:19:34 PM PDT 24
Peak memory 217008 kb
Host smart-4ff47836-80ee-4bd3-9d92-f074bc64af56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528251156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3528251156
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2298517433
Short name T452
Test name
Test status
Simulation time 2743031333 ps
CPU time 87.17 seconds
Started May 12 01:19:27 PM PDT 24
Finished May 12 01:20:55 PM PDT 24
Peak memory 219012 kb
Host smart-c82f0b1d-f7ff-4b3a-bb6c-71c1f8506554
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298517433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2298517433
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4064724918
Short name T360
Test name
Test status
Simulation time 1689290841 ps
CPU time 14.06 seconds
Started May 12 01:19:18 PM PDT 24
Finished May 12 01:19:33 PM PDT 24
Peak memory 214976 kb
Host smart-6b315827-061b-4872-9698-841412f30c1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064724918 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4064724918
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1464042514
Short name T447
Test name
Test status
Simulation time 3694562710 ps
CPU time 24.43 seconds
Started May 12 01:19:19 PM PDT 24
Finished May 12 01:19:44 PM PDT 24
Peak memory 211344 kb
Host smart-83471ec6-f94e-4586-80a1-e030d65cab40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464042514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1464042514
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4137622205
Short name T432
Test name
Test status
Simulation time 100588444392 ps
CPU time 117.55 seconds
Started May 12 01:19:19 PM PDT 24
Finished May 12 01:21:17 PM PDT 24
Peak memory 214112 kb
Host smart-8cf24bcc-a463-4e0a-afb9-3bf764c2c657
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137622205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.4137622205
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3552475983
Short name T81
Test name
Test status
Simulation time 4962487677 ps
CPU time 20.95 seconds
Started May 12 01:19:20 PM PDT 24
Finished May 12 01:19:41 PM PDT 24
Peak memory 212276 kb
Host smart-f2a9c95a-7da2-4cb7-9622-c38b4778fc3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552475983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3552475983
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.122798490
Short name T398
Test name
Test status
Simulation time 3225407610 ps
CPU time 30.2 seconds
Started May 12 01:19:18 PM PDT 24
Finished May 12 01:19:48 PM PDT 24
Peak memory 219156 kb
Host smart-e757986a-a1f8-4177-a7f3-f88dfd9d4485
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122798490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.122798490
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.976257046
Short name T115
Test name
Test status
Simulation time 525416130 ps
CPU time 158.37 seconds
Started May 12 01:19:16 PM PDT 24
Finished May 12 01:21:55 PM PDT 24
Peak memory 213664 kb
Host smart-7ba195b4-daa5-448a-a317-ed6a7266af88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976257046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.976257046
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.788272367
Short name T410
Test name
Test status
Simulation time 706195492 ps
CPU time 8.31 seconds
Started May 12 01:19:18 PM PDT 24
Finished May 12 01:19:27 PM PDT 24
Peak memory 213640 kb
Host smart-35d020e1-0097-4c03-a1b9-5ea828123dc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788272367 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.788272367
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2537568567
Short name T406
Test name
Test status
Simulation time 11651671401 ps
CPU time 24.85 seconds
Started May 12 01:19:27 PM PDT 24
Finished May 12 01:19:53 PM PDT 24
Peak memory 211840 kb
Host smart-76aa88cd-6fb5-4924-b4b6-6dbad4a0d96f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537568567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2537568567
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3980155949
Short name T399
Test name
Test status
Simulation time 719061545 ps
CPU time 37.54 seconds
Started May 12 01:19:17 PM PDT 24
Finished May 12 01:19:55 PM PDT 24
Peak memory 212960 kb
Host smart-92da35f3-4887-4181-8d33-69c80dca8497
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980155949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3980155949
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1082877634
Short name T419
Test name
Test status
Simulation time 3873536717 ps
CPU time 29.34 seconds
Started May 12 01:19:19 PM PDT 24
Finished May 12 01:19:49 PM PDT 24
Peak memory 211964 kb
Host smart-05644599-7b47-46d8-97a7-b554f9b82643
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082877634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1082877634
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4171792897
Short name T408
Test name
Test status
Simulation time 3835432510 ps
CPU time 26.68 seconds
Started May 12 01:19:19 PM PDT 24
Finished May 12 01:19:46 PM PDT 24
Peak memory 215936 kb
Host smart-ba36accc-7653-44dd-945a-4454bfe0df33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171792897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.4171792897
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.46763425
Short name T389
Test name
Test status
Simulation time 9192719390 ps
CPU time 21.45 seconds
Started May 12 01:19:19 PM PDT 24
Finished May 12 01:19:41 PM PDT 24
Peak memory 217212 kb
Host smart-dbc933d8-bfe6-4160-8118-563f23d61903
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46763425 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.46763425
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3703022962
Short name T376
Test name
Test status
Simulation time 689157755 ps
CPU time 8.22 seconds
Started May 12 01:19:21 PM PDT 24
Finished May 12 01:19:29 PM PDT 24
Peak memory 210768 kb
Host smart-979213de-9564-4731-8d6b-76ce41b5efe2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703022962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3703022962
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.929980879
Short name T415
Test name
Test status
Simulation time 6100735032 ps
CPU time 26.52 seconds
Started May 12 01:19:18 PM PDT 24
Finished May 12 01:19:45 PM PDT 24
Peak memory 211384 kb
Host smart-024cc317-db0f-4af2-92b1-0b0f11466fb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929980879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.929980879
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3539473413
Short name T357
Test name
Test status
Simulation time 7339489966 ps
CPU time 32.39 seconds
Started May 12 01:19:18 PM PDT 24
Finished May 12 01:19:51 PM PDT 24
Peak memory 219068 kb
Host smart-7ae33ebb-d085-401a-93c3-6a12a8487dac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539473413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3539473413
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.134021932
Short name T444
Test name
Test status
Simulation time 3332078104 ps
CPU time 91.4 seconds
Started May 12 01:19:19 PM PDT 24
Finished May 12 01:20:51 PM PDT 24
Peak memory 213208 kb
Host smart-df275b13-9778-40ec-8770-842fb19fd148
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134021932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.134021932
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3585319972
Short name T428
Test name
Test status
Simulation time 3940796911 ps
CPU time 31.55 seconds
Started May 12 01:19:27 PM PDT 24
Finished May 12 01:19:59 PM PDT 24
Peak memory 217440 kb
Host smart-6493f247-57c0-4bd4-b57e-f0d5a0b116cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585319972 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3585319972
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3966344817
Short name T400
Test name
Test status
Simulation time 1957279585 ps
CPU time 17.91 seconds
Started May 12 01:19:20 PM PDT 24
Finished May 12 01:19:38 PM PDT 24
Peak memory 211628 kb
Host smart-37d9c0b0-94b1-4a50-8356-691cd7985530
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966344817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3966344817
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1099374200
Short name T411
Test name
Test status
Simulation time 2748815211 ps
CPU time 37.13 seconds
Started May 12 01:19:18 PM PDT 24
Finished May 12 01:19:56 PM PDT 24
Peak memory 212992 kb
Host smart-4ff63ce3-3e79-414d-b2a0-338403728539
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099374200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1099374200
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.883785386
Short name T436
Test name
Test status
Simulation time 167369631 ps
CPU time 8.17 seconds
Started May 12 01:19:20 PM PDT 24
Finished May 12 01:19:28 PM PDT 24
Peak memory 211012 kb
Host smart-c75cf61f-93ef-4d90-9a1e-6143c2b8d2ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883785386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.883785386
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2565760519
Short name T76
Test name
Test status
Simulation time 14405728291 ps
CPU time 34.72 seconds
Started May 12 01:19:18 PM PDT 24
Finished May 12 01:19:53 PM PDT 24
Peak memory 218428 kb
Host smart-98a5649a-75ae-460c-8136-0ad22ebc2c52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565760519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2565760519
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4211545323
Short name T121
Test name
Test status
Simulation time 1326237308 ps
CPU time 158.22 seconds
Started May 12 01:19:17 PM PDT 24
Finished May 12 01:21:56 PM PDT 24
Peak memory 213468 kb
Host smart-d05e3d9b-2de9-4e40-8307-5fe1518883d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211545323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.4211545323
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3097457224
Short name T388
Test name
Test status
Simulation time 7698910689 ps
CPU time 29.96 seconds
Started May 12 01:19:27 PM PDT 24
Finished May 12 01:19:57 PM PDT 24
Peak memory 215936 kb
Host smart-9827ab4b-222b-4b66-bdbd-f8e3fc70d816
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097457224 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3097457224
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2070716329
Short name T448
Test name
Test status
Simulation time 167712938 ps
CPU time 8.15 seconds
Started May 12 01:19:18 PM PDT 24
Finished May 12 01:19:27 PM PDT 24
Peak memory 210844 kb
Host smart-c4dca3a2-8398-4e3f-914c-d5d0b4c0ccf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070716329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2070716329
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3905380342
Short name T383
Test name
Test status
Simulation time 6969230025 ps
CPU time 82.48 seconds
Started May 12 01:19:18 PM PDT 24
Finished May 12 01:20:41 PM PDT 24
Peak memory 215048 kb
Host smart-a1e02e89-6c1f-4c7b-8604-63b4ee9299cd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905380342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3905380342
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3112065332
Short name T102
Test name
Test status
Simulation time 3140953237 ps
CPU time 26.05 seconds
Started May 12 01:19:26 PM PDT 24
Finished May 12 01:19:53 PM PDT 24
Peak memory 211748 kb
Host smart-568aba48-4885-4e2a-b096-7b17316ff364
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112065332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3112065332
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1626406010
Short name T381
Test name
Test status
Simulation time 174235966 ps
CPU time 13.35 seconds
Started May 12 01:19:22 PM PDT 24
Finished May 12 01:19:36 PM PDT 24
Peak memory 217292 kb
Host smart-73cf3e02-fca7-4706-a7da-aea46b7bf070
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626406010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1626406010
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1141138961
Short name T118
Test name
Test status
Simulation time 805071103 ps
CPU time 164.22 seconds
Started May 12 01:19:22 PM PDT 24
Finished May 12 01:22:07 PM PDT 24
Peak memory 213760 kb
Host smart-c9df99db-415c-46b0-81f3-286b3502d7eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141138961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1141138961
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2661625305
Short name T446
Test name
Test status
Simulation time 185902543 ps
CPU time 8.77 seconds
Started May 12 01:19:21 PM PDT 24
Finished May 12 01:19:30 PM PDT 24
Peak memory 219064 kb
Host smart-8cf5b6bb-1956-4f40-8320-a5246d166526
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661625305 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2661625305
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4222725873
Short name T101
Test name
Test status
Simulation time 1666137295 ps
CPU time 15.08 seconds
Started May 12 01:19:28 PM PDT 24
Finished May 12 01:19:44 PM PDT 24
Peak memory 210748 kb
Host smart-87ba3f62-9d70-45b8-b2da-8d916eb0d602
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222725873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.4222725873
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3947140638
Short name T425
Test name
Test status
Simulation time 13631602669 ps
CPU time 111.53 seconds
Started May 12 01:19:19 PM PDT 24
Finished May 12 01:21:11 PM PDT 24
Peak memory 214056 kb
Host smart-fbb9aca8-0278-4b02-8c31-f6589be1e8c1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947140638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3947140638
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1159044056
Short name T103
Test name
Test status
Simulation time 4107822250 ps
CPU time 32.46 seconds
Started May 12 01:19:25 PM PDT 24
Finished May 12 01:19:58 PM PDT 24
Peak memory 212108 kb
Host smart-5b1f0040-00db-4d7f-aba0-b4ec26097cf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159044056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1159044056
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.971365248
Short name T441
Test name
Test status
Simulation time 661992995 ps
CPU time 11.11 seconds
Started May 12 01:19:22 PM PDT 24
Finished May 12 01:19:34 PM PDT 24
Peak memory 219104 kb
Host smart-53ed71bc-382e-4a5c-b5a4-b3bab1c6e902
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971365248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.971365248
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1826401066
Short name T110
Test name
Test status
Simulation time 2534143482 ps
CPU time 85.29 seconds
Started May 12 01:19:20 PM PDT 24
Finished May 12 01:20:46 PM PDT 24
Peak memory 219124 kb
Host smart-996c220e-b103-4c93-943b-b6071363dd5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826401066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1826401066
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3212771284
Short name T362
Test name
Test status
Simulation time 3997094063 ps
CPU time 30.92 seconds
Started May 12 01:19:24 PM PDT 24
Finished May 12 01:19:55 PM PDT 24
Peak memory 214964 kb
Host smart-e9edeed3-5657-4436-8716-041503a69965
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212771284 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3212771284
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3258990957
Short name T426
Test name
Test status
Simulation time 4059858366 ps
CPU time 30.26 seconds
Started May 12 01:19:21 PM PDT 24
Finished May 12 01:19:52 PM PDT 24
Peak memory 211372 kb
Host smart-9c8302b2-641f-42f3-91ab-eaf78c23be3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258990957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3258990957
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1959191245
Short name T98
Test name
Test status
Simulation time 692001797 ps
CPU time 37.12 seconds
Started May 12 01:19:23 PM PDT 24
Finished May 12 01:20:01 PM PDT 24
Peak memory 212824 kb
Host smart-4a4d0f65-b9e8-406a-bf2c-e022b2152135
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959191245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1959191245
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1699669917
Short name T387
Test name
Test status
Simulation time 332386956 ps
CPU time 8.27 seconds
Started May 12 01:19:24 PM PDT 24
Finished May 12 01:19:33 PM PDT 24
Peak memory 210860 kb
Host smart-f8baabdc-9f70-4998-8a2d-5b0e49c93638
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699669917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1699669917
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3137654686
Short name T366
Test name
Test status
Simulation time 15236943553 ps
CPU time 33.69 seconds
Started May 12 01:19:21 PM PDT 24
Finished May 12 01:19:55 PM PDT 24
Peak memory 219196 kb
Host smart-31048ef6-d8fb-40dc-9cea-f4eef2d6e19c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137654686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3137654686
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3863937540
Short name T117
Test name
Test status
Simulation time 23887032105 ps
CPU time 169.48 seconds
Started May 12 01:19:21 PM PDT 24
Finished May 12 01:22:11 PM PDT 24
Peak memory 219084 kb
Host smart-4c10cd87-f4a6-4276-892c-68075ce0c68f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863937540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3863937540
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2421613266
Short name T430
Test name
Test status
Simulation time 17623467381 ps
CPU time 28.33 seconds
Started May 12 01:19:24 PM PDT 24
Finished May 12 01:19:52 PM PDT 24
Peak memory 219072 kb
Host smart-3a700d0d-8a86-45cd-9007-c9b91444d946
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421613266 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2421613266
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4217627708
Short name T396
Test name
Test status
Simulation time 6571095752 ps
CPU time 19.03 seconds
Started May 12 01:19:24 PM PDT 24
Finished May 12 01:19:43 PM PDT 24
Peak memory 212164 kb
Host smart-09a72371-f073-4b38-8069-9a63f357b95f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217627708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.4217627708
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3225183850
Short name T403
Test name
Test status
Simulation time 19538173124 ps
CPU time 114.65 seconds
Started May 12 01:19:23 PM PDT 24
Finished May 12 01:21:19 PM PDT 24
Peak memory 219028 kb
Host smart-4ad5f2e8-f6ca-4d34-9feb-f10572e27add
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225183850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3225183850
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.917353641
Short name T380
Test name
Test status
Simulation time 385691898 ps
CPU time 8.22 seconds
Started May 12 01:19:21 PM PDT 24
Finished May 12 01:19:30 PM PDT 24
Peak memory 210868 kb
Host smart-abe3b041-3336-4cc3-8b20-a9bc15587d04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917353641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.917353641
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2407964328
Short name T377
Test name
Test status
Simulation time 10547445991 ps
CPU time 28.08 seconds
Started May 12 01:19:22 PM PDT 24
Finished May 12 01:19:51 PM PDT 24
Peak memory 218356 kb
Host smart-b8a08957-cb37-41f6-81b7-113c740a12bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407964328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2407964328
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3236850457
Short name T451
Test name
Test status
Simulation time 21108189562 ps
CPU time 162.53 seconds
Started May 12 01:19:22 PM PDT 24
Finished May 12 01:22:05 PM PDT 24
Peak memory 213736 kb
Host smart-6fbc9871-5dff-469e-975a-048ebd6091a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236850457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3236850457
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3282472082
Short name T414
Test name
Test status
Simulation time 14801909156 ps
CPU time 24.82 seconds
Started May 12 01:19:27 PM PDT 24
Finished May 12 01:19:53 PM PDT 24
Peak memory 217936 kb
Host smart-939e0131-69b0-4cac-88a6-45e4c9460077
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282472082 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3282472082
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2351700041
Short name T416
Test name
Test status
Simulation time 2062919767 ps
CPU time 8.2 seconds
Started May 12 01:19:21 PM PDT 24
Finished May 12 01:19:30 PM PDT 24
Peak memory 210864 kb
Host smart-2dd39932-0d54-40cc-b7d1-5c39422402e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351700041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2351700041
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1523611410
Short name T84
Test name
Test status
Simulation time 1081978948 ps
CPU time 56.65 seconds
Started May 12 01:19:23 PM PDT 24
Finished May 12 01:20:20 PM PDT 24
Peak memory 212932 kb
Host smart-62a51453-f4f9-4bb9-96a3-447ee8bc4167
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523611410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1523611410
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.791135579
Short name T429
Test name
Test status
Simulation time 49240784327 ps
CPU time 31.31 seconds
Started May 12 01:19:22 PM PDT 24
Finished May 12 01:19:54 PM PDT 24
Peak memory 211844 kb
Host smart-ce0b5b09-a956-4f94-9219-0c5adec584e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791135579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.791135579
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2952244393
Short name T367
Test name
Test status
Simulation time 3714420429 ps
CPU time 33.91 seconds
Started May 12 01:19:20 PM PDT 24
Finished May 12 01:19:54 PM PDT 24
Peak memory 218220 kb
Host smart-61742860-0329-4bd8-9a40-6dd08ccc3c49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952244393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2952244393
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4094564781
Short name T417
Test name
Test status
Simulation time 3064612134 ps
CPU time 166.74 seconds
Started May 12 01:19:22 PM PDT 24
Finished May 12 01:22:09 PM PDT 24
Peak memory 219092 kb
Host smart-5aa40b27-be2f-4919-b833-82ddda5c9833
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094564781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.4094564781
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3389696913
Short name T65
Test name
Test status
Simulation time 4171134376 ps
CPU time 34.27 seconds
Started May 12 01:19:06 PM PDT 24
Finished May 12 01:19:41 PM PDT 24
Peak memory 211444 kb
Host smart-93bf3a2c-57a9-4578-a279-02ed7673b9fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389696913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3389696913
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.883605354
Short name T422
Test name
Test status
Simulation time 4252343903 ps
CPU time 15.46 seconds
Started May 12 01:19:05 PM PDT 24
Finished May 12 01:19:21 PM PDT 24
Peak memory 211188 kb
Host smart-2bed2b7f-99c9-41bb-b61e-bcaf52802b6e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883605354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.883605354
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1210346071
Short name T107
Test name
Test status
Simulation time 3068346682 ps
CPU time 32.48 seconds
Started May 12 01:19:00 PM PDT 24
Finished May 12 01:19:33 PM PDT 24
Peak memory 211316 kb
Host smart-2af58f71-978d-4a92-b26a-7849a4c6fbce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210346071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1210346071
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3245823427
Short name T431
Test name
Test status
Simulation time 756953854 ps
CPU time 9.23 seconds
Started May 12 01:19:07 PM PDT 24
Finished May 12 01:19:16 PM PDT 24
Peak memory 219324 kb
Host smart-8c4a7165-8fd5-4451-af30-a060957aba39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245823427 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3245823427
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1135858904
Short name T404
Test name
Test status
Simulation time 3118375361 ps
CPU time 27.53 seconds
Started May 12 01:19:02 PM PDT 24
Finished May 12 01:19:30 PM PDT 24
Peak memory 211700 kb
Host smart-4e99c989-270b-4523-8f91-e50d4dfb48f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135858904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1135858904
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3826526874
Short name T413
Test name
Test status
Simulation time 7750200074 ps
CPU time 25.24 seconds
Started May 12 01:19:04 PM PDT 24
Finished May 12 01:19:30 PM PDT 24
Peak memory 210732 kb
Host smart-dc4cbb2f-23d0-4f92-bb77-43cda7594b68
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826526874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3826526874
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.940292441
Short name T370
Test name
Test status
Simulation time 12948622907 ps
CPU time 25.51 seconds
Started May 12 01:19:01 PM PDT 24
Finished May 12 01:19:27 PM PDT 24
Peak memory 210776 kb
Host smart-196ca111-550b-4522-835d-a38ab8563bef
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940292441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
940292441
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1311258157
Short name T423
Test name
Test status
Simulation time 7465373429 ps
CPU time 32.78 seconds
Started May 12 01:19:05 PM PDT 24
Finished May 12 01:19:39 PM PDT 24
Peak memory 212128 kb
Host smart-bdbb9f3f-7bd5-478c-9b41-d7eb151bbf53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311258157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1311258157
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3135761287
Short name T418
Test name
Test status
Simulation time 995648788 ps
CPU time 18.26 seconds
Started May 12 01:19:03 PM PDT 24
Finished May 12 01:19:21 PM PDT 24
Peak memory 219084 kb
Host smart-d8785c32-3100-4272-a434-a0db0a92ff69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135761287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3135761287
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3064122571
Short name T55
Test name
Test status
Simulation time 16618393310 ps
CPU time 173.23 seconds
Started May 12 01:19:02 PM PDT 24
Finished May 12 01:21:56 PM PDT 24
Peak memory 213732 kb
Host smart-22f692d7-718e-431d-839c-596c7ed19669
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064122571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3064122571
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2916829512
Short name T78
Test name
Test status
Simulation time 2217634795 ps
CPU time 15.28 seconds
Started May 12 01:19:14 PM PDT 24
Finished May 12 01:19:29 PM PDT 24
Peak memory 210904 kb
Host smart-415096af-b308-4045-bbdf-ed5aa7111f9a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916829512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2916829512
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.427146562
Short name T421
Test name
Test status
Simulation time 14027184013 ps
CPU time 32.53 seconds
Started May 12 01:19:05 PM PDT 24
Finished May 12 01:19:39 PM PDT 24
Peak memory 211768 kb
Host smart-69767297-e96e-479d-a377-81a35b6027f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427146562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.427146562
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1194777894
Short name T105
Test name
Test status
Simulation time 6869893805 ps
CPU time 31.88 seconds
Started May 12 01:19:06 PM PDT 24
Finished May 12 01:19:39 PM PDT 24
Peak memory 211832 kb
Host smart-4edcfc5b-f975-4ddf-a537-d71f37f014b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194777894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1194777894
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3469348857
Short name T356
Test name
Test status
Simulation time 17696223421 ps
CPU time 31.16 seconds
Started May 12 01:19:05 PM PDT 24
Finished May 12 01:19:37 PM PDT 24
Peak memory 217664 kb
Host smart-24370281-55a8-4621-851b-fcbe7c40209c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469348857 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3469348857
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1188952377
Short name T97
Test name
Test status
Simulation time 3083796895 ps
CPU time 26.16 seconds
Started May 12 01:19:05 PM PDT 24
Finished May 12 01:19:32 PM PDT 24
Peak memory 211096 kb
Host smart-5276bacd-970f-4c1f-93f9-db8652f29d10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188952377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1188952377
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.13174603
Short name T361
Test name
Test status
Simulation time 2688797160 ps
CPU time 23.7 seconds
Started May 12 01:19:06 PM PDT 24
Finished May 12 01:19:30 PM PDT 24
Peak memory 210756 kb
Host smart-c4a05365-d7d2-4c47-9ad5-58992d772bf0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13174603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_
mem_partial_access.13174603
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.157541936
Short name T442
Test name
Test status
Simulation time 174685020 ps
CPU time 8.21 seconds
Started May 12 01:19:09 PM PDT 24
Finished May 12 01:19:18 PM PDT 24
Peak memory 210776 kb
Host smart-f7a1eb12-07d8-454f-b1bb-e211e353b60e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157541936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
157541936
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1699851103
Short name T83
Test name
Test status
Simulation time 12918848563 ps
CPU time 74.73 seconds
Started May 12 01:19:06 PM PDT 24
Finished May 12 01:20:21 PM PDT 24
Peak memory 213972 kb
Host smart-056aecd0-24d4-432d-a053-465e7f090ec5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699851103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1699851103
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2665114594
Short name T438
Test name
Test status
Simulation time 688190674 ps
CPU time 10.43 seconds
Started May 12 01:19:05 PM PDT 24
Finished May 12 01:19:16 PM PDT 24
Peak memory 210860 kb
Host smart-ec462466-b813-49dd-a9b3-e4c8f3502b5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665114594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2665114594
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1665987990
Short name T449
Test name
Test status
Simulation time 3457226277 ps
CPU time 31.84 seconds
Started May 12 01:19:03 PM PDT 24
Finished May 12 01:19:36 PM PDT 24
Peak memory 218056 kb
Host smart-9f60e282-2bc8-4663-8fe3-9a86c4341f2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665987990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1665987990
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.661108583
Short name T63
Test name
Test status
Simulation time 4504030141 ps
CPU time 176.45 seconds
Started May 12 01:19:05 PM PDT 24
Finished May 12 01:22:03 PM PDT 24
Peak memory 213868 kb
Host smart-4e1d4423-6a90-4a84-b60e-0a5e982fce0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661108583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.661108583
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3908152498
Short name T409
Test name
Test status
Simulation time 3523767271 ps
CPU time 28.61 seconds
Started May 12 01:19:09 PM PDT 24
Finished May 12 01:19:38 PM PDT 24
Peak memory 219116 kb
Host smart-0e234c59-9b4b-46be-bf7c-8ca08c4fd179
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908152498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3908152498
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.507290100
Short name T106
Test name
Test status
Simulation time 9573268486 ps
CPU time 22.13 seconds
Started May 12 01:19:09 PM PDT 24
Finished May 12 01:19:32 PM PDT 24
Peak memory 211680 kb
Host smart-71c8fc49-7bf9-4a04-817d-8cc750d388c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507290100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.507290100
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.9604672
Short name T384
Test name
Test status
Simulation time 177319505 ps
CPU time 15.45 seconds
Started May 12 01:19:09 PM PDT 24
Finished May 12 01:19:25 PM PDT 24
Peak memory 211476 kb
Host smart-a09e45ac-98df-4513-b88b-c5f984f7c736
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9604672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_rese
t.9604672
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1995898483
Short name T358
Test name
Test status
Simulation time 7024696591 ps
CPU time 19.72 seconds
Started May 12 01:19:05 PM PDT 24
Finished May 12 01:19:26 PM PDT 24
Peak memory 215476 kb
Host smart-51860795-7b76-4c05-a015-e6d310b8536c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995898483 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1995898483
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1015902180
Short name T95
Test name
Test status
Simulation time 6719908411 ps
CPU time 27.72 seconds
Started May 12 01:19:04 PM PDT 24
Finished May 12 01:19:32 PM PDT 24
Peak memory 211992 kb
Host smart-7ed38ffb-8175-4cb1-b689-cf78073813c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015902180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1015902180
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2743059290
Short name T364
Test name
Test status
Simulation time 33064024695 ps
CPU time 26.67 seconds
Started May 12 01:19:05 PM PDT 24
Finished May 12 01:19:32 PM PDT 24
Peak memory 210740 kb
Host smart-73fe2d6d-9cf4-4935-91a1-a483546b60af
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743059290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2743059290
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3181428857
Short name T382
Test name
Test status
Simulation time 6692327976 ps
CPU time 27.28 seconds
Started May 12 01:19:09 PM PDT 24
Finished May 12 01:19:36 PM PDT 24
Peak memory 210836 kb
Host smart-7597b9cf-33b1-4474-bdd4-4a5e17f3b2bd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181428857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3181428857
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1701823094
Short name T453
Test name
Test status
Simulation time 10493478291 ps
CPU time 80.6 seconds
Started May 12 01:19:05 PM PDT 24
Finished May 12 01:20:26 PM PDT 24
Peak memory 213936 kb
Host smart-d8dd3fb0-8fab-4038-9ca2-8e4cb9dd968e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701823094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1701823094
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1605951870
Short name T378
Test name
Test status
Simulation time 3125097756 ps
CPU time 12.86 seconds
Started May 12 01:19:08 PM PDT 24
Finished May 12 01:19:21 PM PDT 24
Peak memory 210916 kb
Host smart-1b22ba0a-d76a-47d5-b429-6c61dc7c6555
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605951870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1605951870
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3798627588
Short name T412
Test name
Test status
Simulation time 4528841469 ps
CPU time 26.25 seconds
Started May 12 01:19:06 PM PDT 24
Finished May 12 01:19:33 PM PDT 24
Peak memory 218412 kb
Host smart-2e060a3a-abf7-4638-b857-8a9c79309848
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798627588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3798627588
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.4165747292
Short name T443
Test name
Test status
Simulation time 1734466148 ps
CPU time 18.86 seconds
Started May 12 01:19:05 PM PDT 24
Finished May 12 01:19:25 PM PDT 24
Peak memory 216748 kb
Host smart-25e73f5b-1a04-41ee-b5b8-0aa0ea5f4b7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165747292 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.4165747292
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2239503481
Short name T374
Test name
Test status
Simulation time 12515106193 ps
CPU time 25.63 seconds
Started May 12 01:19:06 PM PDT 24
Finished May 12 01:19:33 PM PDT 24
Peak memory 211956 kb
Host smart-4cb6add5-0fbf-4613-95f2-e5c53b89e53c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239503481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2239503481
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.151717485
Short name T395
Test name
Test status
Simulation time 10387006011 ps
CPU time 96.05 seconds
Started May 12 01:19:09 PM PDT 24
Finished May 12 01:20:45 PM PDT 24
Peak memory 213500 kb
Host smart-470093d0-a821-47b9-8236-5f2752940ca9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151717485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.151717485
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3011307381
Short name T386
Test name
Test status
Simulation time 5698971595 ps
CPU time 26.4 seconds
Started May 12 01:19:08 PM PDT 24
Finished May 12 01:19:34 PM PDT 24
Peak memory 212400 kb
Host smart-b91b75e1-9311-426c-963a-4e138abdfa40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011307381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3011307381
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.330892547
Short name T54
Test name
Test status
Simulation time 499142393 ps
CPU time 14.95 seconds
Started May 12 01:19:06 PM PDT 24
Finished May 12 01:19:22 PM PDT 24
Peak memory 219116 kb
Host smart-730c2bdd-d08c-4d35-ba31-9faddf862997
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330892547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.330892547
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2850857390
Short name T111
Test name
Test status
Simulation time 1751536026 ps
CPU time 159.94 seconds
Started May 12 01:19:06 PM PDT 24
Finished May 12 01:21:47 PM PDT 24
Peak memory 213360 kb
Host smart-ca47d86b-53fd-4d09-bbde-4d716a73ec17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850857390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2850857390
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.252982177
Short name T372
Test name
Test status
Simulation time 1737067861 ps
CPU time 8.83 seconds
Started May 12 01:19:13 PM PDT 24
Finished May 12 01:19:22 PM PDT 24
Peak memory 215268 kb
Host smart-fb8ced29-c293-4de1-aed3-fe519aea4b5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252982177 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.252982177
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2950271490
Short name T401
Test name
Test status
Simulation time 6834095982 ps
CPU time 18.55 seconds
Started May 12 01:19:15 PM PDT 24
Finished May 12 01:19:34 PM PDT 24
Peak memory 211464 kb
Host smart-65482849-a5d9-41c2-bfd6-33b509a35a26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950271490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2950271490
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.508621473
Short name T91
Test name
Test status
Simulation time 4485618428 ps
CPU time 55.18 seconds
Started May 12 01:19:11 PM PDT 24
Finished May 12 01:20:07 PM PDT 24
Peak memory 219052 kb
Host smart-987c4ebf-1503-4102-93ab-f703fb741794
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508621473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.508621473
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2926827695
Short name T437
Test name
Test status
Simulation time 6973662753 ps
CPU time 20.26 seconds
Started May 12 01:19:13 PM PDT 24
Finished May 12 01:19:34 PM PDT 24
Peak memory 211908 kb
Host smart-661f2782-c838-435a-88a9-b849e464a293
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926827695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2926827695
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3659626363
Short name T369
Test name
Test status
Simulation time 2810438927 ps
CPU time 19.9 seconds
Started May 12 01:19:12 PM PDT 24
Finished May 12 01:19:32 PM PDT 24
Peak memory 219108 kb
Host smart-93b07b7e-9a49-48f3-b7c8-147e1d3b7399
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659626363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3659626363
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.367287099
Short name T435
Test name
Test status
Simulation time 73460259853 ps
CPU time 102.23 seconds
Started May 12 01:19:14 PM PDT 24
Finished May 12 01:20:57 PM PDT 24
Peak memory 213548 kb
Host smart-34ae3f82-7347-4b83-b9ee-7f95e844aa6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367287099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.367287099
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.922622222
Short name T385
Test name
Test status
Simulation time 3886210298 ps
CPU time 27.66 seconds
Started May 12 01:19:14 PM PDT 24
Finished May 12 01:19:42 PM PDT 24
Peak memory 219188 kb
Host smart-4944dbf8-a960-49bc-a3dd-bf5c8bf7bc17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922622222 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.922622222
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.946427438
Short name T405
Test name
Test status
Simulation time 4182088544 ps
CPU time 30.72 seconds
Started May 12 01:19:14 PM PDT 24
Finished May 12 01:19:45 PM PDT 24
Peak memory 211508 kb
Host smart-b8d6c972-401e-45d3-843d-01db75d0a8c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946427438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.946427438
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.280408204
Short name T445
Test name
Test status
Simulation time 688943139 ps
CPU time 8.05 seconds
Started May 12 01:19:12 PM PDT 24
Finished May 12 01:19:21 PM PDT 24
Peak memory 210980 kb
Host smart-027c8280-8902-4f07-82aa-55c9b187d6ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280408204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.280408204
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1742473653
Short name T440
Test name
Test status
Simulation time 16449577561 ps
CPU time 34.52 seconds
Started May 12 01:19:16 PM PDT 24
Finished May 12 01:19:50 PM PDT 24
Peak memory 217468 kb
Host smart-e40f34b2-5aae-45dc-a9c9-eede239c9c8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742473653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1742473653
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3771032282
Short name T375
Test name
Test status
Simulation time 375935285 ps
CPU time 10.33 seconds
Started May 12 01:19:12 PM PDT 24
Finished May 12 01:19:23 PM PDT 24
Peak memory 215124 kb
Host smart-64f68e98-0d29-48b3-a97a-3bfc12df3bf1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771032282 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3771032282
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3042875634
Short name T427
Test name
Test status
Simulation time 688973659 ps
CPU time 8.07 seconds
Started May 12 01:19:14 PM PDT 24
Finished May 12 01:19:23 PM PDT 24
Peak memory 210804 kb
Host smart-bf095695-6671-4629-8e5a-a47ecab8e381
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042875634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3042875634
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3140166323
Short name T99
Test name
Test status
Simulation time 47043711643 ps
CPU time 179.31 seconds
Started May 12 01:19:11 PM PDT 24
Finished May 12 01:22:11 PM PDT 24
Peak memory 219040 kb
Host smart-7dd87cb0-b4f7-4dd1-b9c0-5072017690b0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140166323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3140166323
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.17522425
Short name T79
Test name
Test status
Simulation time 3379190875 ps
CPU time 26.9 seconds
Started May 12 01:19:13 PM PDT 24
Finished May 12 01:19:41 PM PDT 24
Peak memory 211960 kb
Host smart-b3eeaa46-aa2a-489e-ba8a-63a1123c081b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17522425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctr
l_same_csr_outstanding.17522425
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1816096821
Short name T450
Test name
Test status
Simulation time 20812635395 ps
CPU time 34.48 seconds
Started May 12 01:19:11 PM PDT 24
Finished May 12 01:19:46 PM PDT 24
Peak memory 217292 kb
Host smart-b0d996ec-2ec4-43da-8880-25d322bd8eeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816096821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1816096821
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.431245746
Short name T114
Test name
Test status
Simulation time 5990318192 ps
CPU time 157.29 seconds
Started May 12 01:19:16 PM PDT 24
Finished May 12 01:21:54 PM PDT 24
Peak memory 213888 kb
Host smart-eb297245-e582-4479-8c39-04dfe9bc1479
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431245746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.431245746
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3152481656
Short name T371
Test name
Test status
Simulation time 20718827592 ps
CPU time 30.88 seconds
Started May 12 01:19:17 PM PDT 24
Finished May 12 01:19:49 PM PDT 24
Peak memory 219388 kb
Host smart-6a1e449b-568b-4ff8-be41-f5a8fdb853a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152481656 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3152481656
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4076079973
Short name T397
Test name
Test status
Simulation time 601681720 ps
CPU time 11.92 seconds
Started May 12 01:19:15 PM PDT 24
Finished May 12 01:19:27 PM PDT 24
Peak memory 210816 kb
Host smart-a0a87ffc-9696-42d2-91e7-1f9e2ae4029b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076079973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.4076079973
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1393855846
Short name T66
Test name
Test status
Simulation time 44393223049 ps
CPU time 91.38 seconds
Started May 12 01:19:16 PM PDT 24
Finished May 12 01:20:48 PM PDT 24
Peak memory 219092 kb
Host smart-0b0092e0-662f-46ba-a287-3ab5f0558383
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393855846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1393855846
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2060365829
Short name T379
Test name
Test status
Simulation time 3758645672 ps
CPU time 19.12 seconds
Started May 12 01:19:17 PM PDT 24
Finished May 12 01:19:36 PM PDT 24
Peak memory 211812 kb
Host smart-b8fec59f-7635-4961-98d9-43f8ada8f732
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060365829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2060365829
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1363451846
Short name T392
Test name
Test status
Simulation time 10898285337 ps
CPU time 29.39 seconds
Started May 12 01:19:11 PM PDT 24
Finished May 12 01:19:41 PM PDT 24
Peak memory 217420 kb
Host smart-e48210c3-6dc3-4aba-88c2-fc566b67bf0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363451846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1363451846
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.8694763
Short name T113
Test name
Test status
Simulation time 4262405732 ps
CPU time 101.58 seconds
Started May 12 01:19:15 PM PDT 24
Finished May 12 01:20:57 PM PDT 24
Peak memory 213184 kb
Host smart-b10bacb8-d0fd-4823-970c-3200f5b8cff0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8694763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg_
err.8694763
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.4258109391
Short name T263
Test name
Test status
Simulation time 1026963213 ps
CPU time 11.77 seconds
Started May 12 01:19:27 PM PDT 24
Finished May 12 01:19:39 PM PDT 24
Peak memory 211772 kb
Host smart-be93fdd6-6787-46b3-8382-f7002bcc4ec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258109391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.4258109391
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2879863554
Short name T48
Test name
Test status
Simulation time 27201415497 ps
CPU time 446.4 seconds
Started May 12 01:19:22 PM PDT 24
Finished May 12 01:26:49 PM PDT 24
Peak memory 226140 kb
Host smart-f9053bd7-6329-4d54-8b3f-149909f6e75f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879863554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2879863554
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1901987347
Short name T226
Test name
Test status
Simulation time 853416493 ps
CPU time 25.26 seconds
Started May 12 01:19:24 PM PDT 24
Finished May 12 01:19:50 PM PDT 24
Peak memory 215280 kb
Host smart-2ff6ebd5-085d-46aa-bfb3-7a1762414e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901987347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1901987347
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1739878455
Short name T45
Test name
Test status
Simulation time 14763033189 ps
CPU time 31.89 seconds
Started May 12 01:19:28 PM PDT 24
Finished May 12 01:20:00 PM PDT 24
Peak memory 212200 kb
Host smart-60275b8c-05c0-4d8f-9374-565482501f88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1739878455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1739878455
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1858915646
Short name T347
Test name
Test status
Simulation time 1358518461 ps
CPU time 19.53 seconds
Started May 12 01:19:28 PM PDT 24
Finished May 12 01:19:48 PM PDT 24
Peak memory 217456 kb
Host smart-89437bc2-bb2b-4c38-92ad-a39111a5059c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858915646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1858915646
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.793723966
Short name T193
Test name
Test status
Simulation time 24534493757 ps
CPU time 142.5 seconds
Started May 12 01:19:23 PM PDT 24
Finished May 12 01:21:46 PM PDT 24
Peak memory 222796 kb
Host smart-dadb29ce-aab1-4b25-9d85-c66146a978b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793723966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.793723966
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.836120223
Short name T56
Test name
Test status
Simulation time 15371391530 ps
CPU time 30.74 seconds
Started May 12 01:19:33 PM PDT 24
Finished May 12 01:20:05 PM PDT 24
Peak memory 212712 kb
Host smart-7cdc0198-771d-4fc8-bd18-f6052197edc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836120223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.836120223
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3531924456
Short name T158
Test name
Test status
Simulation time 4256882833 ps
CPU time 33.12 seconds
Started May 12 01:19:32 PM PDT 24
Finished May 12 01:20:06 PM PDT 24
Peak memory 214380 kb
Host smart-6221105f-49aa-4922-b07f-f79117a284ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531924456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3531924456
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.4074821969
Short name T276
Test name
Test status
Simulation time 9170082938 ps
CPU time 24.06 seconds
Started May 12 01:19:28 PM PDT 24
Finished May 12 01:19:53 PM PDT 24
Peak memory 211980 kb
Host smart-6ac965bf-9721-4928-8f94-99499b86db21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4074821969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.4074821969
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2285283196
Short name T33
Test name
Test status
Simulation time 13215699597 ps
CPU time 245.61 seconds
Started May 12 01:19:27 PM PDT 24
Finished May 12 01:23:34 PM PDT 24
Peak memory 238860 kb
Host smart-f7616396-0063-45f7-9aa0-2afc60c5f371
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285283196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2285283196
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2985449574
Short name T231
Test name
Test status
Simulation time 5302462883 ps
CPU time 52.53 seconds
Started May 12 01:19:31 PM PDT 24
Finished May 12 01:20:25 PM PDT 24
Peak memory 218012 kb
Host smart-41a45829-0299-4118-b1a3-89e7d322db92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985449574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2985449574
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1483557459
Short name T137
Test name
Test status
Simulation time 6444351348 ps
CPU time 53.21 seconds
Started May 12 01:19:28 PM PDT 24
Finished May 12 01:20:22 PM PDT 24
Peak memory 219756 kb
Host smart-6f1edc12-209f-425d-a88f-d8c229e1cab9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483557459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1483557459
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2142817936
Short name T71
Test name
Test status
Simulation time 4102589788 ps
CPU time 32.93 seconds
Started May 12 01:19:36 PM PDT 24
Finished May 12 01:20:10 PM PDT 24
Peak memory 212408 kb
Host smart-52069d3f-b811-4c9d-9206-301acd6bca3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142817936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2142817936
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.4259426766
Short name T317
Test name
Test status
Simulation time 1030199405 ps
CPU time 22.65 seconds
Started May 12 01:19:39 PM PDT 24
Finished May 12 01:20:02 PM PDT 24
Peak memory 215132 kb
Host smart-38ffd83d-a462-4571-b318-ae8c8a03acc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259426766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.4259426766
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1826839009
Short name T181
Test name
Test status
Simulation time 7517603979 ps
CPU time 30.41 seconds
Started May 12 01:19:38 PM PDT 24
Finished May 12 01:20:08 PM PDT 24
Peak memory 213044 kb
Host smart-6bb19770-7a92-4a1c-a43f-d901588a2c82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1826839009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1826839009
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.976141899
Short name T172
Test name
Test status
Simulation time 1384344071 ps
CPU time 28.37 seconds
Started May 12 01:19:41 PM PDT 24
Finished May 12 01:20:10 PM PDT 24
Peak memory 215324 kb
Host smart-0d624a55-e064-4a97-b7fb-878664239351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976141899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.976141899
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.761406388
Short name T197
Test name
Test status
Simulation time 27822492949 ps
CPU time 133.21 seconds
Started May 12 01:19:36 PM PDT 24
Finished May 12 01:21:50 PM PDT 24
Peak memory 220196 kb
Host smart-4757fc56-27aa-4b93-a8a7-324595499596
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761406388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.761406388
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.106000949
Short name T42
Test name
Test status
Simulation time 15043252205 ps
CPU time 14.44 seconds
Started May 12 01:19:42 PM PDT 24
Finished May 12 01:19:57 PM PDT 24
Peak memory 211944 kb
Host smart-08ac350f-3063-41e6-ac2d-8a58a319f7b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106000949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.106000949
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1960679892
Short name T122
Test name
Test status
Simulation time 84216308420 ps
CPU time 490.18 seconds
Started May 12 01:19:35 PM PDT 24
Finished May 12 01:27:46 PM PDT 24
Peak memory 240340 kb
Host smart-4cb10ed9-dd37-49b5-85d0-e2a20eb378a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960679892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1960679892
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2869070947
Short name T198
Test name
Test status
Simulation time 18241315216 ps
CPU time 34.92 seconds
Started May 12 01:19:37 PM PDT 24
Finished May 12 01:20:13 PM PDT 24
Peak memory 212368 kb
Host smart-45ee4cc6-f50d-47f8-8179-3c4171f0c315
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2869070947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2869070947
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.309040880
Short name T286
Test name
Test status
Simulation time 6303831614 ps
CPU time 56.25 seconds
Started May 12 01:19:39 PM PDT 24
Finished May 12 01:20:36 PM PDT 24
Peak memory 218548 kb
Host smart-3d7130cf-edd7-461e-86b4-3b4711f8f05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309040880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.309040880
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1259923644
Short name T183
Test name
Test status
Simulation time 10041349754 ps
CPU time 46.55 seconds
Started May 12 01:19:35 PM PDT 24
Finished May 12 01:20:22 PM PDT 24
Peak memory 215244 kb
Host smart-9761961c-bbcc-4b90-acf5-670f757472ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259923644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1259923644
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.16036144
Short name T354
Test name
Test status
Simulation time 1883558886 ps
CPU time 19.61 seconds
Started May 12 01:19:47 PM PDT 24
Finished May 12 01:20:07 PM PDT 24
Peak memory 212280 kb
Host smart-4cb7e858-9c75-4947-ae1d-6e215d3b780b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16036144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.16036144
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2206679888
Short name T180
Test name
Test status
Simulation time 3192478357 ps
CPU time 28.64 seconds
Started May 12 01:19:42 PM PDT 24
Finished May 12 01:20:11 PM PDT 24
Peak memory 212728 kb
Host smart-400a36e3-9cdc-451b-a2e0-71eacb671384
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2206679888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2206679888
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3442158767
Short name T269
Test name
Test status
Simulation time 26188240577 ps
CPU time 67.59 seconds
Started May 12 01:19:42 PM PDT 24
Finished May 12 01:20:50 PM PDT 24
Peak memory 218144 kb
Host smart-570b26fa-1674-4516-8bf5-03e2a920a9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442158767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3442158767
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3069730000
Short name T340
Test name
Test status
Simulation time 2635498305 ps
CPU time 44.31 seconds
Started May 12 01:19:43 PM PDT 24
Finished May 12 01:20:27 PM PDT 24
Peak memory 219956 kb
Host smart-af4d7d3e-8ce3-48f2-8985-31c79575b3b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069730000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3069730000
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3722295825
Short name T153
Test name
Test status
Simulation time 3789208486 ps
CPU time 30.39 seconds
Started May 12 01:19:51 PM PDT 24
Finished May 12 01:20:22 PM PDT 24
Peak memory 212440 kb
Host smart-8ac36ab7-e709-4503-a8ca-af599fad5616
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722295825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3722295825
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.90983740
Short name T266
Test name
Test status
Simulation time 10717729671 ps
CPU time 322.21 seconds
Started May 12 01:19:47 PM PDT 24
Finished May 12 01:25:09 PM PDT 24
Peak memory 235120 kb
Host smart-456375e3-dca4-4a91-afa4-618eb3f984ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90983740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_co
rrupt_sig_fatal_chk.90983740
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2481582958
Short name T146
Test name
Test status
Simulation time 2529492936 ps
CPU time 24.02 seconds
Started May 12 01:19:51 PM PDT 24
Finished May 12 01:20:16 PM PDT 24
Peak memory 215268 kb
Host smart-171a4ab5-bc74-488d-9d3d-f1eca0aa48f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481582958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2481582958
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2350163268
Short name T314
Test name
Test status
Simulation time 177424379 ps
CPU time 10.37 seconds
Started May 12 01:19:47 PM PDT 24
Finished May 12 01:19:58 PM PDT 24
Peak memory 212604 kb
Host smart-8ec7015e-8341-45da-886e-e8a28b22d193
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2350163268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2350163268
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1204957713
Short name T15
Test name
Test status
Simulation time 12964026071 ps
CPU time 76.34 seconds
Started May 12 01:19:47 PM PDT 24
Finished May 12 01:21:03 PM PDT 24
Peak memory 218448 kb
Host smart-94d1c11a-7050-4cde-b13c-67a729f40839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204957713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1204957713
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.801152283
Short name T332
Test name
Test status
Simulation time 1499568429 ps
CPU time 27.89 seconds
Started May 12 01:19:45 PM PDT 24
Finished May 12 01:20:14 PM PDT 24
Peak memory 216320 kb
Host smart-42cbc2a8-fd51-4234-b65d-1ec4ccc3accd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801152283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.801152283
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1581563301
Short name T334
Test name
Test status
Simulation time 832659084 ps
CPU time 14.33 seconds
Started May 12 01:19:57 PM PDT 24
Finished May 12 01:20:12 PM PDT 24
Peak memory 212040 kb
Host smart-eb09f5b2-beb0-427a-8b92-9ce8af433ede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581563301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1581563301
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.86784171
Short name T178
Test name
Test status
Simulation time 2230711369 ps
CPU time 185.23 seconds
Started May 12 01:19:53 PM PDT 24
Finished May 12 01:22:59 PM PDT 24
Peak memory 238372 kb
Host smart-d1e3ef9c-c168-48c5-a283-0c90ce38179d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86784171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_co
rrupt_sig_fatal_chk.86784171
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.261121082
Short name T306
Test name
Test status
Simulation time 5879911775 ps
CPU time 29.52 seconds
Started May 12 01:19:51 PM PDT 24
Finished May 12 01:20:21 PM PDT 24
Peak memory 216276 kb
Host smart-d335961c-d4ec-4307-bb70-29635ccc213b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261121082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.261121082
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.285221279
Short name T8
Test name
Test status
Simulation time 5500326305 ps
CPU time 18.54 seconds
Started May 12 01:19:52 PM PDT 24
Finished May 12 01:20:11 PM PDT 24
Peak memory 212352 kb
Host smart-98fe88f5-644e-46f5-a352-44601ea065fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=285221279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.285221279
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1241315679
Short name T187
Test name
Test status
Simulation time 8592298003 ps
CPU time 37.39 seconds
Started May 12 01:19:52 PM PDT 24
Finished May 12 01:20:30 PM PDT 24
Peak memory 217220 kb
Host smart-5ad622ac-bc27-4195-aea2-6d930a9f9107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241315679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1241315679
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.565049387
Short name T247
Test name
Test status
Simulation time 1979198953 ps
CPU time 37.61 seconds
Started May 12 01:19:53 PM PDT 24
Finished May 12 01:20:31 PM PDT 24
Peak memory 216500 kb
Host smart-6e807d10-f71c-4b1b-afbc-9f86d34e06f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565049387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.565049387
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1540119631
Short name T69
Test name
Test status
Simulation time 2282278812 ps
CPU time 21.34 seconds
Started May 12 01:19:56 PM PDT 24
Finished May 12 01:20:18 PM PDT 24
Peak memory 211940 kb
Host smart-a04734a7-b16b-4b07-9e0d-7017470c3722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540119631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1540119631
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1324795352
Short name T265
Test name
Test status
Simulation time 339250319658 ps
CPU time 837.21 seconds
Started May 12 01:19:55 PM PDT 24
Finished May 12 01:33:53 PM PDT 24
Peak memory 226424 kb
Host smart-8a8608ae-71f6-4b6a-8946-983464f8f109
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324795352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1324795352
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1107262603
Short name T297
Test name
Test status
Simulation time 15755793263 ps
CPU time 64.92 seconds
Started May 12 01:19:55 PM PDT 24
Finished May 12 01:21:01 PM PDT 24
Peak memory 215564 kb
Host smart-2b29a174-ba66-4cdd-b6bc-5763f5db02e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107262603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1107262603
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.4131344095
Short name T318
Test name
Test status
Simulation time 10968581791 ps
CPU time 23.75 seconds
Started May 12 01:19:55 PM PDT 24
Finished May 12 01:20:20 PM PDT 24
Peak memory 211816 kb
Host smart-bd15b1d2-dc12-4a23-a0f9-04f6629a30eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4131344095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.4131344095
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3892729458
Short name T87
Test name
Test status
Simulation time 53689665126 ps
CPU time 64.63 seconds
Started May 12 01:19:55 PM PDT 24
Finished May 12 01:21:00 PM PDT 24
Peak memory 218824 kb
Host smart-ded2def8-7f6e-4e87-9d07-c7ce1c7569c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892729458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3892729458
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.238417584
Short name T304
Test name
Test status
Simulation time 80312357990 ps
CPU time 183.33 seconds
Started May 12 01:19:56 PM PDT 24
Finished May 12 01:23:00 PM PDT 24
Peak memory 220520 kb
Host smart-e4ee3f9b-a570-4521-ab38-09693b7c8a94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238417584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.238417584
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1828257890
Short name T252
Test name
Test status
Simulation time 345704242 ps
CPU time 8.35 seconds
Started May 12 01:20:03 PM PDT 24
Finished May 12 01:20:12 PM PDT 24
Peak memory 211772 kb
Host smart-58812b0c-cf6f-4a37-8f2e-cd6c4d6cd7eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828257890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1828257890
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2495796629
Short name T308
Test name
Test status
Simulation time 157962408872 ps
CPU time 427.03 seconds
Started May 12 01:19:56 PM PDT 24
Finished May 12 01:27:04 PM PDT 24
Peak memory 230112 kb
Host smart-b1812f32-2159-4e8d-9fc9-4999f7b8235d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495796629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2495796629
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.641789285
Short name T192
Test name
Test status
Simulation time 34168055165 ps
CPU time 70.34 seconds
Started May 12 01:19:58 PM PDT 24
Finished May 12 01:21:08 PM PDT 24
Peak memory 215628 kb
Host smart-5b4c54e2-3762-438b-b5fa-662ca216b8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641789285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.641789285
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.491048192
Short name T125
Test name
Test status
Simulation time 6760974586 ps
CPU time 28.15 seconds
Started May 12 01:19:58 PM PDT 24
Finished May 12 01:20:26 PM PDT 24
Peak memory 212440 kb
Host smart-f85be3fa-a5ae-425f-8f8f-414d22be3076
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=491048192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.491048192
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3409445996
Short name T145
Test name
Test status
Simulation time 12460496539 ps
CPU time 63.23 seconds
Started May 12 01:19:55 PM PDT 24
Finished May 12 01:20:59 PM PDT 24
Peak memory 218680 kb
Host smart-377a7076-690f-4379-afa2-21bc4d977dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409445996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3409445996
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3445851523
Short name T166
Test name
Test status
Simulation time 65616740068 ps
CPU time 71.07 seconds
Started May 12 01:19:55 PM PDT 24
Finished May 12 01:21:07 PM PDT 24
Peak memory 218560 kb
Host smart-b00d492a-4172-41e1-9940-a5edfdb70aba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445851523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3445851523
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2985876537
Short name T305
Test name
Test status
Simulation time 8611543499 ps
CPU time 29.96 seconds
Started May 12 01:20:01 PM PDT 24
Finished May 12 01:20:32 PM PDT 24
Peak memory 212664 kb
Host smart-acc1842b-b8e8-43dd-9f6c-a87e11c7d72e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985876537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2985876537
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2574636474
Short name T352
Test name
Test status
Simulation time 19306284034 ps
CPU time 355.91 seconds
Started May 12 01:20:04 PM PDT 24
Finished May 12 01:26:00 PM PDT 24
Peak memory 239212 kb
Host smart-d0af1b65-e2f2-4f42-8c0d-ed59478de9ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574636474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2574636474
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1544802231
Short name T353
Test name
Test status
Simulation time 39998132726 ps
CPU time 66.17 seconds
Started May 12 01:20:02 PM PDT 24
Finished May 12 01:21:08 PM PDT 24
Peak memory 215668 kb
Host smart-dba37135-b516-4216-87bb-6c30b4b1245e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544802231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1544802231
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3172702894
Short name T210
Test name
Test status
Simulation time 17182210043 ps
CPU time 24.21 seconds
Started May 12 01:20:01 PM PDT 24
Finished May 12 01:20:26 PM PDT 24
Peak memory 211796 kb
Host smart-dac39a1d-b20d-418d-bbb4-2dea976a0414
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3172702894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3172702894
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2567080759
Short name T272
Test name
Test status
Simulation time 1561990385 ps
CPU time 19.3 seconds
Started May 12 01:20:03 PM PDT 24
Finished May 12 01:20:23 PM PDT 24
Peak memory 216916 kb
Host smart-2dc9cc87-f7b0-4164-9910-472f0ceb0a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567080759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2567080759
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3823369731
Short name T36
Test name
Test status
Simulation time 431438450 ps
CPU time 11.13 seconds
Started May 12 01:20:08 PM PDT 24
Finished May 12 01:20:20 PM PDT 24
Peak memory 211836 kb
Host smart-dd7ffaff-fbae-4aa5-b8b8-16a80289e0ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823369731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3823369731
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.579956787
Short name T136
Test name
Test status
Simulation time 17044316590 ps
CPU time 67.03 seconds
Started May 12 01:20:02 PM PDT 24
Finished May 12 01:21:10 PM PDT 24
Peak memory 215752 kb
Host smart-def606dd-afa5-457c-9fdb-107d0cb275f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579956787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.579956787
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.243393164
Short name T246
Test name
Test status
Simulation time 357981877 ps
CPU time 10.58 seconds
Started May 12 01:20:03 PM PDT 24
Finished May 12 01:20:14 PM PDT 24
Peak memory 212032 kb
Host smart-2cb519b1-5b6b-4a77-9f1f-0575322abc3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=243393164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.243393164
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1973553837
Short name T124
Test name
Test status
Simulation time 28203730591 ps
CPU time 63.37 seconds
Started May 12 01:20:06 PM PDT 24
Finished May 12 01:21:10 PM PDT 24
Peak memory 218576 kb
Host smart-d8f6e78f-f22d-42ab-a0e2-bc877a1925c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973553837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1973553837
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.921783261
Short name T294
Test name
Test status
Simulation time 995011524 ps
CPU time 18.88 seconds
Started May 12 01:20:06 PM PDT 24
Finished May 12 01:20:25 PM PDT 24
Peak memory 214356 kb
Host smart-3f12a670-19f6-4e8b-b471-c13536086f65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921783261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.921783261
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1307982577
Short name T43
Test name
Test status
Simulation time 174317240 ps
CPU time 8.3 seconds
Started May 12 01:20:10 PM PDT 24
Finished May 12 01:20:18 PM PDT 24
Peak memory 211700 kb
Host smart-3f34f7cc-f138-4104-990e-4874814464d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307982577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1307982577
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.146610808
Short name T2
Test name
Test status
Simulation time 7831348537 ps
CPU time 149.08 seconds
Started May 12 01:20:07 PM PDT 24
Finished May 12 01:22:37 PM PDT 24
Peak memory 225132 kb
Host smart-04a7795d-fdb2-4288-9e16-c06d10ff4b52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146610808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.146610808
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2580364376
Short name T312
Test name
Test status
Simulation time 987583936 ps
CPU time 25.76 seconds
Started May 12 01:20:09 PM PDT 24
Finished May 12 01:20:35 PM PDT 24
Peak memory 215156 kb
Host smart-1ea72b2a-cf8c-4968-b1f9-c97e77bcd27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580364376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2580364376
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2775348087
Short name T16
Test name
Test status
Simulation time 802980282 ps
CPU time 15.66 seconds
Started May 12 01:20:06 PM PDT 24
Finished May 12 01:20:22 PM PDT 24
Peak memory 212680 kb
Host smart-7fb8a77e-0970-4a9c-bdff-4e6500858919
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2775348087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2775348087
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3788658038
Short name T267
Test name
Test status
Simulation time 22408688326 ps
CPU time 88.68 seconds
Started May 12 01:20:07 PM PDT 24
Finished May 12 01:21:36 PM PDT 24
Peak memory 220516 kb
Host smart-9fa76c4e-9264-4728-aa59-1d4568074858
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788658038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3788658038
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3200044871
Short name T235
Test name
Test status
Simulation time 13468347136 ps
CPU time 20.41 seconds
Started May 12 01:19:27 PM PDT 24
Finished May 12 01:19:48 PM PDT 24
Peak memory 211912 kb
Host smart-c8733cd0-a410-4461-ad36-91190750f3e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200044871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3200044871
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3841986005
Short name T32
Test name
Test status
Simulation time 67580664806 ps
CPU time 285.89 seconds
Started May 12 01:19:26 PM PDT 24
Finished May 12 01:24:13 PM PDT 24
Peak memory 234180 kb
Host smart-269015f6-61bd-47d7-8292-28d004053281
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841986005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3841986005
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3803204528
Short name T201
Test name
Test status
Simulation time 512474115 ps
CPU time 22.71 seconds
Started May 12 01:19:26 PM PDT 24
Finished May 12 01:19:49 PM PDT 24
Peak memory 215224 kb
Host smart-c792c12b-4996-4633-b589-0ad287d13c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803204528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3803204528
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.4265395455
Short name T147
Test name
Test status
Simulation time 20109860493 ps
CPU time 23.68 seconds
Started May 12 01:19:30 PM PDT 24
Finished May 12 01:19:54 PM PDT 24
Peak memory 211880 kb
Host smart-3513168f-3081-41b8-88ab-b3a2576c8d89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4265395455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.4265395455
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.204968524
Short name T39
Test name
Test status
Simulation time 1703230053 ps
CPU time 118.58 seconds
Started May 12 01:19:26 PM PDT 24
Finished May 12 01:21:26 PM PDT 24
Peak memory 237820 kb
Host smart-b5b52aca-8aa5-41a5-aa2a-b056d7631ce1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204968524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.204968524
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.645622841
Short name T250
Test name
Test status
Simulation time 1045105618 ps
CPU time 27.36 seconds
Started May 12 01:19:27 PM PDT 24
Finished May 12 01:19:55 PM PDT 24
Peak memory 216932 kb
Host smart-a5e3af53-baf3-475c-8bfa-af125b0b323e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645622841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.645622841
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2127181040
Short name T339
Test name
Test status
Simulation time 2269768136 ps
CPU time 33.33 seconds
Started May 12 01:19:27 PM PDT 24
Finished May 12 01:20:01 PM PDT 24
Peak memory 219952 kb
Host smart-02c3ef0c-9a3e-4ae5-9bc8-4b8d6741cabb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127181040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2127181040
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.399822082
Short name T68
Test name
Test status
Simulation time 3843430992 ps
CPU time 30.42 seconds
Started May 12 01:20:09 PM PDT 24
Finished May 12 01:20:40 PM PDT 24
Peak memory 212316 kb
Host smart-1d919aac-fe2f-4b2e-8f85-cc8ac6418e2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399822082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.399822082
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1158859737
Short name T298
Test name
Test status
Simulation time 5388230118 ps
CPU time 353.5 seconds
Started May 12 01:20:06 PM PDT 24
Finished May 12 01:25:59 PM PDT 24
Peak memory 234520 kb
Host smart-0268e1e7-c3c9-4842-ba17-fc57683ae23e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158859737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1158859737
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1714115299
Short name T213
Test name
Test status
Simulation time 7546265395 ps
CPU time 43.3 seconds
Started May 12 01:20:07 PM PDT 24
Finished May 12 01:20:51 PM PDT 24
Peak memory 215928 kb
Host smart-b7138210-a1da-420e-9773-0fa9c9cb5e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714115299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1714115299
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3539896683
Short name T155
Test name
Test status
Simulation time 363212324 ps
CPU time 10.63 seconds
Started May 12 01:20:07 PM PDT 24
Finished May 12 01:20:18 PM PDT 24
Peak memory 212100 kb
Host smart-fed5fd6d-b45f-4c5c-a480-a990fda53b53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3539896683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3539896683
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.472135562
Short name T12
Test name
Test status
Simulation time 26604630528 ps
CPU time 55.75 seconds
Started May 12 01:20:05 PM PDT 24
Finished May 12 01:21:02 PM PDT 24
Peak memory 217828 kb
Host smart-59034243-b684-4f04-8836-cabf9a73d25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472135562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.472135562
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.315646429
Short name T75
Test name
Test status
Simulation time 21367361391 ps
CPU time 176.13 seconds
Started May 12 01:20:06 PM PDT 24
Finished May 12 01:23:02 PM PDT 24
Peak memory 221212 kb
Host smart-5a235aba-71b0-4cac-9fb3-ca56c8d97e39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315646429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.315646429
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3240497133
Short name T131
Test name
Test status
Simulation time 3567182285 ps
CPU time 28.27 seconds
Started May 12 01:20:07 PM PDT 24
Finished May 12 01:20:35 PM PDT 24
Peak memory 212448 kb
Host smart-a4a61ea5-c8ba-48c7-92b2-a5fdc006b900
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240497133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3240497133
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2558879074
Short name T295
Test name
Test status
Simulation time 35049518568 ps
CPU time 218.01 seconds
Started May 12 01:20:07 PM PDT 24
Finished May 12 01:23:45 PM PDT 24
Peak memory 225152 kb
Host smart-6ce39f7b-2283-4d12-a212-5c6e213ab778
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558879074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2558879074
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2743567343
Short name T216
Test name
Test status
Simulation time 104133075104 ps
CPU time 55.52 seconds
Started May 12 01:20:06 PM PDT 24
Finished May 12 01:21:02 PM PDT 24
Peak memory 215576 kb
Host smart-28f7bc80-f27b-463e-8189-e50acf1234d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743567343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2743567343
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1665435135
Short name T169
Test name
Test status
Simulation time 728197660 ps
CPU time 10.24 seconds
Started May 12 01:20:07 PM PDT 24
Finished May 12 01:20:18 PM PDT 24
Peak memory 212980 kb
Host smart-63e13b84-0064-48d4-aec3-2e27f4be8e9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1665435135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1665435135
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2511028302
Short name T287
Test name
Test status
Simulation time 4122525234 ps
CPU time 32.67 seconds
Started May 12 01:20:06 PM PDT 24
Finished May 12 01:20:39 PM PDT 24
Peak memory 214292 kb
Host smart-5893d29d-16c2-4772-826b-12efe8f6c63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511028302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2511028302
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1338536026
Short name T11
Test name
Test status
Simulation time 23647474972 ps
CPU time 107.05 seconds
Started May 12 01:20:07 PM PDT 24
Finished May 12 01:21:55 PM PDT 24
Peak memory 219900 kb
Host smart-6def64d0-a6b4-480c-ab05-e940a0200a61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338536026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1338536026
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2564616404
Short name T268
Test name
Test status
Simulation time 10926256802 ps
CPU time 25.09 seconds
Started May 12 01:20:11 PM PDT 24
Finished May 12 01:20:37 PM PDT 24
Peak memory 211824 kb
Host smart-8cdb32b4-846f-40cf-9682-54e52cec8949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564616404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2564616404
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1938226315
Short name T239
Test name
Test status
Simulation time 22239039472 ps
CPU time 161.37 seconds
Started May 12 01:20:05 PM PDT 24
Finished May 12 01:22:47 PM PDT 24
Peak memory 216372 kb
Host smart-b9938b5a-a271-4ff7-8dad-44e370308b2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938226315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1938226315
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4007613139
Short name T220
Test name
Test status
Simulation time 1837350965 ps
CPU time 19.03 seconds
Started May 12 01:20:10 PM PDT 24
Finished May 12 01:20:30 PM PDT 24
Peak memory 214932 kb
Host smart-c275241b-cd95-4a89-9cd1-5008bf1cedb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007613139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4007613139
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1122193809
Short name T345
Test name
Test status
Simulation time 366594336 ps
CPU time 9.97 seconds
Started May 12 01:20:06 PM PDT 24
Finished May 12 01:20:17 PM PDT 24
Peak memory 212996 kb
Host smart-f057a1e5-47e6-465a-99b1-9e11a6958473
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1122193809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1122193809
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.988964969
Short name T256
Test name
Test status
Simulation time 14653623564 ps
CPU time 71.72 seconds
Started May 12 01:20:07 PM PDT 24
Finished May 12 01:21:19 PM PDT 24
Peak memory 218048 kb
Host smart-56419ec6-a3af-42e7-a385-8a2c20d6c196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988964969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.988964969
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3326840583
Short name T168
Test name
Test status
Simulation time 25579413772 ps
CPU time 59 seconds
Started May 12 01:20:05 PM PDT 24
Finished May 12 01:21:05 PM PDT 24
Peak memory 218876 kb
Host smart-aa57f694-162b-4442-b4df-e02797a7efe8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326840583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3326840583
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.885531077
Short name T196
Test name
Test status
Simulation time 2844712805 ps
CPU time 17.51 seconds
Started May 12 01:20:12 PM PDT 24
Finished May 12 01:20:29 PM PDT 24
Peak memory 212324 kb
Host smart-c23709ef-a8a7-420d-934d-3d5110f73f60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885531077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.885531077
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.685553192
Short name T167
Test name
Test status
Simulation time 45496475949 ps
CPU time 503.76 seconds
Started May 12 01:20:11 PM PDT 24
Finished May 12 01:28:35 PM PDT 24
Peak memory 227700 kb
Host smart-87280e82-c603-4b00-bd0f-f9e72c98ecca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685553192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.685553192
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3203230472
Short name T335
Test name
Test status
Simulation time 674802475 ps
CPU time 18.97 seconds
Started May 12 01:20:10 PM PDT 24
Finished May 12 01:20:30 PM PDT 24
Peak memory 215204 kb
Host smart-a13eb467-916a-4450-b184-56f74690ddb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203230472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3203230472
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2746296180
Short name T202
Test name
Test status
Simulation time 182813403 ps
CPU time 10.44 seconds
Started May 12 01:20:09 PM PDT 24
Finished May 12 01:20:20 PM PDT 24
Peak memory 212640 kb
Host smart-10f2c5b2-11c0-40d9-ab2c-854fae9d33af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2746296180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2746296180
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3056431054
Short name T207
Test name
Test status
Simulation time 7601085275 ps
CPU time 72.61 seconds
Started May 12 01:20:13 PM PDT 24
Finished May 12 01:21:26 PM PDT 24
Peak memory 216004 kb
Host smart-05a841d0-4241-4406-aee7-7f73c342902a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056431054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3056431054
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3395062625
Short name T301
Test name
Test status
Simulation time 9285858455 ps
CPU time 56.9 seconds
Started May 12 01:20:12 PM PDT 24
Finished May 12 01:21:09 PM PDT 24
Peak memory 218308 kb
Host smart-3568ce82-c781-45f1-b248-d54eb682c56e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395062625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3395062625
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2099909190
Short name T143
Test name
Test status
Simulation time 167308691 ps
CPU time 8.41 seconds
Started May 12 01:20:12 PM PDT 24
Finished May 12 01:20:21 PM PDT 24
Peak memory 211772 kb
Host smart-cf2d1b82-2a74-4753-9ca9-6cc71607fa1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099909190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2099909190
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3934374153
Short name T30
Test name
Test status
Simulation time 5301880413 ps
CPU time 232.7 seconds
Started May 12 01:20:13 PM PDT 24
Finished May 12 01:24:06 PM PDT 24
Peak memory 218844 kb
Host smart-85f4466d-8090-47ac-92c9-d7c634267ff4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934374153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3934374153
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2869438695
Short name T28
Test name
Test status
Simulation time 2745522592 ps
CPU time 23.5 seconds
Started May 12 01:20:13 PM PDT 24
Finished May 12 01:20:37 PM PDT 24
Peak memory 215428 kb
Host smart-81941c19-d208-4d9d-92c8-9870e006546a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869438695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2869438695
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.105378212
Short name T346
Test name
Test status
Simulation time 1589445961 ps
CPU time 10.5 seconds
Started May 12 01:20:09 PM PDT 24
Finished May 12 01:20:20 PM PDT 24
Peak memory 213168 kb
Host smart-f774e487-180c-4f26-a2a5-59d8c4f15baa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=105378212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.105378212
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1603564868
Short name T219
Test name
Test status
Simulation time 42137688599 ps
CPU time 83.7 seconds
Started May 12 01:20:13 PM PDT 24
Finished May 12 01:21:37 PM PDT 24
Peak memory 217092 kb
Host smart-64733884-3342-4174-be1a-91b431aa1b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603564868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1603564868
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3868003998
Short name T257
Test name
Test status
Simulation time 14232880511 ps
CPU time 122.13 seconds
Started May 12 01:20:12 PM PDT 24
Finished May 12 01:22:15 PM PDT 24
Peak memory 219880 kb
Host smart-18522e9d-0039-4ce4-a9a3-d8af63856818
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868003998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3868003998
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.4048638402
Short name T311
Test name
Test status
Simulation time 4031712131 ps
CPU time 20.5 seconds
Started May 12 01:20:17 PM PDT 24
Finished May 12 01:20:38 PM PDT 24
Peak memory 212348 kb
Host smart-a3cbef5e-6406-4391-8ec2-8fb7dd1b2517
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048638402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.4048638402
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3856359106
Short name T140
Test name
Test status
Simulation time 21904160986 ps
CPU time 52.17 seconds
Started May 12 01:20:16 PM PDT 24
Finished May 12 01:21:08 PM PDT 24
Peak memory 214528 kb
Host smart-2f15348f-cdbc-4092-b568-360456609b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856359106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3856359106
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2554383651
Short name T344
Test name
Test status
Simulation time 24726480855 ps
CPU time 31.43 seconds
Started May 12 01:20:10 PM PDT 24
Finished May 12 01:20:42 PM PDT 24
Peak memory 213444 kb
Host smart-1e95792a-429b-443a-9b91-cdb5dfc2fa74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2554383651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2554383651
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2109524812
Short name T278
Test name
Test status
Simulation time 362360149 ps
CPU time 19.75 seconds
Started May 12 01:20:10 PM PDT 24
Finished May 12 01:20:30 PM PDT 24
Peak memory 216328 kb
Host smart-c5a8bb8a-a876-4bfc-b567-76fcb12a5b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109524812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2109524812
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2344676783
Short name T337
Test name
Test status
Simulation time 202469605 ps
CPU time 17.96 seconds
Started May 12 01:20:10 PM PDT 24
Finished May 12 01:20:29 PM PDT 24
Peak memory 212812 kb
Host smart-177e9b56-f57b-461f-9c69-b696ed3f2df8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344676783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2344676783
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.478413979
Short name T279
Test name
Test status
Simulation time 433972793 ps
CPU time 11.29 seconds
Started May 12 01:20:23 PM PDT 24
Finished May 12 01:20:35 PM PDT 24
Peak memory 211836 kb
Host smart-f700c68e-1d9d-4756-8596-a2739782bb52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478413979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.478413979
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2514140073
Short name T290
Test name
Test status
Simulation time 33930214957 ps
CPU time 387.21 seconds
Started May 12 01:20:19 PM PDT 24
Finished May 12 01:26:47 PM PDT 24
Peak memory 237232 kb
Host smart-2d114926-05e6-4819-bed0-19947d2ff60e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514140073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2514140073
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3844892247
Short name T319
Test name
Test status
Simulation time 8852171443 ps
CPU time 67.28 seconds
Started May 12 01:20:22 PM PDT 24
Finished May 12 01:21:30 PM PDT 24
Peak memory 216132 kb
Host smart-221bcda6-4e6f-46bc-b949-4c3feb00f3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844892247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3844892247
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3647357876
Short name T330
Test name
Test status
Simulation time 7270133947 ps
CPU time 21.53 seconds
Started May 12 01:20:17 PM PDT 24
Finished May 12 01:20:39 PM PDT 24
Peak memory 212036 kb
Host smart-a30e4931-502e-4db6-b9db-e5a4be4e928f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3647357876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3647357876
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2077318655
Short name T253
Test name
Test status
Simulation time 1436825708 ps
CPU time 20.85 seconds
Started May 12 01:20:15 PM PDT 24
Finished May 12 01:20:36 PM PDT 24
Peak memory 218032 kb
Host smart-55c2ab8c-0c1b-4f93-baf2-aa96fad4880d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077318655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2077318655
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3794668590
Short name T274
Test name
Test status
Simulation time 730005657 ps
CPU time 20.35 seconds
Started May 12 01:20:17 PM PDT 24
Finished May 12 01:20:38 PM PDT 24
Peak memory 218116 kb
Host smart-1188f84e-a2bc-4e7d-8edb-d73b6e4e23f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794668590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3794668590
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1468526222
Short name T328
Test name
Test status
Simulation time 4409289902 ps
CPU time 15.71 seconds
Started May 12 01:20:15 PM PDT 24
Finished May 12 01:20:31 PM PDT 24
Peak memory 211924 kb
Host smart-566cd141-3215-4140-9323-2462ef1f80d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468526222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1468526222
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1366316093
Short name T249
Test name
Test status
Simulation time 346492210 ps
CPU time 19.55 seconds
Started May 12 01:20:17 PM PDT 24
Finished May 12 01:20:37 PM PDT 24
Peak memory 215128 kb
Host smart-9c8a6af5-fc04-4eb9-bdfc-dff1706e459c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366316093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1366316093
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.943774211
Short name T109
Test name
Test status
Simulation time 17255916813 ps
CPU time 34.43 seconds
Started May 12 01:20:16 PM PDT 24
Finished May 12 01:20:51 PM PDT 24
Peak memory 211872 kb
Host smart-68eabe03-b543-4645-9acf-ad10f0750973
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=943774211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.943774211
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1251628504
Short name T128
Test name
Test status
Simulation time 8315409529 ps
CPU time 69.28 seconds
Started May 12 01:20:23 PM PDT 24
Finished May 12 01:21:33 PM PDT 24
Peak memory 215828 kb
Host smart-2dc39c82-95fe-47a8-8b7a-20954c81504f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251628504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1251628504
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2381606256
Short name T25
Test name
Test status
Simulation time 9345833979 ps
CPU time 118.4 seconds
Started May 12 01:20:21 PM PDT 24
Finished May 12 01:22:20 PM PDT 24
Peak memory 219872 kb
Host smart-9c34dd98-6fc8-4ca9-b815-47d1268b6d52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381606256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2381606256
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1013236734
Short name T206
Test name
Test status
Simulation time 174179099 ps
CPU time 8.21 seconds
Started May 12 01:20:20 PM PDT 24
Finished May 12 01:20:28 PM PDT 24
Peak memory 211772 kb
Host smart-21ef4ec4-4a44-4453-afbb-e53592d5e5ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013236734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1013236734
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3117191541
Short name T343
Test name
Test status
Simulation time 54107550163 ps
CPU time 473.55 seconds
Started May 12 01:20:27 PM PDT 24
Finished May 12 01:28:21 PM PDT 24
Peak memory 218432 kb
Host smart-009761ed-190c-46e5-b1cb-4bf02449855c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117191541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3117191541
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2693731515
Short name T232
Test name
Test status
Simulation time 3954409497 ps
CPU time 44.2 seconds
Started May 12 01:20:23 PM PDT 24
Finished May 12 01:21:08 PM PDT 24
Peak memory 215316 kb
Host smart-b5b67c0d-576d-4d30-9a29-0ca12c6646e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693731515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2693731515
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2278708506
Short name T9
Test name
Test status
Simulation time 3274081935 ps
CPU time 28.35 seconds
Started May 12 01:20:22 PM PDT 24
Finished May 12 01:20:51 PM PDT 24
Peak memory 212892 kb
Host smart-d857a3c7-888f-4f8d-8cb0-0f62a39c11dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2278708506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2278708506
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3510445239
Short name T127
Test name
Test status
Simulation time 2662536593 ps
CPU time 36.91 seconds
Started May 12 01:20:17 PM PDT 24
Finished May 12 01:20:54 PM PDT 24
Peak memory 214396 kb
Host smart-cff58054-48bc-44d2-a192-d12cc4c26354
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510445239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3510445239
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2223396094
Short name T236
Test name
Test status
Simulation time 87381177461 ps
CPU time 348.54 seconds
Started May 12 01:20:24 PM PDT 24
Finished May 12 01:26:13 PM PDT 24
Peak memory 238384 kb
Host smart-415fbc71-d197-4ce7-a02f-244245508e3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223396094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2223396094
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1601799614
Short name T320
Test name
Test status
Simulation time 8036512262 ps
CPU time 65.97 seconds
Started May 12 01:20:24 PM PDT 24
Finished May 12 01:21:31 PM PDT 24
Peak memory 215868 kb
Host smart-bda2c55b-2bc7-4e87-ba1a-a8c99dcfdc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601799614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1601799614
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.167488732
Short name T148
Test name
Test status
Simulation time 8178708323 ps
CPU time 32.46 seconds
Started May 12 01:20:25 PM PDT 24
Finished May 12 01:20:58 PM PDT 24
Peak memory 213080 kb
Host smart-3686a693-02a2-41b8-bc5a-ca3d95401427
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=167488732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.167488732
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1458354195
Short name T299
Test name
Test status
Simulation time 1425982478 ps
CPU time 19.77 seconds
Started May 12 01:20:23 PM PDT 24
Finished May 12 01:20:43 PM PDT 24
Peak memory 216676 kb
Host smart-a69096cf-3079-4202-a4a4-6f106dac9d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458354195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1458354195
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1484111955
Short name T324
Test name
Test status
Simulation time 754841988 ps
CPU time 25.75 seconds
Started May 12 01:20:27 PM PDT 24
Finished May 12 01:20:53 PM PDT 24
Peak memory 218836 kb
Host smart-32cbaad9-f933-4e46-86a4-707cb13027cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484111955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1484111955
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3096410052
Short name T72
Test name
Test status
Simulation time 338904003 ps
CPU time 8.31 seconds
Started May 12 01:19:28 PM PDT 24
Finished May 12 01:19:37 PM PDT 24
Peak memory 211672 kb
Host smart-8394a98d-18da-45a6-8938-6d378432565f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096410052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3096410052
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2774679353
Short name T190
Test name
Test status
Simulation time 28910691510 ps
CPU time 399.07 seconds
Started May 12 01:19:26 PM PDT 24
Finished May 12 01:26:06 PM PDT 24
Peak memory 240324 kb
Host smart-11abf4ab-8739-4ec1-a472-13a74e36db90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774679353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2774679353
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.465739377
Short name T204
Test name
Test status
Simulation time 7558780111 ps
CPU time 32.21 seconds
Started May 12 01:19:28 PM PDT 24
Finished May 12 01:20:00 PM PDT 24
Peak memory 214800 kb
Host smart-c34c4b48-a815-4b8b-bbb4-b294ee271de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465739377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.465739377
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1175802311
Short name T129
Test name
Test status
Simulation time 355490741 ps
CPU time 10.33 seconds
Started May 12 01:19:31 PM PDT 24
Finished May 12 01:19:41 PM PDT 24
Peak memory 212628 kb
Host smart-6d2a8d6d-a5ba-46f1-a5fb-0f3a5101feef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1175802311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1175802311
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1989305833
Short name T35
Test name
Test status
Simulation time 2572500056 ps
CPU time 152.65 seconds
Started May 12 01:19:26 PM PDT 24
Finished May 12 01:21:59 PM PDT 24
Peak memory 250616 kb
Host smart-60b3f836-12f0-4164-b4ac-dd140b31d454
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989305833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1989305833
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2961896014
Short name T288
Test name
Test status
Simulation time 32860145931 ps
CPU time 55.67 seconds
Started May 12 01:19:33 PM PDT 24
Finished May 12 01:20:29 PM PDT 24
Peak memory 218400 kb
Host smart-8ed8d894-ce79-4901-bbf2-671ef56d6825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961896014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2961896014
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3914936118
Short name T237
Test name
Test status
Simulation time 13748202588 ps
CPU time 124.3 seconds
Started May 12 01:19:29 PM PDT 24
Finished May 12 01:21:33 PM PDT 24
Peak memory 221104 kb
Host smart-94584bfc-8961-4092-ad77-50ee8cd8c341
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914936118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3914936118
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2828638456
Short name T58
Test name
Test status
Simulation time 15376792461 ps
CPU time 29.56 seconds
Started May 12 01:20:24 PM PDT 24
Finished May 12 01:20:55 PM PDT 24
Peak memory 212636 kb
Host smart-eabcc675-60f0-4f38-8368-e0a8a0a12f41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828638456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2828638456
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3141696641
Short name T241
Test name
Test status
Simulation time 74000656641 ps
CPU time 266.34 seconds
Started May 12 01:20:23 PM PDT 24
Finished May 12 01:24:50 PM PDT 24
Peak memory 233440 kb
Host smart-2b368d55-e3f3-4a0a-a2ab-c7ffb1e5006b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141696641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3141696641
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.695354371
Short name T293
Test name
Test status
Simulation time 17708349541 ps
CPU time 45.17 seconds
Started May 12 01:20:24 PM PDT 24
Finished May 12 01:21:10 PM PDT 24
Peak memory 215576 kb
Host smart-a212e207-06a2-412e-babd-99c0485f385a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695354371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.695354371
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3694166860
Short name T284
Test name
Test status
Simulation time 12596918528 ps
CPU time 20.5 seconds
Started May 12 01:20:24 PM PDT 24
Finished May 12 01:20:45 PM PDT 24
Peak memory 212280 kb
Host smart-28a54970-6824-4706-9018-c111c14e1bb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3694166860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3694166860
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.769166866
Short name T275
Test name
Test status
Simulation time 22656034782 ps
CPU time 44.06 seconds
Started May 12 01:20:22 PM PDT 24
Finished May 12 01:21:06 PM PDT 24
Peak memory 217960 kb
Host smart-353fba07-ac18-49f9-ab8b-48318d3082d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769166866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.769166866
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1821095334
Short name T162
Test name
Test status
Simulation time 796321169 ps
CPU time 28.61 seconds
Started May 12 01:20:21 PM PDT 24
Finished May 12 01:20:50 PM PDT 24
Peak memory 218560 kb
Host smart-0127632a-5b79-423c-b326-54ee9e159686
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821095334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1821095334
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.792495464
Short name T186
Test name
Test status
Simulation time 3416674950 ps
CPU time 13.4 seconds
Started May 12 01:20:28 PM PDT 24
Finished May 12 01:20:42 PM PDT 24
Peak memory 211820 kb
Host smart-037af86e-3249-4147-94de-053c99d4deb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792495464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.792495464
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2135674876
Short name T326
Test name
Test status
Simulation time 7486889908 ps
CPU time 148.52 seconds
Started May 12 01:20:27 PM PDT 24
Finished May 12 01:22:56 PM PDT 24
Peak memory 239980 kb
Host smart-151cafaa-1512-4396-a128-482e3c906191
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135674876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2135674876
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3576346250
Short name T215
Test name
Test status
Simulation time 32049385789 ps
CPU time 65.45 seconds
Started May 12 01:20:25 PM PDT 24
Finished May 12 01:21:31 PM PDT 24
Peak memory 214836 kb
Host smart-64daabdf-7349-4676-8a41-502fef0d6d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576346250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3576346250
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4249211068
Short name T325
Test name
Test status
Simulation time 1052118731 ps
CPU time 17.21 seconds
Started May 12 01:20:27 PM PDT 24
Finished May 12 01:20:44 PM PDT 24
Peak memory 211752 kb
Host smart-b3daa543-0602-4bc1-b791-fddb665e2a66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4249211068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4249211068
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3529382598
Short name T41
Test name
Test status
Simulation time 4145725489 ps
CPU time 26.79 seconds
Started May 12 01:20:25 PM PDT 24
Finished May 12 01:20:53 PM PDT 24
Peak memory 216352 kb
Host smart-a0fea6a1-9470-4f59-92ca-604365b51446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529382598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3529382598
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.4096253783
Short name T350
Test name
Test status
Simulation time 72568100110 ps
CPU time 115.02 seconds
Started May 12 01:20:27 PM PDT 24
Finished May 12 01:22:22 PM PDT 24
Peak memory 219896 kb
Host smart-5bec847f-ddc0-4ee0-bea2-8ae0c7682022
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096253783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.4096253783
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2859524857
Short name T51
Test name
Test status
Simulation time 26224114632 ps
CPU time 681.79 seconds
Started May 12 01:20:26 PM PDT 24
Finished May 12 01:31:48 PM PDT 24
Peak memory 236324 kb
Host smart-8be18e01-9b5a-47d2-8e4d-24d22395ae99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859524857 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2859524857
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1009135301
Short name T132
Test name
Test status
Simulation time 2568583731 ps
CPU time 23.84 seconds
Started May 12 01:20:27 PM PDT 24
Finished May 12 01:20:51 PM PDT 24
Peak memory 211820 kb
Host smart-6ad68983-bc3b-4617-8ec0-d8a6693fc230
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009135301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1009135301
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3403991492
Short name T329
Test name
Test status
Simulation time 103628743354 ps
CPU time 700.71 seconds
Started May 12 01:20:25 PM PDT 24
Finished May 12 01:32:07 PM PDT 24
Peak memory 234368 kb
Host smart-09e4e682-cfc8-48d1-a0a3-fd83372cc61e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403991492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3403991492
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4116324576
Short name T303
Test name
Test status
Simulation time 53660961698 ps
CPU time 66.97 seconds
Started May 12 01:20:25 PM PDT 24
Finished May 12 01:21:33 PM PDT 24
Peak memory 215976 kb
Host smart-7cba9f3a-5174-4d0f-b625-e120e757bc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116324576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.4116324576
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.910464683
Short name T189
Test name
Test status
Simulation time 178625043 ps
CPU time 10.44 seconds
Started May 12 01:20:27 PM PDT 24
Finished May 12 01:20:38 PM PDT 24
Peak memory 212804 kb
Host smart-37e8ebbe-a18c-445b-9857-25972924de5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=910464683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.910464683
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1643671450
Short name T262
Test name
Test status
Simulation time 27557198891 ps
CPU time 62.87 seconds
Started May 12 01:20:24 PM PDT 24
Finished May 12 01:21:28 PM PDT 24
Peak memory 216320 kb
Host smart-49d88967-7564-4b44-8e15-4d3e37d9fa53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643671450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1643671450
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1046550361
Short name T157
Test name
Test status
Simulation time 7035088569 ps
CPU time 67.66 seconds
Started May 12 01:20:26 PM PDT 24
Finished May 12 01:21:34 PM PDT 24
Peak memory 220872 kb
Host smart-307001e5-a5af-49ab-b660-169cab477349
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046550361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1046550361
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3638029381
Short name T160
Test name
Test status
Simulation time 31439789567 ps
CPU time 31.14 seconds
Started May 12 01:20:30 PM PDT 24
Finished May 12 01:21:02 PM PDT 24
Peak memory 211904 kb
Host smart-6625b0bb-a3cb-452a-be82-e314d774a4db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638029381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3638029381
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2945288953
Short name T243
Test name
Test status
Simulation time 5470403357 ps
CPU time 145.03 seconds
Started May 12 01:20:28 PM PDT 24
Finished May 12 01:22:54 PM PDT 24
Peak memory 237160 kb
Host smart-d42367ee-6c09-4585-88c5-a90b2f042b16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945288953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2945288953
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1017118000
Short name T223
Test name
Test status
Simulation time 339333186 ps
CPU time 20.01 seconds
Started May 12 01:20:30 PM PDT 24
Finished May 12 01:20:51 PM PDT 24
Peak memory 215132 kb
Host smart-9c326340-0410-4bfb-8f48-f5af0dc5ef8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017118000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1017118000
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2601008732
Short name T300
Test name
Test status
Simulation time 686060985 ps
CPU time 12.44 seconds
Started May 12 01:20:25 PM PDT 24
Finished May 12 01:20:38 PM PDT 24
Peak memory 211768 kb
Host smart-291ec76d-be5a-4e7f-a2fc-29143400198c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2601008732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2601008732
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3263190783
Short name T307
Test name
Test status
Simulation time 6648973638 ps
CPU time 38.87 seconds
Started May 12 01:20:24 PM PDT 24
Finished May 12 01:21:04 PM PDT 24
Peak memory 217916 kb
Host smart-8b3e7fa1-a4dd-46c9-b072-f72bbe9e7556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263190783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3263190783
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2933850633
Short name T89
Test name
Test status
Simulation time 13341777258 ps
CPU time 81.3 seconds
Started May 12 01:20:26 PM PDT 24
Finished May 12 01:21:47 PM PDT 24
Peak memory 219868 kb
Host smart-32c5cf85-1393-441c-adaf-31b023da148b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933850633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2933850633
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1733184609
Short name T282
Test name
Test status
Simulation time 174425295 ps
CPU time 8.44 seconds
Started May 12 01:20:30 PM PDT 24
Finished May 12 01:20:38 PM PDT 24
Peak memory 211760 kb
Host smart-327b2cb4-0204-4ea2-a0b2-284c6994c813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733184609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1733184609
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3951240327
Short name T244
Test name
Test status
Simulation time 342430250616 ps
CPU time 417.15 seconds
Started May 12 01:20:33 PM PDT 24
Finished May 12 01:27:31 PM PDT 24
Peak memory 228648 kb
Host smart-a0628ea2-ca4a-47ba-8144-d83d7ce5b100
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951240327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3951240327
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3474167420
Short name T177
Test name
Test status
Simulation time 90153062288 ps
CPU time 53.42 seconds
Started May 12 01:20:30 PM PDT 24
Finished May 12 01:21:24 PM PDT 24
Peak memory 215488 kb
Host smart-61089b10-579e-4e4e-9870-540414d1becf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474167420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3474167420
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1515107440
Short name T199
Test name
Test status
Simulation time 546259988 ps
CPU time 12.85 seconds
Started May 12 01:20:31 PM PDT 24
Finished May 12 01:20:44 PM PDT 24
Peak memory 211976 kb
Host smart-2802ef89-7295-464f-93a1-094d33245d4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1515107440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1515107440
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3333780655
Short name T331
Test name
Test status
Simulation time 31208866171 ps
CPU time 52.85 seconds
Started May 12 01:20:32 PM PDT 24
Finished May 12 01:21:25 PM PDT 24
Peak memory 217872 kb
Host smart-55a6cde2-f72f-4b17-bd87-dbf7b761e54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333780655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3333780655
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1852112799
Short name T5
Test name
Test status
Simulation time 803127172 ps
CPU time 24.51 seconds
Started May 12 01:20:32 PM PDT 24
Finished May 12 01:20:56 PM PDT 24
Peak memory 212348 kb
Host smart-8bb9867d-a368-46b1-89a2-9ffa3f1a3d5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852112799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1852112799
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3226509593
Short name T50
Test name
Test status
Simulation time 18318974907 ps
CPU time 731.23 seconds
Started May 12 01:20:30 PM PDT 24
Finished May 12 01:32:42 PM PDT 24
Peak memory 236292 kb
Host smart-97df666d-4c0e-478d-907b-d5ac349818b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226509593 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.3226509593
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.4207615359
Short name T292
Test name
Test status
Simulation time 7303049178 ps
CPU time 17.35 seconds
Started May 12 01:20:38 PM PDT 24
Finished May 12 01:20:55 PM PDT 24
Peak memory 211900 kb
Host smart-67523a3b-a059-4dc6-9985-61c0e491b0fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207615359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.4207615359
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1456238256
Short name T224
Test name
Test status
Simulation time 97011972457 ps
CPU time 262.99 seconds
Started May 12 01:20:30 PM PDT 24
Finished May 12 01:24:53 PM PDT 24
Peak memory 229228 kb
Host smart-13b5c8da-3216-47a0-93e3-ef6ce5b01c5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456238256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1456238256
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3214049443
Short name T161
Test name
Test status
Simulation time 13290821298 ps
CPU time 54.34 seconds
Started May 12 01:20:38 PM PDT 24
Finished May 12 01:21:33 PM PDT 24
Peak memory 215620 kb
Host smart-63debb89-94e0-4423-96eb-23bac60c6604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214049443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3214049443
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.892957506
Short name T221
Test name
Test status
Simulation time 174631310 ps
CPU time 10.29 seconds
Started May 12 01:20:31 PM PDT 24
Finished May 12 01:20:41 PM PDT 24
Peak memory 213036 kb
Host smart-e11b3935-6a19-4203-804a-4137e6539ba1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=892957506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.892957506
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.401997217
Short name T175
Test name
Test status
Simulation time 16115996040 ps
CPU time 69.88 seconds
Started May 12 01:20:30 PM PDT 24
Finished May 12 01:21:40 PM PDT 24
Peak memory 217752 kb
Host smart-f3859c5c-6b68-43a8-963a-a5272f3cb6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401997217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.401997217
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.4073525537
Short name T74
Test name
Test status
Simulation time 7010737347 ps
CPU time 65.79 seconds
Started May 12 01:20:30 PM PDT 24
Finished May 12 01:21:36 PM PDT 24
Peak memory 216492 kb
Host smart-3ba51bd3-6ad4-495d-9fbd-0226727a8f88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073525537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.4073525537
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1564730341
Short name T302
Test name
Test status
Simulation time 11995959041 ps
CPU time 17.21 seconds
Started May 12 01:20:38 PM PDT 24
Finished May 12 01:20:55 PM PDT 24
Peak memory 211892 kb
Host smart-d55de413-9cde-46a0-9f4c-e4b83b4146c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564730341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1564730341
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3729574960
Short name T281
Test name
Test status
Simulation time 66444336799 ps
CPU time 637.14 seconds
Started May 12 01:20:36 PM PDT 24
Finished May 12 01:31:14 PM PDT 24
Peak memory 218352 kb
Host smart-1b884f84-833e-44ee-bf28-06590c668aba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729574960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3729574960
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3127606788
Short name T240
Test name
Test status
Simulation time 8017782541 ps
CPU time 66.25 seconds
Started May 12 01:20:41 PM PDT 24
Finished May 12 01:21:48 PM PDT 24
Peak memory 213808 kb
Host smart-33fc9744-0c13-450c-b6eb-262bd32b6ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127606788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3127606788
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3658209525
Short name T212
Test name
Test status
Simulation time 2888534119 ps
CPU time 27.08 seconds
Started May 12 01:20:34 PM PDT 24
Finished May 12 01:21:01 PM PDT 24
Peak memory 211872 kb
Host smart-8982c072-eb25-4c2e-b7f5-0b05a2eea55e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3658209525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3658209525
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2865198247
Short name T86
Test name
Test status
Simulation time 18502195232 ps
CPU time 63.64 seconds
Started May 12 01:20:36 PM PDT 24
Finished May 12 01:21:40 PM PDT 24
Peak memory 217800 kb
Host smart-a19dcb94-614d-4244-a440-5a68529caa48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865198247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2865198247
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3301884327
Short name T144
Test name
Test status
Simulation time 27818070758 ps
CPU time 122.91 seconds
Started May 12 01:20:34 PM PDT 24
Finished May 12 01:22:38 PM PDT 24
Peak memory 223928 kb
Host smart-6833fbfd-61cc-4aa0-ae28-c22e720fa2a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301884327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3301884327
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2693646209
Short name T53
Test name
Test status
Simulation time 1226370562502 ps
CPU time 3841.21 seconds
Started May 12 01:20:38 PM PDT 24
Finished May 12 02:24:40 PM PDT 24
Peak memory 252784 kb
Host smart-84c49a2c-09f0-462f-9c7c-61354f05df46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693646209 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.2693646209
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2337295144
Short name T142
Test name
Test status
Simulation time 176303576 ps
CPU time 8.33 seconds
Started May 12 01:20:42 PM PDT 24
Finished May 12 01:20:51 PM PDT 24
Peak memory 211788 kb
Host smart-0a81eb64-4a22-4718-8de1-b2ebf7a89208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337295144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2337295144
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2374307838
Short name T200
Test name
Test status
Simulation time 330972356368 ps
CPU time 750.23 seconds
Started May 12 01:20:42 PM PDT 24
Finished May 12 01:33:13 PM PDT 24
Peak memory 229620 kb
Host smart-2680691b-990c-403e-9455-e29fc2c64545
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374307838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2374307838
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2608060463
Short name T23
Test name
Test status
Simulation time 8219408854 ps
CPU time 52.91 seconds
Started May 12 01:20:39 PM PDT 24
Finished May 12 01:21:32 PM PDT 24
Peak memory 215948 kb
Host smart-4ed74812-7627-4719-b047-bfec7416197b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608060463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2608060463
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2334669403
Short name T165
Test name
Test status
Simulation time 6133403078 ps
CPU time 26.9 seconds
Started May 12 01:20:40 PM PDT 24
Finished May 12 01:21:08 PM PDT 24
Peak memory 213460 kb
Host smart-634f93c4-7b1c-4993-a461-43a3acd45c6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2334669403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2334669403
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.28003714
Short name T229
Test name
Test status
Simulation time 7240832083 ps
CPU time 34.76 seconds
Started May 12 01:20:37 PM PDT 24
Finished May 12 01:21:12 PM PDT 24
Peak memory 218180 kb
Host smart-49f53b54-40f3-4cf2-9956-f31bced07d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28003714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.28003714
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.58371673
Short name T248
Test name
Test status
Simulation time 5947673921 ps
CPU time 67.84 seconds
Started May 12 01:20:42 PM PDT 24
Finished May 12 01:21:50 PM PDT 24
Peak memory 219788 kb
Host smart-1f04af18-1444-4605-ae51-0ef08ff45f28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58371673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 37.rom_ctrl_stress_all.58371673
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1064068424
Short name T259
Test name
Test status
Simulation time 53646646540 ps
CPU time 30.72 seconds
Started May 12 01:20:42 PM PDT 24
Finished May 12 01:21:13 PM PDT 24
Peak memory 212632 kb
Host smart-fc20f792-ac52-4169-a3aa-c6631ee0d66a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064068424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1064068424
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1234452345
Short name T296
Test name
Test status
Simulation time 49833366086 ps
CPU time 346.64 seconds
Started May 12 01:20:40 PM PDT 24
Finished May 12 01:26:27 PM PDT 24
Peak memory 217316 kb
Host smart-97bfddfd-7c1a-47a3-9943-81bf3eed92b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234452345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1234452345
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.248645006
Short name T171
Test name
Test status
Simulation time 362135349 ps
CPU time 10.58 seconds
Started May 12 01:20:41 PM PDT 24
Finished May 12 01:20:52 PM PDT 24
Peak memory 212820 kb
Host smart-be65e3b3-0f11-44a9-a28b-5a289bd0271a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=248645006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.248645006
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2052409527
Short name T149
Test name
Test status
Simulation time 1298738696 ps
CPU time 20.42 seconds
Started May 12 01:20:39 PM PDT 24
Finished May 12 01:20:59 PM PDT 24
Peak memory 217396 kb
Host smart-46c58b57-26b7-4bf4-b671-970311ca598b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052409527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2052409527
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.884365237
Short name T64
Test name
Test status
Simulation time 14936064704 ps
CPU time 72.54 seconds
Started May 12 01:20:42 PM PDT 24
Finished May 12 01:21:55 PM PDT 24
Peak memory 219788 kb
Host smart-f9322dbf-807d-4155-8e33-6d7c399b4871
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884365237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.884365237
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3608092899
Short name T70
Test name
Test status
Simulation time 13302809586 ps
CPU time 30.09 seconds
Started May 12 01:20:46 PM PDT 24
Finished May 12 01:21:16 PM PDT 24
Peak memory 212716 kb
Host smart-08efe2bd-e909-4f4f-9734-c7fe0bfa7244
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608092899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3608092899
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.943386757
Short name T261
Test name
Test status
Simulation time 2563731221 ps
CPU time 157.2 seconds
Started May 12 01:20:45 PM PDT 24
Finished May 12 01:23:23 PM PDT 24
Peak memory 228944 kb
Host smart-9c604881-d0a0-45dd-a0e2-738dfab4ec88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943386757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.943386757
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.394925225
Short name T47
Test name
Test status
Simulation time 843799227 ps
CPU time 25.64 seconds
Started May 12 01:20:48 PM PDT 24
Finished May 12 01:21:14 PM PDT 24
Peak memory 215224 kb
Host smart-2f83c459-5595-4fd7-9a44-9c6c5b43f4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394925225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.394925225
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1830493514
Short name T60
Test name
Test status
Simulation time 177957388 ps
CPU time 10.42 seconds
Started May 12 01:20:46 PM PDT 24
Finished May 12 01:20:57 PM PDT 24
Peak memory 212740 kb
Host smart-76495876-9db5-41dd-992d-3a4b5a964d3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1830493514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1830493514
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1983630514
Short name T209
Test name
Test status
Simulation time 6214361407 ps
CPU time 56.64 seconds
Started May 12 01:20:42 PM PDT 24
Finished May 12 01:21:39 PM PDT 24
Peak memory 218120 kb
Host smart-8ec4c8ff-a3bd-4aa4-b4ce-f6fd4ad9f664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983630514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1983630514
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2693610905
Short name T163
Test name
Test status
Simulation time 7780515207 ps
CPU time 60.83 seconds
Started May 12 01:20:44 PM PDT 24
Finished May 12 01:21:46 PM PDT 24
Peak memory 219924 kb
Host smart-9cbfb271-bed7-4fc9-bea6-4944198d94be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693610905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2693610905
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1536108989
Short name T138
Test name
Test status
Simulation time 10209865107 ps
CPU time 23.43 seconds
Started May 12 01:19:35 PM PDT 24
Finished May 12 01:19:59 PM PDT 24
Peak memory 212752 kb
Host smart-00ab7fab-7238-4e64-a2a1-865085da7263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536108989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1536108989
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.725706723
Short name T24
Test name
Test status
Simulation time 67752522643 ps
CPU time 575.21 seconds
Started May 12 01:19:36 PM PDT 24
Finished May 12 01:29:12 PM PDT 24
Peak memory 234408 kb
Host smart-bbf330b4-f21c-4073-9cbe-f81fb3e749c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725706723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.725706723
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1543652806
Short name T59
Test name
Test status
Simulation time 8198706367 ps
CPU time 68.21 seconds
Started May 12 01:19:32 PM PDT 24
Finished May 12 01:20:41 PM PDT 24
Peak memory 215588 kb
Host smart-9a4c65f0-9427-4ed0-8d2c-748190ac8aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543652806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1543652806
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2709336908
Short name T152
Test name
Test status
Simulation time 3913684258 ps
CPU time 32.24 seconds
Started May 12 01:19:33 PM PDT 24
Finished May 12 01:20:06 PM PDT 24
Peak memory 211820 kb
Host smart-ed2f6cce-b91f-48b2-857e-e691239aac75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2709336908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2709336908
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2694907038
Short name T40
Test name
Test status
Simulation time 1610894131 ps
CPU time 126.28 seconds
Started May 12 01:19:35 PM PDT 24
Finished May 12 01:21:41 PM PDT 24
Peak memory 238040 kb
Host smart-5551d054-969f-441a-a823-d99287d5fe54
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694907038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2694907038
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2817252326
Short name T44
Test name
Test status
Simulation time 1869498229 ps
CPU time 31.34 seconds
Started May 12 01:19:32 PM PDT 24
Finished May 12 01:20:04 PM PDT 24
Peak memory 216772 kb
Host smart-3a56b451-5ef1-4f73-b018-9628b7db7c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817252326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2817252326
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3257071914
Short name T218
Test name
Test status
Simulation time 54808991792 ps
CPU time 144.81 seconds
Started May 12 01:19:31 PM PDT 24
Finished May 12 01:21:57 PM PDT 24
Peak memory 220404 kb
Host smart-015e6c23-1aaf-4603-b750-b7ed6c5be4aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257071914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3257071914
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3221125409
Short name T18
Test name
Test status
Simulation time 54179434115 ps
CPU time 2237.03 seconds
Started May 12 01:19:31 PM PDT 24
Finished May 12 01:56:49 PM PDT 24
Peak memory 245992 kb
Host smart-a91b2589-b52f-448b-b9bf-a1a011288181
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221125409 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.3221125409
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.133281551
Short name T154
Test name
Test status
Simulation time 404829190 ps
CPU time 8.22 seconds
Started May 12 01:20:52 PM PDT 24
Finished May 12 01:21:01 PM PDT 24
Peak memory 211816 kb
Host smart-e3518b51-37ae-483e-9422-5a0849f460d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133281551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.133281551
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3493920909
Short name T225
Test name
Test status
Simulation time 138059261037 ps
CPU time 1347.24 seconds
Started May 12 01:20:46 PM PDT 24
Finished May 12 01:43:14 PM PDT 24
Peak memory 225856 kb
Host smart-84f23791-febc-4a72-bcfd-f2cae30b53fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493920909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3493920909
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1296211240
Short name T150
Test name
Test status
Simulation time 12307565646 ps
CPU time 27.25 seconds
Started May 12 01:20:44 PM PDT 24
Finished May 12 01:21:11 PM PDT 24
Peak memory 215652 kb
Host smart-ea6b223a-4b6d-40a0-805e-c21e813dc4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296211240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1296211240
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2679005910
Short name T108
Test name
Test status
Simulation time 354106605 ps
CPU time 10.48 seconds
Started May 12 01:20:45 PM PDT 24
Finished May 12 01:20:56 PM PDT 24
Peak memory 212704 kb
Host smart-b7bc6071-2b85-44da-8a8a-e5daadd2bf6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2679005910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2679005910
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2117295638
Short name T254
Test name
Test status
Simulation time 1548680079 ps
CPU time 20.1 seconds
Started May 12 01:20:47 PM PDT 24
Finished May 12 01:21:07 PM PDT 24
Peak memory 216228 kb
Host smart-f01486e3-362b-41cc-ab8f-46fdf51bccb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117295638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2117295638
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1878235901
Short name T176
Test name
Test status
Simulation time 57676021410 ps
CPU time 92.25 seconds
Started May 12 01:20:46 PM PDT 24
Finished May 12 01:22:18 PM PDT 24
Peak memory 221348 kb
Host smart-394282f3-623f-4d7c-9723-29e35c0ee46d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878235901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1878235901
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.567231534
Short name T52
Test name
Test status
Simulation time 392065457849 ps
CPU time 3221.02 seconds
Started May 12 01:20:49 PM PDT 24
Finished May 12 02:14:30 PM PDT 24
Peak memory 250708 kb
Host smart-c937cf6d-8596-498b-a992-4d1b5445df25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567231534 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.567231534
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.244944644
Short name T133
Test name
Test status
Simulation time 4339113580 ps
CPU time 32.23 seconds
Started May 12 01:20:49 PM PDT 24
Finished May 12 01:21:21 PM PDT 24
Peak memory 211892 kb
Host smart-b29b2491-a592-4a52-9ffe-e77aa193b22d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244944644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.244944644
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3370553055
Short name T49
Test name
Test status
Simulation time 3262928614 ps
CPU time 217.74 seconds
Started May 12 01:20:54 PM PDT 24
Finished May 12 01:24:32 PM PDT 24
Peak memory 235640 kb
Host smart-b77e0aff-a3fb-4fe2-90dc-da9396da3063
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370553055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3370553055
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3554030303
Short name T242
Test name
Test status
Simulation time 7139939197 ps
CPU time 59.94 seconds
Started May 12 01:20:52 PM PDT 24
Finished May 12 01:21:52 PM PDT 24
Peak memory 215096 kb
Host smart-55ee0c3a-ed6b-4377-bdd0-8066c109776f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554030303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3554030303
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2804045255
Short name T338
Test name
Test status
Simulation time 2086700131 ps
CPU time 23.4 seconds
Started May 12 01:20:50 PM PDT 24
Finished May 12 01:21:14 PM PDT 24
Peak memory 211716 kb
Host smart-bd7dc867-90b5-4d0f-b7b5-351ed91c411b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2804045255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2804045255
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1165216536
Short name T341
Test name
Test status
Simulation time 389097314 ps
CPU time 19.75 seconds
Started May 12 01:20:54 PM PDT 24
Finished May 12 01:21:14 PM PDT 24
Peak memory 216900 kb
Host smart-2cf610bb-17b5-45d9-98fa-282672560a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165216536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1165216536
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3477725556
Short name T159
Test name
Test status
Simulation time 8014782530 ps
CPU time 110.03 seconds
Started May 12 01:20:50 PM PDT 24
Finished May 12 01:22:40 PM PDT 24
Peak memory 219928 kb
Host smart-9cf71cf4-ebb8-45b3-8155-d9b29a84d62d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477725556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3477725556
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1495377746
Short name T333
Test name
Test status
Simulation time 1452073375 ps
CPU time 11.76 seconds
Started May 12 01:20:56 PM PDT 24
Finished May 12 01:21:08 PM PDT 24
Peak memory 211696 kb
Host smart-db012e02-3823-489f-b522-7fb00f784ba0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495377746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1495377746
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1642229462
Short name T271
Test name
Test status
Simulation time 63389932768 ps
CPU time 424.54 seconds
Started May 12 01:20:55 PM PDT 24
Finished May 12 01:28:00 PM PDT 24
Peak memory 228316 kb
Host smart-8387c406-2503-41b2-818e-0de171572bab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642229462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1642229462
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2290359217
Short name T264
Test name
Test status
Simulation time 7493481943 ps
CPU time 61.34 seconds
Started May 12 01:20:57 PM PDT 24
Finished May 12 01:21:59 PM PDT 24
Peak memory 215664 kb
Host smart-aa19bc08-6661-4c32-bcdc-3934ccee98d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290359217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2290359217
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.176744052
Short name T323
Test name
Test status
Simulation time 15954776302 ps
CPU time 29.51 seconds
Started May 12 01:20:57 PM PDT 24
Finished May 12 01:21:27 PM PDT 24
Peak memory 212284 kb
Host smart-895beaec-8475-46cd-abc1-0336c8a1b4ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=176744052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.176744052
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3133787856
Short name T126
Test name
Test status
Simulation time 58476253879 ps
CPU time 46.39 seconds
Started May 12 01:20:49 PM PDT 24
Finished May 12 01:21:36 PM PDT 24
Peak memory 217636 kb
Host smart-44c22b92-17b9-45da-abbd-a234d7dffdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133787856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3133787856
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3128879504
Short name T273
Test name
Test status
Simulation time 39329109171 ps
CPU time 115.43 seconds
Started May 12 01:20:54 PM PDT 24
Finished May 12 01:22:50 PM PDT 24
Peak memory 219944 kb
Host smart-c1c40083-08af-45eb-9be8-8d117d1ad442
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128879504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3128879504
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3259547110
Short name T260
Test name
Test status
Simulation time 6853317466 ps
CPU time 25.36 seconds
Started May 12 01:20:55 PM PDT 24
Finished May 12 01:21:21 PM PDT 24
Peak memory 211932 kb
Host smart-107dfcc2-f852-4e8c-8309-e6f23cc259df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259547110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3259547110
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1238008956
Short name T258
Test name
Test status
Simulation time 108744958622 ps
CPU time 327.2 seconds
Started May 12 01:20:55 PM PDT 24
Finished May 12 01:26:23 PM PDT 24
Peak memory 237344 kb
Host smart-44db3fe7-b74b-48ef-9863-8cced6887854
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238008956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1238008956
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4244234381
Short name T342
Test name
Test status
Simulation time 661766607 ps
CPU time 18.63 seconds
Started May 12 01:20:57 PM PDT 24
Finished May 12 01:21:16 PM PDT 24
Peak memory 215224 kb
Host smart-a4fa65f7-b8e1-483b-9033-63b908d62a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244234381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4244234381
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.4199971282
Short name T151
Test name
Test status
Simulation time 357917313 ps
CPU time 10.71 seconds
Started May 12 01:20:55 PM PDT 24
Finished May 12 01:21:07 PM PDT 24
Peak memory 211816 kb
Host smart-0aeb6d9b-12b6-49f0-b7c4-3dd739bd0ec5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4199971282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.4199971282
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3980421594
Short name T348
Test name
Test status
Simulation time 8041121493 ps
CPU time 94.7 seconds
Started May 12 01:20:54 PM PDT 24
Finished May 12 01:22:30 PM PDT 24
Peak memory 215732 kb
Host smart-23169e02-8e2c-4f8b-b71b-2cfe10f9dde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980421594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3980421594
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2390505475
Short name T251
Test name
Test status
Simulation time 445570151 ps
CPU time 11.81 seconds
Started May 12 01:20:56 PM PDT 24
Finished May 12 01:21:08 PM PDT 24
Peak memory 214320 kb
Host smart-aa75ac23-7b47-4c39-bed9-2b4f0a7c9d9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390505475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2390505475
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2379025851
Short name T141
Test name
Test status
Simulation time 684615378 ps
CPU time 13.07 seconds
Started May 12 01:20:56 PM PDT 24
Finished May 12 01:21:09 PM PDT 24
Peak memory 211796 kb
Host smart-e8fb9efd-bc36-4f9c-99dc-87c949fbdd8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379025851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2379025851
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1522650112
Short name T191
Test name
Test status
Simulation time 31273472274 ps
CPU time 409.47 seconds
Started May 12 01:20:55 PM PDT 24
Finished May 12 01:27:45 PM PDT 24
Peak memory 228692 kb
Host smart-6004111b-1fe1-42be-9c4c-609e996aa588
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522650112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1522650112
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1358333163
Short name T6
Test name
Test status
Simulation time 4689148897 ps
CPU time 48.9 seconds
Started May 12 01:20:56 PM PDT 24
Finished May 12 01:21:46 PM PDT 24
Peak memory 215496 kb
Host smart-cbebb352-cdd6-43e5-b9a9-98d73317c0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358333163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1358333163
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2567628989
Short name T174
Test name
Test status
Simulation time 8657064155 ps
CPU time 34.41 seconds
Started May 12 01:20:54 PM PDT 24
Finished May 12 01:21:29 PM PDT 24
Peak memory 213064 kb
Host smart-93d523de-9a09-4a66-a4e8-45ac99c6f383
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2567628989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2567628989
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.4173887185
Short name T46
Test name
Test status
Simulation time 32083279526 ps
CPU time 75.89 seconds
Started May 12 01:20:56 PM PDT 24
Finished May 12 01:22:12 PM PDT 24
Peak memory 218092 kb
Host smart-c82ced36-2bd8-483e-808c-a3b6e31e7441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173887185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.4173887185
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3959339843
Short name T349
Test name
Test status
Simulation time 10677000291 ps
CPU time 99.58 seconds
Started May 12 01:20:58 PM PDT 24
Finished May 12 01:22:38 PM PDT 24
Peak memory 219928 kb
Host smart-23c01b8a-c832-4e16-9ca4-500b3997be9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959339843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3959339843
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2275865746
Short name T61
Test name
Test status
Simulation time 33806065493 ps
CPU time 27.25 seconds
Started May 12 01:20:57 PM PDT 24
Finished May 12 01:21:25 PM PDT 24
Peak memory 211856 kb
Host smart-a0a11cbe-6ed8-4e57-9fa4-2c3da4ea98e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275865746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2275865746
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2829344612
Short name T14
Test name
Test status
Simulation time 11975702891 ps
CPU time 345.3 seconds
Started May 12 01:20:55 PM PDT 24
Finished May 12 01:26:41 PM PDT 24
Peak memory 237356 kb
Host smart-b70be066-2061-40e7-afae-5efa42977882
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829344612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2829344612
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.407365603
Short name T29
Test name
Test status
Simulation time 1977224862 ps
CPU time 32.53 seconds
Started May 12 01:20:59 PM PDT 24
Finished May 12 01:21:32 PM PDT 24
Peak memory 215460 kb
Host smart-1eaa34b0-6c9b-4423-b366-7d0fb4c10703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407365603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.407365603
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1002516549
Short name T170
Test name
Test status
Simulation time 3557706590 ps
CPU time 30.34 seconds
Started May 12 01:20:54 PM PDT 24
Finished May 12 01:21:25 PM PDT 24
Peak memory 213196 kb
Host smart-7371be82-6061-4884-ac0f-b5f4c74b901c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1002516549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1002516549
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2946202373
Short name T336
Test name
Test status
Simulation time 7573487170 ps
CPU time 68.25 seconds
Started May 12 01:20:54 PM PDT 24
Finished May 12 01:22:03 PM PDT 24
Peak memory 218168 kb
Host smart-06e1161c-6022-48ab-b292-41ab804f471c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946202373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2946202373
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1897156099
Short name T316
Test name
Test status
Simulation time 391878038 ps
CPU time 20.47 seconds
Started May 12 01:20:54 PM PDT 24
Finished May 12 01:21:15 PM PDT 24
Peak memory 211584 kb
Host smart-93e3e6b5-8da4-47a7-98bc-7b0a40c86b2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897156099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1897156099
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3829990369
Short name T270
Test name
Test status
Simulation time 26909361477 ps
CPU time 31.55 seconds
Started May 12 01:21:01 PM PDT 24
Finished May 12 01:21:33 PM PDT 24
Peak memory 212748 kb
Host smart-cb51d273-2706-4fa0-be2e-a6e0c48f8e58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829990369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3829990369
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3095640986
Short name T211
Test name
Test status
Simulation time 3858721606 ps
CPU time 175.34 seconds
Started May 12 01:20:59 PM PDT 24
Finished May 12 01:23:54 PM PDT 24
Peak memory 238380 kb
Host smart-1634819f-573b-4e26-ba11-19714ad723d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095640986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3095640986
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1823110520
Short name T234
Test name
Test status
Simulation time 17673514349 ps
CPU time 46.51 seconds
Started May 12 01:20:59 PM PDT 24
Finished May 12 01:21:46 PM PDT 24
Peak memory 215540 kb
Host smart-32c114a8-c447-43e7-a9c4-fad1eff668b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823110520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1823110520
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1162709003
Short name T233
Test name
Test status
Simulation time 15432767470 ps
CPU time 31.91 seconds
Started May 12 01:20:58 PM PDT 24
Finished May 12 01:21:30 PM PDT 24
Peak memory 212192 kb
Host smart-68f9bc7a-a4b5-4723-91bc-5c68a321a9e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1162709003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1162709003
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2877321335
Short name T285
Test name
Test status
Simulation time 4868336619 ps
CPU time 28.64 seconds
Started May 12 01:20:58 PM PDT 24
Finished May 12 01:21:27 PM PDT 24
Peak memory 217480 kb
Host smart-5980c3ee-4982-46e4-ba88-b1b76baf0b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877321335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2877321335
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3429328193
Short name T173
Test name
Test status
Simulation time 67769767589 ps
CPU time 158.59 seconds
Started May 12 01:21:02 PM PDT 24
Finished May 12 01:23:41 PM PDT 24
Peak memory 220328 kb
Host smart-bf76425e-f97f-4dbe-bf32-3cc4f190c238
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429328193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3429328193
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.186996004
Short name T245
Test name
Test status
Simulation time 13767069015 ps
CPU time 26.8 seconds
Started May 12 01:21:03 PM PDT 24
Finished May 12 01:21:30 PM PDT 24
Peak memory 212668 kb
Host smart-603af6ed-feb5-449b-b36c-55433ae0653b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186996004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.186996004
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1475451159
Short name T26
Test name
Test status
Simulation time 152916830943 ps
CPU time 570.81 seconds
Started May 12 01:21:04 PM PDT 24
Finished May 12 01:30:35 PM PDT 24
Peak memory 229152 kb
Host smart-4262fcf7-525d-4b3f-b801-75f771343dd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475451159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1475451159
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1834117413
Short name T309
Test name
Test status
Simulation time 4705862062 ps
CPU time 26.32 seconds
Started May 12 01:21:03 PM PDT 24
Finished May 12 01:21:29 PM PDT 24
Peak memory 213708 kb
Host smart-35f45d2a-19bb-435f-816c-de5054c9faae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834117413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1834117413
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.88105547
Short name T327
Test name
Test status
Simulation time 358382287 ps
CPU time 10.29 seconds
Started May 12 01:20:59 PM PDT 24
Finished May 12 01:21:10 PM PDT 24
Peak memory 212692 kb
Host smart-2f5b93e5-6cc9-48c5-990a-a984112966cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=88105547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.88105547
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.4248224215
Short name T156
Test name
Test status
Simulation time 4660881986 ps
CPU time 28.11 seconds
Started May 12 01:20:59 PM PDT 24
Finished May 12 01:21:28 PM PDT 24
Peak memory 218288 kb
Host smart-9f58763c-9742-4264-8eb5-3411b5b1117f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248224215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.4248224215
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.870290553
Short name T214
Test name
Test status
Simulation time 7399251970 ps
CPU time 35.76 seconds
Started May 12 01:20:57 PM PDT 24
Finished May 12 01:21:33 PM PDT 24
Peak memory 214612 kb
Host smart-9adc7772-b77a-4ecf-a808-8b3456779741
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870290553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.870290553
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.348397783
Short name T73
Test name
Test status
Simulation time 11816806747 ps
CPU time 25.77 seconds
Started May 12 01:21:03 PM PDT 24
Finished May 12 01:21:29 PM PDT 24
Peak memory 212720 kb
Host smart-dda3a09a-7b68-4ea5-948d-7afcfbedc555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348397783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.348397783
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1305180495
Short name T227
Test name
Test status
Simulation time 3377607971 ps
CPU time 236.78 seconds
Started May 12 01:21:04 PM PDT 24
Finished May 12 01:25:01 PM PDT 24
Peak memory 218544 kb
Host smart-a13eb9ac-7fc0-41d5-a63f-e8b506cc4cd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305180495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1305180495
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2731980654
Short name T289
Test name
Test status
Simulation time 826679462 ps
CPU time 25.89 seconds
Started May 12 01:21:04 PM PDT 24
Finished May 12 01:21:31 PM PDT 24
Peak memory 215348 kb
Host smart-4121ac8a-8013-45de-a170-fb6dd2c5e9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731980654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2731980654
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3748481851
Short name T255
Test name
Test status
Simulation time 4228088712 ps
CPU time 29.75 seconds
Started May 12 01:21:03 PM PDT 24
Finished May 12 01:21:33 PM PDT 24
Peak memory 211868 kb
Host smart-fb1d11d6-8c86-47a8-b2aa-dd20b4c2b56e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3748481851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3748481851
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1983115922
Short name T313
Test name
Test status
Simulation time 3705007439 ps
CPU time 44.41 seconds
Started May 12 01:21:04 PM PDT 24
Finished May 12 01:21:49 PM PDT 24
Peak memory 217076 kb
Host smart-b7c31b2e-aa1e-4e4a-a1fa-4bb97cd0f91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983115922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1983115922
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.976612255
Short name T238
Test name
Test status
Simulation time 1497386745 ps
CPU time 24.95 seconds
Started May 12 01:21:03 PM PDT 24
Finished May 12 01:21:28 PM PDT 24
Peak memory 217836 kb
Host smart-8f257f83-f97d-46af-ad88-1b3c498b1098
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976612255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.976612255
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1759611518
Short name T322
Test name
Test status
Simulation time 10200618269 ps
CPU time 23.48 seconds
Started May 12 01:21:10 PM PDT 24
Finished May 12 01:21:33 PM PDT 24
Peak memory 212716 kb
Host smart-d875457a-11bc-4df1-96eb-6cb2be86e04e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759611518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1759611518
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3608931242
Short name T194
Test name
Test status
Simulation time 228004018627 ps
CPU time 1059.04 seconds
Started May 12 01:21:09 PM PDT 24
Finished May 12 01:38:48 PM PDT 24
Peak memory 217188 kb
Host smart-0ea70262-dfd2-4ee9-8a59-f8ba1604be7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608931242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3608931242
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2199170151
Short name T228
Test name
Test status
Simulation time 5457508723 ps
CPU time 28.16 seconds
Started May 12 01:21:06 PM PDT 24
Finished May 12 01:21:34 PM PDT 24
Peak memory 214388 kb
Host smart-c76c4ccc-a403-474f-92d6-2220442f260d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199170151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2199170151
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1979870907
Short name T230
Test name
Test status
Simulation time 10497992839 ps
CPU time 24.18 seconds
Started May 12 01:21:08 PM PDT 24
Finished May 12 01:21:33 PM PDT 24
Peak memory 212280 kb
Host smart-451fac0e-c7c8-4203-856f-c60062ee9991
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1979870907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1979870907
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2168805732
Short name T13
Test name
Test status
Simulation time 6783037040 ps
CPU time 60.06 seconds
Started May 12 01:21:02 PM PDT 24
Finished May 12 01:22:03 PM PDT 24
Peak memory 217864 kb
Host smart-800d067b-d3e9-43ae-9ad6-a05cc6ecad9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168805732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2168805732
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2197755411
Short name T135
Test name
Test status
Simulation time 2615791681 ps
CPU time 18.06 seconds
Started May 12 01:19:32 PM PDT 24
Finished May 12 01:19:51 PM PDT 24
Peak memory 211936 kb
Host smart-da37b88f-7086-48d4-9d26-31c43ee132b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197755411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2197755411
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.488132165
Short name T351
Test name
Test status
Simulation time 125033602441 ps
CPU time 406.22 seconds
Started May 12 01:19:36 PM PDT 24
Finished May 12 01:26:23 PM PDT 24
Peak memory 238428 kb
Host smart-263f535a-1735-4d5d-8dd6-53609b43459a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488132165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.488132165
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.112568015
Short name T188
Test name
Test status
Simulation time 1155498483 ps
CPU time 27.62 seconds
Started May 12 01:19:33 PM PDT 24
Finished May 12 01:20:01 PM PDT 24
Peak memory 215288 kb
Host smart-351bb634-ebc5-46dc-ace5-f5fe0d009933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112568015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.112568015
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.77886575
Short name T164
Test name
Test status
Simulation time 532808889 ps
CPU time 14.09 seconds
Started May 12 01:19:32 PM PDT 24
Finished May 12 01:19:46 PM PDT 24
Peak memory 212944 kb
Host smart-de75ff96-ba70-4544-b234-0fe847c87317
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77886575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.77886575
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1831461269
Short name T277
Test name
Test status
Simulation time 10574927899 ps
CPU time 36.72 seconds
Started May 12 01:19:32 PM PDT 24
Finished May 12 01:20:10 PM PDT 24
Peak memory 219244 kb
Host smart-3a28e034-4d80-45d8-95ce-9ab7e1ad0159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831461269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1831461269
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3516193984
Short name T283
Test name
Test status
Simulation time 12808342135 ps
CPU time 123.44 seconds
Started May 12 01:19:35 PM PDT 24
Finished May 12 01:21:39 PM PDT 24
Peak memory 220972 kb
Host smart-a923c0a4-6486-45e9-8d3f-970b276dc2dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516193984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3516193984
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3920032302
Short name T280
Test name
Test status
Simulation time 1077267186 ps
CPU time 15.23 seconds
Started May 12 01:19:36 PM PDT 24
Finished May 12 01:19:51 PM PDT 24
Peak memory 211792 kb
Host smart-1df2e4f8-c770-44e2-ab7c-86695d679558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920032302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3920032302
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3939321738
Short name T182
Test name
Test status
Simulation time 7743599557 ps
CPU time 144.19 seconds
Started May 12 01:19:32 PM PDT 24
Finished May 12 01:21:57 PM PDT 24
Peak memory 225268 kb
Host smart-9bebc1cf-9acc-4111-98ec-f967a46ad71f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939321738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3939321738
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2061647377
Short name T22
Test name
Test status
Simulation time 5693082309 ps
CPU time 52.9 seconds
Started May 12 01:19:32 PM PDT 24
Finished May 12 01:20:26 PM PDT 24
Peak memory 215648 kb
Host smart-cb0d7113-204c-4c42-812d-438a524a9ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061647377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2061647377
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.677533463
Short name T7
Test name
Test status
Simulation time 1081497672 ps
CPU time 10.43 seconds
Started May 12 01:19:32 PM PDT 24
Finished May 12 01:19:43 PM PDT 24
Peak memory 213060 kb
Host smart-c1a2dc19-99c0-47fe-9faa-bc2a12f03261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=677533463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.677533463
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.694952200
Short name T88
Test name
Test status
Simulation time 1670594464 ps
CPU time 25.88 seconds
Started May 12 01:19:34 PM PDT 24
Finished May 12 01:20:01 PM PDT 24
Peak memory 216620 kb
Host smart-22f3f80b-361e-455e-96fc-8846b498d6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694952200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.694952200
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.252176672
Short name T222
Test name
Test status
Simulation time 5485584572 ps
CPU time 92.23 seconds
Started May 12 01:19:32 PM PDT 24
Finished May 12 01:21:06 PM PDT 24
Peak memory 219968 kb
Host smart-d1b295c1-baa6-4389-95ac-edbfd667b2e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252176672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.252176672
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.4201200279
Short name T19
Test name
Test status
Simulation time 34663556922 ps
CPU time 650.28 seconds
Started May 12 01:19:31 PM PDT 24
Finished May 12 01:30:22 PM PDT 24
Peak memory 228652 kb
Host smart-310687e0-9722-41a9-adbe-ffe58ac3d000
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201200279 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.4201200279
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.925378494
Short name T57
Test name
Test status
Simulation time 16047364988 ps
CPU time 33.23 seconds
Started May 12 01:19:36 PM PDT 24
Finished May 12 01:20:09 PM PDT 24
Peak memory 212636 kb
Host smart-4ca20201-db89-4e68-a860-5ac209cd3b81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925378494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.925378494
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1961093000
Short name T321
Test name
Test status
Simulation time 110818579777 ps
CPU time 722.79 seconds
Started May 12 01:19:30 PM PDT 24
Finished May 12 01:31:33 PM PDT 24
Peak memory 239312 kb
Host smart-54b36c9e-b8d5-4f71-9366-32cd6f5de657
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961093000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1961093000
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.4149339191
Short name T291
Test name
Test status
Simulation time 44954177346 ps
CPU time 61.66 seconds
Started May 12 01:19:36 PM PDT 24
Finished May 12 01:20:38 PM PDT 24
Peak memory 214580 kb
Host smart-49daa7fc-d12f-4d15-9684-d35347b3d864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149339191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.4149339191
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1885471992
Short name T205
Test name
Test status
Simulation time 707593190 ps
CPU time 10.46 seconds
Started May 12 01:19:33 PM PDT 24
Finished May 12 01:19:44 PM PDT 24
Peak memory 212904 kb
Host smart-aa0d2558-66e4-469b-8899-2f774a022961
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1885471992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1885471992
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2714342341
Short name T90
Test name
Test status
Simulation time 8919340933 ps
CPU time 80.12 seconds
Started May 12 01:19:31 PM PDT 24
Finished May 12 01:20:51 PM PDT 24
Peak memory 218288 kb
Host smart-cf2ce899-b3c4-4403-a46b-38ec83f80598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714342341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2714342341
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1125735938
Short name T185
Test name
Test status
Simulation time 27530323221 ps
CPU time 84.73 seconds
Started May 12 01:19:35 PM PDT 24
Finished May 12 01:21:00 PM PDT 24
Peak memory 222480 kb
Host smart-1a89ced1-994a-41d7-b3f8-636deb725d2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125735938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1125735938
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3431488351
Short name T38
Test name
Test status
Simulation time 11942900218 ps
CPU time 25.99 seconds
Started May 12 01:19:33 PM PDT 24
Finished May 12 01:20:00 PM PDT 24
Peak memory 212780 kb
Host smart-c68b074b-13b3-4df7-913c-db1353e38cc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431488351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3431488351
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2508448060
Short name T203
Test name
Test status
Simulation time 34344712719 ps
CPU time 541.32 seconds
Started May 12 01:19:35 PM PDT 24
Finished May 12 01:28:36 PM PDT 24
Peak memory 238320 kb
Host smart-93542aba-5e3b-431f-9cea-fed957d42ebd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508448060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2508448060
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3395717136
Short name T179
Test name
Test status
Simulation time 2830522742 ps
CPU time 24.43 seconds
Started May 12 01:19:33 PM PDT 24
Finished May 12 01:19:58 PM PDT 24
Peak memory 214340 kb
Host smart-7c14c31e-d2a4-4397-a18d-4bc7284eaf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395717136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3395717136
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.564764039
Short name T208
Test name
Test status
Simulation time 258663775 ps
CPU time 11.94 seconds
Started May 12 01:19:34 PM PDT 24
Finished May 12 01:19:47 PM PDT 24
Peak memory 211888 kb
Host smart-14f40a76-105b-4d83-b837-a24663c94888
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=564764039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.564764039
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3887041097
Short name T217
Test name
Test status
Simulation time 21998758313 ps
CPU time 35.31 seconds
Started May 12 01:19:32 PM PDT 24
Finished May 12 01:20:08 PM PDT 24
Peak memory 217780 kb
Host smart-1e15e221-5649-457d-8608-27f3b821e524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887041097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3887041097
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.429189291
Short name T310
Test name
Test status
Simulation time 2116850351 ps
CPU time 32.95 seconds
Started May 12 01:19:35 PM PDT 24
Finished May 12 01:20:09 PM PDT 24
Peak memory 219500 kb
Host smart-c52c5f30-a4a3-4763-93dc-3b2b97f43338
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429189291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.429189291
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1971818302
Short name T67
Test name
Test status
Simulation time 332132806 ps
CPU time 8.25 seconds
Started May 12 01:19:37 PM PDT 24
Finished May 12 01:19:46 PM PDT 24
Peak memory 211792 kb
Host smart-14e2e5d2-7f00-4eb2-96c6-d823287187a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971818302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1971818302
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3058348474
Short name T123
Test name
Test status
Simulation time 32033570171 ps
CPU time 290.78 seconds
Started May 12 01:19:36 PM PDT 24
Finished May 12 01:24:28 PM PDT 24
Peak memory 234356 kb
Host smart-55bb2f5c-874f-4b10-ab5f-1e60acb6c2d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058348474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3058348474
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4143787710
Short name T134
Test name
Test status
Simulation time 41633461010 ps
CPU time 70.17 seconds
Started May 12 01:19:34 PM PDT 24
Finished May 12 01:20:45 PM PDT 24
Peak memory 215636 kb
Host smart-8236d73b-458b-4fa0-94da-e739934ce0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143787710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.4143787710
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3433888278
Short name T130
Test name
Test status
Simulation time 2705510289 ps
CPU time 25.27 seconds
Started May 12 01:19:37 PM PDT 24
Finished May 12 01:20:02 PM PDT 24
Peak memory 211852 kb
Host smart-13a08e38-6382-49a4-8e0b-8acab470d49f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3433888278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3433888278
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2911193934
Short name T315
Test name
Test status
Simulation time 4295657305 ps
CPU time 35.13 seconds
Started May 12 01:19:33 PM PDT 24
Finished May 12 01:20:09 PM PDT 24
Peak memory 216412 kb
Host smart-c57abdde-2b6c-46a7-8632-0269951016c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911193934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2911193934
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.4240303396
Short name T195
Test name
Test status
Simulation time 12928992694 ps
CPU time 37.39 seconds
Started May 12 01:19:31 PM PDT 24
Finished May 12 01:20:09 PM PDT 24
Peak memory 214616 kb
Host smart-31f692bd-6d50-405b-b628-78c64822ae56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240303396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.4240303396
Directory /workspace/9.rom_ctrl_stress_all/latest
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