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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.60 96.97 93.01 97.88 100.00 98.37 97.88 99.07


Total test records in report: 462
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T301 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3935033883 May 14 12:56:00 PM PDT 24 May 14 01:02:46 PM PDT 24 99959956357 ps
T302 /workspace/coverage/default/38.rom_ctrl_stress_all.2403969544 May 14 12:56:07 PM PDT 24 May 14 12:58:53 PM PDT 24 18831228467 ps
T303 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4074404240 May 14 12:55:39 PM PDT 24 May 14 12:56:41 PM PDT 24 42536976775 ps
T35 /workspace/coverage/default/2.rom_ctrl_sec_cm.2058970674 May 14 12:55:47 PM PDT 24 May 14 12:58:03 PM PDT 24 2919181542 ps
T304 /workspace/coverage/default/10.rom_ctrl_smoke.2502328080 May 14 12:55:24 PM PDT 24 May 14 12:56:05 PM PDT 24 3305560964 ps
T305 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1708506596 May 14 12:55:22 PM PDT 24 May 14 12:56:34 PM PDT 24 54516492812 ps
T57 /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3587402872 May 14 12:55:57 PM PDT 24 May 14 01:28:03 PM PDT 24 211599891898 ps
T306 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.281394391 May 14 12:56:00 PM PDT 24 May 14 12:56:16 PM PDT 24 1557442192 ps
T307 /workspace/coverage/default/4.rom_ctrl_stress_all.2250639480 May 14 12:55:40 PM PDT 24 May 14 12:56:04 PM PDT 24 2497739827 ps
T308 /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2865817909 May 14 12:56:01 PM PDT 24 May 14 02:13:18 PM PDT 24 222702366886 ps
T309 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2230179857 May 14 12:55:58 PM PDT 24 May 14 12:56:11 PM PDT 24 267552511 ps
T310 /workspace/coverage/default/45.rom_ctrl_smoke.367955979 May 14 12:56:08 PM PDT 24 May 14 12:56:43 PM PDT 24 13501644288 ps
T311 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.570825578 May 14 12:55:42 PM PDT 24 May 14 12:55:54 PM PDT 24 692881637 ps
T312 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2066777700 May 14 12:55:46 PM PDT 24 May 14 12:59:39 PM PDT 24 13580087203 ps
T313 /workspace/coverage/default/3.rom_ctrl_smoke.2774056047 May 14 12:55:20 PM PDT 24 May 14 12:56:14 PM PDT 24 11264368297 ps
T314 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3006107000 May 14 12:55:40 PM PDT 24 May 14 12:59:11 PM PDT 24 8894635680 ps
T315 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.632823838 May 14 12:55:35 PM PDT 24 May 14 12:55:57 PM PDT 24 6440946499 ps
T316 /workspace/coverage/default/49.rom_ctrl_smoke.2073062269 May 14 12:56:08 PM PDT 24 May 14 12:56:45 PM PDT 24 4764072306 ps
T317 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3422902392 May 14 12:55:38 PM PDT 24 May 14 12:56:34 PM PDT 24 9535556402 ps
T318 /workspace/coverage/default/24.rom_ctrl_smoke.3497892777 May 14 12:55:40 PM PDT 24 May 14 12:56:36 PM PDT 24 10619103192 ps
T319 /workspace/coverage/default/22.rom_ctrl_stress_all.1402445974 May 14 12:55:39 PM PDT 24 May 14 01:00:48 PM PDT 24 32203508554 ps
T320 /workspace/coverage/default/33.rom_ctrl_smoke.1082870699 May 14 12:55:46 PM PDT 24 May 14 12:56:39 PM PDT 24 6026854517 ps
T321 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3975588011 May 14 12:55:40 PM PDT 24 May 14 01:00:06 PM PDT 24 16101931055 ps
T322 /workspace/coverage/default/17.rom_ctrl_stress_all.1617169793 May 14 12:55:36 PM PDT 24 May 14 12:57:51 PM PDT 24 57176593720 ps
T323 /workspace/coverage/default/32.rom_ctrl_alert_test.991215806 May 14 12:55:51 PM PDT 24 May 14 12:56:16 PM PDT 24 11033530222 ps
T324 /workspace/coverage/default/9.rom_ctrl_smoke.2654778885 May 14 12:55:33 PM PDT 24 May 14 12:56:00 PM PDT 24 5608377327 ps
T325 /workspace/coverage/default/12.rom_ctrl_stress_all.2705826620 May 14 12:55:45 PM PDT 24 May 14 12:57:08 PM PDT 24 16412547265 ps
T326 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1285412819 May 14 12:55:38 PM PDT 24 May 14 12:56:26 PM PDT 24 4847855390 ps
T327 /workspace/coverage/default/23.rom_ctrl_stress_all.2054629842 May 14 12:55:44 PM PDT 24 May 14 12:56:30 PM PDT 24 561334421 ps
T328 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.784781984 May 14 12:55:44 PM PDT 24 May 14 12:59:30 PM PDT 24 18843321468 ps
T329 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.940671034 May 14 12:55:45 PM PDT 24 May 14 12:55:56 PM PDT 24 693406209 ps
T330 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2397146904 May 14 12:55:18 PM PDT 24 May 14 12:56:23 PM PDT 24 11783890749 ps
T331 /workspace/coverage/default/46.rom_ctrl_stress_all.1334371330 May 14 12:56:08 PM PDT 24 May 14 12:56:46 PM PDT 24 1143095916 ps
T332 /workspace/coverage/default/39.rom_ctrl_smoke.3557099507 May 14 12:55:54 PM PDT 24 May 14 12:56:57 PM PDT 24 6567768502 ps
T333 /workspace/coverage/default/9.rom_ctrl_alert_test.1942186049 May 14 12:55:20 PM PDT 24 May 14 12:55:41 PM PDT 24 6777783714 ps
T334 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3621653816 May 14 12:55:17 PM PDT 24 May 14 12:55:40 PM PDT 24 675330425 ps
T335 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3447100979 May 14 12:55:53 PM PDT 24 May 14 12:56:19 PM PDT 24 2745912335 ps
T18 /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1391695411 May 14 12:55:39 PM PDT 24 May 14 01:19:50 PM PDT 24 37208879829 ps
T336 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2637372274 May 14 12:55:17 PM PDT 24 May 14 12:57:49 PM PDT 24 7041347895 ps
T337 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4213091750 May 14 12:55:50 PM PDT 24 May 14 12:56:27 PM PDT 24 4430291880 ps
T338 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2773139365 May 14 12:56:08 PM PDT 24 May 14 12:56:47 PM PDT 24 2490394806 ps
T339 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1246847763 May 14 12:55:34 PM PDT 24 May 14 12:56:15 PM PDT 24 23434878793 ps
T340 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2316768177 May 14 12:55:28 PM PDT 24 May 14 12:55:48 PM PDT 24 1375602965 ps
T341 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.4004264123 May 14 12:55:53 PM PDT 24 May 14 12:58:39 PM PDT 24 9583693504 ps
T342 /workspace/coverage/default/11.rom_ctrl_stress_all.4089865212 May 14 12:55:36 PM PDT 24 May 14 12:58:49 PM PDT 24 32628756841 ps
T343 /workspace/coverage/default/10.rom_ctrl_alert_test.960784681 May 14 12:55:42 PM PDT 24 May 14 12:55:52 PM PDT 24 687804528 ps
T344 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3267661290 May 14 12:55:51 PM PDT 24 May 14 12:56:04 PM PDT 24 185927442 ps
T345 /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1631096909 May 14 12:56:06 PM PDT 24 May 14 01:09:32 PM PDT 24 21664240583 ps
T346 /workspace/coverage/default/41.rom_ctrl_stress_all.2741817210 May 14 12:56:07 PM PDT 24 May 14 12:57:19 PM PDT 24 7530886411 ps
T347 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1327089530 May 14 12:55:38 PM PDT 24 May 14 12:56:10 PM PDT 24 13001165440 ps
T348 /workspace/coverage/default/13.rom_ctrl_smoke.1516297881 May 14 12:55:32 PM PDT 24 May 14 12:56:48 PM PDT 24 23163898048 ps
T349 /workspace/coverage/default/42.rom_ctrl_stress_all.912221645 May 14 12:56:03 PM PDT 24 May 14 12:56:59 PM PDT 24 1777739754 ps
T350 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2318980330 May 14 12:56:06 PM PDT 24 May 14 01:00:37 PM PDT 24 89200533702 ps
T351 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2490167475 May 14 12:56:00 PM PDT 24 May 14 12:56:47 PM PDT 24 18441025279 ps
T352 /workspace/coverage/default/33.rom_ctrl_stress_all.3934454169 May 14 12:55:50 PM PDT 24 May 14 12:56:37 PM PDT 24 17210753421 ps
T353 /workspace/coverage/default/15.rom_ctrl_smoke.249322471 May 14 12:55:37 PM PDT 24 May 14 12:56:00 PM PDT 24 341825678 ps
T354 /workspace/coverage/default/26.rom_ctrl_alert_test.3042709119 May 14 12:55:45 PM PDT 24 May 14 12:56:14 PM PDT 24 34463947205 ps
T355 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3321558941 May 14 12:55:46 PM PDT 24 May 14 01:03:21 PM PDT 24 142191378913 ps
T356 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3264300429 May 14 12:55:57 PM PDT 24 May 14 12:58:33 PM PDT 24 8415893980 ps
T357 /workspace/coverage/default/39.rom_ctrl_alert_test.2052589731 May 14 12:56:06 PM PDT 24 May 14 12:56:42 PM PDT 24 16045628869 ps
T358 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.550689932 May 14 12:55:47 PM PDT 24 May 14 12:56:16 PM PDT 24 11093923571 ps
T359 /workspace/coverage/default/14.rom_ctrl_stress_all.901903909 May 14 12:55:39 PM PDT 24 May 14 12:57:42 PM PDT 24 46683332165 ps
T360 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1114234214 May 14 12:56:05 PM PDT 24 May 14 12:57:16 PM PDT 24 32107495682 ps
T361 /workspace/coverage/default/47.rom_ctrl_stress_all.3032913066 May 14 12:56:07 PM PDT 24 May 14 12:57:20 PM PDT 24 13211805731 ps
T362 /workspace/coverage/default/29.rom_ctrl_alert_test.1065914581 May 14 12:55:47 PM PDT 24 May 14 12:56:11 PM PDT 24 2294941001 ps
T363 /workspace/coverage/default/45.rom_ctrl_alert_test.422699992 May 14 12:56:12 PM PDT 24 May 14 12:56:30 PM PDT 24 2250027013 ps
T364 /workspace/coverage/default/38.rom_ctrl_alert_test.1548263921 May 14 12:55:51 PM PDT 24 May 14 12:56:06 PM PDT 24 1377233758 ps
T61 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.238133069 May 14 12:56:40 PM PDT 24 May 14 12:56:53 PM PDT 24 179984011 ps
T62 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3019899212 May 14 12:56:10 PM PDT 24 May 14 12:57:09 PM PDT 24 1948908458 ps
T63 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3891625465 May 14 12:56:10 PM PDT 24 May 14 12:57:56 PM PDT 24 21279542784 ps
T365 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1234260784 May 14 12:56:21 PM PDT 24 May 14 12:56:38 PM PDT 24 1424247148 ps
T99 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4095751518 May 14 12:56:33 PM PDT 24 May 14 12:57:06 PM PDT 24 17109365983 ps
T366 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1105707803 May 14 12:56:14 PM PDT 24 May 14 12:56:23 PM PDT 24 174353513 ps
T58 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1429164696 May 14 12:56:26 PM PDT 24 May 14 12:59:08 PM PDT 24 1691609902 ps
T367 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3380933537 May 14 12:56:34 PM PDT 24 May 14 12:57:01 PM PDT 24 11718067209 ps
T59 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4089684912 May 14 12:56:42 PM PDT 24 May 14 12:58:22 PM PDT 24 14250039279 ps
T95 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3282378582 May 14 12:56:10 PM PDT 24 May 14 12:56:36 PM PDT 24 2420667198 ps
T368 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4106784914 May 14 12:56:35 PM PDT 24 May 14 12:56:52 PM PDT 24 1023248963 ps
T369 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1689660631 May 14 12:56:33 PM PDT 24 May 14 12:56:53 PM PDT 24 2292864207 ps
T370 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2860667409 May 14 12:56:27 PM PDT 24 May 14 12:56:50 PM PDT 24 2414261784 ps
T371 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.550088225 May 14 12:56:07 PM PDT 24 May 14 12:56:22 PM PDT 24 168971838 ps
T67 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.6844770 May 14 12:56:39 PM PDT 24 May 14 12:57:13 PM PDT 24 4758028198 ps
T60 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.991423205 May 14 12:56:26 PM PDT 24 May 14 12:59:06 PM PDT 24 1212782474 ps
T372 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1177171675 May 14 12:56:09 PM PDT 24 May 14 12:56:42 PM PDT 24 5755194472 ps
T68 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.972902427 May 14 12:56:33 PM PDT 24 May 14 12:58:09 PM PDT 24 10362588203 ps
T69 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1524453687 May 14 12:56:26 PM PDT 24 May 14 12:56:38 PM PDT 24 1130979317 ps
T70 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1855302835 May 14 12:56:32 PM PDT 24 May 14 12:56:53 PM PDT 24 8833813947 ps
T100 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1164754200 May 14 12:56:11 PM PDT 24 May 14 12:56:24 PM PDT 24 2743633685 ps
T71 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2046114141 May 14 12:56:33 PM PDT 24 May 14 12:57:01 PM PDT 24 3289944273 ps
T373 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3281393532 May 14 12:56:22 PM PDT 24 May 14 12:56:41 PM PDT 24 1324897341 ps
T96 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2721106946 May 14 12:56:34 PM PDT 24 May 14 12:56:47 PM PDT 24 503602758 ps
T374 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3800786558 May 14 12:56:42 PM PDT 24 May 14 12:57:23 PM PDT 24 19898402674 ps
T97 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.851794165 May 14 12:56:27 PM PDT 24 May 14 12:56:48 PM PDT 24 18029756802 ps
T375 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.312300252 May 14 12:56:35 PM PDT 24 May 14 12:56:49 PM PDT 24 506195475 ps
T104 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2475411861 May 14 12:56:44 PM PDT 24 May 14 12:59:17 PM PDT 24 342376068 ps
T105 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2436945617 May 14 12:56:08 PM PDT 24 May 14 12:58:57 PM PDT 24 2224097871 ps
T72 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1791358409 May 14 12:56:32 PM PDT 24 May 14 12:56:42 PM PDT 24 477366776 ps
T73 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2807180128 May 14 12:56:35 PM PDT 24 May 14 12:57:02 PM PDT 24 4120353652 ps
T108 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.158595312 May 14 12:56:02 PM PDT 24 May 14 12:58:53 PM PDT 24 7708119124 ps
T74 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.237407746 May 14 12:56:40 PM PDT 24 May 14 12:59:32 PM PDT 24 78098081785 ps
T376 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.158794761 May 14 12:56:05 PM PDT 24 May 14 12:56:35 PM PDT 24 11861807465 ps
T377 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2486165359 May 14 12:56:08 PM PDT 24 May 14 12:56:59 PM PDT 24 2810177769 ps
T98 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.472706454 May 14 12:56:41 PM PDT 24 May 14 12:56:59 PM PDT 24 3622286145 ps
T378 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3524541451 May 14 12:56:33 PM PDT 24 May 14 12:56:59 PM PDT 24 2994085204 ps
T109 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3318234386 May 14 12:56:34 PM PDT 24 May 14 12:59:21 PM PDT 24 5003562602 ps
T379 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.798148387 May 14 12:56:25 PM PDT 24 May 14 12:56:52 PM PDT 24 10668458426 ps
T75 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2537982405 May 14 12:56:33 PM PDT 24 May 14 12:58:20 PM PDT 24 12347133189 ps
T380 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2580160612 May 14 12:56:07 PM PDT 24 May 14 12:56:35 PM PDT 24 2660253512 ps
T381 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2247945827 May 14 12:56:09 PM PDT 24 May 14 12:56:41 PM PDT 24 7237745995 ps
T382 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.169488190 May 14 12:56:27 PM PDT 24 May 14 12:56:52 PM PDT 24 2588878410 ps
T82 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3091385279 May 14 12:56:13 PM PDT 24 May 14 12:56:47 PM PDT 24 17065912737 ps
T383 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3847194163 May 14 12:56:34 PM PDT 24 May 14 12:56:47 PM PDT 24 341463579 ps
T384 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2573193220 May 14 12:56:16 PM PDT 24 May 14 12:56:42 PM PDT 24 2716094327 ps
T385 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3791067715 May 14 12:56:33 PM PDT 24 May 14 12:57:38 PM PDT 24 8440437283 ps
T386 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1685370345 May 14 12:56:34 PM PDT 24 May 14 12:56:46 PM PDT 24 660625246 ps
T387 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3812838747 May 14 12:56:26 PM PDT 24 May 14 12:56:58 PM PDT 24 3391575060 ps
T388 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3687881866 May 14 12:56:41 PM PDT 24 May 14 12:57:05 PM PDT 24 6408216354 ps
T83 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3398396748 May 14 12:56:26 PM PDT 24 May 14 12:58:23 PM PDT 24 37618670984 ps
T389 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2011836292 May 14 12:56:27 PM PDT 24 May 14 12:57:01 PM PDT 24 9140384709 ps
T84 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.670822421 May 14 12:56:07 PM PDT 24 May 14 12:56:41 PM PDT 24 23699357364 ps
T390 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1418560802 May 14 12:56:20 PM PDT 24 May 14 12:57:58 PM PDT 24 12617016942 ps
T85 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2071412492 May 14 12:56:20 PM PDT 24 May 14 12:56:30 PM PDT 24 661467835 ps
T391 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1293441087 May 14 12:56:07 PM PDT 24 May 14 12:56:31 PM PDT 24 15079143683 ps
T392 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.99493513 May 14 12:56:12 PM PDT 24 May 14 12:56:49 PM PDT 24 13132909055 ps
T393 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1249858533 May 14 12:56:13 PM PDT 24 May 14 12:56:23 PM PDT 24 1833912049 ps
T394 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.608189371 May 14 12:56:12 PM PDT 24 May 14 12:56:32 PM PDT 24 3273994981 ps
T86 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.702890378 May 14 12:56:03 PM PDT 24 May 14 12:56:44 PM PDT 24 2853130728 ps
T87 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1831614169 May 14 12:56:41 PM PDT 24 May 14 12:58:58 PM PDT 24 69531579294 ps
T395 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.946361910 May 14 12:56:21 PM PDT 24 May 14 12:56:38 PM PDT 24 4266629718 ps
T396 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1512705223 May 14 12:56:18 PM PDT 24 May 14 12:59:10 PM PDT 24 9095112389 ps
T397 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.362270232 May 14 12:56:33 PM PDT 24 May 14 12:56:45 PM PDT 24 2246693521 ps
T398 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3555927230 May 14 12:56:17 PM PDT 24 May 14 12:56:28 PM PDT 24 385384709 ps
T399 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4081558874 May 14 12:56:11 PM PDT 24 May 14 12:56:29 PM PDT 24 4256345223 ps
T400 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.486026620 May 14 12:56:06 PM PDT 24 May 14 12:56:30 PM PDT 24 6410943289 ps
T401 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1974640009 May 14 12:56:32 PM PDT 24 May 14 12:56:49 PM PDT 24 2227926046 ps
T402 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.526406556 May 14 12:56:34 PM PDT 24 May 14 12:57:08 PM PDT 24 13265056737 ps
T403 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1173688029 May 14 12:56:42 PM PDT 24 May 14 12:56:54 PM PDT 24 661829461 ps
T404 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.158740848 May 14 12:56:15 PM PDT 24 May 14 12:56:35 PM PDT 24 1984643316 ps
T405 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.17504574 May 14 12:56:06 PM PDT 24 May 14 12:56:39 PM PDT 24 8789265227 ps
T88 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.397128259 May 14 12:56:04 PM PDT 24 May 14 12:56:22 PM PDT 24 1182461509 ps
T406 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2505140662 May 14 12:56:21 PM PDT 24 May 14 12:56:46 PM PDT 24 5395900153 ps
T407 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3183639962 May 14 12:56:18 PM PDT 24 May 14 12:56:47 PM PDT 24 3611191082 ps
T408 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2666585123 May 14 12:56:40 PM PDT 24 May 14 12:57:12 PM PDT 24 9251627616 ps
T409 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2019996321 May 14 12:56:28 PM PDT 24 May 14 12:57:52 PM PDT 24 1011051240 ps
T410 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4032356842 May 14 12:56:12 PM PDT 24 May 14 12:56:47 PM PDT 24 20819433174 ps
T411 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1637609016 May 14 12:56:42 PM PDT 24 May 14 12:57:24 PM PDT 24 1435322096 ps
T412 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3831574883 May 14 12:56:45 PM PDT 24 May 14 12:57:16 PM PDT 24 7714584712 ps
T413 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.237038378 May 14 12:56:19 PM PDT 24 May 14 12:56:36 PM PDT 24 1236871034 ps
T414 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2145451708 May 14 12:56:28 PM PDT 24 May 14 12:56:38 PM PDT 24 345303614 ps
T113 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.130259096 May 14 12:56:32 PM PDT 24 May 14 12:59:12 PM PDT 24 1445603685 ps
T91 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2125411159 May 14 12:56:06 PM PDT 24 May 14 12:56:46 PM PDT 24 17366453094 ps
T115 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3051253925 May 14 12:56:40 PM PDT 24 May 14 12:58:07 PM PDT 24 411988759 ps
T415 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4210797004 May 14 12:56:07 PM PDT 24 May 14 12:56:41 PM PDT 24 3524205875 ps
T416 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1517973645 May 14 12:56:07 PM PDT 24 May 14 12:56:42 PM PDT 24 4039414782 ps
T417 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1298342924 May 14 12:56:17 PM PDT 24 May 14 12:56:37 PM PDT 24 1916063427 ps
T418 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.697957222 May 14 12:56:09 PM PDT 24 May 14 12:56:48 PM PDT 24 4421811030 ps
T114 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1179952003 May 14 12:56:32 PM PDT 24 May 14 12:58:15 PM PDT 24 7934061453 ps
T419 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2415602070 May 14 12:56:20 PM PDT 24 May 14 12:56:34 PM PDT 24 2899306827 ps
T106 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1140557813 May 14 12:56:06 PM PDT 24 May 14 12:57:49 PM PDT 24 32589510489 ps
T420 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2833841239 May 14 12:56:39 PM PDT 24 May 14 12:57:10 PM PDT 24 6742329507 ps
T421 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3654341547 May 14 12:56:43 PM PDT 24 May 14 12:57:10 PM PDT 24 14866938833 ps
T92 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4055061347 May 14 12:56:03 PM PDT 24 May 14 12:56:31 PM PDT 24 2866373431 ps
T422 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3289200792 May 14 12:56:19 PM PDT 24 May 14 12:56:49 PM PDT 24 2904619264 ps
T93 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4176197533 May 14 12:56:29 PM PDT 24 May 14 12:57:51 PM PDT 24 30230474440 ps
T423 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2724266407 May 14 12:56:25 PM PDT 24 May 14 12:57:02 PM PDT 24 16464394367 ps
T424 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2965966607 May 14 12:56:28 PM PDT 24 May 14 12:56:49 PM PDT 24 3663573585 ps
T94 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1033951754 May 14 12:56:11 PM PDT 24 May 14 12:57:30 PM PDT 24 41606689572 ps
T425 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1824748307 May 14 12:56:46 PM PDT 24 May 14 12:57:19 PM PDT 24 35954872267 ps
T426 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.210616636 May 14 12:56:28 PM PDT 24 May 14 12:56:41 PM PDT 24 2726167875 ps
T427 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2769251038 May 14 12:56:09 PM PDT 24 May 14 12:56:21 PM PDT 24 570012523 ps
T428 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1460113060 May 14 12:56:11 PM PDT 24 May 14 12:56:22 PM PDT 24 172668823 ps
T429 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.211753105 May 14 12:56:06 PM PDT 24 May 14 12:56:17 PM PDT 24 176035745 ps
T116 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1191275962 May 14 12:56:40 PM PDT 24 May 14 12:59:27 PM PDT 24 1913868598 ps
T110 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3611792271 May 14 12:56:33 PM PDT 24 May 14 12:59:05 PM PDT 24 1215763155 ps
T430 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3820165956 May 14 12:56:08 PM PDT 24 May 14 12:56:38 PM PDT 24 7589149285 ps
T89 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.918588171 May 14 12:56:42 PM PDT 24 May 14 12:57:31 PM PDT 24 5363819755 ps
T431 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1234304915 May 14 12:56:09 PM PDT 24 May 14 12:56:44 PM PDT 24 4050549893 ps
T432 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1421507903 May 14 12:56:18 PM PDT 24 May 14 12:57:37 PM PDT 24 12072817304 ps
T433 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2746282249 May 14 12:56:27 PM PDT 24 May 14 12:56:51 PM PDT 24 2359028354 ps
T90 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2749620697 May 14 12:56:27 PM PDT 24 May 14 12:57:42 PM PDT 24 24336172369 ps
T434 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2328143301 May 14 12:56:19 PM PDT 24 May 14 12:57:45 PM PDT 24 1765878982 ps
T435 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.586721205 May 14 12:56:11 PM PDT 24 May 14 12:56:26 PM PDT 24 180060232 ps
T112 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.750918360 May 14 12:56:03 PM PDT 24 May 14 12:57:25 PM PDT 24 894561191 ps
T436 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3938572845 May 14 12:56:22 PM PDT 24 May 14 12:56:59 PM PDT 24 14903313746 ps
T107 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1124380085 May 14 12:56:16 PM PDT 24 May 14 12:59:04 PM PDT 24 39343450878 ps
T437 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1260890090 May 14 12:56:34 PM PDT 24 May 14 12:56:56 PM PDT 24 5286504401 ps
T438 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1007400038 May 14 12:56:17 PM PDT 24 May 14 12:56:36 PM PDT 24 3101980909 ps
T439 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.768738506 May 14 12:56:10 PM PDT 24 May 14 12:56:34 PM PDT 24 2137157655 ps
T440 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1701187503 May 14 12:56:40 PM PDT 24 May 14 12:57:02 PM PDT 24 851898857 ps
T441 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.505410349 May 14 12:56:16 PM PDT 24 May 14 12:56:43 PM PDT 24 12450758282 ps
T442 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.354425897 May 14 12:56:10 PM PDT 24 May 14 12:56:21 PM PDT 24 689636213 ps
T443 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1866491717 May 14 12:56:12 PM PDT 24 May 14 12:56:29 PM PDT 24 181399766 ps
T444 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2455379410 May 14 12:56:27 PM PDT 24 May 14 12:56:46 PM PDT 24 5290826346 ps
T445 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2389221911 May 14 12:56:45 PM PDT 24 May 14 12:56:55 PM PDT 24 2354265186 ps
T446 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1723528033 May 14 12:56:17 PM PDT 24 May 14 12:56:34 PM PDT 24 5791074243 ps
T447 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1556350901 May 14 12:56:32 PM PDT 24 May 14 12:56:54 PM PDT 24 9205432064 ps
T448 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.609079074 May 14 12:56:26 PM PDT 24 May 14 12:56:49 PM PDT 24 2163857262 ps
T449 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2365083873 May 14 12:56:33 PM PDT 24 May 14 12:57:31 PM PDT 24 1039075568 ps
T450 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3709493243 May 14 12:56:09 PM PDT 24 May 14 12:56:35 PM PDT 24 17236890138 ps
T451 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1375776921 May 14 12:56:33 PM PDT 24 May 14 12:56:53 PM PDT 24 1720878895 ps
T452 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3941656708 May 14 12:56:29 PM PDT 24 May 14 12:58:50 PM PDT 24 109911820582 ps
T453 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1011669952 May 14 12:56:13 PM PDT 24 May 14 12:56:32 PM PDT 24 5450868221 ps
T454 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.928590475 May 14 12:56:33 PM PDT 24 May 14 12:56:58 PM PDT 24 8265838427 ps
T111 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1250942223 May 14 12:56:33 PM PDT 24 May 14 12:58:16 PM PDT 24 4240857109 ps
T455 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2989979923 May 14 12:56:28 PM PDT 24 May 14 12:57:00 PM PDT 24 8060350830 ps
T456 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2886972468 May 14 12:56:40 PM PDT 24 May 14 12:57:11 PM PDT 24 12611288506 ps
T457 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.786890833 May 14 12:56:12 PM PDT 24 May 14 12:56:23 PM PDT 24 376727709 ps
T458 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3518215043 May 14 12:56:14 PM PDT 24 May 14 12:56:28 PM PDT 24 174319637 ps
T459 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2384580500 May 14 12:56:39 PM PDT 24 May 14 12:57:12 PM PDT 24 3694801369 ps
T460 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3767563289 May 14 12:56:41 PM PDT 24 May 14 12:57:18 PM PDT 24 29789516949 ps
T461 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2478420994 May 14 12:56:34 PM PDT 24 May 14 12:58:10 PM PDT 24 5257926575 ps
T462 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.347384060 May 14 12:56:19 PM PDT 24 May 14 12:58:10 PM PDT 24 18565867276 ps

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.970669164
Short name T3
Test name
Test status
Simulation time 23165307457 ps
CPU time 964.02 seconds
Started May 14 12:55:38 PM PDT 24
Finished May 14 01:11:45 PM PDT 24
Peak memory 232304 kb
Host smart-5e16e601-6bd1-4d22-9d9c-35582eac00b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970669164 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.970669164
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.601091569
Short name T25
Test name
Test status
Simulation time 21170104908 ps
CPU time 317.54 seconds
Started May 14 12:55:48 PM PDT 24
Finished May 14 01:01:07 PM PDT 24
Peak memory 229236 kb
Host smart-3e4f6683-21cb-4852-b97e-44d944f43054
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601091569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.601091569
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.257661940
Short name T5
Test name
Test status
Simulation time 4589647880 ps
CPU time 46.17 seconds
Started May 14 12:56:09 PM PDT 24
Finished May 14 12:56:59 PM PDT 24
Peak memory 215172 kb
Host smart-018c4686-3b8f-4c90-a598-bd6ec7a30e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257661940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.257661940
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1429164696
Short name T58
Test name
Test status
Simulation time 1691609902 ps
CPU time 160.32 seconds
Started May 14 12:56:26 PM PDT 24
Finished May 14 12:59:08 PM PDT 24
Peak memory 213556 kb
Host smart-e9f6e327-e275-43e6-849e-41369fac147e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429164696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1429164696
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2395476918
Short name T24
Test name
Test status
Simulation time 101386652953 ps
CPU time 612.7 seconds
Started May 14 12:56:05 PM PDT 24
Finished May 14 01:06:20 PM PDT 24
Peak memory 217976 kb
Host smart-67283390-1c0c-4280-8942-7fbc1e17399a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395476918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2395476918
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3244920061
Short name T6
Test name
Test status
Simulation time 26753950383 ps
CPU time 142.1 seconds
Started May 14 12:55:49 PM PDT 24
Finished May 14 12:58:13 PM PDT 24
Peak memory 219584 kb
Host smart-3e1b6c66-8728-475b-b593-29705e72360a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244920061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3244920061
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1424366438
Short name T29
Test name
Test status
Simulation time 1392646343 ps
CPU time 240.28 seconds
Started May 14 12:55:41 PM PDT 24
Finished May 14 12:59:43 PM PDT 24
Peak memory 239188 kb
Host smart-f2c625b2-aa18-4e43-ba6e-67cce64d7982
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424366438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1424366438
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2527041692
Short name T11
Test name
Test status
Simulation time 29552871007 ps
CPU time 9750.6 seconds
Started May 14 12:55:28 PM PDT 24
Finished May 14 03:38:00 PM PDT 24
Peak memory 233536 kb
Host smart-a3bada60-884a-4c72-9793-6dd220fb198d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527041692 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2527041692
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2046114141
Short name T71
Test name
Test status
Simulation time 3289944273 ps
CPU time 26.92 seconds
Started May 14 12:56:33 PM PDT 24
Finished May 14 12:57:01 PM PDT 24
Peak memory 210824 kb
Host smart-268a3acb-20ad-4789-b61c-2708ab69f4a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046114141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2046114141
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3318234386
Short name T109
Test name
Test status
Simulation time 5003562602 ps
CPU time 165.32 seconds
Started May 14 12:56:34 PM PDT 24
Finished May 14 12:59:21 PM PDT 24
Peak memory 213908 kb
Host smart-21442530-8dae-45cd-a783-c2c14eb1ffc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318234386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3318234386
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2429551428
Short name T33
Test name
Test status
Simulation time 11498207072 ps
CPU time 26.89 seconds
Started May 14 12:55:23 PM PDT 24
Finished May 14 12:55:51 PM PDT 24
Peak memory 212264 kb
Host smart-846689e0-3ef9-4433-aea4-e77b361e5b50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429551428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2429551428
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2537982405
Short name T75
Test name
Test status
Simulation time 12347133189 ps
CPU time 106.18 seconds
Started May 14 12:56:33 PM PDT 24
Finished May 14 12:58:20 PM PDT 24
Peak memory 215024 kb
Host smart-f12db191-d021-48be-b719-2c8889ae1eee
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537982405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2537982405
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3621653816
Short name T334
Test name
Test status
Simulation time 675330425 ps
CPU time 19.11 seconds
Started May 14 12:55:17 PM PDT 24
Finished May 14 12:55:40 PM PDT 24
Peak memory 214640 kb
Host smart-2634749d-b291-4d51-8bb6-362eca213298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621653816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3621653816
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2436945617
Short name T105
Test name
Test status
Simulation time 2224097871 ps
CPU time 165.55 seconds
Started May 14 12:56:08 PM PDT 24
Finished May 14 12:58:57 PM PDT 24
Peak memory 213716 kb
Host smart-18824f21-dd91-44d9-a886-3da6d9cd8b2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436945617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2436945617
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2486165359
Short name T377
Test name
Test status
Simulation time 2810177769 ps
CPU time 47.55 seconds
Started May 14 12:56:08 PM PDT 24
Finished May 14 12:56:59 PM PDT 24
Peak memory 213996 kb
Host smart-9761b950-97fa-4699-b899-2125125d27f2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486165359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2486165359
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.991423205
Short name T60
Test name
Test status
Simulation time 1212782474 ps
CPU time 157.99 seconds
Started May 14 12:56:26 PM PDT 24
Finished May 14 12:59:06 PM PDT 24
Peak memory 219016 kb
Host smart-f35195b9-8f09-447f-8575-17cf4ffc47d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991423205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.991423205
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2475411861
Short name T104
Test name
Test status
Simulation time 342376068 ps
CPU time 150.87 seconds
Started May 14 12:56:44 PM PDT 24
Finished May 14 12:59:17 PM PDT 24
Peak memory 219056 kb
Host smart-106df63c-a332-434f-a392-a6648c54205d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475411861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2475411861
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2544509578
Short name T134
Test name
Test status
Simulation time 185563127 ps
CPU time 10.3 seconds
Started May 14 12:55:42 PM PDT 24
Finished May 14 12:55:54 PM PDT 24
Peak memory 212172 kb
Host smart-f23af200-2d06-4262-be37-50f3158e5110
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2544509578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2544509578
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1391695411
Short name T18
Test name
Test status
Simulation time 37208879829 ps
CPU time 1448.56 seconds
Started May 14 12:55:39 PM PDT 24
Finished May 14 01:19:50 PM PDT 24
Peak memory 234360 kb
Host smart-876b04a1-9dfb-4d32-bd04-693508259963
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391695411 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.1391695411
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.670822421
Short name T84
Test name
Test status
Simulation time 23699357364 ps
CPU time 30.95 seconds
Started May 14 12:56:07 PM PDT 24
Finished May 14 12:56:41 PM PDT 24
Peak memory 219064 kb
Host smart-9383a0e4-c3bc-4ad8-96ba-ac8935546bc5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670822421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.670822421
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1293441087
Short name T391
Test name
Test status
Simulation time 15079143683 ps
CPU time 19.75 seconds
Started May 14 12:56:07 PM PDT 24
Finished May 14 12:56:31 PM PDT 24
Peak memory 218972 kb
Host smart-a5870d25-53ad-41b6-b40e-38c506f7249d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293441087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1293441087
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.697957222
Short name T418
Test name
Test status
Simulation time 4421811030 ps
CPU time 35.66 seconds
Started May 14 12:56:09 PM PDT 24
Finished May 14 12:56:48 PM PDT 24
Peak memory 211424 kb
Host smart-bf438d41-2824-4e14-b276-f501e52e6791
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697957222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.697957222
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1177171675
Short name T372
Test name
Test status
Simulation time 5755194472 ps
CPU time 30.06 seconds
Started May 14 12:56:09 PM PDT 24
Finished May 14 12:56:42 PM PDT 24
Peak memory 214580 kb
Host smart-986ceeff-27a8-4770-8988-cd1aa97850b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177171675 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1177171675
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1517973645
Short name T416
Test name
Test status
Simulation time 4039414782 ps
CPU time 31.59 seconds
Started May 14 12:56:07 PM PDT 24
Finished May 14 12:56:42 PM PDT 24
Peak memory 211500 kb
Host smart-046328cd-baf7-41d1-9b5b-871b6cb843ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517973645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1517973645
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2769251038
Short name T427
Test name
Test status
Simulation time 570012523 ps
CPU time 7.7 seconds
Started May 14 12:56:09 PM PDT 24
Finished May 14 12:56:21 PM PDT 24
Peak memory 210752 kb
Host smart-f1bb067e-f4da-48dc-8174-e2836fe063f3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769251038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2769251038
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.486026620
Short name T400
Test name
Test status
Simulation time 6410943289 ps
CPU time 20.4 seconds
Started May 14 12:56:06 PM PDT 24
Finished May 14 12:56:30 PM PDT 24
Peak memory 210760 kb
Host smart-1d5bd329-f03c-4e43-a585-be3840e55648
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486026620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
486026620
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3019899212
Short name T62
Test name
Test status
Simulation time 1948908458 ps
CPU time 56.04 seconds
Started May 14 12:56:10 PM PDT 24
Finished May 14 12:57:09 PM PDT 24
Peak memory 214124 kb
Host smart-553ff16e-326b-4ebe-aed4-7570607a458b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019899212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3019899212
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.17504574
Short name T405
Test name
Test status
Simulation time 8789265227 ps
CPU time 28.99 seconds
Started May 14 12:56:06 PM PDT 24
Finished May 14 12:56:39 PM PDT 24
Peak memory 212216 kb
Host smart-682c994f-33ad-448e-b12d-5445b500f0ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17504574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_same_csr_outstanding.17504574
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1298342924
Short name T417
Test name
Test status
Simulation time 1916063427 ps
CPU time 19.2 seconds
Started May 14 12:56:17 PM PDT 24
Finished May 14 12:56:37 PM PDT 24
Peak memory 218260 kb
Host smart-ccbae2e1-2acc-4b99-a25f-61057fa89f95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298342924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1298342924
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.750918360
Short name T112
Test name
Test status
Simulation time 894561191 ps
CPU time 79.73 seconds
Started May 14 12:56:03 PM PDT 24
Finished May 14 12:57:25 PM PDT 24
Peak memory 212256 kb
Host smart-5f9db5a6-373f-4370-b246-4def357fb322
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750918360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.750918360
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.397128259
Short name T88
Test name
Test status
Simulation time 1182461509 ps
CPU time 15.65 seconds
Started May 14 12:56:04 PM PDT 24
Finished May 14 12:56:22 PM PDT 24
Peak memory 210896 kb
Host smart-dcc3eba5-b260-48e5-bffa-7479954a1df2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397128259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.397128259
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4032356842
Short name T410
Test name
Test status
Simulation time 20819433174 ps
CPU time 32.96 seconds
Started May 14 12:56:12 PM PDT 24
Finished May 14 12:56:47 PM PDT 24
Peak memory 219068 kb
Host smart-528bad0a-8f4f-455e-a1fc-d977004f15b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032356842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4032356842
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2125411159
Short name T91
Test name
Test status
Simulation time 17366453094 ps
CPU time 36.04 seconds
Started May 14 12:56:06 PM PDT 24
Finished May 14 12:56:46 PM PDT 24
Peak memory 211540 kb
Host smart-e33a3360-b594-46f9-9006-aed19e0569f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125411159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2125411159
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3555927230
Short name T398
Test name
Test status
Simulation time 385384709 ps
CPU time 9.66 seconds
Started May 14 12:56:17 PM PDT 24
Finished May 14 12:56:28 PM PDT 24
Peak memory 219136 kb
Host smart-a7605009-6422-4d59-a2af-191d46d5df8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555927230 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3555927230
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4055061347
Short name T92
Test name
Test status
Simulation time 2866373431 ps
CPU time 25.08 seconds
Started May 14 12:56:03 PM PDT 24
Finished May 14 12:56:31 PM PDT 24
Peak memory 210856 kb
Host smart-ee81f35f-b68c-4bbf-a061-d80c735f4129
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055061347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4055061347
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.211753105
Short name T429
Test name
Test status
Simulation time 176035745 ps
CPU time 7.7 seconds
Started May 14 12:56:06 PM PDT 24
Finished May 14 12:56:17 PM PDT 24
Peak memory 210692 kb
Host smart-a95e7b25-3ebe-4fc0-9e47-ec73692a3f6c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211753105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.211753105
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2247945827
Short name T381
Test name
Test status
Simulation time 7237745995 ps
CPU time 29.42 seconds
Started May 14 12:56:09 PM PDT 24
Finished May 14 12:56:41 PM PDT 24
Peak memory 210872 kb
Host smart-b34ba40e-f127-4283-bd41-0d407cf095f5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247945827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2247945827
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.505410349
Short name T441
Test name
Test status
Simulation time 12450758282 ps
CPU time 25.99 seconds
Started May 14 12:56:16 PM PDT 24
Finished May 14 12:56:43 PM PDT 24
Peak memory 212180 kb
Host smart-5971cff8-2528-4b76-bac6-898c9a54e383
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505410349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.505410349
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.99493513
Short name T392
Test name
Test status
Simulation time 13132909055 ps
CPU time 34.35 seconds
Started May 14 12:56:12 PM PDT 24
Finished May 14 12:56:49 PM PDT 24
Peak memory 218600 kb
Host smart-1b998d41-02c5-4ec2-a788-f445a90a90ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99493513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.99493513
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2746282249
Short name T433
Test name
Test status
Simulation time 2359028354 ps
CPU time 23.41 seconds
Started May 14 12:56:27 PM PDT 24
Finished May 14 12:56:51 PM PDT 24
Peak memory 217264 kb
Host smart-5faddaf3-e810-4142-b172-ee08bf142620
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746282249 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2746282249
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4176197533
Short name T93
Test name
Test status
Simulation time 30230474440 ps
CPU time 80.4 seconds
Started May 14 12:56:29 PM PDT 24
Finished May 14 12:57:51 PM PDT 24
Peak memory 214124 kb
Host smart-33726381-364b-4f2c-9afa-ca7fecf5818d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176197533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.4176197533
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2965966607
Short name T424
Test name
Test status
Simulation time 3663573585 ps
CPU time 19.77 seconds
Started May 14 12:56:28 PM PDT 24
Finished May 14 12:56:49 PM PDT 24
Peak memory 211444 kb
Host smart-f9676371-13b5-4925-9aee-9d5fbc0e6ccb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965966607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2965966607
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3812838747
Short name T387
Test name
Test status
Simulation time 3391575060 ps
CPU time 30.81 seconds
Started May 14 12:56:26 PM PDT 24
Finished May 14 12:56:58 PM PDT 24
Peak memory 219192 kb
Host smart-7cac9b5b-adec-441f-b896-2b088c362314
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812838747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3812838747
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.312300252
Short name T375
Test name
Test status
Simulation time 506195475 ps
CPU time 12.46 seconds
Started May 14 12:56:35 PM PDT 24
Finished May 14 12:56:49 PM PDT 24
Peak memory 216972 kb
Host smart-0d4abcd8-5f22-4fe5-b5de-edd858809795
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312300252 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.312300252
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1524453687
Short name T69
Test name
Test status
Simulation time 1130979317 ps
CPU time 11.69 seconds
Started May 14 12:56:26 PM PDT 24
Finished May 14 12:56:38 PM PDT 24
Peak memory 210852 kb
Host smart-5a8ecba3-7a36-4546-96c5-23abf19eb707
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524453687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1524453687
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2749620697
Short name T90
Test name
Test status
Simulation time 24336172369 ps
CPU time 74.07 seconds
Started May 14 12:56:27 PM PDT 24
Finished May 14 12:57:42 PM PDT 24
Peak memory 211000 kb
Host smart-567fe3f6-3491-4abc-a599-e443bd673612
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749620697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2749620697
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1855302835
Short name T70
Test name
Test status
Simulation time 8833813947 ps
CPU time 21.16 seconds
Started May 14 12:56:32 PM PDT 24
Finished May 14 12:56:53 PM PDT 24
Peak memory 211288 kb
Host smart-a527d108-a46e-4e6a-bf83-90d5708d89cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855302835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1855302835
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2455379410
Short name T444
Test name
Test status
Simulation time 5290826346 ps
CPU time 17.84 seconds
Started May 14 12:56:27 PM PDT 24
Finished May 14 12:56:46 PM PDT 24
Peak memory 217160 kb
Host smart-de82a154-2379-4f92-97ba-ebe77558d44c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455379410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2455379410
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3611792271
Short name T110
Test name
Test status
Simulation time 1215763155 ps
CPU time 150.91 seconds
Started May 14 12:56:33 PM PDT 24
Finished May 14 12:59:05 PM PDT 24
Peak memory 213612 kb
Host smart-7073c522-b028-4a81-a884-d654b3ee4e01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611792271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3611792271
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4106784914
Short name T368
Test name
Test status
Simulation time 1023248963 ps
CPU time 15.02 seconds
Started May 14 12:56:35 PM PDT 24
Finished May 14 12:56:52 PM PDT 24
Peak memory 215892 kb
Host smart-866a1dd9-0656-41ff-a017-a2eb4496006a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106784914 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.4106784914
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1556350901
Short name T447
Test name
Test status
Simulation time 9205432064 ps
CPU time 21.89 seconds
Started May 14 12:56:32 PM PDT 24
Finished May 14 12:56:54 PM PDT 24
Peak memory 211912 kb
Host smart-069b81b6-d2d8-4965-92c9-e40a0b194c18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556350901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1556350901
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1974640009
Short name T401
Test name
Test status
Simulation time 2227926046 ps
CPU time 16.12 seconds
Started May 14 12:56:32 PM PDT 24
Finished May 14 12:56:49 PM PDT 24
Peak memory 211236 kb
Host smart-e6dda496-e9a8-42c9-9157-1b21bdca9a40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974640009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1974640009
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1260890090
Short name T437
Test name
Test status
Simulation time 5286504401 ps
CPU time 20.03 seconds
Started May 14 12:56:34 PM PDT 24
Finished May 14 12:56:56 PM PDT 24
Peak memory 218120 kb
Host smart-da1adbf4-e099-48a2-991e-ba06d102a3db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260890090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1260890090
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2478420994
Short name T461
Test name
Test status
Simulation time 5257926575 ps
CPU time 94.54 seconds
Started May 14 12:56:34 PM PDT 24
Finished May 14 12:58:10 PM PDT 24
Peak memory 213632 kb
Host smart-0970ff6e-a1c7-478b-8916-6973b8c845ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478420994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2478420994
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3380933537
Short name T367
Test name
Test status
Simulation time 11718067209 ps
CPU time 25.72 seconds
Started May 14 12:56:34 PM PDT 24
Finished May 14 12:57:01 PM PDT 24
Peak memory 219176 kb
Host smart-0b8ba163-bafb-408e-ac23-0707d9f57dec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380933537 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3380933537
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2721106946
Short name T96
Test name
Test status
Simulation time 503602758 ps
CPU time 11.86 seconds
Started May 14 12:56:34 PM PDT 24
Finished May 14 12:56:47 PM PDT 24
Peak memory 210876 kb
Host smart-e9cbb272-59fa-41ca-96d2-7c652d34fd4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721106946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2721106946
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.972902427
Short name T68
Test name
Test status
Simulation time 10362588203 ps
CPU time 94.08 seconds
Started May 14 12:56:33 PM PDT 24
Finished May 14 12:58:09 PM PDT 24
Peak memory 210984 kb
Host smart-d3ebf432-6c28-4168-a329-69ac8d181dc9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972902427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.972902427
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1375776921
Short name T451
Test name
Test status
Simulation time 1720878895 ps
CPU time 19.25 seconds
Started May 14 12:56:33 PM PDT 24
Finished May 14 12:56:53 PM PDT 24
Peak memory 211872 kb
Host smart-72d6c703-7ac5-4b56-8baf-c780291628df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375776921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1375776921
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1685370345
Short name T386
Test name
Test status
Simulation time 660625246 ps
CPU time 10.75 seconds
Started May 14 12:56:34 PM PDT 24
Finished May 14 12:56:46 PM PDT 24
Peak memory 216684 kb
Host smart-6d5ff5eb-962f-45f4-84cb-124e62122c3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685370345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1685370345
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1179952003
Short name T114
Test name
Test status
Simulation time 7934061453 ps
CPU time 101.22 seconds
Started May 14 12:56:32 PM PDT 24
Finished May 14 12:58:15 PM PDT 24
Peak memory 212456 kb
Host smart-587025ed-3e41-4eb3-a362-a72085827c2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179952003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1179952003
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.928590475
Short name T454
Test name
Test status
Simulation time 8265838427 ps
CPU time 24.41 seconds
Started May 14 12:56:33 PM PDT 24
Finished May 14 12:56:58 PM PDT 24
Peak memory 218096 kb
Host smart-8e67c15a-7c4f-4d74-a86b-b4b288817403
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928590475 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.928590475
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4095751518
Short name T99
Test name
Test status
Simulation time 17109365983 ps
CPU time 30.77 seconds
Started May 14 12:56:33 PM PDT 24
Finished May 14 12:57:06 PM PDT 24
Peak memory 212064 kb
Host smart-a32f43ad-4f09-4878-9b5f-ee3dcb2d2c44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095751518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.4095751518
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3791067715
Short name T385
Test name
Test status
Simulation time 8440437283 ps
CPU time 63.46 seconds
Started May 14 12:56:33 PM PDT 24
Finished May 14 12:57:38 PM PDT 24
Peak memory 210928 kb
Host smart-1207a8ab-231e-473e-ac61-ac8236885e0b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791067715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3791067715
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1791358409
Short name T72
Test name
Test status
Simulation time 477366776 ps
CPU time 9.72 seconds
Started May 14 12:56:32 PM PDT 24
Finished May 14 12:56:42 PM PDT 24
Peak memory 210820 kb
Host smart-348ded97-1165-4cb7-991d-960fc5a0ad98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791358409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1791358409
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.526406556
Short name T402
Test name
Test status
Simulation time 13265056737 ps
CPU time 31.96 seconds
Started May 14 12:56:34 PM PDT 24
Finished May 14 12:57:08 PM PDT 24
Peak memory 219220 kb
Host smart-a2e15629-7c60-48c4-a5b0-8328f90123b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526406556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.526406556
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.130259096
Short name T113
Test name
Test status
Simulation time 1445603685 ps
CPU time 158.99 seconds
Started May 14 12:56:32 PM PDT 24
Finished May 14 12:59:12 PM PDT 24
Peak memory 213524 kb
Host smart-0935f123-5451-4436-ac2e-7d01f98dc38d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130259096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.130259096
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3847194163
Short name T383
Test name
Test status
Simulation time 341463579 ps
CPU time 11.13 seconds
Started May 14 12:56:34 PM PDT 24
Finished May 14 12:56:47 PM PDT 24
Peak memory 215720 kb
Host smart-ff837f18-f00c-49db-be9e-d4307b789682
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847194163 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3847194163
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3524541451
Short name T378
Test name
Test status
Simulation time 2994085204 ps
CPU time 25.24 seconds
Started May 14 12:56:33 PM PDT 24
Finished May 14 12:56:59 PM PDT 24
Peak memory 211124 kb
Host smart-ead18476-7d80-4bee-9499-92601e3db937
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524541451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3524541451
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2365083873
Short name T449
Test name
Test status
Simulation time 1039075568 ps
CPU time 56.21 seconds
Started May 14 12:56:33 PM PDT 24
Finished May 14 12:57:31 PM PDT 24
Peak memory 214592 kb
Host smart-ccda8d18-d55f-49e8-83fe-ee89ae44b703
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365083873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2365083873
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2807180128
Short name T73
Test name
Test status
Simulation time 4120353652 ps
CPU time 25.46 seconds
Started May 14 12:56:35 PM PDT 24
Finished May 14 12:57:02 PM PDT 24
Peak memory 212144 kb
Host smart-c1318e2c-2fc7-47bd-ac16-0a7f28900853
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807180128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2807180128
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1689660631
Short name T369
Test name
Test status
Simulation time 2292864207 ps
CPU time 18.84 seconds
Started May 14 12:56:33 PM PDT 24
Finished May 14 12:56:53 PM PDT 24
Peak memory 219188 kb
Host smart-2717c2cd-eb4e-4036-a62f-9341e083d3b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689660631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1689660631
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.238133069
Short name T61
Test name
Test status
Simulation time 179984011 ps
CPU time 8.68 seconds
Started May 14 12:56:40 PM PDT 24
Finished May 14 12:56:53 PM PDT 24
Peak memory 215480 kb
Host smart-c55f4fd0-c54a-40f7-882f-acf19284e4f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238133069 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.238133069
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2886972468
Short name T456
Test name
Test status
Simulation time 12611288506 ps
CPU time 27.56 seconds
Started May 14 12:56:40 PM PDT 24
Finished May 14 12:57:11 PM PDT 24
Peak memory 211656 kb
Host smart-ba77048a-ba08-4aa9-9811-8e4f46e663c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886972468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2886972468
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.918588171
Short name T89
Test name
Test status
Simulation time 5363819755 ps
CPU time 46.2 seconds
Started May 14 12:56:42 PM PDT 24
Finished May 14 12:57:31 PM PDT 24
Peak memory 214044 kb
Host smart-176c8fc3-d727-47ba-b261-c99ae93d916e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918588171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.918588171
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.472706454
Short name T98
Test name
Test status
Simulation time 3622286145 ps
CPU time 14.72 seconds
Started May 14 12:56:41 PM PDT 24
Finished May 14 12:56:59 PM PDT 24
Peak memory 210996 kb
Host smart-d13aa2da-b91d-49a6-87d3-ce2e7c8c6878
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472706454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.472706454
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3687881866
Short name T388
Test name
Test status
Simulation time 6408216354 ps
CPU time 20.27 seconds
Started May 14 12:56:41 PM PDT 24
Finished May 14 12:57:05 PM PDT 24
Peak memory 217824 kb
Host smart-a126a724-8af3-4e5f-a83c-54587e1c410e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687881866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3687881866
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4089684912
Short name T59
Test name
Test status
Simulation time 14250039279 ps
CPU time 96.78 seconds
Started May 14 12:56:42 PM PDT 24
Finished May 14 12:58:22 PM PDT 24
Peak memory 219064 kb
Host smart-19568424-71c7-4036-bf7e-9cbfced5bb6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089684912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.4089684912
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3831574883
Short name T412
Test name
Test status
Simulation time 7714584712 ps
CPU time 29.28 seconds
Started May 14 12:56:45 PM PDT 24
Finished May 14 12:57:16 PM PDT 24
Peak memory 219136 kb
Host smart-fd2c5a49-1a4c-471c-b33c-e965d2a703d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831574883 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3831574883
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2389221911
Short name T445
Test name
Test status
Simulation time 2354265186 ps
CPU time 8.45 seconds
Started May 14 12:56:45 PM PDT 24
Finished May 14 12:56:55 PM PDT 24
Peak memory 210952 kb
Host smart-ba03ad3e-0bab-4ef5-84d2-9a75011bff4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389221911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2389221911
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.237407746
Short name T74
Test name
Test status
Simulation time 78098081785 ps
CPU time 168.34 seconds
Started May 14 12:56:40 PM PDT 24
Finished May 14 12:59:32 PM PDT 24
Peak memory 215144 kb
Host smart-464db7eb-36b3-45be-af36-eee005a38656
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237407746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.237407746
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.6844770
Short name T67
Test name
Test status
Simulation time 4758028198 ps
CPU time 30.88 seconds
Started May 14 12:56:39 PM PDT 24
Finished May 14 12:57:13 PM PDT 24
Peak memory 211996 kb
Host smart-c6831c3d-1590-4e83-9c7d-a992214c4b1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6844770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctr
l_same_csr_outstanding.6844770
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2666585123
Short name T408
Test name
Test status
Simulation time 9251627616 ps
CPU time 28.09 seconds
Started May 14 12:56:40 PM PDT 24
Finished May 14 12:57:12 PM PDT 24
Peak memory 219140 kb
Host smart-41ee85d4-2595-41fa-b49e-9b13071f744d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666585123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2666585123
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1191275962
Short name T116
Test name
Test status
Simulation time 1913868598 ps
CPU time 164.24 seconds
Started May 14 12:56:40 PM PDT 24
Finished May 14 12:59:27 PM PDT 24
Peak memory 213616 kb
Host smart-db6c5397-ed45-4df9-b567-0cac48233a41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191275962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1191275962
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1824748307
Short name T425
Test name
Test status
Simulation time 35954872267 ps
CPU time 32.14 seconds
Started May 14 12:56:46 PM PDT 24
Finished May 14 12:57:19 PM PDT 24
Peak memory 219136 kb
Host smart-fddffc3f-28f0-4f51-ae21-4cfa439ea16c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824748307 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1824748307
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3767563289
Short name T460
Test name
Test status
Simulation time 29789516949 ps
CPU time 32.99 seconds
Started May 14 12:56:41 PM PDT 24
Finished May 14 12:57:18 PM PDT 24
Peak memory 212028 kb
Host smart-11b7ce8f-b687-4771-ac73-16d2a295444f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767563289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3767563289
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1637609016
Short name T411
Test name
Test status
Simulation time 1435322096 ps
CPU time 38.03 seconds
Started May 14 12:56:42 PM PDT 24
Finished May 14 12:57:24 PM PDT 24
Peak memory 219124 kb
Host smart-6b1888a5-8acb-4233-b8ab-ba232fa432b8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637609016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1637609016
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2833841239
Short name T420
Test name
Test status
Simulation time 6742329507 ps
CPU time 27.64 seconds
Started May 14 12:56:39 PM PDT 24
Finished May 14 12:57:10 PM PDT 24
Peak memory 211932 kb
Host smart-d7a3cfdd-7b21-4c97-846e-99a6a2118ea4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833841239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2833841239
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1701187503
Short name T440
Test name
Test status
Simulation time 851898857 ps
CPU time 18.33 seconds
Started May 14 12:56:40 PM PDT 24
Finished May 14 12:57:02 PM PDT 24
Peak memory 218164 kb
Host smart-b5d90d0f-8f2f-4de2-959b-09dcf86d8dad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701187503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1701187503
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3051253925
Short name T115
Test name
Test status
Simulation time 411988759 ps
CPU time 83.54 seconds
Started May 14 12:56:40 PM PDT 24
Finished May 14 12:58:07 PM PDT 24
Peak memory 212760 kb
Host smart-d8e23d3e-ea32-4327-bd95-d2e9a71266fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051253925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3051253925
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2384580500
Short name T459
Test name
Test status
Simulation time 3694801369 ps
CPU time 30.07 seconds
Started May 14 12:56:39 PM PDT 24
Finished May 14 12:57:12 PM PDT 24
Peak memory 219076 kb
Host smart-51326c6c-ccd8-46d0-b075-b6d7cb24801a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384580500 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2384580500
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3654341547
Short name T421
Test name
Test status
Simulation time 14866938833 ps
CPU time 24.06 seconds
Started May 14 12:56:43 PM PDT 24
Finished May 14 12:57:10 PM PDT 24
Peak memory 211988 kb
Host smart-d42b343b-4e2b-41a6-9f45-8d1297063253
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654341547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3654341547
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1831614169
Short name T87
Test name
Test status
Simulation time 69531579294 ps
CPU time 132.96 seconds
Started May 14 12:56:41 PM PDT 24
Finished May 14 12:58:58 PM PDT 24
Peak memory 210912 kb
Host smart-3ca3ab42-1613-4b18-8cb4-4a85f6f08663
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831614169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1831614169
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1173688029
Short name T403
Test name
Test status
Simulation time 661829461 ps
CPU time 8.47 seconds
Started May 14 12:56:42 PM PDT 24
Finished May 14 12:56:54 PM PDT 24
Peak memory 210864 kb
Host smart-23a82eef-e58a-4a11-9ed2-8016622257d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173688029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1173688029
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3800786558
Short name T374
Test name
Test status
Simulation time 19898402674 ps
CPU time 37.24 seconds
Started May 14 12:56:42 PM PDT 24
Finished May 14 12:57:23 PM PDT 24
Peak memory 218500 kb
Host smart-8234dae8-f3ee-4b44-861c-471c187f665f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800786558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3800786558
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1234304915
Short name T431
Test name
Test status
Simulation time 4050549893 ps
CPU time 31.23 seconds
Started May 14 12:56:09 PM PDT 24
Finished May 14 12:56:44 PM PDT 24
Peak memory 211060 kb
Host smart-d82b19eb-c021-41d0-beaa-5ac86d229e12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234304915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1234304915
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.158794761
Short name T376
Test name
Test status
Simulation time 11861807465 ps
CPU time 26.3 seconds
Started May 14 12:56:05 PM PDT 24
Finished May 14 12:56:35 PM PDT 24
Peak memory 211808 kb
Host smart-33775a10-c9f0-4608-a855-deb0fcc75da7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158794761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.158794761
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.608189371
Short name T394
Test name
Test status
Simulation time 3273994981 ps
CPU time 16.77 seconds
Started May 14 12:56:12 PM PDT 24
Finished May 14 12:56:32 PM PDT 24
Peak memory 211560 kb
Host smart-3527b142-27c0-4455-85f2-2c0d7c43aa92
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608189371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.608189371
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.786890833
Short name T457
Test name
Test status
Simulation time 376727709 ps
CPU time 8.82 seconds
Started May 14 12:56:12 PM PDT 24
Finished May 14 12:56:23 PM PDT 24
Peak memory 215572 kb
Host smart-6fe1318e-2c25-4f66-b02a-bfae1a5b01ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786890833 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.786890833
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2580160612
Short name T380
Test name
Test status
Simulation time 2660253512 ps
CPU time 24.31 seconds
Started May 14 12:56:07 PM PDT 24
Finished May 14 12:56:35 PM PDT 24
Peak memory 211348 kb
Host smart-da8a6f9f-3e72-4658-945f-57f37cba03a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580160612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2580160612
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4081558874
Short name T399
Test name
Test status
Simulation time 4256345223 ps
CPU time 15.06 seconds
Started May 14 12:56:11 PM PDT 24
Finished May 14 12:56:29 PM PDT 24
Peak memory 210712 kb
Host smart-5c24d0bb-d4f2-4913-b8c8-3470bf357ee8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081558874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.4081558874
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1723528033
Short name T446
Test name
Test status
Simulation time 5791074243 ps
CPU time 15.86 seconds
Started May 14 12:56:17 PM PDT 24
Finished May 14 12:56:34 PM PDT 24
Peak memory 210896 kb
Host smart-483cf178-1e4f-4f90-8167-ea65863391da
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723528033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1723528033
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1033951754
Short name T94
Test name
Test status
Simulation time 41606689572 ps
CPU time 75.63 seconds
Started May 14 12:56:11 PM PDT 24
Finished May 14 12:57:30 PM PDT 24
Peak memory 213968 kb
Host smart-78eb0cce-9426-47b6-bdda-7f49e315d17b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033951754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1033951754
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3282378582
Short name T95
Test name
Test status
Simulation time 2420667198 ps
CPU time 22.96 seconds
Started May 14 12:56:10 PM PDT 24
Finished May 14 12:56:36 PM PDT 24
Peak memory 211832 kb
Host smart-3cb658bb-784e-4b24-b968-d1f331e9c28e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282378582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3282378582
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.550088225
Short name T371
Test name
Test status
Simulation time 168971838 ps
CPU time 11.78 seconds
Started May 14 12:56:07 PM PDT 24
Finished May 14 12:56:22 PM PDT 24
Peak memory 219184 kb
Host smart-e046f381-8377-4446-8250-7a1996571777
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550088225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.550088225
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.158595312
Short name T108
Test name
Test status
Simulation time 7708119124 ps
CPU time 168.7 seconds
Started May 14 12:56:02 PM PDT 24
Finished May 14 12:58:53 PM PDT 24
Peak memory 213672 kb
Host smart-11f9aea0-1a52-452c-bac7-33fb4ce2b2dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158595312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.158595312
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3091385279
Short name T82
Test name
Test status
Simulation time 17065912737 ps
CPU time 31.89 seconds
Started May 14 12:56:13 PM PDT 24
Finished May 14 12:56:47 PM PDT 24
Peak memory 211696 kb
Host smart-ea036590-57d7-4cbf-aa28-f263d372554c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091385279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3091385279
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1460113060
Short name T428
Test name
Test status
Simulation time 172668823 ps
CPU time 7.97 seconds
Started May 14 12:56:11 PM PDT 24
Finished May 14 12:56:22 PM PDT 24
Peak memory 210852 kb
Host smart-2da4c830-b1d9-4928-b667-5f8b6d27f8ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460113060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1460113060
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3820165956
Short name T430
Test name
Test status
Simulation time 7589149285 ps
CPU time 27.15 seconds
Started May 14 12:56:08 PM PDT 24
Finished May 14 12:56:38 PM PDT 24
Peak memory 211940 kb
Host smart-6e683579-b796-49d2-9d59-aaec50893261
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820165956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3820165956
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3709493243
Short name T450
Test name
Test status
Simulation time 17236890138 ps
CPU time 21.8 seconds
Started May 14 12:56:09 PM PDT 24
Finished May 14 12:56:35 PM PDT 24
Peak memory 218340 kb
Host smart-ee3b9e15-a015-4c3f-be16-af9108f4b840
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709493243 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3709493243
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1164754200
Short name T100
Test name
Test status
Simulation time 2743633685 ps
CPU time 10.86 seconds
Started May 14 12:56:11 PM PDT 24
Finished May 14 12:56:24 PM PDT 24
Peak memory 210964 kb
Host smart-a28ffa2a-f820-4936-8f2e-eb4c4a310791
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164754200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1164754200
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1105707803
Short name T366
Test name
Test status
Simulation time 174353513 ps
CPU time 7.88 seconds
Started May 14 12:56:14 PM PDT 24
Finished May 14 12:56:23 PM PDT 24
Peak memory 210740 kb
Host smart-39c432dd-e9f7-4e2b-a801-c0cf04bbaaea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105707803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1105707803
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1249858533
Short name T393
Test name
Test status
Simulation time 1833912049 ps
CPU time 8.09 seconds
Started May 14 12:56:13 PM PDT 24
Finished May 14 12:56:23 PM PDT 24
Peak memory 210796 kb
Host smart-bd617276-d623-410f-bf79-a3a05e3fb9bf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249858533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1249858533
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3891625465
Short name T63
Test name
Test status
Simulation time 21279542784 ps
CPU time 102.93 seconds
Started May 14 12:56:10 PM PDT 24
Finished May 14 12:57:56 PM PDT 24
Peak memory 213976 kb
Host smart-a5c6e7f1-a21f-40b6-a106-57e58443b903
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891625465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3891625465
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.768738506
Short name T439
Test name
Test status
Simulation time 2137157655 ps
CPU time 20.98 seconds
Started May 14 12:56:10 PM PDT 24
Finished May 14 12:56:34 PM PDT 24
Peak memory 211848 kb
Host smart-78dc7c3b-2266-4d97-aabb-c149942d6110
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768738506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.768738506
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4210797004
Short name T415
Test name
Test status
Simulation time 3524205875 ps
CPU time 30.1 seconds
Started May 14 12:56:07 PM PDT 24
Finished May 14 12:56:41 PM PDT 24
Peak memory 218032 kb
Host smart-d80275df-2b63-4275-9fd5-e05d0a89c46f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210797004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4210797004
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1140557813
Short name T106
Test name
Test status
Simulation time 32589510489 ps
CPU time 99.71 seconds
Started May 14 12:56:06 PM PDT 24
Finished May 14 12:57:49 PM PDT 24
Peak memory 219116 kb
Host smart-9f48a7b1-17a8-4529-b9cf-dc21d6333609
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140557813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1140557813
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2071412492
Short name T85
Test name
Test status
Simulation time 661467835 ps
CPU time 8 seconds
Started May 14 12:56:20 PM PDT 24
Finished May 14 12:56:30 PM PDT 24
Peak memory 210844 kb
Host smart-4b4bc227-663d-4577-b577-734af6539b78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071412492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2071412492
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1011669952
Short name T453
Test name
Test status
Simulation time 5450868221 ps
CPU time 17.14 seconds
Started May 14 12:56:13 PM PDT 24
Finished May 14 12:56:32 PM PDT 24
Peak memory 219104 kb
Host smart-d2c123e1-6713-4c17-9d9f-0152c0333845
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011669952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1011669952
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.586721205
Short name T435
Test name
Test status
Simulation time 180060232 ps
CPU time 11.99 seconds
Started May 14 12:56:11 PM PDT 24
Finished May 14 12:56:26 PM PDT 24
Peak memory 211156 kb
Host smart-69ea056f-afe5-475e-8130-6edd1e0932bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586721205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.586721205
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1007400038
Short name T438
Test name
Test status
Simulation time 3101980909 ps
CPU time 18.13 seconds
Started May 14 12:56:17 PM PDT 24
Finished May 14 12:56:36 PM PDT 24
Peak memory 215004 kb
Host smart-c95f9c29-5bb8-4cea-ae13-407c35758f9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007400038 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1007400038
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.158740848
Short name T404
Test name
Test status
Simulation time 1984643316 ps
CPU time 19.23 seconds
Started May 14 12:56:15 PM PDT 24
Finished May 14 12:56:35 PM PDT 24
Peak memory 210956 kb
Host smart-1728b3b7-b882-498b-acff-439165d7889d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158740848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.158740848
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2573193220
Short name T384
Test name
Test status
Simulation time 2716094327 ps
CPU time 24.43 seconds
Started May 14 12:56:16 PM PDT 24
Finished May 14 12:56:42 PM PDT 24
Peak memory 210784 kb
Host smart-8d9536cd-bb40-4fe8-84a6-0f778275b654
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573193220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2573193220
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.354425897
Short name T442
Test name
Test status
Simulation time 689636213 ps
CPU time 8.05 seconds
Started May 14 12:56:10 PM PDT 24
Finished May 14 12:56:21 PM PDT 24
Peak memory 210812 kb
Host smart-d64ed5d8-1b67-4699-b71c-ba8fa2c61123
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354425897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
354425897
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.702890378
Short name T86
Test name
Test status
Simulation time 2853130728 ps
CPU time 37.66 seconds
Started May 14 12:56:03 PM PDT 24
Finished May 14 12:56:44 PM PDT 24
Peak memory 219108 kb
Host smart-661a6742-8df4-4cf2-872e-fefa458b29e4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702890378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.702890378
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3938572845
Short name T436
Test name
Test status
Simulation time 14903313746 ps
CPU time 35.33 seconds
Started May 14 12:56:22 PM PDT 24
Finished May 14 12:56:59 PM PDT 24
Peak memory 212232 kb
Host smart-94cbc1a2-9c5d-4074-9cd8-471c5cf99282
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938572845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3938572845
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3518215043
Short name T458
Test name
Test status
Simulation time 174319637 ps
CPU time 11.85 seconds
Started May 14 12:56:14 PM PDT 24
Finished May 14 12:56:28 PM PDT 24
Peak memory 216696 kb
Host smart-4d7b912b-f508-43ec-bd79-71e2d60407ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518215043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3518215043
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1512705223
Short name T396
Test name
Test status
Simulation time 9095112389 ps
CPU time 170.74 seconds
Started May 14 12:56:18 PM PDT 24
Finished May 14 12:59:10 PM PDT 24
Peak memory 213980 kb
Host smart-78e31344-bbb1-4179-8eb9-83353db55f35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512705223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1512705223
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.362270232
Short name T397
Test name
Test status
Simulation time 2246693521 ps
CPU time 11.28 seconds
Started May 14 12:56:33 PM PDT 24
Finished May 14 12:56:45 PM PDT 24
Peak memory 219164 kb
Host smart-c2350cd8-5d93-416a-88a4-ad0dec053eed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362270232 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.362270232
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.946361910
Short name T395
Test name
Test status
Simulation time 4266629718 ps
CPU time 14.7 seconds
Started May 14 12:56:21 PM PDT 24
Finished May 14 12:56:38 PM PDT 24
Peak memory 210944 kb
Host smart-b5c8a7f5-06fb-4621-8a02-f68365a9b018
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946361910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.946361910
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1421507903
Short name T432
Test name
Test status
Simulation time 12072817304 ps
CPU time 77.47 seconds
Started May 14 12:56:18 PM PDT 24
Finished May 14 12:57:37 PM PDT 24
Peak memory 213028 kb
Host smart-8ac9eeb4-2f2a-44d1-8072-a60391a313c4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421507903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1421507903
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2505140662
Short name T406
Test name
Test status
Simulation time 5395900153 ps
CPU time 23.38 seconds
Started May 14 12:56:21 PM PDT 24
Finished May 14 12:56:46 PM PDT 24
Peak memory 212272 kb
Host smart-7d9b95db-df60-443b-a6b7-670cc2e92670
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505140662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2505140662
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1866491717
Short name T443
Test name
Test status
Simulation time 181399766 ps
CPU time 14.1 seconds
Started May 14 12:56:12 PM PDT 24
Finished May 14 12:56:29 PM PDT 24
Peak memory 217060 kb
Host smart-2457dc1a-3f70-44b8-86fe-f2c9457893f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866491717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1866491717
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1124380085
Short name T107
Test name
Test status
Simulation time 39343450878 ps
CPU time 166.64 seconds
Started May 14 12:56:16 PM PDT 24
Finished May 14 12:59:04 PM PDT 24
Peak memory 219064 kb
Host smart-23f5c06d-6f9d-452a-9ddf-461b9804d254
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124380085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1124380085
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3281393532
Short name T373
Test name
Test status
Simulation time 1324897341 ps
CPU time 16.81 seconds
Started May 14 12:56:22 PM PDT 24
Finished May 14 12:56:41 PM PDT 24
Peak memory 218956 kb
Host smart-5ac4d131-3b09-4143-ab82-08fb7e82f874
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281393532 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3281393532
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.210616636
Short name T426
Test name
Test status
Simulation time 2726167875 ps
CPU time 12.53 seconds
Started May 14 12:56:28 PM PDT 24
Finished May 14 12:56:41 PM PDT 24
Peak memory 210872 kb
Host smart-9b476bef-a1a6-4577-bd39-2eb1debf3565
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210616636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.210616636
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.347384060
Short name T462
Test name
Test status
Simulation time 18565867276 ps
CPU time 110.1 seconds
Started May 14 12:56:19 PM PDT 24
Finished May 14 12:58:10 PM PDT 24
Peak memory 215220 kb
Host smart-ad267d2c-feef-42ce-b43f-5e7168f52217
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347384060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.347384060
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3183639962
Short name T407
Test name
Test status
Simulation time 3611191082 ps
CPU time 28.22 seconds
Started May 14 12:56:18 PM PDT 24
Finished May 14 12:56:47 PM PDT 24
Peak memory 211708 kb
Host smart-81514ddd-fd30-4723-92fb-955a76635c15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183639962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3183639962
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1234260784
Short name T365
Test name
Test status
Simulation time 1424247148 ps
CPU time 15.36 seconds
Started May 14 12:56:21 PM PDT 24
Finished May 14 12:56:38 PM PDT 24
Peak memory 219048 kb
Host smart-51b279b2-73ab-46d4-9a6d-a72045fc66ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234260784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1234260784
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2328143301
Short name T434
Test name
Test status
Simulation time 1765878982 ps
CPU time 84.81 seconds
Started May 14 12:56:19 PM PDT 24
Finished May 14 12:57:45 PM PDT 24
Peak memory 213168 kb
Host smart-99e2c2ab-3f86-41ee-af9f-510f2d1adcbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328143301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2328143301
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2415602070
Short name T419
Test name
Test status
Simulation time 2899306827 ps
CPU time 12.38 seconds
Started May 14 12:56:20 PM PDT 24
Finished May 14 12:56:34 PM PDT 24
Peak memory 214860 kb
Host smart-3f249a8d-0717-43b1-a698-808d9651ad3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415602070 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2415602070
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.237038378
Short name T413
Test name
Test status
Simulation time 1236871034 ps
CPU time 15.81 seconds
Started May 14 12:56:19 PM PDT 24
Finished May 14 12:56:36 PM PDT 24
Peak memory 210884 kb
Host smart-0bea606a-09d9-45c5-b49e-e289596a5be0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237038378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.237038378
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1418560802
Short name T390
Test name
Test status
Simulation time 12617016942 ps
CPU time 95.97 seconds
Started May 14 12:56:20 PM PDT 24
Finished May 14 12:57:58 PM PDT 24
Peak memory 214268 kb
Host smart-05942a7b-e661-4536-8fdf-2fa544fd895c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418560802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1418560802
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.851794165
Short name T97
Test name
Test status
Simulation time 18029756802 ps
CPU time 19.86 seconds
Started May 14 12:56:27 PM PDT 24
Finished May 14 12:56:48 PM PDT 24
Peak memory 211960 kb
Host smart-c4db496c-6652-4f64-ab09-e97cf46c8a3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851794165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.851794165
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3289200792
Short name T422
Test name
Test status
Simulation time 2904619264 ps
CPU time 28.98 seconds
Started May 14 12:56:19 PM PDT 24
Finished May 14 12:56:49 PM PDT 24
Peak memory 217896 kb
Host smart-e2c1c77f-fe21-4c37-9d10-b5b142545834
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289200792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3289200792
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2019996321
Short name T409
Test name
Test status
Simulation time 1011051240 ps
CPU time 82.91 seconds
Started May 14 12:56:28 PM PDT 24
Finished May 14 12:57:52 PM PDT 24
Peak memory 213328 kb
Host smart-177ffe3f-2d39-45cf-9c02-c3ba3cbb06bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019996321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2019996321
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2860667409
Short name T370
Test name
Test status
Simulation time 2414261784 ps
CPU time 21.91 seconds
Started May 14 12:56:27 PM PDT 24
Finished May 14 12:56:50 PM PDT 24
Peak memory 217240 kb
Host smart-e61206f0-11fe-487d-b23e-33590ea8a19d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860667409 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2860667409
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2989979923
Short name T455
Test name
Test status
Simulation time 8060350830 ps
CPU time 30.52 seconds
Started May 14 12:56:28 PM PDT 24
Finished May 14 12:57:00 PM PDT 24
Peak memory 211904 kb
Host smart-414bbe40-91a0-47ad-b194-05b383250d2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989979923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2989979923
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3398396748
Short name T83
Test name
Test status
Simulation time 37618670984 ps
CPU time 116.38 seconds
Started May 14 12:56:26 PM PDT 24
Finished May 14 12:58:23 PM PDT 24
Peak memory 215148 kb
Host smart-6e615dd6-51e0-483c-a04d-8c0bca49f0c7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398396748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3398396748
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2145451708
Short name T414
Test name
Test status
Simulation time 345303614 ps
CPU time 8.24 seconds
Started May 14 12:56:28 PM PDT 24
Finished May 14 12:56:38 PM PDT 24
Peak memory 210936 kb
Host smart-d8bf12c5-0178-4b50-8f9b-166759286d3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145451708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2145451708
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.798148387
Short name T379
Test name
Test status
Simulation time 10668458426 ps
CPU time 25.75 seconds
Started May 14 12:56:25 PM PDT 24
Finished May 14 12:56:52 PM PDT 24
Peak memory 219140 kb
Host smart-cf48c381-4949-4370-bad8-61e94ece4811
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798148387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.798148387
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1250942223
Short name T111
Test name
Test status
Simulation time 4240857109 ps
CPU time 101.79 seconds
Started May 14 12:56:33 PM PDT 24
Finished May 14 12:58:16 PM PDT 24
Peak memory 214372 kb
Host smart-3758e293-cced-48a9-8c02-cd8c7ecfa3a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250942223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1250942223
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.169488190
Short name T382
Test name
Test status
Simulation time 2588878410 ps
CPU time 23.54 seconds
Started May 14 12:56:27 PM PDT 24
Finished May 14 12:56:52 PM PDT 24
Peak memory 217896 kb
Host smart-1267e367-9d5b-4f86-967d-f7c09cac6a80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169488190 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.169488190
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.609079074
Short name T448
Test name
Test status
Simulation time 2163857262 ps
CPU time 21.3 seconds
Started May 14 12:56:26 PM PDT 24
Finished May 14 12:56:49 PM PDT 24
Peak memory 211896 kb
Host smart-3268ac3a-d0e8-4bcc-b6cb-1ba81852bb56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609079074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.609079074
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3941656708
Short name T452
Test name
Test status
Simulation time 109911820582 ps
CPU time 140.15 seconds
Started May 14 12:56:29 PM PDT 24
Finished May 14 12:58:50 PM PDT 24
Peak memory 215072 kb
Host smart-cc4d934c-f83a-443a-bcbc-325c68458306
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941656708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3941656708
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2011836292
Short name T389
Test name
Test status
Simulation time 9140384709 ps
CPU time 33.4 seconds
Started May 14 12:56:27 PM PDT 24
Finished May 14 12:57:01 PM PDT 24
Peak memory 211956 kb
Host smart-2723171c-c371-438a-b2fa-f4a810ee1be6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011836292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2011836292
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2724266407
Short name T423
Test name
Test status
Simulation time 16464394367 ps
CPU time 35.08 seconds
Started May 14 12:56:25 PM PDT 24
Finished May 14 12:57:02 PM PDT 24
Peak memory 219208 kb
Host smart-e050cda2-021b-4e25-9da6-e3b76c3f382b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724266407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2724266407
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2239919028
Short name T64
Test name
Test status
Simulation time 660995833 ps
CPU time 8.41 seconds
Started May 14 12:55:31 PM PDT 24
Finished May 14 12:55:40 PM PDT 24
Peak memory 211216 kb
Host smart-29091220-581c-48aa-802e-26a0990ae993
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239919028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2239919028
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3265075378
Short name T195
Test name
Test status
Simulation time 47862901924 ps
CPU time 246.33 seconds
Started May 14 12:55:42 PM PDT 24
Finished May 14 12:59:50 PM PDT 24
Peak memory 216852 kb
Host smart-f7cf03c0-a0d7-4b55-9598-478b7f61cc5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265075378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3265075378
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1638864430
Short name T300
Test name
Test status
Simulation time 73085994930 ps
CPU time 67.92 seconds
Started May 14 12:55:16 PM PDT 24
Finished May 14 12:56:28 PM PDT 24
Peak memory 214100 kb
Host smart-272fcaed-5f0a-458f-a8ae-96dd22ab087e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638864430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1638864430
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3357904684
Short name T166
Test name
Test status
Simulation time 2678295761 ps
CPU time 15.26 seconds
Started May 14 12:55:15 PM PDT 24
Finished May 14 12:55:32 PM PDT 24
Peak memory 211388 kb
Host smart-3247c126-a053-46dc-a425-910992fd013d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3357904684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3357904684
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2688206352
Short name T31
Test name
Test status
Simulation time 4201871187 ps
CPU time 251.73 seconds
Started May 14 12:55:13 PM PDT 24
Finished May 14 12:59:26 PM PDT 24
Peak memory 238984 kb
Host smart-4270d1ff-e68e-450d-9a2b-e1f7e16585e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688206352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2688206352
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3629470251
Short name T198
Test name
Test status
Simulation time 7249815764 ps
CPU time 47.25 seconds
Started May 14 12:55:16 PM PDT 24
Finished May 14 12:56:07 PM PDT 24
Peak memory 218040 kb
Host smart-a0bf13e7-f54e-42b5-9782-10083f989308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629470251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3629470251
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2914010857
Short name T180
Test name
Test status
Simulation time 784565008 ps
CPU time 32.09 seconds
Started May 14 12:55:19 PM PDT 24
Finished May 14 12:55:54 PM PDT 24
Peak memory 216312 kb
Host smart-a927f8eb-178c-43ed-8b98-da65d510b0a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914010857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2914010857
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.374340871
Short name T28
Test name
Test status
Simulation time 13403770322 ps
CPU time 216.61 seconds
Started May 14 12:55:35 PM PDT 24
Finished May 14 12:59:13 PM PDT 24
Peak memory 217008 kb
Host smart-3341747f-abc7-4379-8789-800aab3f060a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374340871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.374340871
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3848733675
Short name T168
Test name
Test status
Simulation time 5305543186 ps
CPU time 19.02 seconds
Started May 14 12:55:30 PM PDT 24
Finished May 14 12:55:50 PM PDT 24
Peak memory 212824 kb
Host smart-cab4e43c-1ef2-401f-a353-c04d8df8cb3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3848733675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3848733675
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2165862210
Short name T32
Test name
Test status
Simulation time 412578358 ps
CPU time 115.94 seconds
Started May 14 12:55:46 PM PDT 24
Finished May 14 12:57:43 PM PDT 24
Peak memory 237336 kb
Host smart-0fb3fee8-8b12-4529-8b44-7c3ba497c4dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165862210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2165862210
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2037374046
Short name T7
Test name
Test status
Simulation time 365550863 ps
CPU time 20.34 seconds
Started May 14 12:55:27 PM PDT 24
Finished May 14 12:55:48 PM PDT 24
Peak memory 215828 kb
Host smart-f1e251f6-c6fb-49fa-808b-b2c05ed03aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037374046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2037374046
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3776812392
Short name T219
Test name
Test status
Simulation time 9400589218 ps
CPU time 118.26 seconds
Started May 14 12:55:16 PM PDT 24
Finished May 14 12:57:19 PM PDT 24
Peak memory 220216 kb
Host smart-cc1151cb-5405-4601-8032-00d0d932ed86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776812392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3776812392
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.960784681
Short name T343
Test name
Test status
Simulation time 687804528 ps
CPU time 8.31 seconds
Started May 14 12:55:42 PM PDT 24
Finished May 14 12:55:52 PM PDT 24
Peak memory 211332 kb
Host smart-23715759-a3f6-4c1a-b647-0c39c5129b08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960784681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.960784681
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.444821119
Short name T118
Test name
Test status
Simulation time 330300602320 ps
CPU time 791.03 seconds
Started May 14 12:55:37 PM PDT 24
Finished May 14 01:08:50 PM PDT 24
Peak memory 229624 kb
Host smart-79bc608c-a510-43c0-bf68-0a2720793058
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444821119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.444821119
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.960453175
Short name T259
Test name
Test status
Simulation time 95435217717 ps
CPU time 55.45 seconds
Started May 14 12:55:35 PM PDT 24
Finished May 14 12:56:32 PM PDT 24
Peak memory 215136 kb
Host smart-a18db0ae-6d0d-4ca6-a30a-245cba44d211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960453175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.960453175
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1500780486
Short name T234
Test name
Test status
Simulation time 48995766964 ps
CPU time 34.25 seconds
Started May 14 12:55:26 PM PDT 24
Finished May 14 12:56:01 PM PDT 24
Peak memory 211688 kb
Host smart-0408f427-c56e-45ec-9b40-546735133dcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1500780486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1500780486
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2502328080
Short name T304
Test name
Test status
Simulation time 3305560964 ps
CPU time 40.83 seconds
Started May 14 12:55:24 PM PDT 24
Finished May 14 12:56:05 PM PDT 24
Peak memory 217036 kb
Host smart-19f7bdd2-3926-4b42-8b65-fe9dcef44769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502328080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2502328080
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2222107053
Short name T213
Test name
Test status
Simulation time 31012269002 ps
CPU time 70.36 seconds
Started May 14 12:55:30 PM PDT 24
Finished May 14 12:56:41 PM PDT 24
Peak memory 218840 kb
Host smart-46e7c12b-70e4-4193-88c5-d9218bf534e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222107053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2222107053
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.540056798
Short name T258
Test name
Test status
Simulation time 3599046852 ps
CPU time 22.94 seconds
Started May 14 12:55:38 PM PDT 24
Finished May 14 12:56:04 PM PDT 24
Peak memory 212020 kb
Host smart-2f86edf1-cab3-4845-8ca1-6c736e302184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540056798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.540056798
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.455640935
Short name T186
Test name
Test status
Simulation time 6562238994 ps
CPU time 222.74 seconds
Started May 14 12:55:36 PM PDT 24
Finished May 14 12:59:20 PM PDT 24
Peak memory 217100 kb
Host smart-1f9c6e5b-4ef3-4088-aaa1-e56ce85ebe83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455640935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.455640935
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3985193789
Short name T211
Test name
Test status
Simulation time 59399765884 ps
CPU time 65.65 seconds
Started May 14 12:55:41 PM PDT 24
Finished May 14 12:56:48 PM PDT 24
Peak memory 215036 kb
Host smart-84be2458-b35b-4799-8d3c-33f4280d198b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985193789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3985193789
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3025512703
Short name T254
Test name
Test status
Simulation time 13499525051 ps
CPU time 22.13 seconds
Started May 14 12:55:36 PM PDT 24
Finished May 14 12:55:59 PM PDT 24
Peak memory 211712 kb
Host smart-5b96b28a-e70b-4c62-a5cd-dd7e84c11a05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3025512703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3025512703
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2583557706
Short name T139
Test name
Test status
Simulation time 32977554389 ps
CPU time 63.89 seconds
Started May 14 12:55:52 PM PDT 24
Finished May 14 12:56:58 PM PDT 24
Peak memory 217064 kb
Host smart-f5bb2416-4966-465e-b219-764716436344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583557706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2583557706
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.4089865212
Short name T342
Test name
Test status
Simulation time 32628756841 ps
CPU time 191.12 seconds
Started May 14 12:55:36 PM PDT 24
Finished May 14 12:58:49 PM PDT 24
Peak memory 222596 kb
Host smart-7b594fde-f5d2-43a5-9f09-5468321021db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089865212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.4089865212
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1798277655
Short name T194
Test name
Test status
Simulation time 1850423021 ps
CPU time 14.25 seconds
Started May 14 12:55:36 PM PDT 24
Finished May 14 12:55:52 PM PDT 24
Peak memory 211940 kb
Host smart-df5d60c1-29e1-4284-844a-4658ee722f00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798277655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1798277655
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3006107000
Short name T314
Test name
Test status
Simulation time 8894635680 ps
CPU time 208.48 seconds
Started May 14 12:55:40 PM PDT 24
Finished May 14 12:59:11 PM PDT 24
Peak memory 240188 kb
Host smart-cbcfdf21-60c9-41c8-80ca-66cf922863fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006107000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3006107000
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3712226553
Short name T151
Test name
Test status
Simulation time 30365063482 ps
CPU time 54.1 seconds
Started May 14 12:55:42 PM PDT 24
Finished May 14 12:56:38 PM PDT 24
Peak memory 215116 kb
Host smart-1eafee65-a100-46b1-bbdf-e871988e5e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712226553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3712226553
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3726835659
Short name T277
Test name
Test status
Simulation time 22473891155 ps
CPU time 34.66 seconds
Started May 14 12:55:44 PM PDT 24
Finished May 14 12:56:19 PM PDT 24
Peak memory 212708 kb
Host smart-257cc106-1efb-4968-b5fd-a245b5d3c355
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3726835659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3726835659
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2208291167
Short name T171
Test name
Test status
Simulation time 9579473966 ps
CPU time 39.31 seconds
Started May 14 12:55:32 PM PDT 24
Finished May 14 12:56:12 PM PDT 24
Peak memory 218100 kb
Host smart-10388182-1965-4a5a-a585-f5741c73be94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208291167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2208291167
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2705826620
Short name T325
Test name
Test status
Simulation time 16412547265 ps
CPU time 81.21 seconds
Started May 14 12:55:45 PM PDT 24
Finished May 14 12:57:08 PM PDT 24
Peak memory 217336 kb
Host smart-6722cd01-1524-4fa2-8f69-a1c2b527ae0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705826620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2705826620
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.203743323
Short name T222
Test name
Test status
Simulation time 172738724 ps
CPU time 8.29 seconds
Started May 14 12:55:36 PM PDT 24
Finished May 14 12:55:46 PM PDT 24
Peak memory 211360 kb
Host smart-9919df70-7d26-46ff-a02d-3768ff407246
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203743323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.203743323
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1576699741
Short name T169
Test name
Test status
Simulation time 79091335051 ps
CPU time 617.46 seconds
Started May 14 12:55:36 PM PDT 24
Finished May 14 01:05:55 PM PDT 24
Peak memory 217108 kb
Host smart-ee92e93e-f129-426b-a5ad-7995b03ccc6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576699741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1576699741
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.867739864
Short name T170
Test name
Test status
Simulation time 25599543083 ps
CPU time 56.89 seconds
Started May 14 12:55:39 PM PDT 24
Finished May 14 12:56:38 PM PDT 24
Peak memory 215372 kb
Host smart-cb2452cb-cbb4-4b37-a406-e002a51985ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867739864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.867739864
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1516297881
Short name T348
Test name
Test status
Simulation time 23163898048 ps
CPU time 75.1 seconds
Started May 14 12:55:32 PM PDT 24
Finished May 14 12:56:48 PM PDT 24
Peak memory 218320 kb
Host smart-7adf96bd-df95-4a07-82f6-8cb77c737664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516297881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1516297881
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3069629944
Short name T251
Test name
Test status
Simulation time 2843761390 ps
CPU time 26.8 seconds
Started May 14 12:55:33 PM PDT 24
Finished May 14 12:56:01 PM PDT 24
Peak memory 213744 kb
Host smart-94c68d9b-e2e3-439c-b80b-110ccd5c89f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069629944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3069629944
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2346487526
Short name T55
Test name
Test status
Simulation time 13800277517 ps
CPU time 252.33 seconds
Started May 14 12:55:39 PM PDT 24
Finished May 14 12:59:54 PM PDT 24
Peak memory 234564 kb
Host smart-b4433aad-8a64-4451-a9f5-4bd51dfaee47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346487526 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.2346487526
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.900914065
Short name T253
Test name
Test status
Simulation time 167594529 ps
CPU time 8.41 seconds
Started May 14 12:55:41 PM PDT 24
Finished May 14 12:55:51 PM PDT 24
Peak memory 211284 kb
Host smart-461ff4fc-15eb-417b-9767-6d1902918b64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900914065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.900914065
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1524722244
Short name T265
Test name
Test status
Simulation time 62525137640 ps
CPU time 483.12 seconds
Started May 14 12:55:49 PM PDT 24
Finished May 14 01:03:53 PM PDT 24
Peak memory 238416 kb
Host smart-46a02234-bb32-4681-a616-a8e112938be1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524722244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1524722244
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2154029631
Short name T275
Test name
Test status
Simulation time 15110247319 ps
CPU time 42.32 seconds
Started May 14 12:55:37 PM PDT 24
Finished May 14 12:56:21 PM PDT 24
Peak memory 215088 kb
Host smart-24f38c7d-bf02-4047-955a-988e9aad97bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154029631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2154029631
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.632823838
Short name T315
Test name
Test status
Simulation time 6440946499 ps
CPU time 21.06 seconds
Started May 14 12:55:35 PM PDT 24
Finished May 14 12:55:57 PM PDT 24
Peak memory 212776 kb
Host smart-7d1bff6b-d7e0-46df-801c-24187adf8268
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=632823838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.632823838
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2315969796
Short name T284
Test name
Test status
Simulation time 23591945892 ps
CPU time 63.4 seconds
Started May 14 12:55:34 PM PDT 24
Finished May 14 12:56:39 PM PDT 24
Peak memory 217444 kb
Host smart-04be3453-8185-484c-9420-ab602a650c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315969796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2315969796
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.901903909
Short name T359
Test name
Test status
Simulation time 46683332165 ps
CPU time 120.92 seconds
Started May 14 12:55:39 PM PDT 24
Finished May 14 12:57:42 PM PDT 24
Peak memory 220912 kb
Host smart-f1317310-8f26-44ce-8095-b9c65a96b549
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901903909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.901903909
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3061279220
Short name T8
Test name
Test status
Simulation time 174672285 ps
CPU time 8.07 seconds
Started May 14 12:55:49 PM PDT 24
Finished May 14 12:55:58 PM PDT 24
Peak memory 211344 kb
Host smart-b6796204-7820-4f52-82ff-c77014382733
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061279220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3061279220
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1485322211
Short name T117
Test name
Test status
Simulation time 106154868471 ps
CPU time 498.37 seconds
Started May 14 12:55:46 PM PDT 24
Finished May 14 01:04:06 PM PDT 24
Peak memory 237988 kb
Host smart-9d02c142-5325-41d6-89e2-4e7c034ec8c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485322211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1485322211
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2960663619
Short name T125
Test name
Test status
Simulation time 6862860766 ps
CPU time 59.96 seconds
Started May 14 12:55:42 PM PDT 24
Finished May 14 12:56:44 PM PDT 24
Peak memory 215064 kb
Host smart-e9cf526e-3642-48f3-86ea-8dcd27003434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960663619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2960663619
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3258377981
Short name T175
Test name
Test status
Simulation time 187009689 ps
CPU time 10.63 seconds
Started May 14 12:55:38 PM PDT 24
Finished May 14 12:55:51 PM PDT 24
Peak memory 212360 kb
Host smart-253e6b50-50de-4bb0-aa27-07314e019b83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3258377981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3258377981
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.249322471
Short name T353
Test name
Test status
Simulation time 341825678 ps
CPU time 20.01 seconds
Started May 14 12:55:37 PM PDT 24
Finished May 14 12:56:00 PM PDT 24
Peak memory 216340 kb
Host smart-c11ffd0c-5331-4ca9-832c-d64e0a68eb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249322471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.249322471
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.956194235
Short name T121
Test name
Test status
Simulation time 24142466328 ps
CPU time 55.51 seconds
Started May 14 12:55:46 PM PDT 24
Finished May 14 12:56:43 PM PDT 24
Peak memory 218904 kb
Host smart-d31e6ab4-a349-48e1-9a6c-fd92669cdb28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956194235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.956194235
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1682408719
Short name T130
Test name
Test status
Simulation time 360526546 ps
CPU time 8.31 seconds
Started May 14 12:55:44 PM PDT 24
Finished May 14 12:55:53 PM PDT 24
Peak memory 211336 kb
Host smart-45f546ec-c18f-44af-b8e6-486356bdf466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682408719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1682408719
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3329067190
Short name T44
Test name
Test status
Simulation time 9997286903 ps
CPU time 189.3 seconds
Started May 14 12:55:37 PM PDT 24
Finished May 14 12:58:49 PM PDT 24
Peak memory 240536 kb
Host smart-88bbbba2-7009-484f-818e-e4a3e2a4ffe2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329067190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3329067190
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3967108457
Short name T142
Test name
Test status
Simulation time 7592019909 ps
CPU time 50.31 seconds
Started May 14 12:55:36 PM PDT 24
Finished May 14 12:56:29 PM PDT 24
Peak memory 212980 kb
Host smart-7430b996-8ae0-4581-93f4-2d0c221098c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967108457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3967108457
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1327089530
Short name T347
Test name
Test status
Simulation time 13001165440 ps
CPU time 28.85 seconds
Started May 14 12:55:38 PM PDT 24
Finished May 14 12:56:10 PM PDT 24
Peak memory 212892 kb
Host smart-8de53b84-5435-4d0b-8864-e3770bf31160
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1327089530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1327089530
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3637901438
Short name T131
Test name
Test status
Simulation time 59321166709 ps
CPU time 74.06 seconds
Started May 14 12:55:40 PM PDT 24
Finished May 14 12:56:56 PM PDT 24
Peak memory 217620 kb
Host smart-666e7199-ccc6-4d33-bb78-5654ee5d74d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637901438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3637901438
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.867935796
Short name T280
Test name
Test status
Simulation time 529624484 ps
CPU time 26.95 seconds
Started May 14 12:55:33 PM PDT 24
Finished May 14 12:56:02 PM PDT 24
Peak memory 216936 kb
Host smart-f0d8841a-9f01-439e-906b-4cc0171691c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867935796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.867935796
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1690211174
Short name T141
Test name
Test status
Simulation time 1372462908 ps
CPU time 12.85 seconds
Started May 14 12:55:38 PM PDT 24
Finished May 14 12:55:54 PM PDT 24
Peak memory 211276 kb
Host smart-ff0041ab-9d35-43af-9313-1c22a8114757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690211174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1690211174
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4120061293
Short name T27
Test name
Test status
Simulation time 67808780561 ps
CPU time 695.42 seconds
Started May 14 12:55:46 PM PDT 24
Finished May 14 01:07:23 PM PDT 24
Peak memory 239428 kb
Host smart-551cc1e1-6cfa-48a3-8a7c-d1d3e5472908
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120061293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.4120061293
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2986112533
Short name T281
Test name
Test status
Simulation time 13027745852 ps
CPU time 55.8 seconds
Started May 14 12:55:49 PM PDT 24
Finished May 14 12:56:47 PM PDT 24
Peak memory 215408 kb
Host smart-27bd06a0-cbbe-441b-a01d-17690b773fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986112533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2986112533
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.479284083
Short name T199
Test name
Test status
Simulation time 6517848494 ps
CPU time 28.47 seconds
Started May 14 12:55:35 PM PDT 24
Finished May 14 12:56:05 PM PDT 24
Peak memory 212460 kb
Host smart-97731f23-3aa2-4648-8c10-8a1991f0490d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=479284083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.479284083
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3701625706
Short name T36
Test name
Test status
Simulation time 22032349165 ps
CPU time 47.08 seconds
Started May 14 12:55:33 PM PDT 24
Finished May 14 12:56:22 PM PDT 24
Peak memory 217116 kb
Host smart-5d5a6910-3bc3-4f9a-9ffc-4c45f265e313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701625706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3701625706
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1617169793
Short name T322
Test name
Test status
Simulation time 57176593720 ps
CPU time 132.48 seconds
Started May 14 12:55:36 PM PDT 24
Finished May 14 12:57:51 PM PDT 24
Peak memory 221072 kb
Host smart-ae3983f1-55dc-4559-8903-9f496b6d1cfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617169793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1617169793
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3538886310
Short name T38
Test name
Test status
Simulation time 3037808466 ps
CPU time 17.85 seconds
Started May 14 12:55:36 PM PDT 24
Finished May 14 12:55:56 PM PDT 24
Peak memory 211460 kb
Host smart-92bc1e03-50b0-4c83-ac92-b761ed7d7669
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538886310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3538886310
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.784781984
Short name T328
Test name
Test status
Simulation time 18843321468 ps
CPU time 224.55 seconds
Started May 14 12:55:44 PM PDT 24
Finished May 14 12:59:30 PM PDT 24
Peak memory 237872 kb
Host smart-651c7ac6-d888-4e48-a855-71bb09ca103e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784781984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.784781984
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1246847763
Short name T339
Test name
Test status
Simulation time 23434878793 ps
CPU time 40.18 seconds
Started May 14 12:55:34 PM PDT 24
Finished May 14 12:56:15 PM PDT 24
Peak memory 215108 kb
Host smart-28da0758-bdde-456b-8296-36f788b9308f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246847763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1246847763
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3123682727
Short name T294
Test name
Test status
Simulation time 11475280202 ps
CPU time 27.47 seconds
Started May 14 12:55:47 PM PDT 24
Finished May 14 12:56:16 PM PDT 24
Peak memory 212744 kb
Host smart-b58a09ed-2c8a-4891-871f-ee8b6e795e0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3123682727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3123682727
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.91166817
Short name T202
Test name
Test status
Simulation time 7602409515 ps
CPU time 62.21 seconds
Started May 14 12:55:42 PM PDT 24
Finished May 14 12:56:46 PM PDT 24
Peak memory 217284 kb
Host smart-b30278fa-9b19-41d7-93ec-87089070b6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91166817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.91166817
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1363848748
Short name T14
Test name
Test status
Simulation time 9018811877 ps
CPU time 24.12 seconds
Started May 14 12:55:39 PM PDT 24
Finished May 14 12:56:06 PM PDT 24
Peak memory 213680 kb
Host smart-71b15ce4-a85b-497b-a8da-03cef987b789
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363848748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1363848748
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3175116798
Short name T148
Test name
Test status
Simulation time 3990485374 ps
CPU time 32.07 seconds
Started May 14 12:55:37 PM PDT 24
Finished May 14 12:56:11 PM PDT 24
Peak memory 211968 kb
Host smart-04004b2c-2108-47b0-9c68-487718105097
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175116798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3175116798
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1365930638
Short name T200
Test name
Test status
Simulation time 9241459940 ps
CPU time 181.14 seconds
Started May 14 12:56:01 PM PDT 24
Finished May 14 12:59:04 PM PDT 24
Peak memory 239596 kb
Host smart-7a447039-4c6b-4f7b-8e04-14496c997fd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365930638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1365930638
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3047632119
Short name T260
Test name
Test status
Simulation time 10912219775 ps
CPU time 32.25 seconds
Started May 14 12:55:37 PM PDT 24
Finished May 14 12:56:11 PM PDT 24
Peak memory 214372 kb
Host smart-fac70466-2d53-439e-b9f6-297ebfcef382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047632119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3047632119
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.415729236
Short name T220
Test name
Test status
Simulation time 175966620 ps
CPU time 10.01 seconds
Started May 14 12:55:43 PM PDT 24
Finished May 14 12:55:55 PM PDT 24
Peak memory 212260 kb
Host smart-d200d616-b86e-46ec-89e5-1d876f9923b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=415729236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.415729236
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3635145741
Short name T269
Test name
Test status
Simulation time 359638967 ps
CPU time 19.89 seconds
Started May 14 12:55:52 PM PDT 24
Finished May 14 12:56:13 PM PDT 24
Peak memory 216604 kb
Host smart-4c53e462-549c-4684-99a3-db46d9d9b15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635145741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3635145741
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.767737600
Short name T193
Test name
Test status
Simulation time 24222804332 ps
CPU time 104.94 seconds
Started May 14 12:55:38 PM PDT 24
Finished May 14 12:57:25 PM PDT 24
Peak memory 219288 kb
Host smart-07d11d80-6d9b-4fc5-b172-b5becd8e9336
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767737600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.767737600
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1176952895
Short name T140
Test name
Test status
Simulation time 6532584594 ps
CPU time 27.62 seconds
Started May 14 12:55:25 PM PDT 24
Finished May 14 12:55:53 PM PDT 24
Peak memory 211404 kb
Host smart-a119d626-f2cc-49b2-98ce-2aafde3ff3f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176952895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1176952895
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3643629697
Short name T290
Test name
Test status
Simulation time 145600804962 ps
CPU time 531.44 seconds
Started May 14 12:55:34 PM PDT 24
Finished May 14 01:04:27 PM PDT 24
Peak memory 240492 kb
Host smart-4a53b201-4934-46a4-a43a-2625fc143dc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643629697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3643629697
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2397146904
Short name T330
Test name
Test status
Simulation time 11783890749 ps
CPU time 61.07 seconds
Started May 14 12:55:18 PM PDT 24
Finished May 14 12:56:23 PM PDT 24
Peak memory 214060 kb
Host smart-637ab15c-f877-4872-9b7c-d5f691357c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397146904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2397146904
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.951305179
Short name T243
Test name
Test status
Simulation time 4195536592 ps
CPU time 35.37 seconds
Started May 14 12:55:38 PM PDT 24
Finished May 14 12:56:15 PM PDT 24
Peak memory 211268 kb
Host smart-1c321e4b-ff43-4d57-9586-db66baf300dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=951305179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.951305179
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2058970674
Short name T35
Test name
Test status
Simulation time 2919181542 ps
CPU time 134.53 seconds
Started May 14 12:55:47 PM PDT 24
Finished May 14 12:58:03 PM PDT 24
Peak memory 238388 kb
Host smart-6d099b2c-1ed0-45a9-af7f-079a568c5c17
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058970674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2058970674
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3945468879
Short name T76
Test name
Test status
Simulation time 53769607070 ps
CPU time 77.22 seconds
Started May 14 12:55:17 PM PDT 24
Finished May 14 12:56:39 PM PDT 24
Peak memory 215556 kb
Host smart-05edce05-3de1-4935-98ee-e3a62595c7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945468879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3945468879
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3717673441
Short name T156
Test name
Test status
Simulation time 101711636582 ps
CPU time 248.22 seconds
Started May 14 12:55:23 PM PDT 24
Finished May 14 12:59:32 PM PDT 24
Peak memory 221828 kb
Host smart-f54b8261-292a-4d36-89a7-1f6d290d98a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717673441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3717673441
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1675123399
Short name T4
Test name
Test status
Simulation time 2756847500 ps
CPU time 25.36 seconds
Started May 14 12:55:50 PM PDT 24
Finished May 14 12:56:18 PM PDT 24
Peak memory 212300 kb
Host smart-fea05092-14ed-4d7d-902f-ab1c83736c2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675123399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1675123399
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3047966105
Short name T266
Test name
Test status
Simulation time 348086304447 ps
CPU time 712.04 seconds
Started May 14 12:55:46 PM PDT 24
Finished May 14 01:07:40 PM PDT 24
Peak memory 233952 kb
Host smart-82ff7d14-f75e-4465-a2b2-71dfb2226ac9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047966105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3047966105
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.4226331343
Short name T229
Test name
Test status
Simulation time 2633575489 ps
CPU time 35.82 seconds
Started May 14 12:55:40 PM PDT 24
Finished May 14 12:56:18 PM PDT 24
Peak memory 215088 kb
Host smart-ce6c1792-2508-4e23-9a93-317ba23818f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226331343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.4226331343
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.570825578
Short name T311
Test name
Test status
Simulation time 692881637 ps
CPU time 10.28 seconds
Started May 14 12:55:42 PM PDT 24
Finished May 14 12:55:54 PM PDT 24
Peak memory 212116 kb
Host smart-aabc1334-341a-4676-9296-e3d167888683
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=570825578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.570825578
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.517184176
Short name T205
Test name
Test status
Simulation time 22592240008 ps
CPU time 34.36 seconds
Started May 14 12:55:37 PM PDT 24
Finished May 14 12:56:13 PM PDT 24
Peak memory 216924 kb
Host smart-f0506bfc-8fa8-44cf-908e-46dc3cb21d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517184176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.517184176
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3349228631
Short name T77
Test name
Test status
Simulation time 1752421755 ps
CPU time 65.42 seconds
Started May 14 12:55:50 PM PDT 24
Finished May 14 12:56:58 PM PDT 24
Peak memory 219268 kb
Host smart-0981ba05-3f0c-46b7-8e1c-b89f2f9620d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349228631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3349228631
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.887579395
Short name T239
Test name
Test status
Simulation time 2055397889 ps
CPU time 20.83 seconds
Started May 14 12:55:56 PM PDT 24
Finished May 14 12:56:18 PM PDT 24
Peak memory 211100 kb
Host smart-1fe20c11-2f8b-407a-8b74-c199e2397c00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887579395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.887579395
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.951294805
Short name T22
Test name
Test status
Simulation time 283626451751 ps
CPU time 695.74 seconds
Started May 14 12:55:50 PM PDT 24
Finished May 14 01:07:28 PM PDT 24
Peak memory 216744 kb
Host smart-d8d8a134-741b-4d35-81b8-e03995b075be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951294805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.951294805
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4075475975
Short name T228
Test name
Test status
Simulation time 13024250640 ps
CPU time 56.83 seconds
Started May 14 12:55:59 PM PDT 24
Finished May 14 12:56:57 PM PDT 24
Peak memory 215312 kb
Host smart-c5ebe8bf-8ef7-4595-b11c-0243271871c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075475975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4075475975
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3197866430
Short name T39
Test name
Test status
Simulation time 5259098476 ps
CPU time 18.11 seconds
Started May 14 12:55:40 PM PDT 24
Finished May 14 12:56:01 PM PDT 24
Peak memory 212764 kb
Host smart-18382ada-d4f3-46e9-9449-70ded4a8f11b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3197866430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3197866430
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2670859601
Short name T226
Test name
Test status
Simulation time 363526904 ps
CPU time 20.83 seconds
Started May 14 12:55:43 PM PDT 24
Finished May 14 12:56:05 PM PDT 24
Peak memory 215528 kb
Host smart-7f3e22d2-ac40-4177-ad81-1d358d8cff36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670859601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2670859601
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3930611563
Short name T196
Test name
Test status
Simulation time 128494500214 ps
CPU time 135.01 seconds
Started May 14 12:55:39 PM PDT 24
Finished May 14 12:57:57 PM PDT 24
Peak memory 220056 kb
Host smart-9aafc2a8-d719-401b-9466-635f8c8df889
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930611563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3930611563
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1266525365
Short name T146
Test name
Test status
Simulation time 2984554727 ps
CPU time 13.66 seconds
Started May 14 12:55:35 PM PDT 24
Finished May 14 12:55:50 PM PDT 24
Peak memory 211504 kb
Host smart-d0595365-7002-4829-981e-01f612e29211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266525365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1266525365
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2150425020
Short name T50
Test name
Test status
Simulation time 25008382114 ps
CPU time 254.4 seconds
Started May 14 12:55:52 PM PDT 24
Finished May 14 01:00:09 PM PDT 24
Peak memory 236748 kb
Host smart-7ce7ba6a-fe9b-4eee-8052-4d3e0a99fabe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150425020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2150425020
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4074404240
Short name T303
Test name
Test status
Simulation time 42536976775 ps
CPU time 59.02 seconds
Started May 14 12:55:39 PM PDT 24
Finished May 14 12:56:41 PM PDT 24
Peak memory 214104 kb
Host smart-9a499592-2e5e-4547-b25f-0ecde0d81389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074404240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4074404240
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2347704603
Short name T286
Test name
Test status
Simulation time 1027398893 ps
CPU time 13.53 seconds
Started May 14 12:55:39 PM PDT 24
Finished May 14 12:55:55 PM PDT 24
Peak memory 211368 kb
Host smart-ee266dfc-ee6f-47f5-a430-026245ce2299
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2347704603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2347704603
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.3147420716
Short name T299
Test name
Test status
Simulation time 5932125149 ps
CPU time 59.05 seconds
Started May 14 12:55:40 PM PDT 24
Finished May 14 12:56:41 PM PDT 24
Peak memory 217436 kb
Host smart-bfd4786d-4547-4d83-b679-39132657e414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147420716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3147420716
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1402445974
Short name T319
Test name
Test status
Simulation time 32203508554 ps
CPU time 306.45 seconds
Started May 14 12:55:39 PM PDT 24
Finished May 14 01:00:48 PM PDT 24
Peak memory 220848 kb
Host smart-5b5bd3a2-984f-4712-ab48-e7afbdeee385
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402445974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1402445974
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2610198637
Short name T263
Test name
Test status
Simulation time 4308476816 ps
CPU time 31.25 seconds
Started May 14 12:55:40 PM PDT 24
Finished May 14 12:56:13 PM PDT 24
Peak memory 212272 kb
Host smart-dfd215eb-33eb-44fd-a0cf-8c4fb7d91f6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610198637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2610198637
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3004584361
Short name T221
Test name
Test status
Simulation time 8376463479 ps
CPU time 125.16 seconds
Started May 14 12:55:50 PM PDT 24
Finished May 14 12:57:57 PM PDT 24
Peak memory 233924 kb
Host smart-3c65dc05-8f57-4859-accc-69a27ddd3f22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004584361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3004584361
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3447100979
Short name T335
Test name
Test status
Simulation time 2745912335 ps
CPU time 24.29 seconds
Started May 14 12:55:53 PM PDT 24
Finished May 14 12:56:19 PM PDT 24
Peak memory 215584 kb
Host smart-0667d141-2d68-4580-b92c-b1bd1f47f639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447100979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3447100979
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.115299266
Short name T147
Test name
Test status
Simulation time 11079959735 ps
CPU time 17.08 seconds
Started May 14 12:55:37 PM PDT 24
Finished May 14 12:55:57 PM PDT 24
Peak memory 211768 kb
Host smart-7570098a-a2c8-4b38-8a5c-96d0d100db1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=115299266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.115299266
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.50966122
Short name T187
Test name
Test status
Simulation time 15981155604 ps
CPU time 61.94 seconds
Started May 14 12:55:37 PM PDT 24
Finished May 14 12:56:42 PM PDT 24
Peak memory 217756 kb
Host smart-e3e19821-c327-4f08-bdd7-4ab4c33754b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50966122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.50966122
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2054629842
Short name T327
Test name
Test status
Simulation time 561334421 ps
CPU time 44.45 seconds
Started May 14 12:55:44 PM PDT 24
Finished May 14 12:56:30 PM PDT 24
Peak memory 219136 kb
Host smart-1e71e63e-706d-4d84-a047-76bec3d270f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054629842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2054629842
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2213586865
Short name T37
Test name
Test status
Simulation time 4045422196 ps
CPU time 30.9 seconds
Started May 14 12:56:09 PM PDT 24
Finished May 14 12:56:44 PM PDT 24
Peak memory 211788 kb
Host smart-81721291-1658-400f-be7e-aa15b2aea84e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213586865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2213586865
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2405327986
Short name T185
Test name
Test status
Simulation time 6828728496 ps
CPU time 167.2 seconds
Started May 14 12:55:37 PM PDT 24
Finished May 14 12:58:26 PM PDT 24
Peak memory 240708 kb
Host smart-2dcedc75-14f8-4857-85bf-e79295bf57bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405327986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2405327986
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3422902392
Short name T317
Test name
Test status
Simulation time 9535556402 ps
CPU time 49.91 seconds
Started May 14 12:55:38 PM PDT 24
Finished May 14 12:56:34 PM PDT 24
Peak memory 214916 kb
Host smart-e9494113-db44-4a55-bdc1-05218817ae7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422902392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3422902392
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2035605519
Short name T16
Test name
Test status
Simulation time 3415242358 ps
CPU time 15.21 seconds
Started May 14 12:55:57 PM PDT 24
Finished May 14 12:56:13 PM PDT 24
Peak memory 212664 kb
Host smart-a53788cc-87fa-4e86-833b-948b099f76a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2035605519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2035605519
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3497892777
Short name T318
Test name
Test status
Simulation time 10619103192 ps
CPU time 53.73 seconds
Started May 14 12:55:40 PM PDT 24
Finished May 14 12:56:36 PM PDT 24
Peak memory 216300 kb
Host smart-38927bb4-7f3f-4ca4-8b1f-9a7178cb9bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497892777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3497892777
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3776911949
Short name T12
Test name
Test status
Simulation time 7018845441 ps
CPU time 74.25 seconds
Started May 14 12:55:58 PM PDT 24
Finished May 14 12:57:13 PM PDT 24
Peak memory 219448 kb
Host smart-c6d5717a-7289-49df-a047-ffde28c27a18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776911949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3776911949
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3680638487
Short name T230
Test name
Test status
Simulation time 30102787935 ps
CPU time 24.92 seconds
Started May 14 12:55:56 PM PDT 24
Finished May 14 12:56:22 PM PDT 24
Peak memory 211484 kb
Host smart-3b440968-1f59-4cdd-baff-da222d3f817f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680638487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3680638487
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.4143595335
Short name T154
Test name
Test status
Simulation time 49862383314 ps
CPU time 456.1 seconds
Started May 14 12:55:40 PM PDT 24
Finished May 14 01:03:19 PM PDT 24
Peak memory 237780 kb
Host smart-dd3bfa37-3bf0-455b-85fd-af834ea6820a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143595335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.4143595335
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2633742711
Short name T45
Test name
Test status
Simulation time 8010399188 ps
CPU time 66.06 seconds
Started May 14 12:55:45 PM PDT 24
Finished May 14 12:56:52 PM PDT 24
Peak memory 215424 kb
Host smart-31c635c8-40d8-412d-aee2-f0cc39abfe03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633742711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2633742711
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.238844597
Short name T163
Test name
Test status
Simulation time 2748887983 ps
CPU time 25.92 seconds
Started May 14 12:55:49 PM PDT 24
Finished May 14 12:56:17 PM PDT 24
Peak memory 212292 kb
Host smart-64e5276e-5468-4c3e-bb8f-fb8034c16340
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=238844597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.238844597
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2836294127
Short name T80
Test name
Test status
Simulation time 911975714 ps
CPU time 20.43 seconds
Started May 14 12:55:39 PM PDT 24
Finished May 14 12:56:02 PM PDT 24
Peak memory 217100 kb
Host smart-57d75ef9-6e3f-48b0-92e8-3b02d622e82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836294127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2836294127
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1693535885
Short name T10
Test name
Test status
Simulation time 3087961472 ps
CPU time 42.94 seconds
Started May 14 12:55:59 PM PDT 24
Finished May 14 12:56:44 PM PDT 24
Peak memory 219636 kb
Host smart-28b3a10b-723b-480c-8773-723b55f7c5e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693535885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1693535885
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3042709119
Short name T354
Test name
Test status
Simulation time 34463947205 ps
CPU time 28.4 seconds
Started May 14 12:55:45 PM PDT 24
Finished May 14 12:56:14 PM PDT 24
Peak memory 212308 kb
Host smart-92047e55-d3a7-474a-bab7-205c895f87bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042709119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3042709119
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.558096281
Short name T137
Test name
Test status
Simulation time 6831821297 ps
CPU time 111.75 seconds
Started May 14 12:55:56 PM PDT 24
Finished May 14 12:57:49 PM PDT 24
Peak memory 216596 kb
Host smart-96ed38fa-3d0f-4da9-9ab5-d339372eca14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558096281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.558096281
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4281076373
Short name T20
Test name
Test status
Simulation time 1807134747 ps
CPU time 31.66 seconds
Started May 14 12:55:39 PM PDT 24
Finished May 14 12:56:13 PM PDT 24
Peak memory 212668 kb
Host smart-fd0542a8-d278-40e2-957e-8c3ae07e84c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281076373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4281076373
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.4179930794
Short name T119
Test name
Test status
Simulation time 32818604034 ps
CPU time 33.96 seconds
Started May 14 12:55:38 PM PDT 24
Finished May 14 12:56:14 PM PDT 24
Peak memory 211392 kb
Host smart-263d64c5-f7fb-4654-8a91-8f109ea10f96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4179930794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.4179930794
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3649502967
Short name T224
Test name
Test status
Simulation time 21935664972 ps
CPU time 47.5 seconds
Started May 14 12:55:48 PM PDT 24
Finished May 14 12:56:37 PM PDT 24
Peak memory 216572 kb
Host smart-542b6093-0e69-4109-aec0-d282af9d22c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649502967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3649502967
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1492536986
Short name T182
Test name
Test status
Simulation time 54811151959 ps
CPU time 64.88 seconds
Started May 14 12:55:51 PM PDT 24
Finished May 14 12:56:58 PM PDT 24
Peak memory 218896 kb
Host smart-eb881d03-5c13-474f-ab22-150d97981924
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492536986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1492536986
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.619244507
Short name T227
Test name
Test status
Simulation time 3941738428 ps
CPU time 32.12 seconds
Started May 14 12:55:44 PM PDT 24
Finished May 14 12:56:18 PM PDT 24
Peak memory 211848 kb
Host smart-63b250fc-d734-4d80-88a1-ed787657ac5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619244507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.619244507
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.4004264123
Short name T341
Test name
Test status
Simulation time 9583693504 ps
CPU time 164.32 seconds
Started May 14 12:55:53 PM PDT 24
Finished May 14 12:58:39 PM PDT 24
Peak memory 239768 kb
Host smart-f5028951-b9ff-4482-a706-dcfb7b71e49a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004264123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.4004264123
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2029340355
Short name T237
Test name
Test status
Simulation time 2631549573 ps
CPU time 28.76 seconds
Started May 14 12:55:56 PM PDT 24
Finished May 14 12:56:25 PM PDT 24
Peak memory 213764 kb
Host smart-fb1b3dba-0e51-4fce-bf5e-7fe1c7f39a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029340355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2029340355
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.550689932
Short name T358
Test name
Test status
Simulation time 11093923571 ps
CPU time 26.72 seconds
Started May 14 12:55:47 PM PDT 24
Finished May 14 12:56:16 PM PDT 24
Peak memory 211792 kb
Host smart-5923eb11-cdcb-4f2e-8728-c7fb88a68477
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=550689932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.550689932
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1841120229
Short name T190
Test name
Test status
Simulation time 13017616443 ps
CPU time 42.87 seconds
Started May 14 12:56:00 PM PDT 24
Finished May 14 12:56:44 PM PDT 24
Peak memory 217444 kb
Host smart-e402bccf-37ea-4dc9-90c0-982cb1a7165f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841120229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1841120229
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1243983707
Short name T120
Test name
Test status
Simulation time 740754506 ps
CPU time 44.09 seconds
Started May 14 12:55:56 PM PDT 24
Finished May 14 12:56:41 PM PDT 24
Peak memory 219308 kb
Host smart-8e497e27-15b2-4b90-995f-21798b9729a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243983707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1243983707
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3128497752
Short name T238
Test name
Test status
Simulation time 17037471417 ps
CPU time 31.76 seconds
Started May 14 12:55:58 PM PDT 24
Finished May 14 12:56:30 PM PDT 24
Peak memory 212228 kb
Host smart-ae3865a5-f36c-47a6-963a-3ce5e098a7b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128497752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3128497752
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2606200645
Short name T176
Test name
Test status
Simulation time 217680575729 ps
CPU time 1011.17 seconds
Started May 14 12:56:03 PM PDT 24
Finished May 14 01:12:57 PM PDT 24
Peak memory 239984 kb
Host smart-d1302a3f-35a4-4af3-ac15-c660399c4361
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606200645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2606200645
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3272073029
Short name T285
Test name
Test status
Simulation time 3111099253 ps
CPU time 38.45 seconds
Started May 14 12:56:03 PM PDT 24
Finished May 14 12:56:45 PM PDT 24
Peak memory 214856 kb
Host smart-341caaf6-b076-4f89-96f0-84cd3bfbc398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272073029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3272073029
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3412884964
Short name T103
Test name
Test status
Simulation time 3966320118 ps
CPU time 22.62 seconds
Started May 14 12:55:43 PM PDT 24
Finished May 14 12:56:07 PM PDT 24
Peak memory 211264 kb
Host smart-30db0b76-13ac-488d-8f5b-2e93f7c0c802
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3412884964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3412884964
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.379611081
Short name T232
Test name
Test status
Simulation time 4470982422 ps
CPU time 50.91 seconds
Started May 14 12:55:46 PM PDT 24
Finished May 14 12:56:38 PM PDT 24
Peak memory 216440 kb
Host smart-8dd1156c-3714-48ce-9ede-7b7cc8fea220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379611081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.379611081
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.316131455
Short name T132
Test name
Test status
Simulation time 7177215995 ps
CPU time 62.47 seconds
Started May 14 12:55:52 PM PDT 24
Finished May 14 12:56:56 PM PDT 24
Peak memory 220600 kb
Host smart-faaee0ff-c717-429a-b9da-8b98e52a48c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316131455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.316131455
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1065914581
Short name T362
Test name
Test status
Simulation time 2294941001 ps
CPU time 22.46 seconds
Started May 14 12:55:47 PM PDT 24
Finished May 14 12:56:11 PM PDT 24
Peak memory 212080 kb
Host smart-61b11f3c-39a0-4a45-a61d-33c335923a7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065914581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1065914581
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3517831758
Short name T206
Test name
Test status
Simulation time 5210309439 ps
CPU time 132.38 seconds
Started May 14 12:56:06 PM PDT 24
Finished May 14 12:58:22 PM PDT 24
Peak memory 239140 kb
Host smart-2b0d2549-ce73-4605-b5c5-91db34d12d2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517831758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3517831758
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2416159865
Short name T214
Test name
Test status
Simulation time 13461283677 ps
CPU time 55.2 seconds
Started May 14 12:55:51 PM PDT 24
Finished May 14 12:56:48 PM PDT 24
Peak memory 214956 kb
Host smart-6bb1d263-b315-457b-b0d1-44cce7e131ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416159865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2416159865
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.940671034
Short name T329
Test name
Test status
Simulation time 693406209 ps
CPU time 9.86 seconds
Started May 14 12:55:45 PM PDT 24
Finished May 14 12:55:56 PM PDT 24
Peak memory 212504 kb
Host smart-0c772aaf-e128-46bc-8321-cc180d1375d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=940671034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.940671034
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3950105957
Short name T165
Test name
Test status
Simulation time 1465377579 ps
CPU time 19.95 seconds
Started May 14 12:55:47 PM PDT 24
Finished May 14 12:56:08 PM PDT 24
Peak memory 216652 kb
Host smart-cba4e3d4-9189-4b3d-b6ca-1d47f4deaef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950105957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3950105957
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.4282811249
Short name T223
Test name
Test status
Simulation time 18555563623 ps
CPU time 112.26 seconds
Started May 14 12:55:52 PM PDT 24
Finished May 14 12:57:47 PM PDT 24
Peak memory 221808 kb
Host smart-5244ce7e-1d4a-4f4e-b2e3-47374526be71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282811249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.4282811249
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2865817909
Short name T308
Test name
Test status
Simulation time 222702366886 ps
CPU time 4634.81 seconds
Started May 14 12:56:01 PM PDT 24
Finished May 14 02:13:18 PM PDT 24
Peak memory 235960 kb
Host smart-764002a6-d85a-477b-8462-91ed07183a96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865817909 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.2865817909
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2991226153
Short name T184
Test name
Test status
Simulation time 2457454049 ps
CPU time 16.58 seconds
Started May 14 12:55:48 PM PDT 24
Finished May 14 12:56:07 PM PDT 24
Peak memory 211380 kb
Host smart-9289cb75-013e-44e6-947b-352785100cd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991226153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2991226153
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1393692135
Short name T235
Test name
Test status
Simulation time 249701110311 ps
CPU time 634.22 seconds
Started May 14 12:55:28 PM PDT 24
Finished May 14 01:06:03 PM PDT 24
Peak memory 218208 kb
Host smart-507d4326-a2bc-434f-b31f-a9a1529036e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393692135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1393692135
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1937528448
Short name T158
Test name
Test status
Simulation time 2840479648 ps
CPU time 25.92 seconds
Started May 14 12:55:18 PM PDT 24
Finished May 14 12:55:47 PM PDT 24
Peak memory 214816 kb
Host smart-34c2ee8f-a74e-4a92-8929-2e0e95c65c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937528448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1937528448
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3667766360
Short name T255
Test name
Test status
Simulation time 2381320238 ps
CPU time 24.93 seconds
Started May 14 12:55:25 PM PDT 24
Finished May 14 12:55:51 PM PDT 24
Peak memory 211520 kb
Host smart-62de90bc-539a-4dae-93d6-f01b90a4184b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3667766360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3667766360
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3060384974
Short name T34
Test name
Test status
Simulation time 1067431992 ps
CPU time 224.11 seconds
Started May 14 12:55:42 PM PDT 24
Finished May 14 12:59:28 PM PDT 24
Peak memory 238120 kb
Host smart-affb966c-e7fc-495d-b31c-760219f77878
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060384974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3060384974
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2774056047
Short name T313
Test name
Test status
Simulation time 11264368297 ps
CPU time 51.76 seconds
Started May 14 12:55:20 PM PDT 24
Finished May 14 12:56:14 PM PDT 24
Peak memory 217268 kb
Host smart-39bf001b-dcdc-41cb-9563-d2b077bd5264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774056047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2774056047
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2717529595
Short name T201
Test name
Test status
Simulation time 22527265307 ps
CPU time 108.11 seconds
Started May 14 12:55:35 PM PDT 24
Finished May 14 12:57:24 PM PDT 24
Peak memory 219484 kb
Host smart-e4983b2e-ebdd-44f0-8ff1-9d8382be7afe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717529595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2717529595
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.312603444
Short name T123
Test name
Test status
Simulation time 331506427 ps
CPU time 10.68 seconds
Started May 14 12:55:53 PM PDT 24
Finished May 14 12:56:06 PM PDT 24
Peak memory 211332 kb
Host smart-9783e014-cfc0-4e90-856c-a1fec46c6001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312603444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.312603444
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3321558941
Short name T355
Test name
Test status
Simulation time 142191378913 ps
CPU time 452.64 seconds
Started May 14 12:55:46 PM PDT 24
Finished May 14 01:03:21 PM PDT 24
Peak memory 234260 kb
Host smart-b55cd93c-3a1b-4e9c-b607-e69688f23fe8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321558941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3321558941
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3135930025
Short name T136
Test name
Test status
Simulation time 42796855058 ps
CPU time 66.56 seconds
Started May 14 12:55:55 PM PDT 24
Finished May 14 12:57:02 PM PDT 24
Peak memory 215032 kb
Host smart-400793e7-4cc4-4e41-b056-ec7efc43ce51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135930025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3135930025
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3797253641
Short name T241
Test name
Test status
Simulation time 189462228 ps
CPU time 10.89 seconds
Started May 14 12:55:47 PM PDT 24
Finished May 14 12:56:00 PM PDT 24
Peak memory 212200 kb
Host smart-abfa58eb-2b71-48b9-a8b1-7ab963da38e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3797253641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3797253641
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.248567162
Short name T40
Test name
Test status
Simulation time 24226602695 ps
CPU time 71.1 seconds
Started May 14 12:55:59 PM PDT 24
Finished May 14 12:57:11 PM PDT 24
Peak memory 218312 kb
Host smart-9341fbc0-a3c8-4cc4-945e-855b6b13594f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248567162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.248567162
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1122652433
Short name T47
Test name
Test status
Simulation time 4861779773 ps
CPU time 27.87 seconds
Started May 14 12:55:47 PM PDT 24
Finished May 14 12:56:17 PM PDT 24
Peak memory 213604 kb
Host smart-46f93b44-7f37-43eb-bf0c-bdffc452d1ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122652433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1122652433
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.93726484
Short name T135
Test name
Test status
Simulation time 6898661010 ps
CPU time 19.39 seconds
Started May 14 12:55:59 PM PDT 24
Finished May 14 12:56:20 PM PDT 24
Peak memory 212236 kb
Host smart-06d274e4-dd9e-4fd1-a46b-e848fe1fd0df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93726484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.93726484
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2808498617
Short name T207
Test name
Test status
Simulation time 1319052406 ps
CPU time 28.68 seconds
Started May 14 12:55:43 PM PDT 24
Finished May 14 12:56:13 PM PDT 24
Peak memory 214624 kb
Host smart-3c84b92a-aab0-4a9e-b1a5-c3bd29e21f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808498617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2808498617
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4213091750
Short name T337
Test name
Test status
Simulation time 4430291880 ps
CPU time 34.11 seconds
Started May 14 12:55:50 PM PDT 24
Finished May 14 12:56:27 PM PDT 24
Peak memory 212420 kb
Host smart-d87b10a7-cb83-43fa-a5c1-d207fce634c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4213091750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4213091750
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1431948798
Short name T298
Test name
Test status
Simulation time 20996103185 ps
CPU time 54.37 seconds
Started May 14 12:55:44 PM PDT 24
Finished May 14 12:56:40 PM PDT 24
Peak memory 218248 kb
Host smart-17005a0b-a00f-4f5f-92ac-239a44c8fcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431948798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1431948798
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3081462442
Short name T242
Test name
Test status
Simulation time 12585132753 ps
CPU time 117.85 seconds
Started May 14 12:55:54 PM PDT 24
Finished May 14 12:57:53 PM PDT 24
Peak memory 219312 kb
Host smart-a1778d60-e0d3-4a03-8098-eb9ace2c8b6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081462442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3081462442
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.991215806
Short name T323
Test name
Test status
Simulation time 11033530222 ps
CPU time 23.06 seconds
Started May 14 12:55:51 PM PDT 24
Finished May 14 12:56:16 PM PDT 24
Peak memory 212236 kb
Host smart-ad0c203f-7c2d-440c-9d6c-e8e5db5127e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991215806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.991215806
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2066777700
Short name T312
Test name
Test status
Simulation time 13580087203 ps
CPU time 231.22 seconds
Started May 14 12:55:46 PM PDT 24
Finished May 14 12:59:39 PM PDT 24
Peak memory 216748 kb
Host smart-333c848a-1368-4f36-9d0c-e73d3c1c1951
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066777700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2066777700
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4259312367
Short name T191
Test name
Test status
Simulation time 30782073318 ps
CPU time 62.53 seconds
Started May 14 12:56:06 PM PDT 24
Finished May 14 12:57:12 PM PDT 24
Peak memory 215040 kb
Host smart-60d561ad-1d76-440f-ae07-eea388b76a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259312367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.4259312367
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3974058987
Short name T41
Test name
Test status
Simulation time 1658539857 ps
CPU time 20.22 seconds
Started May 14 12:55:58 PM PDT 24
Finished May 14 12:56:19 PM PDT 24
Peak memory 212128 kb
Host smart-083d7203-4541-4dac-a113-f99dba1a47d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3974058987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3974058987
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2732139465
Short name T179
Test name
Test status
Simulation time 3783550156 ps
CPU time 46.55 seconds
Started May 14 12:55:49 PM PDT 24
Finished May 14 12:56:37 PM PDT 24
Peak memory 218228 kb
Host smart-cb4325fa-5b65-4e35-8830-522379d5736a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732139465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2732139465
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3587402872
Short name T57
Test name
Test status
Simulation time 211599891898 ps
CPU time 1925.17 seconds
Started May 14 12:55:57 PM PDT 24
Finished May 14 01:28:03 PM PDT 24
Peak memory 247600 kb
Host smart-ae128b12-3763-4a16-afd0-b1876185f3e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587402872 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.3587402872
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.883975630
Short name T288
Test name
Test status
Simulation time 6312697155 ps
CPU time 14.79 seconds
Started May 14 12:55:49 PM PDT 24
Finished May 14 12:56:06 PM PDT 24
Peak memory 211448 kb
Host smart-9e1059f1-aaa4-4ebc-94e9-9df91fa89940
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883975630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.883975630
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3935033883
Short name T301
Test name
Test status
Simulation time 99959956357 ps
CPU time 404.77 seconds
Started May 14 12:56:00 PM PDT 24
Finished May 14 01:02:46 PM PDT 24
Peak memory 215688 kb
Host smart-26a15d04-dbba-4c07-b6f2-fefb60e2e357
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935033883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3935033883
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3275522922
Short name T9
Test name
Test status
Simulation time 8609474779 ps
CPU time 63.42 seconds
Started May 14 12:56:01 PM PDT 24
Finished May 14 12:57:06 PM PDT 24
Peak memory 215192 kb
Host smart-48e275a4-c716-400d-a1ee-927007601729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275522922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3275522922
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3235450585
Short name T210
Test name
Test status
Simulation time 373090369 ps
CPU time 10.53 seconds
Started May 14 12:56:01 PM PDT 24
Finished May 14 12:56:13 PM PDT 24
Peak memory 212116 kb
Host smart-82ecb019-08fa-402f-8a85-62e02e5bd301
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3235450585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3235450585
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1082870699
Short name T320
Test name
Test status
Simulation time 6026854517 ps
CPU time 51.94 seconds
Started May 14 12:55:46 PM PDT 24
Finished May 14 12:56:39 PM PDT 24
Peak memory 217056 kb
Host smart-3467e25c-2ce2-4966-9472-2cd0f7e5f599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082870699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1082870699
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3934454169
Short name T352
Test name
Test status
Simulation time 17210753421 ps
CPU time 45.34 seconds
Started May 14 12:55:50 PM PDT 24
Finished May 14 12:56:37 PM PDT 24
Peak memory 217480 kb
Host smart-afabe25b-530d-47fb-8aa1-1dc349e661c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934454169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3934454169
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1552285814
Short name T271
Test name
Test status
Simulation time 3162062971 ps
CPU time 26.26 seconds
Started May 14 12:56:01 PM PDT 24
Finished May 14 12:56:29 PM PDT 24
Peak memory 212032 kb
Host smart-99cccbb9-c602-4215-b040-2218ea35d280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552285814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1552285814
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.949037586
Short name T42
Test name
Test status
Simulation time 158524996495 ps
CPU time 597.88 seconds
Started May 14 12:55:52 PM PDT 24
Finished May 14 01:05:52 PM PDT 24
Peak memory 248588 kb
Host smart-101dcb83-7cfe-4364-8ed5-f7ee7009af4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949037586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.949037586
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3758853833
Short name T144
Test name
Test status
Simulation time 15717451674 ps
CPU time 42.99 seconds
Started May 14 12:55:42 PM PDT 24
Finished May 14 12:56:26 PM PDT 24
Peak memory 215292 kb
Host smart-faccb0c4-5fc1-4462-ad5f-78a8e567f017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758853833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3758853833
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2319421206
Short name T143
Test name
Test status
Simulation time 1125218677 ps
CPU time 17.43 seconds
Started May 14 12:55:49 PM PDT 24
Finished May 14 12:56:08 PM PDT 24
Peak memory 211172 kb
Host smart-cb9052c8-3ec4-4113-a9ae-f42f377129c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2319421206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2319421206
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1326696067
Short name T133
Test name
Test status
Simulation time 35779212318 ps
CPU time 69.2 seconds
Started May 14 12:55:51 PM PDT 24
Finished May 14 12:57:02 PM PDT 24
Peak memory 217348 kb
Host smart-96b7259f-a15a-4a61-b489-ea91510f1188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326696067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1326696067
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3374919880
Short name T257
Test name
Test status
Simulation time 711304229 ps
CPU time 10.31 seconds
Started May 14 12:55:47 PM PDT 24
Finished May 14 12:55:59 PM PDT 24
Peak memory 213796 kb
Host smart-e20b837d-843d-4a5e-a39a-204fbd704bb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374919880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3374919880
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.275168315
Short name T272
Test name
Test status
Simulation time 6300592798 ps
CPU time 27.31 seconds
Started May 14 12:55:55 PM PDT 24
Finished May 14 12:56:23 PM PDT 24
Peak memory 212368 kb
Host smart-6a7609c2-3b23-4446-9d51-0f60fe89b50d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275168315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.275168315
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.300179944
Short name T244
Test name
Test status
Simulation time 86387288413 ps
CPU time 406.66 seconds
Started May 14 12:55:54 PM PDT 24
Finished May 14 01:02:42 PM PDT 24
Peak memory 240904 kb
Host smart-fee9c2ec-f969-4591-b249-4b4d50cccee2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300179944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.300179944
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3031663670
Short name T181
Test name
Test status
Simulation time 4054232003 ps
CPU time 42.63 seconds
Started May 14 12:55:57 PM PDT 24
Finished May 14 12:56:41 PM PDT 24
Peak memory 214848 kb
Host smart-9c97cdf6-045a-4180-b617-33c1b105335a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031663670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3031663670
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3874544250
Short name T174
Test name
Test status
Simulation time 8526626827 ps
CPU time 22.07 seconds
Started May 14 12:55:51 PM PDT 24
Finished May 14 12:56:15 PM PDT 24
Peak memory 211272 kb
Host smart-b3e5601d-1ce4-4e98-9381-e55d1b66c53d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3874544250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3874544250
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2159844724
Short name T81
Test name
Test status
Simulation time 3811349893 ps
CPU time 20.04 seconds
Started May 14 12:55:52 PM PDT 24
Finished May 14 12:56:13 PM PDT 24
Peak memory 216984 kb
Host smart-eaefb98b-0fa2-4da9-9c83-d500b82878f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159844724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2159844724
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2606849162
Short name T264
Test name
Test status
Simulation time 17850861851 ps
CPU time 100.06 seconds
Started May 14 12:55:53 PM PDT 24
Finished May 14 12:57:35 PM PDT 24
Peak memory 219364 kb
Host smart-55055290-1bfd-4654-ae4e-ecd87234a228
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606849162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2606849162
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3951687509
Short name T51
Test name
Test status
Simulation time 97648759688 ps
CPU time 1965.6 seconds
Started May 14 12:56:05 PM PDT 24
Finished May 14 01:28:54 PM PDT 24
Peak memory 244952 kb
Host smart-6496de06-ebb3-4587-8d93-72b673ddf9a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951687509 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3951687509
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2339956842
Short name T274
Test name
Test status
Simulation time 4495899321 ps
CPU time 15.48 seconds
Started May 14 12:55:47 PM PDT 24
Finished May 14 12:56:05 PM PDT 24
Peak memory 211504 kb
Host smart-c8f1173d-f9d9-4b7d-ac00-f35ac5a5e34f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339956842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2339956842
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1572618110
Short name T283
Test name
Test status
Simulation time 18570655247 ps
CPU time 245.08 seconds
Started May 14 12:56:00 PM PDT 24
Finished May 14 01:00:07 PM PDT 24
Peak memory 237880 kb
Host smart-6c53fe1a-af20-486f-aedd-29c226a1f950
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572618110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1572618110
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1456933202
Short name T19
Test name
Test status
Simulation time 688838376 ps
CPU time 18.8 seconds
Started May 14 12:56:07 PM PDT 24
Finished May 14 12:56:29 PM PDT 24
Peak memory 214724 kb
Host smart-9e6e2140-50d5-43bc-a3b4-a05e7910b449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456933202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1456933202
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.503386363
Short name T48
Test name
Test status
Simulation time 3527632381 ps
CPU time 31.52 seconds
Started May 14 12:56:04 PM PDT 24
Finished May 14 12:56:38 PM PDT 24
Peak memory 212300 kb
Host smart-2c45b9fe-62f9-45ed-bf70-e11beab0d6c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=503386363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.503386363
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.612457732
Short name T79
Test name
Test status
Simulation time 881210928 ps
CPU time 20.22 seconds
Started May 14 12:56:04 PM PDT 24
Finished May 14 12:56:27 PM PDT 24
Peak memory 216356 kb
Host smart-a72aee86-e097-4981-8780-81cb923c0086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612457732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.612457732
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.147358952
Short name T124
Test name
Test status
Simulation time 23316482859 ps
CPU time 62.05 seconds
Started May 14 12:56:02 PM PDT 24
Finished May 14 12:57:07 PM PDT 24
Peak memory 219340 kb
Host smart-f663178e-8238-43d1-9136-b04400311fa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147358952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.147358952
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.4276054413
Short name T183
Test name
Test status
Simulation time 1199379019 ps
CPU time 12.33 seconds
Started May 14 12:56:05 PM PDT 24
Finished May 14 12:56:20 PM PDT 24
Peak memory 211360 kb
Host smart-9c242723-ae0a-46e6-8168-79bbdb3bcc4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276054413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.4276054413
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.178406595
Short name T292
Test name
Test status
Simulation time 61729777989 ps
CPU time 377.02 seconds
Started May 14 12:56:05 PM PDT 24
Finished May 14 01:02:26 PM PDT 24
Peak memory 240504 kb
Host smart-7b1f0c31-851a-4876-9ff5-2e320deef078
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178406595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.178406595
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2490167475
Short name T351
Test name
Test status
Simulation time 18441025279 ps
CPU time 45.98 seconds
Started May 14 12:56:00 PM PDT 24
Finished May 14 12:56:47 PM PDT 24
Peak memory 214064 kb
Host smart-f85be1b0-d60e-4195-b864-42ceb86ede1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490167475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2490167475
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2335777713
Short name T204
Test name
Test status
Simulation time 9599267411 ps
CPU time 23.6 seconds
Started May 14 12:56:03 PM PDT 24
Finished May 14 12:56:29 PM PDT 24
Peak memory 211444 kb
Host smart-ea157ea1-b922-4430-950f-58da144f433c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2335777713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2335777713
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.173927886
Short name T248
Test name
Test status
Simulation time 21630383288 ps
CPU time 48.54 seconds
Started May 14 12:56:06 PM PDT 24
Finished May 14 12:56:59 PM PDT 24
Peak memory 217340 kb
Host smart-d710bd43-d3a0-4ced-98ce-e04958345a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173927886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.173927886
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2124505900
Short name T293
Test name
Test status
Simulation time 18784082875 ps
CPU time 160.67 seconds
Started May 14 12:56:07 PM PDT 24
Finished May 14 12:58:52 PM PDT 24
Peak memory 220904 kb
Host smart-3da15d6e-561d-4e15-aee0-25dbea9e33c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124505900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2124505900
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.4293209488
Short name T56
Test name
Test status
Simulation time 8457077741 ps
CPU time 330.71 seconds
Started May 14 12:56:03 PM PDT 24
Finished May 14 01:01:37 PM PDT 24
Peak memory 224372 kb
Host smart-7d78943a-a5d0-4e1b-969c-29b2fc6efbfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293209488 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.4293209488
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1548263921
Short name T364
Test name
Test status
Simulation time 1377233758 ps
CPU time 13.14 seconds
Started May 14 12:55:51 PM PDT 24
Finished May 14 12:56:06 PM PDT 24
Peak memory 211348 kb
Host smart-04167dbe-aa5f-41cf-b630-5898b3d4e3a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548263921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1548263921
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1462779379
Short name T49
Test name
Test status
Simulation time 17552741574 ps
CPU time 65.76 seconds
Started May 14 12:56:02 PM PDT 24
Finished May 14 12:57:11 PM PDT 24
Peak memory 215208 kb
Host smart-7a35d743-b0a4-40eb-890d-a662c91c2f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462779379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1462779379
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3267661290
Short name T344
Test name
Test status
Simulation time 185927442 ps
CPU time 10.58 seconds
Started May 14 12:55:51 PM PDT 24
Finished May 14 12:56:04 PM PDT 24
Peak memory 212224 kb
Host smart-bdd83344-72fa-4f02-a701-2d61d0c111a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3267661290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3267661290
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2853862457
Short name T225
Test name
Test status
Simulation time 20540686982 ps
CPU time 49.26 seconds
Started May 14 12:56:03 PM PDT 24
Finished May 14 12:56:55 PM PDT 24
Peak memory 217476 kb
Host smart-f021131e-afa3-4515-8a1f-da7f9ed632ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853862457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2853862457
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2403969544
Short name T302
Test name
Test status
Simulation time 18831228467 ps
CPU time 161.72 seconds
Started May 14 12:56:07 PM PDT 24
Finished May 14 12:58:53 PM PDT 24
Peak memory 220472 kb
Host smart-e7b15d19-bfb2-4ea8-b4c5-6232e83f2a0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403969544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2403969544
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2052589731
Short name T357
Test name
Test status
Simulation time 16045628869 ps
CPU time 31.89 seconds
Started May 14 12:56:06 PM PDT 24
Finished May 14 12:56:42 PM PDT 24
Peak memory 212220 kb
Host smart-e5fa9ee9-450f-44cd-851a-9f32021e0e70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052589731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2052589731
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.184908176
Short name T127
Test name
Test status
Simulation time 214351881749 ps
CPU time 701.48 seconds
Started May 14 12:55:49 PM PDT 24
Finished May 14 01:07:32 PM PDT 24
Peak memory 233896 kb
Host smart-2078a157-b352-416a-a37e-6b385210fada
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184908176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.184908176
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3602054561
Short name T217
Test name
Test status
Simulation time 21169077750 ps
CPU time 56.39 seconds
Started May 14 12:56:06 PM PDT 24
Finished May 14 12:57:06 PM PDT 24
Peak memory 215104 kb
Host smart-c2ef758b-bf14-4850-b178-d1d82c978cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602054561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3602054561
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4104622776
Short name T102
Test name
Test status
Simulation time 700218785 ps
CPU time 10.48 seconds
Started May 14 12:55:54 PM PDT 24
Finished May 14 12:56:06 PM PDT 24
Peak memory 212208 kb
Host smart-307c9fdf-133a-4616-aacc-baeb30f84960
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4104622776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4104622776
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3557099507
Short name T332
Test name
Test status
Simulation time 6567768502 ps
CPU time 61.57 seconds
Started May 14 12:55:54 PM PDT 24
Finished May 14 12:56:57 PM PDT 24
Peak memory 216676 kb
Host smart-f1fccb28-b217-43fb-9946-00265a0db4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557099507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3557099507
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.999750344
Short name T1
Test name
Test status
Simulation time 9897036281 ps
CPU time 92.81 seconds
Started May 14 12:56:05 PM PDT 24
Finished May 14 12:57:41 PM PDT 24
Peak memory 220084 kb
Host smart-a88dfe0d-6237-4770-88f3-21425f4f4562
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999750344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.999750344
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2301858640
Short name T157
Test name
Test status
Simulation time 15361708472 ps
CPU time 29.97 seconds
Started May 14 12:55:29 PM PDT 24
Finished May 14 12:56:00 PM PDT 24
Peak memory 212348 kb
Host smart-0dc21ddd-2fe6-4b60-bc44-635cac78f179
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301858640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2301858640
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3843602049
Short name T267
Test name
Test status
Simulation time 144450535057 ps
CPU time 412.39 seconds
Started May 14 12:55:35 PM PDT 24
Finished May 14 01:02:29 PM PDT 24
Peak memory 240208 kb
Host smart-d539c890-b98c-4d20-960d-6b5dc69002ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843602049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3843602049
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2316768177
Short name T340
Test name
Test status
Simulation time 1375602965 ps
CPU time 19.37 seconds
Started May 14 12:55:28 PM PDT 24
Finished May 14 12:55:48 PM PDT 24
Peak memory 214796 kb
Host smart-8a2758b5-0102-42e9-a60c-c438cfc6d6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316768177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2316768177
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.621626385
Short name T197
Test name
Test status
Simulation time 188075129 ps
CPU time 10.6 seconds
Started May 14 12:55:18 PM PDT 24
Finished May 14 12:55:32 PM PDT 24
Peak memory 212232 kb
Host smart-65695316-6061-4a8c-825e-e1c090d7df3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=621626385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.621626385
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2201086349
Short name T250
Test name
Test status
Simulation time 6578626003 ps
CPU time 57.14 seconds
Started May 14 12:55:17 PM PDT 24
Finished May 14 12:56:18 PM PDT 24
Peak memory 217284 kb
Host smart-e9866eec-af92-40fd-8c22-c0bfe3b69903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201086349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2201086349
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2250639480
Short name T307
Test name
Test status
Simulation time 2497739827 ps
CPU time 21.04 seconds
Started May 14 12:55:40 PM PDT 24
Finished May 14 12:56:04 PM PDT 24
Peak memory 218608 kb
Host smart-3f71a1ee-7db1-4f82-b5f1-9285f0735231
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250639480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2250639480
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3719076841
Short name T150
Test name
Test status
Simulation time 26573697316 ps
CPU time 32.69 seconds
Started May 14 12:56:05 PM PDT 24
Finished May 14 12:56:41 PM PDT 24
Peak memory 212376 kb
Host smart-2291cd2d-018e-49ef-bfd8-f6eb61928722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719076841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3719076841
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2062976753
Short name T178
Test name
Test status
Simulation time 36485813871 ps
CPU time 348.12 seconds
Started May 14 12:56:02 PM PDT 24
Finished May 14 01:01:53 PM PDT 24
Peak memory 240040 kb
Host smart-3b8adaf9-5f6f-43c9-931b-24938fd9c6ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062976753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2062976753
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.514448725
Short name T240
Test name
Test status
Simulation time 8853588457 ps
CPU time 69.8 seconds
Started May 14 12:56:07 PM PDT 24
Finished May 14 12:57:20 PM PDT 24
Peak memory 214976 kb
Host smart-dfb57bb2-8b82-4870-9b76-9fef7df3103f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514448725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.514448725
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2230179857
Short name T309
Test name
Test status
Simulation time 267552511 ps
CPU time 12.09 seconds
Started May 14 12:55:58 PM PDT 24
Finished May 14 12:56:11 PM PDT 24
Peak memory 212484 kb
Host smart-acee093c-1cd1-46bf-9d49-67c767152d0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2230179857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2230179857
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1698779981
Short name T153
Test name
Test status
Simulation time 29570769514 ps
CPU time 65.47 seconds
Started May 14 12:55:58 PM PDT 24
Finished May 14 12:57:05 PM PDT 24
Peak memory 218068 kb
Host smart-9d073621-4e08-4429-9628-2852a8846a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698779981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1698779981
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3802995882
Short name T46
Test name
Test status
Simulation time 19837457332 ps
CPU time 57.37 seconds
Started May 14 12:56:07 PM PDT 24
Finished May 14 12:57:08 PM PDT 24
Peak memory 219204 kb
Host smart-df48960d-6cb2-4074-9e2a-693874c27d0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802995882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3802995882
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1694405451
Short name T247
Test name
Test status
Simulation time 3389493405 ps
CPU time 27.09 seconds
Started May 14 12:56:05 PM PDT 24
Finished May 14 12:56:36 PM PDT 24
Peak memory 211968 kb
Host smart-ab770934-623c-4224-a805-20d9b9c9071d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694405451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1694405451
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.138251942
Short name T26
Test name
Test status
Simulation time 5151676351 ps
CPU time 263.31 seconds
Started May 14 12:56:05 PM PDT 24
Finished May 14 01:00:32 PM PDT 24
Peak memory 240672 kb
Host smart-b61e4232-94b4-447b-bc23-8df747f08e16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138251942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.138251942
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1094925697
Short name T278
Test name
Test status
Simulation time 4115220748 ps
CPU time 45.07 seconds
Started May 14 12:56:04 PM PDT 24
Finished May 14 12:56:51 PM PDT 24
Peak memory 214824 kb
Host smart-4d742e80-9311-420b-ac27-e744a90516a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094925697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1094925697
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1954200913
Short name T216
Test name
Test status
Simulation time 2441202806 ps
CPU time 10.11 seconds
Started May 14 12:56:08 PM PDT 24
Finished May 14 12:56:22 PM PDT 24
Peak memory 212416 kb
Host smart-5c88a053-4fd5-4240-85e5-6cda38998749
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1954200913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1954200913
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.106437365
Short name T129
Test name
Test status
Simulation time 18146555429 ps
CPU time 60.22 seconds
Started May 14 12:56:05 PM PDT 24
Finished May 14 12:57:08 PM PDT 24
Peak memory 215120 kb
Host smart-c55dcd61-9256-4da7-86e9-871b96579bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106437365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.106437365
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2741817210
Short name T346
Test name
Test status
Simulation time 7530886411 ps
CPU time 69 seconds
Started May 14 12:56:07 PM PDT 24
Finished May 14 12:57:19 PM PDT 24
Peak memory 219716 kb
Host smart-a2a086ff-907e-45b2-86ff-85b05bb4857f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741817210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2741817210
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3790056285
Short name T162
Test name
Test status
Simulation time 14769243539 ps
CPU time 29.93 seconds
Started May 14 12:56:04 PM PDT 24
Finished May 14 12:56:37 PM PDT 24
Peak memory 212264 kb
Host smart-c841ce9b-2861-4999-b530-4d0b9407d93c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790056285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3790056285
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2464944061
Short name T177
Test name
Test status
Simulation time 13736041018 ps
CPU time 288.42 seconds
Started May 14 12:56:06 PM PDT 24
Finished May 14 01:00:58 PM PDT 24
Peak memory 216760 kb
Host smart-4e387fcf-5a47-4f47-a61a-3ec3054f8acb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464944061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2464944061
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1048248921
Short name T21
Test name
Test status
Simulation time 332280334 ps
CPU time 18.7 seconds
Started May 14 12:56:00 PM PDT 24
Finished May 14 12:56:20 PM PDT 24
Peak memory 214828 kb
Host smart-9c642f71-b3ab-40c0-a4ff-f7e04ed47d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048248921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1048248921
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3596802471
Short name T101
Test name
Test status
Simulation time 1731003160 ps
CPU time 20.18 seconds
Started May 14 12:56:02 PM PDT 24
Finished May 14 12:56:25 PM PDT 24
Peak memory 211220 kb
Host smart-67f3f4e9-6e94-4d63-be83-c3ce34d79c1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3596802471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3596802471
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3792162377
Short name T276
Test name
Test status
Simulation time 18503331822 ps
CPU time 48.52 seconds
Started May 14 12:55:59 PM PDT 24
Finished May 14 12:56:48 PM PDT 24
Peak memory 218124 kb
Host smart-6e03768b-faf4-46c9-91ff-3596a5e2caa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792162377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3792162377
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.912221645
Short name T349
Test name
Test status
Simulation time 1777739754 ps
CPU time 53.45 seconds
Started May 14 12:56:03 PM PDT 24
Finished May 14 12:56:59 PM PDT 24
Peak memory 219296 kb
Host smart-96210d13-a839-4680-9f08-f9192d773239
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912221645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.912221645
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1631096909
Short name T345
Test name
Test status
Simulation time 21664240583 ps
CPU time 802.31 seconds
Started May 14 12:56:06 PM PDT 24
Finished May 14 01:09:32 PM PDT 24
Peak memory 235952 kb
Host smart-d6fc9cfe-3fe8-4e1c-874c-204a0dcbb69c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631096909 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.1631096909
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.446297255
Short name T167
Test name
Test status
Simulation time 1716702199 ps
CPU time 11.35 seconds
Started May 14 12:56:02 PM PDT 24
Finished May 14 12:56:15 PM PDT 24
Peak memory 211360 kb
Host smart-6437eebd-d83d-4567-89ba-6791d7834bf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446297255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.446297255
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1165677044
Short name T270
Test name
Test status
Simulation time 40124269702 ps
CPU time 240.54 seconds
Started May 14 12:56:06 PM PDT 24
Finished May 14 01:00:10 PM PDT 24
Peak memory 240168 kb
Host smart-2a33209c-8213-4496-9df6-c43b65ed67cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165677044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1165677044
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2624270941
Short name T164
Test name
Test status
Simulation time 16206562408 ps
CPU time 67.49 seconds
Started May 14 12:56:06 PM PDT 24
Finished May 14 12:57:17 PM PDT 24
Peak memory 215000 kb
Host smart-0e43116a-4a94-4518-856a-e9402dac95c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624270941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2624270941
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.301306181
Short name T291
Test name
Test status
Simulation time 17877608210 ps
CPU time 22.3 seconds
Started May 14 12:56:12 PM PDT 24
Finished May 14 12:56:37 PM PDT 24
Peak memory 212524 kb
Host smart-cb985573-9a9f-4cba-8a13-67c03473144c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=301306181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.301306181
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2965350165
Short name T297
Test name
Test status
Simulation time 22114802615 ps
CPU time 66.81 seconds
Started May 14 12:56:03 PM PDT 24
Finished May 14 12:57:12 PM PDT 24
Peak memory 217344 kb
Host smart-05a0ce2b-ca61-4fd9-8806-35385281332c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965350165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2965350165
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2786698759
Short name T262
Test name
Test status
Simulation time 5879453337 ps
CPU time 62.46 seconds
Started May 14 12:56:09 PM PDT 24
Finished May 14 12:57:15 PM PDT 24
Peak memory 216592 kb
Host smart-9e96d217-c6dc-42e4-a3fb-360b6d988543
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786698759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2786698759
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3307765100
Short name T52
Test name
Test status
Simulation time 315640133656 ps
CPU time 2185.99 seconds
Started May 14 12:56:03 PM PDT 24
Finished May 14 01:32:33 PM PDT 24
Peak memory 244072 kb
Host smart-ac7f46bc-885b-47b6-8d90-8d5e3b62e37f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307765100 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3307765100
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3233333662
Short name T161
Test name
Test status
Simulation time 3057298311 ps
CPU time 25.62 seconds
Started May 14 12:56:01 PM PDT 24
Finished May 14 12:56:28 PM PDT 24
Peak memory 211932 kb
Host smart-2c23984d-405b-4000-9cab-58afe02bde3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233333662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3233333662
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.282959060
Short name T152
Test name
Test status
Simulation time 89948580416 ps
CPU time 859.36 seconds
Started May 14 12:56:08 PM PDT 24
Finished May 14 01:10:31 PM PDT 24
Peak memory 239900 kb
Host smart-82672294-4906-4545-a88d-b3c522d0fdf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282959060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.282959060
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1114234214
Short name T360
Test name
Test status
Simulation time 32107495682 ps
CPU time 68.29 seconds
Started May 14 12:56:05 PM PDT 24
Finished May 14 12:57:16 PM PDT 24
Peak memory 215028 kb
Host smart-d4cfb9ee-11e3-4cd9-8170-314a69a08cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114234214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1114234214
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.281394391
Short name T306
Test name
Test status
Simulation time 1557442192 ps
CPU time 15.4 seconds
Started May 14 12:56:00 PM PDT 24
Finished May 14 12:56:16 PM PDT 24
Peak memory 212444 kb
Host smart-ff57a6c0-5b5a-456f-a27c-99e8b8cd72e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=281394391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.281394391
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2131224218
Short name T78
Test name
Test status
Simulation time 16009588390 ps
CPU time 73.63 seconds
Started May 14 12:56:04 PM PDT 24
Finished May 14 12:57:20 PM PDT 24
Peak memory 217472 kb
Host smart-f1fae81c-396d-4824-b1fe-5ea0ab190b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131224218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2131224218
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.754816
Short name T296
Test name
Test status
Simulation time 733943591 ps
CPU time 23.42 seconds
Started May 14 12:56:06 PM PDT 24
Finished May 14 12:56:33 PM PDT 24
Peak memory 217392 kb
Host smart-a6750ad1-2fb1-4b96-8333-6564e7e791e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM
_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 44.rom_ctrl_stress_all.754816
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.422699992
Short name T363
Test name
Test status
Simulation time 2250027013 ps
CPU time 15.47 seconds
Started May 14 12:56:12 PM PDT 24
Finished May 14 12:56:30 PM PDT 24
Peak memory 211492 kb
Host smart-699371f3-c580-4c05-b130-5c08a7510652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422699992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.422699992
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4035559529
Short name T155
Test name
Test status
Simulation time 235745217929 ps
CPU time 564.62 seconds
Started May 14 12:56:09 PM PDT 24
Finished May 14 01:05:38 PM PDT 24
Peak memory 240008 kb
Host smart-b0c617f1-a8e2-4616-890b-33380cd418b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035559529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.4035559529
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1214965208
Short name T273
Test name
Test status
Simulation time 8462413109 ps
CPU time 62.34 seconds
Started May 14 12:56:02 PM PDT 24
Finished May 14 12:57:07 PM PDT 24
Peak memory 215392 kb
Host smart-0e75386e-41a9-4bb2-9648-4cd79b2bf9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214965208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1214965208
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1591761263
Short name T15
Test name
Test status
Simulation time 721674197 ps
CPU time 10.73 seconds
Started May 14 12:56:08 PM PDT 24
Finished May 14 12:56:23 PM PDT 24
Peak memory 211432 kb
Host smart-fd32660c-772e-42da-85e4-655258797f93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1591761263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1591761263
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.367955979
Short name T310
Test name
Test status
Simulation time 13501644288 ps
CPU time 31.3 seconds
Started May 14 12:56:08 PM PDT 24
Finished May 14 12:56:43 PM PDT 24
Peak memory 217136 kb
Host smart-711f684c-7ad0-47b2-8924-366c82fde3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367955979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.367955979
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2590335538
Short name T279
Test name
Test status
Simulation time 20508438395 ps
CPU time 195.51 seconds
Started May 14 12:56:06 PM PDT 24
Finished May 14 12:59:25 PM PDT 24
Peak memory 221668 kb
Host smart-3ce99ac1-cd4d-41e4-9c9a-cc2bbdd3bf92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590335538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2590335538
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1269838689
Short name T128
Test name
Test status
Simulation time 13341734761 ps
CPU time 15.78 seconds
Started May 14 12:56:04 PM PDT 24
Finished May 14 12:56:23 PM PDT 24
Peak memory 211468 kb
Host smart-20985602-ee2f-45e9-af4d-0b1a9e72df52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269838689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1269838689
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3264300429
Short name T356
Test name
Test status
Simulation time 8415893980 ps
CPU time 154.97 seconds
Started May 14 12:55:57 PM PDT 24
Finished May 14 12:58:33 PM PDT 24
Peak memory 229012 kb
Host smart-49410e36-097e-4a0b-ad45-c1b4f9c12562
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264300429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3264300429
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3901307979
Short name T289
Test name
Test status
Simulation time 7711427411 ps
CPU time 33.53 seconds
Started May 14 12:56:10 PM PDT 24
Finished May 14 12:56:47 PM PDT 24
Peak memory 211784 kb
Host smart-b4d890b0-ce7f-4200-a387-6404e09ae4b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3901307979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3901307979
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1031416356
Short name T209
Test name
Test status
Simulation time 1061388403 ps
CPU time 23.02 seconds
Started May 14 12:56:01 PM PDT 24
Finished May 14 12:56:26 PM PDT 24
Peak memory 215712 kb
Host smart-f4030e1a-937d-4752-9aee-ca7b655f7a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031416356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1031416356
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1334371330
Short name T331
Test name
Test status
Simulation time 1143095916 ps
CPU time 34.11 seconds
Started May 14 12:56:08 PM PDT 24
Finished May 14 12:56:46 PM PDT 24
Peak memory 219168 kb
Host smart-8c64589a-c88b-4a7e-8117-0662c463cd53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334371330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1334371330
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2514856093
Short name T65
Test name
Test status
Simulation time 6396577456 ps
CPU time 26.95 seconds
Started May 14 12:56:02 PM PDT 24
Finished May 14 12:56:31 PM PDT 24
Peak memory 212296 kb
Host smart-c997340a-a72c-4cfb-83da-66e4a3fcdf5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514856093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2514856093
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.633725484
Short name T43
Test name
Test status
Simulation time 56522564921 ps
CPU time 548.21 seconds
Started May 14 12:56:07 PM PDT 24
Finished May 14 01:05:20 PM PDT 24
Peak memory 230864 kb
Host smart-262dc2b5-1629-4f5f-a448-12ec4d15924a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633725484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.633725484
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2773139365
Short name T338
Test name
Test status
Simulation time 2490394806 ps
CPU time 35.53 seconds
Started May 14 12:56:08 PM PDT 24
Finished May 14 12:56:47 PM PDT 24
Peak memory 214776 kb
Host smart-ffdf94ff-00cd-4be6-9f99-622548c236a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773139365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2773139365
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1926682925
Short name T236
Test name
Test status
Simulation time 1155309164 ps
CPU time 14.87 seconds
Started May 14 12:56:07 PM PDT 24
Finished May 14 12:56:26 PM PDT 24
Peak memory 211116 kb
Host smart-c33747b6-d23f-4f81-920b-1fedefcd10ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1926682925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1926682925
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1663873405
Short name T122
Test name
Test status
Simulation time 360638740 ps
CPU time 19.91 seconds
Started May 14 12:56:06 PM PDT 24
Finished May 14 12:56:29 PM PDT 24
Peak memory 217124 kb
Host smart-6881f920-7336-4d13-a588-03b962613a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663873405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1663873405
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3032913066
Short name T361
Test name
Test status
Simulation time 13211805731 ps
CPU time 69 seconds
Started May 14 12:56:07 PM PDT 24
Finished May 14 12:57:20 PM PDT 24
Peak memory 222196 kb
Host smart-5d3a5b3d-30c5-42a6-a9ba-797f46d6abc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032913066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3032913066
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3364441167
Short name T252
Test name
Test status
Simulation time 1024631874 ps
CPU time 14.64 seconds
Started May 14 12:56:05 PM PDT 24
Finished May 14 12:56:23 PM PDT 24
Peak memory 211356 kb
Host smart-7c6b4ce1-c08d-42b1-ac57-9e648a68fcde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364441167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3364441167
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2318980330
Short name T350
Test name
Test status
Simulation time 89200533702 ps
CPU time 267.37 seconds
Started May 14 12:56:06 PM PDT 24
Finished May 14 01:00:37 PM PDT 24
Peak memory 240732 kb
Host smart-bd64a1a6-ba57-450d-b255-d8b138d47321
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318980330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2318980330
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1457722590
Short name T218
Test name
Test status
Simulation time 19725534540 ps
CPU time 31.01 seconds
Started May 14 12:56:07 PM PDT 24
Finished May 14 12:56:42 PM PDT 24
Peak memory 215472 kb
Host smart-1d7742b5-d856-4c9d-828a-e3248cae7a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457722590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1457722590
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2010980653
Short name T160
Test name
Test status
Simulation time 1342135079 ps
CPU time 12.77 seconds
Started May 14 12:56:05 PM PDT 24
Finished May 14 12:56:21 PM PDT 24
Peak memory 211212 kb
Host smart-07fcb854-0a07-422b-b013-96cfeb104a60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2010980653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2010980653
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.367788457
Short name T23
Test name
Test status
Simulation time 9905967897 ps
CPU time 47.43 seconds
Started May 14 12:56:12 PM PDT 24
Finished May 14 12:57:02 PM PDT 24
Peak memory 218056 kb
Host smart-cba5d47d-3f5e-4665-811d-1c086cf252e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367788457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.367788457
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.4021244822
Short name T233
Test name
Test status
Simulation time 8968197635 ps
CPU time 90.96 seconds
Started May 14 12:56:09 PM PDT 24
Finished May 14 12:57:44 PM PDT 24
Peak memory 219224 kb
Host smart-7a5ba775-531c-46d7-81d4-32923b88304e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021244822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.4021244822
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.647736644
Short name T53
Test name
Test status
Simulation time 393647502898 ps
CPU time 3896.74 seconds
Started May 14 12:56:02 PM PDT 24
Finished May 14 02:01:02 PM PDT 24
Peak memory 247848 kb
Host smart-9675aedd-9334-425a-a8d8-6455163101c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647736644 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.647736644
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3304245354
Short name T188
Test name
Test status
Simulation time 2336357648 ps
CPU time 22.53 seconds
Started May 14 12:56:05 PM PDT 24
Finished May 14 12:56:30 PM PDT 24
Peak memory 211984 kb
Host smart-52b110bc-0388-4b00-8114-bf964bc94c1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304245354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3304245354
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3197926837
Short name T30
Test name
Test status
Simulation time 9656706266 ps
CPU time 319.41 seconds
Started May 14 12:56:12 PM PDT 24
Finished May 14 01:01:34 PM PDT 24
Peak memory 229664 kb
Host smart-02ab7d9e-cd31-42f9-b032-f62fc741ab7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197926837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3197926837
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.448503457
Short name T2
Test name
Test status
Simulation time 3047566768 ps
CPU time 25.42 seconds
Started May 14 12:56:09 PM PDT 24
Finished May 14 12:56:38 PM PDT 24
Peak memory 213696 kb
Host smart-a492a616-022c-4aec-9f40-100fb227df19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448503457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.448503457
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3670204570
Short name T149
Test name
Test status
Simulation time 11848234530 ps
CPU time 27.74 seconds
Started May 14 12:56:07 PM PDT 24
Finished May 14 12:56:39 PM PDT 24
Peak memory 212424 kb
Host smart-b27efd68-b06b-475c-9ab6-046045d5434a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3670204570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3670204570
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2073062269
Short name T316
Test name
Test status
Simulation time 4764072306 ps
CPU time 33.19 seconds
Started May 14 12:56:08 PM PDT 24
Finished May 14 12:56:45 PM PDT 24
Peak memory 216820 kb
Host smart-47ce1fd0-eb28-4180-b584-30475a17d80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073062269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2073062269
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2591401289
Short name T126
Test name
Test status
Simulation time 25186432060 ps
CPU time 135.41 seconds
Started May 14 12:56:02 PM PDT 24
Finished May 14 12:58:20 PM PDT 24
Peak memory 220804 kb
Host smart-32e2373b-dd9c-41d6-9f8c-93504a6148e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591401289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2591401289
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3321719215
Short name T212
Test name
Test status
Simulation time 12324011736 ps
CPU time 26.69 seconds
Started May 14 12:55:34 PM PDT 24
Finished May 14 12:56:02 PM PDT 24
Peak memory 211472 kb
Host smart-7758fe47-db0c-44cf-a108-e8e0651bb46a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321719215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3321719215
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3975588011
Short name T321
Test name
Test status
Simulation time 16101931055 ps
CPU time 263.68 seconds
Started May 14 12:55:40 PM PDT 24
Finished May 14 01:00:06 PM PDT 24
Peak memory 216376 kb
Host smart-e83dac0e-d6f0-4478-969f-1f30f39caaa8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975588011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3975588011
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1115592370
Short name T261
Test name
Test status
Simulation time 10796129281 ps
CPU time 51.74 seconds
Started May 14 12:55:40 PM PDT 24
Finished May 14 12:56:34 PM PDT 24
Peak memory 214104 kb
Host smart-45cf70c1-5b52-4d62-949e-4d8db208d087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115592370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1115592370
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3481900571
Short name T295
Test name
Test status
Simulation time 3113646589 ps
CPU time 28.69 seconds
Started May 14 12:55:17 PM PDT 24
Finished May 14 12:55:49 PM PDT 24
Peak memory 211204 kb
Host smart-340e2e7d-a9cc-4e68-84c0-170c552c8c22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3481900571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3481900571
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3639748036
Short name T192
Test name
Test status
Simulation time 4005239692 ps
CPU time 18.51 seconds
Started May 14 12:55:17 PM PDT 24
Finished May 14 12:55:39 PM PDT 24
Peak memory 213940 kb
Host smart-0861059e-2fde-4ba2-abe9-6097ec11b848
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639748036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3639748036
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.297114652
Short name T172
Test name
Test status
Simulation time 16304960898 ps
CPU time 29.14 seconds
Started May 14 12:55:47 PM PDT 24
Finished May 14 12:56:18 PM PDT 24
Peak memory 212132 kb
Host smart-2cbd7fd0-6390-4ede-b8e9-b56c55bf3ea7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297114652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.297114652
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2637372274
Short name T336
Test name
Test status
Simulation time 7041347895 ps
CPU time 148.52 seconds
Started May 14 12:55:17 PM PDT 24
Finished May 14 12:57:49 PM PDT 24
Peak memory 239188 kb
Host smart-44fd9e6c-b31f-443c-aa88-64c2aaa7956a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637372274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2637372274
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1285412819
Short name T326
Test name
Test status
Simulation time 4847855390 ps
CPU time 45.95 seconds
Started May 14 12:55:38 PM PDT 24
Finished May 14 12:56:26 PM PDT 24
Peak memory 215280 kb
Host smart-862371ea-4681-4ea1-9217-9ad29c597a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285412819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1285412819
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.723720854
Short name T203
Test name
Test status
Simulation time 4464378338 ps
CPU time 22.93 seconds
Started May 14 12:55:17 PM PDT 24
Finished May 14 12:55:43 PM PDT 24
Peak memory 211352 kb
Host smart-5480997a-cd85-4030-9b2b-3e3d1ee4aa93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=723720854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.723720854
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3563491666
Short name T249
Test name
Test status
Simulation time 3194757072 ps
CPU time 40.63 seconds
Started May 14 12:55:20 PM PDT 24
Finished May 14 12:56:03 PM PDT 24
Peak memory 218232 kb
Host smart-397bd0f0-bd86-42bd-b483-dbf34ba9bfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563491666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3563491666
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2177816517
Short name T282
Test name
Test status
Simulation time 14739528166 ps
CPU time 33.58 seconds
Started May 14 12:55:33 PM PDT 24
Finished May 14 12:56:07 PM PDT 24
Peak memory 214148 kb
Host smart-31c9be9f-e913-4ec0-934e-da4322dcb9fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177816517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2177816517
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.459382068
Short name T17
Test name
Test status
Simulation time 33626809061 ps
CPU time 1246.32 seconds
Started May 14 12:55:38 PM PDT 24
Finished May 14 01:16:27 PM PDT 24
Peak memory 235908 kb
Host smart-46241755-2dcd-4afb-9aea-23da3bbcda24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459382068 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.459382068
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2517780001
Short name T145
Test name
Test status
Simulation time 586150008 ps
CPU time 12.46 seconds
Started May 14 12:55:36 PM PDT 24
Finished May 14 12:55:50 PM PDT 24
Peak memory 211340 kb
Host smart-08783c1e-4f18-4741-a99e-ed197a4e96cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517780001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2517780001
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.253667287
Short name T159
Test name
Test status
Simulation time 4665255126 ps
CPU time 236.63 seconds
Started May 14 12:55:19 PM PDT 24
Finished May 14 12:59:19 PM PDT 24
Peak memory 239984 kb
Host smart-5f629e14-856d-47a6-8222-b6b6809c3eaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253667287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.253667287
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1825046669
Short name T138
Test name
Test status
Simulation time 17756142976 ps
CPU time 44.86 seconds
Started May 14 12:55:17 PM PDT 24
Finished May 14 12:56:05 PM PDT 24
Peak memory 215228 kb
Host smart-85721168-84cf-4cf1-bb8e-5e59c5712701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825046669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1825046669
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3533322701
Short name T246
Test name
Test status
Simulation time 2087706215 ps
CPU time 22.85 seconds
Started May 14 12:55:24 PM PDT 24
Finished May 14 12:55:47 PM PDT 24
Peak memory 211236 kb
Host smart-8266e6a5-6a45-47af-b7fe-e713e371f799
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3533322701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3533322701
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.4080628586
Short name T231
Test name
Test status
Simulation time 37276075830 ps
CPU time 76.97 seconds
Started May 14 12:55:43 PM PDT 24
Finished May 14 12:57:06 PM PDT 24
Peak memory 218400 kb
Host smart-1747c38a-6e12-4d69-9e0d-235a7b4c9fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080628586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.4080628586
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2300156907
Short name T268
Test name
Test status
Simulation time 232262443 ps
CPU time 12.02 seconds
Started May 14 12:55:19 PM PDT 24
Finished May 14 12:55:34 PM PDT 24
Peak memory 213620 kb
Host smart-afbd1db9-e070-4890-b8c7-9c28873ea65c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300156907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2300156907
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.908014024
Short name T66
Test name
Test status
Simulation time 2547602667 ps
CPU time 16.07 seconds
Started May 14 12:55:45 PM PDT 24
Finished May 14 12:56:03 PM PDT 24
Peak memory 211488 kb
Host smart-c90e6965-9ecf-452b-a0eb-d1033358dd23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908014024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.908014024
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1346016083
Short name T245
Test name
Test status
Simulation time 47897198336 ps
CPU time 513.11 seconds
Started May 14 12:55:47 PM PDT 24
Finished May 14 01:04:22 PM PDT 24
Peak memory 224700 kb
Host smart-1e98bb46-b077-45c4-9945-4ddcd3de87d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346016083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1346016083
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1708506596
Short name T305
Test name
Test status
Simulation time 54516492812 ps
CPU time 70.44 seconds
Started May 14 12:55:22 PM PDT 24
Finished May 14 12:56:34 PM PDT 24
Peak memory 215100 kb
Host smart-4b0cc2f1-352b-4780-a853-472cef0db671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708506596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1708506596
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.627235417
Short name T215
Test name
Test status
Simulation time 2627833748 ps
CPU time 25.3 seconds
Started May 14 12:55:44 PM PDT 24
Finished May 14 12:56:11 PM PDT 24
Peak memory 211348 kb
Host smart-4b0b1acd-0345-4770-baec-84393d07999d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=627235417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.627235417
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3133497088
Short name T173
Test name
Test status
Simulation time 675310373 ps
CPU time 20.38 seconds
Started May 14 12:55:19 PM PDT 24
Finished May 14 12:55:42 PM PDT 24
Peak memory 217492 kb
Host smart-865ff19e-fac0-4357-a67e-1c962a6a709c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133497088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3133497088
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2476842161
Short name T208
Test name
Test status
Simulation time 763186910 ps
CPU time 24.8 seconds
Started May 14 12:55:52 PM PDT 24
Finished May 14 12:56:19 PM PDT 24
Peak memory 217856 kb
Host smart-7ad5f854-2643-43c1-8787-f12785ede5b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476842161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2476842161
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.678084731
Short name T54
Test name
Test status
Simulation time 91155637186 ps
CPU time 897.37 seconds
Started May 14 12:55:45 PM PDT 24
Finished May 14 01:10:44 PM PDT 24
Peak memory 235924 kb
Host smart-734d3ec2-06a9-4e38-8c26-05a061e38300
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678084731 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.678084731
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1942186049
Short name T333
Test name
Test status
Simulation time 6777783714 ps
CPU time 18.65 seconds
Started May 14 12:55:20 PM PDT 24
Finished May 14 12:55:41 PM PDT 24
Peak memory 211488 kb
Host smart-6f14a8af-1276-4eb9-87b9-980b53d8d6de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942186049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1942186049
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1071165103
Short name T256
Test name
Test status
Simulation time 1290868564 ps
CPU time 113.25 seconds
Started May 14 12:55:35 PM PDT 24
Finished May 14 12:57:29 PM PDT 24
Peak memory 238900 kb
Host smart-7454f6ad-4fd5-4a28-8ee6-7ebc74059954
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071165103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1071165103
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4037283934
Short name T189
Test name
Test status
Simulation time 16557010667 ps
CPU time 44.12 seconds
Started May 14 12:55:43 PM PDT 24
Finished May 14 12:56:28 PM PDT 24
Peak memory 214616 kb
Host smart-544f6f27-a99e-4bef-a836-15050f989900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037283934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.4037283934
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1546818417
Short name T287
Test name
Test status
Simulation time 11228053310 ps
CPU time 26.22 seconds
Started May 14 12:55:35 PM PDT 24
Finished May 14 12:56:02 PM PDT 24
Peak memory 211616 kb
Host smart-28374d24-307c-4fff-a0bc-a84b429ca18c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1546818417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1546818417
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2654778885
Short name T324
Test name
Test status
Simulation time 5608377327 ps
CPU time 25.89 seconds
Started May 14 12:55:33 PM PDT 24
Finished May 14 12:56:00 PM PDT 24
Peak memory 216920 kb
Host smart-82104dc4-582d-4970-8d97-ceb4155aef71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654778885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2654778885
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3871376503
Short name T13
Test name
Test status
Simulation time 814384851 ps
CPU time 22.99 seconds
Started May 14 12:55:30 PM PDT 24
Finished May 14 12:55:54 PM PDT 24
Peak memory 216584 kb
Host smart-57027fb7-10d0-4e29-b824-fbd1cba3520f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871376503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3871376503
Directory /workspace/9.rom_ctrl_stress_all/latest
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