Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.63 96.97 93.44 97.88 100.00 98.69 98.03 98.37


Total test records in report: 456
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T305 /workspace/coverage/default/12.rom_ctrl_smoke.14736119 May 16 01:14:59 PM PDT 24 May 16 01:16:11 PM PDT 24 8375895590 ps
T306 /workspace/coverage/default/17.rom_ctrl_smoke.3464536046 May 16 01:15:13 PM PDT 24 May 16 01:15:54 PM PDT 24 2978863801 ps
T307 /workspace/coverage/default/21.rom_ctrl_stress_all.1347113631 May 16 01:15:34 PM PDT 24 May 16 01:16:08 PM PDT 24 915599596 ps
T308 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2373629390 May 16 01:14:56 PM PDT 24 May 16 01:15:22 PM PDT 24 34459667799 ps
T309 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2305195131 May 16 01:15:13 PM PDT 24 May 16 01:18:57 PM PDT 24 14717731654 ps
T310 /workspace/coverage/default/13.rom_ctrl_stress_all.1243766094 May 16 01:15:02 PM PDT 24 May 16 01:16:50 PM PDT 24 11029589117 ps
T311 /workspace/coverage/default/41.rom_ctrl_stress_all.769555719 May 16 01:16:22 PM PDT 24 May 16 01:16:58 PM PDT 24 1028669656 ps
T312 /workspace/coverage/default/12.rom_ctrl_stress_all.4285999033 May 16 01:15:00 PM PDT 24 May 16 01:17:13 PM PDT 24 17218167688 ps
T313 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3554548891 May 16 01:14:32 PM PDT 24 May 16 01:25:06 PM PDT 24 133675812464 ps
T314 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.494812102 May 16 01:16:19 PM PDT 24 May 16 01:16:49 PM PDT 24 7265435003 ps
T315 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1162042548 May 16 01:15:37 PM PDT 24 May 16 01:16:13 PM PDT 24 21449009390 ps
T316 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1288794504 May 16 01:15:12 PM PDT 24 May 16 01:15:28 PM PDT 24 791606036 ps
T317 /workspace/coverage/default/27.rom_ctrl_stress_all.1033142870 May 16 01:16:01 PM PDT 24 May 16 01:17:12 PM PDT 24 5706436687 ps
T318 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.520116934 May 16 01:14:11 PM PDT 24 May 16 01:14:24 PM PDT 24 3504889614 ps
T319 /workspace/coverage/default/45.rom_ctrl_stress_all.667712002 May 16 01:16:32 PM PDT 24 May 16 01:17:26 PM PDT 24 1412153139 ps
T320 /workspace/coverage/default/46.rom_ctrl_stress_all.3604516110 May 16 01:16:25 PM PDT 24 May 16 01:17:18 PM PDT 24 20276686917 ps
T321 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1718402931 May 16 01:16:17 PM PDT 24 May 16 01:24:56 PM PDT 24 105240857709 ps
T322 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2807460423 May 16 01:14:43 PM PDT 24 May 16 01:18:26 PM PDT 24 2829116117 ps
T323 /workspace/coverage/default/35.rom_ctrl_stress_all.3181670857 May 16 01:16:17 PM PDT 24 May 16 01:17:41 PM PDT 24 26935028932 ps
T324 /workspace/coverage/default/19.rom_ctrl_smoke.3732965674 May 16 01:15:30 PM PDT 24 May 16 01:15:53 PM PDT 24 1428213311 ps
T325 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3011278999 May 16 01:15:32 PM PDT 24 May 16 01:16:37 PM PDT 24 7375044560 ps
T326 /workspace/coverage/default/19.rom_ctrl_stress_all.3508994743 May 16 01:15:34 PM PDT 24 May 16 01:16:06 PM PDT 24 6934167883 ps
T327 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.100053176 May 16 01:15:57 PM PDT 24 May 16 01:16:13 PM PDT 24 524905112 ps
T328 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3577222951 May 16 01:15:58 PM PDT 24 May 16 01:16:41 PM PDT 24 6569040574 ps
T329 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2809589233 May 16 01:14:51 PM PDT 24 May 16 01:15:20 PM PDT 24 3885912409 ps
T330 /workspace/coverage/default/4.rom_ctrl_alert_test.3819927862 May 16 01:14:38 PM PDT 24 May 16 01:14:48 PM PDT 24 1500040006 ps
T331 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2969996720 May 16 01:15:57 PM PDT 24 May 16 01:16:09 PM PDT 24 737875268 ps
T332 /workspace/coverage/default/2.rom_ctrl_alert_test.3567465114 May 16 01:14:37 PM PDT 24 May 16 01:14:55 PM PDT 24 4923457967 ps
T333 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3709675434 May 16 01:16:43 PM PDT 24 May 16 01:17:11 PM PDT 24 8497791136 ps
T334 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.582356539 May 16 01:16:40 PM PDT 24 May 16 01:19:57 PM PDT 24 50775664630 ps
T335 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1101788649 May 16 01:16:21 PM PDT 24 May 16 01:22:11 PM PDT 24 4570122463 ps
T53 /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.556534382 May 16 01:16:09 PM PDT 24 May 16 01:42:39 PM PDT 24 83201369324 ps
T336 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.207971507 May 16 01:16:03 PM PDT 24 May 16 01:25:19 PM PDT 24 40401884081 ps
T337 /workspace/coverage/default/9.rom_ctrl_smoke.522997280 May 16 01:14:54 PM PDT 24 May 16 01:15:18 PM PDT 24 523639680 ps
T338 /workspace/coverage/default/3.rom_ctrl_stress_all.253944545 May 16 01:14:38 PM PDT 24 May 16 01:16:59 PM PDT 24 59043441586 ps
T339 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1230249291 May 16 01:15:14 PM PDT 24 May 16 01:15:35 PM PDT 24 689831728 ps
T340 /workspace/coverage/default/49.rom_ctrl_stress_all.3054784426 May 16 01:16:40 PM PDT 24 May 16 01:19:15 PM PDT 24 16090716781 ps
T341 /workspace/coverage/default/14.rom_ctrl_alert_test.2975294569 May 16 01:15:09 PM PDT 24 May 16 01:15:26 PM PDT 24 1204165154 ps
T342 /workspace/coverage/default/26.rom_ctrl_alert_test.4294002479 May 16 01:15:57 PM PDT 24 May 16 01:16:22 PM PDT 24 2699689301 ps
T54 /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.686119360 May 16 01:14:48 PM PDT 24 May 16 03:35:55 PM PDT 24 119398607906 ps
T343 /workspace/coverage/default/28.rom_ctrl_alert_test.386534461 May 16 01:16:08 PM PDT 24 May 16 01:16:18 PM PDT 24 2059859430 ps
T344 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3548395885 May 16 01:14:46 PM PDT 24 May 16 01:15:06 PM PDT 24 5466617902 ps
T345 /workspace/coverage/default/40.rom_ctrl_alert_test.3390033795 May 16 01:16:16 PM PDT 24 May 16 01:16:40 PM PDT 24 2464986137 ps
T346 /workspace/coverage/default/22.rom_ctrl_alert_test.2179302557 May 16 01:15:47 PM PDT 24 May 16 01:16:00 PM PDT 24 983670536 ps
T347 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1610488966 May 16 01:16:08 PM PDT 24 May 16 01:17:18 PM PDT 24 8053848196 ps
T348 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3723958718 May 16 01:16:19 PM PDT 24 May 16 01:17:19 PM PDT 24 40006055534 ps
T349 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.704921077 May 16 01:16:12 PM PDT 24 May 16 01:16:33 PM PDT 24 689274681 ps
T350 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2125429067 May 16 01:15:35 PM PDT 24 May 16 01:16:04 PM PDT 24 1026981717 ps
T351 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3642085355 May 16 01:16:26 PM PDT 24 May 16 01:16:56 PM PDT 24 5697260657 ps
T352 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1230741967 May 16 01:16:41 PM PDT 24 May 16 01:17:30 PM PDT 24 32825327344 ps
T353 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1849442090 May 16 01:14:31 PM PDT 24 May 16 01:19:08 PM PDT 24 8233711433 ps
T354 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1076220764 May 16 01:16:20 PM PDT 24 May 16 01:16:43 PM PDT 24 6597925526 ps
T355 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3757352395 May 16 01:16:01 PM PDT 24 May 16 01:19:24 PM PDT 24 5283828429 ps
T356 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3647292273 May 16 01:16:21 PM PDT 24 May 16 01:16:55 PM PDT 24 18494642474 ps
T357 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2548004129 May 16 01:16:13 PM PDT 24 May 16 01:17:09 PM PDT 24 22383162225 ps
T358 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.236936000 May 16 01:14:54 PM PDT 24 May 16 01:15:32 PM PDT 24 17804308641 ps
T359 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1362724373 May 16 01:14:58 PM PDT 24 May 16 01:15:21 PM PDT 24 332499969 ps
T360 /workspace/coverage/default/23.rom_ctrl_alert_test.2697949132 May 16 01:15:47 PM PDT 24 May 16 01:15:56 PM PDT 24 751586033 ps
T361 /workspace/coverage/default/17.rom_ctrl_stress_all.2749558693 May 16 01:15:10 PM PDT 24 May 16 01:15:31 PM PDT 24 2386578374 ps
T362 /workspace/coverage/default/6.rom_ctrl_stress_all.3579807881 May 16 01:14:44 PM PDT 24 May 16 01:16:39 PM PDT 24 23623784066 ps
T363 /workspace/coverage/default/43.rom_ctrl_alert_test.4109830930 May 16 01:16:27 PM PDT 24 May 16 01:16:37 PM PDT 24 172482926 ps
T55 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3012212983 May 16 01:10:26 PM PDT 24 May 16 01:11:08 PM PDT 24 14429531459 ps
T65 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.964887665 May 16 01:10:26 PM PDT 24 May 16 01:13:12 PM PDT 24 535952371 ps
T71 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1575921215 May 16 01:10:26 PM PDT 24 May 16 01:11:00 PM PDT 24 4211239289 ps
T364 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3736882268 May 16 01:10:13 PM PDT 24 May 16 01:10:32 PM PDT 24 972589646 ps
T66 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1025874229 May 16 01:14:04 PM PDT 24 May 16 01:16:59 PM PDT 24 4180740405 ps
T365 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2982951330 May 16 01:10:47 PM PDT 24 May 16 01:11:12 PM PDT 24 369826532 ps
T78 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1632840818 May 16 01:10:28 PM PDT 24 May 16 01:10:49 PM PDT 24 174396058 ps
T79 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2946579609 May 16 01:10:38 PM PDT 24 May 16 01:11:13 PM PDT 24 10000266472 ps
T116 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1942797122 May 16 01:10:25 PM PDT 24 May 16 01:11:05 PM PDT 24 7049150469 ps
T366 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1430976421 May 16 01:10:38 PM PDT 24 May 16 01:11:06 PM PDT 24 1906733374 ps
T80 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.469851123 May 16 01:10:28 PM PDT 24 May 16 01:12:39 PM PDT 24 20818797769 ps
T367 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3379607993 May 16 01:14:04 PM PDT 24 May 16 01:14:42 PM PDT 24 17744314897 ps
T368 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.692887039 May 16 01:10:46 PM PDT 24 May 16 01:11:21 PM PDT 24 1319005139 ps
T117 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.776171206 May 16 01:10:13 PM PDT 24 May 16 01:11:01 PM PDT 24 20061415080 ps
T81 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.641634211 May 16 01:10:40 PM PDT 24 May 16 01:11:02 PM PDT 24 688914648 ps
T82 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1723475215 May 16 01:10:04 PM PDT 24 May 16 01:10:22 PM PDT 24 661616012 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1790154251 May 16 01:10:07 PM PDT 24 May 16 01:10:24 PM PDT 24 167611971 ps
T67 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3659192061 May 16 01:10:35 PM PDT 24 May 16 01:12:08 PM PDT 24 5254377520 ps
T83 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3712452511 May 16 01:10:04 PM PDT 24 May 16 01:10:36 PM PDT 24 2145023431 ps
T370 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3750628766 May 16 01:10:48 PM PDT 24 May 16 01:11:32 PM PDT 24 3624659877 ps
T84 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3922439846 May 16 01:10:26 PM PDT 24 May 16 01:13:42 PM PDT 24 21204857791 ps
T110 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2448870848 May 16 01:14:21 PM PDT 24 May 16 01:14:56 PM PDT 24 61422614142 ps
T371 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2342708337 May 16 01:10:25 PM PDT 24 May 16 01:10:47 PM PDT 24 267799123 ps
T372 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3716894093 May 16 01:14:14 PM PDT 24 May 16 01:14:45 PM PDT 24 3544323503 ps
T85 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1417301581 May 16 01:10:04 PM PDT 24 May 16 01:11:33 PM PDT 24 6666569652 ps
T373 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2378074938 May 16 01:10:04 PM PDT 24 May 16 01:10:32 PM PDT 24 4587904449 ps
T374 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1242400644 May 16 01:10:03 PM PDT 24 May 16 01:10:45 PM PDT 24 13442708907 ps
T375 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2333100330 May 16 01:10:37 PM PDT 24 May 16 01:11:07 PM PDT 24 4418347541 ps
T376 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2510464786 May 16 01:10:47 PM PDT 24 May 16 01:11:31 PM PDT 24 16803496665 ps
T377 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1487542569 May 16 01:10:35 PM PDT 24 May 16 01:11:03 PM PDT 24 167479331 ps
T119 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.495371885 May 16 01:10:36 PM PDT 24 May 16 01:13:23 PM PDT 24 327707491 ps
T378 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1803205208 May 16 01:10:36 PM PDT 24 May 16 01:11:05 PM PDT 24 4488054897 ps
T86 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2192798926 May 16 01:10:35 PM PDT 24 May 16 01:11:14 PM PDT 24 6718135930 ps
T87 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1531685547 May 16 01:10:37 PM PDT 24 May 16 01:12:37 PM PDT 24 47978281039 ps
T379 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.796152415 May 16 01:10:34 PM PDT 24 May 16 01:12:55 PM PDT 24 15698001720 ps
T97 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3715142598 May 16 01:10:25 PM PDT 24 May 16 01:11:09 PM PDT 24 4280408555 ps
T380 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.12507386 May 16 01:10:37 PM PDT 24 May 16 01:11:18 PM PDT 24 3157785445 ps
T381 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1138232060 May 16 01:10:49 PM PDT 24 May 16 01:11:21 PM PDT 24 494211451 ps
T382 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3039431314 May 16 01:10:46 PM PDT 24 May 16 01:11:13 PM PDT 24 1749546610 ps
T383 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2821346745 May 16 01:10:27 PM PDT 24 May 16 01:10:50 PM PDT 24 167479970 ps
T384 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.389679046 May 16 01:10:13 PM PDT 24 May 16 01:10:38 PM PDT 24 12831284314 ps
T118 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.657372529 May 16 01:10:15 PM PDT 24 May 16 01:12:00 PM PDT 24 11903627094 ps
T385 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1755256059 May 16 01:10:42 PM PDT 24 May 16 01:11:04 PM PDT 24 717546076 ps
T130 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.829481880 May 16 01:10:35 PM PDT 24 May 16 01:12:16 PM PDT 24 2233563515 ps
T386 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4172685643 May 16 01:10:04 PM PDT 24 May 16 01:10:46 PM PDT 24 4356373352 ps
T387 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.317866295 May 16 01:10:09 PM PDT 24 May 16 01:10:40 PM PDT 24 9554030809 ps
T92 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1843222421 May 16 01:10:25 PM PDT 24 May 16 01:11:50 PM PDT 24 2608358705 ps
T93 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2828508426 May 16 01:10:48 PM PDT 24 May 16 01:13:16 PM PDT 24 35542149607 ps
T388 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1733586720 May 16 01:10:14 PM PDT 24 May 16 01:10:36 PM PDT 24 174463607 ps
T111 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2758566235 May 16 01:10:15 PM PDT 24 May 16 01:10:48 PM PDT 24 7277332620 ps
T389 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1483301188 May 16 01:10:16 PM PDT 24 May 16 01:10:57 PM PDT 24 33796148792 ps
T112 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2514331746 May 16 01:10:36 PM PDT 24 May 16 01:11:04 PM PDT 24 358471043 ps
T124 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2672572245 May 16 01:10:34 PM PDT 24 May 16 01:12:07 PM PDT 24 1018251941 ps
T390 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.462439055 May 16 01:10:10 PM PDT 24 May 16 01:10:32 PM PDT 24 689299719 ps
T391 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4070404763 May 16 01:10:17 PM PDT 24 May 16 01:10:57 PM PDT 24 2360402755 ps
T392 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4148414320 May 16 01:10:17 PM PDT 24 May 16 01:10:39 PM PDT 24 181451349 ps
T128 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2721246937 May 16 01:10:26 PM PDT 24 May 16 01:12:20 PM PDT 24 3838280525 ps
T393 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2811367558 May 16 01:10:26 PM PDT 24 May 16 01:11:09 PM PDT 24 44268277796 ps
T94 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1729890347 May 16 01:14:12 PM PDT 24 May 16 01:17:07 PM PDT 24 20820106030 ps
T95 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1986582661 May 16 01:10:28 PM PDT 24 May 16 01:12:37 PM PDT 24 26773761187 ps
T113 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1800205682 May 16 01:10:08 PM PDT 24 May 16 01:10:32 PM PDT 24 1974184002 ps
T394 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2742796541 May 16 01:10:40 PM PDT 24 May 16 01:11:02 PM PDT 24 1030137328 ps
T395 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3326042585 May 16 01:10:44 PM PDT 24 May 16 01:11:07 PM PDT 24 223944759 ps
T96 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1954917953 May 16 01:10:27 PM PDT 24 May 16 01:13:28 PM PDT 24 37157501243 ps
T396 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1323588121 May 16 01:10:03 PM PDT 24 May 16 01:10:33 PM PDT 24 8583740156 ps
T122 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3934898019 May 16 01:10:35 PM PDT 24 May 16 01:12:26 PM PDT 24 24592293798 ps
T114 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3984106816 May 16 01:10:29 PM PDT 24 May 16 01:11:03 PM PDT 24 10452781299 ps
T397 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2880960143 May 16 01:14:34 PM PDT 24 May 16 01:14:59 PM PDT 24 4284563970 ps
T398 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.216820226 May 16 01:10:03 PM PDT 24 May 16 01:10:44 PM PDT 24 11041509270 ps
T399 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2759185208 May 16 01:10:39 PM PDT 24 May 16 01:11:07 PM PDT 24 1828789687 ps
T115 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.320750690 May 16 01:10:27 PM PDT 24 May 16 01:11:06 PM PDT 24 4035257762 ps
T400 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3269820804 May 16 01:10:04 PM PDT 24 May 16 01:10:34 PM PDT 24 7959047815 ps
T98 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3205726961 May 16 01:10:08 PM PDT 24 May 16 01:11:36 PM PDT 24 7125337840 ps
T401 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.8405992 May 16 01:10:34 PM PDT 24 May 16 01:11:16 PM PDT 24 54183600237 ps
T125 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2718055633 May 16 01:10:26 PM PDT 24 May 16 01:12:19 PM PDT 24 14389858117 ps
T402 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2550565263 May 16 01:10:09 PM PDT 24 May 16 01:10:27 PM PDT 24 170739045 ps
T403 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3753595034 May 16 01:10:46 PM PDT 24 May 16 01:11:39 PM PDT 24 767791362 ps
T404 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1807095121 May 16 01:10:16 PM PDT 24 May 16 01:10:45 PM PDT 24 4458861800 ps
T405 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4152645937 May 16 01:10:10 PM PDT 24 May 16 01:10:27 PM PDT 24 167603729 ps
T406 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2156985113 May 16 01:10:04 PM PDT 24 May 16 01:10:46 PM PDT 24 14328720619 ps
T407 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2373450464 May 16 01:10:10 PM PDT 24 May 16 01:10:37 PM PDT 24 1431778364 ps
T408 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1980798156 May 16 01:10:47 PM PDT 24 May 16 01:11:23 PM PDT 24 2721153740 ps
T129 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3116622648 May 16 01:10:48 PM PDT 24 May 16 01:13:56 PM PDT 24 3905272796 ps
T409 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3965299444 May 16 01:10:48 PM PDT 24 May 16 01:11:24 PM PDT 24 9637324758 ps
T410 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3579098350 May 16 01:10:28 PM PDT 24 May 16 01:11:11 PM PDT 24 75546823551 ps
T411 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3179360724 May 16 01:10:03 PM PDT 24 May 16 01:10:21 PM PDT 24 346321751 ps
T412 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.266023077 May 16 01:10:25 PM PDT 24 May 16 01:11:07 PM PDT 24 14078766370 ps
T120 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4272846916 May 16 01:10:27 PM PDT 24 May 16 01:13:13 PM PDT 24 2227040120 ps
T413 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3017065107 May 16 01:10:15 PM PDT 24 May 16 01:10:54 PM PDT 24 7057253114 ps
T99 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1781541406 May 16 01:10:36 PM PDT 24 May 16 01:12:18 PM PDT 24 9352273752 ps
T414 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2126076677 May 16 01:10:28 PM PDT 24 May 16 01:10:58 PM PDT 24 1450274128 ps
T415 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2422139434 May 16 01:10:07 PM PDT 24 May 16 01:10:31 PM PDT 24 3058731883 ps
T131 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4048952149 May 16 01:14:12 PM PDT 24 May 16 01:15:59 PM PDT 24 18034631985 ps
T416 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3475812599 May 16 01:10:36 PM PDT 24 May 16 01:11:26 PM PDT 24 4272235535 ps
T102 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3588462802 May 16 01:10:48 PM PDT 24 May 16 01:11:11 PM PDT 24 1832279827 ps
T417 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3595061818 May 16 01:10:17 PM PDT 24 May 16 01:13:12 PM PDT 24 1957022473 ps
T418 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4129192426 May 16 01:10:04 PM PDT 24 May 16 01:10:40 PM PDT 24 6423595940 ps
T419 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.375726173 May 16 01:10:47 PM PDT 24 May 16 01:11:30 PM PDT 24 9142262513 ps
T420 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4005415819 May 16 01:10:16 PM PDT 24 May 16 01:10:37 PM PDT 24 2041401627 ps
T100 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1981534529 May 16 01:10:15 PM PDT 24 May 16 01:10:57 PM PDT 24 4434455744 ps
T421 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1482915348 May 16 01:10:27 PM PDT 24 May 16 01:11:11 PM PDT 24 3341098026 ps
T101 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2846453403 May 16 01:14:09 PM PDT 24 May 16 01:14:39 PM PDT 24 13724115523 ps
T121 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.489374652 May 16 01:10:47 PM PDT 24 May 16 01:13:50 PM PDT 24 38332471920 ps
T422 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1308246228 May 16 01:10:47 PM PDT 24 May 16 01:11:12 PM PDT 24 658025340 ps
T423 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4246695412 May 16 01:10:15 PM PDT 24 May 16 01:10:57 PM PDT 24 37075860843 ps
T424 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.208722215 May 16 01:10:26 PM PDT 24 May 16 01:10:57 PM PDT 24 3353632607 ps
T425 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3686883119 May 16 01:10:35 PM PDT 24 May 16 01:11:20 PM PDT 24 3186088155 ps
T104 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2331689708 May 16 01:10:47 PM PDT 24 May 16 01:12:01 PM PDT 24 1041548196 ps
T103 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1955468583 May 16 01:10:35 PM PDT 24 May 16 01:12:29 PM PDT 24 27659990833 ps
T426 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3993276779 May 16 01:10:14 PM PDT 24 May 16 01:10:35 PM PDT 24 248952012 ps
T427 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3258915866 May 16 01:10:48 PM PDT 24 May 16 01:11:32 PM PDT 24 14755697152 ps
T428 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.501154389 May 16 01:10:35 PM PDT 24 May 16 01:11:13 PM PDT 24 18040127573 ps
T429 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.558921528 May 16 01:10:16 PM PDT 24 May 16 01:10:35 PM PDT 24 167412806 ps
T430 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1509729197 May 16 01:10:09 PM PDT 24 May 16 01:10:38 PM PDT 24 19767070330 ps
T431 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.357361447 May 16 01:10:16 PM PDT 24 May 16 01:12:09 PM PDT 24 31043199699 ps
T432 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2942445922 May 16 01:10:41 PM PDT 24 May 16 01:11:13 PM PDT 24 6251250656 ps
T433 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1660038527 May 16 01:10:27 PM PDT 24 May 16 01:10:59 PM PDT 24 1855444247 ps
T434 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1927979503 May 16 01:10:16 PM PDT 24 May 16 01:10:58 PM PDT 24 39838912065 ps
T435 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2112373915 May 16 01:14:13 PM PDT 24 May 16 01:14:46 PM PDT 24 30362623958 ps
T436 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1189351475 May 16 01:14:12 PM PDT 24 May 16 01:14:43 PM PDT 24 12877008522 ps
T437 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1870583115 May 16 01:10:17 PM PDT 24 May 16 01:10:36 PM PDT 24 459936368 ps
T126 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2589125085 May 16 01:10:04 PM PDT 24 May 16 01:12:51 PM PDT 24 3954333620 ps
T105 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2423009568 May 16 01:10:08 PM PDT 24 May 16 01:10:54 PM PDT 24 721508230 ps
T438 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3536285450 May 16 01:10:37 PM PDT 24 May 16 01:11:04 PM PDT 24 1875494026 ps
T439 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4014336542 May 16 01:10:17 PM PDT 24 May 16 01:10:36 PM PDT 24 368816502 ps
T440 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1452171894 May 16 01:10:47 PM PDT 24 May 16 01:11:09 PM PDT 24 3294680210 ps
T441 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2374719455 May 16 01:10:48 PM PDT 24 May 16 01:11:19 PM PDT 24 4404139193 ps
T442 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1868362352 May 16 01:10:04 PM PDT 24 May 16 01:10:36 PM PDT 24 8810499304 ps
T106 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3393478993 May 16 01:10:46 PM PDT 24 May 16 01:13:43 PM PDT 24 41158823713 ps
T443 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3313307771 May 16 01:10:28 PM PDT 24 May 16 01:11:13 PM PDT 24 36962249571 ps
T444 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2141695006 May 16 01:10:47 PM PDT 24 May 16 01:11:24 PM PDT 24 2316920385 ps
T445 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1493766853 May 16 01:10:04 PM PDT 24 May 16 01:12:51 PM PDT 24 1293671997 ps
T446 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1062056506 May 16 01:10:37 PM PDT 24 May 16 01:11:15 PM PDT 24 3751526755 ps
T127 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3613672944 May 16 01:10:47 PM PDT 24 May 16 01:13:41 PM PDT 24 2781146034 ps
T447 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1991339278 May 16 01:10:47 PM PDT 24 May 16 01:13:11 PM PDT 24 148136286712 ps
T448 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.324329969 May 16 01:10:15 PM PDT 24 May 16 01:11:21 PM PDT 24 1035169995 ps
T449 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1380688615 May 16 01:10:14 PM PDT 24 May 16 01:10:38 PM PDT 24 3088629618 ps
T450 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2987771147 May 16 01:10:15 PM PDT 24 May 16 01:10:45 PM PDT 24 3463427661 ps
T451 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.443805069 May 16 01:10:47 PM PDT 24 May 16 01:11:16 PM PDT 24 277619735 ps
T452 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.953693520 May 16 01:10:03 PM PDT 24 May 16 01:11:51 PM PDT 24 5305933103 ps
T453 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2636582382 May 16 01:10:26 PM PDT 24 May 16 01:10:51 PM PDT 24 719012986 ps
T123 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4112222328 May 16 01:10:48 PM PDT 24 May 16 01:12:25 PM PDT 24 550972180 ps
T454 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1269682712 May 16 01:10:16 PM PDT 24 May 16 01:10:49 PM PDT 24 8152350015 ps
T455 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1205732902 May 16 01:14:10 PM PDT 24 May 16 01:14:27 PM PDT 24 1094945327 ps
T456 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2035177503 May 16 01:10:15 PM PDT 24 May 16 01:10:34 PM PDT 24 167450627 ps

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.966848982
Short name T4
Test name
Test status
Simulation time 40823686540 ps
CPU time 282.21 seconds
Started May 16 01:16:09 PM PDT 24
Finished May 16 01:20:54 PM PDT 24
Peak memory 239880 kb
Host smart-54838c24-6634-44d6-82e0-a77d7f2878d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966848982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.966848982
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2679154339
Short name T26
Test name
Test status
Simulation time 57344679004 ps
CPU time 777.53 seconds
Started May 16 01:14:30 PM PDT 24
Finished May 16 01:27:30 PM PDT 24
Peak memory 235888 kb
Host smart-a3db4d68-dd7f-411c-afc8-6d9115f9510f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679154339 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.2679154339
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2132503566
Short name T7
Test name
Test status
Simulation time 2231199753 ps
CPU time 23.96 seconds
Started May 16 01:15:08 PM PDT 24
Finished May 16 01:15:33 PM PDT 24
Peak memory 212404 kb
Host smart-77e104ea-b979-464c-9c30-4a017bae7c77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2132503566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2132503566
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.224811754
Short name T23
Test name
Test status
Simulation time 39931768093 ps
CPU time 392.43 seconds
Started May 16 01:16:41 PM PDT 24
Finished May 16 01:23:17 PM PDT 24
Peak memory 240884 kb
Host smart-b1b1b21d-0401-48bf-8aec-c103a1e152c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224811754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.224811754
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3589256897
Short name T11
Test name
Test status
Simulation time 961617261 ps
CPU time 18.46 seconds
Started May 16 01:16:12 PM PDT 24
Finished May 16 01:16:33 PM PDT 24
Peak memory 213832 kb
Host smart-39253eb8-7d92-4bc8-92ed-1b2afb03dcf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589256897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3589256897
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2376606069
Short name T10
Test name
Test status
Simulation time 176062314 ps
CPU time 8.31 seconds
Started May 16 01:15:00 PM PDT 24
Finished May 16 01:15:12 PM PDT 24
Peak memory 211332 kb
Host smart-1cd5cf24-7174-4d56-9649-631a3d96be40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376606069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2376606069
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1025874229
Short name T66
Test name
Test status
Simulation time 4180740405 ps
CPU time 172.87 seconds
Started May 16 01:14:04 PM PDT 24
Finished May 16 01:16:59 PM PDT 24
Peak memory 213708 kb
Host smart-5f217d8a-39c0-446e-a615-c993fcd69314
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025874229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1025874229
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3312712988
Short name T32
Test name
Test status
Simulation time 15959317956 ps
CPU time 138.31 seconds
Started May 16 01:14:33 PM PDT 24
Finished May 16 01:16:53 PM PDT 24
Peak memory 236844 kb
Host smart-ebc1b037-6b0e-46c0-a0a6-7fe402ed8d73
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312712988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3312712988
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1809342904
Short name T143
Test name
Test status
Simulation time 24789422598 ps
CPU time 133.83 seconds
Started May 16 01:16:11 PM PDT 24
Finished May 16 01:18:28 PM PDT 24
Peak memory 220124 kb
Host smart-c876e81a-802d-4c65-abbb-5648206e933b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809342904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1809342904
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3922439846
Short name T84
Test name
Test status
Simulation time 21204857791 ps
CPU time 184.9 seconds
Started May 16 01:10:26 PM PDT 24
Finished May 16 01:13:42 PM PDT 24
Peak memory 215044 kb
Host smart-fedd9dda-bf00-473a-be2f-e1c17583d13d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922439846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3922439846
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.4180836493
Short name T137
Test name
Test status
Simulation time 3321809847 ps
CPU time 15.87 seconds
Started May 16 01:15:59 PM PDT 24
Finished May 16 01:16:17 PM PDT 24
Peak memory 212712 kb
Host smart-75ee2997-5e34-471f-89b6-d444aa674824
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4180836493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.4180836493
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.219886954
Short name T30
Test name
Test status
Simulation time 15321293156 ps
CPU time 601.94 seconds
Started May 16 01:15:01 PM PDT 24
Finished May 16 01:25:06 PM PDT 24
Peak memory 228840 kb
Host smart-9fcc8488-803f-49f0-8692-5ebc168aab70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219886954 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.219886954
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.489374652
Short name T121
Test name
Test status
Simulation time 38332471920 ps
CPU time 167.52 seconds
Started May 16 01:10:47 PM PDT 24
Finished May 16 01:13:50 PM PDT 24
Peak memory 213680 kb
Host smart-f0264007-816d-4e51-9879-2670d59b767e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489374652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.489374652
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3613672944
Short name T127
Test name
Test status
Simulation time 2781146034 ps
CPU time 160.32 seconds
Started May 16 01:10:47 PM PDT 24
Finished May 16 01:13:41 PM PDT 24
Peak memory 213704 kb
Host smart-209bb84f-23cb-4840-bb87-2664a607bd99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613672944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3613672944
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3813047369
Short name T8
Test name
Test status
Simulation time 2889086136 ps
CPU time 44.59 seconds
Started May 16 01:15:10 PM PDT 24
Finished May 16 01:15:56 PM PDT 24
Peak memory 216552 kb
Host smart-7ea026f3-118d-437f-abb4-885b15960db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813047369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3813047369
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1806443094
Short name T190
Test name
Test status
Simulation time 26780857373 ps
CPU time 38.7 seconds
Started May 16 01:14:53 PM PDT 24
Finished May 16 01:15:34 PM PDT 24
Peak memory 215316 kb
Host smart-a8854264-32f4-4526-8f7a-1023d2f95b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806443094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1806443094
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2012991939
Short name T15
Test name
Test status
Simulation time 675177976 ps
CPU time 19.42 seconds
Started May 16 01:14:56 PM PDT 24
Finished May 16 01:15:19 PM PDT 24
Peak memory 214692 kb
Host smart-2ad28a33-1b96-4b0a-ae41-6686d699f241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012991939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2012991939
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2718055633
Short name T125
Test name
Test status
Simulation time 14389858117 ps
CPU time 101.33 seconds
Started May 16 01:10:26 PM PDT 24
Finished May 16 01:12:19 PM PDT 24
Peak memory 212404 kb
Host smart-217213f4-afc1-44d7-8cf5-247890410804
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718055633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2718055633
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1955468583
Short name T103
Test name
Test status
Simulation time 27659990833 ps
CPU time 100.54 seconds
Started May 16 01:10:35 PM PDT 24
Finished May 16 01:12:29 PM PDT 24
Peak memory 215084 kb
Host smart-82884570-3822-4621-9f58-15ee0258f0f4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955468583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1955468583
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4112222328
Short name T123
Test name
Test status
Simulation time 550972180 ps
CPU time 81.44 seconds
Started May 16 01:10:48 PM PDT 24
Finished May 16 01:12:25 PM PDT 24
Peak memory 213288 kb
Host smart-b06a2902-ea15-4510-ad69-ef48558239e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112222328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.4112222328
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2703819879
Short name T132
Test name
Test status
Simulation time 3415761367 ps
CPU time 234.12 seconds
Started May 16 01:15:07 PM PDT 24
Finished May 16 01:19:02 PM PDT 24
Peak memory 228640 kb
Host smart-28613108-cde4-49e8-918c-c17446b17224
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703819879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2703819879
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1800205682
Short name T113
Test name
Test status
Simulation time 1974184002 ps
CPU time 15.36 seconds
Started May 16 01:10:08 PM PDT 24
Finished May 16 01:10:32 PM PDT 24
Peak memory 211692 kb
Host smart-000e619d-8f42-4426-8e0d-17056ccf96cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800205682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1800205682
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1359252637
Short name T107
Test name
Test status
Simulation time 351572069 ps
CPU time 10.53 seconds
Started May 16 01:16:18 PM PDT 24
Finished May 16 01:16:31 PM PDT 24
Peak memory 212200 kb
Host smart-8c2b2041-72a7-483a-9e14-4d7ae195536b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1359252637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1359252637
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.809669716
Short name T29
Test name
Test status
Simulation time 106727772871 ps
CPU time 3889.55 seconds
Started May 16 01:16:40 PM PDT 24
Finished May 16 02:21:33 PM PDT 24
Peak memory 252304 kb
Host smart-a5b279b9-761e-4195-9888-640748bec444
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809669716 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.809669716
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1510983875
Short name T150
Test name
Test status
Simulation time 54377087148 ps
CPU time 597.36 seconds
Started May 16 01:15:01 PM PDT 24
Finished May 16 01:25:01 PM PDT 24
Peak memory 237700 kb
Host smart-4677d440-28c4-4be2-badf-ca0299314c12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510983875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1510983875
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2373450464
Short name T407
Test name
Test status
Simulation time 1431778364 ps
CPU time 17.12 seconds
Started May 16 01:10:10 PM PDT 24
Finished May 16 01:10:37 PM PDT 24
Peak memory 219024 kb
Host smart-96053b67-d567-414c-bbec-2f9de3534007
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373450464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2373450464
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3179360724
Short name T411
Test name
Test status
Simulation time 346321751 ps
CPU time 8.13 seconds
Started May 16 01:10:03 PM PDT 24
Finished May 16 01:10:21 PM PDT 24
Peak memory 210908 kb
Host smart-c90b45aa-8d7c-447e-b2fa-576c7170afe3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179360724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3179360724
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2156985113
Short name T406
Test name
Test status
Simulation time 14328720619 ps
CPU time 32.2 seconds
Started May 16 01:10:04 PM PDT 24
Finished May 16 01:10:46 PM PDT 24
Peak memory 211844 kb
Host smart-c0e3dace-42d4-42c4-910d-79d90053d87d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156985113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2156985113
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1242400644
Short name T374
Test name
Test status
Simulation time 13442708907 ps
CPU time 32.19 seconds
Started May 16 01:10:03 PM PDT 24
Finished May 16 01:10:45 PM PDT 24
Peak memory 217292 kb
Host smart-61db0c4e-e789-4dbf-a8aa-3f314f413058
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242400644 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1242400644
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.317866295
Short name T387
Test name
Test status
Simulation time 9554030809 ps
CPU time 21.88 seconds
Started May 16 01:10:09 PM PDT 24
Finished May 16 01:10:40 PM PDT 24
Peak memory 210900 kb
Host smart-3d92e26b-b71d-42eb-935d-a50dee3966bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317866295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.317866295
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1790154251
Short name T369
Test name
Test status
Simulation time 167611971 ps
CPU time 7.97 seconds
Started May 16 01:10:07 PM PDT 24
Finished May 16 01:10:24 PM PDT 24
Peak memory 210676 kb
Host smart-bf5e5a9f-48b5-4fa8-b16a-e1334806a0da
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790154251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1790154251
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1323588121
Short name T396
Test name
Test status
Simulation time 8583740156 ps
CPU time 19.7 seconds
Started May 16 01:10:03 PM PDT 24
Finished May 16 01:10:33 PM PDT 24
Peak memory 210880 kb
Host smart-14b642b6-906d-4f67-b072-3dbd5aa8bfd3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323588121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1323588121
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2423009568
Short name T105
Test name
Test status
Simulation time 721508230 ps
CPU time 37.52 seconds
Started May 16 01:10:08 PM PDT 24
Finished May 16 01:10:54 PM PDT 24
Peak memory 213240 kb
Host smart-65382efc-4e9c-403f-9e94-be02f8c148c9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423009568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2423009568
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1509729197
Short name T430
Test name
Test status
Simulation time 19767070330 ps
CPU time 20.94 seconds
Started May 16 01:10:09 PM PDT 24
Finished May 16 01:10:38 PM PDT 24
Peak memory 212276 kb
Host smart-9f367691-e5c9-4d0a-a62e-3346baa14eff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509729197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1509729197
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.216820226
Short name T398
Test name
Test status
Simulation time 11041509270 ps
CPU time 30.48 seconds
Started May 16 01:10:03 PM PDT 24
Finished May 16 01:10:44 PM PDT 24
Peak memory 219124 kb
Host smart-01f6747d-30fd-4510-85a6-2b4760576431
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216820226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.216820226
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.953693520
Short name T452
Test name
Test status
Simulation time 5305933103 ps
CPU time 98.29 seconds
Started May 16 01:10:03 PM PDT 24
Finished May 16 01:11:51 PM PDT 24
Peak memory 219208 kb
Host smart-f13d6434-f3a8-41e2-a980-de6cce243dee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953693520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.953693520
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1723475215
Short name T82
Test name
Test status
Simulation time 661616012 ps
CPU time 8.11 seconds
Started May 16 01:10:04 PM PDT 24
Finished May 16 01:10:22 PM PDT 24
Peak memory 210880 kb
Host smart-063109fb-cb5a-438a-af63-901346e7e095
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723475215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1723475215
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1868362352
Short name T442
Test name
Test status
Simulation time 8810499304 ps
CPU time 22.54 seconds
Started May 16 01:10:04 PM PDT 24
Finished May 16 01:10:36 PM PDT 24
Peak memory 211720 kb
Host smart-2fe58129-db6c-4171-9c3e-9c1f47bb46c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868362352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1868362352
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3712452511
Short name T83
Test name
Test status
Simulation time 2145023431 ps
CPU time 22.41 seconds
Started May 16 01:10:04 PM PDT 24
Finished May 16 01:10:36 PM PDT 24
Peak memory 211692 kb
Host smart-601e2785-f855-499d-988e-d95245b54bd1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712452511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3712452511
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3269820804
Short name T400
Test name
Test status
Simulation time 7959047815 ps
CPU time 20.39 seconds
Started May 16 01:10:04 PM PDT 24
Finished May 16 01:10:34 PM PDT 24
Peak memory 216528 kb
Host smart-ffdabef8-c5c7-4fc8-ab9f-5d3851facae6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269820804 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3269820804
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4129192426
Short name T418
Test name
Test status
Simulation time 6423595940 ps
CPU time 26.77 seconds
Started May 16 01:10:04 PM PDT 24
Finished May 16 01:10:40 PM PDT 24
Peak memory 211876 kb
Host smart-828be040-ce2c-404c-910f-cc87f4d48f34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129192426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4129192426
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2550565263
Short name T402
Test name
Test status
Simulation time 170739045 ps
CPU time 8.03 seconds
Started May 16 01:10:09 PM PDT 24
Finished May 16 01:10:27 PM PDT 24
Peak memory 210724 kb
Host smart-e7d81ee2-f0c1-4c6a-bbe6-954d86bb6d5b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550565263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2550565263
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4172685643
Short name T386
Test name
Test status
Simulation time 4356373352 ps
CPU time 31.89 seconds
Started May 16 01:10:04 PM PDT 24
Finished May 16 01:10:46 PM PDT 24
Peak memory 210892 kb
Host smart-ad71cf50-7bf1-4d4d-a294-90aade276ae9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172685643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.4172685643
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3205726961
Short name T98
Test name
Test status
Simulation time 7125337840 ps
CPU time 79.25 seconds
Started May 16 01:10:08 PM PDT 24
Finished May 16 01:11:36 PM PDT 24
Peak memory 219116 kb
Host smart-ce4c7164-87a6-4e89-9c61-c3eba81a01d7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205726961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3205726961
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.462439055
Short name T390
Test name
Test status
Simulation time 689299719 ps
CPU time 12.83 seconds
Started May 16 01:10:10 PM PDT 24
Finished May 16 01:10:32 PM PDT 24
Peak memory 217292 kb
Host smart-9ab9cc9a-6619-4cff-bb53-70d7c4f5853a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462439055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.462439055
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1493766853
Short name T445
Test name
Test status
Simulation time 1293671997 ps
CPU time 157.92 seconds
Started May 16 01:10:04 PM PDT 24
Finished May 16 01:12:51 PM PDT 24
Peak memory 219072 kb
Host smart-522372fd-5b36-4f78-b458-681fcff7eae0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493766853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1493766853
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3326042585
Short name T395
Test name
Test status
Simulation time 223944759 ps
CPU time 9.38 seconds
Started May 16 01:10:44 PM PDT 24
Finished May 16 01:11:07 PM PDT 24
Peak memory 216752 kb
Host smart-16646e5d-91ef-4b6b-a996-f6ae21cc5878
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326042585 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3326042585
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3536285450
Short name T438
Test name
Test status
Simulation time 1875494026 ps
CPU time 13.74 seconds
Started May 16 01:10:37 PM PDT 24
Finished May 16 01:11:04 PM PDT 24
Peak memory 210768 kb
Host smart-83abe551-1273-4f1d-be14-459049fcb96e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536285450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3536285450
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2942445922
Short name T432
Test name
Test status
Simulation time 6251250656 ps
CPU time 17.72 seconds
Started May 16 01:10:41 PM PDT 24
Finished May 16 01:11:13 PM PDT 24
Peak memory 212068 kb
Host smart-0b56534a-cd74-48a4-92be-c099bd0f1634
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942445922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2942445922
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2759185208
Short name T399
Test name
Test status
Simulation time 1828789687 ps
CPU time 13.62 seconds
Started May 16 01:10:39 PM PDT 24
Finished May 16 01:11:07 PM PDT 24
Peak memory 217284 kb
Host smart-0ed4501c-aec4-43de-ad9c-577122b55418
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759185208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2759185208
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3934898019
Short name T122
Test name
Test status
Simulation time 24592293798 ps
CPU time 97.83 seconds
Started May 16 01:10:35 PM PDT 24
Finished May 16 01:12:26 PM PDT 24
Peak memory 219084 kb
Host smart-c4f03b6f-f8f2-4b25-9067-fd7b2d4d2aa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934898019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3934898019
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.501154389
Short name T428
Test name
Test status
Simulation time 18040127573 ps
CPU time 24.62 seconds
Started May 16 01:10:35 PM PDT 24
Finished May 16 01:11:13 PM PDT 24
Peak memory 215048 kb
Host smart-9c9623a2-eebf-4d99-bd33-03d226288739
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501154389 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.501154389
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1755256059
Short name T385
Test name
Test status
Simulation time 717546076 ps
CPU time 8.35 seconds
Started May 16 01:10:42 PM PDT 24
Finished May 16 01:11:04 PM PDT 24
Peak memory 210844 kb
Host smart-812665ad-1841-4f69-a2a7-1eb6c5e60bfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755256059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1755256059
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1781541406
Short name T99
Test name
Test status
Simulation time 9352273752 ps
CPU time 87.51 seconds
Started May 16 01:10:36 PM PDT 24
Finished May 16 01:12:18 PM PDT 24
Peak memory 214012 kb
Host smart-6cc491d6-161b-48be-b8c4-b05876f1e3a9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781541406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1781541406
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2192798926
Short name T86
Test name
Test status
Simulation time 6718135930 ps
CPU time 25.55 seconds
Started May 16 01:10:35 PM PDT 24
Finished May 16 01:11:14 PM PDT 24
Peak memory 212412 kb
Host smart-7a9e70e7-361e-4fd0-bc82-b1b1fd7e7776
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192798926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2192798926
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3475812599
Short name T416
Test name
Test status
Simulation time 4272235535 ps
CPU time 36.65 seconds
Started May 16 01:10:36 PM PDT 24
Finished May 16 01:11:26 PM PDT 24
Peak memory 217248 kb
Host smart-5375d1b5-2bb7-4e1c-9064-f7ba33e00945
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475812599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3475812599
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2672572245
Short name T124
Test name
Test status
Simulation time 1018251941 ps
CPU time 79.88 seconds
Started May 16 01:10:34 PM PDT 24
Finished May 16 01:12:07 PM PDT 24
Peak memory 213156 kb
Host smart-a8786286-8d7d-4891-859d-5fd038eb4601
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672572245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2672572245
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1430976421
Short name T366
Test name
Test status
Simulation time 1906733374 ps
CPU time 14.29 seconds
Started May 16 01:10:38 PM PDT 24
Finished May 16 01:11:06 PM PDT 24
Peak memory 219100 kb
Host smart-8cb49bd3-1390-48ab-a6f9-0018f6b191c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430976421 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1430976421
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2742796541
Short name T394
Test name
Test status
Simulation time 1030137328 ps
CPU time 8.15 seconds
Started May 16 01:10:40 PM PDT 24
Finished May 16 01:11:02 PM PDT 24
Peak memory 210864 kb
Host smart-d6afae4b-050d-4058-8cf3-f4af3c87c8b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742796541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2742796541
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.796152415
Short name T379
Test name
Test status
Simulation time 15698001720 ps
CPU time 127.99 seconds
Started May 16 01:10:34 PM PDT 24
Finished May 16 01:12:55 PM PDT 24
Peak memory 214176 kb
Host smart-21be964d-6e66-40e1-a696-0019012a5c6f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796152415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.796152415
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.8405992
Short name T401
Test name
Test status
Simulation time 54183600237 ps
CPU time 30.25 seconds
Started May 16 01:10:34 PM PDT 24
Finished May 16 01:11:16 PM PDT 24
Peak memory 212192 kb
Host smart-5214c04e-46c6-4d85-a24c-60e968d0327a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8405992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctr
l_same_csr_outstanding.8405992
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3686883119
Short name T425
Test name
Test status
Simulation time 3186088155 ps
CPU time 31.2 seconds
Started May 16 01:10:35 PM PDT 24
Finished May 16 01:11:20 PM PDT 24
Peak memory 218332 kb
Host smart-66db1337-8b43-4e92-883f-1970350ea0e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686883119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3686883119
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3659192061
Short name T67
Test name
Test status
Simulation time 5254377520 ps
CPU time 79.6 seconds
Started May 16 01:10:35 PM PDT 24
Finished May 16 01:12:08 PM PDT 24
Peak memory 213600 kb
Host smart-75d06a0a-9f6b-44d2-8907-eb7b26837445
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659192061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3659192061
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.12507386
Short name T380
Test name
Test status
Simulation time 3157785445 ps
CPU time 27.19 seconds
Started May 16 01:10:37 PM PDT 24
Finished May 16 01:11:18 PM PDT 24
Peak memory 216444 kb
Host smart-056fae82-0055-4597-90c0-e0b36ad1fa49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12507386 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.12507386
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2333100330
Short name T375
Test name
Test status
Simulation time 4418347541 ps
CPU time 15.56 seconds
Started May 16 01:10:37 PM PDT 24
Finished May 16 01:11:07 PM PDT 24
Peak memory 211088 kb
Host smart-ba05712c-d87a-4561-92bf-edd8eed95af3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333100330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2333100330
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1531685547
Short name T87
Test name
Test status
Simulation time 47978281039 ps
CPU time 106.67 seconds
Started May 16 01:10:37 PM PDT 24
Finished May 16 01:12:37 PM PDT 24
Peak memory 214068 kb
Host smart-63f8ecd2-8650-45c2-bce8-5e80e3ba860f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531685547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1531685547
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2946579609
Short name T79
Test name
Test status
Simulation time 10000266472 ps
CPU time 21.17 seconds
Started May 16 01:10:38 PM PDT 24
Finished May 16 01:11:13 PM PDT 24
Peak memory 212312 kb
Host smart-5b666e6d-08c2-46d9-9b76-d9fb70d467da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946579609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2946579609
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1062056506
Short name T446
Test name
Test status
Simulation time 3751526755 ps
CPU time 24.52 seconds
Started May 16 01:10:37 PM PDT 24
Finished May 16 01:11:15 PM PDT 24
Peak memory 219184 kb
Host smart-177b5caa-6cf4-40fb-9717-632274dc2fed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062056506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1062056506
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.829481880
Short name T130
Test name
Test status
Simulation time 2233563515 ps
CPU time 88.36 seconds
Started May 16 01:10:35 PM PDT 24
Finished May 16 01:12:16 PM PDT 24
Peak memory 219116 kb
Host smart-58b85b74-4ca0-4b79-9a25-e83ae2101564
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829481880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.829481880
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3750628766
Short name T370
Test name
Test status
Simulation time 3624659877 ps
CPU time 29.21 seconds
Started May 16 01:10:48 PM PDT 24
Finished May 16 01:11:32 PM PDT 24
Peak memory 214468 kb
Host smart-734392bd-3e0f-4e01-9cbd-0539bed50b18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750628766 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3750628766
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3588462802
Short name T102
Test name
Test status
Simulation time 1832279827 ps
CPU time 8.21 seconds
Started May 16 01:10:48 PM PDT 24
Finished May 16 01:11:11 PM PDT 24
Peak memory 210788 kb
Host smart-e8dc5fff-38c8-47cf-bf01-e4c92cf2d9d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588462802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3588462802
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3393478993
Short name T106
Test name
Test status
Simulation time 41158823713 ps
CPU time 162.6 seconds
Started May 16 01:10:46 PM PDT 24
Finished May 16 01:13:43 PM PDT 24
Peak memory 219148 kb
Host smart-8b609ba3-f47c-4d94-93e5-46c46ba4ee65
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393478993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3393478993
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3965299444
Short name T409
Test name
Test status
Simulation time 9637324758 ps
CPU time 21.57 seconds
Started May 16 01:10:48 PM PDT 24
Finished May 16 01:11:24 PM PDT 24
Peak memory 212136 kb
Host smart-b34f8b02-6da6-4db3-9560-22a3299e6ceb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965299444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3965299444
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1980798156
Short name T408
Test name
Test status
Simulation time 2721153740 ps
CPU time 21.84 seconds
Started May 16 01:10:47 PM PDT 24
Finished May 16 01:11:23 PM PDT 24
Peak memory 219172 kb
Host smart-17fed1c4-e8ba-461b-b268-078ece05e6f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980798156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1980798156
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3116622648
Short name T129
Test name
Test status
Simulation time 3905272796 ps
CPU time 173.81 seconds
Started May 16 01:10:48 PM PDT 24
Finished May 16 01:13:56 PM PDT 24
Peak memory 213432 kb
Host smart-a43c4d81-f5e7-4121-99b3-a29f03d51485
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116622648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3116622648
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2982951330
Short name T365
Test name
Test status
Simulation time 369826532 ps
CPU time 9.48 seconds
Started May 16 01:10:47 PM PDT 24
Finished May 16 01:11:12 PM PDT 24
Peak memory 219104 kb
Host smart-71a069bc-039a-4541-8718-a8f499c3ace0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982951330 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2982951330
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1452171894
Short name T440
Test name
Test status
Simulation time 3294680210 ps
CPU time 8.1 seconds
Started May 16 01:10:47 PM PDT 24
Finished May 16 01:11:09 PM PDT 24
Peak memory 210996 kb
Host smart-4a13eb14-d6be-4c0d-b011-55ad1da806d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452171894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1452171894
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2331689708
Short name T104
Test name
Test status
Simulation time 1041548196 ps
CPU time 58.28 seconds
Started May 16 01:10:47 PM PDT 24
Finished May 16 01:12:01 PM PDT 24
Peak memory 215040 kb
Host smart-0bc1b4d2-1a8d-4468-991e-5994bd91df4c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331689708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2331689708
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1308246228
Short name T422
Test name
Test status
Simulation time 658025340 ps
CPU time 11.03 seconds
Started May 16 01:10:47 PM PDT 24
Finished May 16 01:11:12 PM PDT 24
Peak memory 210852 kb
Host smart-f36eb999-a873-45d3-9eca-5c8ce57c0274
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308246228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1308246228
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.692887039
Short name T368
Test name
Test status
Simulation time 1319005139 ps
CPU time 21.52 seconds
Started May 16 01:10:46 PM PDT 24
Finished May 16 01:11:21 PM PDT 24
Peak memory 219088 kb
Host smart-9afb01a5-ccfa-4efa-a629-870ed76db9a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692887039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.692887039
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3039431314
Short name T382
Test name
Test status
Simulation time 1749546610 ps
CPU time 11.91 seconds
Started May 16 01:10:46 PM PDT 24
Finished May 16 01:11:13 PM PDT 24
Peak memory 219116 kb
Host smart-f562691b-edf7-47ff-bb25-3ede1eb7657c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039431314 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3039431314
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2374719455
Short name T441
Test name
Test status
Simulation time 4404139193 ps
CPU time 15.52 seconds
Started May 16 01:10:48 PM PDT 24
Finished May 16 01:11:19 PM PDT 24
Peak memory 210968 kb
Host smart-a77def45-956a-41cd-bbfa-c186cc6b8a12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374719455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2374719455
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2828508426
Short name T93
Test name
Test status
Simulation time 35542149607 ps
CPU time 132.42 seconds
Started May 16 01:10:48 PM PDT 24
Finished May 16 01:13:16 PM PDT 24
Peak memory 219172 kb
Host smart-45f843cd-da62-4637-a338-cca2200ada55
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828508426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2828508426
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.375726173
Short name T419
Test name
Test status
Simulation time 9142262513 ps
CPU time 27.66 seconds
Started May 16 01:10:47 PM PDT 24
Finished May 16 01:11:30 PM PDT 24
Peak memory 212268 kb
Host smart-c7c129a8-caa9-4e43-b71d-568a3643aee8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375726173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.375726173
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1138232060
Short name T381
Test name
Test status
Simulation time 494211451 ps
CPU time 17.4 seconds
Started May 16 01:10:49 PM PDT 24
Finished May 16 01:11:21 PM PDT 24
Peak memory 217176 kb
Host smart-6964abb5-03fa-4820-912a-6b264c927ddd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138232060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1138232060
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2141695006
Short name T444
Test name
Test status
Simulation time 2316920385 ps
CPU time 22.74 seconds
Started May 16 01:10:47 PM PDT 24
Finished May 16 01:11:24 PM PDT 24
Peak memory 219068 kb
Host smart-6dd398ec-c107-46a9-85fc-037cbc6eed29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141695006 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2141695006
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3258915866
Short name T427
Test name
Test status
Simulation time 14755697152 ps
CPU time 29.78 seconds
Started May 16 01:10:48 PM PDT 24
Finished May 16 01:11:32 PM PDT 24
Peak memory 211872 kb
Host smart-f94e3318-6833-47f6-864b-53fc96ca1f04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258915866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3258915866
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1991339278
Short name T447
Test name
Test status
Simulation time 148136286712 ps
CPU time 130.41 seconds
Started May 16 01:10:47 PM PDT 24
Finished May 16 01:13:11 PM PDT 24
Peak memory 216112 kb
Host smart-a0450ecc-485a-4bae-87b7-776357fb7758
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991339278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1991339278
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.443805069
Short name T451
Test name
Test status
Simulation time 277619735 ps
CPU time 13.81 seconds
Started May 16 01:10:47 PM PDT 24
Finished May 16 01:11:16 PM PDT 24
Peak memory 212144 kb
Host smart-9094a278-bc83-4b0f-90a6-e54984acc96e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443805069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.443805069
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2510464786
Short name T376
Test name
Test status
Simulation time 16803496665 ps
CPU time 30.63 seconds
Started May 16 01:10:47 PM PDT 24
Finished May 16 01:11:31 PM PDT 24
Peak memory 216504 kb
Host smart-87fba78b-58f2-40c7-b7e4-e2908e0e9baf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510464786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2510464786
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1189351475
Short name T436
Test name
Test status
Simulation time 12877008522 ps
CPU time 28.85 seconds
Started May 16 01:14:12 PM PDT 24
Finished May 16 01:14:43 PM PDT 24
Peak memory 219180 kb
Host smart-cfaf9d63-8657-44cc-84e1-96017b7cdf8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189351475 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1189351475
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2846453403
Short name T101
Test name
Test status
Simulation time 13724115523 ps
CPU time 28.7 seconds
Started May 16 01:14:09 PM PDT 24
Finished May 16 01:14:39 PM PDT 24
Peak memory 211952 kb
Host smart-eb8ba4ad-eb54-4947-9f25-d0578746bd90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846453403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2846453403
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3753595034
Short name T403
Test name
Test status
Simulation time 767791362 ps
CPU time 38.99 seconds
Started May 16 01:10:46 PM PDT 24
Finished May 16 01:11:39 PM PDT 24
Peak memory 211216 kb
Host smart-55f1b32f-f3a5-469a-9e65-165d8b5cd80c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753595034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3753595034
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2448870848
Short name T110
Test name
Test status
Simulation time 61422614142 ps
CPU time 32.31 seconds
Started May 16 01:14:21 PM PDT 24
Finished May 16 01:14:56 PM PDT 24
Peak memory 212404 kb
Host smart-7a81c1df-251a-46f6-9c15-c9ac4f10f742
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448870848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2448870848
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3379607993
Short name T367
Test name
Test status
Simulation time 17744314897 ps
CPU time 35.81 seconds
Started May 16 01:14:04 PM PDT 24
Finished May 16 01:14:42 PM PDT 24
Peak memory 217216 kb
Host smart-b3985069-5f31-49be-bb3c-0921eb1782a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379607993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3379607993
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1205732902
Short name T455
Test name
Test status
Simulation time 1094945327 ps
CPU time 16.31 seconds
Started May 16 01:14:10 PM PDT 24
Finished May 16 01:14:27 PM PDT 24
Peak memory 216332 kb
Host smart-b16ebfda-374d-4920-8d75-983075f2364b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205732902 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1205732902
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3716894093
Short name T372
Test name
Test status
Simulation time 3544323503 ps
CPU time 29.51 seconds
Started May 16 01:14:14 PM PDT 24
Finished May 16 01:14:45 PM PDT 24
Peak memory 211452 kb
Host smart-6b75ad2e-3961-42ea-9389-176df49f4c2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716894093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3716894093
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1729890347
Short name T94
Test name
Test status
Simulation time 20820106030 ps
CPU time 173.24 seconds
Started May 16 01:14:12 PM PDT 24
Finished May 16 01:17:07 PM PDT 24
Peak memory 215332 kb
Host smart-1a882c35-6c03-4e24-abe4-6efd2c23bd02
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729890347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1729890347
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2112373915
Short name T435
Test name
Test status
Simulation time 30362623958 ps
CPU time 30.95 seconds
Started May 16 01:14:13 PM PDT 24
Finished May 16 01:14:46 PM PDT 24
Peak memory 211156 kb
Host smart-81ccb1f6-84ed-4b40-b276-f2a7ce74e9aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112373915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2112373915
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2880960143
Short name T397
Test name
Test status
Simulation time 4284563970 ps
CPU time 23.83 seconds
Started May 16 01:14:34 PM PDT 24
Finished May 16 01:14:59 PM PDT 24
Peak memory 218328 kb
Host smart-a5e4bc02-526b-476c-a737-aa1aa8e16fa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880960143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2880960143
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4048952149
Short name T131
Test name
Test status
Simulation time 18034631985 ps
CPU time 105.12 seconds
Started May 16 01:14:12 PM PDT 24
Finished May 16 01:15:59 PM PDT 24
Peak memory 213412 kb
Host smart-87de686e-401b-4ecc-a05d-6a9c99e282ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048952149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.4048952149
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1483301188
Short name T389
Test name
Test status
Simulation time 33796148792 ps
CPU time 31.12 seconds
Started May 16 01:10:16 PM PDT 24
Finished May 16 01:10:57 PM PDT 24
Peak memory 219096 kb
Host smart-223b8368-f97c-453a-8aae-cef186b55df0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483301188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1483301188
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.558921528
Short name T429
Test name
Test status
Simulation time 167412806 ps
CPU time 8.23 seconds
Started May 16 01:10:16 PM PDT 24
Finished May 16 01:10:35 PM PDT 24
Peak memory 210884 kb
Host smart-6c899764-0c9b-404e-aca1-8249369bcd35
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558921528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.558921528
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4070404763
Short name T391
Test name
Test status
Simulation time 2360402755 ps
CPU time 29.63 seconds
Started May 16 01:10:17 PM PDT 24
Finished May 16 01:10:57 PM PDT 24
Peak memory 211552 kb
Host smart-345f4ef8-f3d7-4632-89ce-79a93755d26a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070404763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.4070404763
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3736882268
Short name T364
Test name
Test status
Simulation time 972589646 ps
CPU time 8.96 seconds
Started May 16 01:10:13 PM PDT 24
Finished May 16 01:10:32 PM PDT 24
Peak memory 215096 kb
Host smart-9f26051c-a762-47b3-aafc-f3991ddb06d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736882268 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3736882268
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.389679046
Short name T384
Test name
Test status
Simulation time 12831284314 ps
CPU time 14.62 seconds
Started May 16 01:10:13 PM PDT 24
Finished May 16 01:10:38 PM PDT 24
Peak memory 210940 kb
Host smart-0da1f6c7-235b-4575-8d81-38f04e54b01a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389679046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.389679046
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.4152645937
Short name T405
Test name
Test status
Simulation time 167603729 ps
CPU time 7.79 seconds
Started May 16 01:10:10 PM PDT 24
Finished May 16 01:10:27 PM PDT 24
Peak memory 210688 kb
Host smart-3e8a6a5d-24d4-4821-82b7-c049a2f4ea1b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152645937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.4152645937
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2422139434
Short name T415
Test name
Test status
Simulation time 3058731883 ps
CPU time 14.76 seconds
Started May 16 01:10:07 PM PDT 24
Finished May 16 01:10:31 PM PDT 24
Peak memory 210768 kb
Host smart-9c5e7531-915e-44ab-8bcd-f09fcb1e78e1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422139434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2422139434
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1417301581
Short name T85
Test name
Test status
Simulation time 6666569652 ps
CPU time 79.31 seconds
Started May 16 01:10:04 PM PDT 24
Finished May 16 01:11:33 PM PDT 24
Peak memory 214256 kb
Host smart-d9c214e3-d46d-488c-a115-ea57f60df3c5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417301581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1417301581
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3017065107
Short name T413
Test name
Test status
Simulation time 7057253114 ps
CPU time 29.25 seconds
Started May 16 01:10:15 PM PDT 24
Finished May 16 01:10:54 PM PDT 24
Peak memory 212220 kb
Host smart-f8f3f622-0d4d-4238-af46-dc2e3e149a03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017065107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3017065107
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2378074938
Short name T373
Test name
Test status
Simulation time 4587904449 ps
CPU time 18.57 seconds
Started May 16 01:10:04 PM PDT 24
Finished May 16 01:10:32 PM PDT 24
Peak memory 219136 kb
Host smart-925d033a-d7c8-4c3b-b09b-e092bce18f07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378074938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2378074938
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2589125085
Short name T126
Test name
Test status
Simulation time 3954333620 ps
CPU time 157.37 seconds
Started May 16 01:10:04 PM PDT 24
Finished May 16 01:12:51 PM PDT 24
Peak memory 213688 kb
Host smart-d7282ac5-d62c-4e3f-84c2-2fb709bdf289
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589125085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2589125085
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1981534529
Short name T100
Test name
Test status
Simulation time 4434455744 ps
CPU time 31.83 seconds
Started May 16 01:10:15 PM PDT 24
Finished May 16 01:10:57 PM PDT 24
Peak memory 211440 kb
Host smart-ae7a3a16-12a4-4b79-80a0-34e40549c4d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981534529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1981534529
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2987771147
Short name T450
Test name
Test status
Simulation time 3463427661 ps
CPU time 19.23 seconds
Started May 16 01:10:15 PM PDT 24
Finished May 16 01:10:45 PM PDT 24
Peak memory 211664 kb
Host smart-eef29f2c-c79b-4255-a74a-225f57ae15b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987771147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2987771147
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4148414320
Short name T392
Test name
Test status
Simulation time 181451349 ps
CPU time 11.91 seconds
Started May 16 01:10:17 PM PDT 24
Finished May 16 01:10:39 PM PDT 24
Peak memory 211272 kb
Host smart-a70f8bc9-b8d3-4306-8529-93094bc4f4eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148414320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.4148414320
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1380688615
Short name T449
Test name
Test status
Simulation time 3088629618 ps
CPU time 13.86 seconds
Started May 16 01:10:14 PM PDT 24
Finished May 16 01:10:38 PM PDT 24
Peak memory 215064 kb
Host smart-41e5d87f-7470-47b6-b58e-a2f3b84aba30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380688615 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1380688615
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1870583115
Short name T437
Test name
Test status
Simulation time 459936368 ps
CPU time 8.11 seconds
Started May 16 01:10:17 PM PDT 24
Finished May 16 01:10:36 PM PDT 24
Peak memory 210872 kb
Host smart-551cc48f-d1b0-4e2d-b7e3-68bfbc85f608
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870583115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1870583115
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1807095121
Short name T404
Test name
Test status
Simulation time 4458861800 ps
CPU time 18.3 seconds
Started May 16 01:10:16 PM PDT 24
Finished May 16 01:10:45 PM PDT 24
Peak memory 210800 kb
Host smart-89116a7d-fd5a-4901-814b-9924121330b5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807095121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1807095121
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1269682712
Short name T454
Test name
Test status
Simulation time 8152350015 ps
CPU time 21.75 seconds
Started May 16 01:10:16 PM PDT 24
Finished May 16 01:10:49 PM PDT 24
Peak memory 210756 kb
Host smart-361366af-611b-4e2c-89b8-ec97aa05737e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269682712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1269682712
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.324329969
Short name T448
Test name
Test status
Simulation time 1035169995 ps
CPU time 56.45 seconds
Started May 16 01:10:15 PM PDT 24
Finished May 16 01:11:21 PM PDT 24
Peak memory 214596 kb
Host smart-048574d9-33cf-4b3f-bcee-edb7334315c6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324329969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.324329969
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2758566235
Short name T111
Test name
Test status
Simulation time 7277332620 ps
CPU time 23 seconds
Started May 16 01:10:15 PM PDT 24
Finished May 16 01:10:48 PM PDT 24
Peak memory 212476 kb
Host smart-f15ec8ea-c31b-43b4-95e8-19c07355bc25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758566235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2758566235
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1733586720
Short name T388
Test name
Test status
Simulation time 174463607 ps
CPU time 11.57 seconds
Started May 16 01:10:14 PM PDT 24
Finished May 16 01:10:36 PM PDT 24
Peak memory 217064 kb
Host smart-5b55aa08-fda4-44aa-9385-e990aabcb547
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733586720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1733586720
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3595061818
Short name T417
Test name
Test status
Simulation time 1957022473 ps
CPU time 164.44 seconds
Started May 16 01:10:17 PM PDT 24
Finished May 16 01:13:12 PM PDT 24
Peak memory 213544 kb
Host smart-2257e978-6973-4c0c-a2bd-f878ddca7454
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595061818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3595061818
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4014336542
Short name T439
Test name
Test status
Simulation time 368816502 ps
CPU time 8.28 seconds
Started May 16 01:10:17 PM PDT 24
Finished May 16 01:10:36 PM PDT 24
Peak memory 210896 kb
Host smart-cbd0999e-bf57-4c71-be43-bf7382fa3561
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014336542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.4014336542
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3993276779
Short name T426
Test name
Test status
Simulation time 248952012 ps
CPU time 10.04 seconds
Started May 16 01:10:14 PM PDT 24
Finished May 16 01:10:35 PM PDT 24
Peak memory 210856 kb
Host smart-76b22563-f686-41b1-a53b-f7463c0248d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993276779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3993276779
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.776171206
Short name T117
Test name
Test status
Simulation time 20061415080 ps
CPU time 37.51 seconds
Started May 16 01:10:13 PM PDT 24
Finished May 16 01:11:01 PM PDT 24
Peak memory 211956 kb
Host smart-4d868f96-497b-4beb-9758-5b5145e4dba3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776171206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.776171206
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1660038527
Short name T433
Test name
Test status
Simulation time 1855444247 ps
CPU time 19.59 seconds
Started May 16 01:10:27 PM PDT 24
Finished May 16 01:10:59 PM PDT 24
Peak memory 216592 kb
Host smart-c2f3ff2d-4181-421a-8c91-c6504bd1b21a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660038527 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1660038527
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2035177503
Short name T456
Test name
Test status
Simulation time 167450627 ps
CPU time 8.28 seconds
Started May 16 01:10:15 PM PDT 24
Finished May 16 01:10:34 PM PDT 24
Peak memory 210844 kb
Host smart-bd550e42-06de-418b-8349-3235dc726762
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035177503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2035177503
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4246695412
Short name T423
Test name
Test status
Simulation time 37075860843 ps
CPU time 31.53 seconds
Started May 16 01:10:15 PM PDT 24
Finished May 16 01:10:57 PM PDT 24
Peak memory 210840 kb
Host smart-2f2f24bf-2f8b-4aed-b664-9e269bd926cc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246695412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.4246695412
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4005415819
Short name T420
Test name
Test status
Simulation time 2041401627 ps
CPU time 10.49 seconds
Started May 16 01:10:16 PM PDT 24
Finished May 16 01:10:37 PM PDT 24
Peak memory 210788 kb
Host smart-147e79f2-378e-4a53-aff1-d77835066f05
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005415819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.4005415819
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.357361447
Short name T431
Test name
Test status
Simulation time 31043199699 ps
CPU time 102.65 seconds
Started May 16 01:10:16 PM PDT 24
Finished May 16 01:12:09 PM PDT 24
Peak memory 214056 kb
Host smart-3daca55a-346e-420e-bfea-918873a71c3e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357361447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.357361447
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.320750690
Short name T115
Test name
Test status
Simulation time 4035257762 ps
CPU time 27.09 seconds
Started May 16 01:10:27 PM PDT 24
Finished May 16 01:11:06 PM PDT 24
Peak memory 211996 kb
Host smart-b17a348d-a694-48af-9af0-a28027ed5eaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320750690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.320750690
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1927979503
Short name T434
Test name
Test status
Simulation time 39838912065 ps
CPU time 31.29 seconds
Started May 16 01:10:16 PM PDT 24
Finished May 16 01:10:58 PM PDT 24
Peak memory 218620 kb
Host smart-2d1feab8-1e19-4564-9a43-af6873b67948
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927979503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1927979503
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.657372529
Short name T118
Test name
Test status
Simulation time 11903627094 ps
CPU time 94 seconds
Started May 16 01:10:15 PM PDT 24
Finished May 16 01:12:00 PM PDT 24
Peak memory 219128 kb
Host smart-1b21e8e5-6877-4449-bef9-4b0acfca7b27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657372529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.657372529
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2342708337
Short name T371
Test name
Test status
Simulation time 267799123 ps
CPU time 10.06 seconds
Started May 16 01:10:25 PM PDT 24
Finished May 16 01:10:47 PM PDT 24
Peak memory 219120 kb
Host smart-06790c5a-aac4-4711-92a9-ac5a56832258
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342708337 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2342708337
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3715142598
Short name T97
Test name
Test status
Simulation time 4280408555 ps
CPU time 31.77 seconds
Started May 16 01:10:25 PM PDT 24
Finished May 16 01:11:09 PM PDT 24
Peak memory 211136 kb
Host smart-d92c1951-1ac4-45e1-bd31-062353d67bd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715142598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3715142598
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1954917953
Short name T96
Test name
Test status
Simulation time 37157501243 ps
CPU time 168.14 seconds
Started May 16 01:10:27 PM PDT 24
Finished May 16 01:13:28 PM PDT 24
Peak memory 214156 kb
Host smart-3022b15e-5c56-4f95-ba6f-3de6ca71db86
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954917953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1954917953
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.208722215
Short name T424
Test name
Test status
Simulation time 3353632607 ps
CPU time 18.5 seconds
Started May 16 01:10:26 PM PDT 24
Finished May 16 01:10:57 PM PDT 24
Peak memory 211708 kb
Host smart-161b74a8-ec6b-4fe6-8aed-72c942e9808d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208722215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.208722215
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2636582382
Short name T453
Test name
Test status
Simulation time 719012986 ps
CPU time 13.81 seconds
Started May 16 01:10:26 PM PDT 24
Finished May 16 01:10:51 PM PDT 24
Peak memory 216024 kb
Host smart-25432d66-4f61-4993-ac65-cb593ef3edcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636582382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2636582382
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2721246937
Short name T128
Test name
Test status
Simulation time 3838280525 ps
CPU time 102.81 seconds
Started May 16 01:10:26 PM PDT 24
Finished May 16 01:12:20 PM PDT 24
Peak memory 213012 kb
Host smart-84916c98-6640-468f-b406-611752465e55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721246937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2721246937
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3012212983
Short name T55
Test name
Test status
Simulation time 14429531459 ps
CPU time 30.51 seconds
Started May 16 01:10:26 PM PDT 24
Finished May 16 01:11:08 PM PDT 24
Peak memory 219188 kb
Host smart-349b8e4c-3921-4dc8-9269-59f373bc1fbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012212983 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3012212983
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1632840818
Short name T78
Test name
Test status
Simulation time 174396058 ps
CPU time 8.34 seconds
Started May 16 01:10:28 PM PDT 24
Finished May 16 01:10:49 PM PDT 24
Peak memory 210876 kb
Host smart-1cb5aefd-a087-4b26-ac7f-2498c9e2e4d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632840818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1632840818
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1986582661
Short name T95
Test name
Test status
Simulation time 26773761187 ps
CPU time 116.31 seconds
Started May 16 01:10:28 PM PDT 24
Finished May 16 01:12:37 PM PDT 24
Peak memory 213936 kb
Host smart-2377b83f-52cb-4c20-8a0a-329f912c1aad
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986582661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1986582661
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.266023077
Short name T412
Test name
Test status
Simulation time 14078766370 ps
CPU time 30.45 seconds
Started May 16 01:10:25 PM PDT 24
Finished May 16 01:11:07 PM PDT 24
Peak memory 212316 kb
Host smart-aa8c0d2a-5a2a-49e6-bf0c-e66330f9288d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266023077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.266023077
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1482915348
Short name T421
Test name
Test status
Simulation time 3341098026 ps
CPU time 32.04 seconds
Started May 16 01:10:27 PM PDT 24
Finished May 16 01:11:11 PM PDT 24
Peak memory 218412 kb
Host smart-00cfb33c-fc47-4136-9395-95fe73416158
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482915348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1482915348
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2126076677
Short name T414
Test name
Test status
Simulation time 1450274128 ps
CPU time 17.36 seconds
Started May 16 01:10:28 PM PDT 24
Finished May 16 01:10:58 PM PDT 24
Peak memory 219140 kb
Host smart-2c52d2f3-4d0c-44c4-b33c-f176a8255788
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126076677 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2126076677
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2811367558
Short name T393
Test name
Test status
Simulation time 44268277796 ps
CPU time 31.25 seconds
Started May 16 01:10:26 PM PDT 24
Finished May 16 01:11:09 PM PDT 24
Peak memory 212080 kb
Host smart-65ca2f0d-011a-444b-b068-283021a1588a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811367558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2811367558
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.469851123
Short name T80
Test name
Test status
Simulation time 20818797769 ps
CPU time 118.67 seconds
Started May 16 01:10:28 PM PDT 24
Finished May 16 01:12:39 PM PDT 24
Peak memory 213024 kb
Host smart-934011b9-4059-4528-a5e4-51644ba08cd8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469851123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.469851123
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3579098350
Short name T410
Test name
Test status
Simulation time 75546823551 ps
CPU time 30.45 seconds
Started May 16 01:10:28 PM PDT 24
Finished May 16 01:11:11 PM PDT 24
Peak memory 210936 kb
Host smart-febb1d83-9361-45c2-931f-2981a3b4cd8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579098350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3579098350
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2821346745
Short name T383
Test name
Test status
Simulation time 167479970 ps
CPU time 11.29 seconds
Started May 16 01:10:27 PM PDT 24
Finished May 16 01:10:50 PM PDT 24
Peak memory 216696 kb
Host smart-825d7d90-fc1c-48ad-99aa-1e99cc95f06a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821346745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2821346745
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4272846916
Short name T120
Test name
Test status
Simulation time 2227040120 ps
CPU time 153.68 seconds
Started May 16 01:10:27 PM PDT 24
Finished May 16 01:13:13 PM PDT 24
Peak memory 213720 kb
Host smart-6e88eb61-2802-420d-9681-4a537e2118d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272846916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.4272846916
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1575921215
Short name T71
Test name
Test status
Simulation time 4211239289 ps
CPU time 22.33 seconds
Started May 16 01:10:26 PM PDT 24
Finished May 16 01:11:00 PM PDT 24
Peak memory 219116 kb
Host smart-53f90f23-9012-451c-a36f-ce8d60da64db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575921215 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1575921215
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1942797122
Short name T116
Test name
Test status
Simulation time 7049150469 ps
CPU time 28.45 seconds
Started May 16 01:10:25 PM PDT 24
Finished May 16 01:11:05 PM PDT 24
Peak memory 211172 kb
Host smart-6dd40941-c090-4dd2-b4c0-b155f9175f9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942797122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1942797122
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3984106816
Short name T114
Test name
Test status
Simulation time 10452781299 ps
CPU time 22.2 seconds
Started May 16 01:10:29 PM PDT 24
Finished May 16 01:11:03 PM PDT 24
Peak memory 212024 kb
Host smart-7e12641b-b442-4c85-9add-91d4a3a1cf4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984106816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3984106816
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3313307771
Short name T443
Test name
Test status
Simulation time 36962249571 ps
CPU time 32.81 seconds
Started May 16 01:10:28 PM PDT 24
Finished May 16 01:11:13 PM PDT 24
Peak memory 217528 kb
Host smart-c9b5b367-566b-4f64-884c-785d3cd30718
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313307771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3313307771
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.964887665
Short name T65
Test name
Test status
Simulation time 535952371 ps
CPU time 154.04 seconds
Started May 16 01:10:26 PM PDT 24
Finished May 16 01:13:12 PM PDT 24
Peak memory 213712 kb
Host smart-27519128-09e2-479b-b09c-a28453e35a31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964887665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.964887665
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1803205208
Short name T378
Test name
Test status
Simulation time 4488054897 ps
CPU time 15.61 seconds
Started May 16 01:10:36 PM PDT 24
Finished May 16 01:11:05 PM PDT 24
Peak memory 219208 kb
Host smart-c0768d0c-9757-4828-8424-987d953f3b7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803205208 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1803205208
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.641634211
Short name T81
Test name
Test status
Simulation time 688914648 ps
CPU time 8.28 seconds
Started May 16 01:10:40 PM PDT 24
Finished May 16 01:11:02 PM PDT 24
Peak memory 210864 kb
Host smart-733b119a-7cb1-42da-8765-b37df11879dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641634211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.641634211
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1843222421
Short name T92
Test name
Test status
Simulation time 2608358705 ps
CPU time 72.85 seconds
Started May 16 01:10:25 PM PDT 24
Finished May 16 01:11:50 PM PDT 24
Peak memory 214140 kb
Host smart-60c02e91-e583-45ea-9c2d-3bce75854bb4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843222421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1843222421
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2514331746
Short name T112
Test name
Test status
Simulation time 358471043 ps
CPU time 14.69 seconds
Started May 16 01:10:36 PM PDT 24
Finished May 16 01:11:04 PM PDT 24
Peak memory 211852 kb
Host smart-09c589f7-c89b-4fac-8b0f-38aec87182db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514331746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2514331746
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1487542569
Short name T377
Test name
Test status
Simulation time 167479331 ps
CPU time 14.01 seconds
Started May 16 01:10:35 PM PDT 24
Finished May 16 01:11:03 PM PDT 24
Peak memory 217036 kb
Host smart-093c61ce-bed1-49fd-bf49-0a528108f522
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487542569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1487542569
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.495371885
Short name T119
Test name
Test status
Simulation time 327707491 ps
CPU time 153.31 seconds
Started May 16 01:10:36 PM PDT 24
Finished May 16 01:13:23 PM PDT 24
Peak memory 213652 kb
Host smart-b95fc9f7-7813-45e2-a472-c50186ef3f4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495371885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.495371885
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3620915080
Short name T178
Test name
Test status
Simulation time 11025840457 ps
CPU time 25.31 seconds
Started May 16 01:14:13 PM PDT 24
Finished May 16 01:14:40 PM PDT 24
Peak memory 211500 kb
Host smart-892d4e1b-0c41-4220-b225-e166a568b39f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620915080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3620915080
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1667723119
Short name T298
Test name
Test status
Simulation time 8724765379 ps
CPU time 193.97 seconds
Started May 16 01:14:11 PM PDT 24
Finished May 16 01:17:27 PM PDT 24
Peak memory 237920 kb
Host smart-5733d863-3e44-46b0-bd57-c302c7d43e8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667723119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1667723119
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3467218095
Short name T206
Test name
Test status
Simulation time 37767872283 ps
CPU time 70.11 seconds
Started May 16 01:14:16 PM PDT 24
Finished May 16 01:15:27 PM PDT 24
Peak memory 215068 kb
Host smart-4a0e00ec-7351-47c1-bf32-98c7938d569a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467218095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3467218095
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.520116934
Short name T318
Test name
Test status
Simulation time 3504889614 ps
CPU time 10.74 seconds
Started May 16 01:14:11 PM PDT 24
Finished May 16 01:14:24 PM PDT 24
Peak memory 211724 kb
Host smart-8b71132f-edc5-466d-84e1-05d333b8d584
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=520116934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.520116934
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.186832881
Short name T31
Test name
Test status
Simulation time 14836359547 ps
CPU time 141.37 seconds
Started May 16 01:14:17 PM PDT 24
Finished May 16 01:16:40 PM PDT 24
Peak memory 238664 kb
Host smart-01a43a04-585b-4e6e-89f8-0c27889632f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186832881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.186832881
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.4073185818
Short name T274
Test name
Test status
Simulation time 2656398219 ps
CPU time 28.95 seconds
Started May 16 01:14:10 PM PDT 24
Finished May 16 01:14:40 PM PDT 24
Peak memory 217112 kb
Host smart-8a835b5a-f568-468f-bacc-836b57d4c4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073185818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.4073185818
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3653972953
Short name T255
Test name
Test status
Simulation time 14739286281 ps
CPU time 78.64 seconds
Started May 16 01:14:11 PM PDT 24
Finished May 16 01:15:32 PM PDT 24
Peak memory 219336 kb
Host smart-6030f975-cafe-4371-ab78-4c3288caed9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653972953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3653972953
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3008694218
Short name T287
Test name
Test status
Simulation time 339079252 ps
CPU time 8.2 seconds
Started May 16 01:14:28 PM PDT 24
Finished May 16 01:14:39 PM PDT 24
Peak memory 211348 kb
Host smart-a7ae4ec6-aca9-4e2f-99b9-dc02cfcd0720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008694218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3008694218
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3554548891
Short name T313
Test name
Test status
Simulation time 133675812464 ps
CPU time 631.99 seconds
Started May 16 01:14:32 PM PDT 24
Finished May 16 01:25:06 PM PDT 24
Peak memory 217140 kb
Host smart-c8c4a796-535c-4e02-bc55-89af7564bb7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554548891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3554548891
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2129328751
Short name T181
Test name
Test status
Simulation time 7417484275 ps
CPU time 62.99 seconds
Started May 16 01:14:38 PM PDT 24
Finished May 16 01:15:47 PM PDT 24
Peak memory 213104 kb
Host smart-7a8da41f-06e6-4822-905f-cd517c6dc61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129328751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2129328751
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3331690653
Short name T250
Test name
Test status
Simulation time 40850967224 ps
CPU time 24.31 seconds
Started May 16 01:14:29 PM PDT 24
Finished May 16 01:14:56 PM PDT 24
Peak memory 211764 kb
Host smart-597f9729-2389-42b0-9d1d-551940ccd8c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3331690653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3331690653
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3132368393
Short name T36
Test name
Test status
Simulation time 442192991 ps
CPU time 117.6 seconds
Started May 16 01:14:38 PM PDT 24
Finished May 16 01:16:37 PM PDT 24
Peak memory 237660 kb
Host smart-60ef274e-e7f9-4de2-93bb-d58c06804dd7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132368393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3132368393
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1140573214
Short name T140
Test name
Test status
Simulation time 36428909845 ps
CPU time 69.97 seconds
Started May 16 01:14:11 PM PDT 24
Finished May 16 01:15:23 PM PDT 24
Peak memory 216964 kb
Host smart-87d37e62-78ef-422e-8e75-814f5ad6daaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140573214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1140573214
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1018847692
Short name T172
Test name
Test status
Simulation time 1038955603 ps
CPU time 18.86 seconds
Started May 16 01:14:31 PM PDT 24
Finished May 16 01:14:53 PM PDT 24
Peak memory 213428 kb
Host smart-3badf680-3540-4b9a-82d9-50447cf29d0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018847692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1018847692
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1803138197
Short name T230
Test name
Test status
Simulation time 58538527809 ps
CPU time 335.33 seconds
Started May 16 01:14:57 PM PDT 24
Finished May 16 01:20:36 PM PDT 24
Peak memory 239920 kb
Host smart-cdba5d74-fd53-4089-8719-277a09df5e64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803138197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1803138197
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.282387486
Short name T134
Test name
Test status
Simulation time 182440193 ps
CPU time 10.34 seconds
Started May 16 01:14:56 PM PDT 24
Finished May 16 01:15:10 PM PDT 24
Peak memory 212336 kb
Host smart-032325db-54db-4e39-aedc-6e58e6d83aab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=282387486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.282387486
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1362924866
Short name T68
Test name
Test status
Simulation time 4621295933 ps
CPU time 60.21 seconds
Started May 16 01:14:59 PM PDT 24
Finished May 16 01:16:04 PM PDT 24
Peak memory 217208 kb
Host smart-62597f55-aed5-438f-830a-758e69b742b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362924866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1362924866
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.310755703
Short name T297
Test name
Test status
Simulation time 20428472850 ps
CPU time 35.05 seconds
Started May 16 01:15:08 PM PDT 24
Finished May 16 01:15:44 PM PDT 24
Peak memory 212272 kb
Host smart-97d73b2c-07da-47d8-8892-3c72b0d0847e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310755703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.310755703
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1840908480
Short name T301
Test name
Test status
Simulation time 161711799130 ps
CPU time 407.47 seconds
Started May 16 01:15:04 PM PDT 24
Finished May 16 01:21:53 PM PDT 24
Peak memory 229360 kb
Host smart-5c2f5fcd-f44a-4a9c-af8e-eec14601fdad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840908480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1840908480
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1342385283
Short name T155
Test name
Test status
Simulation time 332695318 ps
CPU time 19.56 seconds
Started May 16 01:15:01 PM PDT 24
Finished May 16 01:15:24 PM PDT 24
Peak memory 214832 kb
Host smart-476de071-034a-4e89-ac0e-3544ca7e11e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342385283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1342385283
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2422919840
Short name T61
Test name
Test status
Simulation time 3303668425 ps
CPU time 16.63 seconds
Started May 16 01:15:01 PM PDT 24
Finished May 16 01:15:21 PM PDT 24
Peak memory 211744 kb
Host smart-519e22e1-f74a-44ac-a72a-7bf4f234c6aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2422919840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2422919840
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.682275067
Short name T262
Test name
Test status
Simulation time 18323567868 ps
CPU time 46.02 seconds
Started May 16 01:14:59 PM PDT 24
Finished May 16 01:15:49 PM PDT 24
Peak memory 215752 kb
Host smart-e4015ac9-eca8-4dc6-ae8c-06b50e434c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682275067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.682275067
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2465077859
Short name T270
Test name
Test status
Simulation time 7076243279 ps
CPU time 49.78 seconds
Started May 16 01:15:05 PM PDT 24
Finished May 16 01:15:57 PM PDT 24
Peak memory 219460 kb
Host smart-988c6612-1f2a-481b-a80b-43cf5648da96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465077859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2465077859
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.528456990
Short name T72
Test name
Test status
Simulation time 5126903093 ps
CPU time 16.7 seconds
Started May 16 01:15:09 PM PDT 24
Finished May 16 01:15:27 PM PDT 24
Peak memory 212344 kb
Host smart-22b6b1a4-27eb-4b0d-993d-249571f1a70b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528456990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.528456990
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.896095048
Short name T290
Test name
Test status
Simulation time 6826879482 ps
CPU time 58.35 seconds
Started May 16 01:15:07 PM PDT 24
Finished May 16 01:16:06 PM PDT 24
Peak memory 213924 kb
Host smart-77b593d0-c5b9-4372-8e69-9792089b3785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896095048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.896095048
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1552370535
Short name T2
Test name
Test status
Simulation time 3606071785 ps
CPU time 19.66 seconds
Started May 16 01:15:05 PM PDT 24
Finished May 16 01:15:27 PM PDT 24
Peak memory 211424 kb
Host smart-cbc4db4c-4a55-42a8-9e52-c80b3c9ac047
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1552370535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1552370535
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.14736119
Short name T305
Test name
Test status
Simulation time 8375895590 ps
CPU time 67.8 seconds
Started May 16 01:14:59 PM PDT 24
Finished May 16 01:16:11 PM PDT 24
Peak memory 218192 kb
Host smart-561e0da0-cea8-44c4-932e-6bedd1e91a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14736119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.14736119
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.4285999033
Short name T312
Test name
Test status
Simulation time 17218167688 ps
CPU time 129.43 seconds
Started May 16 01:15:00 PM PDT 24
Finished May 16 01:17:13 PM PDT 24
Peak memory 220576 kb
Host smart-ee3c7496-3ddb-4201-9e77-2f16a06255c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285999033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.4285999033
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.923537946
Short name T236
Test name
Test status
Simulation time 13279403809 ps
CPU time 19.14 seconds
Started May 16 01:14:59 PM PDT 24
Finished May 16 01:15:22 PM PDT 24
Peak memory 212328 kb
Host smart-0393ee37-2e01-4a4e-92e6-b2fbd26690c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923537946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.923537946
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2057361291
Short name T18
Test name
Test status
Simulation time 59300315097 ps
CPU time 610.15 seconds
Started May 16 01:15:11 PM PDT 24
Finished May 16 01:25:23 PM PDT 24
Peak memory 217060 kb
Host smart-2cb9fb08-a96c-4338-bb04-22b40e4bc841
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057361291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2057361291
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.843523485
Short name T275
Test name
Test status
Simulation time 404813836 ps
CPU time 19.21 seconds
Started May 16 01:15:06 PM PDT 24
Finished May 16 01:15:26 PM PDT 24
Peak memory 214676 kb
Host smart-180088b3-49fe-4ab1-a9a4-b81085955208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843523485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.843523485
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2230292790
Short name T136
Test name
Test status
Simulation time 374715509 ps
CPU time 10.51 seconds
Started May 16 01:15:05 PM PDT 24
Finished May 16 01:15:18 PM PDT 24
Peak memory 212124 kb
Host smart-fbcba833-bfde-4970-b67f-b341170ade57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2230292790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2230292790
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.186150874
Short name T40
Test name
Test status
Simulation time 3955675264 ps
CPU time 35.26 seconds
Started May 16 01:15:01 PM PDT 24
Finished May 16 01:15:40 PM PDT 24
Peak memory 215924 kb
Host smart-0aca5a47-560a-4d64-8427-de3720263dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186150874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.186150874
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1243766094
Short name T310
Test name
Test status
Simulation time 11029589117 ps
CPU time 105.51 seconds
Started May 16 01:15:02 PM PDT 24
Finished May 16 01:16:50 PM PDT 24
Peak memory 219388 kb
Host smart-75f022d9-5581-4230-949f-265792edb259
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243766094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1243766094
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2975294569
Short name T341
Test name
Test status
Simulation time 1204165154 ps
CPU time 15.85 seconds
Started May 16 01:15:09 PM PDT 24
Finished May 16 01:15:26 PM PDT 24
Peak memory 211344 kb
Host smart-f3f5221b-b20e-4370-906e-f2db5f6bbc27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975294569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2975294569
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1336333979
Short name T220
Test name
Test status
Simulation time 336048345 ps
CPU time 19.45 seconds
Started May 16 01:15:11 PM PDT 24
Finished May 16 01:15:31 PM PDT 24
Peak memory 215252 kb
Host smart-9c32c17b-71fb-4a2e-a1d2-357f393f3712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336333979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1336333979
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.733911119
Short name T303
Test name
Test status
Simulation time 358544053 ps
CPU time 10.55 seconds
Started May 16 01:15:05 PM PDT 24
Finished May 16 01:15:18 PM PDT 24
Peak memory 211588 kb
Host smart-2c494952-54e5-45f0-9085-b7b779b3fa4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=733911119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.733911119
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.4119405635
Short name T154
Test name
Test status
Simulation time 6528885416 ps
CPU time 70.96 seconds
Started May 16 01:15:08 PM PDT 24
Finished May 16 01:16:21 PM PDT 24
Peak memory 217388 kb
Host smart-a39b8fa4-ea59-4dce-9ab7-8cf72882ebea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119405635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.4119405635
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2725768242
Short name T144
Test name
Test status
Simulation time 4946495376 ps
CPU time 58.84 seconds
Started May 16 01:14:59 PM PDT 24
Finished May 16 01:16:02 PM PDT 24
Peak memory 220912 kb
Host smart-8b2cb9f7-a42f-42c9-8024-6babcceba7d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725768242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2725768242
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3843294602
Short name T227
Test name
Test status
Simulation time 36154267388 ps
CPU time 21.36 seconds
Started May 16 01:15:10 PM PDT 24
Finished May 16 01:15:33 PM PDT 24
Peak memory 212392 kb
Host smart-bdc3c0f7-c3e7-47d5-b289-21c2ebbbd835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843294602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3843294602
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2305195131
Short name T309
Test name
Test status
Simulation time 14717731654 ps
CPU time 222.35 seconds
Started May 16 01:15:13 PM PDT 24
Finished May 16 01:18:57 PM PDT 24
Peak memory 217868 kb
Host smart-b256d107-548a-4535-8510-608eec6eef23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305195131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2305195131
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1230249291
Short name T339
Test name
Test status
Simulation time 689831728 ps
CPU time 19.25 seconds
Started May 16 01:15:14 PM PDT 24
Finished May 16 01:15:35 PM PDT 24
Peak memory 214772 kb
Host smart-9ae83cf2-3ca3-4ffc-b95b-3a9b88d36df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230249291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1230249291
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3968377011
Short name T196
Test name
Test status
Simulation time 16736162415 ps
CPU time 114.42 seconds
Started May 16 01:15:09 PM PDT 24
Finished May 16 01:17:05 PM PDT 24
Peak memory 219392 kb
Host smart-2e10c97e-4c08-4442-866b-2991655a5cdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968377011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3968377011
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2760609253
Short name T159
Test name
Test status
Simulation time 167603094 ps
CPU time 8.58 seconds
Started May 16 01:15:12 PM PDT 24
Finished May 16 01:15:22 PM PDT 24
Peak memory 211296 kb
Host smart-3145e8ac-7e52-4744-b175-35f0ce6fa3f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760609253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2760609253
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3169923351
Short name T168
Test name
Test status
Simulation time 12778233883 ps
CPU time 243.06 seconds
Started May 16 01:15:08 PM PDT 24
Finished May 16 01:19:13 PM PDT 24
Peak memory 240180 kb
Host smart-8e6c63f7-4113-4d33-ac4f-b060c26d95fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169923351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3169923351
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3530273437
Short name T20
Test name
Test status
Simulation time 17938613978 ps
CPU time 43.41 seconds
Started May 16 01:15:10 PM PDT 24
Finished May 16 01:15:54 PM PDT 24
Peak memory 215160 kb
Host smart-5a0078a0-dca9-4e3a-8fd2-df73d23ad8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530273437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3530273437
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3164254453
Short name T229
Test name
Test status
Simulation time 72610753617 ps
CPU time 32.48 seconds
Started May 16 01:15:13 PM PDT 24
Finished May 16 01:15:48 PM PDT 24
Peak memory 211888 kb
Host smart-c62cc2d8-b366-4dab-93ee-3cea8ccee6f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3164254453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3164254453
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.4182951223
Short name T299
Test name
Test status
Simulation time 40030017361 ps
CPU time 67.61 seconds
Started May 16 01:15:10 PM PDT 24
Finished May 16 01:16:19 PM PDT 24
Peak memory 217860 kb
Host smart-55561441-3d72-4482-adc8-37fe50ab2203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182951223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.4182951223
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1739935084
Short name T302
Test name
Test status
Simulation time 36005458134 ps
CPU time 79.42 seconds
Started May 16 01:15:10 PM PDT 24
Finished May 16 01:16:31 PM PDT 24
Peak memory 219424 kb
Host smart-39a32a14-4bed-4f07-809e-8da4afb7ffee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739935084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1739935084
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3388942530
Short name T223
Test name
Test status
Simulation time 1791902983 ps
CPU time 19.89 seconds
Started May 16 01:15:24 PM PDT 24
Finished May 16 01:15:46 PM PDT 24
Peak memory 211856 kb
Host smart-f1ed74b2-9167-4a4f-902c-b7c50e3a0fe0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388942530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3388942530
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3699695704
Short name T50
Test name
Test status
Simulation time 2010551198 ps
CPU time 139.6 seconds
Started May 16 01:15:10 PM PDT 24
Finished May 16 01:17:31 PM PDT 24
Peak memory 218648 kb
Host smart-dfb53bc0-8100-4a93-9318-f04a570b9f54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699695704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3699695704
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2540142436
Short name T169
Test name
Test status
Simulation time 35211201801 ps
CPU time 50.14 seconds
Started May 16 01:15:11 PM PDT 24
Finished May 16 01:16:02 PM PDT 24
Peak memory 216088 kb
Host smart-37bd9b55-cff1-462e-933c-519516ddbcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540142436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2540142436
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1288794504
Short name T316
Test name
Test status
Simulation time 791606036 ps
CPU time 14.9 seconds
Started May 16 01:15:12 PM PDT 24
Finished May 16 01:15:28 PM PDT 24
Peak memory 212200 kb
Host smart-750bafa6-4a22-4684-9a25-cdd9cf65547d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1288794504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1288794504
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3464536046
Short name T306
Test name
Test status
Simulation time 2978863801 ps
CPU time 39.07 seconds
Started May 16 01:15:13 PM PDT 24
Finished May 16 01:15:54 PM PDT 24
Peak memory 215884 kb
Host smart-fdcb6452-c907-46d8-af3f-c0dd63a807fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464536046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3464536046
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2749558693
Short name T361
Test name
Test status
Simulation time 2386578374 ps
CPU time 19.65 seconds
Started May 16 01:15:10 PM PDT 24
Finished May 16 01:15:31 PM PDT 24
Peak memory 212508 kb
Host smart-2b68f7ab-b63e-4468-b95a-0abd5e90f1f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749558693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2749558693
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1682869531
Short name T74
Test name
Test status
Simulation time 661179250 ps
CPU time 8.28 seconds
Started May 16 01:15:29 PM PDT 24
Finished May 16 01:15:39 PM PDT 24
Peak memory 211204 kb
Host smart-9e356cdf-9ea4-4ec5-bba1-096e25215e7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682869531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1682869531
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3438593254
Short name T38
Test name
Test status
Simulation time 105050981916 ps
CPU time 391.77 seconds
Started May 16 01:15:19 PM PDT 24
Finished May 16 01:21:52 PM PDT 24
Peak memory 236896 kb
Host smart-85b04d2d-e6cf-49ae-a2ca-2c89df2c02de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438593254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3438593254
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.690511125
Short name T21
Test name
Test status
Simulation time 854350883 ps
CPU time 26.03 seconds
Started May 16 01:15:30 PM PDT 24
Finished May 16 01:15:58 PM PDT 24
Peak memory 214744 kb
Host smart-2247db43-c19b-4fb4-b3e2-f82b2e184938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690511125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.690511125
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1585811723
Short name T60
Test name
Test status
Simulation time 11561946397 ps
CPU time 25.58 seconds
Started May 16 01:15:21 PM PDT 24
Finished May 16 01:15:47 PM PDT 24
Peak memory 211312 kb
Host smart-25995c93-148a-4e95-932c-18a868a90a6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1585811723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1585811723
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.4149268724
Short name T269
Test name
Test status
Simulation time 16435836639 ps
CPU time 46.19 seconds
Started May 16 01:15:27 PM PDT 24
Finished May 16 01:16:16 PM PDT 24
Peak memory 217636 kb
Host smart-0c248cee-e132-4f61-af7a-618758f2d2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149268724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.4149268724
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2302866100
Short name T288
Test name
Test status
Simulation time 21053344122 ps
CPU time 101.29 seconds
Started May 16 01:15:25 PM PDT 24
Finished May 16 01:17:08 PM PDT 24
Peak memory 219356 kb
Host smart-5369248f-d16c-408c-a9e4-2ebd1748062a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302866100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2302866100
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.749661030
Short name T291
Test name
Test status
Simulation time 946061489 ps
CPU time 14.34 seconds
Started May 16 01:15:30 PM PDT 24
Finished May 16 01:15:46 PM PDT 24
Peak memory 211908 kb
Host smart-c0cc9eb7-a2be-4336-951f-4d9acc33a9a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749661030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.749661030
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1439410403
Short name T69
Test name
Test status
Simulation time 150686649626 ps
CPU time 351.11 seconds
Started May 16 01:15:28 PM PDT 24
Finished May 16 01:21:21 PM PDT 24
Peak memory 216728 kb
Host smart-31725dfe-fa22-4ff4-af30-c4b8fa64f76a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439410403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1439410403
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1282767439
Short name T57
Test name
Test status
Simulation time 11062172152 ps
CPU time 53.12 seconds
Started May 16 01:15:33 PM PDT 24
Finished May 16 01:16:28 PM PDT 24
Peak memory 214104 kb
Host smart-3f1612e2-5d10-4371-80ca-22503c365c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282767439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1282767439
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3371044850
Short name T238
Test name
Test status
Simulation time 6677642602 ps
CPU time 29.73 seconds
Started May 16 01:15:34 PM PDT 24
Finished May 16 01:16:06 PM PDT 24
Peak memory 212652 kb
Host smart-f0198d2c-acba-4c4d-a1d2-41d4074bac2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3371044850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3371044850
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3732965674
Short name T324
Test name
Test status
Simulation time 1428213311 ps
CPU time 20.47 seconds
Started May 16 01:15:30 PM PDT 24
Finished May 16 01:15:53 PM PDT 24
Peak memory 216712 kb
Host smart-ae41c263-04df-4595-957b-974187987a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732965674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3732965674
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3508994743
Short name T326
Test name
Test status
Simulation time 6934167883 ps
CPU time 30.08 seconds
Started May 16 01:15:34 PM PDT 24
Finished May 16 01:16:06 PM PDT 24
Peak memory 211636 kb
Host smart-391edf58-ba39-441a-9c53-261080e5686c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508994743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3508994743
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3567465114
Short name T332
Test name
Test status
Simulation time 4923457967 ps
CPU time 16.31 seconds
Started May 16 01:14:37 PM PDT 24
Finished May 16 01:14:55 PM PDT 24
Peak memory 212448 kb
Host smart-2b1a0968-dffa-42eb-81f4-12f5ff0ea649
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567465114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3567465114
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1849442090
Short name T353
Test name
Test status
Simulation time 8233711433 ps
CPU time 274.42 seconds
Started May 16 01:14:31 PM PDT 24
Finished May 16 01:19:08 PM PDT 24
Peak memory 234480 kb
Host smart-e721ed17-1002-40ad-bddc-b8fa20166d04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849442090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1849442090
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3164567592
Short name T245
Test name
Test status
Simulation time 9995989110 ps
CPU time 67.66 seconds
Started May 16 01:14:34 PM PDT 24
Finished May 16 01:15:43 PM PDT 24
Peak memory 215128 kb
Host smart-0f2f499a-ccc4-4b4f-8137-7576605a845a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164567592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3164567592
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3410592954
Short name T257
Test name
Test status
Simulation time 9093729798 ps
CPU time 35.7 seconds
Started May 16 01:14:37 PM PDT 24
Finished May 16 01:15:14 PM PDT 24
Peak memory 212584 kb
Host smart-92ceeea3-ced5-4f81-bad2-685df019536e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3410592954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3410592954
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2795244940
Short name T265
Test name
Test status
Simulation time 3922497745 ps
CPU time 35.59 seconds
Started May 16 01:14:39 PM PDT 24
Finished May 16 01:15:16 PM PDT 24
Peak memory 218784 kb
Host smart-baa11812-9d5c-4c03-9644-6b2b6e55c572
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795244940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2795244940
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3271719165
Short name T203
Test name
Test status
Simulation time 38551335280 ps
CPU time 32.4 seconds
Started May 16 01:15:36 PM PDT 24
Finished May 16 01:16:10 PM PDT 24
Peak memory 212356 kb
Host smart-ff21de8f-93fa-492c-9ebb-b95d40a45bfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271719165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3271719165
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3626811273
Short name T261
Test name
Test status
Simulation time 32078808295 ps
CPU time 386.23 seconds
Started May 16 01:15:27 PM PDT 24
Finished May 16 01:21:55 PM PDT 24
Peak memory 237048 kb
Host smart-32c58149-a250-4388-bab5-f29bc7a7943e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626811273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3626811273
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2125429067
Short name T350
Test name
Test status
Simulation time 1026981717 ps
CPU time 26.56 seconds
Started May 16 01:15:35 PM PDT 24
Finished May 16 01:16:04 PM PDT 24
Peak memory 212516 kb
Host smart-7f8a8ead-1e75-42da-a0bb-3c195865d07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125429067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2125429067
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3391021896
Short name T259
Test name
Test status
Simulation time 3987702607 ps
CPU time 22.66 seconds
Started May 16 01:15:35 PM PDT 24
Finished May 16 01:16:00 PM PDT 24
Peak memory 211320 kb
Host smart-d994a9ac-e325-43e3-a55d-5f98a4a3bf23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3391021896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3391021896
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2391787924
Short name T242
Test name
Test status
Simulation time 696198040 ps
CPU time 19.55 seconds
Started May 16 01:15:34 PM PDT 24
Finished May 16 01:15:56 PM PDT 24
Peak memory 217360 kb
Host smart-17949412-d83a-4236-922d-18b26bc37c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391787924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2391787924
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.911414432
Short name T228
Test name
Test status
Simulation time 33855491013 ps
CPU time 58.39 seconds
Started May 16 01:15:30 PM PDT 24
Finished May 16 01:16:30 PM PDT 24
Peak memory 218272 kb
Host smart-763d2a3c-cb50-46dd-9cff-c3532f4541e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911414432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.911414432
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1288338566
Short name T211
Test name
Test status
Simulation time 41118267965 ps
CPU time 29.95 seconds
Started May 16 01:15:35 PM PDT 24
Finished May 16 01:16:07 PM PDT 24
Peak memory 212284 kb
Host smart-fac77d83-d18e-4eea-a364-42ec0e08e0bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288338566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1288338566
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.522094824
Short name T192
Test name
Test status
Simulation time 167900192455 ps
CPU time 573.44 seconds
Started May 16 01:15:29 PM PDT 24
Finished May 16 01:25:04 PM PDT 24
Peak memory 237876 kb
Host smart-4e905881-ef78-4d85-9ec5-b6117762b301
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522094824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.522094824
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3011278999
Short name T325
Test name
Test status
Simulation time 7375044560 ps
CPU time 63.57 seconds
Started May 16 01:15:32 PM PDT 24
Finished May 16 01:16:37 PM PDT 24
Peak memory 215440 kb
Host smart-f757938c-16e9-4286-b523-2de3b1d7a923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011278999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3011278999
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1162042548
Short name T315
Test name
Test status
Simulation time 21449009390 ps
CPU time 34.14 seconds
Started May 16 01:15:37 PM PDT 24
Finished May 16 01:16:13 PM PDT 24
Peak memory 211836 kb
Host smart-3d2b1ce5-6aa2-4689-8096-16a16b6cc214
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1162042548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1162042548
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3213690933
Short name T70
Test name
Test status
Simulation time 11818636701 ps
CPU time 62.68 seconds
Started May 16 01:15:34 PM PDT 24
Finished May 16 01:16:39 PM PDT 24
Peak memory 214128 kb
Host smart-f8a6b18e-661e-4d57-b08e-390439cb6777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213690933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3213690933
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1347113631
Short name T307
Test name
Test status
Simulation time 915599596 ps
CPU time 31.61 seconds
Started May 16 01:15:34 PM PDT 24
Finished May 16 01:16:08 PM PDT 24
Peak memory 218600 kb
Host smart-900ca9d0-67cd-44db-84f1-77f0f5811987
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347113631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1347113631
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2179302557
Short name T346
Test name
Test status
Simulation time 983670536 ps
CPU time 12.04 seconds
Started May 16 01:15:47 PM PDT 24
Finished May 16 01:16:00 PM PDT 24
Peak memory 211384 kb
Host smart-6a89d8ba-a9f0-47f7-9aad-2c210d5c1ff0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179302557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2179302557
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.966805829
Short name T173
Test name
Test status
Simulation time 19049154520 ps
CPU time 140.44 seconds
Started May 16 01:15:29 PM PDT 24
Finished May 16 01:17:51 PM PDT 24
Peak memory 216144 kb
Host smart-5aebad54-5cd6-4a92-8cbb-aa9f69e93a53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966805829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.966805829
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.606756988
Short name T185
Test name
Test status
Simulation time 30627073419 ps
CPU time 67.42 seconds
Started May 16 01:15:32 PM PDT 24
Finished May 16 01:16:41 PM PDT 24
Peak memory 215072 kb
Host smart-7561d24c-1089-4cd5-83a6-9d78b5e46f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606756988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.606756988
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2703852746
Short name T231
Test name
Test status
Simulation time 7343121556 ps
CPU time 31.97 seconds
Started May 16 01:15:36 PM PDT 24
Finished May 16 01:16:10 PM PDT 24
Peak memory 212516 kb
Host smart-4b4f0360-10a7-4b7b-9ec9-d96a9cb97593
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2703852746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2703852746
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2470687597
Short name T1
Test name
Test status
Simulation time 22262508999 ps
CPU time 54.48 seconds
Started May 16 01:15:34 PM PDT 24
Finished May 16 01:16:31 PM PDT 24
Peak memory 217336 kb
Host smart-e6061fa4-7f5b-4693-983d-1f01ecb7abe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470687597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2470687597
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.946835396
Short name T218
Test name
Test status
Simulation time 3589747990 ps
CPU time 26.02 seconds
Started May 16 01:15:39 PM PDT 24
Finished May 16 01:16:06 PM PDT 24
Peak memory 218552 kb
Host smart-20ed03ba-f91f-4b1f-a3a9-aaafae860a08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946835396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.946835396
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2697949132
Short name T360
Test name
Test status
Simulation time 751586033 ps
CPU time 8.52 seconds
Started May 16 01:15:47 PM PDT 24
Finished May 16 01:15:56 PM PDT 24
Peak memory 211472 kb
Host smart-ad44e649-2fa8-42b6-9961-47e502cb588b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697949132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2697949132
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2508731919
Short name T64
Test name
Test status
Simulation time 258718114754 ps
CPU time 294.57 seconds
Started May 16 01:15:48 PM PDT 24
Finished May 16 01:20:43 PM PDT 24
Peak memory 237640 kb
Host smart-a0aea831-6705-4838-ae11-3f03581e90be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508731919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2508731919
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2972922318
Short name T253
Test name
Test status
Simulation time 31368720893 ps
CPU time 64.1 seconds
Started May 16 01:15:51 PM PDT 24
Finished May 16 01:16:56 PM PDT 24
Peak memory 215112 kb
Host smart-644bddad-5394-441c-8f75-cc954f71e8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972922318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2972922318
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.902858381
Short name T222
Test name
Test status
Simulation time 1096094809 ps
CPU time 13.4 seconds
Started May 16 01:15:48 PM PDT 24
Finished May 16 01:16:02 PM PDT 24
Peak memory 211240 kb
Host smart-c28c1bce-370a-427b-bef8-0920c49bb7d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=902858381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.902858381
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.534651343
Short name T165
Test name
Test status
Simulation time 2923123959 ps
CPU time 41.74 seconds
Started May 16 01:15:47 PM PDT 24
Finished May 16 01:16:30 PM PDT 24
Peak memory 215976 kb
Host smart-6c205e4e-f9bc-4d38-b206-d582c1321dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534651343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.534651343
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2176318496
Short name T146
Test name
Test status
Simulation time 2944479434 ps
CPU time 28.92 seconds
Started May 16 01:15:48 PM PDT 24
Finished May 16 01:16:18 PM PDT 24
Peak memory 212216 kb
Host smart-787df273-b11e-4f6c-af6b-e57f6427fd24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176318496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2176318496
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.4218232105
Short name T215
Test name
Test status
Simulation time 6679707115 ps
CPU time 18.21 seconds
Started May 16 01:16:00 PM PDT 24
Finished May 16 01:16:20 PM PDT 24
Peak memory 211496 kb
Host smart-3eed2f2f-c162-476f-8f02-977fc77a7ee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218232105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.4218232105
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3757352395
Short name T355
Test name
Test status
Simulation time 5283828429 ps
CPU time 201.5 seconds
Started May 16 01:16:01 PM PDT 24
Finished May 16 01:19:24 PM PDT 24
Peak memory 234100 kb
Host smart-e49b3121-3572-4c86-8740-1f4bdc6040ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757352395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3757352395
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1725719771
Short name T240
Test name
Test status
Simulation time 16029839051 ps
CPU time 69.1 seconds
Started May 16 01:16:02 PM PDT 24
Finished May 16 01:17:13 PM PDT 24
Peak memory 215108 kb
Host smart-793b24a2-2228-4a24-b171-20e3fccaa8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725719771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1725719771
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.4048167663
Short name T187
Test name
Test status
Simulation time 10866717517 ps
CPU time 26.57 seconds
Started May 16 01:15:51 PM PDT 24
Finished May 16 01:16:18 PM PDT 24
Peak memory 211868 kb
Host smart-bd596aa6-c38d-4713-b030-5bcaf73f41c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4048167663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.4048167663
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1490749624
Short name T156
Test name
Test status
Simulation time 2210359729 ps
CPU time 26.9 seconds
Started May 16 01:15:46 PM PDT 24
Finished May 16 01:16:14 PM PDT 24
Peak memory 215852 kb
Host smart-b5e2315d-f4a6-4b99-9599-945b11dfe9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490749624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1490749624
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2163575040
Short name T235
Test name
Test status
Simulation time 115388941112 ps
CPU time 105.48 seconds
Started May 16 01:15:46 PM PDT 24
Finished May 16 01:17:32 PM PDT 24
Peak memory 220284 kb
Host smart-c11630f3-13a1-49bb-b859-73267ea6493e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163575040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2163575040
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.245795157
Short name T224
Test name
Test status
Simulation time 661812404 ps
CPU time 8.16 seconds
Started May 16 01:15:59 PM PDT 24
Finished May 16 01:16:09 PM PDT 24
Peak memory 211360 kb
Host smart-91f76088-3a13-4642-b371-c5d59e312524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245795157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.245795157
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.4240122493
Short name T62
Test name
Test status
Simulation time 77013585399 ps
CPU time 667.63 seconds
Started May 16 01:16:03 PM PDT 24
Finished May 16 01:27:12 PM PDT 24
Peak memory 224840 kb
Host smart-348f7fb6-9a25-4e97-84f6-798ee333574e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240122493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.4240122493
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3577222951
Short name T328
Test name
Test status
Simulation time 6569040574 ps
CPU time 41.12 seconds
Started May 16 01:15:58 PM PDT 24
Finished May 16 01:16:41 PM PDT 24
Peak memory 215352 kb
Host smart-0540b3ad-1c64-44d6-bc0c-9322559ac72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577222951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3577222951
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3398041508
Short name T88
Test name
Test status
Simulation time 1416687282 ps
CPU time 20.36 seconds
Started May 16 01:15:58 PM PDT 24
Finished May 16 01:16:20 PM PDT 24
Peak memory 218048 kb
Host smart-a95993ae-3c83-4af3-a64c-c71b5df79965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398041508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3398041508
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1037689072
Short name T214
Test name
Test status
Simulation time 9380276616 ps
CPU time 35 seconds
Started May 16 01:16:00 PM PDT 24
Finished May 16 01:16:37 PM PDT 24
Peak memory 213244 kb
Host smart-a1a3932a-58bd-41a5-a554-54f6ce8f55d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037689072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1037689072
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.4294002479
Short name T342
Test name
Test status
Simulation time 2699689301 ps
CPU time 23.46 seconds
Started May 16 01:15:57 PM PDT 24
Finished May 16 01:16:22 PM PDT 24
Peak memory 212076 kb
Host smart-ad88e5e8-59a7-4a8a-bce6-69d2ad01b0ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294002479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.4294002479
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.207971507
Short name T336
Test name
Test status
Simulation time 40401884081 ps
CPU time 553.74 seconds
Started May 16 01:16:03 PM PDT 24
Finished May 16 01:25:19 PM PDT 24
Peak memory 224724 kb
Host smart-cb84c62e-dde5-49c0-bf1a-6f4f6609c358
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207971507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.207971507
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2089311565
Short name T277
Test name
Test status
Simulation time 34305427098 ps
CPU time 70.35 seconds
Started May 16 01:15:59 PM PDT 24
Finished May 16 01:17:11 PM PDT 24
Peak memory 213164 kb
Host smart-4017a4f2-e67b-45cd-8b80-024b5917de44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089311565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2089311565
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.100053176
Short name T327
Test name
Test status
Simulation time 524905112 ps
CPU time 14.85 seconds
Started May 16 01:15:57 PM PDT 24
Finished May 16 01:16:13 PM PDT 24
Peak memory 212256 kb
Host smart-daf11cc6-28ce-48e3-be76-9a890bd3e08a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100053176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.100053176
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2287070059
Short name T201
Test name
Test status
Simulation time 6018798437 ps
CPU time 55.17 seconds
Started May 16 01:16:01 PM PDT 24
Finished May 16 01:16:58 PM PDT 24
Peak memory 217308 kb
Host smart-ff5d4570-0440-400f-8120-aa0497da2db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287070059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2287070059
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2717123177
Short name T273
Test name
Test status
Simulation time 238721759805 ps
CPU time 150.66 seconds
Started May 16 01:16:00 PM PDT 24
Finished May 16 01:18:32 PM PDT 24
Peak memory 229400 kb
Host smart-ea169243-c866-404d-8e1f-0dc37d6ce67d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717123177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2717123177
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1646145454
Short name T27
Test name
Test status
Simulation time 11257683002 ps
CPU time 455.68 seconds
Started May 16 01:16:00 PM PDT 24
Finished May 16 01:23:38 PM PDT 24
Peak memory 235948 kb
Host smart-ff1fb6a2-2484-4ab9-b025-c9fe129f093c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646145454 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1646145454
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.134814452
Short name T34
Test name
Test status
Simulation time 16671542942 ps
CPU time 33.05 seconds
Started May 16 01:16:01 PM PDT 24
Finished May 16 01:16:36 PM PDT 24
Peak memory 212136 kb
Host smart-b7aea141-6309-4a2a-8911-6b0c4822003f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134814452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.134814452
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.644780606
Short name T295
Test name
Test status
Simulation time 369280946859 ps
CPU time 767.37 seconds
Started May 16 01:16:00 PM PDT 24
Finished May 16 01:28:49 PM PDT 24
Peak memory 233908 kb
Host smart-c694dcb2-9066-4d39-b748-a64d13eaf577
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644780606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.644780606
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3590311907
Short name T197
Test name
Test status
Simulation time 6524325408 ps
CPU time 57.21 seconds
Started May 16 01:16:03 PM PDT 24
Finished May 16 01:17:02 PM PDT 24
Peak memory 214956 kb
Host smart-8d126e4c-005f-408c-a8ac-b955aeeba4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590311907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3590311907
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1788472508
Short name T199
Test name
Test status
Simulation time 363917387 ps
CPU time 10.43 seconds
Started May 16 01:16:01 PM PDT 24
Finished May 16 01:16:14 PM PDT 24
Peak memory 211440 kb
Host smart-9ecd6872-4a62-4c7e-8c54-65052b5b223d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1788472508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1788472508
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3272183039
Short name T207
Test name
Test status
Simulation time 7190760038 ps
CPU time 77.97 seconds
Started May 16 01:16:02 PM PDT 24
Finished May 16 01:17:21 PM PDT 24
Peak memory 216748 kb
Host smart-b6d95654-3191-436a-a2f6-ac534b42d373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272183039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3272183039
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1033142870
Short name T317
Test name
Test status
Simulation time 5706436687 ps
CPU time 68.73 seconds
Started May 16 01:16:01 PM PDT 24
Finished May 16 01:17:12 PM PDT 24
Peak memory 220496 kb
Host smart-d1eb1fbb-86cb-4e03-b712-c231a0df1e30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033142870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1033142870
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.386534461
Short name T343
Test name
Test status
Simulation time 2059859430 ps
CPU time 8.18 seconds
Started May 16 01:16:08 PM PDT 24
Finished May 16 01:16:18 PM PDT 24
Peak memory 211348 kb
Host smart-12296ebf-bb22-412a-b9f5-c75ce239409e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386534461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.386534461
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2905204071
Short name T176
Test name
Test status
Simulation time 32034011434 ps
CPU time 235.67 seconds
Started May 16 01:16:08 PM PDT 24
Finished May 16 01:20:06 PM PDT 24
Peak memory 217212 kb
Host smart-27c7a3e1-dc1e-44ac-a3fd-72bd767608f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905204071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2905204071
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.4069270451
Short name T184
Test name
Test status
Simulation time 2537319861 ps
CPU time 18.94 seconds
Started May 16 01:16:07 PM PDT 24
Finished May 16 01:16:28 PM PDT 24
Peak memory 214888 kb
Host smart-3eac2cdd-df2d-4d37-818d-05850e2f68bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069270451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.4069270451
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2969996720
Short name T331
Test name
Test status
Simulation time 737875268 ps
CPU time 10.77 seconds
Started May 16 01:15:57 PM PDT 24
Finished May 16 01:16:09 PM PDT 24
Peak memory 212424 kb
Host smart-18a79853-8a41-41ae-8f36-35ea5e5820fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2969996720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2969996720
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.75945839
Short name T89
Test name
Test status
Simulation time 4285369481 ps
CPU time 20.61 seconds
Started May 16 01:16:00 PM PDT 24
Finished May 16 01:16:23 PM PDT 24
Peak memory 217968 kb
Host smart-5855e25e-1014-456f-8c40-aba5b3eaa6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75945839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.75945839
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.949933092
Short name T171
Test name
Test status
Simulation time 4356162702 ps
CPU time 69.72 seconds
Started May 16 01:15:57 PM PDT 24
Finished May 16 01:17:09 PM PDT 24
Peak memory 219496 kb
Host smart-8b67abf8-a62d-426f-916b-148a2d99ef19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949933092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.949933092
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.45033922
Short name T260
Test name
Test status
Simulation time 10903537734 ps
CPU time 24.68 seconds
Started May 16 01:16:07 PM PDT 24
Finished May 16 01:16:33 PM PDT 24
Peak memory 211408 kb
Host smart-52d60f8d-163f-415d-8641-a6f73bba39f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45033922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.45033922
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3201142599
Short name T247
Test name
Test status
Simulation time 14689417507 ps
CPU time 250.37 seconds
Started May 16 01:16:12 PM PDT 24
Finished May 16 01:20:25 PM PDT 24
Peak memory 236092 kb
Host smart-3b8783a1-8f6d-475f-8c78-ddf048e90557
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201142599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3201142599
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1610488966
Short name T347
Test name
Test status
Simulation time 8053848196 ps
CPU time 66.84 seconds
Started May 16 01:16:08 PM PDT 24
Finished May 16 01:17:18 PM PDT 24
Peak memory 213896 kb
Host smart-2e6eb487-e3d1-4931-a987-1bfad7533789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610488966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1610488966
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2668456182
Short name T133
Test name
Test status
Simulation time 1214228010 ps
CPU time 18.94 seconds
Started May 16 01:16:08 PM PDT 24
Finished May 16 01:16:29 PM PDT 24
Peak memory 211180 kb
Host smart-abf9e8ca-3ed0-4ece-ac8e-3d0fdd2371c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2668456182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2668456182
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.531519040
Short name T91
Test name
Test status
Simulation time 12985127197 ps
CPU time 66.46 seconds
Started May 16 01:16:11 PM PDT 24
Finished May 16 01:17:20 PM PDT 24
Peak memory 216832 kb
Host smart-d82cdeba-1325-4dc5-9c5e-a81e7dd91289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531519040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.531519040
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2997743861
Short name T266
Test name
Test status
Simulation time 2807742048 ps
CPU time 44.49 seconds
Started May 16 01:16:11 PM PDT 24
Finished May 16 01:16:59 PM PDT 24
Peak memory 219456 kb
Host smart-5f7fa9bd-1943-4cac-8806-d2c52392ea05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997743861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2997743861
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.4167755564
Short name T51
Test name
Test status
Simulation time 30668376852 ps
CPU time 1206.06 seconds
Started May 16 01:16:08 PM PDT 24
Finished May 16 01:36:17 PM PDT 24
Peak memory 231948 kb
Host smart-f53a8b95-6d4e-4203-acba-80f6e921ce9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167755564 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.4167755564
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1862827176
Short name T161
Test name
Test status
Simulation time 6648469194 ps
CPU time 33.84 seconds
Started May 16 01:14:36 PM PDT 24
Finished May 16 01:15:12 PM PDT 24
Peak memory 211512 kb
Host smart-3658f150-4a4f-4215-b68d-397dd1e035d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862827176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1862827176
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3020614239
Short name T237
Test name
Test status
Simulation time 392130506485 ps
CPU time 892.43 seconds
Started May 16 01:14:36 PM PDT 24
Finished May 16 01:29:29 PM PDT 24
Peak memory 219572 kb
Host smart-24e43fdc-3551-4f25-8701-a9c93737b4e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020614239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3020614239
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.498447379
Short name T209
Test name
Test status
Simulation time 6219241114 ps
CPU time 58 seconds
Started May 16 01:14:47 PM PDT 24
Finished May 16 01:15:46 PM PDT 24
Peak memory 215248 kb
Host smart-a8704c3f-71d8-4f87-824c-3ee1c9777754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498447379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.498447379
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2782616243
Short name T188
Test name
Test status
Simulation time 2940573294 ps
CPU time 28.33 seconds
Started May 16 01:14:43 PM PDT 24
Finished May 16 01:15:13 PM PDT 24
Peak memory 212516 kb
Host smart-1955c4f2-3eff-454f-aaec-89da6ae76b70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2782616243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2782616243
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3368508455
Short name T33
Test name
Test status
Simulation time 19538285998 ps
CPU time 135.69 seconds
Started May 16 01:14:43 PM PDT 24
Finished May 16 01:17:00 PM PDT 24
Peak memory 239716 kb
Host smart-6ea63d68-5208-4f9e-9c70-1c4e11e9ad24
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368508455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3368508455
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3319690874
Short name T56
Test name
Test status
Simulation time 23310887829 ps
CPU time 50.84 seconds
Started May 16 01:14:42 PM PDT 24
Finished May 16 01:15:34 PM PDT 24
Peak memory 217272 kb
Host smart-c88a3456-c343-4fbc-be80-90df1454ac46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319690874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3319690874
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.253944545
Short name T338
Test name
Test status
Simulation time 59043441586 ps
CPU time 138.82 seconds
Started May 16 01:14:38 PM PDT 24
Finished May 16 01:16:59 PM PDT 24
Peak memory 219544 kb
Host smart-b5e77cc6-ad6d-425a-abd2-61fe6951b554
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253944545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.253944545
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2055130174
Short name T241
Test name
Test status
Simulation time 16663310171 ps
CPU time 31.44 seconds
Started May 16 01:16:11 PM PDT 24
Finished May 16 01:16:45 PM PDT 24
Peak memory 212232 kb
Host smart-8760acbd-5a81-47cf-a674-8624ee1fb602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055130174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2055130174
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2149110707
Short name T167
Test name
Test status
Simulation time 88302820451 ps
CPU time 410.55 seconds
Started May 16 01:16:10 PM PDT 24
Finished May 16 01:23:03 PM PDT 24
Peak memory 217760 kb
Host smart-99f41f22-600f-466e-a096-b7093252fd5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149110707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2149110707
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2548004129
Short name T357
Test name
Test status
Simulation time 22383162225 ps
CPU time 53.88 seconds
Started May 16 01:16:13 PM PDT 24
Finished May 16 01:17:09 PM PDT 24
Peak memory 214988 kb
Host smart-f01d7b12-76f6-4018-86b7-80ae056d0478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548004129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2548004129
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2195181700
Short name T243
Test name
Test status
Simulation time 602608352 ps
CPU time 14.16 seconds
Started May 16 01:16:16 PM PDT 24
Finished May 16 01:16:32 PM PDT 24
Peak memory 212148 kb
Host smart-e987dc8d-1b08-4174-87d4-61e9899d3da3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2195181700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2195181700
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.322823561
Short name T147
Test name
Test status
Simulation time 358569702 ps
CPU time 20.58 seconds
Started May 16 01:16:10 PM PDT 24
Finished May 16 01:16:33 PM PDT 24
Peak memory 215700 kb
Host smart-962dda28-8f02-47b5-ba71-1f832b4469d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322823561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.322823561
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.556534382
Short name T53
Test name
Test status
Simulation time 83201369324 ps
CPU time 1587.86 seconds
Started May 16 01:16:09 PM PDT 24
Finished May 16 01:42:39 PM PDT 24
Peak memory 239756 kb
Host smart-8fea4e39-0f32-4733-86b9-8453cea62f04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556534382 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.556534382
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.842796253
Short name T216
Test name
Test status
Simulation time 178255412 ps
CPU time 8.59 seconds
Started May 16 01:16:11 PM PDT 24
Finished May 16 01:16:23 PM PDT 24
Peak memory 211424 kb
Host smart-46edec2a-66a6-4dd9-88fb-15a0a7ecc022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842796253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.842796253
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.300960050
Short name T46
Test name
Test status
Simulation time 108792539416 ps
CPU time 406.77 seconds
Started May 16 01:16:09 PM PDT 24
Finished May 16 01:22:58 PM PDT 24
Peak memory 240004 kb
Host smart-a0d815bf-b16c-4450-872c-1a3f139e30ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300960050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.300960050
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.755777810
Short name T286
Test name
Test status
Simulation time 14629112838 ps
CPU time 63.33 seconds
Started May 16 01:16:09 PM PDT 24
Finished May 16 01:17:15 PM PDT 24
Peak memory 215036 kb
Host smart-532ebcc8-5acf-4de4-82e6-30df1091d0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755777810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.755777810
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4032420775
Short name T109
Test name
Test status
Simulation time 8501071448 ps
CPU time 34.37 seconds
Started May 16 01:16:05 PM PDT 24
Finished May 16 01:16:41 PM PDT 24
Peak memory 211772 kb
Host smart-13fb6891-177e-4ee9-a695-7c4a77e368cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4032420775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4032420775
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.4019749184
Short name T249
Test name
Test status
Simulation time 5716688637 ps
CPU time 54.55 seconds
Started May 16 01:16:08 PM PDT 24
Finished May 16 01:17:05 PM PDT 24
Peak memory 217228 kb
Host smart-dee9292d-d055-46a4-879e-735fd5feef58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019749184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.4019749184
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2236210853
Short name T296
Test name
Test status
Simulation time 95067895654 ps
CPU time 240.46 seconds
Started May 16 01:16:09 PM PDT 24
Finished May 16 01:20:12 PM PDT 24
Peak memory 220452 kb
Host smart-3bf0ed2c-f68d-4840-9edc-78a6cf48ab89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236210853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2236210853
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1975534185
Short name T73
Test name
Test status
Simulation time 8904054172 ps
CPU time 22.33 seconds
Started May 16 01:16:09 PM PDT 24
Finished May 16 01:16:35 PM PDT 24
Peak memory 211480 kb
Host smart-9507273a-7be1-4890-82c0-deda8cc70a2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975534185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1975534185
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1865189760
Short name T179
Test name
Test status
Simulation time 119947005780 ps
CPU time 616.6 seconds
Started May 16 01:16:09 PM PDT 24
Finished May 16 01:26:28 PM PDT 24
Peak memory 226268 kb
Host smart-d497e0aa-bf01-4b55-b47f-c29d587713a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865189760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1865189760
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.704921077
Short name T349
Test name
Test status
Simulation time 689274681 ps
CPU time 18.91 seconds
Started May 16 01:16:12 PM PDT 24
Finished May 16 01:16:33 PM PDT 24
Peak memory 214808 kb
Host smart-3cd6ec4d-d74d-4ecf-b895-44fc064fa51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704921077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.704921077
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.16551376
Short name T5
Test name
Test status
Simulation time 1688478081 ps
CPU time 15.85 seconds
Started May 16 01:16:11 PM PDT 24
Finished May 16 01:16:30 PM PDT 24
Peak memory 211420 kb
Host smart-2fbf8179-71a6-4996-bfee-b6063e43d77c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16551376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.16551376
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3124609933
Short name T90
Test name
Test status
Simulation time 17206522101 ps
CPU time 47.28 seconds
Started May 16 01:16:08 PM PDT 24
Finished May 16 01:16:57 PM PDT 24
Peak memory 217624 kb
Host smart-4b6e468e-9bb0-4dcd-be97-0053b5137546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124609933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3124609933
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.137634209
Short name T158
Test name
Test status
Simulation time 648522952 ps
CPU time 22.61 seconds
Started May 16 01:16:11 PM PDT 24
Finished May 16 01:16:37 PM PDT 24
Peak memory 217852 kb
Host smart-b8260e00-9ae9-44f5-861a-87cf4dbc6ef9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137634209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.137634209
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3490834459
Short name T42
Test name
Test status
Simulation time 2542610411 ps
CPU time 23.89 seconds
Started May 16 01:16:10 PM PDT 24
Finished May 16 01:16:37 PM PDT 24
Peak memory 211460 kb
Host smart-beaa3f70-aebd-4388-8eeb-3d0919fb37eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490834459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3490834459
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.128988752
Short name T17
Test name
Test status
Simulation time 1321054490 ps
CPU time 19.08 seconds
Started May 16 01:16:08 PM PDT 24
Finished May 16 01:16:30 PM PDT 24
Peak memory 214704 kb
Host smart-26257271-c2b2-4440-897f-5306945cd62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128988752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.128988752
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2405579672
Short name T217
Test name
Test status
Simulation time 3657627853 ps
CPU time 15.94 seconds
Started May 16 01:16:10 PM PDT 24
Finished May 16 01:16:29 PM PDT 24
Peak memory 212696 kb
Host smart-06ca231d-a1f9-4a6f-9da1-152e14fc73a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2405579672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2405579672
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3904328624
Short name T148
Test name
Test status
Simulation time 1159472595 ps
CPU time 29.81 seconds
Started May 16 01:16:11 PM PDT 24
Finished May 16 01:16:44 PM PDT 24
Peak memory 215808 kb
Host smart-9b8bbd5e-9fd1-4bbb-905e-9bd2cd2da73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904328624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3904328624
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1214685866
Short name T58
Test name
Test status
Simulation time 3505918633 ps
CPU time 29.83 seconds
Started May 16 01:16:20 PM PDT 24
Finished May 16 01:16:53 PM PDT 24
Peak memory 211984 kb
Host smart-ee950f1a-02d8-46f1-a963-c93a745bee4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214685866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1214685866
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1718402931
Short name T321
Test name
Test status
Simulation time 105240857709 ps
CPU time 516.86 seconds
Started May 16 01:16:17 PM PDT 24
Finished May 16 01:24:56 PM PDT 24
Peak memory 228980 kb
Host smart-61fb19ac-b2cf-477d-81ba-87666996c816
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718402931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1718402931
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3121553227
Short name T22
Test name
Test status
Simulation time 29560433186 ps
CPU time 63.21 seconds
Started May 16 01:16:24 PM PDT 24
Finished May 16 01:17:29 PM PDT 24
Peak memory 214136 kb
Host smart-84c30def-7768-409f-8b7f-2557d417d4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121553227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3121553227
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2888856983
Short name T300
Test name
Test status
Simulation time 3850271521 ps
CPU time 18.33 seconds
Started May 16 01:16:12 PM PDT 24
Finished May 16 01:16:33 PM PDT 24
Peak memory 211600 kb
Host smart-02877ecf-1e91-4e5a-b5d1-903c572f27ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2888856983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2888856983
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3512732171
Short name T157
Test name
Test status
Simulation time 1354725327 ps
CPU time 19.1 seconds
Started May 16 01:16:09 PM PDT 24
Finished May 16 01:16:31 PM PDT 24
Peak memory 215636 kb
Host smart-ebbdc2cb-c466-4ab3-8dbb-b07f209af1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512732171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3512732171
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2735792363
Short name T281
Test name
Test status
Simulation time 1470392256 ps
CPU time 25.83 seconds
Started May 16 01:16:09 PM PDT 24
Finished May 16 01:16:37 PM PDT 24
Peak memory 211492 kb
Host smart-d5cbb42e-1688-4457-973a-d0288c2edc04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735792363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2735792363
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.37860375
Short name T35
Test name
Test status
Simulation time 2269849888 ps
CPU time 21.88 seconds
Started May 16 01:16:16 PM PDT 24
Finished May 16 01:16:40 PM PDT 24
Peak memory 211988 kb
Host smart-cdaecf03-4533-4a59-b818-a1df9141b69a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37860375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.37860375
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1118207988
Short name T194
Test name
Test status
Simulation time 67479848779 ps
CPU time 479.37 seconds
Started May 16 01:16:18 PM PDT 24
Finished May 16 01:24:20 PM PDT 24
Peak memory 216744 kb
Host smart-f014472c-6be4-43b1-94e6-e6c8121428a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118207988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1118207988
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3723958718
Short name T348
Test name
Test status
Simulation time 40006055534 ps
CPU time 57.95 seconds
Started May 16 01:16:19 PM PDT 24
Finished May 16 01:17:19 PM PDT 24
Peak memory 214376 kb
Host smart-38e6834c-6e91-4da5-b51e-5972a50796aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723958718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3723958718
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3297441507
Short name T256
Test name
Test status
Simulation time 2511249373 ps
CPU time 23.9 seconds
Started May 16 01:16:18 PM PDT 24
Finished May 16 01:16:44 PM PDT 24
Peak memory 212448 kb
Host smart-7cc02edd-16b4-475d-a160-b5536c02c2bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3297441507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3297441507
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.115615223
Short name T152
Test name
Test status
Simulation time 3891361834 ps
CPU time 43.52 seconds
Started May 16 01:16:17 PM PDT 24
Finished May 16 01:17:02 PM PDT 24
Peak memory 217300 kb
Host smart-1f591c75-0190-4214-86bd-06d4bc25388e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115615223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.115615223
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3181670857
Short name T323
Test name
Test status
Simulation time 26935028932 ps
CPU time 82.05 seconds
Started May 16 01:16:17 PM PDT 24
Finished May 16 01:17:41 PM PDT 24
Peak memory 216212 kb
Host smart-8a2ef33e-dbb2-44c6-8fa9-6b5e0f59b95f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181670857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3181670857
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.665798772
Short name T183
Test name
Test status
Simulation time 167772735 ps
CPU time 8.23 seconds
Started May 16 01:16:17 PM PDT 24
Finished May 16 01:16:27 PM PDT 24
Peak memory 211368 kb
Host smart-330c5f7d-8196-4c23-a378-295dcc52addd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665798772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.665798772
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1459881409
Short name T272
Test name
Test status
Simulation time 88902015305 ps
CPU time 849.1 seconds
Started May 16 01:16:21 PM PDT 24
Finished May 16 01:30:33 PM PDT 24
Peak memory 225496 kb
Host smart-93259c4e-e460-4b49-b3dd-b9b15a871229
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459881409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1459881409
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.494812102
Short name T314
Test name
Test status
Simulation time 7265435003 ps
CPU time 27.93 seconds
Started May 16 01:16:19 PM PDT 24
Finished May 16 01:16:49 PM PDT 24
Peak memory 213708 kb
Host smart-fb528a8e-72f1-442b-8046-6a0e9bd48d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494812102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.494812102
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.590288493
Short name T177
Test name
Test status
Simulation time 539690708 ps
CPU time 20.73 seconds
Started May 16 01:16:19 PM PDT 24
Finished May 16 01:16:42 PM PDT 24
Peak memory 216424 kb
Host smart-16ccd1c0-9c46-4539-b020-cb036a0e2c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590288493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.590288493
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2648182836
Short name T145
Test name
Test status
Simulation time 5091204468 ps
CPU time 73.45 seconds
Started May 16 01:16:20 PM PDT 24
Finished May 16 01:17:35 PM PDT 24
Peak memory 218980 kb
Host smart-16466136-1dd5-43c3-9afc-79978d69906e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648182836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2648182836
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1372157104
Short name T28
Test name
Test status
Simulation time 86961886613 ps
CPU time 3384.02 seconds
Started May 16 01:16:17 PM PDT 24
Finished May 16 02:12:44 PM PDT 24
Peak memory 252276 kb
Host smart-a9cd5613-dd56-48d8-a777-d7d04e0b8f3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372157104 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.1372157104
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1095219970
Short name T76
Test name
Test status
Simulation time 662225211 ps
CPU time 8.67 seconds
Started May 16 01:16:19 PM PDT 24
Finished May 16 01:16:29 PM PDT 24
Peak memory 211332 kb
Host smart-3d1e69d0-e775-4631-be11-754f25130852
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095219970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1095219970
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.788712036
Short name T49
Test name
Test status
Simulation time 474313784983 ps
CPU time 505.45 seconds
Started May 16 01:16:20 PM PDT 24
Finished May 16 01:24:48 PM PDT 24
Peak memory 240944 kb
Host smart-3d46782c-d2d2-4e42-b2a2-cdd18a7b8c59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788712036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.788712036
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2170204428
Short name T278
Test name
Test status
Simulation time 16403388402 ps
CPU time 44.31 seconds
Started May 16 01:16:16 PM PDT 24
Finished May 16 01:17:02 PM PDT 24
Peak memory 214112 kb
Host smart-c764afb1-baa6-484e-bdc0-6b61d516fe18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170204428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2170204428
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1076220764
Short name T354
Test name
Test status
Simulation time 6597925526 ps
CPU time 20.6 seconds
Started May 16 01:16:20 PM PDT 24
Finished May 16 01:16:43 PM PDT 24
Peak memory 211864 kb
Host smart-199dfc85-8028-44f3-bf0a-853cee1a74f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1076220764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1076220764
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3059723436
Short name T41
Test name
Test status
Simulation time 5759575640 ps
CPU time 67.59 seconds
Started May 16 01:16:18 PM PDT 24
Finished May 16 01:17:28 PM PDT 24
Peak memory 218196 kb
Host smart-0d19eb22-1328-46ac-88a9-d136b5f75a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059723436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3059723436
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1942679585
Short name T225
Test name
Test status
Simulation time 33670679773 ps
CPU time 95 seconds
Started May 16 01:16:18 PM PDT 24
Finished May 16 01:17:55 PM PDT 24
Peak memory 220768 kb
Host smart-3de5ea9c-3612-46c5-b999-956ce9223227
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942679585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1942679585
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2371331557
Short name T75
Test name
Test status
Simulation time 6129986731 ps
CPU time 17.82 seconds
Started May 16 01:16:22 PM PDT 24
Finished May 16 01:16:42 PM PDT 24
Peak memory 211388 kb
Host smart-2b8cae3e-e751-4356-85bd-112c4d281d8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371331557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2371331557
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3780753126
Short name T180
Test name
Test status
Simulation time 22067341881 ps
CPU time 215.31 seconds
Started May 16 01:16:18 PM PDT 24
Finished May 16 01:19:55 PM PDT 24
Peak memory 229816 kb
Host smart-f3bbcb1a-6fc7-4cb5-bd9a-48936be7c6c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780753126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3780753126
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2098317251
Short name T263
Test name
Test status
Simulation time 12648381793 ps
CPU time 60.97 seconds
Started May 16 01:16:20 PM PDT 24
Finished May 16 01:17:23 PM PDT 24
Peak memory 215180 kb
Host smart-16132625-11be-4db1-9d34-2f4e4cfe5ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098317251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2098317251
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3647292273
Short name T356
Test name
Test status
Simulation time 18494642474 ps
CPU time 31.27 seconds
Started May 16 01:16:21 PM PDT 24
Finished May 16 01:16:55 PM PDT 24
Peak memory 211788 kb
Host smart-c7b5e60c-6ee5-4e64-8a46-5e5b629e0250
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3647292273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3647292273
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3030494246
Short name T139
Test name
Test status
Simulation time 9298693179 ps
CPU time 71.68 seconds
Started May 16 01:16:20 PM PDT 24
Finished May 16 01:17:34 PM PDT 24
Peak memory 217028 kb
Host smart-c53313c3-268c-471d-ad87-e50aff2ace83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030494246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3030494246
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.262423467
Short name T135
Test name
Test status
Simulation time 30259058479 ps
CPU time 90.57 seconds
Started May 16 01:16:19 PM PDT 24
Finished May 16 01:17:52 PM PDT 24
Peak memory 221172 kb
Host smart-95cac417-7969-4904-b451-65b246dbb6ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262423467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.262423467
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2115616853
Short name T280
Test name
Test status
Simulation time 867927142 ps
CPU time 8.3 seconds
Started May 16 01:16:21 PM PDT 24
Finished May 16 01:16:32 PM PDT 24
Peak memory 211388 kb
Host smart-92c6723b-27ee-4043-8acb-2836b2ef0791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115616853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2115616853
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1101788649
Short name T335
Test name
Test status
Simulation time 4570122463 ps
CPU time 347.93 seconds
Started May 16 01:16:21 PM PDT 24
Finished May 16 01:22:11 PM PDT 24
Peak memory 239128 kb
Host smart-5151c736-8c8b-450a-aa5e-93f00ef931b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101788649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1101788649
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.220361418
Short name T252
Test name
Test status
Simulation time 8234848655 ps
CPU time 32.66 seconds
Started May 16 01:16:23 PM PDT 24
Finished May 16 01:16:58 PM PDT 24
Peak memory 215388 kb
Host smart-3b7f5113-ccdf-48c1-85ba-da912d4065a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220361418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.220361418
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.352956425
Short name T191
Test name
Test status
Simulation time 2110322298 ps
CPU time 22.83 seconds
Started May 16 01:16:18 PM PDT 24
Finished May 16 01:16:43 PM PDT 24
Peak memory 211184 kb
Host smart-5762a00a-9f45-4669-946b-09aa7ed9437f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=352956425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.352956425
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1498411306
Short name T284
Test name
Test status
Simulation time 1373072971 ps
CPU time 19.95 seconds
Started May 16 01:16:21 PM PDT 24
Finished May 16 01:16:44 PM PDT 24
Peak memory 216756 kb
Host smart-725d3388-cbc5-4714-89fb-ae33e260c25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498411306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1498411306
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.129369363
Short name T141
Test name
Test status
Simulation time 33427121704 ps
CPU time 160.41 seconds
Started May 16 01:16:23 PM PDT 24
Finished May 16 01:19:05 PM PDT 24
Peak memory 219280 kb
Host smart-b7d0a8dc-08c7-45a0-9899-1338724934ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129369363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.129369363
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3819927862
Short name T330
Test name
Test status
Simulation time 1500040006 ps
CPU time 8.5 seconds
Started May 16 01:14:38 PM PDT 24
Finished May 16 01:14:48 PM PDT 24
Peak memory 211388 kb
Host smart-50572164-20cf-433d-bab6-29a92c3e1675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819927862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3819927862
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2429729810
Short name T48
Test name
Test status
Simulation time 13669195846 ps
CPU time 231.84 seconds
Started May 16 01:14:42 PM PDT 24
Finished May 16 01:18:36 PM PDT 24
Peak memory 237936 kb
Host smart-ebd157ec-bb91-4568-97d6-9ce3f6efda5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429729810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2429729810
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1246650726
Short name T248
Test name
Test status
Simulation time 23638060393 ps
CPU time 57.16 seconds
Started May 16 01:14:37 PM PDT 24
Finished May 16 01:15:36 PM PDT 24
Peak memory 214048 kb
Host smart-e65a0045-875b-4fdb-ae93-7959086e28b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246650726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1246650726
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3548395885
Short name T344
Test name
Test status
Simulation time 5466617902 ps
CPU time 19.12 seconds
Started May 16 01:14:46 PM PDT 24
Finished May 16 01:15:06 PM PDT 24
Peak memory 212808 kb
Host smart-0e108ed1-8729-406a-bc3a-295220071ba6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3548395885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3548395885
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1698595512
Short name T37
Test name
Test status
Simulation time 34067054123 ps
CPU time 245.81 seconds
Started May 16 01:14:42 PM PDT 24
Finished May 16 01:18:50 PM PDT 24
Peak memory 238428 kb
Host smart-0fdb19ea-7701-4a3c-b73f-ea559eea7196
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698595512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1698595512
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3615316032
Short name T142
Test name
Test status
Simulation time 13076132935 ps
CPU time 62.85 seconds
Started May 16 01:14:40 PM PDT 24
Finished May 16 01:15:45 PM PDT 24
Peak memory 217772 kb
Host smart-28ec1ac1-d868-4baa-8e82-e68652d48cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615316032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3615316032
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1805221290
Short name T244
Test name
Test status
Simulation time 5809010479 ps
CPU time 27.76 seconds
Started May 16 01:14:52 PM PDT 24
Finished May 16 01:15:22 PM PDT 24
Peak memory 214000 kb
Host smart-32222943-a49d-4032-9988-8dba5097a9ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805221290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1805221290
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3390033795
Short name T345
Test name
Test status
Simulation time 2464986137 ps
CPU time 22.61 seconds
Started May 16 01:16:16 PM PDT 24
Finished May 16 01:16:40 PM PDT 24
Peak memory 211476 kb
Host smart-f40295da-7a37-4541-b54f-86e445ad79cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390033795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3390033795
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.619664677
Short name T195
Test name
Test status
Simulation time 30036400624 ps
CPU time 295.32 seconds
Started May 16 01:16:23 PM PDT 24
Finished May 16 01:21:21 PM PDT 24
Peak memory 240068 kb
Host smart-4642c0b4-a723-4ab3-b7d6-883ff5767561
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619664677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.619664677
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2529463177
Short name T16
Test name
Test status
Simulation time 3001395237 ps
CPU time 19.05 seconds
Started May 16 01:16:21 PM PDT 24
Finished May 16 01:16:43 PM PDT 24
Peak memory 215012 kb
Host smart-e8ff6592-8205-489e-b2fc-dbcc3f9a6fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529463177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2529463177
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3217894697
Short name T14
Test name
Test status
Simulation time 3559030513 ps
CPU time 30.58 seconds
Started May 16 01:16:21 PM PDT 24
Finished May 16 01:16:54 PM PDT 24
Peak memory 212272 kb
Host smart-531d7ea6-ec20-4f7f-9d76-3ba08995a1bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3217894697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3217894697
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3708734616
Short name T160
Test name
Test status
Simulation time 5366415680 ps
CPU time 58.38 seconds
Started May 16 01:16:22 PM PDT 24
Finished May 16 01:17:23 PM PDT 24
Peak memory 215892 kb
Host smart-c2d00fab-e4fd-415e-a2bc-5fbcd082e303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708734616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3708734616
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2122042945
Short name T283
Test name
Test status
Simulation time 11908124773 ps
CPU time 35.35 seconds
Started May 16 01:16:23 PM PDT 24
Finished May 16 01:17:01 PM PDT 24
Peak memory 214140 kb
Host smart-91e28f62-083a-4e9c-874a-cd5c8a2fc41a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122042945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2122042945
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.224278044
Short name T233
Test name
Test status
Simulation time 172832545 ps
CPU time 8.43 seconds
Started May 16 01:16:21 PM PDT 24
Finished May 16 01:16:32 PM PDT 24
Peak memory 211472 kb
Host smart-91f6f20c-db55-4e15-bdff-2ff5dc088422
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224278044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.224278044
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2290007486
Short name T251
Test name
Test status
Simulation time 490997647118 ps
CPU time 733.21 seconds
Started May 16 01:16:21 PM PDT 24
Finished May 16 01:28:36 PM PDT 24
Peak memory 234636 kb
Host smart-4f49d60f-8d85-406c-a5d9-79c255cb6648
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290007486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2290007486
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2366740564
Short name T63
Test name
Test status
Simulation time 8352054997 ps
CPU time 67.04 seconds
Started May 16 01:16:20 PM PDT 24
Finished May 16 01:17:30 PM PDT 24
Peak memory 215348 kb
Host smart-da92f0f2-b1fd-44c4-8ea2-5b99a647c0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366740564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2366740564
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3642085355
Short name T351
Test name
Test status
Simulation time 5697260657 ps
CPU time 26.73 seconds
Started May 16 01:16:26 PM PDT 24
Finished May 16 01:16:56 PM PDT 24
Peak memory 212552 kb
Host smart-274c7deb-e9f5-4b54-9c47-d94d28b015f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3642085355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3642085355
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1501528666
Short name T276
Test name
Test status
Simulation time 687687028 ps
CPU time 20.4 seconds
Started May 16 01:16:19 PM PDT 24
Finished May 16 01:16:42 PM PDT 24
Peak memory 216312 kb
Host smart-f6a3f51a-36ce-46f4-9365-198c9eb4c2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501528666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1501528666
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.769555719
Short name T311
Test name
Test status
Simulation time 1028669656 ps
CPU time 33.61 seconds
Started May 16 01:16:22 PM PDT 24
Finished May 16 01:16:58 PM PDT 24
Peak memory 215344 kb
Host smart-7791f879-2b84-4c84-9453-1ea56f823a71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769555719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.769555719
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2203750949
Short name T175
Test name
Test status
Simulation time 7743866140 ps
CPU time 24.56 seconds
Started May 16 01:16:26 PM PDT 24
Finished May 16 01:16:53 PM PDT 24
Peak memory 211508 kb
Host smart-4e3b1606-ce9c-459d-bc9b-09279c6df4f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203750949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2203750949
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.797742620
Short name T24
Test name
Test status
Simulation time 15345179309 ps
CPU time 276.46 seconds
Started May 16 01:16:29 PM PDT 24
Finished May 16 01:21:09 PM PDT 24
Peak memory 248824 kb
Host smart-be4c354e-8c34-4b92-afbc-c9660d44e279
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797742620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.797742620
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.809210923
Short name T219
Test name
Test status
Simulation time 9708872496 ps
CPU time 38.03 seconds
Started May 16 01:16:27 PM PDT 24
Finished May 16 01:17:08 PM PDT 24
Peak memory 215072 kb
Host smart-2363537f-60c8-4bc1-9ebb-1b8e6e4682bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809210923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.809210923
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1352829036
Short name T232
Test name
Test status
Simulation time 187426216 ps
CPU time 10.39 seconds
Started May 16 01:16:30 PM PDT 24
Finished May 16 01:16:44 PM PDT 24
Peak memory 212404 kb
Host smart-f42ca24f-003b-4669-9160-c58d3f7ed3f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1352829036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1352829036
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.407484546
Short name T204
Test name
Test status
Simulation time 684955016 ps
CPU time 20.03 seconds
Started May 16 01:16:26 PM PDT 24
Finished May 16 01:16:49 PM PDT 24
Peak memory 216044 kb
Host smart-446d9820-cb23-4061-b7ef-a4b0080b46c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407484546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.407484546
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1454256748
Short name T254
Test name
Test status
Simulation time 53470302478 ps
CPU time 116.87 seconds
Started May 16 01:16:28 PM PDT 24
Finished May 16 01:18:27 PM PDT 24
Peak memory 219488 kb
Host smart-3b494c86-79ee-41f1-9760-974656322464
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454256748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1454256748
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.4109830930
Short name T363
Test name
Test status
Simulation time 172482926 ps
CPU time 8.42 seconds
Started May 16 01:16:27 PM PDT 24
Finished May 16 01:16:37 PM PDT 24
Peak memory 211388 kb
Host smart-b7f77e02-a741-43e7-9511-0253f51e0a0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109830930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.4109830930
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4136319958
Short name T25
Test name
Test status
Simulation time 104887043830 ps
CPU time 989.22 seconds
Started May 16 01:16:26 PM PDT 24
Finished May 16 01:32:57 PM PDT 24
Peak memory 224800 kb
Host smart-3ab6b393-d030-4a17-8807-5b39c2a13b59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136319958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.4136319958
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2051887725
Short name T279
Test name
Test status
Simulation time 332617913 ps
CPU time 19.34 seconds
Started May 16 01:16:32 PM PDT 24
Finished May 16 01:16:54 PM PDT 24
Peak memory 214072 kb
Host smart-b6d64b77-b2da-40bc-8e27-d2cc150aca3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051887725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2051887725
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.783758072
Short name T292
Test name
Test status
Simulation time 592622489 ps
CPU time 15.03 seconds
Started May 16 01:16:28 PM PDT 24
Finished May 16 01:16:46 PM PDT 24
Peak memory 211292 kb
Host smart-5579218d-44e9-4811-9189-6554b72cd327
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=783758072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.783758072
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.866588594
Short name T246
Test name
Test status
Simulation time 38618569025 ps
CPU time 38.14 seconds
Started May 16 01:16:30 PM PDT 24
Finished May 16 01:17:11 PM PDT 24
Peak memory 218372 kb
Host smart-d8328943-1a0b-4237-bdc7-b4871cf83645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866588594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.866588594
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.898141490
Short name T170
Test name
Test status
Simulation time 7812469515 ps
CPU time 90.77 seconds
Started May 16 01:16:27 PM PDT 24
Finished May 16 01:18:01 PM PDT 24
Peak memory 219880 kb
Host smart-52de461f-4ec0-4fff-931b-16c85e533ebc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898141490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.898141490
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3164306123
Short name T221
Test name
Test status
Simulation time 3891853711 ps
CPU time 30.7 seconds
Started May 16 01:16:32 PM PDT 24
Finished May 16 01:17:05 PM PDT 24
Peak memory 212048 kb
Host smart-4bfe34c7-16a2-4db0-9292-85f0fe299095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164306123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3164306123
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3288231494
Short name T289
Test name
Test status
Simulation time 59234712283 ps
CPU time 292.28 seconds
Started May 16 01:16:27 PM PDT 24
Finished May 16 01:21:22 PM PDT 24
Peak memory 218048 kb
Host smart-177d3625-09fc-40b4-915d-d3cb1e28ade1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288231494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3288231494
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2710225637
Short name T193
Test name
Test status
Simulation time 56289883606 ps
CPU time 45.83 seconds
Started May 16 01:16:28 PM PDT 24
Finished May 16 01:17:17 PM PDT 24
Peak memory 215188 kb
Host smart-59b3ac82-b808-4093-98d5-714c46b2690c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710225637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2710225637
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.958659219
Short name T202
Test name
Test status
Simulation time 8368202841 ps
CPU time 32.53 seconds
Started May 16 01:16:42 PM PDT 24
Finished May 16 01:17:17 PM PDT 24
Peak memory 212420 kb
Host smart-1f2314c3-9d34-4edb-b024-6c89113e8018
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=958659219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.958659219
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1146392306
Short name T226
Test name
Test status
Simulation time 1323889824 ps
CPU time 19.65 seconds
Started May 16 01:16:30 PM PDT 24
Finished May 16 01:16:52 PM PDT 24
Peak memory 213976 kb
Host smart-227eb692-d486-476f-ab45-cbac4488731b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146392306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1146392306
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3307782788
Short name T108
Test name
Test status
Simulation time 50292540221 ps
CPU time 35.81 seconds
Started May 16 01:16:26 PM PDT 24
Finished May 16 01:17:05 PM PDT 24
Peak memory 212768 kb
Host smart-eca24ce8-7b8b-4603-a612-b796ef440c7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307782788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3307782788
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3089095098
Short name T186
Test name
Test status
Simulation time 719045268 ps
CPU time 8.43 seconds
Started May 16 01:16:27 PM PDT 24
Finished May 16 01:16:38 PM PDT 24
Peak memory 211348 kb
Host smart-2149bec8-8f1b-4931-bd0b-36479c015838
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089095098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3089095098
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3818030956
Short name T213
Test name
Test status
Simulation time 252045306418 ps
CPU time 657.97 seconds
Started May 16 01:16:28 PM PDT 24
Finished May 16 01:27:29 PM PDT 24
Peak memory 225712 kb
Host smart-21158cdf-b160-4f38-8fae-b241908f9c15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818030956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3818030956
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1970531360
Short name T258
Test name
Test status
Simulation time 346236561 ps
CPU time 19.29 seconds
Started May 16 01:16:27 PM PDT 24
Finished May 16 01:16:49 PM PDT 24
Peak memory 214640 kb
Host smart-12c8c6ce-ca56-4450-8a00-b30302c50462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970531360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1970531360
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.199476036
Short name T189
Test name
Test status
Simulation time 3510641850 ps
CPU time 29.81 seconds
Started May 16 01:16:31 PM PDT 24
Finished May 16 01:17:04 PM PDT 24
Peak memory 211428 kb
Host smart-96ad0627-4209-4d45-979e-59effb4e7955
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=199476036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.199476036
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.691442395
Short name T162
Test name
Test status
Simulation time 24559989943 ps
CPU time 62.13 seconds
Started May 16 01:16:26 PM PDT 24
Finished May 16 01:17:30 PM PDT 24
Peak memory 217372 kb
Host smart-609f54da-0fcf-441f-9037-9c6442aa69e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691442395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.691442395
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.667712002
Short name T319
Test name
Test status
Simulation time 1412153139 ps
CPU time 51.67 seconds
Started May 16 01:16:32 PM PDT 24
Finished May 16 01:17:26 PM PDT 24
Peak memory 218692 kb
Host smart-aa689d21-f2e9-40a6-91a9-4e705c68b362
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667712002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.667712002
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2573310381
Short name T210
Test name
Test status
Simulation time 2029185013 ps
CPU time 20.79 seconds
Started May 16 01:16:32 PM PDT 24
Finished May 16 01:16:55 PM PDT 24
Peak memory 211940 kb
Host smart-e752e7a6-fd92-46af-a177-cdd0b1a016d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573310381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2573310381
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1384545519
Short name T19
Test name
Test status
Simulation time 6332533483 ps
CPU time 206.33 seconds
Started May 16 01:16:46 PM PDT 24
Finished May 16 01:20:16 PM PDT 24
Peak memory 237012 kb
Host smart-ee5270ac-0c02-49fa-ba3a-7f9790728bb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384545519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1384545519
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2013488288
Short name T285
Test name
Test status
Simulation time 19104305301 ps
CPU time 47.99 seconds
Started May 16 01:16:26 PM PDT 24
Finished May 16 01:17:16 PM PDT 24
Peak memory 215224 kb
Host smart-90cb4cb6-c249-4b2e-b244-ccc734a6de7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013488288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2013488288
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2844260706
Short name T13
Test name
Test status
Simulation time 3037943698 ps
CPU time 27.19 seconds
Started May 16 01:16:26 PM PDT 24
Finished May 16 01:16:55 PM PDT 24
Peak memory 211292 kb
Host smart-a4c11682-448c-4318-8a87-cc1ba368788c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2844260706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2844260706
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.4200598862
Short name T45
Test name
Test status
Simulation time 5542289141 ps
CPU time 52.89 seconds
Started May 16 01:16:30 PM PDT 24
Finished May 16 01:17:26 PM PDT 24
Peak memory 216348 kb
Host smart-52c7d2d8-c2fd-454f-8407-13c6932749ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200598862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.4200598862
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3604516110
Short name T320
Test name
Test status
Simulation time 20276686917 ps
CPU time 51.54 seconds
Started May 16 01:16:25 PM PDT 24
Finished May 16 01:17:18 PM PDT 24
Peak memory 218580 kb
Host smart-6398adc7-4ddf-4b2e-a30c-e2c1b60e8f80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604516110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3604516110
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1553351485
Short name T267
Test name
Test status
Simulation time 332372469 ps
CPU time 8.63 seconds
Started May 16 01:16:42 PM PDT 24
Finished May 16 01:16:53 PM PDT 24
Peak memory 211400 kb
Host smart-5dfb3c13-20c4-4173-853d-f1a559666a44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553351485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1553351485
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2181271911
Short name T234
Test name
Test status
Simulation time 542253156898 ps
CPU time 520.76 seconds
Started May 16 01:16:27 PM PDT 24
Finished May 16 01:25:10 PM PDT 24
Peak memory 237728 kb
Host smart-bde98396-39f4-4d87-a499-a3b34e21aa88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181271911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2181271911
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1381838852
Short name T166
Test name
Test status
Simulation time 47266533675 ps
CPU time 61.4 seconds
Started May 16 01:16:37 PM PDT 24
Finished May 16 01:17:39 PM PDT 24
Peak memory 214088 kb
Host smart-29452d7a-3c76-445a-9b3a-1f350275c12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381838852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1381838852
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.4208655261
Short name T304
Test name
Test status
Simulation time 16368339521 ps
CPU time 31.95 seconds
Started May 16 01:16:27 PM PDT 24
Finished May 16 01:17:02 PM PDT 24
Peak memory 211804 kb
Host smart-875f50ad-dc2b-4d11-97af-bcdd06660e50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4208655261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.4208655261
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.32952245
Short name T153
Test name
Test status
Simulation time 51994012512 ps
CPU time 58.06 seconds
Started May 16 01:16:28 PM PDT 24
Finished May 16 01:17:29 PM PDT 24
Peak memory 217524 kb
Host smart-b81b3d50-c95f-4e75-b060-1284fcea215a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32952245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.32952245
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2395635125
Short name T294
Test name
Test status
Simulation time 557195521 ps
CPU time 29.91 seconds
Started May 16 01:16:28 PM PDT 24
Finished May 16 01:17:01 PM PDT 24
Peak memory 219252 kb
Host smart-38a4b915-de32-4601-a28f-bb9bfcf3c8b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395635125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2395635125
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3984554998
Short name T59
Test name
Test status
Simulation time 174348606 ps
CPU time 8.61 seconds
Started May 16 01:16:40 PM PDT 24
Finished May 16 01:16:50 PM PDT 24
Peak memory 211384 kb
Host smart-66903cc8-3da1-45c6-8dbd-fa51824a0e96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984554998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3984554998
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1312369031
Short name T205
Test name
Test status
Simulation time 6811716849 ps
CPU time 40.44 seconds
Started May 16 01:16:43 PM PDT 24
Finished May 16 01:17:26 PM PDT 24
Peak memory 215440 kb
Host smart-a7caa92f-2ab0-4c88-a65f-9636de49e62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312369031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1312369031
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3709675434
Short name T333
Test name
Test status
Simulation time 8497791136 ps
CPU time 25.05 seconds
Started May 16 01:16:43 PM PDT 24
Finished May 16 01:17:11 PM PDT 24
Peak memory 212852 kb
Host smart-7ce4dcc0-94bc-4db5-bf18-fa3b75c8afdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3709675434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3709675434
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1682468774
Short name T43
Test name
Test status
Simulation time 1736831896 ps
CPU time 31.56 seconds
Started May 16 01:16:44 PM PDT 24
Finished May 16 01:17:18 PM PDT 24
Peak memory 216784 kb
Host smart-5f03d1c1-4b22-4214-94e4-0992f2dde5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682468774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1682468774
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1324177535
Short name T163
Test name
Test status
Simulation time 11828082313 ps
CPU time 148.89 seconds
Started May 16 01:16:43 PM PDT 24
Finished May 16 01:19:15 PM PDT 24
Peak memory 219428 kb
Host smart-7aaaace2-9fd9-468e-bda9-afc3d3cccc66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324177535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1324177535
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3360174129
Short name T212
Test name
Test status
Simulation time 3308724400 ps
CPU time 27.29 seconds
Started May 16 01:16:44 PM PDT 24
Finished May 16 01:17:14 PM PDT 24
Peak memory 211996 kb
Host smart-bc900f6b-adfe-414b-9127-4abc404902d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360174129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3360174129
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.582356539
Short name T334
Test name
Test status
Simulation time 50775664630 ps
CPU time 194.01 seconds
Started May 16 01:16:40 PM PDT 24
Finished May 16 01:19:57 PM PDT 24
Peak memory 215840 kb
Host smart-4cc67e43-6a04-46ae-89d5-87e75a71a533
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582356539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.582356539
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1230741967
Short name T352
Test name
Test status
Simulation time 32825327344 ps
CPU time 46.72 seconds
Started May 16 01:16:41 PM PDT 24
Finished May 16 01:17:30 PM PDT 24
Peak memory 215236 kb
Host smart-bfdd91a8-81df-4120-8a4a-c0c49a57c9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230741967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1230741967
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1599635487
Short name T200
Test name
Test status
Simulation time 7650481825 ps
CPU time 32.42 seconds
Started May 16 01:16:41 PM PDT 24
Finished May 16 01:17:17 PM PDT 24
Peak memory 211284 kb
Host smart-47e35ff2-c9fa-4b52-8e4c-624da4eb70bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1599635487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1599635487
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1081205611
Short name T198
Test name
Test status
Simulation time 33000644814 ps
CPU time 55.95 seconds
Started May 16 01:16:45 PM PDT 24
Finished May 16 01:17:44 PM PDT 24
Peak memory 217372 kb
Host smart-a27d190d-51ae-44b6-8489-690fe492063a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081205611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1081205611
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3054784426
Short name T340
Test name
Test status
Simulation time 16090716781 ps
CPU time 152.68 seconds
Started May 16 01:16:40 PM PDT 24
Finished May 16 01:19:15 PM PDT 24
Peak memory 220424 kb
Host smart-ff85d19c-75f7-4ccc-aab6-f2e7e2b64d6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054784426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3054784426
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1734147281
Short name T293
Test name
Test status
Simulation time 4075833357 ps
CPU time 32.09 seconds
Started May 16 01:14:56 PM PDT 24
Finished May 16 01:15:31 PM PDT 24
Peak memory 212056 kb
Host smart-70841010-4a4c-40bf-93aa-c153ef4e6094
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734147281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1734147281
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2807460423
Short name T322
Test name
Test status
Simulation time 2829116117 ps
CPU time 221.98 seconds
Started May 16 01:14:43 PM PDT 24
Finished May 16 01:18:26 PM PDT 24
Peak memory 237948 kb
Host smart-35dd0bfd-fad2-4b80-9433-efa564917ecd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807460423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2807460423
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3819673345
Short name T208
Test name
Test status
Simulation time 22180137041 ps
CPU time 49.88 seconds
Started May 16 01:14:51 PM PDT 24
Finished May 16 01:15:43 PM PDT 24
Peak memory 215504 kb
Host smart-c9bfd5f2-dac0-48e0-a5a8-0419fed836ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819673345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3819673345
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2242019610
Short name T44
Test name
Test status
Simulation time 180035522 ps
CPU time 10.43 seconds
Started May 16 01:14:43 PM PDT 24
Finished May 16 01:14:55 PM PDT 24
Peak memory 212480 kb
Host smart-13daf9b1-2078-4e58-bc60-e31ab09a8200
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2242019610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2242019610
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3096530626
Short name T39
Test name
Test status
Simulation time 1165989401 ps
CPU time 27.14 seconds
Started May 16 01:14:36 PM PDT 24
Finished May 16 01:15:04 PM PDT 24
Peak memory 217040 kb
Host smart-fa935163-d2c2-465a-8c0f-93938f6a97b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096530626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3096530626
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.4079235023
Short name T164
Test name
Test status
Simulation time 8136188507 ps
CPU time 93.64 seconds
Started May 16 01:14:40 PM PDT 24
Finished May 16 01:16:15 PM PDT 24
Peak memory 217580 kb
Host smart-89f87b3b-c003-43b1-b9a3-8b5e0de8290e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079235023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.4079235023
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.686119360
Short name T54
Test name
Test status
Simulation time 119398607906 ps
CPU time 8464.41 seconds
Started May 16 01:14:48 PM PDT 24
Finished May 16 03:35:55 PM PDT 24
Peak memory 237864 kb
Host smart-8758e587-29bb-414a-b434-6d1e077a5707
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686119360 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.686119360
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3743931968
Short name T174
Test name
Test status
Simulation time 17363306784 ps
CPU time 24.72 seconds
Started May 16 01:14:49 PM PDT 24
Finished May 16 01:15:16 PM PDT 24
Peak memory 212040 kb
Host smart-d7c7e2c1-f023-40a6-b1a6-43e91c4eeb30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743931968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3743931968
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2704088688
Short name T149
Test name
Test status
Simulation time 3305230590 ps
CPU time 224.02 seconds
Started May 16 01:14:50 PM PDT 24
Finished May 16 01:18:36 PM PDT 24
Peak memory 229716 kb
Host smart-67c42ba0-8933-4595-ad2c-ac36c5d80312
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704088688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2704088688
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.719317690
Short name T138
Test name
Test status
Simulation time 29209149183 ps
CPU time 29.89 seconds
Started May 16 01:14:53 PM PDT 24
Finished May 16 01:15:24 PM PDT 24
Peak memory 211732 kb
Host smart-414f674f-2b1e-4d08-b100-310ea5a3514b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=719317690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.719317690
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.757224434
Short name T9
Test name
Test status
Simulation time 17077828022 ps
CPU time 52.32 seconds
Started May 16 01:14:52 PM PDT 24
Finished May 16 01:15:47 PM PDT 24
Peak memory 216764 kb
Host smart-cc82f506-b693-463e-a035-666a4c320d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757224434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.757224434
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3579807881
Short name T362
Test name
Test status
Simulation time 23623784066 ps
CPU time 113.21 seconds
Started May 16 01:14:44 PM PDT 24
Finished May 16 01:16:39 PM PDT 24
Peak memory 221028 kb
Host smart-69617247-3da3-407b-9107-8876fd1999af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579807881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3579807881
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2668410145
Short name T52
Test name
Test status
Simulation time 613550563308 ps
CPU time 3976.49 seconds
Started May 16 01:14:47 PM PDT 24
Finished May 16 02:21:05 PM PDT 24
Peak memory 252312 kb
Host smart-c7c95e94-9aa0-4f90-96ee-ebdbb83b5eed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668410145 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.2668410145
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1978936891
Short name T182
Test name
Test status
Simulation time 662159517 ps
CPU time 8.67 seconds
Started May 16 01:14:52 PM PDT 24
Finished May 16 01:15:03 PM PDT 24
Peak memory 211328 kb
Host smart-3fad530d-b1c9-4b69-856f-6f83ba7f2daa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978936891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1978936891
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.434096074
Short name T239
Test name
Test status
Simulation time 25745393830 ps
CPU time 379.78 seconds
Started May 16 01:14:56 PM PDT 24
Finished May 16 01:21:20 PM PDT 24
Peak memory 217768 kb
Host smart-2eb3446d-10ba-4497-9ba6-38dbe0c1cc59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434096074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.434096074
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1362724373
Short name T359
Test name
Test status
Simulation time 332499969 ps
CPU time 19.01 seconds
Started May 16 01:14:58 PM PDT 24
Finished May 16 01:15:21 PM PDT 24
Peak memory 214708 kb
Host smart-8e8a1697-9de2-425a-a39c-8081192c2580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362724373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1362724373
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2373629390
Short name T308
Test name
Test status
Simulation time 34459667799 ps
CPU time 22.11 seconds
Started May 16 01:14:56 PM PDT 24
Finished May 16 01:15:22 PM PDT 24
Peak memory 211776 kb
Host smart-13b21a0c-ac1c-4186-9a4a-d8985509b19a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2373629390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2373629390
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1621103524
Short name T271
Test name
Test status
Simulation time 47496063571 ps
CPU time 47.65 seconds
Started May 16 01:14:53 PM PDT 24
Finished May 16 01:15:42 PM PDT 24
Peak memory 218392 kb
Host smart-4052d306-00ff-459c-a98c-af3ecd808d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621103524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1621103524
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3100888497
Short name T12
Test name
Test status
Simulation time 2607066683 ps
CPU time 38.03 seconds
Started May 16 01:14:54 PM PDT 24
Finished May 16 01:15:34 PM PDT 24
Peak memory 216464 kb
Host smart-b59a20ba-2591-4748-9c00-71e34a595245
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100888497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3100888497
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3998503864
Short name T77
Test name
Test status
Simulation time 1643001043 ps
CPU time 18.74 seconds
Started May 16 01:14:56 PM PDT 24
Finished May 16 01:15:18 PM PDT 24
Peak memory 211372 kb
Host smart-ab7b4a4f-1b77-496c-8e54-b64f1ee2ac65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998503864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3998503864
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.141377049
Short name T47
Test name
Test status
Simulation time 50447649179 ps
CPU time 548.26 seconds
Started May 16 01:14:56 PM PDT 24
Finished May 16 01:24:08 PM PDT 24
Peak memory 238028 kb
Host smart-cd800ca9-7177-463f-a485-b2e5b272cfac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141377049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.141377049
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.236936000
Short name T358
Test name
Test status
Simulation time 17804308641 ps
CPU time 35.72 seconds
Started May 16 01:14:54 PM PDT 24
Finished May 16 01:15:32 PM PDT 24
Peak memory 211644 kb
Host smart-a629d13c-9d85-4308-9de0-8d3b21a98222
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=236936000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.236936000
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1622852385
Short name T268
Test name
Test status
Simulation time 1412133615 ps
CPU time 21.23 seconds
Started May 16 01:14:53 PM PDT 24
Finished May 16 01:15:17 PM PDT 24
Peak memory 217352 kb
Host smart-3e9c1c75-dd24-48ff-9000-2f164cdddb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622852385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1622852385
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1851128441
Short name T3
Test name
Test status
Simulation time 2034952043 ps
CPU time 25.66 seconds
Started May 16 01:14:56 PM PDT 24
Finished May 16 01:15:26 PM PDT 24
Peak memory 217436 kb
Host smart-3c521469-ba0b-4527-b552-3813e2c5a3ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851128441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1851128441
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.263117196
Short name T6
Test name
Test status
Simulation time 8690761419 ps
CPU time 34.68 seconds
Started May 16 01:14:54 PM PDT 24
Finished May 16 01:15:32 PM PDT 24
Peak memory 212312 kb
Host smart-4f807132-02a4-483d-b68b-56b7742f676d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263117196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.263117196
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.976263035
Short name T264
Test name
Test status
Simulation time 34686413735 ps
CPU time 190.87 seconds
Started May 16 01:14:59 PM PDT 24
Finished May 16 01:18:13 PM PDT 24
Peak memory 237924 kb
Host smart-bff922db-fbed-4109-921b-4ce826980fc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976263035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.976263035
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3207419076
Short name T282
Test name
Test status
Simulation time 3383661855 ps
CPU time 28.04 seconds
Started May 16 01:14:57 PM PDT 24
Finished May 16 01:15:29 PM PDT 24
Peak memory 214816 kb
Host smart-07bd98ab-832a-4ab2-a90e-2361c4b74a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207419076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3207419076
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2809589233
Short name T329
Test name
Test status
Simulation time 3885912409 ps
CPU time 27.29 seconds
Started May 16 01:14:51 PM PDT 24
Finished May 16 01:15:20 PM PDT 24
Peak memory 211576 kb
Host smart-a03390c9-ea65-41df-a473-13a651d9e19b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2809589233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2809589233
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.522997280
Short name T337
Test name
Test status
Simulation time 523639680 ps
CPU time 20.16 seconds
Started May 16 01:14:54 PM PDT 24
Finished May 16 01:15:18 PM PDT 24
Peak memory 217592 kb
Host smart-85e02dab-55f1-46d5-9770-de9726d10533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522997280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.522997280
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1829580901
Short name T151
Test name
Test status
Simulation time 7746491333 ps
CPU time 34.17 seconds
Started May 16 01:14:55 PM PDT 24
Finished May 16 01:15:33 PM PDT 24
Peak memory 213552 kb
Host smart-aa91766c-2ddd-48a6-be8a-cec8cd44b2f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829580901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1829580901
Directory /workspace/9.rom_ctrl_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%