| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.52 | 96.97 | 93.01 | 97.88 | 100.00 | 98.37 | 98.03 | 98.37 |
| T299 | /workspace/coverage/default/44.rom_ctrl_stress_all.1465574832 | May 19 12:50:13 PM PDT 24 | May 19 12:51:18 PM PDT 24 | 30528472955 ps | ||
| T300 | /workspace/coverage/default/0.rom_ctrl_smoke.2196985111 | May 19 12:49:32 PM PDT 24 | May 19 12:50:39 PM PDT 24 | 32951870453 ps | ||
| T301 | /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1241689551 | May 19 12:50:10 PM PDT 24 | May 19 01:00:28 PM PDT 24 | 70871685345 ps | ||
| T302 | /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3192391685 | May 19 12:49:51 PM PDT 24 | May 19 12:50:44 PM PDT 24 | 21552954178 ps | ||
| T303 | /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2292746502 | May 19 12:49:28 PM PDT 24 | May 19 12:49:56 PM PDT 24 | 2354329405 ps | ||
| T304 | /workspace/coverage/default/24.rom_ctrl_smoke.2838155690 | May 19 12:49:44 PM PDT 24 | May 19 12:50:28 PM PDT 24 | 24014940854 ps | ||
| T305 | /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2434833815 | May 19 12:49:53 PM PDT 24 | May 19 12:56:35 PM PDT 24 | 138122560595 ps | ||
| T306 | /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2140452278 | May 19 12:49:50 PM PDT 24 | May 19 12:50:16 PM PDT 24 | 2134013598 ps | ||
| T307 | /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3695196626 | May 19 12:49:54 PM PDT 24 | May 19 12:50:32 PM PDT 24 | 2464753275 ps | ||
| T308 | /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2884538345 | May 19 12:49:41 PM PDT 24 | May 19 12:56:28 PM PDT 24 | 54933127654 ps | ||
| T309 | /workspace/coverage/default/40.rom_ctrl_alert_test.3197341799 | May 19 12:50:03 PM PDT 24 | May 19 12:50:36 PM PDT 24 | 36404711930 ps | ||
| T310 | /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2766182342 | May 19 12:49:29 PM PDT 24 | May 19 12:49:44 PM PDT 24 | 180596916 ps | ||
| T311 | /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.632267999 | May 19 12:49:27 PM PDT 24 | May 19 12:50:26 PM PDT 24 | 24506820368 ps | ||
| T312 | /workspace/coverage/default/1.rom_ctrl_alert_test.1063332034 | May 19 12:49:42 PM PDT 24 | May 19 12:49:54 PM PDT 24 | 167699757 ps | ||
| T313 | /workspace/coverage/default/24.rom_ctrl_stress_all.2604633064 | May 19 12:49:43 PM PDT 24 | May 19 12:52:17 PM PDT 24 | 59104971421 ps | ||
| T314 | /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3316976461 | May 19 12:50:21 PM PDT 24 | May 19 01:02:09 PM PDT 24 | 251520587005 ps | ||
| T315 | /workspace/coverage/default/48.rom_ctrl_stress_all.1904292334 | May 19 12:50:21 PM PDT 24 | May 19 12:50:58 PM PDT 24 | 9352743114 ps | ||
| T316 | /workspace/coverage/default/15.rom_ctrl_smoke.2545702171 | May 19 12:49:51 PM PDT 24 | May 19 12:50:34 PM PDT 24 | 6390954606 ps | ||
| T317 | /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1558993045 | May 19 12:50:08 PM PDT 24 | May 19 01:04:59 PM PDT 24 | 195760465471 ps | ||
| T318 | /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3681054169 | May 19 12:49:45 PM PDT 24 | May 19 12:50:40 PM PDT 24 | 5630688219 ps | ||
| T319 | /workspace/coverage/default/37.rom_ctrl_stress_all.3889298878 | May 19 12:49:57 PM PDT 24 | May 19 12:51:02 PM PDT 24 | 26296092189 ps | ||
| T320 | /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.367279667 | May 19 12:49:44 PM PDT 24 | May 19 12:55:22 PM PDT 24 | 225186100348 ps | ||
| T34 | /workspace/coverage/default/2.rom_ctrl_sec_cm.2168675189 | May 19 12:49:27 PM PDT 24 | May 19 12:51:34 PM PDT 24 | 1007361289 ps | ||
| T321 | /workspace/coverage/default/43.rom_ctrl_alert_test.701132760 | May 19 12:50:05 PM PDT 24 | May 19 12:50:40 PM PDT 24 | 4396474986 ps | ||
| T322 | /workspace/coverage/default/22.rom_ctrl_smoke.3498521016 | May 19 12:49:48 PM PDT 24 | May 19 12:50:30 PM PDT 24 | 5935529723 ps | ||
| T19 | /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2957977543 | May 19 12:49:32 PM PDT 24 | May 19 01:59:00 PM PDT 24 | 115416070305 ps | ||
| T91 | /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4044219335 | May 19 12:50:01 PM PDT 24 | May 19 12:50:31 PM PDT 24 | 3685393138 ps | ||
| T323 | /workspace/coverage/default/3.rom_ctrl_smoke.1385781055 | May 19 12:49:28 PM PDT 24 | May 19 12:50:43 PM PDT 24 | 50171619099 ps | ||
| T324 | /workspace/coverage/default/5.rom_ctrl_stress_all.3235339876 | May 19 12:49:29 PM PDT 24 | May 19 12:49:45 PM PDT 24 | 210585386 ps | ||
| T325 | /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3324219372 | May 19 12:50:04 PM PDT 24 | May 19 12:50:17 PM PDT 24 | 259305712 ps | ||
| T326 | /workspace/coverage/default/21.rom_ctrl_alert_test.1709117751 | May 19 12:49:42 PM PDT 24 | May 19 12:50:07 PM PDT 24 | 2149400780 ps | ||
| T327 | /workspace/coverage/default/41.rom_ctrl_stress_all.1459546680 | May 19 12:50:00 PM PDT 24 | May 19 12:50:36 PM PDT 24 | 16294869627 ps | ||
| T328 | /workspace/coverage/default/7.rom_ctrl_stress_all.115927074 | May 19 12:49:30 PM PDT 24 | May 19 12:50:03 PM PDT 24 | 3486205586 ps | ||
| T329 | /workspace/coverage/default/42.rom_ctrl_alert_test.3783892434 | May 19 12:50:10 PM PDT 24 | May 19 12:50:41 PM PDT 24 | 22414658763 ps | ||
| T330 | /workspace/coverage/default/28.rom_ctrl_alert_test.2176241513 | May 19 12:49:44 PM PDT 24 | May 19 12:50:21 PM PDT 24 | 16961811819 ps | ||
| T331 | /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1841155174 | May 19 12:49:49 PM PDT 24 | May 19 12:50:35 PM PDT 24 | 15735321191 ps | ||
| T332 | /workspace/coverage/default/23.rom_ctrl_alert_test.3585303394 | May 19 12:49:41 PM PDT 24 | May 19 12:49:52 PM PDT 24 | 660188230 ps | ||
| T333 | /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.220405370 | May 19 12:49:53 PM PDT 24 | May 19 12:50:15 PM PDT 24 | 972167135 ps | ||
| T334 | /workspace/coverage/default/18.rom_ctrl_smoke.323883669 | May 19 12:49:35 PM PDT 24 | May 19 12:49:59 PM PDT 24 | 347918579 ps | ||
| T335 | /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.940181390 | May 19 12:49:35 PM PDT 24 | May 19 12:49:53 PM PDT 24 | 2095942229 ps | ||
| T336 | /workspace/coverage/default/6.rom_ctrl_alert_test.3673433179 | May 19 12:49:48 PM PDT 24 | May 19 12:50:18 PM PDT 24 | 20415960715 ps | ||
| T337 | /workspace/coverage/default/39.rom_ctrl_smoke.2279201777 | May 19 12:49:57 PM PDT 24 | May 19 12:50:20 PM PDT 24 | 374488956 ps | ||
| T338 | /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3965220252 | May 19 12:50:23 PM PDT 24 | May 19 01:33:57 PM PDT 24 | 406572114382 ps | ||
| T339 | /workspace/coverage/default/31.rom_ctrl_stress_all.3073323642 | May 19 12:49:48 PM PDT 24 | May 19 12:51:11 PM PDT 24 | 5790777828 ps | ||
| T340 | /workspace/coverage/default/40.rom_ctrl_stress_all.3056294272 | May 19 12:49:59 PM PDT 24 | May 19 12:51:04 PM PDT 24 | 24928820949 ps | ||
| T341 | /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1267770331 | May 19 12:49:37 PM PDT 24 | May 19 12:52:11 PM PDT 24 | 26645960451 ps | ||
| T342 | /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.487363484 | May 19 12:49:39 PM PDT 24 | May 19 12:50:00 PM PDT 24 | 3667781414 ps | ||
| T343 | /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3596293203 | May 19 12:49:44 PM PDT 24 | May 19 12:50:55 PM PDT 24 | 33384889884 ps | ||
| T344 | /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3009492898 | May 19 12:49:31 PM PDT 24 | May 19 12:50:17 PM PDT 24 | 12434967078 ps | ||
| T345 | /workspace/coverage/default/20.rom_ctrl_alert_test.1519059387 | May 19 12:49:45 PM PDT 24 | May 19 12:50:10 PM PDT 24 | 2213657769 ps | ||
| T346 | /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.750566676 | May 19 12:49:42 PM PDT 24 | May 19 12:50:17 PM PDT 24 | 16052235022 ps | ||
| T347 | /workspace/coverage/default/16.rom_ctrl_stress_all.4084869352 | May 19 12:49:36 PM PDT 24 | May 19 12:50:52 PM PDT 24 | 6402287972 ps | ||
| T348 | /workspace/coverage/default/11.rom_ctrl_stress_all.3447275991 | May 19 12:49:34 PM PDT 24 | May 19 12:50:00 PM PDT 24 | 364744642 ps | ||
| T349 | /workspace/coverage/default/9.rom_ctrl_smoke.3407462989 | May 19 12:49:27 PM PDT 24 | May 19 12:50:48 PM PDT 24 | 28140184203 ps | ||
| T350 | /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.907014173 | May 19 12:50:25 PM PDT 24 | May 19 12:50:47 PM PDT 24 | 1375101300 ps | ||
| T351 | /workspace/coverage/default/17.rom_ctrl_stress_all.2893550792 | May 19 12:49:37 PM PDT 24 | May 19 12:52:12 PM PDT 24 | 16921379281 ps | ||
| T352 | /workspace/coverage/default/46.rom_ctrl_alert_test.1628557761 | May 19 12:50:15 PM PDT 24 | May 19 12:50:44 PM PDT 24 | 3181464910 ps | ||
| T353 | /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3221000904 | May 19 12:49:52 PM PDT 24 | May 19 12:50:27 PM PDT 24 | 3881899240 ps | ||
| T354 | /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2431668 | May 19 12:49:53 PM PDT 24 | May 19 12:50:16 PM PDT 24 | 1435642909 ps | ||
| T355 | /workspace/coverage/default/24.rom_ctrl_alert_test.1069068030 | May 19 12:49:47 PM PDT 24 | May 19 12:49:58 PM PDT 24 | 1098355805 ps | ||
| T356 | /workspace/coverage/default/13.rom_ctrl_smoke.4157053937 | May 19 12:49:26 PM PDT 24 | May 19 12:50:35 PM PDT 24 | 6904149344 ps | ||
| T357 | /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.569014709 | May 19 12:49:42 PM PDT 24 | May 19 12:49:58 PM PDT 24 | 863968766 ps | ||
| T358 | /workspace/coverage/default/7.rom_ctrl_smoke.3101166331 | May 19 12:49:46 PM PDT 24 | May 19 12:50:43 PM PDT 24 | 14900750707 ps | ||
| T359 | /workspace/coverage/default/1.rom_ctrl_smoke.1441962792 | May 19 12:49:23 PM PDT 24 | May 19 12:50:18 PM PDT 24 | 5401631739 ps | ||
| T360 | /workspace/coverage/default/8.rom_ctrl_alert_test.3287745899 | May 19 12:49:37 PM PDT 24 | May 19 12:49:49 PM PDT 24 | 313385819 ps | ||
| T57 | /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.4182168394 | May 19 12:49:20 PM PDT 24 | May 19 12:49:36 PM PDT 24 | 1831055595 ps | ||
| T58 | /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2384924386 | May 19 12:49:23 PM PDT 24 | May 19 12:49:34 PM PDT 24 | 689596065 ps | ||
| T59 | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.182219731 | May 19 12:49:25 PM PDT 24 | May 19 12:50:01 PM PDT 24 | 4445920832 ps | ||
| T361 | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2088267449 | May 19 12:49:23 PM PDT 24 | May 19 12:49:45 PM PDT 24 | 3606383074 ps | ||
| T362 | /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.952266696 | May 19 12:49:22 PM PDT 24 | May 19 12:49:37 PM PDT 24 | 174159757 ps | ||
| T63 | /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3141666050 | May 19 12:49:14 PM PDT 24 | May 19 12:51:22 PM PDT 24 | 16095986141 ps | ||
| T363 | /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2072551357 | May 19 12:49:25 PM PDT 24 | May 19 12:49:50 PM PDT 24 | 14006327123 ps | ||
| T54 | /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1988177936 | May 19 12:49:13 PM PDT 24 | May 19 12:51:48 PM PDT 24 | 1181786331 ps | ||
| T364 | /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1162402213 | May 19 12:49:17 PM PDT 24 | May 19 12:49:30 PM PDT 24 | 170990940 ps | ||
| T365 | /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1502421926 | May 19 12:49:21 PM PDT 24 | May 19 12:49:51 PM PDT 24 | 3655236682 ps | ||
| T64 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1668561398 | May 19 12:49:18 PM PDT 24 | May 19 12:49:49 PM PDT 24 | 16294111628 ps | ||
| T92 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2832972553 | May 19 12:49:22 PM PDT 24 | May 19 12:49:39 PM PDT 24 | 640779338 ps | ||
| T366 | /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2410238744 | May 19 12:49:25 PM PDT 24 | May 19 12:50:05 PM PDT 24 | 14787755304 ps | ||
| T86 | /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.749677842 | May 19 12:49:28 PM PDT 24 | May 19 12:49:55 PM PDT 24 | 40366294592 ps | ||
| T65 | /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3487496665 | May 19 12:49:12 PM PDT 24 | May 19 12:49:43 PM PDT 24 | 7905711162 ps | ||
| T55 | /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2528311617 | May 19 12:49:21 PM PDT 24 | May 19 12:50:57 PM PDT 24 | 10675963712 ps | ||
| T367 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1438351442 | May 19 12:49:22 PM PDT 24 | May 19 12:49:51 PM PDT 24 | 3322815577 ps | ||
| T66 | /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1491116496 | May 19 12:49:26 PM PDT 24 | May 19 12:49:58 PM PDT 24 | 5953994743 ps | ||
| T67 | /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2010029214 | May 19 12:49:21 PM PDT 24 | May 19 12:51:51 PM PDT 24 | 15415268316 ps | ||
| T68 | /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.747046838 | May 19 12:49:30 PM PDT 24 | May 19 12:51:45 PM PDT 24 | 12830925061 ps | ||
| T56 | /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2248969961 | May 19 12:49:18 PM PDT 24 | May 19 12:52:04 PM PDT 24 | 4458242902 ps | ||
| T100 | /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3690121453 | May 19 12:49:28 PM PDT 24 | May 19 12:51:09 PM PDT 24 | 2922500858 ps | ||
| T69 | /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.817788532 | May 19 12:49:21 PM PDT 24 | May 19 12:49:55 PM PDT 24 | 8343600967 ps | ||
| T368 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2241032765 | May 19 12:49:13 PM PDT 24 | May 19 12:49:41 PM PDT 24 | 13760839491 ps | ||
| T70 | /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1927733457 | May 19 12:49:12 PM PDT 24 | May 19 12:50:17 PM PDT 24 | 24174087126 ps | ||
| T87 | /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2947380075 | May 19 12:49:11 PM PDT 24 | May 19 12:49:33 PM PDT 24 | 3939185254 ps | ||
| T71 | /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2249212178 | May 19 12:49:28 PM PDT 24 | May 19 12:50:02 PM PDT 24 | 3839552232 ps | ||
| T75 | /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.708107011 | May 19 12:49:23 PM PDT 24 | May 19 12:50:49 PM PDT 24 | 7882041677 ps | ||
| T88 | /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4290721288 | May 19 12:49:25 PM PDT 24 | May 19 12:49:53 PM PDT 24 | 24657615377 ps | ||
| T369 | /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.687589202 | May 19 12:49:12 PM PDT 24 | May 19 12:49:38 PM PDT 24 | 2625524259 ps | ||
| T370 | /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.821494859 | May 19 12:49:28 PM PDT 24 | May 19 12:49:41 PM PDT 24 | 193089381 ps | ||
| T371 | /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3381705004 | May 19 12:49:22 PM PDT 24 | May 19 12:49:55 PM PDT 24 | 12726023256 ps | ||
| T372 | /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2455583191 | May 19 12:49:18 PM PDT 24 | May 19 12:49:30 PM PDT 24 | 867915578 ps | ||
| T373 | /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4029687363 | May 19 12:49:19 PM PDT 24 | May 19 12:49:48 PM PDT 24 | 3322809727 ps | ||
| T98 | /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3675897936 | May 19 12:49:24 PM PDT 24 | May 19 12:50:55 PM PDT 24 | 1335532491 ps | ||
| T374 | /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2480079676 | May 19 12:49:07 PM PDT 24 | May 19 12:49:33 PM PDT 24 | 21165679825 ps | ||
| T375 | /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2378202033 | May 19 12:49:28 PM PDT 24 | May 19 12:49:46 PM PDT 24 | 1185636387 ps | ||
| T376 | /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.748410354 | May 19 12:49:24 PM PDT 24 | May 19 12:49:38 PM PDT 24 | 319818357 ps | ||
| T377 | /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1334867978 | May 19 12:49:23 PM PDT 24 | May 19 12:49:42 PM PDT 24 | 2037451213 ps | ||
| T378 | /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.140208452 | May 19 12:49:30 PM PDT 24 | May 19 12:50:04 PM PDT 24 | 13116617555 ps | ||
| T379 | /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1999377157 | May 19 12:49:29 PM PDT 24 | May 19 12:49:41 PM PDT 24 | 1498812434 ps | ||
| T76 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.821416864 | May 19 12:49:17 PM PDT 24 | May 19 12:49:52 PM PDT 24 | 7474632893 ps | ||
| T380 | /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.19371584 | May 19 12:49:31 PM PDT 24 | May 19 12:51:49 PM PDT 24 | 16777958368 ps | ||
| T381 | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2360803256 | May 19 12:49:21 PM PDT 24 | May 19 12:49:32 PM PDT 24 | 1647525513 ps | ||
| T89 | /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1169221951 | May 19 12:49:36 PM PDT 24 | May 19 12:50:11 PM PDT 24 | 3907326541 ps | ||
| T382 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3596682648 | May 19 12:49:19 PM PDT 24 | May 19 12:49:40 PM PDT 24 | 1650361797 ps | ||
| T383 | /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4286719515 | May 19 12:49:25 PM PDT 24 | May 19 12:49:52 PM PDT 24 | 13776205040 ps | ||
| T384 | /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3480362218 | May 19 12:49:22 PM PDT 24 | May 19 12:49:54 PM PDT 24 | 14702119801 ps | ||
| T90 | /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3006223601 | May 19 12:49:18 PM PDT 24 | May 19 12:49:42 PM PDT 24 | 9933746334 ps | ||
| T101 | /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4158546125 | May 19 12:49:26 PM PDT 24 | May 19 12:50:51 PM PDT 24 | 994105598 ps | ||
| T385 | /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.232168194 | May 19 12:49:17 PM PDT 24 | May 19 12:49:49 PM PDT 24 | 16121725871 ps | ||
| T77 | /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2457487845 | May 19 12:49:24 PM PDT 24 | May 19 12:49:49 PM PDT 24 | 20457007671 ps | ||
| T99 | /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1731999497 | May 19 12:49:20 PM PDT 24 | May 19 12:52:18 PM PDT 24 | 48305137241 ps | ||
| T386 | /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4002729746 | May 19 12:49:24 PM PDT 24 | May 19 12:50:00 PM PDT 24 | 11868267191 ps | ||
| T387 | /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.208104888 | May 19 12:49:26 PM PDT 24 | May 19 12:49:46 PM PDT 24 | 1191316374 ps | ||
| T388 | /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1494439692 | May 19 12:49:29 PM PDT 24 | May 19 12:50:04 PM PDT 24 | 7337039503 ps | ||
| T389 | /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1020119392 | May 19 12:49:27 PM PDT 24 | May 19 12:49:40 PM PDT 24 | 350968791 ps | ||
| T390 | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3663808931 | May 19 12:49:24 PM PDT 24 | May 19 12:49:58 PM PDT 24 | 24370625080 ps | ||
| T391 | /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.572490089 | May 19 12:49:23 PM PDT 24 | May 19 12:52:17 PM PDT 24 | 21517428248 ps | ||
| T392 | /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.710683246 | May 19 12:49:25 PM PDT 24 | May 19 12:49:49 PM PDT 24 | 4349522601 ps | ||
| T103 | /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2162900723 | May 19 12:49:14 PM PDT 24 | May 19 12:50:49 PM PDT 24 | 2148681129 ps | ||
| T393 | /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3992420348 | May 19 12:49:22 PM PDT 24 | May 19 12:49:43 PM PDT 24 | 4610800990 ps | ||
| T394 | /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3306565344 | May 19 12:49:32 PM PDT 24 | May 19 12:50:03 PM PDT 24 | 5882439484 ps | ||
| T395 | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.866102079 | May 19 12:49:28 PM PDT 24 | May 19 12:49:53 PM PDT 24 | 7256273519 ps | ||
| T396 | /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3977190851 | May 19 12:49:25 PM PDT 24 | May 19 12:49:48 PM PDT 24 | 2743151303 ps | ||
| T397 | /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1635276362 | May 19 12:49:27 PM PDT 24 | May 19 12:49:48 PM PDT 24 | 9384716752 ps | ||
| T398 | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.548622341 | May 19 12:49:21 PM PDT 24 | May 19 12:49:39 PM PDT 24 | 180785407 ps | ||
| T399 | /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3023301672 | May 19 12:49:29 PM PDT 24 | May 19 12:49:42 PM PDT 24 | 385607434 ps | ||
| T400 | /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2269223589 | May 19 12:49:26 PM PDT 24 | May 19 12:50:03 PM PDT 24 | 5106339092 ps | ||
| T102 | /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1247319743 | May 19 12:49:25 PM PDT 24 | May 19 12:52:08 PM PDT 24 | 620310797 ps | ||
| T78 | /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1915427970 | May 19 12:49:28 PM PDT 24 | May 19 12:50:48 PM PDT 24 | 6397279282 ps | ||
| T401 | /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.369739302 | May 19 12:49:41 PM PDT 24 | May 19 12:49:53 PM PDT 24 | 363543420 ps | ||
| T97 | /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1533371106 | May 19 12:49:19 PM PDT 24 | May 19 12:51:06 PM PDT 24 | 29661199243 ps | ||
| T402 | /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1097628836 | May 19 12:49:25 PM PDT 24 | May 19 12:49:56 PM PDT 24 | 5377926563 ps | ||
| T403 | /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1229318088 | May 19 12:49:21 PM PDT 24 | May 19 12:49:39 PM PDT 24 | 1505880386 ps | ||
| T404 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3250283057 | May 19 12:49:23 PM PDT 24 | May 19 12:49:53 PM PDT 24 | 3112440132 ps | ||
| T104 | /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3381936511 | May 19 12:49:29 PM PDT 24 | May 19 12:52:19 PM PDT 24 | 8066877821 ps | ||
| T405 | /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.802897164 | May 19 12:49:23 PM PDT 24 | May 19 12:50:57 PM PDT 24 | 8079616886 ps | ||
| T406 | /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1021927015 | May 19 12:49:22 PM PDT 24 | May 19 12:49:33 PM PDT 24 | 688981397 ps | ||
| T407 | /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3899353642 | May 19 12:49:21 PM PDT 24 | May 19 12:49:43 PM PDT 24 | 3941188357 ps | ||
| T79 | /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3433129605 | May 19 12:49:25 PM PDT 24 | May 19 12:52:42 PM PDT 24 | 119094218935 ps | ||
| T408 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2853736108 | May 19 12:49:20 PM PDT 24 | May 19 12:49:38 PM PDT 24 | 6107187682 ps | ||
| T409 | /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3421291979 | May 19 12:49:30 PM PDT 24 | May 19 12:49:57 PM PDT 24 | 21799184783 ps | ||
| T410 | /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2897026344 | May 19 12:49:18 PM PDT 24 | May 19 12:49:51 PM PDT 24 | 17447202150 ps | ||
| T411 | /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3626624071 | May 19 12:49:29 PM PDT 24 | May 19 12:49:50 PM PDT 24 | 1285104327 ps | ||
| T412 | /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.581434871 | May 19 12:49:27 PM PDT 24 | May 19 12:50:00 PM PDT 24 | 14477593418 ps | ||
| T413 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3187486527 | May 19 12:49:24 PM PDT 24 | May 19 12:49:36 PM PDT 24 | 346138384 ps | ||
| T85 | /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3991515592 | May 19 12:49:28 PM PDT 24 | May 19 12:52:12 PM PDT 24 | 16921829927 ps | ||
| T414 | /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2106639760 | May 19 12:49:33 PM PDT 24 | May 19 12:49:49 PM PDT 24 | 689180451 ps | ||
| T415 | /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1084853349 | May 19 12:49:32 PM PDT 24 | May 19 12:49:59 PM PDT 24 | 1647692176 ps | ||
| T416 | /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4035781287 | May 19 12:49:25 PM PDT 24 | May 19 12:49:48 PM PDT 24 | 3458744492 ps | ||
| T417 | /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3904673108 | May 19 12:49:14 PM PDT 24 | May 19 12:49:40 PM PDT 24 | 2458288656 ps | ||
| T418 | /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2799951730 | May 19 12:49:27 PM PDT 24 | May 19 12:49:54 PM PDT 24 | 7008258942 ps | ||
| T419 | /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2352615815 | May 19 12:49:24 PM PDT 24 | May 19 12:50:59 PM PDT 24 | 9091233072 ps | ||
| T420 | /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2317403470 | May 19 12:49:27 PM PDT 24 | May 19 12:51:10 PM PDT 24 | 27985119194 ps | ||
| T421 | /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2039851392 | May 19 12:49:31 PM PDT 24 | May 19 12:50:05 PM PDT 24 | 3621590122 ps | ||
| T422 | /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1439229966 | May 19 12:49:24 PM PDT 24 | May 19 12:50:06 PM PDT 24 | 4923319898 ps | ||
| T423 | /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2892508109 | May 19 12:49:19 PM PDT 24 | May 19 12:49:39 PM PDT 24 | 9648892454 ps | ||
| T106 | /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3128924288 | May 19 12:49:30 PM PDT 24 | May 19 12:52:13 PM PDT 24 | 2703208749 ps | ||
| T424 | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2715842861 | May 19 12:49:06 PM PDT 24 | May 19 12:49:16 PM PDT 24 | 172467792 ps | ||
| T425 | /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2301094048 | May 19 12:49:26 PM PDT 24 | May 19 12:52:26 PM PDT 24 | 82338857234 ps | ||
| T426 | /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3723392656 | May 19 12:49:19 PM PDT 24 | May 19 12:49:42 PM PDT 24 | 2221329501 ps | ||
| T427 | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2601290720 | May 19 12:49:18 PM PDT 24 | May 19 12:49:27 PM PDT 24 | 688992666 ps | ||
| T428 | /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.982755778 | May 19 12:49:19 PM PDT 24 | May 19 12:49:43 PM PDT 24 | 5732082141 ps | ||
| T429 | /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2972616356 | May 19 12:49:10 PM PDT 24 | May 19 12:49:39 PM PDT 24 | 3554292024 ps | ||
| T107 | /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.397704825 | May 19 12:49:24 PM PDT 24 | May 19 12:50:48 PM PDT 24 | 3214015302 ps | ||
| T430 | /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2214170299 | May 19 12:49:20 PM PDT 24 | May 19 12:49:30 PM PDT 24 | 169179974 ps | ||
| T108 | /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3252897527 | May 19 12:49:19 PM PDT 24 | May 19 12:50:58 PM PDT 24 | 21475139329 ps | ||
| T431 | /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3892656410 | May 19 12:49:19 PM PDT 24 | May 19 12:52:47 PM PDT 24 | 51393795885 ps | ||
| T432 | /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.693348630 | May 19 12:49:21 PM PDT 24 | May 19 12:49:51 PM PDT 24 | 31317691378 ps | ||
| T433 | /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.914792421 | May 19 12:49:27 PM PDT 24 | May 19 12:49:52 PM PDT 24 | 21344673145 ps | ||
| T434 | /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2268945168 | May 19 12:49:28 PM PDT 24 | May 19 12:50:07 PM PDT 24 | 16077013255 ps | ||
| T435 | /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2844749917 | May 19 12:49:27 PM PDT 24 | May 19 12:49:48 PM PDT 24 | 1354760394 ps | ||
| T436 | /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3681378789 | May 19 12:49:26 PM PDT 24 | May 19 12:49:38 PM PDT 24 | 169242801 ps | ||
| T437 | /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3833195237 | May 19 12:49:23 PM PDT 24 | May 19 12:51:38 PM PDT 24 | 51394540808 ps | ||
| T438 | /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.846316848 | May 19 12:49:25 PM PDT 24 | May 19 12:49:51 PM PDT 24 | 17062501094 ps | ||
| T439 | /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4216740619 | May 19 12:49:23 PM PDT 24 | May 19 12:49:34 PM PDT 24 | 3295471943 ps | ||
| T440 | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2695524338 | May 19 12:49:27 PM PDT 24 | May 19 12:49:48 PM PDT 24 | 1515598329 ps | ||
| T441 | /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2754181233 | May 19 12:49:15 PM PDT 24 | May 19 12:50:47 PM PDT 24 | 70908361302 ps | ||
| T442 | /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3375229747 | May 19 12:49:10 PM PDT 24 | May 19 12:49:43 PM PDT 24 | 6150203023 ps | ||
| T80 | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.839100539 | May 19 12:49:20 PM PDT 24 | May 19 12:50:00 PM PDT 24 | 4433000617 ps | ||
| T443 | /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2435541897 | May 19 12:49:33 PM PDT 24 | May 19 12:50:00 PM PDT 24 | 3752432043 ps | ||
| T81 | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1374611538 | May 19 12:49:13 PM PDT 24 | May 19 12:49:42 PM PDT 24 | 3613540801 ps | ||
| T105 | /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.169053884 | May 19 12:49:28 PM PDT 24 | May 19 12:51:04 PM PDT 24 | 8731017584 ps | ||
| T444 | /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3534707786 | May 19 12:49:24 PM PDT 24 | May 19 12:49:54 PM PDT 24 | 13615551444 ps | ||
| T82 | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.939425359 | May 19 12:49:23 PM PDT 24 | May 19 12:49:41 PM PDT 24 | 2303400236 ps | ||
| T445 | /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.558844547 | May 19 12:49:29 PM PDT 24 | May 19 12:51:37 PM PDT 24 | 16259052397 ps | ||
| T446 | /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.688883963 | May 19 12:49:21 PM PDT 24 | May 19 12:49:44 PM PDT 24 | 2224618111 ps | ||
| T447 | /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2379227467 | May 19 12:49:22 PM PDT 24 | May 19 12:49:54 PM PDT 24 | 10449576744 ps | ||
| T448 | /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2061288677 | May 19 12:49:08 PM PDT 24 | May 19 12:49:24 PM PDT 24 | 496571041 ps | ||
| T449 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1927189692 | May 19 12:49:18 PM PDT 24 | May 19 12:49:49 PM PDT 24 | 18167709852 ps | ||
| T450 | /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.558187025 | May 19 12:49:15 PM PDT 24 | May 19 12:50:12 PM PDT 24 | 4289793692 ps | ||
| T451 | /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3370518794 | May 19 12:49:37 PM PDT 24 | May 19 12:51:00 PM PDT 24 | 1231376031 ps | ||
| T83 | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3081432498 | May 19 12:49:19 PM PDT 24 | May 19 12:49:45 PM PDT 24 | 10111907193 ps | ||
| T452 | /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3542755630 | May 19 12:49:28 PM PDT 24 | May 19 12:49:52 PM PDT 24 | 4124609681 ps | ||
| T453 | /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3205008155 | May 19 12:49:23 PM PDT 24 | May 19 12:49:37 PM PDT 24 | 179142340 ps | ||
| T84 | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1983840610 | May 19 12:49:17 PM PDT 24 | May 19 12:49:49 PM PDT 24 | 16752448145 ps | ||
| T454 | /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3835189844 | May 19 12:49:23 PM PDT 24 | May 19 12:50:56 PM PDT 24 | 7202493080 ps | ||
| T455 | /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3998056258 | May 19 12:49:25 PM PDT 24 | May 19 12:51:39 PM PDT 24 | 16115477478 ps | ||
| T456 | /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2507094225 | May 19 12:49:28 PM PDT 24 | May 19 12:49:50 PM PDT 24 | 1795835659 ps | ||
| T457 | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2783010082 | May 19 12:49:09 PM PDT 24 | May 19 12:49:30 PM PDT 24 | 1804823888 ps | ||
| T458 | /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.245561946 | May 19 12:49:09 PM PDT 24 | May 19 12:52:00 PM PDT 24 | 80028632486 ps | ||
| T109 | /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2695228307 | May 19 12:49:25 PM PDT 24 | May 19 12:51:12 PM PDT 24 | 4149333529 ps | ||
| T459 | /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2011162506 | May 19 12:49:26 PM PDT 24 | May 19 12:49:44 PM PDT 24 | 2726954293 ps | ||
| T460 | /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3367992106 | May 19 12:49:39 PM PDT 24 | May 19 12:50:08 PM PDT 24 | 9124059451 ps |
| Test location | /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2892258244 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 69192532241 ps |
| CPU time | 2439.79 seconds |
| Started | May 19 12:49:40 PM PDT 24 |
| Finished | May 19 01:30:23 PM PDT 24 |
| Peak memory | 243996 kb |
| Host | smart-3e29e11d-09b4-4d2b-9b57-b3c493aacdec |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892258244 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.2892258244 |
| Directory | /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.424225400 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 49702004374 ps |
| CPU time | 315.27 seconds |
| Started | May 19 12:49:51 PM PDT 24 |
| Finished | May 19 12:55:10 PM PDT 24 |
| Peak memory | 240788 kb |
| Host | smart-ed172c0b-8e97-4805-9a41-3b9845704e4f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424225400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c orrupt_sig_fatal_chk.424225400 |
| Directory | /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1988177936 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1181786331 ps |
| CPU time | 153.48 seconds |
| Started | May 19 12:49:13 PM PDT 24 |
| Finished | May 19 12:51:48 PM PDT 24 |
| Peak memory | 213444 kb |
| Host | smart-b2b9b0ca-4679-4e47-a60d-5da922724cc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988177936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in tg_err.1988177936 |
| Directory | /workspace/6.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1425309949 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 104541600412 ps |
| CPU time | 9527.1 seconds |
| Started | May 19 12:49:46 PM PDT 24 |
| Finished | May 19 03:28:36 PM PDT 24 |
| Peak memory | 235852 kb |
| Host | smart-b6dd7f63-72f4-4727-a027-e06003ef9aa8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425309949 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1425309949 |
| Directory | /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_sec_cm.3705597032 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1624847371 ps |
| CPU time | 237.22 seconds |
| Started | May 19 12:49:28 PM PDT 24 |
| Finished | May 19 12:53:30 PM PDT 24 |
| Peak memory | 236656 kb |
| Host | smart-ee1bc889-8718-4cc2-8b45-e846b8c5c046 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705597032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3705597032 |
| Directory | /workspace/4.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.966925731 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1969170464 ps |
| CPU time | 22.75 seconds |
| Started | May 19 12:49:49 PM PDT 24 |
| Finished | May 19 12:50:14 PM PDT 24 |
| Peak memory | 212200 kb |
| Host | smart-a553d54a-63c4-48c8-86d1-960b7db655de |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=966925731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.966925731 |
| Directory | /workspace/20.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3675897936 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1335532491 ps |
| CPU time | 88.58 seconds |
| Started | May 19 12:49:24 PM PDT 24 |
| Finished | May 19 12:50:55 PM PDT 24 |
| Peak memory | 218880 kb |
| Host | smart-8f998905-e12d-4331-9337-ec088e085a38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675897936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in tg_err.3675897936 |
| Directory | /workspace/4.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1668561398 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 16294111628 ps |
| CPU time | 30.89 seconds |
| Started | May 19 12:49:18 PM PDT 24 |
| Finished | May 19 12:49:49 PM PDT 24 |
| Peak memory | 211948 kb |
| Host | smart-a2b1d51b-3d0a-4595-9f81-e1e67227910e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668561398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia sing.1668561398 |
| Directory | /workspace/2.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_alert_test.1869056920 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4319194995 ps |
| CPU time | 18.68 seconds |
| Started | May 19 12:49:54 PM PDT 24 |
| Finished | May 19 12:50:15 PM PDT 24 |
| Peak memory | 211392 kb |
| Host | smart-47a8b029-0bcd-453e-a606-c4d556caa705 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869056920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1869056920 |
| Directory | /workspace/26.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3916269493 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 1739038179 ps |
| CPU time | 19.1 seconds |
| Started | May 19 12:49:31 PM PDT 24 |
| Finished | May 19 12:49:55 PM PDT 24 |
| Peak memory | 214772 kb |
| Host | smart-a8c582b4-42f7-423d-beab-5211130200c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3916269493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3916269493 |
| Directory | /workspace/0.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1725155048 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 5843208933 ps |
| CPU time | 54.38 seconds |
| Started | May 19 12:49:33 PM PDT 24 |
| Finished | May 19 12:50:33 PM PDT 24 |
| Peak memory | 214236 kb |
| Host | smart-2cccfb7f-9f0d-41f5-8c04-0a120e8c408b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1725155048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1725155048 |
| Directory | /workspace/7.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.322576270 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 66081033119 ps |
| CPU time | 2410.44 seconds |
| Started | May 19 12:49:34 PM PDT 24 |
| Finished | May 19 01:29:49 PM PDT 24 |
| Peak memory | 243896 kb |
| Host | smart-b407a69b-df7f-466d-8dda-65821a74dcfc |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322576270 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.322576270 |
| Directory | /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_stress_all.487601282 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2831982701 ps |
| CPU time | 24.67 seconds |
| Started | May 19 12:50:05 PM PDT 24 |
| Finished | May 19 12:50:30 PM PDT 24 |
| Peak memory | 212672 kb |
| Host | smart-8afbcc0f-f76c-4e39-9aed-33b958ef8c35 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487601282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 35.rom_ctrl_stress_all.487601282 |
| Directory | /workspace/35.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2162900723 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2148681129 ps |
| CPU time | 93.48 seconds |
| Started | May 19 12:49:14 PM PDT 24 |
| Finished | May 19 12:50:49 PM PDT 24 |
| Peak memory | 213208 kb |
| Host | smart-3955929d-a6c8-4f63-a483-c93da4fcc22a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162900723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in tg_err.2162900723 |
| Directory | /workspace/0.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4158546125 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 994105598 ps |
| CPU time | 80.95 seconds |
| Started | May 19 12:49:26 PM PDT 24 |
| Finished | May 19 12:50:51 PM PDT 24 |
| Peak memory | 211776 kb |
| Host | smart-75d4f408-dfd2-4787-815b-5f8c98e21cf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158546125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i ntg_err.4158546125 |
| Directory | /workspace/15.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.169053884 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 8731017584 ps |
| CPU time | 92.39 seconds |
| Started | May 19 12:49:28 PM PDT 24 |
| Finished | May 19 12:51:04 PM PDT 24 |
| Peak memory | 213536 kb |
| Host | smart-b0ba3229-7aa0-4aa9-b2f5-ae3ce642be7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169053884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in tg_err.169053884 |
| Directory | /workspace/19.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3487496665 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 7905711162 ps |
| CPU time | 30.52 seconds |
| Started | May 19 12:49:12 PM PDT 24 |
| Finished | May 19 12:49:43 PM PDT 24 |
| Peak memory | 212224 kb |
| Host | smart-38dda498-cfe9-451f-81ea-2eee44692f1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487496665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c trl_same_csr_outstanding.3487496665 |
| Directory | /workspace/0.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2796509033 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 44328043918 ps |
| CPU time | 1669.6 seconds |
| Started | May 19 12:49:38 PM PDT 24 |
| Finished | May 19 01:17:31 PM PDT 24 |
| Peak memory | 236536 kb |
| Host | smart-6e8e6af0-4ff6-4d28-9d64-c1a6906449be |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796509033 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2796509033 |
| Directory | /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3081432498 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 10111907193 ps |
| CPU time | 24.89 seconds |
| Started | May 19 12:49:19 PM PDT 24 |
| Finished | May 19 12:49:45 PM PDT 24 |
| Peak memory | 211504 kb |
| Host | smart-c4b3c31c-840d-4c0e-9133-3398cc326089 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081432498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia sing.3081432498 |
| Directory | /workspace/0.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.866102079 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 7256273519 ps |
| CPU time | 20.97 seconds |
| Started | May 19 12:49:28 PM PDT 24 |
| Finished | May 19 12:49:53 PM PDT 24 |
| Peak memory | 218972 kb |
| Host | smart-0f5f9a18-b604-404f-9622-2c6cb73cfc5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866102079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b ash.866102079 |
| Directory | /workspace/0.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.548622341 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 180785407 ps |
| CPU time | 15.93 seconds |
| Started | May 19 12:49:21 PM PDT 24 |
| Finished | May 19 12:49:39 PM PDT 24 |
| Peak memory | 211328 kb |
| Host | smart-19079d6f-f158-4fb3-ba00-268452f67786 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548622341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re set.548622341 |
| Directory | /workspace/0.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2715842861 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 172467792 ps |
| CPU time | 8.62 seconds |
| Started | May 19 12:49:06 PM PDT 24 |
| Finished | May 19 12:49:16 PM PDT 24 |
| Peak memory | 213736 kb |
| Host | smart-3ca97799-f0d8-4706-9fe7-76640702f8a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715842861 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2715842861 |
| Directory | /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3663808931 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 24370625080 ps |
| CPU time | 31.8 seconds |
| Started | May 19 12:49:24 PM PDT 24 |
| Finished | May 19 12:49:58 PM PDT 24 |
| Peak memory | 211432 kb |
| Host | smart-3220e151-2325-49fc-9ffd-88348949b7c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663808931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3663808931 |
| Directory | /workspace/0.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1021927015 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 688981397 ps |
| CPU time | 8.17 seconds |
| Started | May 19 12:49:22 PM PDT 24 |
| Finished | May 19 12:49:33 PM PDT 24 |
| Peak memory | 210624 kb |
| Host | smart-b7487196-4edb-46a3-b8c9-3126f50dc5d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021927015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr l_mem_partial_access.1021927015 |
| Directory | /workspace/0.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.687589202 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 2625524259 ps |
| CPU time | 24.61 seconds |
| Started | May 19 12:49:12 PM PDT 24 |
| Finished | May 19 12:49:38 PM PDT 24 |
| Peak memory | 210772 kb |
| Host | smart-8faa1a9a-e4e1-49e6-b3e7-48115583b825 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687589202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk. 687589202 |
| Directory | /workspace/0.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.558187025 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 4289793692 ps |
| CPU time | 55.92 seconds |
| Started | May 19 12:49:15 PM PDT 24 |
| Finished | May 19 12:50:12 PM PDT 24 |
| Peak memory | 215188 kb |
| Host | smart-74404d65-1fdd-4931-9a9e-362bacf08638 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558187025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas sthru_mem_tl_intg_err.558187025 |
| Directory | /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2061288677 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 496571041 ps |
| CPU time | 15.42 seconds |
| Started | May 19 12:49:08 PM PDT 24 |
| Finished | May 19 12:49:24 PM PDT 24 |
| Peak memory | 218992 kb |
| Host | smart-be895354-544e-437b-87fd-12440583f7a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061288677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2061288677 |
| Directory | /workspace/0.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1983840610 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 16752448145 ps |
| CPU time | 30.92 seconds |
| Started | May 19 12:49:17 PM PDT 24 |
| Finished | May 19 12:49:49 PM PDT 24 |
| Peak memory | 211512 kb |
| Host | smart-a812e241-5fa4-4f55-b4c5-31bf9563caa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983840610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia sing.1983840610 |
| Directory | /workspace/1.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2601290720 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 688992666 ps |
| CPU time | 8.71 seconds |
| Started | May 19 12:49:18 PM PDT 24 |
| Finished | May 19 12:49:27 PM PDT 24 |
| Peak memory | 210720 kb |
| Host | smart-c267783a-3e7d-4930-b278-190c2f2ffa9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601290720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_ bash.2601290720 |
| Directory | /workspace/1.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.839100539 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 4433000617 ps |
| CPU time | 31.38 seconds |
| Started | May 19 12:49:20 PM PDT 24 |
| Finished | May 19 12:50:00 PM PDT 24 |
| Peak memory | 211576 kb |
| Host | smart-b657c6a5-0ae9-442d-88e6-947c16d7ff58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839100539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re set.839100539 |
| Directory | /workspace/1.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2088267449 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 3606383074 ps |
| CPU time | 19.91 seconds |
| Started | May 19 12:49:23 PM PDT 24 |
| Finished | May 19 12:49:45 PM PDT 24 |
| Peak memory | 219020 kb |
| Host | smart-de7229a3-580f-4958-ab95-b75a66fdf6a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088267449 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2088267449 |
| Directory | /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2783010082 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1804823888 ps |
| CPU time | 19.8 seconds |
| Started | May 19 12:49:09 PM PDT 24 |
| Finished | May 19 12:49:30 PM PDT 24 |
| Peak memory | 211260 kb |
| Host | smart-c48ca140-bb58-4497-a3cd-261972c49fe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783010082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2783010082 |
| Directory | /workspace/1.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2435541897 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 3752432043 ps |
| CPU time | 21.43 seconds |
| Started | May 19 12:49:33 PM PDT 24 |
| Finished | May 19 12:50:00 PM PDT 24 |
| Peak memory | 210788 kb |
| Host | smart-b5a22478-ddbb-4a16-b02d-c83eedbcca33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435541897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr l_mem_partial_access.2435541897 |
| Directory | /workspace/1.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3375229747 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 6150203023 ps |
| CPU time | 31.94 seconds |
| Started | May 19 12:49:10 PM PDT 24 |
| Finished | May 19 12:49:43 PM PDT 24 |
| Peak memory | 210728 kb |
| Host | smart-2ab01958-5373-4dc6-968e-c6715ca4dfc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375229747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk .3375229747 |
| Directory | /workspace/1.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3141666050 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 16095986141 ps |
| CPU time | 127.09 seconds |
| Started | May 19 12:49:14 PM PDT 24 |
| Finished | May 19 12:51:22 PM PDT 24 |
| Peak memory | 213904 kb |
| Host | smart-6c2a1ae2-bdcc-4bae-9cba-3318f6b66a3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141666050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa ssthru_mem_tl_intg_err.3141666050 |
| Directory | /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3006223601 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 9933746334 ps |
| CPU time | 23.01 seconds |
| Started | May 19 12:49:18 PM PDT 24 |
| Finished | May 19 12:49:42 PM PDT 24 |
| Peak memory | 212176 kb |
| Host | smart-96783c5c-80b3-4a54-8a03-88248def0fe2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006223601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c trl_same_csr_outstanding.3006223601 |
| Directory | /workspace/1.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2480079676 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 21165679825 ps |
| CPU time | 25.54 seconds |
| Started | May 19 12:49:07 PM PDT 24 |
| Finished | May 19 12:49:33 PM PDT 24 |
| Peak memory | 219100 kb |
| Host | smart-7581b149-0af0-4e5e-b9fd-8d68011f7675 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480079676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2480079676 |
| Directory | /workspace/1.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.397704825 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 3214015302 ps |
| CPU time | 80.56 seconds |
| Started | May 19 12:49:24 PM PDT 24 |
| Finished | May 19 12:50:48 PM PDT 24 |
| Peak memory | 213376 kb |
| Host | smart-6bd56a3d-ab59-4ab2-be37-630477077e4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397704825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int g_err.397704825 |
| Directory | /workspace/1.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3626624071 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1285104327 ps |
| CPU time | 16.42 seconds |
| Started | May 19 12:49:29 PM PDT 24 |
| Finished | May 19 12:49:50 PM PDT 24 |
| Peak memory | 215560 kb |
| Host | smart-aa7ff38e-bda7-4f2f-bb3d-76bead5573bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626624071 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3626624071 |
| Directory | /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1491116496 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 5953994743 ps |
| CPU time | 28.54 seconds |
| Started | May 19 12:49:26 PM PDT 24 |
| Finished | May 19 12:49:58 PM PDT 24 |
| Peak memory | 211464 kb |
| Host | smart-ecb759fa-420a-4d82-855e-5dfcb06af0c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491116496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1491116496 |
| Directory | /workspace/10.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1533371106 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 29661199243 ps |
| CPU time | 105.77 seconds |
| Started | May 19 12:49:19 PM PDT 24 |
| Finished | May 19 12:51:06 PM PDT 24 |
| Peak memory | 219036 kb |
| Host | smart-4471e879-dd91-48cb-a78b-de5f96eff961 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533371106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p assthru_mem_tl_intg_err.1533371106 |
| Directory | /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3977190851 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2743151303 ps |
| CPU time | 20.86 seconds |
| Started | May 19 12:49:25 PM PDT 24 |
| Finished | May 19 12:49:48 PM PDT 24 |
| Peak memory | 212040 kb |
| Host | smart-21162e1b-84d1-4e4a-a826-23aac3949223 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977190851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ ctrl_same_csr_outstanding.3977190851 |
| Directory | /workspace/10.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2379227467 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 10449576744 ps |
| CPU time | 29.88 seconds |
| Started | May 19 12:49:22 PM PDT 24 |
| Finished | May 19 12:49:54 PM PDT 24 |
| Peak memory | 217348 kb |
| Host | smart-e40a5c8a-548f-42c4-b614-c829e83a06da |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379227467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2379227467 |
| Directory | /workspace/10.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2528311617 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 10675963712 ps |
| CPU time | 95.16 seconds |
| Started | May 19 12:49:21 PM PDT 24 |
| Finished | May 19 12:50:57 PM PDT 24 |
| Peak memory | 219000 kb |
| Host | smart-285082ff-aa1d-4de7-8d50-237a7e5673a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528311617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i ntg_err.2528311617 |
| Directory | /workspace/10.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3534707786 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 13615551444 ps |
| CPU time | 27.48 seconds |
| Started | May 19 12:49:24 PM PDT 24 |
| Finished | May 19 12:49:54 PM PDT 24 |
| Peak memory | 219000 kb |
| Host | smart-d204b00e-afae-4adf-8507-ac3cc7fe53ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534707786 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3534707786 |
| Directory | /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2892508109 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 9648892454 ps |
| CPU time | 18.92 seconds |
| Started | May 19 12:49:19 PM PDT 24 |
| Finished | May 19 12:49:39 PM PDT 24 |
| Peak memory | 211908 kb |
| Host | smart-bd664e79-a62c-46c4-9949-653b8471480f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892508109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2892508109 |
| Directory | /workspace/11.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1439229966 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 4923319898 ps |
| CPU time | 38.23 seconds |
| Started | May 19 12:49:24 PM PDT 24 |
| Finished | May 19 12:50:06 PM PDT 24 |
| Peak memory | 214184 kb |
| Host | smart-34280768-7b94-4463-958e-cffe5bd15209 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439229966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p assthru_mem_tl_intg_err.1439229966 |
| Directory | /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3542755630 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 4124609681 ps |
| CPU time | 20.77 seconds |
| Started | May 19 12:49:28 PM PDT 24 |
| Finished | May 19 12:49:52 PM PDT 24 |
| Peak memory | 211960 kb |
| Host | smart-83b2c687-53ea-40c0-a783-0db5e161479d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542755630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ ctrl_same_csr_outstanding.3542755630 |
| Directory | /workspace/11.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1494439692 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 7337039503 ps |
| CPU time | 31.42 seconds |
| Started | May 19 12:49:29 PM PDT 24 |
| Finished | May 19 12:50:04 PM PDT 24 |
| Peak memory | 217704 kb |
| Host | smart-58bf0ef7-f80a-4e4c-b983-34fc8bc14b5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494439692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1494439692 |
| Directory | /workspace/11.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2695228307 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 4149333529 ps |
| CPU time | 103.5 seconds |
| Started | May 19 12:49:25 PM PDT 24 |
| Finished | May 19 12:51:12 PM PDT 24 |
| Peak memory | 213264 kb |
| Host | smart-95868f5e-1c42-45fb-a1a3-c0f368c6de4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695228307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i ntg_err.2695228307 |
| Directory | /workspace/11.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1020119392 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 350968791 ps |
| CPU time | 8.69 seconds |
| Started | May 19 12:49:27 PM PDT 24 |
| Finished | May 19 12:49:40 PM PDT 24 |
| Peak memory | 216064 kb |
| Host | smart-fa6ef822-0978-4408-bbd5-2eb17daf64fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020119392 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1020119392 |
| Directory | /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3480362218 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 14702119801 ps |
| CPU time | 28.69 seconds |
| Started | May 19 12:49:22 PM PDT 24 |
| Finished | May 19 12:49:54 PM PDT 24 |
| Peak memory | 211548 kb |
| Host | smart-9fabda6b-5afc-4a18-93db-91254294cdd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480362218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3480362218 |
| Directory | /workspace/12.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3433129605 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 119094218935 ps |
| CPU time | 193.7 seconds |
| Started | May 19 12:49:25 PM PDT 24 |
| Finished | May 19 12:52:42 PM PDT 24 |
| Peak memory | 210848 kb |
| Host | smart-855bd176-1024-496e-95e3-6950d6100bbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433129605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p assthru_mem_tl_intg_err.3433129605 |
| Directory | /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2844749917 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1354760394 ps |
| CPU time | 16.77 seconds |
| Started | May 19 12:49:27 PM PDT 24 |
| Finished | May 19 12:49:48 PM PDT 24 |
| Peak memory | 210824 kb |
| Host | smart-059ffea4-7ff6-488c-b65d-f1328cf9e8c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844749917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ ctrl_same_csr_outstanding.2844749917 |
| Directory | /workspace/12.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3992420348 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 4610800990 ps |
| CPU time | 19.74 seconds |
| Started | May 19 12:49:22 PM PDT 24 |
| Finished | May 19 12:49:43 PM PDT 24 |
| Peak memory | 218468 kb |
| Host | smart-e667a0d0-599c-4d04-a266-e92c9e9b4d3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992420348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3992420348 |
| Directory | /workspace/12.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.572490089 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 21517428248 ps |
| CPU time | 171.05 seconds |
| Started | May 19 12:49:23 PM PDT 24 |
| Finished | May 19 12:52:17 PM PDT 24 |
| Peak memory | 213764 kb |
| Host | smart-8d69b343-9deb-4a8e-acf3-b6ae36fd1bd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572490089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in tg_err.572490089 |
| Directory | /workspace/12.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.4182168394 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1831055595 ps |
| CPU time | 15.37 seconds |
| Started | May 19 12:49:20 PM PDT 24 |
| Finished | May 19 12:49:36 PM PDT 24 |
| Peak memory | 215908 kb |
| Host | smart-ed0bb3ce-6e5a-40d9-aca8-26e8083d2d1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182168394 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.4182168394 |
| Directory | /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.208104888 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 1191316374 ps |
| CPU time | 16.36 seconds |
| Started | May 19 12:49:26 PM PDT 24 |
| Finished | May 19 12:49:46 PM PDT 24 |
| Peak memory | 211060 kb |
| Host | smart-cd7c08f3-c107-4751-a342-92abda667ae3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208104888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.208104888 |
| Directory | /workspace/13.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2301094048 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 82338857234 ps |
| CPU time | 176.67 seconds |
| Started | May 19 12:49:26 PM PDT 24 |
| Finished | May 19 12:52:26 PM PDT 24 |
| Peak memory | 210836 kb |
| Host | smart-5bf7895f-9a6e-40a8-bc87-b39be6c00872 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301094048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p assthru_mem_tl_intg_err.2301094048 |
| Directory | /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.693348630 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 31317691378 ps |
| CPU time | 27.88 seconds |
| Started | May 19 12:49:21 PM PDT 24 |
| Finished | May 19 12:49:51 PM PDT 24 |
| Peak memory | 212072 kb |
| Host | smart-ccfddd7e-c6d6-4c48-bf48-0298ce57b9f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693348630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c trl_same_csr_outstanding.693348630 |
| Directory | /workspace/13.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3381705004 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 12726023256 ps |
| CPU time | 31.57 seconds |
| Started | May 19 12:49:22 PM PDT 24 |
| Finished | May 19 12:49:55 PM PDT 24 |
| Peak memory | 217548 kb |
| Host | smart-18ea2cf2-c4a0-4ed1-a677-a6f7aef82b03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381705004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3381705004 |
| Directory | /workspace/13.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2352615815 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 9091233072 ps |
| CPU time | 91.39 seconds |
| Started | May 19 12:49:24 PM PDT 24 |
| Finished | May 19 12:50:59 PM PDT 24 |
| Peak memory | 213544 kb |
| Host | smart-8c616ad9-d32d-43d1-a7ec-d381367c972c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352615815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i ntg_err.2352615815 |
| Directory | /workspace/13.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4035781287 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 3458744492 ps |
| CPU time | 19.6 seconds |
| Started | May 19 12:49:25 PM PDT 24 |
| Finished | May 19 12:49:48 PM PDT 24 |
| Peak memory | 219020 kb |
| Host | smart-fcc66c15-0c89-45eb-a43f-b7fdb0608dc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035781287 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4035781287 |
| Directory | /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.846316848 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 17062501094 ps |
| CPU time | 23.41 seconds |
| Started | May 19 12:49:25 PM PDT 24 |
| Finished | May 19 12:49:51 PM PDT 24 |
| Peak memory | 211864 kb |
| Host | smart-9beb492c-0b73-44fe-bf30-946bc49fdabe |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846316848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.846316848 |
| Directory | /workspace/14.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3833195237 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 51394540808 ps |
| CPU time | 131.82 seconds |
| Started | May 19 12:49:23 PM PDT 24 |
| Finished | May 19 12:51:38 PM PDT 24 |
| Peak memory | 215036 kb |
| Host | smart-29947aa2-cd76-4b9e-94dd-93837baf0de0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833195237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p assthru_mem_tl_intg_err.3833195237 |
| Directory | /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4216740619 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 3295471943 ps |
| CPU time | 8.4 seconds |
| Started | May 19 12:49:23 PM PDT 24 |
| Finished | May 19 12:49:34 PM PDT 24 |
| Peak memory | 210792 kb |
| Host | smart-d999406f-3245-4b3a-8743-6ded557093a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216740619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ ctrl_same_csr_outstanding.4216740619 |
| Directory | /workspace/14.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.748410354 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 319818357 ps |
| CPU time | 11.18 seconds |
| Started | May 19 12:49:24 PM PDT 24 |
| Finished | May 19 12:49:38 PM PDT 24 |
| Peak memory | 219044 kb |
| Host | smart-89a03c90-4fa2-4f75-8f26-8da608bc64b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748410354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.748410354 |
| Directory | /workspace/14.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.802897164 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 8079616886 ps |
| CPU time | 92.01 seconds |
| Started | May 19 12:49:23 PM PDT 24 |
| Finished | May 19 12:50:57 PM PDT 24 |
| Peak memory | 214224 kb |
| Host | smart-48f02683-a661-466d-93d8-23523a592dc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802897164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in tg_err.802897164 |
| Directory | /workspace/14.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3899353642 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 3941188357 ps |
| CPU time | 20.92 seconds |
| Started | May 19 12:49:21 PM PDT 24 |
| Finished | May 19 12:49:43 PM PDT 24 |
| Peak memory | 219044 kb |
| Host | smart-05e9d79e-0fa1-46dd-9dcf-49e2aadfa49e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899353642 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3899353642 |
| Directory | /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3023301672 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 385607434 ps |
| CPU time | 8.18 seconds |
| Started | May 19 12:49:29 PM PDT 24 |
| Finished | May 19 12:49:42 PM PDT 24 |
| Peak memory | 210760 kb |
| Host | smart-c45bcf1d-d515-4e00-9251-da8f078fad14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023301672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3023301672 |
| Directory | /workspace/15.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.558844547 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 16259052397 ps |
| CPU time | 124.32 seconds |
| Started | May 19 12:49:29 PM PDT 24 |
| Finished | May 19 12:51:37 PM PDT 24 |
| Peak memory | 219032 kb |
| Host | smart-e82a175e-6d1e-4357-8d09-aa77ae8b4909 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558844547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa ssthru_mem_tl_intg_err.558844547 |
| Directory | /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2799951730 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 7008258942 ps |
| CPU time | 23.03 seconds |
| Started | May 19 12:49:27 PM PDT 24 |
| Finished | May 19 12:49:54 PM PDT 24 |
| Peak memory | 212196 kb |
| Host | smart-e01c3d72-6ff1-422f-80f2-76e97aa25391 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799951730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ ctrl_same_csr_outstanding.2799951730 |
| Directory | /workspace/15.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2106639760 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 689180451 ps |
| CPU time | 11.21 seconds |
| Started | May 19 12:49:33 PM PDT 24 |
| Finished | May 19 12:49:49 PM PDT 24 |
| Peak memory | 216620 kb |
| Host | smart-7b51db5b-71d0-4017-8081-bf96c16fabe7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106639760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2106639760 |
| Directory | /workspace/15.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.581434871 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 14477593418 ps |
| CPU time | 29.41 seconds |
| Started | May 19 12:49:27 PM PDT 24 |
| Finished | May 19 12:50:00 PM PDT 24 |
| Peak memory | 217140 kb |
| Host | smart-d8e3073c-4c77-4284-88c9-e627f3c34ec5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581434871 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.581434871 |
| Directory | /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2249212178 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 3839552232 ps |
| CPU time | 30.23 seconds |
| Started | May 19 12:49:28 PM PDT 24 |
| Finished | May 19 12:50:02 PM PDT 24 |
| Peak memory | 211268 kb |
| Host | smart-f02f6303-9df5-4ac5-a29f-3c9805d7f95a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249212178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2249212178 |
| Directory | /workspace/16.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3991515592 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 16921829927 ps |
| CPU time | 159.56 seconds |
| Started | May 19 12:49:28 PM PDT 24 |
| Finished | May 19 12:52:12 PM PDT 24 |
| Peak memory | 215168 kb |
| Host | smart-d3fba06f-5c12-4493-a4bb-c82e5bff644a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991515592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p assthru_mem_tl_intg_err.3991515592 |
| Directory | /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3205008155 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 179142340 ps |
| CPU time | 11.75 seconds |
| Started | May 19 12:49:23 PM PDT 24 |
| Finished | May 19 12:49:37 PM PDT 24 |
| Peak memory | 211980 kb |
| Host | smart-0c3d2e58-e728-42fb-b77f-2dfde04cff14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205008155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ ctrl_same_csr_outstanding.3205008155 |
| Directory | /workspace/16.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2011162506 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 2726954293 ps |
| CPU time | 14.78 seconds |
| Started | May 19 12:49:26 PM PDT 24 |
| Finished | May 19 12:49:44 PM PDT 24 |
| Peak memory | 217156 kb |
| Host | smart-094c8608-d9dd-4d56-8049-309bafe2bcb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011162506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2011162506 |
| Directory | /workspace/16.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3128924288 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 2703208749 ps |
| CPU time | 157.45 seconds |
| Started | May 19 12:49:30 PM PDT 24 |
| Finished | May 19 12:52:13 PM PDT 24 |
| Peak memory | 213700 kb |
| Host | smart-9649e2d4-ecd2-48bb-b889-944bcd6b751d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128924288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i ntg_err.3128924288 |
| Directory | /workspace/16.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2378202033 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 1185636387 ps |
| CPU time | 13.79 seconds |
| Started | May 19 12:49:28 PM PDT 24 |
| Finished | May 19 12:49:46 PM PDT 24 |
| Peak memory | 218904 kb |
| Host | smart-fff1231a-a72b-4a1f-86dd-0ebf797ddf81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378202033 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2378202033 |
| Directory | /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3306565344 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 5882439484 ps |
| CPU time | 25.49 seconds |
| Started | May 19 12:49:32 PM PDT 24 |
| Finished | May 19 12:50:03 PM PDT 24 |
| Peak memory | 212056 kb |
| Host | smart-e3460ff4-c31b-41a1-a468-c511a1c2b162 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306565344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3306565344 |
| Directory | /workspace/17.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.708107011 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 7882041677 ps |
| CPU time | 83.08 seconds |
| Started | May 19 12:49:23 PM PDT 24 |
| Finished | May 19 12:50:49 PM PDT 24 |
| Peak memory | 214904 kb |
| Host | smart-5a122c85-e8d7-430a-a3ca-8f452d2eca2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708107011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa ssthru_mem_tl_intg_err.708107011 |
| Directory | /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2268945168 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 16077013255 ps |
| CPU time | 35.42 seconds |
| Started | May 19 12:49:28 PM PDT 24 |
| Finished | May 19 12:50:07 PM PDT 24 |
| Peak memory | 212320 kb |
| Host | smart-206f977c-e8ef-4222-9012-a42177b3f0b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268945168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ ctrl_same_csr_outstanding.2268945168 |
| Directory | /workspace/17.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.140208452 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 13116617555 ps |
| CPU time | 28.63 seconds |
| Started | May 19 12:49:30 PM PDT 24 |
| Finished | May 19 12:50:04 PM PDT 24 |
| Peak memory | 219076 kb |
| Host | smart-ba606177-8969-4355-8940-4096bc5c41df |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140208452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.140208452 |
| Directory | /workspace/17.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3370518794 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 1231376031 ps |
| CPU time | 79.69 seconds |
| Started | May 19 12:49:37 PM PDT 24 |
| Finished | May 19 12:51:00 PM PDT 24 |
| Peak memory | 212140 kb |
| Host | smart-d3a9b8a8-791b-476b-ab83-c4eb15cd9d70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370518794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i ntg_err.3370518794 |
| Directory | /workspace/17.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2897026344 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 17447202150 ps |
| CPU time | 31.96 seconds |
| Started | May 19 12:49:18 PM PDT 24 |
| Finished | May 19 12:49:51 PM PDT 24 |
| Peak memory | 216556 kb |
| Host | smart-7c03122a-245c-4be6-9961-56e2b6228142 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897026344 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2897026344 |
| Directory | /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3681378789 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 169242801 ps |
| CPU time | 8.3 seconds |
| Started | May 19 12:49:26 PM PDT 24 |
| Finished | May 19 12:49:38 PM PDT 24 |
| Peak memory | 210720 kb |
| Host | smart-3fda83f6-f444-4c91-8924-c2d56f1a19fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681378789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3681378789 |
| Directory | /workspace/18.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.19371584 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 16777958368 ps |
| CPU time | 132.21 seconds |
| Started | May 19 12:49:31 PM PDT 24 |
| Finished | May 19 12:51:49 PM PDT 24 |
| Peak memory | 214308 kb |
| Host | smart-1f8730ef-5374-4f18-8ebb-5179f2b1de36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19371584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pas sthru_mem_tl_intg_err.19371584 |
| Directory | /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1169221951 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3907326541 ps |
| CPU time | 30.9 seconds |
| Started | May 19 12:49:36 PM PDT 24 |
| Finished | May 19 12:50:11 PM PDT 24 |
| Peak memory | 211744 kb |
| Host | smart-080c4fad-6cce-4dec-8f6f-e8ebbdb2be6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169221951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ ctrl_same_csr_outstanding.1169221951 |
| Directory | /workspace/18.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1084853349 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1647692176 ps |
| CPU time | 22.28 seconds |
| Started | May 19 12:49:32 PM PDT 24 |
| Finished | May 19 12:49:59 PM PDT 24 |
| Peak memory | 219120 kb |
| Host | smart-88905915-4a25-43f5-8ef3-86e0a5112c21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084853349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1084853349 |
| Directory | /workspace/18.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3835189844 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 7202493080 ps |
| CPU time | 90.52 seconds |
| Started | May 19 12:49:23 PM PDT 24 |
| Finished | May 19 12:50:56 PM PDT 24 |
| Peak memory | 213080 kb |
| Host | smart-c69b75d9-56fa-4de1-90bd-0790c87624e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835189844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i ntg_err.3835189844 |
| Directory | /workspace/18.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.369739302 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 363543420 ps |
| CPU time | 8.76 seconds |
| Started | May 19 12:49:41 PM PDT 24 |
| Finished | May 19 12:49:53 PM PDT 24 |
| Peak memory | 219112 kb |
| Host | smart-4cd0d2b3-f8f0-4c3e-ab94-02dbf7676372 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369739302 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.369739302 |
| Directory | /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2457487845 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 20457007671 ps |
| CPU time | 22.36 seconds |
| Started | May 19 12:49:24 PM PDT 24 |
| Finished | May 19 12:49:49 PM PDT 24 |
| Peak memory | 211672 kb |
| Host | smart-58ad8001-51e1-449b-999c-be145c395a6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457487845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2457487845 |
| Directory | /workspace/19.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1915427970 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 6397279282 ps |
| CPU time | 75.67 seconds |
| Started | May 19 12:49:28 PM PDT 24 |
| Finished | May 19 12:50:48 PM PDT 24 |
| Peak memory | 214268 kb |
| Host | smart-2e1d0e74-bb49-43d7-8920-73cafe1adca2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915427970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p assthru_mem_tl_intg_err.1915427970 |
| Directory | /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3367992106 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 9124059451 ps |
| CPU time | 26.19 seconds |
| Started | May 19 12:49:39 PM PDT 24 |
| Finished | May 19 12:50:08 PM PDT 24 |
| Peak memory | 212172 kb |
| Host | smart-b06f2af2-8dcb-4ab6-86bb-38e179d40dc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367992106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ ctrl_same_csr_outstanding.3367992106 |
| Directory | /workspace/19.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4002729746 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 11868267191 ps |
| CPU time | 34.05 seconds |
| Started | May 19 12:49:24 PM PDT 24 |
| Finished | May 19 12:50:00 PM PDT 24 |
| Peak memory | 218236 kb |
| Host | smart-3e07e376-9b9e-4b75-90fa-e7bcbd6fe8ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002729746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.4002729746 |
| Directory | /workspace/19.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3187486527 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 346138384 ps |
| CPU time | 9.03 seconds |
| Started | May 19 12:49:24 PM PDT 24 |
| Finished | May 19 12:49:36 PM PDT 24 |
| Peak memory | 210728 kb |
| Host | smart-d5aa7c19-25c2-42c0-897f-294e928fdfed |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187486527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_ bash.3187486527 |
| Directory | /workspace/2.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.821416864 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 7474632893 ps |
| CPU time | 34.05 seconds |
| Started | May 19 12:49:17 PM PDT 24 |
| Finished | May 19 12:49:52 PM PDT 24 |
| Peak memory | 211896 kb |
| Host | smart-7e17fec8-000f-4b6a-9bb2-e4e94caee245 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821416864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re set.821416864 |
| Directory | /workspace/2.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2853736108 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 6107187682 ps |
| CPU time | 17.14 seconds |
| Started | May 19 12:49:20 PM PDT 24 |
| Finished | May 19 12:49:38 PM PDT 24 |
| Peak memory | 216172 kb |
| Host | smart-6cd5ef67-8668-40f4-966d-1da5f808391a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853736108 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2853736108 |
| Directory | /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3596682648 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1650361797 ps |
| CPU time | 18.92 seconds |
| Started | May 19 12:49:19 PM PDT 24 |
| Finished | May 19 12:49:40 PM PDT 24 |
| Peak memory | 211252 kb |
| Host | smart-617ea6af-b969-45d9-b2ad-70bb8f763f71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596682648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3596682648 |
| Directory | /workspace/2.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.710683246 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 4349522601 ps |
| CPU time | 21.33 seconds |
| Started | May 19 12:49:25 PM PDT 24 |
| Finished | May 19 12:49:49 PM PDT 24 |
| Peak memory | 210656 kb |
| Host | smart-f82c1c20-388d-4876-8ad5-3568bcb0a9d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710683246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl _mem_partial_access.710683246 |
| Directory | /workspace/2.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4029687363 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 3322809727 ps |
| CPU time | 27.92 seconds |
| Started | May 19 12:49:19 PM PDT 24 |
| Finished | May 19 12:49:48 PM PDT 24 |
| Peak memory | 210720 kb |
| Host | smart-641a2895-475f-4415-9991-456da7731d5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029687363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk .4029687363 |
| Directory | /workspace/2.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1927733457 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 24174087126 ps |
| CPU time | 63.37 seconds |
| Started | May 19 12:49:12 PM PDT 24 |
| Finished | May 19 12:50:17 PM PDT 24 |
| Peak memory | 213880 kb |
| Host | smart-ac8ee722-cb64-4208-919e-a50bee945b4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927733457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa ssthru_mem_tl_intg_err.1927733457 |
| Directory | /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2947380075 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 3939185254 ps |
| CPU time | 20.57 seconds |
| Started | May 19 12:49:11 PM PDT 24 |
| Finished | May 19 12:49:33 PM PDT 24 |
| Peak memory | 211944 kb |
| Host | smart-b9041b37-057d-49e6-ad9e-8d3342390024 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947380075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c trl_same_csr_outstanding.2947380075 |
| Directory | /workspace/2.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1162402213 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 170990940 ps |
| CPU time | 12.21 seconds |
| Started | May 19 12:49:17 PM PDT 24 |
| Finished | May 19 12:49:30 PM PDT 24 |
| Peak memory | 219020 kb |
| Host | smart-b6d2e5de-2288-423f-b7b8-ff3f0e6317b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162402213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1162402213 |
| Directory | /workspace/2.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1731999497 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 48305137241 ps |
| CPU time | 175.86 seconds |
| Started | May 19 12:49:20 PM PDT 24 |
| Finished | May 19 12:52:18 PM PDT 24 |
| Peak memory | 218968 kb |
| Host | smart-ffdbc8ad-aead-4600-8f41-f0189f21d9cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731999497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in tg_err.1731999497 |
| Directory | /workspace/2.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1927189692 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 18167709852 ps |
| CPU time | 29.04 seconds |
| Started | May 19 12:49:18 PM PDT 24 |
| Finished | May 19 12:49:49 PM PDT 24 |
| Peak memory | 211644 kb |
| Host | smart-6cba058b-f5d9-44c0-8c18-f3fe732ab440 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927189692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia sing.1927189692 |
| Directory | /workspace/3.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3250283057 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 3112440132 ps |
| CPU time | 27.78 seconds |
| Started | May 19 12:49:23 PM PDT 24 |
| Finished | May 19 12:49:53 PM PDT 24 |
| Peak memory | 218968 kb |
| Host | smart-ccf8d93f-9e86-4717-bc7b-3ea0530dbe65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250283057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_ bash.3250283057 |
| Directory | /workspace/3.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2832972553 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 640779338 ps |
| CPU time | 15.45 seconds |
| Started | May 19 12:49:22 PM PDT 24 |
| Finished | May 19 12:49:39 PM PDT 24 |
| Peak memory | 211268 kb |
| Host | smart-083f6bf8-b3fa-4ae7-baa7-2d9b64f3a2df |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832972553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r eset.2832972553 |
| Directory | /workspace/3.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2241032765 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 13760839491 ps |
| CPU time | 27.02 seconds |
| Started | May 19 12:49:13 PM PDT 24 |
| Finished | May 19 12:49:41 PM PDT 24 |
| Peak memory | 219052 kb |
| Host | smart-6ada854b-fda2-4782-99c0-a6143ac2c13e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241032765 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2241032765 |
| Directory | /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1438351442 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 3322815577 ps |
| CPU time | 27.06 seconds |
| Started | May 19 12:49:22 PM PDT 24 |
| Finished | May 19 12:49:51 PM PDT 24 |
| Peak memory | 210784 kb |
| Host | smart-b1130beb-b400-4221-88e6-949d154924e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438351442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1438351442 |
| Directory | /workspace/3.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.688883963 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 2224618111 ps |
| CPU time | 20.92 seconds |
| Started | May 19 12:49:21 PM PDT 24 |
| Finished | May 19 12:49:44 PM PDT 24 |
| Peak memory | 210708 kb |
| Host | smart-8ebc85d1-3e94-4969-9267-cc6004350ba6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688883963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl _mem_partial_access.688883963 |
| Directory | /workspace/3.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.914792421 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 21344673145 ps |
| CPU time | 20.53 seconds |
| Started | May 19 12:49:27 PM PDT 24 |
| Finished | May 19 12:49:52 PM PDT 24 |
| Peak memory | 210776 kb |
| Host | smart-d353d327-9772-4e8f-a469-e32dd20a7462 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914792421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk. 914792421 |
| Directory | /workspace/3.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2754181233 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 70908361302 ps |
| CPU time | 90.64 seconds |
| Started | May 19 12:49:15 PM PDT 24 |
| Finished | May 19 12:50:47 PM PDT 24 |
| Peak memory | 215032 kb |
| Host | smart-4631d7d3-cbbf-4f4a-9758-a2a2be38b230 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754181233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa ssthru_mem_tl_intg_err.2754181233 |
| Directory | /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1097628836 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 5377926563 ps |
| CPU time | 27.7 seconds |
| Started | May 19 12:49:25 PM PDT 24 |
| Finished | May 19 12:49:56 PM PDT 24 |
| Peak memory | 212292 kb |
| Host | smart-cd3308a6-936d-402b-8543-5ce096f4775f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097628836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c trl_same_csr_outstanding.1097628836 |
| Directory | /workspace/3.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2410238744 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 14787755304 ps |
| CPU time | 36.03 seconds |
| Started | May 19 12:49:25 PM PDT 24 |
| Finished | May 19 12:50:05 PM PDT 24 |
| Peak memory | 218464 kb |
| Host | smart-bcd71808-c6ea-461e-a0f7-3026fb1de851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410238744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2410238744 |
| Directory | /workspace/3.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3690121453 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 2922500858 ps |
| CPU time | 97.04 seconds |
| Started | May 19 12:49:28 PM PDT 24 |
| Finished | May 19 12:51:09 PM PDT 24 |
| Peak memory | 213236 kb |
| Host | smart-d3ce600f-bf89-472c-9e3a-9873879a7922 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690121453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in tg_err.3690121453 |
| Directory | /workspace/3.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.939425359 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 2303400236 ps |
| CPU time | 15.25 seconds |
| Started | May 19 12:49:23 PM PDT 24 |
| Finished | May 19 12:49:41 PM PDT 24 |
| Peak memory | 211084 kb |
| Host | smart-ff4a19bf-ba5b-4a3d-a2d3-801e1f11df03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939425359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias ing.939425359 |
| Directory | /workspace/4.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2360803256 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1647525513 ps |
| CPU time | 8.26 seconds |
| Started | May 19 12:49:21 PM PDT 24 |
| Finished | May 19 12:49:32 PM PDT 24 |
| Peak memory | 209336 kb |
| Host | smart-a0cffe7e-5b14-4e5d-9170-fa07004caf16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360803256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_ bash.2360803256 |
| Directory | /workspace/4.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2695524338 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1515598329 ps |
| CPU time | 17.28 seconds |
| Started | May 19 12:49:27 PM PDT 24 |
| Finished | May 19 12:49:48 PM PDT 24 |
| Peak memory | 211688 kb |
| Host | smart-b8123a17-3459-4fff-8b85-872513656e13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695524338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r eset.2695524338 |
| Directory | /workspace/4.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.182219731 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 4445920832 ps |
| CPU time | 32.98 seconds |
| Started | May 19 12:49:25 PM PDT 24 |
| Finished | May 19 12:50:01 PM PDT 24 |
| Peak memory | 219080 kb |
| Host | smart-1ea53a00-1201-4985-9f6e-c38702eab6db |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182219731 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.182219731 |
| Directory | /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1374611538 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 3613540801 ps |
| CPU time | 27.4 seconds |
| Started | May 19 12:49:13 PM PDT 24 |
| Finished | May 19 12:49:42 PM PDT 24 |
| Peak memory | 211272 kb |
| Host | smart-3070594c-cf90-48ed-bd4c-f34acdd6625e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374611538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1374611538 |
| Directory | /workspace/4.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1502421926 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 3655236682 ps |
| CPU time | 29.11 seconds |
| Started | May 19 12:49:21 PM PDT 24 |
| Finished | May 19 12:49:51 PM PDT 24 |
| Peak memory | 210716 kb |
| Host | smart-e2723a76-5483-4f09-b9e6-e33e759a3883 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502421926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr l_mem_partial_access.1502421926 |
| Directory | /workspace/4.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1229318088 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1505880386 ps |
| CPU time | 16.9 seconds |
| Started | May 19 12:49:21 PM PDT 24 |
| Finished | May 19 12:49:39 PM PDT 24 |
| Peak memory | 210680 kb |
| Host | smart-66a5a2b2-38e2-45a1-90d3-b35d9db3c9d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229318088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk .1229318088 |
| Directory | /workspace/4.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3998056258 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 16115477478 ps |
| CPU time | 130.95 seconds |
| Started | May 19 12:49:25 PM PDT 24 |
| Finished | May 19 12:51:39 PM PDT 24 |
| Peak memory | 214060 kb |
| Host | smart-c2b57565-95fe-4ec1-9c8d-2d06a88237d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998056258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa ssthru_mem_tl_intg_err.3998056258 |
| Directory | /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.817788532 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 8343600967 ps |
| CPU time | 31.3 seconds |
| Started | May 19 12:49:21 PM PDT 24 |
| Finished | May 19 12:49:55 PM PDT 24 |
| Peak memory | 210432 kb |
| Host | smart-1e8a6894-e7e1-49e4-a4e4-89b483c88663 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817788532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct rl_same_csr_outstanding.817788532 |
| Directory | /workspace/4.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2455583191 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 867915578 ps |
| CPU time | 11.36 seconds |
| Started | May 19 12:49:18 PM PDT 24 |
| Finished | May 19 12:49:30 PM PDT 24 |
| Peak memory | 218976 kb |
| Host | smart-2736f248-5500-4f1c-bb1b-05806d112e63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455583191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2455583191 |
| Directory | /workspace/4.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.232168194 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 16121725871 ps |
| CPU time | 31.49 seconds |
| Started | May 19 12:49:17 PM PDT 24 |
| Finished | May 19 12:49:49 PM PDT 24 |
| Peak memory | 217012 kb |
| Host | smart-84185e05-2a87-4365-82fe-f23332307478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232168194 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.232168194 |
| Directory | /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2972616356 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 3554292024 ps |
| CPU time | 28.08 seconds |
| Started | May 19 12:49:10 PM PDT 24 |
| Finished | May 19 12:49:39 PM PDT 24 |
| Peak memory | 211236 kb |
| Host | smart-a5ae14fd-b6d9-43e1-96eb-9ad7e98700b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972616356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2972616356 |
| Directory | /workspace/5.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.245561946 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 80028632486 ps |
| CPU time | 169.51 seconds |
| Started | May 19 12:49:09 PM PDT 24 |
| Finished | May 19 12:52:00 PM PDT 24 |
| Peak memory | 214540 kb |
| Host | smart-5eb9854a-2f3f-4f2b-a2d0-e7dc9db448f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245561946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas sthru_mem_tl_intg_err.245561946 |
| Directory | /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.982755778 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 5732082141 ps |
| CPU time | 23.35 seconds |
| Started | May 19 12:49:19 PM PDT 24 |
| Finished | May 19 12:49:43 PM PDT 24 |
| Peak memory | 211824 kb |
| Host | smart-966d7a8a-fbb8-47a5-bfab-63df9f8fd968 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982755778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct rl_same_csr_outstanding.982755778 |
| Directory | /workspace/5.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4286719515 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 13776205040 ps |
| CPU time | 23.67 seconds |
| Started | May 19 12:49:25 PM PDT 24 |
| Finished | May 19 12:49:52 PM PDT 24 |
| Peak memory | 218860 kb |
| Host | smart-d577f9ee-99f7-4209-b140-9a5a661ce33d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286719515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.4286719515 |
| Directory | /workspace/5.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3252897527 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 21475139329 ps |
| CPU time | 97.87 seconds |
| Started | May 19 12:49:19 PM PDT 24 |
| Finished | May 19 12:50:58 PM PDT 24 |
| Peak memory | 213136 kb |
| Host | smart-58111682-b8e2-4aee-aa98-0908252b3e83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252897527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in tg_err.3252897527 |
| Directory | /workspace/5.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1334867978 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 2037451213 ps |
| CPU time | 16.23 seconds |
| Started | May 19 12:49:23 PM PDT 24 |
| Finished | May 19 12:49:42 PM PDT 24 |
| Peak memory | 217272 kb |
| Host | smart-25821698-bba0-4b5c-b942-6eb19051e7b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334867978 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1334867978 |
| Directory | /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2214170299 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 169179974 ps |
| CPU time | 8.19 seconds |
| Started | May 19 12:49:20 PM PDT 24 |
| Finished | May 19 12:49:30 PM PDT 24 |
| Peak memory | 210712 kb |
| Host | smart-c83a6b09-e8a7-4651-a6cb-52a640514c9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214170299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2214170299 |
| Directory | /workspace/6.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3892656410 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 51393795885 ps |
| CPU time | 207.27 seconds |
| Started | May 19 12:49:19 PM PDT 24 |
| Finished | May 19 12:52:47 PM PDT 24 |
| Peak memory | 214912 kb |
| Host | smart-9755543a-ab61-4297-86c2-ea4d833aafd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892656410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa ssthru_mem_tl_intg_err.3892656410 |
| Directory | /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.749677842 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 40366294592 ps |
| CPU time | 22.57 seconds |
| Started | May 19 12:49:28 PM PDT 24 |
| Finished | May 19 12:49:55 PM PDT 24 |
| Peak memory | 212288 kb |
| Host | smart-3dd16da3-9930-4387-b140-6e476e812ee1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749677842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct rl_same_csr_outstanding.749677842 |
| Directory | /workspace/6.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3904673108 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 2458288656 ps |
| CPU time | 24.91 seconds |
| Started | May 19 12:49:14 PM PDT 24 |
| Finished | May 19 12:49:40 PM PDT 24 |
| Peak memory | 218084 kb |
| Host | smart-81dbf8e0-7f49-4f9d-8f5e-d9df7ee41580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904673108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3904673108 |
| Directory | /workspace/6.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.821494859 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 193089381 ps |
| CPU time | 8.79 seconds |
| Started | May 19 12:49:28 PM PDT 24 |
| Finished | May 19 12:49:41 PM PDT 24 |
| Peak memory | 219000 kb |
| Host | smart-d86db8cd-73b5-4644-87a1-d098d53d06f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821494859 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.821494859 |
| Directory | /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2039851392 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 3621590122 ps |
| CPU time | 29.5 seconds |
| Started | May 19 12:49:31 PM PDT 24 |
| Finished | May 19 12:50:05 PM PDT 24 |
| Peak memory | 211216 kb |
| Host | smart-628c4ae2-4c01-497c-85b3-2830added941 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039851392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2039851392 |
| Directory | /workspace/7.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2010029214 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 15415268316 ps |
| CPU time | 148.65 seconds |
| Started | May 19 12:49:21 PM PDT 24 |
| Finished | May 19 12:51:51 PM PDT 24 |
| Peak memory | 210964 kb |
| Host | smart-48b991ce-1913-48de-b997-9a7a987ca9f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010029214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa ssthru_mem_tl_intg_err.2010029214 |
| Directory | /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1635276362 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 9384716752 ps |
| CPU time | 17.05 seconds |
| Started | May 19 12:49:27 PM PDT 24 |
| Finished | May 19 12:49:48 PM PDT 24 |
| Peak memory | 212228 kb |
| Host | smart-001ec112-3861-4aea-8279-bdcc4ff58e89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635276362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c trl_same_csr_outstanding.1635276362 |
| Directory | /workspace/7.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.952266696 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 174159757 ps |
| CPU time | 13.23 seconds |
| Started | May 19 12:49:22 PM PDT 24 |
| Finished | May 19 12:49:37 PM PDT 24 |
| Peak memory | 217260 kb |
| Host | smart-1c4bd119-afad-4c6e-9540-90ee971df4db |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952266696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.952266696 |
| Directory | /workspace/7.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1247319743 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 620310797 ps |
| CPU time | 160.09 seconds |
| Started | May 19 12:49:25 PM PDT 24 |
| Finished | May 19 12:52:08 PM PDT 24 |
| Peak memory | 213336 kb |
| Host | smart-80a2392c-59bf-4b80-aeaf-a55f82c9f983 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247319743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in tg_err.1247319743 |
| Directory | /workspace/7.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3723392656 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 2221329501 ps |
| CPU time | 21.69 seconds |
| Started | May 19 12:49:19 PM PDT 24 |
| Finished | May 19 12:49:42 PM PDT 24 |
| Peak memory | 216012 kb |
| Host | smart-fc0bd228-d7ff-4104-a43f-359641d2a285 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723392656 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3723392656 |
| Directory | /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1999377157 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1498812434 ps |
| CPU time | 8.18 seconds |
| Started | May 19 12:49:29 PM PDT 24 |
| Finished | May 19 12:49:41 PM PDT 24 |
| Peak memory | 210728 kb |
| Host | smart-8c45fd01-5e9a-4050-a1ee-fedeaf4ec68f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999377157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1999377157 |
| Directory | /workspace/8.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.747046838 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 12830925061 ps |
| CPU time | 131.17 seconds |
| Started | May 19 12:49:30 PM PDT 24 |
| Finished | May 19 12:51:45 PM PDT 24 |
| Peak memory | 215160 kb |
| Host | smart-7ebc3fbb-0168-42a6-b6bf-706292b06b7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747046838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas sthru_mem_tl_intg_err.747046838 |
| Directory | /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4290721288 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 24657615377 ps |
| CPU time | 24.82 seconds |
| Started | May 19 12:49:25 PM PDT 24 |
| Finished | May 19 12:49:53 PM PDT 24 |
| Peak memory | 212012 kb |
| Host | smart-1c56b6d9-e7f9-4de2-a867-0996f8f74d2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290721288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c trl_same_csr_outstanding.4290721288 |
| Directory | /workspace/8.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2072551357 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 14006327123 ps |
| CPU time | 21.31 seconds |
| Started | May 19 12:49:25 PM PDT 24 |
| Finished | May 19 12:49:50 PM PDT 24 |
| Peak memory | 217552 kb |
| Host | smart-101f129a-e477-4d48-a56f-539d1d1880a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072551357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2072551357 |
| Directory | /workspace/8.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2248969961 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 4458242902 ps |
| CPU time | 164.88 seconds |
| Started | May 19 12:49:18 PM PDT 24 |
| Finished | May 19 12:52:04 PM PDT 24 |
| Peak memory | 213644 kb |
| Host | smart-9ae34aa7-7b28-44b1-87e4-ee534f86a3b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248969961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in tg_err.2248969961 |
| Directory | /workspace/8.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3421291979 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 21799184783 ps |
| CPU time | 22.3 seconds |
| Started | May 19 12:49:30 PM PDT 24 |
| Finished | May 19 12:49:57 PM PDT 24 |
| Peak memory | 217436 kb |
| Host | smart-dbc99418-0b55-47ad-9bcf-eb97c0479766 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421291979 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3421291979 |
| Directory | /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2384924386 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 689596065 ps |
| CPU time | 8.27 seconds |
| Started | May 19 12:49:23 PM PDT 24 |
| Finished | May 19 12:49:34 PM PDT 24 |
| Peak memory | 210752 kb |
| Host | smart-670dafbd-1170-40b8-a7dc-a3ecf8e88477 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384924386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2384924386 |
| Directory | /workspace/9.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2317403470 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 27985119194 ps |
| CPU time | 98.63 seconds |
| Started | May 19 12:49:27 PM PDT 24 |
| Finished | May 19 12:51:10 PM PDT 24 |
| Peak memory | 213844 kb |
| Host | smart-57d24203-e88f-44fa-8760-0d86f0082f5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317403470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa ssthru_mem_tl_intg_err.2317403470 |
| Directory | /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2269223589 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 5106339092 ps |
| CPU time | 32.82 seconds |
| Started | May 19 12:49:26 PM PDT 24 |
| Finished | May 19 12:50:03 PM PDT 24 |
| Peak memory | 212676 kb |
| Host | smart-cc799eeb-9567-47c4-a45a-b8c20531fdb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269223589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c trl_same_csr_outstanding.2269223589 |
| Directory | /workspace/9.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2507094225 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 1795835659 ps |
| CPU time | 18.58 seconds |
| Started | May 19 12:49:28 PM PDT 24 |
| Finished | May 19 12:49:50 PM PDT 24 |
| Peak memory | 218032 kb |
| Host | smart-cf5757c6-8b1b-4d13-b59f-85d74f42adca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507094225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2507094225 |
| Directory | /workspace/9.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3381936511 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 8066877821 ps |
| CPU time | 165.22 seconds |
| Started | May 19 12:49:29 PM PDT 24 |
| Finished | May 19 12:52:19 PM PDT 24 |
| Peak memory | 218960 kb |
| Host | smart-e977eea2-2752-4a32-a60c-99c59d2c027d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381936511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in tg_err.3381936511 |
| Directory | /workspace/9.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_alert_test.2736186371 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 1710652268 ps |
| CPU time | 11.53 seconds |
| Started | May 19 12:49:31 PM PDT 24 |
| Finished | May 19 12:49:47 PM PDT 24 |
| Peak memory | 211632 kb |
| Host | smart-33ee0041-c829-443e-b6c2-966f47e95813 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736186371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2736186371 |
| Directory | /workspace/0.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.963043139 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 65177355397 ps |
| CPU time | 656.47 seconds |
| Started | May 19 12:49:32 PM PDT 24 |
| Finished | May 19 01:00:34 PM PDT 24 |
| Peak memory | 216576 kb |
| Host | smart-96310067-c193-4005-9435-d69d09677f35 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963043139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co rrupt_sig_fatal_chk.963043139 |
| Directory | /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.828125973 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 7859096764 ps |
| CPU time | 20.76 seconds |
| Started | May 19 12:49:30 PM PDT 24 |
| Finished | May 19 12:49:56 PM PDT 24 |
| Peak memory | 211248 kb |
| Host | smart-2bb7f542-2444-4f1b-9e6f-69a1878f6163 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=828125973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.828125973 |
| Directory | /workspace/0.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_sec_cm.3508843371 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 18348699689 ps |
| CPU time | 126.27 seconds |
| Started | May 19 12:49:31 PM PDT 24 |
| Finished | May 19 12:51:43 PM PDT 24 |
| Peak memory | 238568 kb |
| Host | smart-e4081c6c-d384-447d-ae08-d3d5269b5a0f |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508843371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3508843371 |
| Directory | /workspace/0.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_smoke.2196985111 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 32951870453 ps |
| CPU time | 61.54 seconds |
| Started | May 19 12:49:32 PM PDT 24 |
| Finished | May 19 12:50:39 PM PDT 24 |
| Peak memory | 218060 kb |
| Host | smart-4b06a675-10c9-481e-bb0c-d5ee17f01a52 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2196985111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2196985111 |
| Directory | /workspace/0.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_stress_all.1766020359 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 22565978349 ps |
| CPU time | 81.78 seconds |
| Started | May 19 12:49:32 PM PDT 24 |
| Finished | May 19 12:50:59 PM PDT 24 |
| Peak memory | 219496 kb |
| Host | smart-a4def185-9886-4b78-810a-0b1ec82e1223 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766020359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.rom_ctrl_stress_all.1766020359 |
| Directory | /workspace/0.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_alert_test.1063332034 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 167699757 ps |
| CPU time | 8.26 seconds |
| Started | May 19 12:49:42 PM PDT 24 |
| Finished | May 19 12:49:54 PM PDT 24 |
| Peak memory | 211196 kb |
| Host | smart-dc08950e-74d2-4d27-9584-9ea934d87471 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063332034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1063332034 |
| Directory | /workspace/1.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2181904064 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 27419659331 ps |
| CPU time | 289.46 seconds |
| Started | May 19 12:49:30 PM PDT 24 |
| Finished | May 19 12:54:24 PM PDT 24 |
| Peak memory | 237868 kb |
| Host | smart-4c930f70-a1f9-4157-a75a-1d037caf94df |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181904064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c orrupt_sig_fatal_chk.2181904064 |
| Directory | /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1189509077 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 54665123115 ps |
| CPU time | 65.24 seconds |
| Started | May 19 12:49:22 PM PDT 24 |
| Finished | May 19 12:50:30 PM PDT 24 |
| Peak memory | 214988 kb |
| Host | smart-e00b37a3-7144-4283-8285-934beb8cdb9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1189509077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1189509077 |
| Directory | /workspace/1.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1726929812 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 5271100826 ps |
| CPU time | 18.31 seconds |
| Started | May 19 12:49:31 PM PDT 24 |
| Finished | May 19 12:49:55 PM PDT 24 |
| Peak memory | 211460 kb |
| Host | smart-2a1d7283-1e3b-47d4-bcbf-6544bc5fa52c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1726929812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1726929812 |
| Directory | /workspace/1.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_sec_cm.3341941775 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1538783654 ps |
| CPU time | 119.94 seconds |
| Started | May 19 12:49:41 PM PDT 24 |
| Finished | May 19 12:51:44 PM PDT 24 |
| Peak memory | 239204 kb |
| Host | smart-1a3c5b03-b93c-470d-99f2-7e12b6b6e7ba |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341941775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3341941775 |
| Directory | /workspace/1.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_smoke.1441962792 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 5401631739 ps |
| CPU time | 53.23 seconds |
| Started | May 19 12:49:23 PM PDT 24 |
| Finished | May 19 12:50:18 PM PDT 24 |
| Peak memory | 217152 kb |
| Host | smart-9331e71b-ef9e-4bce-afc9-107049a1f35a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1441962792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1441962792 |
| Directory | /workspace/1.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_stress_all.4017027647 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 33349831478 ps |
| CPU time | 94.46 seconds |
| Started | May 19 12:49:40 PM PDT 24 |
| Finished | May 19 12:51:17 PM PDT 24 |
| Peak memory | 220620 kb |
| Host | smart-f29ffd17-0cce-4f23-838c-233b5498d626 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017027647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.rom_ctrl_stress_all.4017027647 |
| Directory | /workspace/1.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_alert_test.3073263799 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3823763277 ps |
| CPU time | 31.06 seconds |
| Started | May 19 12:49:37 PM PDT 24 |
| Finished | May 19 12:50:12 PM PDT 24 |
| Peak memory | 211888 kb |
| Host | smart-80c5bbed-72f1-4c2e-a2e7-f633a56d2032 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073263799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3073263799 |
| Directory | /workspace/10.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.698033762 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 54509403670 ps |
| CPU time | 333.24 seconds |
| Started | May 19 12:49:32 PM PDT 24 |
| Finished | May 19 12:55:11 PM PDT 24 |
| Peak memory | 227716 kb |
| Host | smart-fb0240d8-5003-4edf-8d98-4e95ebe2bee1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698033762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c orrupt_sig_fatal_chk.698033762 |
| Directory | /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3596293203 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 33384889884 ps |
| CPU time | 67.73 seconds |
| Started | May 19 12:49:44 PM PDT 24 |
| Finished | May 19 12:50:55 PM PDT 24 |
| Peak memory | 215000 kb |
| Host | smart-abba100f-bd8b-4e64-a364-c35ada45b7fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3596293203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3596293203 |
| Directory | /workspace/10.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1510649853 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 4112695174 ps |
| CPU time | 33.92 seconds |
| Started | May 19 12:49:47 PM PDT 24 |
| Finished | May 19 12:50:23 PM PDT 24 |
| Peak memory | 211260 kb |
| Host | smart-4a0adba7-c1d0-4095-b641-9a3aee5b3ec1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1510649853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1510649853 |
| Directory | /workspace/10.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_smoke.446954305 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4571001996 ps |
| CPU time | 46.69 seconds |
| Started | May 19 12:49:40 PM PDT 24 |
| Finished | May 19 12:50:30 PM PDT 24 |
| Peak memory | 215512 kb |
| Host | smart-1ff0080e-3d2f-4065-97b1-63553a48ba0f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=446954305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.446954305 |
| Directory | /workspace/10.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_stress_all.996036421 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 25173960446 ps |
| CPU time | 141.3 seconds |
| Started | May 19 12:49:31 PM PDT 24 |
| Finished | May 19 12:51:58 PM PDT 24 |
| Peak memory | 227504 kb |
| Host | smart-21192273-3eeb-48db-b20e-00870aa36b4b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996036421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 10.rom_ctrl_stress_all.996036421 |
| Directory | /workspace/10.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_alert_test.3016800148 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 7873568229 ps |
| CPU time | 32.78 seconds |
| Started | May 19 12:49:36 PM PDT 24 |
| Finished | May 19 12:50:13 PM PDT 24 |
| Peak memory | 211992 kb |
| Host | smart-ead549a2-8dea-492b-944b-39927af1c807 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016800148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3016800148 |
| Directory | /workspace/11.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2884538345 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 54933127654 ps |
| CPU time | 404.38 seconds |
| Started | May 19 12:49:41 PM PDT 24 |
| Finished | May 19 12:56:28 PM PDT 24 |
| Peak memory | 217296 kb |
| Host | smart-47102632-3212-4bba-ba65-c2f213475682 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884538345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_ corrupt_sig_fatal_chk.2884538345 |
| Directory | /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.4110864601 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 150293731928 ps |
| CPU time | 69.01 seconds |
| Started | May 19 12:49:44 PM PDT 24 |
| Finished | May 19 12:50:56 PM PDT 24 |
| Peak memory | 213976 kb |
| Host | smart-79652418-20e0-483d-b087-c44b443e806f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4110864601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.4110864601 |
| Directory | /workspace/11.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.325750786 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 3080553650 ps |
| CPU time | 27.52 seconds |
| Started | May 19 12:49:47 PM PDT 24 |
| Finished | May 19 12:50:17 PM PDT 24 |
| Peak memory | 212168 kb |
| Host | smart-d48b9bd2-61f6-405e-8cbf-d022f57c4da0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=325750786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.325750786 |
| Directory | /workspace/11.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_smoke.2148111945 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 17966188903 ps |
| CPU time | 44.1 seconds |
| Started | May 19 12:49:41 PM PDT 24 |
| Finished | May 19 12:50:27 PM PDT 24 |
| Peak memory | 217216 kb |
| Host | smart-2f78b453-30a7-45f1-b70e-523202096b6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2148111945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2148111945 |
| Directory | /workspace/11.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_stress_all.3447275991 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 364744642 ps |
| CPU time | 21.17 seconds |
| Started | May 19 12:49:34 PM PDT 24 |
| Finished | May 19 12:50:00 PM PDT 24 |
| Peak memory | 211540 kb |
| Host | smart-5d5edfcf-acad-4778-9964-e8fd6dba137b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447275991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 11.rom_ctrl_stress_all.3447275991 |
| Directory | /workspace/11.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_alert_test.138136523 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 516932410 ps |
| CPU time | 12 seconds |
| Started | May 19 12:49:49 PM PDT 24 |
| Finished | May 19 12:50:04 PM PDT 24 |
| Peak memory | 211240 kb |
| Host | smart-b8180666-20b2-4d1a-a67a-7f4436ade6f3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138136523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.138136523 |
| Directory | /workspace/12.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2344849856 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 29865572217 ps |
| CPU time | 187.23 seconds |
| Started | May 19 12:49:36 PM PDT 24 |
| Finished | May 19 12:52:47 PM PDT 24 |
| Peak memory | 237076 kb |
| Host | smart-8e8ad812-bd43-4f19-b384-4bb43e23d844 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344849856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_ corrupt_sig_fatal_chk.2344849856 |
| Directory | /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3637278352 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 3116180876 ps |
| CPU time | 31.35 seconds |
| Started | May 19 12:49:31 PM PDT 24 |
| Finished | May 19 12:50:08 PM PDT 24 |
| Peak memory | 214740 kb |
| Host | smart-2b0b923a-7759-44d6-a21a-131ea9397880 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3637278352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3637278352 |
| Directory | /workspace/12.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.275368532 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 3810689629 ps |
| CPU time | 27.22 seconds |
| Started | May 19 12:49:36 PM PDT 24 |
| Finished | May 19 12:50:07 PM PDT 24 |
| Peak memory | 211368 kb |
| Host | smart-7a557db3-73d0-401f-9e56-a3d787246eba |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=275368532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.275368532 |
| Directory | /workspace/12.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_smoke.1128936136 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 360904933 ps |
| CPU time | 19.93 seconds |
| Started | May 19 12:49:35 PM PDT 24 |
| Finished | May 19 12:49:59 PM PDT 24 |
| Peak memory | 217244 kb |
| Host | smart-3391f774-26ee-40ca-a5fb-20822f40f01c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1128936136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1128936136 |
| Directory | /workspace/12.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_stress_all.1455255222 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 5692780395 ps |
| CPU time | 80.2 seconds |
| Started | May 19 12:49:41 PM PDT 24 |
| Finished | May 19 12:51:04 PM PDT 24 |
| Peak memory | 219280 kb |
| Host | smart-8af73fac-be5c-40af-ad22-2702c7869b26 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455255222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 12.rom_ctrl_stress_all.1455255222 |
| Directory | /workspace/12.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_alert_test.3637444924 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 432910495 ps |
| CPU time | 11.71 seconds |
| Started | May 19 12:49:31 PM PDT 24 |
| Finished | May 19 12:49:48 PM PDT 24 |
| Peak memory | 211168 kb |
| Host | smart-f74ad56f-8f36-403b-9a8a-c2e221a6eb85 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637444924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3637444924 |
| Directory | /workspace/13.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.296321355 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 18186025679 ps |
| CPU time | 49.37 seconds |
| Started | May 19 12:49:37 PM PDT 24 |
| Finished | May 19 12:50:30 PM PDT 24 |
| Peak memory | 214984 kb |
| Host | smart-09c3b80f-30f2-46eb-af1e-443737e403f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=296321355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.296321355 |
| Directory | /workspace/13.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2100816534 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 453895758 ps |
| CPU time | 10.1 seconds |
| Started | May 19 12:49:50 PM PDT 24 |
| Finished | May 19 12:50:03 PM PDT 24 |
| Peak memory | 212060 kb |
| Host | smart-d390fddb-591a-48a7-b365-7952eed2aa78 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2100816534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2100816534 |
| Directory | /workspace/13.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_smoke.4157053937 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 6904149344 ps |
| CPU time | 59.8 seconds |
| Started | May 19 12:49:26 PM PDT 24 |
| Finished | May 19 12:50:35 PM PDT 24 |
| Peak memory | 215252 kb |
| Host | smart-71044cdd-571f-4153-89b1-a4af59306e8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4157053937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.4157053937 |
| Directory | /workspace/13.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_stress_all.1037012670 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 13419809618 ps |
| CPU time | 112.64 seconds |
| Started | May 19 12:49:52 PM PDT 24 |
| Finished | May 19 12:51:47 PM PDT 24 |
| Peak memory | 230212 kb |
| Host | smart-3bd30b42-3ebc-4e77-b376-061148ca84e0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037012670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 13.rom_ctrl_stress_all.1037012670 |
| Directory | /workspace/13.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_alert_test.580479505 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2007773099 ps |
| CPU time | 14.75 seconds |
| Started | May 19 12:49:33 PM PDT 24 |
| Finished | May 19 12:49:53 PM PDT 24 |
| Peak memory | 211348 kb |
| Host | smart-1e86b388-0b62-4b13-846a-0c068611da59 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580479505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.580479505 |
| Directory | /workspace/14.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2859152946 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 80730685355 ps |
| CPU time | 480.5 seconds |
| Started | May 19 12:49:34 PM PDT 24 |
| Finished | May 19 12:57:40 PM PDT 24 |
| Peak memory | 238624 kb |
| Host | smart-485f6cb3-6dad-4a8d-b2a7-d8391342fc69 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859152946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_ corrupt_sig_fatal_chk.2859152946 |
| Directory | /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.481667764 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 138626221505 ps |
| CPU time | 65.95 seconds |
| Started | May 19 12:49:49 PM PDT 24 |
| Finished | May 19 12:50:58 PM PDT 24 |
| Peak memory | 215260 kb |
| Host | smart-8339e3b5-58a0-4ffa-95b9-4806b5a1e1f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=481667764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.481667764 |
| Directory | /workspace/14.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2075759765 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 18769080823 ps |
| CPU time | 33.04 seconds |
| Started | May 19 12:49:42 PM PDT 24 |
| Finished | May 19 12:50:18 PM PDT 24 |
| Peak memory | 211632 kb |
| Host | smart-a23131ff-dfff-4e2e-b55a-f2a5d97b647b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2075759765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2075759765 |
| Directory | /workspace/14.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_smoke.2694055684 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 704356336 ps |
| CPU time | 19.89 seconds |
| Started | May 19 12:49:50 PM PDT 24 |
| Finished | May 19 12:50:13 PM PDT 24 |
| Peak memory | 216776 kb |
| Host | smart-c36dabfd-225c-45d1-a093-2313e1cf5767 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2694055684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2694055684 |
| Directory | /workspace/14.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_stress_all.854649448 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 35724868112 ps |
| CPU time | 77.88 seconds |
| Started | May 19 12:49:35 PM PDT 24 |
| Finished | May 19 12:50:57 PM PDT 24 |
| Peak memory | 217304 kb |
| Host | smart-a5e9ca98-af4d-4d0a-8f78-ffcad09619fa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854649448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 14.rom_ctrl_stress_all.854649448 |
| Directory | /workspace/14.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_alert_test.1411072128 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 352873073 ps |
| CPU time | 8.4 seconds |
| Started | May 19 12:49:49 PM PDT 24 |
| Finished | May 19 12:50:00 PM PDT 24 |
| Peak memory | 211224 kb |
| Host | smart-9529748c-fdca-49a4-8754-0d14c8e5a76e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411072128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1411072128 |
| Directory | /workspace/15.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3550632053 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 14498641231 ps |
| CPU time | 355.26 seconds |
| Started | May 19 12:49:34 PM PDT 24 |
| Finished | May 19 12:55:34 PM PDT 24 |
| Peak memory | 240804 kb |
| Host | smart-97910857-66af-4e7d-8423-16b401345d94 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550632053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_ corrupt_sig_fatal_chk.3550632053 |
| Directory | /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3593048871 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 5688160783 ps |
| CPU time | 28.9 seconds |
| Started | May 19 12:49:33 PM PDT 24 |
| Finished | May 19 12:50:07 PM PDT 24 |
| Peak memory | 213824 kb |
| Host | smart-7ec94ec1-2fdd-49a3-8eed-da6cc026168d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3593048871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3593048871 |
| Directory | /workspace/15.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.883294033 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 16131902917 ps |
| CPU time | 32.63 seconds |
| Started | May 19 12:49:39 PM PDT 24 |
| Finished | May 19 12:50:14 PM PDT 24 |
| Peak memory | 211384 kb |
| Host | smart-ea2156b8-7ae6-4dcd-9c4b-145142ae257f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=883294033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.883294033 |
| Directory | /workspace/15.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_smoke.2545702171 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 6390954606 ps |
| CPU time | 39.59 seconds |
| Started | May 19 12:49:51 PM PDT 24 |
| Finished | May 19 12:50:34 PM PDT 24 |
| Peak memory | 218372 kb |
| Host | smart-fceb7236-9edf-4bca-a98a-ca803ad65bd9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2545702171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2545702171 |
| Directory | /workspace/15.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_stress_all.2611504630 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 4378869951 ps |
| CPU time | 18.14 seconds |
| Started | May 19 12:49:37 PM PDT 24 |
| Finished | May 19 12:49:59 PM PDT 24 |
| Peak memory | 213692 kb |
| Host | smart-3c72e462-e1ce-4ece-9113-2ba5fac3e131 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611504630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 15.rom_ctrl_stress_all.2611504630 |
| Directory | /workspace/15.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_alert_test.2590025194 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 3961870713 ps |
| CPU time | 31.27 seconds |
| Started | May 19 12:49:37 PM PDT 24 |
| Finished | May 19 12:50:12 PM PDT 24 |
| Peak memory | 211860 kb |
| Host | smart-a9c66fb6-8d2a-4717-a4b8-302ab1ddef2c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590025194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2590025194 |
| Directory | /workspace/16.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1267770331 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 26645960451 ps |
| CPU time | 150.69 seconds |
| Started | May 19 12:49:37 PM PDT 24 |
| Finished | May 19 12:52:11 PM PDT 24 |
| Peak memory | 217620 kb |
| Host | smart-a62c27b8-04be-4f56-8f32-c0f199c87169 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267770331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_ corrupt_sig_fatal_chk.1267770331 |
| Directory | /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3154984112 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 3921826898 ps |
| CPU time | 24.44 seconds |
| Started | May 19 12:49:36 PM PDT 24 |
| Finished | May 19 12:50:04 PM PDT 24 |
| Peak memory | 214588 kb |
| Host | smart-c2210cad-dc78-458b-863c-8dcbcdeeb763 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3154984112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3154984112 |
| Directory | /workspace/16.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2259843972 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 10296533210 ps |
| CPU time | 28.67 seconds |
| Started | May 19 12:49:41 PM PDT 24 |
| Finished | May 19 12:50:13 PM PDT 24 |
| Peak memory | 212744 kb |
| Host | smart-6fb573f4-58ac-4547-b0e4-1d0e17534109 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2259843972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2259843972 |
| Directory | /workspace/16.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_smoke.2854286739 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 7197263738 ps |
| CPU time | 62.54 seconds |
| Started | May 19 12:49:47 PM PDT 24 |
| Finished | May 19 12:50:52 PM PDT 24 |
| Peak memory | 216636 kb |
| Host | smart-72e0d682-d62d-4ded-9afa-d9d2c9ad89e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2854286739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2854286739 |
| Directory | /workspace/16.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_stress_all.4084869352 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 6402287972 ps |
| CPU time | 71.81 seconds |
| Started | May 19 12:49:36 PM PDT 24 |
| Finished | May 19 12:50:52 PM PDT 24 |
| Peak memory | 219440 kb |
| Host | smart-24bb6567-5a95-4f2f-b754-3824181359a4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084869352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 16.rom_ctrl_stress_all.4084869352 |
| Directory | /workspace/16.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_alert_test.30477248 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 3490836825 ps |
| CPU time | 19.19 seconds |
| Started | May 19 12:49:38 PM PDT 24 |
| Finished | May 19 12:50:00 PM PDT 24 |
| Peak memory | 211732 kb |
| Host | smart-47dc4344-af37-40c5-a9fe-e313352d1709 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30477248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.30477248 |
| Directory | /workspace/17.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3028684844 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 63457443928 ps |
| CPU time | 312.91 seconds |
| Started | May 19 12:49:37 PM PDT 24 |
| Finished | May 19 12:54:53 PM PDT 24 |
| Peak memory | 227972 kb |
| Host | smart-5b6d0c54-9ba0-43e7-8ff5-07c27987be4f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028684844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_ corrupt_sig_fatal_chk.3028684844 |
| Directory | /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.724797073 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 3813900373 ps |
| CPU time | 44.47 seconds |
| Started | May 19 12:49:40 PM PDT 24 |
| Finished | May 19 12:50:27 PM PDT 24 |
| Peak memory | 213604 kb |
| Host | smart-ddc6f9b5-80b9-4308-b60f-bc4df64ef81e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=724797073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.724797073 |
| Directory | /workspace/17.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3849986365 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 7867711218 ps |
| CPU time | 31.85 seconds |
| Started | May 19 12:49:43 PM PDT 24 |
| Finished | May 19 12:50:18 PM PDT 24 |
| Peak memory | 211312 kb |
| Host | smart-bd37771c-4328-4cd9-b231-0905b94eb98d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3849986365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3849986365 |
| Directory | /workspace/17.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_smoke.1657044292 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 44321444733 ps |
| CPU time | 51.99 seconds |
| Started | May 19 12:49:48 PM PDT 24 |
| Finished | May 19 12:50:43 PM PDT 24 |
| Peak memory | 215224 kb |
| Host | smart-77039031-0949-45d5-9222-f31f291b5455 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1657044292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1657044292 |
| Directory | /workspace/17.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_stress_all.2893550792 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 16921379281 ps |
| CPU time | 151.5 seconds |
| Started | May 19 12:49:37 PM PDT 24 |
| Finished | May 19 12:52:12 PM PDT 24 |
| Peak memory | 219760 kb |
| Host | smart-4c3eb905-1f26-4dd5-8468-92436df8f10a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893550792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 17.rom_ctrl_stress_all.2893550792 |
| Directory | /workspace/17.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_alert_test.1008237643 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 11470832498 ps |
| CPU time | 26.28 seconds |
| Started | May 19 12:49:43 PM PDT 24 |
| Finished | May 19 12:50:12 PM PDT 24 |
| Peak memory | 211368 kb |
| Host | smart-0a19b43e-93f2-4931-9908-d29600ec61ef |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008237643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1008237643 |
| Directory | /workspace/18.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3406115795 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 176746209643 ps |
| CPU time | 499.35 seconds |
| Started | May 19 12:49:40 PM PDT 24 |
| Finished | May 19 12:58:03 PM PDT 24 |
| Peak memory | 228916 kb |
| Host | smart-84118071-c6ba-40d9-9cd3-95dd21d45088 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406115795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_ corrupt_sig_fatal_chk.3406115795 |
| Directory | /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.419542957 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 12371155130 ps |
| CPU time | 38.71 seconds |
| Started | May 19 12:49:45 PM PDT 24 |
| Finished | May 19 12:50:27 PM PDT 24 |
| Peak memory | 215008 kb |
| Host | smart-10c8e09f-f875-4f04-ad19-0779f7741b5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=419542957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.419542957 |
| Directory | /workspace/18.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2783464644 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 3095270020 ps |
| CPU time | 27.04 seconds |
| Started | May 19 12:49:31 PM PDT 24 |
| Finished | May 19 12:50:03 PM PDT 24 |
| Peak memory | 212136 kb |
| Host | smart-af143d0c-db60-4bac-b527-9b184df459c3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2783464644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2783464644 |
| Directory | /workspace/18.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_smoke.323883669 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 347918579 ps |
| CPU time | 19.43 seconds |
| Started | May 19 12:49:35 PM PDT 24 |
| Finished | May 19 12:49:59 PM PDT 24 |
| Peak memory | 216540 kb |
| Host | smart-7361326b-2650-4838-a0e5-510d658e5da0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=323883669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.323883669 |
| Directory | /workspace/18.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_stress_all.2639998292 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 621492976 ps |
| CPU time | 25.73 seconds |
| Started | May 19 12:49:52 PM PDT 24 |
| Finished | May 19 12:50:20 PM PDT 24 |
| Peak memory | 212992 kb |
| Host | smart-487174ef-7b4f-4ba9-bf3b-f3fbb73126d2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639998292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 18.rom_ctrl_stress_all.2639998292 |
| Directory | /workspace/18.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_alert_test.2909591907 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 1906522694 ps |
| CPU time | 20.18 seconds |
| Started | May 19 12:49:33 PM PDT 24 |
| Finished | May 19 12:49:58 PM PDT 24 |
| Peak memory | 211272 kb |
| Host | smart-747c277b-5569-4d4a-9d81-a5a69ba2bbf0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909591907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2909591907 |
| Directory | /workspace/19.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.98441534 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 350000447545 ps |
| CPU time | 508 seconds |
| Started | May 19 12:49:41 PM PDT 24 |
| Finished | May 19 12:58:12 PM PDT 24 |
| Peak memory | 237992 kb |
| Host | smart-f73e87a6-8908-4d78-b933-ce9eab00378a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98441534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_ sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_co rrupt_sig_fatal_chk.98441534 |
| Directory | /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.487363484 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 3667781414 ps |
| CPU time | 18.97 seconds |
| Started | May 19 12:49:39 PM PDT 24 |
| Finished | May 19 12:50:00 PM PDT 24 |
| Peak memory | 215332 kb |
| Host | smart-4c037598-12b2-41e1-a502-635d4318ff54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=487363484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.487363484 |
| Directory | /workspace/19.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2582585406 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 729119255 ps |
| CPU time | 10.51 seconds |
| Started | May 19 12:49:44 PM PDT 24 |
| Finished | May 19 12:49:57 PM PDT 24 |
| Peak memory | 212724 kb |
| Host | smart-8a0799f7-bb6d-4631-a189-350b6b97a911 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2582585406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2582585406 |
| Directory | /workspace/19.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_smoke.2234719608 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 5472817529 ps |
| CPU time | 40.21 seconds |
| Started | May 19 12:49:43 PM PDT 24 |
| Finished | May 19 12:50:27 PM PDT 24 |
| Peak memory | 217144 kb |
| Host | smart-f93360bb-3cc7-4596-811f-3439018e81b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2234719608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2234719608 |
| Directory | /workspace/19.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_stress_all.4182968059 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 557027196 ps |
| CPU time | 29.49 seconds |
| Started | May 19 12:49:36 PM PDT 24 |
| Finished | May 19 12:50:10 PM PDT 24 |
| Peak memory | 219732 kb |
| Host | smart-aef33a89-477c-47dd-9c52-8bac69ab8590 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182968059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 19.rom_ctrl_stress_all.4182968059 |
| Directory | /workspace/19.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3429149792 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 363113115195 ps |
| CPU time | 1556.7 seconds |
| Started | May 19 12:49:45 PM PDT 24 |
| Finished | May 19 01:15:45 PM PDT 24 |
| Peak memory | 244052 kb |
| Host | smart-051d982b-0234-4349-83ff-654f4fbb7071 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429149792 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.3429149792 |
| Directory | /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_alert_test.525192310 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 338725580 ps |
| CPU time | 8.22 seconds |
| Started | May 19 12:49:35 PM PDT 24 |
| Finished | May 19 12:49:48 PM PDT 24 |
| Peak memory | 211244 kb |
| Host | smart-4a2e9f0d-1955-4287-87b7-9710eec3fd50 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525192310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.525192310 |
| Directory | /workspace/2.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3817635230 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 74978859657 ps |
| CPU time | 439.87 seconds |
| Started | May 19 12:49:35 PM PDT 24 |
| Finished | May 19 12:56:59 PM PDT 24 |
| Peak memory | 225536 kb |
| Host | smart-a8d605e2-e7dc-433a-997d-46b9dc325a45 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817635230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c orrupt_sig_fatal_chk.3817635230 |
| Directory | /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2083266016 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 69195522167 ps |
| CPU time | 61.43 seconds |
| Started | May 19 12:49:33 PM PDT 24 |
| Finished | May 19 12:50:40 PM PDT 24 |
| Peak memory | 215236 kb |
| Host | smart-b5b0d9fe-f028-4065-ad4c-a74e0fcca6d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2083266016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2083266016 |
| Directory | /workspace/2.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1920431286 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 10745130219 ps |
| CPU time | 27.12 seconds |
| Started | May 19 12:49:29 PM PDT 24 |
| Finished | May 19 12:50:00 PM PDT 24 |
| Peak memory | 212688 kb |
| Host | smart-441fc9fa-f588-4ec9-9238-cd05a04d24bc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1920431286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1920431286 |
| Directory | /workspace/2.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_sec_cm.2168675189 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1007361289 ps |
| CPU time | 123.93 seconds |
| Started | May 19 12:49:27 PM PDT 24 |
| Finished | May 19 12:51:34 PM PDT 24 |
| Peak memory | 237152 kb |
| Host | smart-e762afba-471e-4c62-ae3f-5e7bdb285f86 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168675189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2168675189 |
| Directory | /workspace/2.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_smoke.4165964478 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1373070272 ps |
| CPU time | 20.48 seconds |
| Started | May 19 12:49:26 PM PDT 24 |
| Finished | May 19 12:49:51 PM PDT 24 |
| Peak memory | 216660 kb |
| Host | smart-4504442b-b037-4645-bcfa-2f63b67c4ea4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4165964478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.4165964478 |
| Directory | /workspace/2.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_stress_all.3346372518 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 100688521605 ps |
| CPU time | 232.5 seconds |
| Started | May 19 12:49:35 PM PDT 24 |
| Finished | May 19 12:53:32 PM PDT 24 |
| Peak memory | 221836 kb |
| Host | smart-b264b438-27d8-4bd0-ac57-c29fdf97d83c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346372518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.rom_ctrl_stress_all.3346372518 |
| Directory | /workspace/2.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_alert_test.1519059387 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 2213657769 ps |
| CPU time | 22.56 seconds |
| Started | May 19 12:49:45 PM PDT 24 |
| Finished | May 19 12:50:10 PM PDT 24 |
| Peak memory | 211352 kb |
| Host | smart-9454a043-a3c6-493b-b956-02b722c82668 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519059387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1519059387 |
| Directory | /workspace/20.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1622336310 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 118439122679 ps |
| CPU time | 645.29 seconds |
| Started | May 19 12:49:43 PM PDT 24 |
| Finished | May 19 01:00:31 PM PDT 24 |
| Peak memory | 238776 kb |
| Host | smart-4e461e72-ac4b-4a40-bf2d-e82643a90017 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622336310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_ corrupt_sig_fatal_chk.1622336310 |
| Directory | /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3542663424 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 33404129952 ps |
| CPU time | 66.17 seconds |
| Started | May 19 12:49:38 PM PDT 24 |
| Finished | May 19 12:50:47 PM PDT 24 |
| Peak memory | 215224 kb |
| Host | smart-8bfd653b-8408-4d12-8445-337c3ca55894 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3542663424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3542663424 |
| Directory | /workspace/20.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_smoke.533293083 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 3300103493 ps |
| CPU time | 47.22 seconds |
| Started | May 19 12:49:43 PM PDT 24 |
| Finished | May 19 12:50:33 PM PDT 24 |
| Peak memory | 215708 kb |
| Host | smart-75699d71-815c-4d40-94fb-5d6aec3e5abe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=533293083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.533293083 |
| Directory | /workspace/20.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_stress_all.3320669734 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 49324814873 ps |
| CPU time | 103.71 seconds |
| Started | May 19 12:49:43 PM PDT 24 |
| Finished | May 19 12:51:30 PM PDT 24 |
| Peak memory | 219220 kb |
| Host | smart-3889d3ac-bdc9-41a3-afab-5385530a3791 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320669734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 20.rom_ctrl_stress_all.3320669734 |
| Directory | /workspace/20.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_alert_test.1709117751 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 2149400780 ps |
| CPU time | 21.44 seconds |
| Started | May 19 12:49:42 PM PDT 24 |
| Finished | May 19 12:50:07 PM PDT 24 |
| Peak memory | 211468 kb |
| Host | smart-078e625d-899d-4d40-9476-8573a7905b06 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709117751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1709117751 |
| Directory | /workspace/21.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1052785195 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 66427681870 ps |
| CPU time | 199.94 seconds |
| Started | May 19 12:49:43 PM PDT 24 |
| Finished | May 19 12:53:06 PM PDT 24 |
| Peak memory | 240692 kb |
| Host | smart-dab9c8fa-7567-4536-8360-19ce652f65fe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052785195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_ corrupt_sig_fatal_chk.1052785195 |
| Directory | /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2908949001 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 769892650 ps |
| CPU time | 18.78 seconds |
| Started | May 19 12:49:39 PM PDT 24 |
| Finished | May 19 12:50:00 PM PDT 24 |
| Peak memory | 214676 kb |
| Host | smart-26807133-a28c-4300-b497-ceda1a8d4b63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2908949001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2908949001 |
| Directory | /workspace/21.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3619581744 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 3438764789 ps |
| CPU time | 23.95 seconds |
| Started | May 19 12:49:49 PM PDT 24 |
| Finished | May 19 12:50:16 PM PDT 24 |
| Peak memory | 212588 kb |
| Host | smart-e10d8501-6e2c-4e72-ba1c-7042ca1c86f3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3619581744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3619581744 |
| Directory | /workspace/21.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_smoke.494087338 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1677705942 ps |
| CPU time | 26.59 seconds |
| Started | May 19 12:49:42 PM PDT 24 |
| Finished | May 19 12:50:11 PM PDT 24 |
| Peak memory | 215632 kb |
| Host | smart-14ad4f48-b42c-4115-a785-6e137b6cef02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=494087338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.494087338 |
| Directory | /workspace/21.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_stress_all.913489192 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 23718215259 ps |
| CPU time | 74.44 seconds |
| Started | May 19 12:49:42 PM PDT 24 |
| Finished | May 19 12:50:59 PM PDT 24 |
| Peak memory | 219516 kb |
| Host | smart-7dc21f4a-858c-4107-8dad-b3800b9cb267 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913489192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 21.rom_ctrl_stress_all.913489192 |
| Directory | /workspace/21.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_alert_test.2370041053 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1193455145 ps |
| CPU time | 15.8 seconds |
| Started | May 19 12:49:44 PM PDT 24 |
| Finished | May 19 12:50:02 PM PDT 24 |
| Peak memory | 211240 kb |
| Host | smart-5813f298-85a0-47f4-8e44-6372bd44c863 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370041053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2370041053 |
| Directory | /workspace/22.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2434833815 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 138122560595 ps |
| CPU time | 399.36 seconds |
| Started | May 19 12:49:53 PM PDT 24 |
| Finished | May 19 12:56:35 PM PDT 24 |
| Peak memory | 237780 kb |
| Host | smart-8e3ed8cf-7619-4271-9002-6eae87eac3ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434833815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_ corrupt_sig_fatal_chk.2434833815 |
| Directory | /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3192391685 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 21552954178 ps |
| CPU time | 49.42 seconds |
| Started | May 19 12:49:51 PM PDT 24 |
| Finished | May 19 12:50:44 PM PDT 24 |
| Peak memory | 215132 kb |
| Host | smart-b6b68234-74fe-4797-ab4c-14fedde78855 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3192391685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3192391685 |
| Directory | /workspace/22.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.569014709 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 863968766 ps |
| CPU time | 12.83 seconds |
| Started | May 19 12:49:42 PM PDT 24 |
| Finished | May 19 12:49:58 PM PDT 24 |
| Peak memory | 211108 kb |
| Host | smart-5805a17f-6174-4944-9722-4f871f0af57c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=569014709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.569014709 |
| Directory | /workspace/22.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_smoke.3498521016 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 5935529723 ps |
| CPU time | 39.38 seconds |
| Started | May 19 12:49:48 PM PDT 24 |
| Finished | May 19 12:50:30 PM PDT 24 |
| Peak memory | 216524 kb |
| Host | smart-237f1868-8cf3-4ca8-8604-711f87c169f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3498521016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3498521016 |
| Directory | /workspace/22.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_stress_all.4040673293 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 14901921417 ps |
| CPU time | 96.89 seconds |
| Started | May 19 12:49:42 PM PDT 24 |
| Finished | May 19 12:51:22 PM PDT 24 |
| Peak memory | 221260 kb |
| Host | smart-fce1eda3-d474-4a1c-b44f-f136511c3897 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040673293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 22.rom_ctrl_stress_all.4040673293 |
| Directory | /workspace/22.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_alert_test.3585303394 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 660188230 ps |
| CPU time | 8.21 seconds |
| Started | May 19 12:49:41 PM PDT 24 |
| Finished | May 19 12:49:52 PM PDT 24 |
| Peak memory | 211220 kb |
| Host | smart-286ee88f-c637-4c84-aa6c-a3efe7309099 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585303394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3585303394 |
| Directory | /workspace/23.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1501112343 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 13928121941 ps |
| CPU time | 231.17 seconds |
| Started | May 19 12:49:42 PM PDT 24 |
| Finished | May 19 12:53:36 PM PDT 24 |
| Peak memory | 233836 kb |
| Host | smart-4749a69a-fb24-40d8-8e6e-4607eb70287b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501112343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_ corrupt_sig_fatal_chk.1501112343 |
| Directory | /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1795680962 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 20403109751 ps |
| CPU time | 50.35 seconds |
| Started | May 19 12:49:42 PM PDT 24 |
| Finished | May 19 12:50:35 PM PDT 24 |
| Peak memory | 214964 kb |
| Host | smart-45658c53-c37f-49e1-9996-67bad51ad177 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1795680962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1795680962 |
| Directory | /workspace/23.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.434132035 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 11005045571 ps |
| CPU time | 16.59 seconds |
| Started | May 19 12:49:47 PM PDT 24 |
| Finished | May 19 12:50:06 PM PDT 24 |
| Peak memory | 211536 kb |
| Host | smart-0b36ea44-0810-4aac-80ad-bd3575153850 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=434132035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.434132035 |
| Directory | /workspace/23.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_smoke.1713315873 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 4495152690 ps |
| CPU time | 34.1 seconds |
| Started | May 19 12:49:41 PM PDT 24 |
| Finished | May 19 12:50:18 PM PDT 24 |
| Peak memory | 217008 kb |
| Host | smart-9b513286-b958-47f5-9522-de710b0d96e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1713315873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1713315873 |
| Directory | /workspace/23.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_stress_all.4231357986 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 173179999 ps |
| CPU time | 13.57 seconds |
| Started | May 19 12:49:49 PM PDT 24 |
| Finished | May 19 12:50:05 PM PDT 24 |
| Peak memory | 211232 kb |
| Host | smart-44be414c-0545-4574-8317-9cd4bd9bf19d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231357986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 23.rom_ctrl_stress_all.4231357986 |
| Directory | /workspace/23.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_alert_test.1069068030 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 1098355805 ps |
| CPU time | 8.33 seconds |
| Started | May 19 12:49:47 PM PDT 24 |
| Finished | May 19 12:49:58 PM PDT 24 |
| Peak memory | 211216 kb |
| Host | smart-33b45aff-7f68-4bf5-9540-dfd34e741ee7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069068030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1069068030 |
| Directory | /workspace/24.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1113484393 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 184598018515 ps |
| CPU time | 483.14 seconds |
| Started | May 19 12:49:51 PM PDT 24 |
| Finished | May 19 12:57:58 PM PDT 24 |
| Peak memory | 234052 kb |
| Host | smart-39cfac1e-33ea-47d9-a7c4-263a7c147177 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113484393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_ corrupt_sig_fatal_chk.1113484393 |
| Directory | /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2639638383 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 4260942755 ps |
| CPU time | 46.16 seconds |
| Started | May 19 12:49:53 PM PDT 24 |
| Finished | May 19 12:50:42 PM PDT 24 |
| Peak memory | 213592 kb |
| Host | smart-dff22625-56b7-4ba4-b5b9-ceae5cf8e381 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2639638383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2639638383 |
| Directory | /workspace/24.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1394715890 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 10970357605 ps |
| CPU time | 19.32 seconds |
| Started | May 19 12:49:44 PM PDT 24 |
| Finished | May 19 12:50:06 PM PDT 24 |
| Peak memory | 211712 kb |
| Host | smart-60827d28-3994-45b3-8ff2-383de97e849b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1394715890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1394715890 |
| Directory | /workspace/24.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_smoke.2838155690 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 24014940854 ps |
| CPU time | 40.33 seconds |
| Started | May 19 12:49:44 PM PDT 24 |
| Finished | May 19 12:50:28 PM PDT 24 |
| Peak memory | 216200 kb |
| Host | smart-a0cd815b-e253-42ba-ac6c-7134a7a00a6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2838155690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2838155690 |
| Directory | /workspace/24.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_stress_all.2604633064 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 59104971421 ps |
| CPU time | 150.41 seconds |
| Started | May 19 12:49:43 PM PDT 24 |
| Finished | May 19 12:52:17 PM PDT 24 |
| Peak memory | 220544 kb |
| Host | smart-6215707f-7363-48b9-9b52-3d3b58667851 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604633064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 24.rom_ctrl_stress_all.2604633064 |
| Directory | /workspace/24.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_alert_test.2920329349 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 5569708078 ps |
| CPU time | 17.16 seconds |
| Started | May 19 12:49:41 PM PDT 24 |
| Finished | May 19 12:50:01 PM PDT 24 |
| Peak memory | 211360 kb |
| Host | smart-8fe4c071-19e6-48d5-a8d0-4e261eb9b889 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920329349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2920329349 |
| Directory | /workspace/25.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.682642070 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 16504975293 ps |
| CPU time | 174.2 seconds |
| Started | May 19 12:49:44 PM PDT 24 |
| Finished | May 19 12:52:41 PM PDT 24 |
| Peak memory | 218588 kb |
| Host | smart-abbcae8b-f6d4-4e7f-8390-a470d652dcf0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682642070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c orrupt_sig_fatal_chk.682642070 |
| Directory | /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3974065848 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 7849798014 ps |
| CPU time | 33.62 seconds |
| Started | May 19 12:49:44 PM PDT 24 |
| Finished | May 19 12:50:21 PM PDT 24 |
| Peak memory | 215496 kb |
| Host | smart-f738690b-72be-46e0-a3aa-2e452dada859 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3974065848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3974065848 |
| Directory | /workspace/25.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.750566676 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 16052235022 ps |
| CPU time | 32.51 seconds |
| Started | May 19 12:49:42 PM PDT 24 |
| Finished | May 19 12:50:17 PM PDT 24 |
| Peak memory | 212712 kb |
| Host | smart-5f2f1230-4456-4d88-b1df-185ed0d81e34 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=750566676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.750566676 |
| Directory | /workspace/25.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_smoke.1249247044 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 28027504569 ps |
| CPU time | 76.41 seconds |
| Started | May 19 12:49:45 PM PDT 24 |
| Finished | May 19 12:51:04 PM PDT 24 |
| Peak memory | 216676 kb |
| Host | smart-7a1786f4-af39-4b36-8b2b-0d275a2c3670 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1249247044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1249247044 |
| Directory | /workspace/25.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_stress_all.191127621 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 3744771812 ps |
| CPU time | 42.12 seconds |
| Started | May 19 12:49:49 PM PDT 24 |
| Finished | May 19 12:50:34 PM PDT 24 |
| Peak memory | 213760 kb |
| Host | smart-fa6cefad-91b6-494e-9f8b-2c416f5dace7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191127621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.rom_ctrl_stress_all.191127621 |
| Directory | /workspace/25.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.628583207 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 135644959900 ps |
| CPU time | 707.67 seconds |
| Started | May 19 12:49:50 PM PDT 24 |
| Finished | May 19 01:01:41 PM PDT 24 |
| Peak memory | 217740 kb |
| Host | smart-9357a697-7d4b-4d67-96d7-e26d943351b3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628583207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c orrupt_sig_fatal_chk.628583207 |
| Directory | /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1064354903 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 662684418 ps |
| CPU time | 18.65 seconds |
| Started | May 19 12:49:55 PM PDT 24 |
| Finished | May 19 12:50:16 PM PDT 24 |
| Peak memory | 214776 kb |
| Host | smart-9f507ce6-f975-469a-b74f-61c788526813 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1064354903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1064354903 |
| Directory | /workspace/26.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2259335435 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 2664705888 ps |
| CPU time | 23.46 seconds |
| Started | May 19 12:49:48 PM PDT 24 |
| Finished | May 19 12:50:14 PM PDT 24 |
| Peak memory | 212524 kb |
| Host | smart-1874b794-4825-4fb4-a198-4ec8092ad447 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2259335435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2259335435 |
| Directory | /workspace/26.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_smoke.2406940121 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 3358867362 ps |
| CPU time | 46.18 seconds |
| Started | May 19 12:49:46 PM PDT 24 |
| Finished | May 19 12:50:34 PM PDT 24 |
| Peak memory | 217092 kb |
| Host | smart-690ba9a0-3fb7-4db9-be59-4034fb3da526 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2406940121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2406940121 |
| Directory | /workspace/26.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_stress_all.2992883597 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 1643266859 ps |
| CPU time | 26.68 seconds |
| Started | May 19 12:49:42 PM PDT 24 |
| Finished | May 19 12:50:12 PM PDT 24 |
| Peak memory | 211032 kb |
| Host | smart-2f3c1173-ed10-4a93-b1c1-2a423cfb08af |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992883597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 26.rom_ctrl_stress_all.2992883597 |
| Directory | /workspace/26.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_alert_test.3280108615 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 661051722 ps |
| CPU time | 8.18 seconds |
| Started | May 19 12:49:45 PM PDT 24 |
| Finished | May 19 12:49:56 PM PDT 24 |
| Peak memory | 211220 kb |
| Host | smart-9e6554a1-3adb-49fa-a78b-44f3bd2e3fac |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280108615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3280108615 |
| Directory | /workspace/27.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2073024037 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 169541665031 ps |
| CPU time | 548.03 seconds |
| Started | May 19 12:49:55 PM PDT 24 |
| Finished | May 19 12:59:05 PM PDT 24 |
| Peak memory | 237832 kb |
| Host | smart-cdf6897d-737f-4d85-98eb-5d1ecbebec83 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073024037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_ corrupt_sig_fatal_chk.2073024037 |
| Directory | /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3523668948 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 17780856102 ps |
| CPU time | 46.49 seconds |
| Started | May 19 12:49:46 PM PDT 24 |
| Finished | May 19 12:50:35 PM PDT 24 |
| Peak memory | 215028 kb |
| Host | smart-826ecdfa-b431-44e4-83a4-98fb3eeb6c04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3523668948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3523668948 |
| Directory | /workspace/27.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1659200544 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 3958060748 ps |
| CPU time | 16 seconds |
| Started | May 19 12:49:44 PM PDT 24 |
| Finished | May 19 12:50:03 PM PDT 24 |
| Peak memory | 212140 kb |
| Host | smart-14b595b3-5562-46b1-8a6c-a63e4b8fe871 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1659200544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1659200544 |
| Directory | /workspace/27.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_smoke.3428604451 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 29422571302 ps |
| CPU time | 67.72 seconds |
| Started | May 19 12:49:53 PM PDT 24 |
| Finished | May 19 12:51:04 PM PDT 24 |
| Peak memory | 217948 kb |
| Host | smart-338c88c4-36b5-49b9-91fe-f821ae762add |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3428604451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3428604451 |
| Directory | /workspace/27.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_stress_all.3480247877 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 4192062790 ps |
| CPU time | 99.6 seconds |
| Started | May 19 12:49:43 PM PDT 24 |
| Finished | May 19 12:51:26 PM PDT 24 |
| Peak memory | 221132 kb |
| Host | smart-587bd01d-56c5-4fcf-99f7-eec40e91b114 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480247877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 27.rom_ctrl_stress_all.3480247877 |
| Directory | /workspace/27.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_alert_test.2176241513 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 16961811819 ps |
| CPU time | 33.81 seconds |
| Started | May 19 12:49:44 PM PDT 24 |
| Finished | May 19 12:50:21 PM PDT 24 |
| Peak memory | 211680 kb |
| Host | smart-756475ce-b62f-46b7-bf32-051e4aadb630 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176241513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2176241513 |
| Directory | /workspace/28.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2528679993 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 28659266245 ps |
| CPU time | 208.72 seconds |
| Started | May 19 12:49:45 PM PDT 24 |
| Finished | May 19 12:53:17 PM PDT 24 |
| Peak memory | 215988 kb |
| Host | smart-30863f29-1d7e-4339-974f-afeef842a68b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528679993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_ corrupt_sig_fatal_chk.2528679993 |
| Directory | /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.4108736936 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 336006570 ps |
| CPU time | 20.2 seconds |
| Started | May 19 12:49:53 PM PDT 24 |
| Finished | May 19 12:50:16 PM PDT 24 |
| Peak memory | 214848 kb |
| Host | smart-eb3187d2-8339-4481-94c2-60fb13a892cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4108736936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.4108736936 |
| Directory | /workspace/28.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2140452278 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 2134013598 ps |
| CPU time | 22.91 seconds |
| Started | May 19 12:49:50 PM PDT 24 |
| Finished | May 19 12:50:16 PM PDT 24 |
| Peak memory | 211068 kb |
| Host | smart-1945bee9-f2df-4e84-a4b7-b26c2c336b31 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2140452278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2140452278 |
| Directory | /workspace/28.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_smoke.3055447042 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 12340979273 ps |
| CPU time | 60.3 seconds |
| Started | May 19 12:49:57 PM PDT 24 |
| Finished | May 19 12:50:59 PM PDT 24 |
| Peak memory | 215288 kb |
| Host | smart-ba6629ce-2ec2-41bf-85c5-9cef575c8461 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3055447042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3055447042 |
| Directory | /workspace/28.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_stress_all.2976155893 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 10054760192 ps |
| CPU time | 41.29 seconds |
| Started | May 19 12:49:53 PM PDT 24 |
| Finished | May 19 12:50:38 PM PDT 24 |
| Peak memory | 219096 kb |
| Host | smart-0f2cb57c-a5fb-4eca-851a-c6637f9afdd9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976155893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 28.rom_ctrl_stress_all.2976155893 |
| Directory | /workspace/28.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.295723019 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 28153378590 ps |
| CPU time | 575.89 seconds |
| Started | May 19 12:49:45 PM PDT 24 |
| Finished | May 19 12:59:24 PM PDT 24 |
| Peak memory | 229364 kb |
| Host | smart-8a92aa41-f2b2-43ef-aed0-b9e34b1649e7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295723019 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.295723019 |
| Directory | /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_alert_test.3018644034 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 42117607402 ps |
| CPU time | 29.35 seconds |
| Started | May 19 12:49:54 PM PDT 24 |
| Finished | May 19 12:50:26 PM PDT 24 |
| Peak memory | 212220 kb |
| Host | smart-0288ec0e-45b5-4068-bdc0-e33cec157ea7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018644034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3018644034 |
| Directory | /workspace/29.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2056466728 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 101706085708 ps |
| CPU time | 620.57 seconds |
| Started | May 19 12:49:43 PM PDT 24 |
| Finished | May 19 01:00:07 PM PDT 24 |
| Peak memory | 234308 kb |
| Host | smart-6681ab10-7fcd-4075-bf25-5946d3576df7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056466728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_ corrupt_sig_fatal_chk.2056466728 |
| Directory | /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2798949728 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 5903538125 ps |
| CPU time | 30.19 seconds |
| Started | May 19 12:49:47 PM PDT 24 |
| Finished | May 19 12:50:19 PM PDT 24 |
| Peak memory | 215208 kb |
| Host | smart-245f39a3-2bc0-40d5-8527-d6f067183d3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2798949728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2798949728 |
| Directory | /workspace/29.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3098218099 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 7793784836 ps |
| CPU time | 28.07 seconds |
| Started | May 19 12:49:54 PM PDT 24 |
| Finished | May 19 12:50:25 PM PDT 24 |
| Peak memory | 211656 kb |
| Host | smart-e64073a4-2f75-4b95-9d93-fa8df9e4cab7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3098218099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3098218099 |
| Directory | /workspace/29.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_stress_all.2582208074 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 30892077796 ps |
| CPU time | 79.04 seconds |
| Started | May 19 12:49:46 PM PDT 24 |
| Finished | May 19 12:51:07 PM PDT 24 |
| Peak memory | 216768 kb |
| Host | smart-72f10551-7389-45f9-a48a-12ec65c7943b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582208074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 29.rom_ctrl_stress_all.2582208074 |
| Directory | /workspace/29.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_alert_test.1729411888 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 12426999039 ps |
| CPU time | 27.51 seconds |
| Started | May 19 12:49:27 PM PDT 24 |
| Finished | May 19 12:49:59 PM PDT 24 |
| Peak memory | 212108 kb |
| Host | smart-d74f975f-711c-4d55-8fb3-e61c5982a51a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729411888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1729411888 |
| Directory | /workspace/3.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1280859705 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 5738577436 ps |
| CPU time | 218.05 seconds |
| Started | May 19 12:49:31 PM PDT 24 |
| Finished | May 19 12:53:14 PM PDT 24 |
| Peak memory | 236864 kb |
| Host | smart-0f82a9e7-cb23-4cbd-96ad-df119aaf9b1b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280859705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c orrupt_sig_fatal_chk.1280859705 |
| Directory | /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2599347355 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 13972234601 ps |
| CPU time | 63.25 seconds |
| Started | May 19 12:49:40 PM PDT 24 |
| Finished | May 19 12:50:46 PM PDT 24 |
| Peak memory | 214892 kb |
| Host | smart-fa6e1f9a-a0ee-42cd-9f88-711d87aa62d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2599347355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2599347355 |
| Directory | /workspace/3.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2338265573 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 348657967 ps |
| CPU time | 10.28 seconds |
| Started | May 19 12:49:25 PM PDT 24 |
| Finished | May 19 12:49:38 PM PDT 24 |
| Peak memory | 211976 kb |
| Host | smart-db448859-bbdd-495b-b684-b44304e660ed |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2338265573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2338265573 |
| Directory | /workspace/3.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_sec_cm.569325591 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 672778467 ps |
| CPU time | 231.14 seconds |
| Started | May 19 12:49:32 PM PDT 24 |
| Finished | May 19 12:53:28 PM PDT 24 |
| Peak memory | 238048 kb |
| Host | smart-2df8624c-6f0a-4968-9c09-cf4c9bc461a3 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569325591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.569325591 |
| Directory | /workspace/3.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_smoke.1385781055 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 50171619099 ps |
| CPU time | 70.4 seconds |
| Started | May 19 12:49:28 PM PDT 24 |
| Finished | May 19 12:50:43 PM PDT 24 |
| Peak memory | 217148 kb |
| Host | smart-c578d35c-d391-40c8-baf1-f38ee05eae8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1385781055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1385781055 |
| Directory | /workspace/3.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_stress_all.4083411827 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 921281252 ps |
| CPU time | 52.6 seconds |
| Started | May 19 12:49:26 PM PDT 24 |
| Finished | May 19 12:50:23 PM PDT 24 |
| Peak memory | 219216 kb |
| Host | smart-b7cb3228-d497-4547-a0ea-2ac3b7266de7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083411827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 3.rom_ctrl_stress_all.4083411827 |
| Directory | /workspace/3.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_alert_test.1838618179 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 4143062101 ps |
| CPU time | 21.3 seconds |
| Started | May 19 12:49:52 PM PDT 24 |
| Finished | May 19 12:50:16 PM PDT 24 |
| Peak memory | 211460 kb |
| Host | smart-7fc78e5b-5a35-4ee6-b955-d4f7485dfd3d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838618179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1838618179 |
| Directory | /workspace/30.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2869639206 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 62511632622 ps |
| CPU time | 619.77 seconds |
| Started | May 19 12:49:52 PM PDT 24 |
| Finished | May 19 01:00:15 PM PDT 24 |
| Peak memory | 233968 kb |
| Host | smart-fe76359f-fbca-4ae9-a027-4537bdf9c382 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869639206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_ corrupt_sig_fatal_chk.2869639206 |
| Directory | /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3681054169 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 5630688219 ps |
| CPU time | 52.37 seconds |
| Started | May 19 12:49:45 PM PDT 24 |
| Finished | May 19 12:50:40 PM PDT 24 |
| Peak memory | 215328 kb |
| Host | smart-ee7a132c-8cc4-4129-bd90-db0168b05ae9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3681054169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3681054169 |
| Directory | /workspace/30.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.468106250 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 2919245663 ps |
| CPU time | 27.13 seconds |
| Started | May 19 12:49:51 PM PDT 24 |
| Finished | May 19 12:50:21 PM PDT 24 |
| Peak memory | 211404 kb |
| Host | smart-1875b00b-ba8b-4792-8655-a5f748bf6a07 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=468106250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.468106250 |
| Directory | /workspace/30.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_smoke.398032876 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 28037911864 ps |
| CPU time | 63.42 seconds |
| Started | May 19 12:49:56 PM PDT 24 |
| Finished | May 19 12:51:01 PM PDT 24 |
| Peak memory | 217644 kb |
| Host | smart-0b9e567f-0d34-4c8c-8ef3-4340f7504a92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=398032876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.398032876 |
| Directory | /workspace/30.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_stress_all.979667081 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 679141058 ps |
| CPU time | 16.58 seconds |
| Started | May 19 12:49:52 PM PDT 24 |
| Finished | May 19 12:50:12 PM PDT 24 |
| Peak memory | 212168 kb |
| Host | smart-0bd21658-e3f2-4f01-9356-d5e1cf6f3e40 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979667081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 30.rom_ctrl_stress_all.979667081 |
| Directory | /workspace/30.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_alert_test.550911687 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 3023971081 ps |
| CPU time | 17.96 seconds |
| Started | May 19 12:49:55 PM PDT 24 |
| Finished | May 19 12:50:15 PM PDT 24 |
| Peak memory | 211932 kb |
| Host | smart-eff7d2b2-bcf7-4a23-a7bb-93f57ff079c1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550911687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.550911687 |
| Directory | /workspace/31.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4005682716 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 8433368975 ps |
| CPU time | 174.37 seconds |
| Started | May 19 12:49:49 PM PDT 24 |
| Finished | May 19 12:52:46 PM PDT 24 |
| Peak memory | 236792 kb |
| Host | smart-e74821a9-feed-48f4-9474-c38d530d0a3d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005682716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_ corrupt_sig_fatal_chk.4005682716 |
| Directory | /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.668532846 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 7489475624 ps |
| CPU time | 61.73 seconds |
| Started | May 19 12:49:57 PM PDT 24 |
| Finished | May 19 12:51:00 PM PDT 24 |
| Peak memory | 214840 kb |
| Host | smart-e18e89a9-b712-44d1-bc6b-129682d6e7f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=668532846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.668532846 |
| Directory | /workspace/31.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.4179410783 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 4649125848 ps |
| CPU time | 18.25 seconds |
| Started | May 19 12:49:58 PM PDT 24 |
| Finished | May 19 12:50:17 PM PDT 24 |
| Peak memory | 212856 kb |
| Host | smart-f1d56424-8adb-4eba-8ab0-7064c50baf3f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4179410783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.4179410783 |
| Directory | /workspace/31.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_smoke.2916596820 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 10461334817 ps |
| CPU time | 75.18 seconds |
| Started | May 19 12:49:49 PM PDT 24 |
| Finished | May 19 12:51:07 PM PDT 24 |
| Peak memory | 217888 kb |
| Host | smart-5b6add93-9bc2-4a01-adec-a6037a150db0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2916596820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2916596820 |
| Directory | /workspace/31.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_stress_all.3073323642 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 5790777828 ps |
| CPU time | 80.09 seconds |
| Started | May 19 12:49:48 PM PDT 24 |
| Finished | May 19 12:51:11 PM PDT 24 |
| Peak memory | 219252 kb |
| Host | smart-b235eb0b-41fd-4379-854a-c30f5cf99492 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073323642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 31.rom_ctrl_stress_all.3073323642 |
| Directory | /workspace/31.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_alert_test.3452583815 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 1893441975 ps |
| CPU time | 19.28 seconds |
| Started | May 19 12:49:50 PM PDT 24 |
| Finished | May 19 12:50:12 PM PDT 24 |
| Peak memory | 211216 kb |
| Host | smart-8cec1757-6a88-49ec-91d9-35e5ae28cc73 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452583815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3452583815 |
| Directory | /workspace/32.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2910117904 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 120852361581 ps |
| CPU time | 558.45 seconds |
| Started | May 19 12:49:46 PM PDT 24 |
| Finished | May 19 12:59:07 PM PDT 24 |
| Peak memory | 237868 kb |
| Host | smart-b3a015df-6311-438b-818e-49bad9ed6b66 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910117904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_ corrupt_sig_fatal_chk.2910117904 |
| Directory | /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1020999781 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 8660469130 ps |
| CPU time | 47.5 seconds |
| Started | May 19 12:49:53 PM PDT 24 |
| Finished | May 19 12:50:43 PM PDT 24 |
| Peak memory | 215004 kb |
| Host | smart-0676e39e-8e88-499e-a958-009ba0bd81d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1020999781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1020999781 |
| Directory | /workspace/32.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3072670688 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 261095491 ps |
| CPU time | 11.62 seconds |
| Started | May 19 12:49:53 PM PDT 24 |
| Finished | May 19 12:50:07 PM PDT 24 |
| Peak memory | 212116 kb |
| Host | smart-23fd958e-8a91-40f9-b50c-1bce2b67b9dd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3072670688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3072670688 |
| Directory | /workspace/32.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_smoke.2214746974 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 9363237873 ps |
| CPU time | 43.76 seconds |
| Started | May 19 12:49:50 PM PDT 24 |
| Finished | May 19 12:50:37 PM PDT 24 |
| Peak memory | 215800 kb |
| Host | smart-9f4f54bb-8e5c-4a40-8bc3-043cc30c9bc8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2214746974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2214746974 |
| Directory | /workspace/32.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_stress_all.3623766104 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1500359467 ps |
| CPU time | 27.9 seconds |
| Started | May 19 12:49:49 PM PDT 24 |
| Finished | May 19 12:50:20 PM PDT 24 |
| Peak memory | 217580 kb |
| Host | smart-f077bc30-cc9c-48db-894a-7e1f075d696e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623766104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 32.rom_ctrl_stress_all.3623766104 |
| Directory | /workspace/32.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_alert_test.1323563795 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 4391687921 ps |
| CPU time | 19.53 seconds |
| Started | May 19 12:49:52 PM PDT 24 |
| Finished | May 19 12:50:15 PM PDT 24 |
| Peak memory | 212204 kb |
| Host | smart-81356809-cb24-4f49-b862-70e7cab702c0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323563795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1323563795 |
| Directory | /workspace/33.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.942320192 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 247519060399 ps |
| CPU time | 378.73 seconds |
| Started | May 19 12:49:58 PM PDT 24 |
| Finished | May 19 12:56:18 PM PDT 24 |
| Peak memory | 233924 kb |
| Host | smart-5105b37e-efbc-492f-adfc-cdf43af4f617 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942320192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c orrupt_sig_fatal_chk.942320192 |
| Directory | /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.220405370 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 972167135 ps |
| CPU time | 19.07 seconds |
| Started | May 19 12:49:53 PM PDT 24 |
| Finished | May 19 12:50:15 PM PDT 24 |
| Peak memory | 214668 kb |
| Host | smart-c623d023-855e-43c5-83be-f85f5acbcc14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=220405370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.220405370 |
| Directory | /workspace/33.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1706757696 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 185109608 ps |
| CPU time | 10.68 seconds |
| Started | May 19 12:49:49 PM PDT 24 |
| Finished | May 19 12:50:02 PM PDT 24 |
| Peak memory | 212624 kb |
| Host | smart-933e29a5-f4a9-48a2-8bba-fc5b1ca35aa4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1706757696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1706757696 |
| Directory | /workspace/33.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_smoke.4077227179 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 6898890055 ps |
| CPU time | 75.73 seconds |
| Started | May 19 12:49:54 PM PDT 24 |
| Finished | May 19 12:51:12 PM PDT 24 |
| Peak memory | 217776 kb |
| Host | smart-9508ff6f-ce2d-43cc-8f75-fdab7427ac8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4077227179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.4077227179 |
| Directory | /workspace/33.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_stress_all.630543230 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 49260687676 ps |
| CPU time | 111.64 seconds |
| Started | May 19 12:49:48 PM PDT 24 |
| Finished | May 19 12:51:43 PM PDT 24 |
| Peak memory | 218600 kb |
| Host | smart-b6e58d9c-7d02-4ab5-b365-0eec1bb2fd08 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630543230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 33.rom_ctrl_stress_all.630543230 |
| Directory | /workspace/33.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_alert_test.1180774665 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 3602199541 ps |
| CPU time | 14.98 seconds |
| Started | May 19 12:49:48 PM PDT 24 |
| Finished | May 19 12:50:05 PM PDT 24 |
| Peak memory | 211380 kb |
| Host | smart-2b688135-54fd-4224-9775-6c65c2cc277e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180774665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1180774665 |
| Directory | /workspace/34.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2897144366 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4571708544 ps |
| CPU time | 181.21 seconds |
| Started | May 19 12:50:00 PM PDT 24 |
| Finished | May 19 12:53:02 PM PDT 24 |
| Peak memory | 228248 kb |
| Host | smart-82321250-a246-41e0-87af-0e9d8b09c025 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897144366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_ corrupt_sig_fatal_chk.2897144366 |
| Directory | /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2431668 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 1435642909 ps |
| CPU time | 19.79 seconds |
| Started | May 19 12:49:53 PM PDT 24 |
| Finished | May 19 12:50:16 PM PDT 24 |
| Peak memory | 214596 kb |
| Host | smart-50ff16f3-001a-48a9-b755-03b63f65de79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2431668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2431668 |
| Directory | /workspace/34.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2027473938 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 3366074061 ps |
| CPU time | 28.78 seconds |
| Started | May 19 12:49:48 PM PDT 24 |
| Finished | May 19 12:50:19 PM PDT 24 |
| Peak memory | 211308 kb |
| Host | smart-143171bd-282b-4604-9014-9f536102ef56 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2027473938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2027473938 |
| Directory | /workspace/34.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_smoke.129953427 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 72286834934 ps |
| CPU time | 61.15 seconds |
| Started | May 19 12:49:47 PM PDT 24 |
| Finished | May 19 12:50:50 PM PDT 24 |
| Peak memory | 217344 kb |
| Host | smart-3c68ca74-1afd-4746-bebd-b53f46139cb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=129953427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.129953427 |
| Directory | /workspace/34.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_stress_all.2423837187 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 5953232271 ps |
| CPU time | 66.49 seconds |
| Started | May 19 12:50:05 PM PDT 24 |
| Finished | May 19 12:51:12 PM PDT 24 |
| Peak memory | 216592 kb |
| Host | smart-97e902ff-f6a7-4bb2-94eb-4e7069fd8b7d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423837187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 34.rom_ctrl_stress_all.2423837187 |
| Directory | /workspace/34.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3110333367 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 47611265599 ps |
| CPU time | 4057.92 seconds |
| Started | May 19 12:49:52 PM PDT 24 |
| Finished | May 19 01:57:33 PM PDT 24 |
| Peak memory | 235836 kb |
| Host | smart-c41fb22c-b814-4f71-bc73-53cee7eb9819 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110333367 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.3110333367 |
| Directory | /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_alert_test.3386104593 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 338577000 ps |
| CPU time | 8.24 seconds |
| Started | May 19 12:49:57 PM PDT 24 |
| Finished | May 19 12:50:07 PM PDT 24 |
| Peak memory | 211352 kb |
| Host | smart-19b5db80-079b-4134-a08b-42106234d457 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386104593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3386104593 |
| Directory | /workspace/35.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1411605395 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 51917561238 ps |
| CPU time | 173.83 seconds |
| Started | May 19 12:49:50 PM PDT 24 |
| Finished | May 19 12:52:47 PM PDT 24 |
| Peak memory | 228516 kb |
| Host | smart-feaee937-3aa5-4447-9a0e-40e1330b9dcc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411605395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_ corrupt_sig_fatal_chk.1411605395 |
| Directory | /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1841155174 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 15735321191 ps |
| CPU time | 43.38 seconds |
| Started | May 19 12:49:49 PM PDT 24 |
| Finished | May 19 12:50:35 PM PDT 24 |
| Peak memory | 214960 kb |
| Host | smart-bd03d6e4-e41a-4f51-900d-5930f4c859ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1841155174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1841155174 |
| Directory | /workspace/35.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3397528738 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11520607467 ps |
| CPU time | 21.29 seconds |
| Started | May 19 12:49:49 PM PDT 24 |
| Finished | May 19 12:50:13 PM PDT 24 |
| Peak memory | 211328 kb |
| Host | smart-66705fc9-bcaf-45c7-91c2-1574b6aad268 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3397528738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3397528738 |
| Directory | /workspace/35.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_smoke.4158401810 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 693552064 ps |
| CPU time | 20.05 seconds |
| Started | May 19 12:49:55 PM PDT 24 |
| Finished | May 19 12:50:17 PM PDT 24 |
| Peak memory | 216544 kb |
| Host | smart-99d393a6-6eab-42a8-9a6e-471d5c5ff388 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4158401810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.4158401810 |
| Directory | /workspace/35.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_alert_test.1722371106 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 3751834679 ps |
| CPU time | 15.09 seconds |
| Started | May 19 12:49:55 PM PDT 24 |
| Finished | May 19 12:50:12 PM PDT 24 |
| Peak memory | 211368 kb |
| Host | smart-47c65c4b-9104-4ac8-81aa-d1791dd1965d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722371106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1722371106 |
| Directory | /workspace/36.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2672016625 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 31513032130 ps |
| CPU time | 542.41 seconds |
| Started | May 19 12:49:52 PM PDT 24 |
| Finished | May 19 12:58:57 PM PDT 24 |
| Peak memory | 238980 kb |
| Host | smart-2b444d6a-d88f-44e6-b98e-05293622f2ba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672016625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_ corrupt_sig_fatal_chk.2672016625 |
| Directory | /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1846069153 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 674867638 ps |
| CPU time | 19.19 seconds |
| Started | May 19 12:49:51 PM PDT 24 |
| Finished | May 19 12:50:13 PM PDT 24 |
| Peak memory | 214784 kb |
| Host | smart-b1d22055-ae01-4d59-9f0a-0049c4682949 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1846069153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1846069153 |
| Directory | /workspace/36.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3221000904 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 3881899240 ps |
| CPU time | 32.74 seconds |
| Started | May 19 12:49:52 PM PDT 24 |
| Finished | May 19 12:50:27 PM PDT 24 |
| Peak memory | 211208 kb |
| Host | smart-15f0a32c-2039-43ca-81c8-350ddc022c5a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3221000904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3221000904 |
| Directory | /workspace/36.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_smoke.324796071 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 708133321 ps |
| CPU time | 19.45 seconds |
| Started | May 19 12:49:55 PM PDT 24 |
| Finished | May 19 12:50:17 PM PDT 24 |
| Peak memory | 217388 kb |
| Host | smart-5c273401-61ed-4b7d-a9f4-f48125131996 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=324796071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.324796071 |
| Directory | /workspace/36.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.344514690 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 25327585900 ps |
| CPU time | 1108.82 seconds |
| Started | May 19 12:49:58 PM PDT 24 |
| Finished | May 19 01:08:28 PM PDT 24 |
| Peak memory | 228528 kb |
| Host | smart-20591777-d2cc-4b61-9f35-8e53c3d69723 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344514690 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.344514690 |
| Directory | /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_alert_test.629302078 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 15431429775 ps |
| CPU time | 25.14 seconds |
| Started | May 19 12:49:56 PM PDT 24 |
| Finished | May 19 12:50:23 PM PDT 24 |
| Peak memory | 211360 kb |
| Host | smart-4d24b39b-9839-4ddf-a361-949ca6835e8e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629302078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.629302078 |
| Directory | /workspace/37.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2701707085 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 74204369979 ps |
| CPU time | 339.32 seconds |
| Started | May 19 12:49:58 PM PDT 24 |
| Finished | May 19 12:55:38 PM PDT 24 |
| Peak memory | 236640 kb |
| Host | smart-0d5a3d1e-261a-4aa5-b782-fb0b976f227b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701707085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_ corrupt_sig_fatal_chk.2701707085 |
| Directory | /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3695196626 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 2464753275 ps |
| CPU time | 35.55 seconds |
| Started | May 19 12:49:54 PM PDT 24 |
| Finished | May 19 12:50:32 PM PDT 24 |
| Peak memory | 214708 kb |
| Host | smart-2c9dd35b-ac05-4db3-8637-12d3a6182e09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3695196626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3695196626 |
| Directory | /workspace/37.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1032983163 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 5333520452 ps |
| CPU time | 25.87 seconds |
| Started | May 19 12:49:52 PM PDT 24 |
| Finished | May 19 12:50:21 PM PDT 24 |
| Peak memory | 211740 kb |
| Host | smart-97da7055-0b98-4327-b529-ca66afc3d2c8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1032983163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1032983163 |
| Directory | /workspace/37.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_smoke.645049277 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 8648182239 ps |
| CPU time | 64.4 seconds |
| Started | May 19 12:49:56 PM PDT 24 |
| Finished | May 19 12:51:02 PM PDT 24 |
| Peak memory | 217520 kb |
| Host | smart-f4147f94-ec86-4637-b7c1-368b678d141f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=645049277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.645049277 |
| Directory | /workspace/37.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_stress_all.3889298878 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 26296092189 ps |
| CPU time | 63.25 seconds |
| Started | May 19 12:49:57 PM PDT 24 |
| Finished | May 19 12:51:02 PM PDT 24 |
| Peak memory | 218208 kb |
| Host | smart-16c6404f-b89d-4e18-8557-1ce3229840b8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889298878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 37.rom_ctrl_stress_all.3889298878 |
| Directory | /workspace/37.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_alert_test.3811980917 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 6829226493 ps |
| CPU time | 20.81 seconds |
| Started | May 19 12:50:00 PM PDT 24 |
| Finished | May 19 12:50:21 PM PDT 24 |
| Peak memory | 212308 kb |
| Host | smart-748bc46b-1bf7-4c49-a6f0-6b77dc315762 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811980917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3811980917 |
| Directory | /workspace/38.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1797280140 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 68245705544 ps |
| CPU time | 240.98 seconds |
| Started | May 19 12:50:02 PM PDT 24 |
| Finished | May 19 12:54:03 PM PDT 24 |
| Peak memory | 236268 kb |
| Host | smart-61f6cb39-a3a5-45f7-a475-f39a14cf181c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797280140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_ corrupt_sig_fatal_chk.1797280140 |
| Directory | /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.721210711 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 346547352 ps |
| CPU time | 18.99 seconds |
| Started | May 19 12:49:54 PM PDT 24 |
| Finished | May 19 12:50:16 PM PDT 24 |
| Peak memory | 214636 kb |
| Host | smart-4de7f248-cdbc-450c-963e-7ee38edd14c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=721210711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.721210711 |
| Directory | /workspace/38.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.300202649 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 22197999267 ps |
| CPU time | 24.13 seconds |
| Started | May 19 12:50:01 PM PDT 24 |
| Finished | May 19 12:50:26 PM PDT 24 |
| Peak memory | 212808 kb |
| Host | smart-9e08a8f7-3db4-4a56-9679-a33abaf2dd13 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=300202649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.300202649 |
| Directory | /workspace/38.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_smoke.3369704216 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 1425797344 ps |
| CPU time | 20.78 seconds |
| Started | May 19 12:49:59 PM PDT 24 |
| Finished | May 19 12:50:20 PM PDT 24 |
| Peak memory | 217088 kb |
| Host | smart-efe09b14-e7dc-4864-8a99-65f3d9f40242 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3369704216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3369704216 |
| Directory | /workspace/38.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_stress_all.2786432150 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 12585604350 ps |
| CPU time | 50.66 seconds |
| Started | May 19 12:50:04 PM PDT 24 |
| Finished | May 19 12:50:55 PM PDT 24 |
| Peak memory | 218052 kb |
| Host | smart-aaf22149-d3c4-41f1-a0b4-d9b0b73c0595 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786432150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 38.rom_ctrl_stress_all.2786432150 |
| Directory | /workspace/38.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_alert_test.4169058360 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 170897267 ps |
| CPU time | 8.56 seconds |
| Started | May 19 12:49:58 PM PDT 24 |
| Finished | May 19 12:50:08 PM PDT 24 |
| Peak memory | 211228 kb |
| Host | smart-b370d089-775a-4217-a571-ac5c34b021ee |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169058360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.4169058360 |
| Directory | /workspace/39.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2349032729 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 430414078441 ps |
| CPU time | 656.94 seconds |
| Started | May 19 12:49:59 PM PDT 24 |
| Finished | May 19 01:00:57 PM PDT 24 |
| Peak memory | 218976 kb |
| Host | smart-480966d2-16bb-4f96-b659-b01f87af8a73 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349032729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_ corrupt_sig_fatal_chk.2349032729 |
| Directory | /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.589865679 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4124532869 ps |
| CPU time | 26.5 seconds |
| Started | May 19 12:50:06 PM PDT 24 |
| Finished | May 19 12:50:33 PM PDT 24 |
| Peak memory | 212640 kb |
| Host | smart-fc182bba-07ad-4afe-936b-67e6263c6cfa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=589865679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.589865679 |
| Directory | /workspace/39.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4044219335 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 3685393138 ps |
| CPU time | 29.96 seconds |
| Started | May 19 12:50:01 PM PDT 24 |
| Finished | May 19 12:50:31 PM PDT 24 |
| Peak memory | 211388 kb |
| Host | smart-2bdbcd73-4ca3-4e36-a8bf-9e91028e8ace |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4044219335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4044219335 |
| Directory | /workspace/39.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_smoke.2279201777 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 374488956 ps |
| CPU time | 21 seconds |
| Started | May 19 12:49:57 PM PDT 24 |
| Finished | May 19 12:50:20 PM PDT 24 |
| Peak memory | 217052 kb |
| Host | smart-5c71287a-2a54-4432-aecc-7c414507819a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2279201777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2279201777 |
| Directory | /workspace/39.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_stress_all.4268211385 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 11822437948 ps |
| CPU time | 45.68 seconds |
| Started | May 19 12:49:56 PM PDT 24 |
| Finished | May 19 12:50:44 PM PDT 24 |
| Peak memory | 216808 kb |
| Host | smart-021e7ab4-9070-4b30-a725-62ac26248331 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268211385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 39.rom_ctrl_stress_all.4268211385 |
| Directory | /workspace/39.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_alert_test.2033183695 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 13034365614 ps |
| CPU time | 27.46 seconds |
| Started | May 19 12:49:32 PM PDT 24 |
| Finished | May 19 12:50:04 PM PDT 24 |
| Peak memory | 212172 kb |
| Host | smart-d9fefd6f-5b9e-49e6-9f8c-30e048870a98 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033183695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2033183695 |
| Directory | /workspace/4.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2622601758 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 435952380222 ps |
| CPU time | 822.01 seconds |
| Started | May 19 12:49:26 PM PDT 24 |
| Finished | May 19 01:03:13 PM PDT 24 |
| Peak memory | 225508 kb |
| Host | smart-82e91c92-4f2b-4b1c-8f11-a191299ed9fe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622601758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c orrupt_sig_fatal_chk.2622601758 |
| Directory | /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.791674573 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3847178162 ps |
| CPU time | 31.96 seconds |
| Started | May 19 12:49:31 PM PDT 24 |
| Finished | May 19 12:50:08 PM PDT 24 |
| Peak memory | 214656 kb |
| Host | smart-f8acb9f3-ccfc-4f36-8fa6-9ca5358a6b48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=791674573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.791674573 |
| Directory | /workspace/4.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1536168803 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 916738402 ps |
| CPU time | 16.1 seconds |
| Started | May 19 12:49:31 PM PDT 24 |
| Finished | May 19 12:49:53 PM PDT 24 |
| Peak memory | 211048 kb |
| Host | smart-cf98a02c-49d2-46ff-b36b-d115687159d8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1536168803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1536168803 |
| Directory | /workspace/4.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_smoke.708718734 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1423745523 ps |
| CPU time | 20.21 seconds |
| Started | May 19 12:49:31 PM PDT 24 |
| Finished | May 19 12:49:56 PM PDT 24 |
| Peak memory | 215648 kb |
| Host | smart-145e589f-be8a-4010-9c41-166272df7225 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=708718734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.708718734 |
| Directory | /workspace/4.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_stress_all.2493654688 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 2305450118 ps |
| CPU time | 52.43 seconds |
| Started | May 19 12:49:44 PM PDT 24 |
| Finished | May 19 12:50:39 PM PDT 24 |
| Peak memory | 219316 kb |
| Host | smart-44a2177f-f934-4276-a6ba-4cef7b9445c0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493654688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 4.rom_ctrl_stress_all.2493654688 |
| Directory | /workspace/4.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2957977543 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 115416070305 ps |
| CPU time | 4162.23 seconds |
| Started | May 19 12:49:32 PM PDT 24 |
| Finished | May 19 01:59:00 PM PDT 24 |
| Peak memory | 248448 kb |
| Host | smart-81e14e29-8e28-4785-a2fa-8ccd96180177 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957977543 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2957977543 |
| Directory | /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_alert_test.3197341799 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 36404711930 ps |
| CPU time | 32.56 seconds |
| Started | May 19 12:50:03 PM PDT 24 |
| Finished | May 19 12:50:36 PM PDT 24 |
| Peak memory | 211408 kb |
| Host | smart-11bd8827-7d55-4337-ad7e-a457b52f8034 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197341799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3197341799 |
| Directory | /workspace/40.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3872382780 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 23908880532 ps |
| CPU time | 352.31 seconds |
| Started | May 19 12:50:06 PM PDT 24 |
| Finished | May 19 12:56:00 PM PDT 24 |
| Peak memory | 217316 kb |
| Host | smart-83e93e41-bfae-4f40-8864-df911d372694 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872382780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_ corrupt_sig_fatal_chk.3872382780 |
| Directory | /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2605876480 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 56190535579 ps |
| CPU time | 51.23 seconds |
| Started | May 19 12:49:58 PM PDT 24 |
| Finished | May 19 12:50:51 PM PDT 24 |
| Peak memory | 214968 kb |
| Host | smart-fe9dffb2-c619-4d2a-9934-d842888f5a9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2605876480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2605876480 |
| Directory | /workspace/40.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1360372577 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 696414756 ps |
| CPU time | 10.45 seconds |
| Started | May 19 12:50:06 PM PDT 24 |
| Finished | May 19 12:50:17 PM PDT 24 |
| Peak memory | 211264 kb |
| Host | smart-69faa8a7-3512-4f8b-a6d2-5d1dbdaed1ed |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1360372577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1360372577 |
| Directory | /workspace/40.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_smoke.2138996670 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 6703538095 ps |
| CPU time | 71.84 seconds |
| Started | May 19 12:50:01 PM PDT 24 |
| Finished | May 19 12:51:13 PM PDT 24 |
| Peak memory | 215240 kb |
| Host | smart-626315ad-a6c8-42c8-a7bc-36dd53ed22e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2138996670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2138996670 |
| Directory | /workspace/40.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_stress_all.3056294272 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 24928820949 ps |
| CPU time | 64.06 seconds |
| Started | May 19 12:49:59 PM PDT 24 |
| Finished | May 19 12:51:04 PM PDT 24 |
| Peak memory | 217916 kb |
| Host | smart-0fac4a7c-3a3a-4012-8402-fd685af6a322 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056294272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 40.rom_ctrl_stress_all.3056294272 |
| Directory | /workspace/40.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_alert_test.2909299070 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 8520862894 ps |
| CPU time | 20.71 seconds |
| Started | May 19 12:50:05 PM PDT 24 |
| Finished | May 19 12:50:27 PM PDT 24 |
| Peak memory | 212196 kb |
| Host | smart-db399d9e-08a7-42a7-af23-a4a24313ce64 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909299070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2909299070 |
| Directory | /workspace/41.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3461268378 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 114968174481 ps |
| CPU time | 550.46 seconds |
| Started | May 19 12:50:05 PM PDT 24 |
| Finished | May 19 12:59:16 PM PDT 24 |
| Peak memory | 237700 kb |
| Host | smart-2c114174-199c-41f4-b911-2d32f3b0640b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461268378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_ corrupt_sig_fatal_chk.3461268378 |
| Directory | /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1008799927 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 16383646187 ps |
| CPU time | 45 seconds |
| Started | May 19 12:50:05 PM PDT 24 |
| Finished | May 19 12:50:51 PM PDT 24 |
| Peak memory | 215216 kb |
| Host | smart-acdb6808-e3d2-47a7-b00d-7044b601073e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1008799927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1008799927 |
| Directory | /workspace/41.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1086609166 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 4941930466 ps |
| CPU time | 18.94 seconds |
| Started | May 19 12:50:04 PM PDT 24 |
| Finished | May 19 12:50:24 PM PDT 24 |
| Peak memory | 212752 kb |
| Host | smart-58e13b83-e2de-40d6-92a7-8c4606015f5e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1086609166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1086609166 |
| Directory | /workspace/41.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_smoke.694548488 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 5005082195 ps |
| CPU time | 49.51 seconds |
| Started | May 19 12:50:05 PM PDT 24 |
| Finished | May 19 12:50:55 PM PDT 24 |
| Peak memory | 217940 kb |
| Host | smart-efc0bf77-8b77-4576-b131-bf0a269df6c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=694548488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.694548488 |
| Directory | /workspace/41.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_stress_all.1459546680 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 16294869627 ps |
| CPU time | 35.1 seconds |
| Started | May 19 12:50:00 PM PDT 24 |
| Finished | May 19 12:50:36 PM PDT 24 |
| Peak memory | 214024 kb |
| Host | smart-bf5e90b8-1415-4f51-9ac7-16f064782e7b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459546680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 41.rom_ctrl_stress_all.1459546680 |
| Directory | /workspace/41.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_alert_test.3783892434 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 22414658763 ps |
| CPU time | 30.26 seconds |
| Started | May 19 12:50:10 PM PDT 24 |
| Finished | May 19 12:50:41 PM PDT 24 |
| Peak memory | 212560 kb |
| Host | smart-99774038-aad8-4977-bc37-cd8a9fea5abc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783892434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3783892434 |
| Directory | /workspace/42.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.153158168 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 358865650010 ps |
| CPU time | 557.44 seconds |
| Started | May 19 12:50:08 PM PDT 24 |
| Finished | May 19 12:59:26 PM PDT 24 |
| Peak memory | 217180 kb |
| Host | smart-55a25aaf-1bb5-4ab5-b29d-89f1101dd895 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153158168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c orrupt_sig_fatal_chk.153158168 |
| Directory | /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.30419553 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 26167098882 ps |
| CPU time | 61.64 seconds |
| Started | May 19 12:50:08 PM PDT 24 |
| Finished | May 19 12:51:10 PM PDT 24 |
| Peak memory | 214980 kb |
| Host | smart-f9e777e4-1c87-4634-bf53-653e2e2fdcd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30419553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.30419553 |
| Directory | /workspace/42.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1033964446 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 344597893 ps |
| CPU time | 12.79 seconds |
| Started | May 19 12:50:09 PM PDT 24 |
| Finished | May 19 12:50:22 PM PDT 24 |
| Peak memory | 211232 kb |
| Host | smart-efb6fc36-3623-4f65-964b-2370e2038df7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1033964446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1033964446 |
| Directory | /workspace/42.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_smoke.1119103059 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 15668595797 ps |
| CPU time | 64.58 seconds |
| Started | May 19 12:50:05 PM PDT 24 |
| Finished | May 19 12:51:11 PM PDT 24 |
| Peak memory | 217608 kb |
| Host | smart-0e56cadc-0e08-43f5-8aa4-e7dfa50748ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1119103059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1119103059 |
| Directory | /workspace/42.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_stress_all.2421486260 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 9675679182 ps |
| CPU time | 49.86 seconds |
| Started | May 19 12:50:06 PM PDT 24 |
| Finished | May 19 12:50:57 PM PDT 24 |
| Peak memory | 218612 kb |
| Host | smart-35f1b32a-8197-4d53-96ce-d35ab2697abc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421486260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 42.rom_ctrl_stress_all.2421486260 |
| Directory | /workspace/42.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_alert_test.701132760 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4396474986 ps |
| CPU time | 33.06 seconds |
| Started | May 19 12:50:05 PM PDT 24 |
| Finished | May 19 12:50:40 PM PDT 24 |
| Peak memory | 211304 kb |
| Host | smart-d4fb2762-195b-494b-9442-5acc1d2e7241 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701132760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.701132760 |
| Directory | /workspace/43.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1558993045 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 195760465471 ps |
| CPU time | 890.29 seconds |
| Started | May 19 12:50:08 PM PDT 24 |
| Finished | May 19 01:04:59 PM PDT 24 |
| Peak memory | 238164 kb |
| Host | smart-04ca1411-15fc-4227-8e39-2d58a72bc6ac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558993045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_ corrupt_sig_fatal_chk.1558993045 |
| Directory | /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.380859568 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 12890314812 ps |
| CPU time | 41.9 seconds |
| Started | May 19 12:50:08 PM PDT 24 |
| Finished | May 19 12:50:51 PM PDT 24 |
| Peak memory | 215048 kb |
| Host | smart-9bb3cf7d-8308-405a-a45a-fbe181945fa8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=380859568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.380859568 |
| Directory | /workspace/43.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3324219372 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 259305712 ps |
| CPU time | 11.84 seconds |
| Started | May 19 12:50:04 PM PDT 24 |
| Finished | May 19 12:50:17 PM PDT 24 |
| Peak memory | 212088 kb |
| Host | smart-f67eff04-8c60-4a3a-a722-75557b1481be |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3324219372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3324219372 |
| Directory | /workspace/43.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_smoke.2921926399 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 2613647738 ps |
| CPU time | 28.26 seconds |
| Started | May 19 12:50:05 PM PDT 24 |
| Finished | May 19 12:50:35 PM PDT 24 |
| Peak memory | 217196 kb |
| Host | smart-e8ce37db-d0e8-405b-92d0-83108440ed72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2921926399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2921926399 |
| Directory | /workspace/43.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_stress_all.476230406 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 2562571371 ps |
| CPU time | 51.51 seconds |
| Started | May 19 12:50:06 PM PDT 24 |
| Finished | May 19 12:50:58 PM PDT 24 |
| Peak memory | 219272 kb |
| Host | smart-dfdee132-25e6-488d-adb8-1608521b9f59 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476230406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 43.rom_ctrl_stress_all.476230406 |
| Directory | /workspace/43.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_alert_test.1955524775 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 688822121 ps |
| CPU time | 8.62 seconds |
| Started | May 19 12:50:17 PM PDT 24 |
| Finished | May 19 12:50:27 PM PDT 24 |
| Peak memory | 211128 kb |
| Host | smart-275f0d03-4e20-4fb4-a967-1f2ccc3d0c36 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955524775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1955524775 |
| Directory | /workspace/44.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2809967104 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 127423510236 ps |
| CPU time | 479.83 seconds |
| Started | May 19 12:50:13 PM PDT 24 |
| Finished | May 19 12:58:13 PM PDT 24 |
| Peak memory | 233872 kb |
| Host | smart-c3ef8f8f-542f-4bd0-8863-3ac647295251 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809967104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_ corrupt_sig_fatal_chk.2809967104 |
| Directory | /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2710897239 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 17439932697 ps |
| CPU time | 70.18 seconds |
| Started | May 19 12:50:11 PM PDT 24 |
| Finished | May 19 12:51:22 PM PDT 24 |
| Peak memory | 213972 kb |
| Host | smart-5af3f584-185e-426e-b50b-b6063dc57c7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2710897239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2710897239 |
| Directory | /workspace/44.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3509573671 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 17119195926 ps |
| CPU time | 33.62 seconds |
| Started | May 19 12:50:09 PM PDT 24 |
| Finished | May 19 12:50:44 PM PDT 24 |
| Peak memory | 211204 kb |
| Host | smart-3989b3e6-58c3-4db5-9863-71c6748a2ecf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3509573671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3509573671 |
| Directory | /workspace/44.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_smoke.1614340015 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 365625157 ps |
| CPU time | 19.54 seconds |
| Started | May 19 12:50:09 PM PDT 24 |
| Finished | May 19 12:50:30 PM PDT 24 |
| Peak memory | 215632 kb |
| Host | smart-a7198d89-9e89-4c09-acb9-a91b46e6110d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1614340015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1614340015 |
| Directory | /workspace/44.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_stress_all.1465574832 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 30528472955 ps |
| CPU time | 65.13 seconds |
| Started | May 19 12:50:13 PM PDT 24 |
| Finished | May 19 12:51:18 PM PDT 24 |
| Peak memory | 218820 kb |
| Host | smart-6a611401-5b3d-40a2-8b18-e335c5836b23 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465574832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 44.rom_ctrl_stress_all.1465574832 |
| Directory | /workspace/44.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.173019110 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 52411173059 ps |
| CPU time | 1974.66 seconds |
| Started | May 19 12:50:11 PM PDT 24 |
| Finished | May 19 01:23:06 PM PDT 24 |
| Peak memory | 237564 kb |
| Host | smart-13ed9a5b-1ba5-4d05-8def-4c2175be4dc3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173019110 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.173019110 |
| Directory | /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_alert_test.1313681454 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 19136246013 ps |
| CPU time | 31.62 seconds |
| Started | May 19 12:50:14 PM PDT 24 |
| Finished | May 19 12:50:46 PM PDT 24 |
| Peak memory | 212232 kb |
| Host | smart-4bd9b2f4-a31c-4558-9f1b-da68581fa63e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313681454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1313681454 |
| Directory | /workspace/45.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1241689551 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 70871685345 ps |
| CPU time | 616.63 seconds |
| Started | May 19 12:50:10 PM PDT 24 |
| Finished | May 19 01:00:28 PM PDT 24 |
| Peak memory | 239916 kb |
| Host | smart-3a441cd6-1b6d-42e3-8ffc-4757b2567381 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241689551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_ corrupt_sig_fatal_chk.1241689551 |
| Directory | /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1739789637 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2634766739 ps |
| CPU time | 24.64 seconds |
| Started | May 19 12:50:16 PM PDT 24 |
| Finished | May 19 12:50:42 PM PDT 24 |
| Peak memory | 214780 kb |
| Host | smart-90b267a5-faaf-4cb6-92b9-ad8655e623f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1739789637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1739789637 |
| Directory | /workspace/45.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1583154229 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 719588060 ps |
| CPU time | 10.62 seconds |
| Started | May 19 12:50:10 PM PDT 24 |
| Finished | May 19 12:50:21 PM PDT 24 |
| Peak memory | 211400 kb |
| Host | smart-51d85f41-ae01-4bf4-8bd3-9d8562e3f038 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1583154229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1583154229 |
| Directory | /workspace/45.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_smoke.1039836242 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 2154792798 ps |
| CPU time | 36.19 seconds |
| Started | May 19 12:50:09 PM PDT 24 |
| Finished | May 19 12:50:46 PM PDT 24 |
| Peak memory | 216524 kb |
| Host | smart-9ea29fe3-e42a-48c7-90a8-9c76fef4a8da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1039836242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1039836242 |
| Directory | /workspace/45.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_stress_all.4050247644 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 386479309 ps |
| CPU time | 28.15 seconds |
| Started | May 19 12:50:11 PM PDT 24 |
| Finished | May 19 12:50:40 PM PDT 24 |
| Peak memory | 215180 kb |
| Host | smart-6038e242-1adb-4dea-a18d-954d1324ec9b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050247644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 45.rom_ctrl_stress_all.4050247644 |
| Directory | /workspace/45.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_alert_test.1628557761 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 3181464910 ps |
| CPU time | 28.35 seconds |
| Started | May 19 12:50:15 PM PDT 24 |
| Finished | May 19 12:50:44 PM PDT 24 |
| Peak memory | 211976 kb |
| Host | smart-94c538cf-5af4-40b1-876b-947924e23be6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628557761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1628557761 |
| Directory | /workspace/46.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.706571328 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 16898609384 ps |
| CPU time | 213.59 seconds |
| Started | May 19 12:50:20 PM PDT 24 |
| Finished | May 19 12:53:56 PM PDT 24 |
| Peak memory | 237628 kb |
| Host | smart-baf80151-0c95-4702-8d32-4ee2d18c92fb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706571328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c orrupt_sig_fatal_chk.706571328 |
| Directory | /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2670514299 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 14851981044 ps |
| CPU time | 60.48 seconds |
| Started | May 19 12:50:20 PM PDT 24 |
| Finished | May 19 12:51:22 PM PDT 24 |
| Peak memory | 219536 kb |
| Host | smart-a1980b1e-85ac-4db2-82e5-72024aa30678 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2670514299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2670514299 |
| Directory | /workspace/46.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.4064878749 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 16661736994 ps |
| CPU time | 16.39 seconds |
| Started | May 19 12:50:20 PM PDT 24 |
| Finished | May 19 12:50:38 PM PDT 24 |
| Peak memory | 212652 kb |
| Host | smart-fc3c6e38-772a-4cbe-8971-eb3da42d860f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4064878749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.4064878749 |
| Directory | /workspace/46.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_smoke.494436781 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 54455415967 ps |
| CPU time | 55.38 seconds |
| Started | May 19 12:50:25 PM PDT 24 |
| Finished | May 19 12:51:23 PM PDT 24 |
| Peak memory | 217392 kb |
| Host | smart-2385868c-9a04-48ec-bf0e-9da61cb0a23e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=494436781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.494436781 |
| Directory | /workspace/46.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_stress_all.4016811695 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 4063907419 ps |
| CPU time | 24.27 seconds |
| Started | May 19 12:50:16 PM PDT 24 |
| Finished | May 19 12:50:41 PM PDT 24 |
| Peak memory | 215500 kb |
| Host | smart-6d576a52-944d-49ad-8e4d-e303dd152e02 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016811695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 46.rom_ctrl_stress_all.4016811695 |
| Directory | /workspace/46.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_alert_test.145935272 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 338399022 ps |
| CPU time | 8.33 seconds |
| Started | May 19 12:50:24 PM PDT 24 |
| Finished | May 19 12:50:35 PM PDT 24 |
| Peak memory | 211240 kb |
| Host | smart-3d0366dd-11d9-4cb4-bda4-58698b9dc3e1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145935272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.145935272 |
| Directory | /workspace/47.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3316976461 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 251520587005 ps |
| CPU time | 705.6 seconds |
| Started | May 19 12:50:21 PM PDT 24 |
| Finished | May 19 01:02:09 PM PDT 24 |
| Peak memory | 237772 kb |
| Host | smart-f7688268-586d-4e86-839d-1127542fca37 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316976461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_ corrupt_sig_fatal_chk.3316976461 |
| Directory | /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1895802942 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 4457552711 ps |
| CPU time | 47.61 seconds |
| Started | May 19 12:50:19 PM PDT 24 |
| Finished | May 19 12:51:07 PM PDT 24 |
| Peak memory | 215092 kb |
| Host | smart-acadc8aa-1acc-476a-ad93-d09087284780 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1895802942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1895802942 |
| Directory | /workspace/47.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.969447472 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 3129505406 ps |
| CPU time | 15.25 seconds |
| Started | May 19 12:50:21 PM PDT 24 |
| Finished | May 19 12:50:38 PM PDT 24 |
| Peak memory | 212180 kb |
| Host | smart-e3462e13-b3d6-49d0-99b9-4a89d7f6a072 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=969447472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.969447472 |
| Directory | /workspace/47.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_smoke.2232578091 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 2977739152 ps |
| CPU time | 42.64 seconds |
| Started | May 19 12:50:19 PM PDT 24 |
| Finished | May 19 12:51:03 PM PDT 24 |
| Peak memory | 217144 kb |
| Host | smart-94175f9a-7bc8-409d-b255-65438c3ae466 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2232578091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2232578091 |
| Directory | /workspace/47.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_stress_all.1427232384 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 41208024772 ps |
| CPU time | 114.75 seconds |
| Started | May 19 12:50:19 PM PDT 24 |
| Finished | May 19 12:52:15 PM PDT 24 |
| Peak memory | 220740 kb |
| Host | smart-29813f89-cb1b-4cc9-92fc-52a89b930b32 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427232384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 47.rom_ctrl_stress_all.1427232384 |
| Directory | /workspace/47.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2131378322 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 12594662822 ps |
| CPU time | 536.43 seconds |
| Started | May 19 12:50:21 PM PDT 24 |
| Finished | May 19 12:59:20 PM PDT 24 |
| Peak memory | 228176 kb |
| Host | smart-f1533882-ba16-4fe8-a9a0-ab2752036468 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131378322 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2131378322 |
| Directory | /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_alert_test.2514357050 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 4043436462 ps |
| CPU time | 33.25 seconds |
| Started | May 19 12:50:26 PM PDT 24 |
| Finished | May 19 12:51:02 PM PDT 24 |
| Peak memory | 211780 kb |
| Host | smart-037c3e54-b19e-4f10-9339-d97926652c15 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514357050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2514357050 |
| Directory | /workspace/48.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3873400223 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 29445294804 ps |
| CPU time | 386.67 seconds |
| Started | May 19 12:50:24 PM PDT 24 |
| Finished | May 19 12:56:53 PM PDT 24 |
| Peak memory | 240740 kb |
| Host | smart-f2bc6926-b8ea-4b2e-b9f4-df606ee2eb9a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873400223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_ corrupt_sig_fatal_chk.3873400223 |
| Directory | /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3843947522 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 11960824638 ps |
| CPU time | 54.49 seconds |
| Started | May 19 12:50:21 PM PDT 24 |
| Finished | May 19 12:51:17 PM PDT 24 |
| Peak memory | 215108 kb |
| Host | smart-db166986-02af-4aed-8f6c-c79c4b8643d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3843947522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3843947522 |
| Directory | /workspace/48.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.4289445556 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 4459221354 ps |
| CPU time | 35.62 seconds |
| Started | May 19 12:50:23 PM PDT 24 |
| Finished | May 19 12:51:01 PM PDT 24 |
| Peak memory | 211408 kb |
| Host | smart-b83ed51a-62b8-4333-a806-45d27843aa2b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4289445556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.4289445556 |
| Directory | /workspace/48.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_smoke.2096175369 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 26837062069 ps |
| CPU time | 68.99 seconds |
| Started | May 19 12:50:24 PM PDT 24 |
| Finished | May 19 12:51:35 PM PDT 24 |
| Peak memory | 218580 kb |
| Host | smart-94b990b9-7bfe-43be-bed0-2b3164afc4ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2096175369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2096175369 |
| Directory | /workspace/48.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_stress_all.1904292334 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 9352743114 ps |
| CPU time | 35.08 seconds |
| Started | May 19 12:50:21 PM PDT 24 |
| Finished | May 19 12:50:58 PM PDT 24 |
| Peak memory | 214228 kb |
| Host | smart-bde1630b-7971-4257-8978-f8176161d054 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904292334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 48.rom_ctrl_stress_all.1904292334 |
| Directory | /workspace/48.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_alert_test.3355078052 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 4016662363 ps |
| CPU time | 32.15 seconds |
| Started | May 19 12:50:29 PM PDT 24 |
| Finished | May 19 12:51:03 PM PDT 24 |
| Peak memory | 211792 kb |
| Host | smart-7dbfe2e3-3535-4873-aec5-f25dbfa7de62 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355078052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3355078052 |
| Directory | /workspace/49.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3708113660 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 172257946050 ps |
| CPU time | 857.6 seconds |
| Started | May 19 12:50:23 PM PDT 24 |
| Finished | May 19 01:04:43 PM PDT 24 |
| Peak memory | 239472 kb |
| Host | smart-392d338f-04bf-4fa9-b403-57d7e3b6dcef |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708113660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_ corrupt_sig_fatal_chk.3708113660 |
| Directory | /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.907014173 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 1375101300 ps |
| CPU time | 18.98 seconds |
| Started | May 19 12:50:25 PM PDT 24 |
| Finished | May 19 12:50:47 PM PDT 24 |
| Peak memory | 214540 kb |
| Host | smart-09e1042f-d4c6-468d-b456-f005b5e33d0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=907014173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.907014173 |
| Directory | /workspace/49.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2286665537 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 446878405 ps |
| CPU time | 13.95 seconds |
| Started | May 19 12:50:23 PM PDT 24 |
| Finished | May 19 12:50:39 PM PDT 24 |
| Peak memory | 211284 kb |
| Host | smart-7dafb419-e356-417c-b1ad-2ce1ede627c7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2286665537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2286665537 |
| Directory | /workspace/49.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_smoke.121044106 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 5611961131 ps |
| CPU time | 60.55 seconds |
| Started | May 19 12:50:23 PM PDT 24 |
| Finished | May 19 12:51:26 PM PDT 24 |
| Peak memory | 217976 kb |
| Host | smart-b6513036-06e7-4525-adb9-6b2d8707a31c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=121044106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.121044106 |
| Directory | /workspace/49.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_stress_all.576112115 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 7532182616 ps |
| CPU time | 49.66 seconds |
| Started | May 19 12:50:25 PM PDT 24 |
| Finished | May 19 12:51:17 PM PDT 24 |
| Peak memory | 215972 kb |
| Host | smart-260c1c09-03f0-4e7f-b67d-95ee76d7a061 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576112115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 49.rom_ctrl_stress_all.576112115 |
| Directory | /workspace/49.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3965220252 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 406572114382 ps |
| CPU time | 2611.7 seconds |
| Started | May 19 12:50:23 PM PDT 24 |
| Finished | May 19 01:33:57 PM PDT 24 |
| Peak memory | 244056 kb |
| Host | smart-a8d3331c-46a6-4bb7-a5ee-ddb285a57487 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965220252 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.3965220252 |
| Directory | /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_alert_test.2136427963 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 176015246 ps |
| CPU time | 8.41 seconds |
| Started | May 19 12:49:33 PM PDT 24 |
| Finished | May 19 12:49:46 PM PDT 24 |
| Peak memory | 211276 kb |
| Host | smart-b39859eb-3ec8-4cd1-9278-0905493fd8e6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136427963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2136427963 |
| Directory | /workspace/5.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.367279667 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 225186100348 ps |
| CPU time | 335.45 seconds |
| Started | May 19 12:49:44 PM PDT 24 |
| Finished | May 19 12:55:22 PM PDT 24 |
| Peak memory | 237820 kb |
| Host | smart-b64dc204-5e6a-43e8-9e47-0baf5045af1f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367279667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co rrupt_sig_fatal_chk.367279667 |
| Directory | /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.632267999 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 24506820368 ps |
| CPU time | 54.03 seconds |
| Started | May 19 12:49:27 PM PDT 24 |
| Finished | May 19 12:50:26 PM PDT 24 |
| Peak memory | 215480 kb |
| Host | smart-837ced6c-0cc2-4a15-b3e8-d189ce2b248a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=632267999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.632267999 |
| Directory | /workspace/5.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1308020774 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 6252909989 ps |
| CPU time | 26.01 seconds |
| Started | May 19 12:49:37 PM PDT 24 |
| Finished | May 19 12:50:06 PM PDT 24 |
| Peak memory | 212780 kb |
| Host | smart-d324ea49-e1e5-4b66-be68-e4ad9c129148 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1308020774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1308020774 |
| Directory | /workspace/5.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_smoke.1740451016 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 10758638276 ps |
| CPU time | 59.6 seconds |
| Started | May 19 12:49:29 PM PDT 24 |
| Finished | May 19 12:50:33 PM PDT 24 |
| Peak memory | 217584 kb |
| Host | smart-09788bd3-630b-4be8-9821-aa8fd45be98c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1740451016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1740451016 |
| Directory | /workspace/5.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_stress_all.3235339876 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 210585386 ps |
| CPU time | 11.2 seconds |
| Started | May 19 12:49:29 PM PDT 24 |
| Finished | May 19 12:49:45 PM PDT 24 |
| Peak memory | 213404 kb |
| Host | smart-8397481e-b1dd-452d-92fb-3addfe801e9c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235339876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 5.rom_ctrl_stress_all.3235339876 |
| Directory | /workspace/5.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_alert_test.3673433179 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 20415960715 ps |
| CPU time | 26.52 seconds |
| Started | May 19 12:49:48 PM PDT 24 |
| Finished | May 19 12:50:18 PM PDT 24 |
| Peak memory | 211480 kb |
| Host | smart-cadd899c-73c7-4862-9e5d-d5df078a9e09 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673433179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3673433179 |
| Directory | /workspace/6.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2716983448 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 64785360467 ps |
| CPU time | 640.59 seconds |
| Started | May 19 12:49:28 PM PDT 24 |
| Finished | May 19 01:00:12 PM PDT 24 |
| Peak memory | 233824 kb |
| Host | smart-df07fd91-8fd9-4ecd-bf44-72e555dc61fc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716983448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c orrupt_sig_fatal_chk.2716983448 |
| Directory | /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.65246781 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 30787682193 ps |
| CPU time | 68.48 seconds |
| Started | May 19 12:49:32 PM PDT 24 |
| Finished | May 19 12:50:46 PM PDT 24 |
| Peak memory | 215060 kb |
| Host | smart-fc968dbb-f42f-4580-a95f-943195b8c834 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=65246781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.65246781 |
| Directory | /workspace/6.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2292746502 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 2354329405 ps |
| CPU time | 23.86 seconds |
| Started | May 19 12:49:28 PM PDT 24 |
| Finished | May 19 12:49:56 PM PDT 24 |
| Peak memory | 211212 kb |
| Host | smart-29ad87a8-7641-4a65-99cb-b8fa01a53a83 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2292746502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2292746502 |
| Directory | /workspace/6.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_smoke.1174401366 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 28791374532 ps |
| CPU time | 68.49 seconds |
| Started | May 19 12:49:33 PM PDT 24 |
| Finished | May 19 12:50:47 PM PDT 24 |
| Peak memory | 217804 kb |
| Host | smart-d47e5048-f6a5-4ad6-a9b5-c6d560b65618 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1174401366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1174401366 |
| Directory | /workspace/6.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_stress_all.1497395672 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 3155978940 ps |
| CPU time | 49.43 seconds |
| Started | May 19 12:49:31 PM PDT 24 |
| Finished | May 19 12:50:25 PM PDT 24 |
| Peak memory | 219312 kb |
| Host | smart-ab9a4119-0229-4897-b204-55941acc0cbf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497395672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 6.rom_ctrl_stress_all.1497395672 |
| Directory | /workspace/6.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_alert_test.3111416561 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 167444479 ps |
| CPU time | 8.51 seconds |
| Started | May 19 12:49:30 PM PDT 24 |
| Finished | May 19 12:49:43 PM PDT 24 |
| Peak memory | 211608 kb |
| Host | smart-b1c39344-fdc2-4f63-afaa-52bdfd595b39 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111416561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3111416561 |
| Directory | /workspace/7.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1399284311 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 66864199078 ps |
| CPU time | 679.32 seconds |
| Started | May 19 12:49:41 PM PDT 24 |
| Finished | May 19 01:01:03 PM PDT 24 |
| Peak memory | 217052 kb |
| Host | smart-c5ef2c06-b28b-45d0-9b8b-a42019551047 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399284311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c orrupt_sig_fatal_chk.1399284311 |
| Directory | /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.940181390 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 2095942229 ps |
| CPU time | 14 seconds |
| Started | May 19 12:49:35 PM PDT 24 |
| Finished | May 19 12:49:53 PM PDT 24 |
| Peak memory | 211940 kb |
| Host | smart-2d59565e-9824-47be-a733-7f440498acca |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=940181390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.940181390 |
| Directory | /workspace/7.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_smoke.3101166331 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 14900750707 ps |
| CPU time | 54.12 seconds |
| Started | May 19 12:49:46 PM PDT 24 |
| Finished | May 19 12:50:43 PM PDT 24 |
| Peak memory | 216816 kb |
| Host | smart-75aa1191-976f-4cb6-b988-89ed9b13d406 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3101166331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3101166331 |
| Directory | /workspace/7.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_stress_all.115927074 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 3486205586 ps |
| CPU time | 27.83 seconds |
| Started | May 19 12:49:30 PM PDT 24 |
| Finished | May 19 12:50:03 PM PDT 24 |
| Peak memory | 212188 kb |
| Host | smart-ba30e469-b334-4d34-a3bd-67c2ac8fa6e6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115927074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.rom_ctrl_stress_all.115927074 |
| Directory | /workspace/7.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_alert_test.3287745899 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 313385819 ps |
| CPU time | 8.19 seconds |
| Started | May 19 12:49:37 PM PDT 24 |
| Finished | May 19 12:49:49 PM PDT 24 |
| Peak memory | 211216 kb |
| Host | smart-69bd7ccc-ca84-424d-9b9b-ae599f9785c9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287745899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3287745899 |
| Directory | /workspace/8.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3369161215 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 14098863157 ps |
| CPU time | 319.49 seconds |
| Started | May 19 12:49:41 PM PDT 24 |
| Finished | May 19 12:55:03 PM PDT 24 |
| Peak memory | 235944 kb |
| Host | smart-25b86dd3-11a4-436d-b427-2e933300326f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369161215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c orrupt_sig_fatal_chk.3369161215 |
| Directory | /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3009492898 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 12434967078 ps |
| CPU time | 40.94 seconds |
| Started | May 19 12:49:31 PM PDT 24 |
| Finished | May 19 12:50:17 PM PDT 24 |
| Peak memory | 214944 kb |
| Host | smart-a87305ea-3b6e-49a8-b081-c4e02f8467be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3009492898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3009492898 |
| Directory | /workspace/8.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.746411662 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 3843438174 ps |
| CPU time | 33.21 seconds |
| Started | May 19 12:49:45 PM PDT 24 |
| Finished | May 19 12:50:22 PM PDT 24 |
| Peak memory | 212120 kb |
| Host | smart-b58b5ec0-27c2-4bd4-bb5f-5bf79573ff5a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=746411662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.746411662 |
| Directory | /workspace/8.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_smoke.1064004899 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 366736896 ps |
| CPU time | 19.36 seconds |
| Started | May 19 12:49:34 PM PDT 24 |
| Finished | May 19 12:49:58 PM PDT 24 |
| Peak memory | 217664 kb |
| Host | smart-8e383a85-0025-49a6-95ef-9dd2b1a5a5e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1064004899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1064004899 |
| Directory | /workspace/8.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_stress_all.4106225734 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 8699277725 ps |
| CPU time | 35.24 seconds |
| Started | May 19 12:49:28 PM PDT 24 |
| Finished | May 19 12:50:07 PM PDT 24 |
| Peak memory | 212516 kb |
| Host | smart-e5d372bc-355b-4e82-90e5-8b9a59b3797f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106225734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 8.rom_ctrl_stress_all.4106225734 |
| Directory | /workspace/8.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_alert_test.622497310 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 6701561634 ps |
| CPU time | 28.28 seconds |
| Started | May 19 12:49:43 PM PDT 24 |
| Finished | May 19 12:50:15 PM PDT 24 |
| Peak memory | 211320 kb |
| Host | smart-e3edc624-0116-4b48-8e30-049bd8741323 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622497310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.622497310 |
| Directory | /workspace/9.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.229038362 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 144896504101 ps |
| CPU time | 448.55 seconds |
| Started | May 19 12:49:41 PM PDT 24 |
| Finished | May 19 12:57:13 PM PDT 24 |
| Peak memory | 224516 kb |
| Host | smart-0bb3a468-9f0b-4586-a220-e6fc289335a6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229038362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co rrupt_sig_fatal_chk.229038362 |
| Directory | /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.57591133 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 141427265272 ps |
| CPU time | 66.26 seconds |
| Started | May 19 12:49:41 PM PDT 24 |
| Finished | May 19 12:50:50 PM PDT 24 |
| Peak memory | 214048 kb |
| Host | smart-40323543-e527-478b-bb91-a9fd8e9a100b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=57591133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.57591133 |
| Directory | /workspace/9.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2766182342 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 180596916 ps |
| CPU time | 10.12 seconds |
| Started | May 19 12:49:29 PM PDT 24 |
| Finished | May 19 12:49:44 PM PDT 24 |
| Peak memory | 212020 kb |
| Host | smart-e46d577e-3667-4f95-a53a-af0fcb265589 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2766182342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2766182342 |
| Directory | /workspace/9.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_smoke.3407462989 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 28140184203 ps |
| CPU time | 77.65 seconds |
| Started | May 19 12:49:27 PM PDT 24 |
| Finished | May 19 12:50:48 PM PDT 24 |
| Peak memory | 218168 kb |
| Host | smart-0c039ece-e224-4c77-9647-b2c63906214f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3407462989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3407462989 |
| Directory | /workspace/9.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_stress_all.13236964 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1933965251 ps |
| CPU time | 30.93 seconds |
| Started | May 19 12:49:32 PM PDT 24 |
| Finished | May 19 12:50:08 PM PDT 24 |
| Peak memory | 219180 kb |
| Host | smart-7691b2bb-606e-4cfc-a355-e6ad4d2f04c5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13236964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 9.rom_ctrl_stress_all.13236964 |
| Directory | /workspace/9.rom_ctrl_stress_all/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |