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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 96.97 93.44 97.88 100.00 98.69 98.03 99.07


Total test records in report: 463
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T301 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2782738277 May 21 12:39:09 PM PDT 24 May 21 12:52:40 PM PDT 24 80913586700 ps
T302 /workspace/coverage/default/4.rom_ctrl_stress_all.993746449 May 21 12:38:25 PM PDT 24 May 21 12:39:09 PM PDT 24 3592756680 ps
T303 /workspace/coverage/default/2.rom_ctrl_stress_all.2786972906 May 21 12:38:26 PM PDT 24 May 21 12:39:40 PM PDT 24 27101545729 ps
T304 /workspace/coverage/default/28.rom_ctrl_alert_test.2806746640 May 21 12:38:48 PM PDT 24 May 21 12:39:26 PM PDT 24 3404221788 ps
T305 /workspace/coverage/default/49.rom_ctrl_smoke.2470759360 May 21 12:39:07 PM PDT 24 May 21 12:40:06 PM PDT 24 5148448947 ps
T306 /workspace/coverage/default/3.rom_ctrl_alert_test.2443318759 May 21 12:38:31 PM PDT 24 May 21 12:38:53 PM PDT 24 519026124 ps
T307 /workspace/coverage/default/34.rom_ctrl_stress_all.3933055547 May 21 12:38:57 PM PDT 24 May 21 12:42:04 PM PDT 24 86831512167 ps
T308 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1513683649 May 21 12:38:24 PM PDT 24 May 21 12:38:46 PM PDT 24 762257894 ps
T309 /workspace/coverage/default/2.rom_ctrl_smoke.1301140531 May 21 12:38:26 PM PDT 24 May 21 12:39:48 PM PDT 24 7428493309 ps
T310 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1048853325 May 21 12:38:54 PM PDT 24 May 21 12:39:33 PM PDT 24 11100843743 ps
T311 /workspace/coverage/default/17.rom_ctrl_stress_all.2176526497 May 21 12:38:47 PM PDT 24 May 21 12:41:51 PM PDT 24 17636835202 ps
T312 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1613407232 May 21 12:39:13 PM PDT 24 May 21 12:46:12 PM PDT 24 19364147016 ps
T313 /workspace/coverage/default/9.rom_ctrl_alert_test.1056241767 May 21 12:38:27 PM PDT 24 May 21 12:38:48 PM PDT 24 516485236 ps
T30 /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.504984953 May 21 12:39:03 PM PDT 24 May 21 02:32:08 PM PDT 24 59950139559 ps
T314 /workspace/coverage/default/43.rom_ctrl_smoke.3098689977 May 21 12:39:16 PM PDT 24 May 21 12:40:12 PM PDT 24 4474162354 ps
T315 /workspace/coverage/default/25.rom_ctrl_alert_test.1676926856 May 21 12:38:52 PM PDT 24 May 21 12:39:13 PM PDT 24 915817191 ps
T316 /workspace/coverage/default/33.rom_ctrl_alert_test.3166622516 May 21 12:39:08 PM PDT 24 May 21 12:39:50 PM PDT 24 4342132881 ps
T317 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2400508302 May 21 12:38:45 PM PDT 24 May 21 12:39:19 PM PDT 24 4096333443 ps
T318 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1548839816 May 21 12:38:44 PM PDT 24 May 21 12:59:58 PM PDT 24 101091435579 ps
T319 /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.761177558 May 21 12:39:18 PM PDT 24 May 21 01:39:07 PM PDT 24 82518803797 ps
T320 /workspace/coverage/default/46.rom_ctrl_smoke.3442406332 May 21 12:39:18 PM PDT 24 May 21 12:39:48 PM PDT 24 1358663288 ps
T321 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.106796176 May 21 12:38:54 PM PDT 24 May 21 12:39:40 PM PDT 24 4104998815 ps
T32 /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.583723903 May 21 12:38:48 PM PDT 24 May 21 02:07:47 PM PDT 24 89902702403 ps
T322 /workspace/coverage/default/1.rom_ctrl_alert_test.2950063264 May 21 12:38:40 PM PDT 24 May 21 12:39:13 PM PDT 24 36906760871 ps
T323 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1437271 May 21 12:38:50 PM PDT 24 May 21 12:39:34 PM PDT 24 1971308211 ps
T324 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.654036498 May 21 12:38:47 PM PDT 24 May 21 12:45:07 PM PDT 24 137237432810 ps
T325 /workspace/coverage/default/11.rom_ctrl_alert_test.3777502930 May 21 12:38:29 PM PDT 24 May 21 12:38:53 PM PDT 24 1199362718 ps
T326 /workspace/coverage/default/41.rom_ctrl_stress_all.3616452882 May 21 12:39:06 PM PDT 24 May 21 12:39:52 PM PDT 24 15722945021 ps
T327 /workspace/coverage/default/6.rom_ctrl_stress_all.3409221617 May 21 12:38:25 PM PDT 24 May 21 12:39:19 PM PDT 24 10370562586 ps
T328 /workspace/coverage/default/7.rom_ctrl_alert_test.688947399 May 21 12:38:27 PM PDT 24 May 21 12:39:07 PM PDT 24 13581253981 ps
T329 /workspace/coverage/default/19.rom_ctrl_smoke.1231912958 May 21 12:39:44 PM PDT 24 May 21 12:40:14 PM PDT 24 356365009 ps
T330 /workspace/coverage/default/22.rom_ctrl_stress_all.1037650311 May 21 12:38:44 PM PDT 24 May 21 12:39:49 PM PDT 24 3245082165 ps
T331 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2268162481 May 21 12:38:49 PM PDT 24 May 21 12:39:52 PM PDT 24 10610977511 ps
T332 /workspace/coverage/default/16.rom_ctrl_alert_test.1738671714 May 21 12:38:36 PM PDT 24 May 21 12:39:18 PM PDT 24 25736444731 ps
T37 /workspace/coverage/default/2.rom_ctrl_sec_cm.1743529600 May 21 12:38:41 PM PDT 24 May 21 12:41:00 PM PDT 24 7140383749 ps
T333 /workspace/coverage/default/8.rom_ctrl_stress_all.2688790893 May 21 12:38:26 PM PDT 24 May 21 12:41:12 PM PDT 24 84031403229 ps
T334 /workspace/coverage/default/29.rom_ctrl_stress_all.329127111 May 21 12:39:23 PM PDT 24 May 21 12:40:35 PM PDT 24 6192665125 ps
T335 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1418046632 May 21 12:38:51 PM PDT 24 May 21 12:48:14 PM PDT 24 232519690780 ps
T336 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1005952894 May 21 12:38:37 PM PDT 24 May 21 12:47:40 PM PDT 24 278036359685 ps
T337 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.878339146 May 21 12:38:31 PM PDT 24 May 21 12:39:12 PM PDT 24 12253933627 ps
T338 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3432597330 May 21 12:38:31 PM PDT 24 May 21 12:39:05 PM PDT 24 8215526081 ps
T339 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1103471403 May 21 12:38:50 PM PDT 24 May 21 12:39:13 PM PDT 24 183431333 ps
T340 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2041416322 May 21 12:38:49 PM PDT 24 May 21 12:39:56 PM PDT 24 6995535620 ps
T341 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1223786978 May 21 12:38:23 PM PDT 24 May 21 12:39:37 PM PDT 24 27464021988 ps
T342 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2055604164 May 21 12:38:50 PM PDT 24 May 21 12:40:03 PM PDT 24 111875788411 ps
T38 /workspace/coverage/default/4.rom_ctrl_sec_cm.2484700478 May 21 12:38:22 PM PDT 24 May 21 12:40:36 PM PDT 24 1121917031 ps
T343 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3082253010 May 21 12:39:53 PM PDT 24 May 21 12:40:17 PM PDT 24 941020341 ps
T344 /workspace/coverage/default/40.rom_ctrl_alert_test.1903480248 May 21 12:39:08 PM PDT 24 May 21 12:39:44 PM PDT 24 3256508964 ps
T345 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.250158827 May 21 12:38:48 PM PDT 24 May 21 12:42:51 PM PDT 24 217888072817 ps
T346 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2283914899 May 21 12:38:46 PM PDT 24 May 21 12:39:17 PM PDT 24 1503864154 ps
T347 /workspace/coverage/default/14.rom_ctrl_alert_test.1516121081 May 21 12:39:48 PM PDT 24 May 21 12:40:27 PM PDT 24 21756340448 ps
T348 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2206226220 May 21 12:38:45 PM PDT 24 May 21 12:39:52 PM PDT 24 25599685866 ps
T349 /workspace/coverage/default/1.rom_ctrl_stress_all.4130661052 May 21 12:38:29 PM PDT 24 May 21 12:39:41 PM PDT 24 7814814916 ps
T350 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4170887821 May 21 12:38:38 PM PDT 24 May 21 12:39:18 PM PDT 24 13389017282 ps
T351 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.593290859 May 21 12:38:51 PM PDT 24 May 21 12:39:54 PM PDT 24 10908041332 ps
T352 /workspace/coverage/default/46.rom_ctrl_stress_all.1941516614 May 21 12:39:00 PM PDT 24 May 21 12:41:25 PM PDT 24 12013392171 ps
T353 /workspace/coverage/default/46.rom_ctrl_alert_test.367997341 May 21 12:39:17 PM PDT 24 May 21 12:39:36 PM PDT 24 169051430 ps
T354 /workspace/coverage/default/18.rom_ctrl_alert_test.1575873732 May 21 12:38:47 PM PDT 24 May 21 12:39:17 PM PDT 24 1148585245 ps
T355 /workspace/coverage/default/12.rom_ctrl_stress_all.2996584312 May 21 12:38:43 PM PDT 24 May 21 12:39:42 PM PDT 24 2782136880 ps
T356 /workspace/coverage/default/38.rom_ctrl_smoke.3560906708 May 21 12:39:16 PM PDT 24 May 21 12:39:48 PM PDT 24 355583916 ps
T357 /workspace/coverage/default/30.rom_ctrl_alert_test.3070352632 May 21 12:39:05 PM PDT 24 May 21 12:39:28 PM PDT 24 1829560202 ps
T358 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1503877402 May 21 12:39:08 PM PDT 24 May 21 12:39:28 PM PDT 24 227426563 ps
T359 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.390865652 May 21 12:38:42 PM PDT 24 May 21 12:39:31 PM PDT 24 15483083988 ps
T360 /workspace/coverage/default/9.rom_ctrl_smoke.1723319136 May 21 12:38:34 PM PDT 24 May 21 12:39:43 PM PDT 24 4518404194 ps
T361 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3249063165 May 21 12:38:44 PM PDT 24 May 21 12:51:21 PM PDT 24 69125767435 ps
T362 /workspace/coverage/default/42.rom_ctrl_stress_all.954429374 May 21 12:39:18 PM PDT 24 May 21 12:40:12 PM PDT 24 3192175506 ps
T363 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1776497225 May 21 12:38:33 PM PDT 24 May 21 12:39:38 PM PDT 24 58045693710 ps
T364 /workspace/coverage/default/29.rom_ctrl_smoke.2764250602 May 21 12:38:53 PM PDT 24 May 21 12:40:02 PM PDT 24 22304264891 ps
T58 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3176059320 May 21 01:54:04 PM PDT 24 May 21 01:55:02 PM PDT 24 2205422567 ps
T59 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1413046325 May 21 01:54:16 PM PDT 24 May 21 01:54:53 PM PDT 24 9721302944 ps
T365 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.463298969 May 21 01:54:50 PM PDT 24 May 21 01:55:19 PM PDT 24 11061547277 ps
T60 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.230482237 May 21 01:54:49 PM PDT 24 May 21 01:55:12 PM PDT 24 2046229780 ps
T366 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1479021158 May 21 01:54:29 PM PDT 24 May 21 01:54:43 PM PDT 24 699997107 ps
T64 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4065767366 May 21 01:54:01 PM PDT 24 May 21 01:54:38 PM PDT 24 4285121049 ps
T95 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3692107729 May 21 01:53:42 PM PDT 24 May 21 01:54:09 PM PDT 24 12420085521 ps
T367 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.540791469 May 21 01:53:55 PM PDT 24 May 21 01:54:08 PM PDT 24 916939861 ps
T368 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2587783402 May 21 01:54:21 PM PDT 24 May 21 01:54:42 PM PDT 24 9542371897 ps
T369 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3521799313 May 21 01:53:47 PM PDT 24 May 21 01:54:15 PM PDT 24 11914475803 ps
T55 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1317876835 May 21 01:54:29 PM PDT 24 May 21 01:56:05 PM PDT 24 5256925103 ps
T370 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.766188437 May 21 01:53:54 PM PDT 24 May 21 01:54:04 PM PDT 24 171079784 ps
T371 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3777669164 May 21 01:54:55 PM PDT 24 May 21 01:55:25 PM PDT 24 13493273380 ps
T372 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4089602842 May 21 01:54:48 PM PDT 24 May 21 01:55:03 PM PDT 24 527458953 ps
T56 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1554246398 May 21 01:54:22 PM PDT 24 May 21 01:56:56 PM PDT 24 2491830150 ps
T373 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1223773476 May 21 01:53:41 PM PDT 24 May 21 01:54:00 PM PDT 24 6259532436 ps
T65 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.357979740 May 21 01:53:43 PM PDT 24 May 21 01:53:52 PM PDT 24 172400198 ps
T57 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2915583678 May 21 01:53:48 PM PDT 24 May 21 01:55:28 PM PDT 24 2955191425 ps
T98 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1950960603 May 21 01:54:15 PM PDT 24 May 21 01:56:53 PM PDT 24 1859747853 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1652006262 May 21 01:54:06 PM PDT 24 May 21 01:54:15 PM PDT 24 338395032 ps
T89 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2354801992 May 21 01:54:08 PM PDT 24 May 21 01:54:33 PM PDT 24 2979045431 ps
T66 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.149047333 May 21 01:54:30 PM PDT 24 May 21 01:54:48 PM PDT 24 2358357454 ps
T96 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2728692037 May 21 01:54:42 PM PDT 24 May 21 01:54:55 PM PDT 24 1072441010 ps
T99 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2073262899 May 21 01:54:19 PM PDT 24 May 21 01:55:50 PM PDT 24 1512257465 ps
T100 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4094947294 May 21 01:54:03 PM PDT 24 May 21 01:55:31 PM PDT 24 1006659045 ps
T375 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1157640451 May 21 01:53:42 PM PDT 24 May 21 01:55:06 PM PDT 24 875421941 ps
T90 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1858517219 May 21 01:53:48 PM PDT 24 May 21 01:54:12 PM PDT 24 6812502248 ps
T91 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1543352075 May 21 01:54:14 PM PDT 24 May 21 01:54:37 PM PDT 24 2436961667 ps
T376 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1475899891 May 21 01:54:30 PM PDT 24 May 21 01:55:05 PM PDT 24 3793722996 ps
T377 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3490080416 May 21 01:53:42 PM PDT 24 May 21 01:54:19 PM PDT 24 4240459724 ps
T378 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.657531885 May 21 01:54:30 PM PDT 24 May 21 01:54:53 PM PDT 24 2135719430 ps
T379 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2432310681 May 21 01:53:47 PM PDT 24 May 21 01:54:11 PM PDT 24 2482677390 ps
T380 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1529091924 May 21 01:53:54 PM PDT 24 May 21 01:54:03 PM PDT 24 661159235 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4255316817 May 21 01:53:54 PM PDT 24 May 21 01:54:23 PM PDT 24 4524497164 ps
T67 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3857518198 May 21 01:54:15 PM PDT 24 May 21 01:55:21 PM PDT 24 5003201815 ps
T382 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.901039485 May 21 01:53:46 PM PDT 24 May 21 01:54:00 PM PDT 24 345626010 ps
T68 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.212645848 May 21 01:54:13 PM PDT 24 May 21 01:54:45 PM PDT 24 23266127787 ps
T383 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2218398133 May 21 01:54:09 PM PDT 24 May 21 01:54:43 PM PDT 24 4268556237 ps
T97 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.981667383 May 21 01:54:42 PM PDT 24 May 21 01:56:18 PM PDT 24 48390823620 ps
T384 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3674364390 May 21 01:54:57 PM PDT 24 May 21 01:55:26 PM PDT 24 5445620331 ps
T385 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.572565897 May 21 01:54:15 PM PDT 24 May 21 01:54:37 PM PDT 24 7670507095 ps
T92 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2327883982 May 21 01:54:06 PM PDT 24 May 21 01:54:16 PM PDT 24 332473136 ps
T386 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.145703897 May 21 01:53:41 PM PDT 24 May 21 01:54:03 PM PDT 24 2043805299 ps
T387 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3861342836 May 21 01:53:48 PM PDT 24 May 21 01:54:02 PM PDT 24 3097267428 ps
T388 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.826859016 May 21 01:53:56 PM PDT 24 May 21 01:54:10 PM PDT 24 368842797 ps
T69 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.920040383 May 21 01:54:41 PM PDT 24 May 21 01:55:19 PM PDT 24 1431046634 ps
T70 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3961807278 May 21 01:53:49 PM PDT 24 May 21 01:56:39 PM PDT 24 19846819095 ps
T93 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3398946528 May 21 01:54:28 PM PDT 24 May 21 01:54:58 PM PDT 24 3994925607 ps
T389 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.865988458 May 21 01:54:40 PM PDT 24 May 21 01:55:14 PM PDT 24 8361129116 ps
T71 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1973959790 May 21 01:54:07 PM PDT 24 May 21 01:54:37 PM PDT 24 3836303575 ps
T102 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.588236569 May 21 01:54:50 PM PDT 24 May 21 01:57:30 PM PDT 24 457309176 ps
T390 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1427714482 May 21 01:54:14 PM PDT 24 May 21 01:57:15 PM PDT 24 22080494393 ps
T391 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1915508313 May 21 01:54:16 PM PDT 24 May 21 01:54:37 PM PDT 24 1819154922 ps
T392 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2732220430 May 21 01:54:01 PM PDT 24 May 21 01:54:12 PM PDT 24 665582273 ps
T393 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.971348409 May 21 01:54:16 PM PDT 24 May 21 01:54:28 PM PDT 24 1074699578 ps
T394 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.84818339 May 21 01:54:21 PM PDT 24 May 21 01:54:45 PM PDT 24 10585793834 ps
T395 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2113678925 May 21 01:53:55 PM PDT 24 May 21 01:54:15 PM PDT 24 17337173922 ps
T105 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3788632609 May 21 01:54:46 PM PDT 24 May 21 01:56:31 PM PDT 24 4408883603 ps
T72 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4215560631 May 21 01:54:33 PM PDT 24 May 21 01:55:05 PM PDT 24 4115940472 ps
T396 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1649933197 May 21 01:54:00 PM PDT 24 May 21 01:54:35 PM PDT 24 4441753388 ps
T397 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2193545825 May 21 01:53:48 PM PDT 24 May 21 01:54:03 PM PDT 24 961415626 ps
T80 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3112854662 May 21 01:54:30 PM PDT 24 May 21 01:56:46 PM PDT 24 16428808451 ps
T398 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2690523424 May 21 01:54:34 PM PDT 24 May 21 01:55:05 PM PDT 24 15677258040 ps
T399 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1939696933 May 21 01:54:16 PM PDT 24 May 21 01:54:34 PM PDT 24 2455090005 ps
T81 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.568575277 May 21 01:54:01 PM PDT 24 May 21 01:54:20 PM PDT 24 3822679679 ps
T400 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2194155553 May 21 01:54:43 PM PDT 24 May 21 01:55:16 PM PDT 24 8330295429 ps
T401 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1503322257 May 21 01:54:05 PM PDT 24 May 21 01:55:31 PM PDT 24 1909718444 ps
T402 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.316566853 May 21 01:54:40 PM PDT 24 May 21 01:55:51 PM PDT 24 4954662271 ps
T82 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1252390887 May 21 01:54:34 PM PDT 24 May 21 01:55:58 PM PDT 24 14797130217 ps
T403 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.358416946 May 21 01:53:49 PM PDT 24 May 21 01:54:05 PM PDT 24 751502988 ps
T404 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1391828839 May 21 01:54:40 PM PDT 24 May 21 01:54:50 PM PDT 24 258200957 ps
T405 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1153867634 May 21 01:54:43 PM PDT 24 May 21 01:55:07 PM PDT 24 6100389154 ps
T83 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3043739155 May 21 01:54:30 PM PDT 24 May 21 01:54:39 PM PDT 24 1649838118 ps
T406 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3990059038 May 21 01:54:14 PM PDT 24 May 21 01:55:12 PM PDT 24 4094760592 ps
T407 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.92691160 May 21 01:53:59 PM PDT 24 May 21 01:54:08 PM PDT 24 660956078 ps
T408 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3123408668 May 21 01:54:29 PM PDT 24 May 21 01:54:42 PM PDT 24 1741997250 ps
T409 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2782307790 May 21 01:54:34 PM PDT 24 May 21 01:54:46 PM PDT 24 1821040171 ps
T410 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1357482541 May 21 01:54:12 PM PDT 24 May 21 01:54:38 PM PDT 24 1736278461 ps
T84 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2105876515 May 21 01:54:30 PM PDT 24 May 21 01:57:06 PM PDT 24 32508525645 ps
T411 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3380255354 May 21 01:54:11 PM PDT 24 May 21 01:54:39 PM PDT 24 4081144788 ps
T85 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.796849874 May 21 01:54:48 PM PDT 24 May 21 01:56:17 PM PDT 24 4482407400 ps
T109 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1968670646 May 21 01:54:55 PM PDT 24 May 21 01:57:37 PM PDT 24 1682855499 ps
T412 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2775908452 May 21 01:54:49 PM PDT 24 May 21 01:55:11 PM PDT 24 3786153149 ps
T106 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2905392537 May 21 01:54:29 PM PDT 24 May 21 01:57:05 PM PDT 24 1146793340 ps
T413 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3018920482 May 21 01:54:30 PM PDT 24 May 21 01:54:56 PM PDT 24 4206203367 ps
T87 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1085497964 May 21 01:54:33 PM PDT 24 May 21 01:54:57 PM PDT 24 5294700123 ps
T88 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2834423372 May 21 01:54:26 PM PDT 24 May 21 01:55:21 PM PDT 24 2192843993 ps
T414 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.431941789 May 21 01:54:07 PM PDT 24 May 21 01:54:38 PM PDT 24 13469786870 ps
T415 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2278621018 May 21 01:53:47 PM PDT 24 May 21 01:53:57 PM PDT 24 169002576 ps
T416 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.772670900 May 21 01:54:06 PM PDT 24 May 21 01:54:31 PM PDT 24 2541930627 ps
T417 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.826933697 May 21 01:54:56 PM PDT 24 May 21 01:55:21 PM PDT 24 13483024581 ps
T418 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.788690941 May 21 01:54:34 PM PDT 24 May 21 01:55:11 PM PDT 24 3929729353 ps
T419 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1935811992 May 21 01:54:32 PM PDT 24 May 21 01:54:47 PM PDT 24 988310446 ps
T420 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1895192619 May 21 01:53:54 PM PDT 24 May 21 01:55:23 PM PDT 24 3111104984 ps
T421 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2843997341 May 21 01:54:02 PM PDT 24 May 21 01:54:20 PM PDT 24 2859013885 ps
T422 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3034102412 May 21 01:54:15 PM PDT 24 May 21 01:54:40 PM PDT 24 9877553410 ps
T423 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.859584159 May 21 01:54:36 PM PDT 24 May 21 01:54:46 PM PDT 24 721735044 ps
T424 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1057523540 May 21 01:53:40 PM PDT 24 May 21 01:53:56 PM PDT 24 980912747 ps
T425 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4128266750 May 21 01:53:41 PM PDT 24 May 21 01:53:58 PM PDT 24 353020949 ps
T426 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.895355931 May 21 01:53:55 PM PDT 24 May 21 01:54:35 PM PDT 24 715396084 ps
T427 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2031409252 May 21 01:53:55 PM PDT 24 May 21 01:54:30 PM PDT 24 8784785003 ps
T428 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2586680263 May 21 01:54:20 PM PDT 24 May 21 01:54:39 PM PDT 24 675970036 ps
T429 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3001176215 May 21 01:53:40 PM PDT 24 May 21 01:54:48 PM PDT 24 66139365505 ps
T430 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.925481507 May 21 01:54:29 PM PDT 24 May 21 01:54:39 PM PDT 24 1032191256 ps
T431 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1837598318 May 21 01:54:26 PM PDT 24 May 21 01:55:04 PM PDT 24 4604098447 ps
T432 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1010073133 May 21 01:54:41 PM PDT 24 May 21 01:54:52 PM PDT 24 338305906 ps
T433 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.740951192 May 21 01:53:54 PM PDT 24 May 21 01:54:18 PM PDT 24 3507449862 ps
T107 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1750956949 May 21 01:54:40 PM PDT 24 May 21 01:56:21 PM PDT 24 3173509443 ps
T434 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.451616005 May 21 01:54:02 PM PDT 24 May 21 01:54:20 PM PDT 24 418092668 ps
T435 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3623382810 May 21 01:54:33 PM PDT 24 May 21 01:54:56 PM PDT 24 6817463340 ps
T436 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3839077589 May 21 01:54:41 PM PDT 24 May 21 01:54:59 PM PDT 24 2890290049 ps
T103 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1065179919 May 21 01:54:34 PM PDT 24 May 21 01:55:58 PM PDT 24 232866771 ps
T437 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1411744403 May 21 01:54:08 PM PDT 24 May 21 01:54:25 PM PDT 24 1155122727 ps
T438 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2235233999 May 21 01:54:06 PM PDT 24 May 21 01:57:13 PM PDT 24 84842077527 ps
T439 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.196237466 May 21 01:54:25 PM PDT 24 May 21 01:54:51 PM PDT 24 11072218116 ps
T440 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.420862142 May 21 01:54:14 PM PDT 24 May 21 01:54:52 PM PDT 24 34898578843 ps
T441 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2613668042 May 21 01:54:41 PM PDT 24 May 21 01:54:51 PM PDT 24 364844149 ps
T442 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.515369365 May 21 01:54:48 PM PDT 24 May 21 01:55:08 PM PDT 24 8649153388 ps
T443 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.810253366 May 21 01:54:50 PM PDT 24 May 21 01:55:00 PM PDT 24 660876688 ps
T444 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1651328056 May 21 01:54:30 PM PDT 24 May 21 01:54:51 PM PDT 24 7892107998 ps
T101 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2694445408 May 21 01:54:16 PM PDT 24 May 21 01:56:51 PM PDT 24 1113220781 ps
T445 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3146045019 May 21 01:53:49 PM PDT 24 May 21 01:54:16 PM PDT 24 10113509964 ps
T446 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2920891917 May 21 01:54:56 PM PDT 24 May 21 01:55:12 PM PDT 24 978857409 ps
T447 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3880528647 May 21 01:54:01 PM PDT 24 May 21 01:54:18 PM PDT 24 178981172 ps
T104 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.804600158 May 21 01:54:34 PM PDT 24 May 21 01:56:12 PM PDT 24 10881039436 ps
T448 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.350947369 May 21 01:54:34 PM PDT 24 May 21 01:55:51 PM PDT 24 23140754007 ps
T449 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.395779739 May 21 01:54:41 PM PDT 24 May 21 01:55:09 PM PDT 24 3062534198 ps
T450 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.295764347 May 21 01:54:30 PM PDT 24 May 21 01:56:10 PM PDT 24 21485194980 ps
T451 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.57029201 May 21 01:54:48 PM PDT 24 May 21 01:55:05 PM PDT 24 3996500157 ps
T452 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3115897150 May 21 01:53:46 PM PDT 24 May 21 01:53:55 PM PDT 24 167447725 ps
T453 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3809637303 May 21 01:53:53 PM PDT 24 May 21 01:54:23 PM PDT 24 3448967272 ps
T454 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.831185547 May 21 01:54:02 PM PDT 24 May 21 01:54:31 PM PDT 24 6735539330 ps
T455 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3654106853 May 21 01:54:50 PM PDT 24 May 21 01:55:27 PM PDT 24 11272817129 ps
T456 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2281949633 May 21 01:54:35 PM PDT 24 May 21 01:55:06 PM PDT 24 7002900365 ps
T457 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4133310073 May 21 01:54:06 PM PDT 24 May 21 01:54:24 PM PDT 24 1201442419 ps
T458 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2586426690 May 21 01:54:20 PM PDT 24 May 21 01:54:30 PM PDT 24 217200165 ps
T110 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2871811171 May 21 01:54:08 PM PDT 24 May 21 01:56:44 PM PDT 24 564709352 ps
T111 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2770266815 May 21 01:54:25 PM PDT 24 May 21 01:56:03 PM PDT 24 14012510370 ps
T459 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1048134094 May 21 01:53:49 PM PDT 24 May 21 01:55:23 PM PDT 24 55466301500 ps
T460 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2093555519 May 21 01:54:47 PM PDT 24 May 21 01:55:56 PM PDT 24 4716831876 ps
T461 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3599416591 May 21 01:54:32 PM PDT 24 May 21 01:54:54 PM PDT 24 2600642810 ps
T462 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1062303688 May 21 01:54:22 PM PDT 24 May 21 01:54:51 PM PDT 24 2695397211 ps
T86 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3098154751 May 21 01:53:42 PM PDT 24 May 21 01:54:01 PM PDT 24 6251996752 ps
T463 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.115834525 May 21 01:53:55 PM PDT 24 May 21 01:54:15 PM PDT 24 5254080056 ps
T108 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1529178533 May 21 01:54:41 PM PDT 24 May 21 01:56:17 PM PDT 24 5152602912 ps

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.292761497
Short name T8
Test name
Test status
Simulation time 152255528177 ps
CPU time 378.66 seconds
Started May 21 12:38:52 PM PDT 24
Finished May 21 12:45:24 PM PDT 24
Peak memory 240960 kb
Host smart-d5559e54-fc93-49be-98fc-1d744a1d96ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292761497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.292761497
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2874446757
Short name T26
Test name
Test status
Simulation time 286880416800 ps
CPU time 2771.8 seconds
Started May 21 12:39:42 PM PDT 24
Finished May 21 01:26:04 PM PDT 24
Peak memory 244024 kb
Host smart-b4a6b476-303a-40ef-b612-40eaeece46eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874446757 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2874446757
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.280868907
Short name T10
Test name
Test status
Simulation time 1803857245 ps
CPU time 52.36 seconds
Started May 21 12:38:57 PM PDT 24
Finished May 21 12:40:01 PM PDT 24
Peak memory 219328 kb
Host smart-1be14dab-fd3f-4993-853a-094035a37c40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280868907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.280868907
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2390382211
Short name T17
Test name
Test status
Simulation time 26806144180 ps
CPU time 414.99 seconds
Started May 21 12:38:50 PM PDT 24
Finished May 21 12:45:58 PM PDT 24
Peak memory 237808 kb
Host smart-e70c85f6-399e-4969-a2e7-13cba582848a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390382211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2390382211
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1950960603
Short name T98
Test name
Test status
Simulation time 1859747853 ps
CPU time 157.01 seconds
Started May 21 01:54:15 PM PDT 24
Finished May 21 01:56:53 PM PDT 24
Peak memory 212964 kb
Host smart-1987a6a7-8afc-41b2-8162-6def1d0d5f5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950960603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1950960603
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.60275381
Short name T25
Test name
Test status
Simulation time 2345246037 ps
CPU time 229.88 seconds
Started May 21 12:38:26 PM PDT 24
Finished May 21 12:42:28 PM PDT 24
Peak memory 238244 kb
Host smart-34b0f56b-10fc-4239-9ee7-a9c453d1ed7d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60275381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.60275381
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3961807278
Short name T70
Test name
Test status
Simulation time 19846819095 ps
CPU time 168.99 seconds
Started May 21 01:53:49 PM PDT 24
Finished May 21 01:56:39 PM PDT 24
Peak memory 215848 kb
Host smart-164ed3e4-37c3-4b9b-9a4d-6907c75e7a8f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961807278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3961807278
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3788632609
Short name T105
Test name
Test status
Simulation time 4408883603 ps
CPU time 104.21 seconds
Started May 21 01:54:46 PM PDT 24
Finished May 21 01:56:31 PM PDT 24
Peak memory 214012 kb
Host smart-d58656a4-a08f-4353-98d8-57ef50fa8191
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788632609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3788632609
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3798713215
Short name T94
Test name
Test status
Simulation time 29860545343 ps
CPU time 299.15 seconds
Started May 21 12:38:48 PM PDT 24
Finished May 21 12:44:00 PM PDT 24
Peak memory 221632 kb
Host smart-8679cb8b-1046-4aa8-a330-c3f4a2afcb4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798713215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3798713215
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.583723903
Short name T32
Test name
Test status
Simulation time 89902702403 ps
CPU time 5325.7 seconds
Started May 21 12:38:48 PM PDT 24
Finished May 21 02:07:47 PM PDT 24
Peak memory 235972 kb
Host smart-654e6617-3681-4cb9-ad70-36818d221d2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583723903 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.583723903
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3393242391
Short name T24
Test name
Test status
Simulation time 662043868 ps
CPU time 8.37 seconds
Started May 21 12:38:53 PM PDT 24
Finished May 21 12:39:14 PM PDT 24
Peak memory 211400 kb
Host smart-e456628f-081e-470b-a46a-229e315733e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393242391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3393242391
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.4171029468
Short name T47
Test name
Test status
Simulation time 6534764721 ps
CPU time 59.04 seconds
Started May 21 12:38:45 PM PDT 24
Finished May 21 12:39:56 PM PDT 24
Peak memory 213992 kb
Host smart-27f7758c-a39d-470e-9134-4bf18ecfa7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171029468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.4171029468
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.4179817470
Short name T269
Test name
Test status
Simulation time 661808429 ps
CPU time 19.12 seconds
Started May 21 12:38:44 PM PDT 24
Finished May 21 12:39:15 PM PDT 24
Peak memory 214740 kb
Host smart-f90562c7-9220-4f04-8ec7-b4bffad8ac25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179817470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.4179817470
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1750956949
Short name T107
Test name
Test status
Simulation time 3173509443 ps
CPU time 100.46 seconds
Started May 21 01:54:40 PM PDT 24
Finished May 21 01:56:21 PM PDT 24
Peak memory 213748 kb
Host smart-4895565d-13e9-4819-8ba1-123876d1eebb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750956949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1750956949
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2694445408
Short name T101
Test name
Test status
Simulation time 1113220781 ps
CPU time 153.23 seconds
Started May 21 01:54:16 PM PDT 24
Finished May 21 01:56:51 PM PDT 24
Peak memory 214032 kb
Host smart-ed4bfef2-a0ea-4320-9589-8481dfe55f9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694445408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2694445408
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3185935473
Short name T29
Test name
Test status
Simulation time 33369310584 ps
CPU time 1553.83 seconds
Started May 21 12:38:48 PM PDT 24
Finished May 21 01:04:55 PM PDT 24
Peak memory 235860 kb
Host smart-332888d5-17cf-47f6-b809-ac993d9534f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185935473 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.3185935473
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3692107729
Short name T95
Test name
Test status
Simulation time 12420085521 ps
CPU time 26.24 seconds
Started May 21 01:53:42 PM PDT 24
Finished May 21 01:54:09 PM PDT 24
Peak memory 212188 kb
Host smart-36801817-a590-4e8b-9745-aabca7a21b56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692107729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3692107729
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1968670646
Short name T109
Test name
Test status
Simulation time 1682855499 ps
CPU time 161.04 seconds
Started May 21 01:54:55 PM PDT 24
Finished May 21 01:57:37 PM PDT 24
Peak memory 213800 kb
Host smart-1b934e17-d30e-49a1-8d8a-0aa438831e36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968670646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1968670646
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1823525219
Short name T4
Test name
Test status
Simulation time 714390102 ps
CPU time 19.75 seconds
Started May 21 12:38:47 PM PDT 24
Finished May 21 12:39:20 PM PDT 24
Peak memory 214592 kb
Host smart-6dfb4ff9-0dff-4333-a4ae-c80a0b676a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823525219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1823525219
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3098154751
Short name T86
Test name
Test status
Simulation time 6251996752 ps
CPU time 17.39 seconds
Started May 21 01:53:42 PM PDT 24
Finished May 21 01:54:01 PM PDT 24
Peak memory 212084 kb
Host smart-7b1f733f-16c6-46a0-8f0e-f81014f670b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098154751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3098154751
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.145703897
Short name T386
Test name
Test status
Simulation time 2043805299 ps
CPU time 20.34 seconds
Started May 21 01:53:41 PM PDT 24
Finished May 21 01:54:03 PM PDT 24
Peak memory 219432 kb
Host smart-65c62ab2-63cd-4e1c-a320-9894cbc36ad8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145703897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.145703897
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4128266750
Short name T425
Test name
Test status
Simulation time 353020949 ps
CPU time 15.38 seconds
Started May 21 01:53:41 PM PDT 24
Finished May 21 01:53:58 PM PDT 24
Peak memory 212152 kb
Host smart-9672e870-cfef-4f6f-aec9-ebd2a86b974c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128266750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.4128266750
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2193545825
Short name T397
Test name
Test status
Simulation time 961415626 ps
CPU time 15.08 seconds
Started May 21 01:53:48 PM PDT 24
Finished May 21 01:54:03 PM PDT 24
Peak memory 217268 kb
Host smart-0d09cd85-88eb-49eb-a8a8-27c170e5fca4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193545825 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2193545825
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1057523540
Short name T424
Test name
Test status
Simulation time 980912747 ps
CPU time 14.82 seconds
Started May 21 01:53:40 PM PDT 24
Finished May 21 01:53:56 PM PDT 24
Peak memory 211140 kb
Host smart-e25e39e0-9e3f-4359-98e7-91ca73ebf02f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057523540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1057523540
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1223773476
Short name T373
Test name
Test status
Simulation time 6259532436 ps
CPU time 17.1 seconds
Started May 21 01:53:41 PM PDT 24
Finished May 21 01:54:00 PM PDT 24
Peak memory 211280 kb
Host smart-bf9a9287-cc12-4c4e-bb6f-3a4a7dda5c55
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223773476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1223773476
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3001176215
Short name T429
Test name
Test status
Simulation time 66139365505 ps
CPU time 67.16 seconds
Started May 21 01:53:40 PM PDT 24
Finished May 21 01:54:48 PM PDT 24
Peak memory 214384 kb
Host smart-27b21691-f787-4326-b354-850b1b5d0aab
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001176215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3001176215
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.357979740
Short name T65
Test name
Test status
Simulation time 172400198 ps
CPU time 8.54 seconds
Started May 21 01:53:43 PM PDT 24
Finished May 21 01:53:52 PM PDT 24
Peak memory 211408 kb
Host smart-5a8774fc-4228-4cf1-9bb9-ffcf99f49771
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357979740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.357979740
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3490080416
Short name T377
Test name
Test status
Simulation time 4240459724 ps
CPU time 36.06 seconds
Started May 21 01:53:42 PM PDT 24
Finished May 21 01:54:19 PM PDT 24
Peak memory 218432 kb
Host smart-0be52a48-3f7b-466e-b142-0fa37ac4f098
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490080416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3490080416
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1157640451
Short name T375
Test name
Test status
Simulation time 875421941 ps
CPU time 82.29 seconds
Started May 21 01:53:42 PM PDT 24
Finished May 21 01:55:06 PM PDT 24
Peak memory 213712 kb
Host smart-0428e115-fd40-4878-b9b1-11a226d30f3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157640451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1157640451
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3861342836
Short name T387
Test name
Test status
Simulation time 3097267428 ps
CPU time 13.37 seconds
Started May 21 01:53:48 PM PDT 24
Finished May 21 01:54:02 PM PDT 24
Peak memory 211344 kb
Host smart-c923adb7-aeb5-4800-a4b2-62ef625cfa5c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861342836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3861342836
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3521799313
Short name T369
Test name
Test status
Simulation time 11914475803 ps
CPU time 27.1 seconds
Started May 21 01:53:47 PM PDT 24
Finished May 21 01:54:15 PM PDT 24
Peak memory 212424 kb
Host smart-a6d35a32-5c49-4b09-be6d-6c87d67be8d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521799313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3521799313
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3146045019
Short name T445
Test name
Test status
Simulation time 10113509964 ps
CPU time 25.62 seconds
Started May 21 01:53:49 PM PDT 24
Finished May 21 01:54:16 PM PDT 24
Peak memory 212004 kb
Host smart-2f8dc412-cc06-4ec8-907c-41822c318d2f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146045019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3146045019
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.358416946
Short name T403
Test name
Test status
Simulation time 751502988 ps
CPU time 13.81 seconds
Started May 21 01:53:49 PM PDT 24
Finished May 21 01:54:05 PM PDT 24
Peak memory 215316 kb
Host smart-fb7fba98-3903-4705-8d76-c0fdefea6891
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358416946 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.358416946
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2278621018
Short name T415
Test name
Test status
Simulation time 169002576 ps
CPU time 8.35 seconds
Started May 21 01:53:47 PM PDT 24
Finished May 21 01:53:57 PM PDT 24
Peak memory 211284 kb
Host smart-c3aeb941-fd77-4d6e-84c2-a494aaa65635
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278621018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2278621018
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2432310681
Short name T379
Test name
Test status
Simulation time 2482677390 ps
CPU time 22.21 seconds
Started May 21 01:53:47 PM PDT 24
Finished May 21 01:54:11 PM PDT 24
Peak memory 211264 kb
Host smart-a48a9e22-3bc7-4d2c-a2c4-596adb35f1dc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432310681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2432310681
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3115897150
Short name T452
Test name
Test status
Simulation time 167447725 ps
CPU time 7.97 seconds
Started May 21 01:53:46 PM PDT 24
Finished May 21 01:53:55 PM PDT 24
Peak memory 211192 kb
Host smart-c7cc9ec4-c1fc-4e03-8629-e5b19e79cdc7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115897150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3115897150
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1048134094
Short name T459
Test name
Test status
Simulation time 55466301500 ps
CPU time 92.34 seconds
Started May 21 01:53:49 PM PDT 24
Finished May 21 01:55:23 PM PDT 24
Peak memory 214472 kb
Host smart-38f2b014-5691-4530-af33-28547c0cf18c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048134094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1048134094
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1858517219
Short name T90
Test name
Test status
Simulation time 6812502248 ps
CPU time 23.2 seconds
Started May 21 01:53:48 PM PDT 24
Finished May 21 01:54:12 PM PDT 24
Peak memory 212784 kb
Host smart-9ea07ecb-6c9e-410d-b949-53c7a6eb5611
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858517219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1858517219
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.901039485
Short name T382
Test name
Test status
Simulation time 345626010 ps
CPU time 12.71 seconds
Started May 21 01:53:46 PM PDT 24
Finished May 21 01:54:00 PM PDT 24
Peak memory 219520 kb
Host smart-5c227556-0553-4db2-b00e-d14b37b4a381
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901039485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.901039485
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2915583678
Short name T57
Test name
Test status
Simulation time 2955191425 ps
CPU time 98.47 seconds
Started May 21 01:53:48 PM PDT 24
Finished May 21 01:55:28 PM PDT 24
Peak memory 213600 kb
Host smart-7e76526b-a740-4bae-b78c-fbff758fb7b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915583678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2915583678
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.657531885
Short name T378
Test name
Test status
Simulation time 2135719430 ps
CPU time 21.49 seconds
Started May 21 01:54:30 PM PDT 24
Finished May 21 01:54:53 PM PDT 24
Peak memory 216736 kb
Host smart-bf2d0de8-4288-45d6-9274-27f88c7bfdc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657531885 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.657531885
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3043739155
Short name T83
Test name
Test status
Simulation time 1649838118 ps
CPU time 8.15 seconds
Started May 21 01:54:30 PM PDT 24
Finished May 21 01:54:39 PM PDT 24
Peak memory 211276 kb
Host smart-8cac8734-09cf-4c52-854f-c117dd51b2af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043739155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3043739155
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2834423372
Short name T88
Test name
Test status
Simulation time 2192843993 ps
CPU time 54.85 seconds
Started May 21 01:54:26 PM PDT 24
Finished May 21 01:55:21 PM PDT 24
Peak memory 215408 kb
Host smart-b216a075-17cc-4dc7-b714-f95c3b695175
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834423372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2834423372
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.925481507
Short name T430
Test name
Test status
Simulation time 1032191256 ps
CPU time 8.65 seconds
Started May 21 01:54:29 PM PDT 24
Finished May 21 01:54:39 PM PDT 24
Peak memory 211244 kb
Host smart-c6aa636e-2aea-4976-8eb6-b56241c7f112
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925481507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.925481507
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1062303688
Short name T462
Test name
Test status
Simulation time 2695397211 ps
CPU time 28.53 seconds
Started May 21 01:54:22 PM PDT 24
Finished May 21 01:54:51 PM PDT 24
Peak memory 219492 kb
Host smart-43848090-356f-44ec-9512-ed7fbf55064a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062303688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1062303688
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2073262899
Short name T99
Test name
Test status
Simulation time 1512257465 ps
CPU time 89.49 seconds
Started May 21 01:54:19 PM PDT 24
Finished May 21 01:55:50 PM PDT 24
Peak memory 213672 kb
Host smart-a546ce2e-65c8-4bfe-ae1b-c1706b7d2afa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073262899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2073262899
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3123408668
Short name T408
Test name
Test status
Simulation time 1741997250 ps
CPU time 11.76 seconds
Started May 21 01:54:29 PM PDT 24
Finished May 21 01:54:42 PM PDT 24
Peak memory 214476 kb
Host smart-5ff43dd5-f0b8-4268-be49-6b7d0fd9c314
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123408668 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3123408668
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3599416591
Short name T461
Test name
Test status
Simulation time 2600642810 ps
CPU time 20.79 seconds
Started May 21 01:54:32 PM PDT 24
Finished May 21 01:54:54 PM PDT 24
Peak memory 211724 kb
Host smart-a26335f1-c3ac-46f8-b638-4309c0ed0ffe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599416591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3599416591
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3112854662
Short name T80
Test name
Test status
Simulation time 16428808451 ps
CPU time 135.12 seconds
Started May 21 01:54:30 PM PDT 24
Finished May 21 01:56:46 PM PDT 24
Peak memory 214592 kb
Host smart-1ce68529-295a-4c43-90dd-d717d26f18f5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112854662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3112854662
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.149047333
Short name T66
Test name
Test status
Simulation time 2358357454 ps
CPU time 16.81 seconds
Started May 21 01:54:30 PM PDT 24
Finished May 21 01:54:48 PM PDT 24
Peak memory 212236 kb
Host smart-19584f73-551a-4845-892c-5054a75436f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149047333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.149047333
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1475899891
Short name T376
Test name
Test status
Simulation time 3793722996 ps
CPU time 33.75 seconds
Started May 21 01:54:30 PM PDT 24
Finished May 21 01:55:05 PM PDT 24
Peak memory 218460 kb
Host smart-c1d72608-e80f-45d3-a3ec-4a1441ff073e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475899891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1475899891
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1317876835
Short name T55
Test name
Test status
Simulation time 5256925103 ps
CPU time 95.26 seconds
Started May 21 01:54:29 PM PDT 24
Finished May 21 01:56:05 PM PDT 24
Peak memory 219504 kb
Host smart-32bafd4f-170d-4ba5-a8fb-df7310e20f8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317876835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1317876835
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.859584159
Short name T423
Test name
Test status
Simulation time 721735044 ps
CPU time 9.12 seconds
Started May 21 01:54:36 PM PDT 24
Finished May 21 01:54:46 PM PDT 24
Peak memory 219524 kb
Host smart-5192079a-37ce-475c-aae6-c484b5aa5559
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859584159 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.859584159
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3398946528
Short name T93
Test name
Test status
Simulation time 3994925607 ps
CPU time 29.7 seconds
Started May 21 01:54:28 PM PDT 24
Finished May 21 01:54:58 PM PDT 24
Peak memory 211984 kb
Host smart-c8aaa921-dffa-469e-9acc-c44df37d6896
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398946528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3398946528
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.295764347
Short name T450
Test name
Test status
Simulation time 21485194980 ps
CPU time 99.08 seconds
Started May 21 01:54:30 PM PDT 24
Finished May 21 01:56:10 PM PDT 24
Peak memory 214460 kb
Host smart-8d53499f-2f6b-48af-84a6-18bcaf0b89f3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295764347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.295764347
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2782307790
Short name T409
Test name
Test status
Simulation time 1821040171 ps
CPU time 10.81 seconds
Started May 21 01:54:34 PM PDT 24
Finished May 21 01:54:46 PM PDT 24
Peak memory 211188 kb
Host smart-d08543b5-037d-4974-bb2c-d944b5cccf56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782307790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2782307790
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1479021158
Short name T366
Test name
Test status
Simulation time 699997107 ps
CPU time 13.61 seconds
Started May 21 01:54:29 PM PDT 24
Finished May 21 01:54:43 PM PDT 24
Peak memory 217716 kb
Host smart-eda393ac-7e13-43e7-8192-669767fb000f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479021158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1479021158
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2905392537
Short name T106
Test name
Test status
Simulation time 1146793340 ps
CPU time 154.99 seconds
Started May 21 01:54:29 PM PDT 24
Finished May 21 01:57:05 PM PDT 24
Peak memory 219468 kb
Host smart-63031b9c-6ea3-4e85-9199-53c3c2e82705
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905392537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2905392537
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2690523424
Short name T398
Test name
Test status
Simulation time 15677258040 ps
CPU time 30.3 seconds
Started May 21 01:54:34 PM PDT 24
Finished May 21 01:55:05 PM PDT 24
Peak memory 217524 kb
Host smart-67bf1687-dc66-46b0-8567-353c3b4cd421
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690523424 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2690523424
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1085497964
Short name T87
Test name
Test status
Simulation time 5294700123 ps
CPU time 23.35 seconds
Started May 21 01:54:33 PM PDT 24
Finished May 21 01:54:57 PM PDT 24
Peak memory 212312 kb
Host smart-4523b81f-9628-4edd-ad17-36a5f193322c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085497964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1085497964
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.350947369
Short name T448
Test name
Test status
Simulation time 23140754007 ps
CPU time 75.97 seconds
Started May 21 01:54:34 PM PDT 24
Finished May 21 01:55:51 PM PDT 24
Peak memory 214560 kb
Host smart-e5127277-75f3-49cf-9fa5-a9fd1e9e5a9e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350947369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.350947369
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4215560631
Short name T72
Test name
Test status
Simulation time 4115940472 ps
CPU time 31.74 seconds
Started May 21 01:54:33 PM PDT 24
Finished May 21 01:55:05 PM PDT 24
Peak memory 212136 kb
Host smart-3a9ec7f3-f006-4fe6-a9d0-ad1e37f7a3ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215560631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.4215560631
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.788690941
Short name T418
Test name
Test status
Simulation time 3929729353 ps
CPU time 36.02 seconds
Started May 21 01:54:34 PM PDT 24
Finished May 21 01:55:11 PM PDT 24
Peak memory 218284 kb
Host smart-377c2a5c-0271-4e2d-84f1-61fced6f028f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788690941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.788690941
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1065179919
Short name T103
Test name
Test status
Simulation time 232866771 ps
CPU time 83.23 seconds
Started May 21 01:54:34 PM PDT 24
Finished May 21 01:55:58 PM PDT 24
Peak memory 213780 kb
Host smart-8f8f02f0-f7d0-46bc-b30c-ed1f7c97a096
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065179919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1065179919
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.395779739
Short name T449
Test name
Test status
Simulation time 3062534198 ps
CPU time 26.13 seconds
Started May 21 01:54:41 PM PDT 24
Finished May 21 01:55:09 PM PDT 24
Peak memory 217692 kb
Host smart-820f4e54-988a-4404-93a0-fec8c152df74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395779739 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.395779739
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1935811992
Short name T419
Test name
Test status
Simulation time 988310446 ps
CPU time 14.6 seconds
Started May 21 01:54:32 PM PDT 24
Finished May 21 01:54:47 PM PDT 24
Peak memory 211236 kb
Host smart-97d345d4-46df-4d44-a146-f30e1acbe5c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935811992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1935811992
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1252390887
Short name T82
Test name
Test status
Simulation time 14797130217 ps
CPU time 83.42 seconds
Started May 21 01:54:34 PM PDT 24
Finished May 21 01:55:58 PM PDT 24
Peak memory 214544 kb
Host smart-5ee67a29-fec9-4301-a482-93e980ba77a2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252390887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1252390887
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3623382810
Short name T435
Test name
Test status
Simulation time 6817463340 ps
CPU time 22.07 seconds
Started May 21 01:54:33 PM PDT 24
Finished May 21 01:54:56 PM PDT 24
Peak memory 212756 kb
Host smart-c7d8821e-4091-49c5-82c3-ae102e9e8f0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623382810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3623382810
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2281949633
Short name T456
Test name
Test status
Simulation time 7002900365 ps
CPU time 30.98 seconds
Started May 21 01:54:35 PM PDT 24
Finished May 21 01:55:06 PM PDT 24
Peak memory 218576 kb
Host smart-2d23e787-596c-4853-94e7-83870c3edea9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281949633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2281949633
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.804600158
Short name T104
Test name
Test status
Simulation time 10881039436 ps
CPU time 97.28 seconds
Started May 21 01:54:34 PM PDT 24
Finished May 21 01:56:12 PM PDT 24
Peak memory 213688 kb
Host smart-b8e2e274-2345-431e-bc8b-9a9d81a0b2d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804600158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.804600158
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1391828839
Short name T404
Test name
Test status
Simulation time 258200957 ps
CPU time 9.99 seconds
Started May 21 01:54:40 PM PDT 24
Finished May 21 01:54:50 PM PDT 24
Peak memory 214232 kb
Host smart-a8411602-bf56-41d7-a4bd-61a9b0f5f042
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391828839 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1391828839
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2728692037
Short name T96
Test name
Test status
Simulation time 1072441010 ps
CPU time 11.83 seconds
Started May 21 01:54:42 PM PDT 24
Finished May 21 01:54:55 PM PDT 24
Peak memory 211244 kb
Host smart-632f2873-f2cd-4355-af80-c21eccef99bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728692037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2728692037
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.981667383
Short name T97
Test name
Test status
Simulation time 48390823620 ps
CPU time 94.12 seconds
Started May 21 01:54:42 PM PDT 24
Finished May 21 01:56:18 PM PDT 24
Peak memory 213408 kb
Host smart-86a36dec-6beb-4d49-8e6a-32d2194760f8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981667383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.981667383
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2194155553
Short name T400
Test name
Test status
Simulation time 8330295429 ps
CPU time 31.97 seconds
Started May 21 01:54:43 PM PDT 24
Finished May 21 01:55:16 PM PDT 24
Peak memory 212520 kb
Host smart-5f390f48-331e-49d3-b022-8c1751b30ccb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194155553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2194155553
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.865988458
Short name T389
Test name
Test status
Simulation time 8361129116 ps
CPU time 33.7 seconds
Started May 21 01:54:40 PM PDT 24
Finished May 21 01:55:14 PM PDT 24
Peak memory 219616 kb
Host smart-ee04ad27-0b1d-45b7-8620-e6b8d2428113
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865988458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.865988458
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1529178533
Short name T108
Test name
Test status
Simulation time 5152602912 ps
CPU time 94.97 seconds
Started May 21 01:54:41 PM PDT 24
Finished May 21 01:56:17 PM PDT 24
Peak memory 215028 kb
Host smart-d8b42e4a-7a4e-4d7f-9160-fa36f378d3ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529178533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1529178533
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2613668042
Short name T441
Test name
Test status
Simulation time 364844149 ps
CPU time 8.71 seconds
Started May 21 01:54:41 PM PDT 24
Finished May 21 01:54:51 PM PDT 24
Peak memory 217056 kb
Host smart-31390e00-e615-4629-b1cc-d157178c1512
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613668042 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2613668042
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3839077589
Short name T436
Test name
Test status
Simulation time 2890290049 ps
CPU time 17.45 seconds
Started May 21 01:54:41 PM PDT 24
Finished May 21 01:54:59 PM PDT 24
Peak memory 212036 kb
Host smart-21ea4bcc-9991-4cb6-ab7b-1811a01534b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839077589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3839077589
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.920040383
Short name T69
Test name
Test status
Simulation time 1431046634 ps
CPU time 37.75 seconds
Started May 21 01:54:41 PM PDT 24
Finished May 21 01:55:19 PM PDT 24
Peak memory 214396 kb
Host smart-fe3baaf9-d9b6-4a7f-b897-a68d3c2d475f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920040383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.920040383
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1010073133
Short name T432
Test name
Test status
Simulation time 338305906 ps
CPU time 8.56 seconds
Started May 21 01:54:41 PM PDT 24
Finished May 21 01:54:52 PM PDT 24
Peak memory 211280 kb
Host smart-37ecd6cb-4c81-4e48-940c-74909d8a9de3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010073133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1010073133
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1153867634
Short name T405
Test name
Test status
Simulation time 6100389154 ps
CPU time 22.87 seconds
Started May 21 01:54:43 PM PDT 24
Finished May 21 01:55:07 PM PDT 24
Peak memory 219012 kb
Host smart-0f42b029-8957-458a-9b03-7d41813327dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153867634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1153867634
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4089602842
Short name T372
Test name
Test status
Simulation time 527458953 ps
CPU time 12.5 seconds
Started May 21 01:54:48 PM PDT 24
Finished May 21 01:55:03 PM PDT 24
Peak memory 219516 kb
Host smart-1e91556d-d65c-40f2-9adb-c592c67129e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089602842 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.4089602842
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.515369365
Short name T442
Test name
Test status
Simulation time 8649153388 ps
CPU time 18.46 seconds
Started May 21 01:54:48 PM PDT 24
Finished May 21 01:55:08 PM PDT 24
Peak memory 212272 kb
Host smart-565c5e4a-872d-427d-8d66-bf23f5919042
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515369365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.515369365
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.316566853
Short name T402
Test name
Test status
Simulation time 4954662271 ps
CPU time 70.17 seconds
Started May 21 01:54:40 PM PDT 24
Finished May 21 01:55:51 PM PDT 24
Peak memory 213580 kb
Host smart-4a232e86-a896-4744-9b9b-28f9948a5e3d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316566853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.316566853
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2775908452
Short name T412
Test name
Test status
Simulation time 3786153149 ps
CPU time 20.41 seconds
Started May 21 01:54:49 PM PDT 24
Finished May 21 01:55:11 PM PDT 24
Peak memory 212344 kb
Host smart-b66cd955-7403-41a5-b8f9-6df923636201
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775908452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2775908452
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.463298969
Short name T365
Test name
Test status
Simulation time 11061547277 ps
CPU time 28.09 seconds
Started May 21 01:54:50 PM PDT 24
Finished May 21 01:55:19 PM PDT 24
Peak memory 218556 kb
Host smart-ef799c35-40c4-4cd6-8c34-f2765f88ad8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463298969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.463298969
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.57029201
Short name T451
Test name
Test status
Simulation time 3996500157 ps
CPU time 15.14 seconds
Started May 21 01:54:48 PM PDT 24
Finished May 21 01:55:05 PM PDT 24
Peak memory 216192 kb
Host smart-f439afa4-4ba0-4a2a-b890-54c7cbb51f68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57029201 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.57029201
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.230482237
Short name T60
Test name
Test status
Simulation time 2046229780 ps
CPU time 21 seconds
Started May 21 01:54:49 PM PDT 24
Finished May 21 01:55:12 PM PDT 24
Peak memory 211200 kb
Host smart-4d04f088-802f-4681-b234-c9e5fde54d60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230482237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.230482237
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2093555519
Short name T460
Test name
Test status
Simulation time 4716831876 ps
CPU time 67.81 seconds
Started May 21 01:54:47 PM PDT 24
Finished May 21 01:55:56 PM PDT 24
Peak memory 214448 kb
Host smart-2e9e31ff-3cb5-41bd-b420-560159aba738
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093555519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2093555519
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.810253366
Short name T443
Test name
Test status
Simulation time 660876688 ps
CPU time 8.34 seconds
Started May 21 01:54:50 PM PDT 24
Finished May 21 01:55:00 PM PDT 24
Peak memory 211204 kb
Host smart-979696b3-baab-4c99-98da-f93e96bfa5f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810253366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.810253366
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3654106853
Short name T455
Test name
Test status
Simulation time 11272817129 ps
CPU time 35.84 seconds
Started May 21 01:54:50 PM PDT 24
Finished May 21 01:55:27 PM PDT 24
Peak memory 219004 kb
Host smart-e74c21a2-5603-4d67-bbca-6c59c50d082f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654106853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3654106853
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.588236569
Short name T102
Test name
Test status
Simulation time 457309176 ps
CPU time 158.96 seconds
Started May 21 01:54:50 PM PDT 24
Finished May 21 01:57:30 PM PDT 24
Peak memory 213844 kb
Host smart-a56f7361-ac50-494c-9868-198e68f72e50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588236569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.588236569
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.826933697
Short name T417
Test name
Test status
Simulation time 13483024581 ps
CPU time 23.38 seconds
Started May 21 01:54:56 PM PDT 24
Finished May 21 01:55:21 PM PDT 24
Peak memory 214712 kb
Host smart-5dc071a8-2e7f-4bd9-b98a-4f9d17bc654b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826933697 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.826933697
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3777669164
Short name T371
Test name
Test status
Simulation time 13493273380 ps
CPU time 28.48 seconds
Started May 21 01:54:55 PM PDT 24
Finished May 21 01:55:25 PM PDT 24
Peak memory 212232 kb
Host smart-496e1a98-112e-454a-904a-555bef1d57d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777669164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3777669164
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.796849874
Short name T85
Test name
Test status
Simulation time 4482407400 ps
CPU time 86.98 seconds
Started May 21 01:54:48 PM PDT 24
Finished May 21 01:56:17 PM PDT 24
Peak memory 215528 kb
Host smart-523dc108-7ec8-4a3a-b2e4-76a4b24a6d07
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796849874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.796849874
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2920891917
Short name T446
Test name
Test status
Simulation time 978857409 ps
CPU time 15.13 seconds
Started May 21 01:54:56 PM PDT 24
Finished May 21 01:55:12 PM PDT 24
Peak memory 211392 kb
Host smart-f5a1134d-3adf-4b3f-a382-49c2b972ecda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920891917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2920891917
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3674364390
Short name T384
Test name
Test status
Simulation time 5445620331 ps
CPU time 28.76 seconds
Started May 21 01:54:57 PM PDT 24
Finished May 21 01:55:26 PM PDT 24
Peak memory 217944 kb
Host smart-8b7638e8-e126-455a-8321-92638e1d9d74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674364390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3674364390
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.740951192
Short name T433
Test name
Test status
Simulation time 3507449862 ps
CPU time 23.36 seconds
Started May 21 01:53:54 PM PDT 24
Finished May 21 01:54:18 PM PDT 24
Peak memory 211488 kb
Host smart-97bf9271-40d7-44a2-bd8a-f634449d424d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740951192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.740951192
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1529091924
Short name T380
Test name
Test status
Simulation time 661159235 ps
CPU time 8.79 seconds
Started May 21 01:53:54 PM PDT 24
Finished May 21 01:54:03 PM PDT 24
Peak memory 211144 kb
Host smart-ea28573a-97af-4de3-b943-8d60b6ae23f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529091924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1529091924
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4255316817
Short name T381
Test name
Test status
Simulation time 4524497164 ps
CPU time 29.03 seconds
Started May 21 01:53:54 PM PDT 24
Finished May 21 01:54:23 PM PDT 24
Peak memory 212256 kb
Host smart-a72a42dd-d504-4d57-9e52-2aaf298f9ee7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255316817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.4255316817
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3809637303
Short name T453
Test name
Test status
Simulation time 3448967272 ps
CPU time 29.18 seconds
Started May 21 01:53:53 PM PDT 24
Finished May 21 01:54:23 PM PDT 24
Peak memory 219612 kb
Host smart-d04e00b2-2f14-4dcc-997d-cef8be80c274
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809637303 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3809637303
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.766188437
Short name T370
Test name
Test status
Simulation time 171079784 ps
CPU time 8.29 seconds
Started May 21 01:53:54 PM PDT 24
Finished May 21 01:54:04 PM PDT 24
Peak memory 211300 kb
Host smart-bb77cef6-304e-4db6-b8eb-d648d5b7e2fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766188437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.766188437
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2113678925
Short name T395
Test name
Test status
Simulation time 17337173922 ps
CPU time 19.15 seconds
Started May 21 01:53:55 PM PDT 24
Finished May 21 01:54:15 PM PDT 24
Peak memory 211232 kb
Host smart-3dac9b8f-1ec0-408e-a811-ee44f634cd6e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113678925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2113678925
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2031409252
Short name T427
Test name
Test status
Simulation time 8784785003 ps
CPU time 33.99 seconds
Started May 21 01:53:55 PM PDT 24
Finished May 21 01:54:30 PM PDT 24
Peak memory 211300 kb
Host smart-687e1692-fc56-4f71-a2c8-19e9ba5fcbc2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031409252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2031409252
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.115834525
Short name T463
Test name
Test status
Simulation time 5254080056 ps
CPU time 19.8 seconds
Started May 21 01:53:55 PM PDT 24
Finished May 21 01:54:15 PM PDT 24
Peak memory 212732 kb
Host smart-bacaca19-8e00-4dfb-aa44-07af00d27f7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115834525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.115834525
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.826859016
Short name T388
Test name
Test status
Simulation time 368842797 ps
CPU time 13.69 seconds
Started May 21 01:53:56 PM PDT 24
Finished May 21 01:54:10 PM PDT 24
Peak memory 217680 kb
Host smart-5a494397-b7be-4a44-9f2a-8809f728f144
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826859016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.826859016
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1895192619
Short name T420
Test name
Test status
Simulation time 3111104984 ps
CPU time 88.64 seconds
Started May 21 01:53:54 PM PDT 24
Finished May 21 01:55:23 PM PDT 24
Peak memory 214440 kb
Host smart-0ee342c5-1032-474b-996b-087a1d51685f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895192619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1895192619
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.568575277
Short name T81
Test name
Test status
Simulation time 3822679679 ps
CPU time 18.62 seconds
Started May 21 01:54:01 PM PDT 24
Finished May 21 01:54:20 PM PDT 24
Peak memory 219524 kb
Host smart-9fb6be73-9f49-417b-a5c1-a90259ee1464
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568575277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.568575277
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.831185547
Short name T454
Test name
Test status
Simulation time 6735539330 ps
CPU time 28.83 seconds
Started May 21 01:54:02 PM PDT 24
Finished May 21 01:54:31 PM PDT 24
Peak memory 211428 kb
Host smart-17adc23b-b2da-487d-a15a-fffd40eb7779
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831185547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.831185547
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3880528647
Short name T447
Test name
Test status
Simulation time 178981172 ps
CPU time 16 seconds
Started May 21 01:54:01 PM PDT 24
Finished May 21 01:54:18 PM PDT 24
Peak memory 211856 kb
Host smart-57cbbc4e-f55b-4f37-9452-5e0a22abb540
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880528647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3880528647
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2732220430
Short name T392
Test name
Test status
Simulation time 665582273 ps
CPU time 9.75 seconds
Started May 21 01:54:01 PM PDT 24
Finished May 21 01:54:12 PM PDT 24
Peak memory 219432 kb
Host smart-974e8829-801a-4b0f-b644-95b7272c52e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732220430 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2732220430
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4065767366
Short name T64
Test name
Test status
Simulation time 4285121049 ps
CPU time 35.21 seconds
Started May 21 01:54:01 PM PDT 24
Finished May 21 01:54:38 PM PDT 24
Peak memory 211628 kb
Host smart-59575f07-1178-4919-ac20-58b991f1598d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065767366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.4065767366
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.92691160
Short name T407
Test name
Test status
Simulation time 660956078 ps
CPU time 8.11 seconds
Started May 21 01:53:59 PM PDT 24
Finished May 21 01:54:08 PM PDT 24
Peak memory 211136 kb
Host smart-ff6e82c6-e08c-4fb4-98a8-1a57a5d6bfb7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92691160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_
mem_partial_access.92691160
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2843997341
Short name T421
Test name
Test status
Simulation time 2859013885 ps
CPU time 17.21 seconds
Started May 21 01:54:02 PM PDT 24
Finished May 21 01:54:20 PM PDT 24
Peak memory 211232 kb
Host smart-2de8f6e2-1b7a-4f9c-83ba-96068437c4b5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843997341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2843997341
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.895355931
Short name T426
Test name
Test status
Simulation time 715396084 ps
CPU time 39.17 seconds
Started May 21 01:53:55 PM PDT 24
Finished May 21 01:54:35 PM PDT 24
Peak memory 213256 kb
Host smart-46ef0f52-3eed-418d-b51f-8028f4c27f15
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895355931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.895355931
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1649933197
Short name T396
Test name
Test status
Simulation time 4441753388 ps
CPU time 34.55 seconds
Started May 21 01:54:00 PM PDT 24
Finished May 21 01:54:35 PM PDT 24
Peak memory 212588 kb
Host smart-b6d10821-f4af-4696-bfb3-256afbbe93e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649933197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1649933197
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.540791469
Short name T367
Test name
Test status
Simulation time 916939861 ps
CPU time 13.18 seconds
Started May 21 01:53:55 PM PDT 24
Finished May 21 01:54:08 PM PDT 24
Peak memory 218472 kb
Host smart-800ed1a3-35be-449c-86b7-da62ec6776b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540791469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.540791469
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4094947294
Short name T100
Test name
Test status
Simulation time 1006659045 ps
CPU time 87.19 seconds
Started May 21 01:54:03 PM PDT 24
Finished May 21 01:55:31 PM PDT 24
Peak memory 213736 kb
Host smart-c1a7e24c-62d2-4703-9b7f-de94dc758cdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094947294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.4094947294
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1973959790
Short name T71
Test name
Test status
Simulation time 3836303575 ps
CPU time 29.39 seconds
Started May 21 01:54:07 PM PDT 24
Finished May 21 01:54:37 PM PDT 24
Peak memory 211320 kb
Host smart-b6dc2f1a-272b-4d82-8892-fce40295f549
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973959790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1973959790
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1411744403
Short name T437
Test name
Test status
Simulation time 1155122727 ps
CPU time 16.54 seconds
Started May 21 01:54:08 PM PDT 24
Finished May 21 01:54:25 PM PDT 24
Peak memory 211268 kb
Host smart-a86ac10b-b8dd-42de-951a-ecb23a990afb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411744403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1411744403
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4133310073
Short name T457
Test name
Test status
Simulation time 1201442419 ps
CPU time 16.78 seconds
Started May 21 01:54:06 PM PDT 24
Finished May 21 01:54:24 PM PDT 24
Peak memory 211260 kb
Host smart-38b4bf1d-d672-486d-b070-4d4cff781fab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133310073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4133310073
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2218398133
Short name T383
Test name
Test status
Simulation time 4268556237 ps
CPU time 33.6 seconds
Started May 21 01:54:09 PM PDT 24
Finished May 21 01:54:43 PM PDT 24
Peak memory 219520 kb
Host smart-075eede7-5b59-4413-8918-1759d682ec39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218398133 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2218398133
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.431941789
Short name T414
Test name
Test status
Simulation time 13469786870 ps
CPU time 30.24 seconds
Started May 21 01:54:07 PM PDT 24
Finished May 21 01:54:38 PM PDT 24
Peak memory 212560 kb
Host smart-d4917d6a-7eca-41a2-a7f8-abe770e4639e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431941789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.431941789
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1652006262
Short name T374
Test name
Test status
Simulation time 338395032 ps
CPU time 8.06 seconds
Started May 21 01:54:06 PM PDT 24
Finished May 21 01:54:15 PM PDT 24
Peak memory 211144 kb
Host smart-c90dd077-18df-4f55-bb59-5d4c09db7d27
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652006262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1652006262
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.772670900
Short name T416
Test name
Test status
Simulation time 2541930627 ps
CPU time 23.64 seconds
Started May 21 01:54:06 PM PDT 24
Finished May 21 01:54:31 PM PDT 24
Peak memory 211276 kb
Host smart-0d9a1e48-aa45-429e-af8b-d51114a5a3e5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772670900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
772670900
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3176059320
Short name T58
Test name
Test status
Simulation time 2205422567 ps
CPU time 57.59 seconds
Started May 21 01:54:04 PM PDT 24
Finished May 21 01:55:02 PM PDT 24
Peak memory 214376 kb
Host smart-48dabe59-d2f0-46ff-a7de-abacba735d2b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176059320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3176059320
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2354801992
Short name T89
Test name
Test status
Simulation time 2979045431 ps
CPU time 24.46 seconds
Started May 21 01:54:08 PM PDT 24
Finished May 21 01:54:33 PM PDT 24
Peak memory 211952 kb
Host smart-3c8051e6-e941-4e32-a13b-d2bdb138dea1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354801992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2354801992
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.451616005
Short name T434
Test name
Test status
Simulation time 418092668 ps
CPU time 16.6 seconds
Started May 21 01:54:02 PM PDT 24
Finished May 21 01:54:20 PM PDT 24
Peak memory 217716 kb
Host smart-3e8bb1af-9245-42f8-9574-62f93a0b9b4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451616005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.451616005
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1503322257
Short name T401
Test name
Test status
Simulation time 1909718444 ps
CPU time 85.19 seconds
Started May 21 01:54:05 PM PDT 24
Finished May 21 01:55:31 PM PDT 24
Peak memory 214660 kb
Host smart-ac7ab7ff-5d73-4be7-8ccf-659cadb09a43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503322257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1503322257
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.572565897
Short name T385
Test name
Test status
Simulation time 7670507095 ps
CPU time 20.46 seconds
Started May 21 01:54:15 PM PDT 24
Finished May 21 01:54:37 PM PDT 24
Peak memory 218248 kb
Host smart-0eaae330-1587-443e-a28e-5332dc6e64dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572565897 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.572565897
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3380255354
Short name T411
Test name
Test status
Simulation time 4081144788 ps
CPU time 27.5 seconds
Started May 21 01:54:11 PM PDT 24
Finished May 21 01:54:39 PM PDT 24
Peak memory 211876 kb
Host smart-37270324-4b6f-4032-8c77-078dbc54dbc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380255354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3380255354
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2235233999
Short name T438
Test name
Test status
Simulation time 84842077527 ps
CPU time 186.34 seconds
Started May 21 01:54:06 PM PDT 24
Finished May 21 01:57:13 PM PDT 24
Peak memory 215436 kb
Host smart-712833a3-530f-4611-8ee4-1ccff7059a5c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235233999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2235233999
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2327883982
Short name T92
Test name
Test status
Simulation time 332473136 ps
CPU time 8.44 seconds
Started May 21 01:54:06 PM PDT 24
Finished May 21 01:54:16 PM PDT 24
Peak memory 211272 kb
Host smart-666b62c5-838f-423e-af76-3282181ba1b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327883982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2327883982
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1357482541
Short name T410
Test name
Test status
Simulation time 1736278461 ps
CPU time 24.73 seconds
Started May 21 01:54:12 PM PDT 24
Finished May 21 01:54:38 PM PDT 24
Peak memory 218360 kb
Host smart-abf63df7-6908-42d3-ae54-0c630eedd245
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357482541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1357482541
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2871811171
Short name T110
Test name
Test status
Simulation time 564709352 ps
CPU time 155.17 seconds
Started May 21 01:54:08 PM PDT 24
Finished May 21 01:56:44 PM PDT 24
Peak memory 214068 kb
Host smart-4be262a1-7fe8-47d3-8681-6a25aca7a1e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871811171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2871811171
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.971348409
Short name T393
Test name
Test status
Simulation time 1074699578 ps
CPU time 10.26 seconds
Started May 21 01:54:16 PM PDT 24
Finished May 21 01:54:28 PM PDT 24
Peak memory 219424 kb
Host smart-6968e4a6-cf41-433f-bcac-2ba0f1635e93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971348409 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.971348409
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.212645848
Short name T68
Test name
Test status
Simulation time 23266127787 ps
CPU time 31.68 seconds
Started May 21 01:54:13 PM PDT 24
Finished May 21 01:54:45 PM PDT 24
Peak memory 212296 kb
Host smart-b274e2f4-ccd0-48c2-b1a7-26c9503ee9c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212645848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.212645848
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3857518198
Short name T67
Test name
Test status
Simulation time 5003201815 ps
CPU time 64.06 seconds
Started May 21 01:54:15 PM PDT 24
Finished May 21 01:55:21 PM PDT 24
Peak memory 215380 kb
Host smart-773021ca-8aef-42e4-9d6c-cae8fb215665
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857518198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3857518198
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1543352075
Short name T91
Test name
Test status
Simulation time 2436961667 ps
CPU time 22.54 seconds
Started May 21 01:54:14 PM PDT 24
Finished May 21 01:54:37 PM PDT 24
Peak memory 212424 kb
Host smart-64ce9f9d-f34e-4896-aea0-e531a0fd28ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543352075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1543352075
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1915508313
Short name T391
Test name
Test status
Simulation time 1819154922 ps
CPU time 19.65 seconds
Started May 21 01:54:16 PM PDT 24
Finished May 21 01:54:37 PM PDT 24
Peak memory 218540 kb
Host smart-f492a64a-c202-40b5-b64f-4cc8c9af9e4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915508313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1915508313
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1413046325
Short name T59
Test name
Test status
Simulation time 9721302944 ps
CPU time 35.14 seconds
Started May 21 01:54:16 PM PDT 24
Finished May 21 01:54:53 PM PDT 24
Peak memory 218860 kb
Host smart-d5b36769-01e9-43c4-bd0a-672de42462f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413046325 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1413046325
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1939696933
Short name T399
Test name
Test status
Simulation time 2455090005 ps
CPU time 16.39 seconds
Started May 21 01:54:16 PM PDT 24
Finished May 21 01:54:34 PM PDT 24
Peak memory 211916 kb
Host smart-35aa48fb-9664-49d6-9505-9789b562eef0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939696933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1939696933
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1427714482
Short name T390
Test name
Test status
Simulation time 22080494393 ps
CPU time 179.17 seconds
Started May 21 01:54:14 PM PDT 24
Finished May 21 01:57:15 PM PDT 24
Peak memory 215792 kb
Host smart-9f094f87-6cbd-4653-b8e0-5f5b82169ec3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427714482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1427714482
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3034102412
Short name T422
Test name
Test status
Simulation time 9877553410 ps
CPU time 23.57 seconds
Started May 21 01:54:15 PM PDT 24
Finished May 21 01:54:40 PM PDT 24
Peak memory 212640 kb
Host smart-07411437-0160-4b53-b255-92885a29e6a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034102412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3034102412
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.420862142
Short name T440
Test name
Test status
Simulation time 34898578843 ps
CPU time 36.5 seconds
Started May 21 01:54:14 PM PDT 24
Finished May 21 01:54:52 PM PDT 24
Peak memory 218732 kb
Host smart-16b7647d-f16f-4b32-8a49-f1dfdae24975
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420862142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.420862142
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.196237466
Short name T439
Test name
Test status
Simulation time 11072218116 ps
CPU time 25.03 seconds
Started May 21 01:54:25 PM PDT 24
Finished May 21 01:54:51 PM PDT 24
Peak memory 217096 kb
Host smart-c152a4b0-c3ec-4d1f-a909-65e5dc22f0b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196237466 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.196237466
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2587783402
Short name T368
Test name
Test status
Simulation time 9542371897 ps
CPU time 19.93 seconds
Started May 21 01:54:21 PM PDT 24
Finished May 21 01:54:42 PM PDT 24
Peak memory 212200 kb
Host smart-88dafa1e-abc7-40dc-9441-571c5098ce37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587783402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2587783402
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3990059038
Short name T406
Test name
Test status
Simulation time 4094760592 ps
CPU time 57.28 seconds
Started May 21 01:54:14 PM PDT 24
Finished May 21 01:55:12 PM PDT 24
Peak memory 215468 kb
Host smart-4d9d2786-8964-4a36-898b-723e653e58b3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990059038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3990059038
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.84818339
Short name T394
Test name
Test status
Simulation time 10585793834 ps
CPU time 24.12 seconds
Started May 21 01:54:21 PM PDT 24
Finished May 21 01:54:45 PM PDT 24
Peak memory 212304 kb
Host smart-fabbca31-598c-43e9-a501-30fde568e313
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84818339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctr
l_same_csr_outstanding.84818339
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2586680263
Short name T428
Test name
Test status
Simulation time 675970036 ps
CPU time 18.21 seconds
Started May 21 01:54:20 PM PDT 24
Finished May 21 01:54:39 PM PDT 24
Peak memory 217324 kb
Host smart-3ac949cd-c3a7-48bc-b383-f48c36b2eba5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586680263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2586680263
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2770266815
Short name T111
Test name
Test status
Simulation time 14012510370 ps
CPU time 96.86 seconds
Started May 21 01:54:25 PM PDT 24
Finished May 21 01:56:03 PM PDT 24
Peak memory 213516 kb
Host smart-88bfa26e-0ef5-4f83-9876-30dcc145bc1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770266815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2770266815
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2586426690
Short name T458
Test name
Test status
Simulation time 217200165 ps
CPU time 9.29 seconds
Started May 21 01:54:20 PM PDT 24
Finished May 21 01:54:30 PM PDT 24
Peak memory 217204 kb
Host smart-fcef0074-5fdf-4c43-ac39-ff6b8e5b03a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586426690 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2586426690
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1651328056
Short name T444
Test name
Test status
Simulation time 7892107998 ps
CPU time 20.3 seconds
Started May 21 01:54:30 PM PDT 24
Finished May 21 01:54:51 PM PDT 24
Peak memory 212272 kb
Host smart-ce1c26b1-0541-4e47-ab36-b5f28c79db08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651328056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1651328056
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2105876515
Short name T84
Test name
Test status
Simulation time 32508525645 ps
CPU time 154.88 seconds
Started May 21 01:54:30 PM PDT 24
Finished May 21 01:57:06 PM PDT 24
Peak memory 215688 kb
Host smart-117f09d4-7ea9-4847-82ec-a6b8c84d1e83
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105876515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2105876515
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1837598318
Short name T431
Test name
Test status
Simulation time 4604098447 ps
CPU time 37.42 seconds
Started May 21 01:54:26 PM PDT 24
Finished May 21 01:55:04 PM PDT 24
Peak memory 212780 kb
Host smart-0e71e311-e25b-4863-b997-cce5dead9f83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837598318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1837598318
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3018920482
Short name T413
Test name
Test status
Simulation time 4206203367 ps
CPU time 25.29 seconds
Started May 21 01:54:30 PM PDT 24
Finished May 21 01:54:56 PM PDT 24
Peak memory 219148 kb
Host smart-1754cacc-32db-4618-99f9-de8dc70b170b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018920482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3018920482
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1554246398
Short name T56
Test name
Test status
Simulation time 2491830150 ps
CPU time 153.11 seconds
Started May 21 01:54:22 PM PDT 24
Finished May 21 01:56:56 PM PDT 24
Peak memory 213888 kb
Host smart-4c70d7be-28e1-4355-ae77-09a1e0a7897c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554246398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1554246398
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3347060622
Short name T229
Test name
Test status
Simulation time 2668853009 ps
CPU time 23.79 seconds
Started May 21 12:38:37 PM PDT 24
Finished May 21 12:39:11 PM PDT 24
Peak memory 211480 kb
Host smart-7d434dc9-7c21-4210-8688-6a154df2dfec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347060622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3347060622
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3198805704
Short name T22
Test name
Test status
Simulation time 54316828299 ps
CPU time 515.74 seconds
Started May 21 12:38:49 PM PDT 24
Finished May 21 12:47:38 PM PDT 24
Peak memory 216768 kb
Host smart-8e1ef3c8-9334-4aa8-b7d6-07ea3e659257
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198805704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3198805704
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1223786978
Short name T341
Test name
Test status
Simulation time 27464021988 ps
CPU time 61.53 seconds
Started May 21 12:38:23 PM PDT 24
Finished May 21 12:39:37 PM PDT 24
Peak memory 215080 kb
Host smart-b6674880-17c2-4ef0-8260-a5da1485452b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223786978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1223786978
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1513683649
Short name T308
Test name
Test status
Simulation time 762257894 ps
CPU time 10.31 seconds
Started May 21 12:38:24 PM PDT 24
Finished May 21 12:38:46 PM PDT 24
Peak memory 212404 kb
Host smart-af4267a0-a722-481a-9b37-2c137de7b38e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1513683649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1513683649
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2285976995
Short name T33
Test name
Test status
Simulation time 29145459898 ps
CPU time 244.76 seconds
Started May 21 12:38:31 PM PDT 24
Finished May 21 12:42:48 PM PDT 24
Peak memory 236820 kb
Host smart-3197508d-5dda-426f-ae51-6bcd225fbbed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285976995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2285976995
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2979346084
Short name T214
Test name
Test status
Simulation time 348383809 ps
CPU time 19.98 seconds
Started May 21 12:38:20 PM PDT 24
Finished May 21 12:38:53 PM PDT 24
Peak memory 213856 kb
Host smart-95d5158e-670d-4430-9962-e50b7c8289f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979346084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2979346084
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3254321029
Short name T164
Test name
Test status
Simulation time 22301641470 ps
CPU time 140.07 seconds
Started May 21 12:38:24 PM PDT 24
Finished May 21 12:40:56 PM PDT 24
Peak memory 227568 kb
Host smart-44f8d70e-274c-4077-b555-d2916789ea95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254321029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3254321029
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.504984953
Short name T30
Test name
Test status
Simulation time 59950139559 ps
CPU time 6769.1 seconds
Started May 21 12:39:03 PM PDT 24
Finished May 21 02:32:08 PM PDT 24
Peak memory 235904 kb
Host smart-b4525110-9c9e-402c-a7a2-897be7e14f08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504984953 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.504984953
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2950063264
Short name T322
Test name
Test status
Simulation time 36906760871 ps
CPU time 22.44 seconds
Started May 21 12:38:40 PM PDT 24
Finished May 21 12:39:13 PM PDT 24
Peak memory 211484 kb
Host smart-88156a50-bda9-4a2d-858b-8edbe7e16a05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950063264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2950063264
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1666321094
Short name T45
Test name
Test status
Simulation time 200101212077 ps
CPU time 526.96 seconds
Started May 21 12:38:38 PM PDT 24
Finished May 21 12:47:35 PM PDT 24
Peak memory 234100 kb
Host smart-f34cdf7e-30f9-4d49-8b16-9ec5bd6d1f80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666321094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1666321094
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1776497225
Short name T363
Test name
Test status
Simulation time 58045693710 ps
CPU time 53.94 seconds
Started May 21 12:38:33 PM PDT 24
Finished May 21 12:39:38 PM PDT 24
Peak memory 215108 kb
Host smart-fac17fed-278c-4778-93b0-c0165c26a47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776497225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1776497225
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3635525530
Short name T293
Test name
Test status
Simulation time 3999282898 ps
CPU time 33.48 seconds
Started May 21 12:38:36 PM PDT 24
Finished May 21 12:39:20 PM PDT 24
Peak memory 211564 kb
Host smart-71560358-1f2b-4836-9382-94d5a918e5e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3635525530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3635525530
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.943686901
Short name T34
Test name
Test status
Simulation time 2578121258 ps
CPU time 235.55 seconds
Started May 21 12:38:35 PM PDT 24
Finished May 21 12:42:42 PM PDT 24
Peak memory 239080 kb
Host smart-b6065d0f-ecea-4f12-a5b6-1e741aa1dfd8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943686901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.943686901
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.699964616
Short name T203
Test name
Test status
Simulation time 3102405288 ps
CPU time 26.77 seconds
Started May 21 12:38:26 PM PDT 24
Finished May 21 12:39:05 PM PDT 24
Peak memory 217112 kb
Host smart-fb618c2d-327e-4f7d-98a4-3cc8f8d0d946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699964616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.699964616
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.4130661052
Short name T349
Test name
Test status
Simulation time 7814814916 ps
CPU time 59.9 seconds
Started May 21 12:38:29 PM PDT 24
Finished May 21 12:39:41 PM PDT 24
Peak memory 219204 kb
Host smart-712f8353-43c5-4223-9b3f-7aff7dc5d3a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130661052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.4130661052
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2290942883
Short name T215
Test name
Test status
Simulation time 5688316067 ps
CPU time 25.44 seconds
Started May 21 12:38:32 PM PDT 24
Finished May 21 12:39:09 PM PDT 24
Peak memory 212320 kb
Host smart-398b9d4f-00f6-4bcf-87de-9d20bab14264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290942883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2290942883
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.564499440
Short name T278
Test name
Test status
Simulation time 76704445044 ps
CPU time 754.98 seconds
Started May 21 12:38:28 PM PDT 24
Finished May 21 12:51:15 PM PDT 24
Peak memory 245016 kb
Host smart-6286868b-b248-4e2c-8693-fd8f68241fbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564499440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.564499440
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.927175060
Short name T251
Test name
Test status
Simulation time 1450061012 ps
CPU time 10.68 seconds
Started May 21 12:38:28 PM PDT 24
Finished May 21 12:38:51 PM PDT 24
Peak memory 212520 kb
Host smart-716dd9b5-2649-4ed9-945b-58e9da2f944b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=927175060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.927175060
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1132560420
Short name T231
Test name
Test status
Simulation time 5622295889 ps
CPU time 52.42 seconds
Started May 21 12:38:29 PM PDT 24
Finished May 21 12:39:34 PM PDT 24
Peak memory 217488 kb
Host smart-2e0b16ab-a94e-42c1-a0d7-95d07454c935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132560420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1132560420
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.292294724
Short name T178
Test name
Test status
Simulation time 757192907 ps
CPU time 45.27 seconds
Started May 21 12:38:45 PM PDT 24
Finished May 21 12:39:42 PM PDT 24
Peak memory 218504 kb
Host smart-825fda61-d3c9-4463-9ca0-9781b22caadf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292294724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.292294724
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3777502930
Short name T325
Test name
Test status
Simulation time 1199362718 ps
CPU time 12.66 seconds
Started May 21 12:38:29 PM PDT 24
Finished May 21 12:38:53 PM PDT 24
Peak memory 211376 kb
Host smart-b9d2e630-6034-4560-bef2-1c9be627c215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777502930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3777502930
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2190092141
Short name T246
Test name
Test status
Simulation time 65957860455 ps
CPU time 400.06 seconds
Started May 21 12:38:43 PM PDT 24
Finished May 21 12:45:33 PM PDT 24
Peak memory 219700 kb
Host smart-8ad05378-85df-4026-b54d-5110925b1e0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190092141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2190092141
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2188587927
Short name T212
Test name
Test status
Simulation time 20344116000 ps
CPU time 36.41 seconds
Started May 21 12:38:50 PM PDT 24
Finished May 21 12:39:39 PM PDT 24
Peak memory 215120 kb
Host smart-026329bd-c4fa-497a-919f-3cd8948c2828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188587927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2188587927
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2480018476
Short name T281
Test name
Test status
Simulation time 12181970864 ps
CPU time 28.21 seconds
Started May 21 12:38:47 PM PDT 24
Finished May 21 12:39:28 PM PDT 24
Peak memory 211308 kb
Host smart-82cf7109-ecef-4cea-afde-803037c3a951
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2480018476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2480018476
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.4197609601
Short name T165
Test name
Test status
Simulation time 5205797790 ps
CPU time 56.63 seconds
Started May 21 12:38:28 PM PDT 24
Finished May 21 12:39:36 PM PDT 24
Peak memory 217188 kb
Host smart-0986228a-bd62-43d3-bbf5-8ec1ef298dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197609601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.4197609601
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3820938859
Short name T147
Test name
Test status
Simulation time 894369838 ps
CPU time 52.38 seconds
Started May 21 12:38:45 PM PDT 24
Finished May 21 12:39:49 PM PDT 24
Peak memory 219276 kb
Host smart-64be295d-3d6a-4d93-b1de-c77971dbd5c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820938859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3820938859
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1893318760
Short name T285
Test name
Test status
Simulation time 1829386232 ps
CPU time 8.13 seconds
Started May 21 12:38:53 PM PDT 24
Finished May 21 12:39:14 PM PDT 24
Peak memory 211360 kb
Host smart-d5c841a1-a56e-47b4-a88d-bb78d911530b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893318760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1893318760
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.169625402
Short name T136
Test name
Test status
Simulation time 6946800317 ps
CPU time 271.9 seconds
Started May 21 12:38:28 PM PDT 24
Finished May 21 12:43:12 PM PDT 24
Peak memory 237928 kb
Host smart-fff6d8b3-6506-4bb9-b0cc-89e667254bf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169625402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.169625402
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.390865652
Short name T359
Test name
Test status
Simulation time 15483083988 ps
CPU time 38.39 seconds
Started May 21 12:38:42 PM PDT 24
Finished May 21 12:39:31 PM PDT 24
Peak memory 215008 kb
Host smart-944d9e5e-c25a-43b2-87c8-fe2d9b6fc994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390865652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.390865652
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1360399204
Short name T289
Test name
Test status
Simulation time 3301312726 ps
CPU time 30.16 seconds
Started May 21 12:38:41 PM PDT 24
Finished May 21 12:39:22 PM PDT 24
Peak memory 211448 kb
Host smart-526bd687-11f8-43f2-8f94-44fe1dfd7290
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1360399204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1360399204
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3311567488
Short name T176
Test name
Test status
Simulation time 6605192520 ps
CPU time 68.96 seconds
Started May 21 12:38:28 PM PDT 24
Finished May 21 12:39:49 PM PDT 24
Peak memory 218224 kb
Host smart-8df7d790-04a6-42d7-82e7-fe5296a5e4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311567488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3311567488
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2996584312
Short name T355
Test name
Test status
Simulation time 2782136880 ps
CPU time 48.19 seconds
Started May 21 12:38:43 PM PDT 24
Finished May 21 12:39:42 PM PDT 24
Peak memory 215324 kb
Host smart-e85ec718-6d84-4b6f-b051-6bc08110bb1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996584312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2996584312
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3675052061
Short name T253
Test name
Test status
Simulation time 2552928723 ps
CPU time 23.04 seconds
Started May 21 12:38:30 PM PDT 24
Finished May 21 12:39:05 PM PDT 24
Peak memory 211436 kb
Host smart-1d511d14-2092-4966-a44c-728d2f03b072
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675052061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3675052061
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2060750311
Short name T19
Test name
Test status
Simulation time 315829955235 ps
CPU time 774.34 seconds
Started May 21 12:38:30 PM PDT 24
Finished May 21 12:51:36 PM PDT 24
Peak memory 237892 kb
Host smart-da30d6e2-f638-4a15-9cc3-87681eb284a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060750311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2060750311
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1834864703
Short name T254
Test name
Test status
Simulation time 6096529465 ps
CPU time 56.14 seconds
Started May 21 12:38:30 PM PDT 24
Finished May 21 12:39:37 PM PDT 24
Peak memory 215088 kb
Host smart-ef24ccb5-bcb6-4343-a5ff-7af2f5597297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834864703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1834864703
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4232350962
Short name T156
Test name
Test status
Simulation time 12495846633 ps
CPU time 18.48 seconds
Started May 21 12:38:47 PM PDT 24
Finished May 21 12:39:19 PM PDT 24
Peak memory 212780 kb
Host smart-5a8801b7-bdeb-4de2-993b-b6dbab575266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4232350962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4232350962
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1923900301
Short name T280
Test name
Test status
Simulation time 1400698581 ps
CPU time 20.48 seconds
Started May 21 12:38:28 PM PDT 24
Finished May 21 12:39:01 PM PDT 24
Peak memory 215668 kb
Host smart-680e864d-4bb6-4523-ae22-4bdca4669f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923900301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1923900301
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.4228003691
Short name T13
Test name
Test status
Simulation time 41471437887 ps
CPU time 92.33 seconds
Started May 21 12:38:28 PM PDT 24
Finished May 21 12:40:12 PM PDT 24
Peak memory 219244 kb
Host smart-9a7ee7bb-deb5-41ea-9210-9b2db353b3e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228003691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.4228003691
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1516121081
Short name T347
Test name
Test status
Simulation time 21756340448 ps
CPU time 28.91 seconds
Started May 21 12:39:48 PM PDT 24
Finished May 21 12:40:27 PM PDT 24
Peak memory 212132 kb
Host smart-1eac668f-1feb-4490-9a8c-98e5aefe5c20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516121081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1516121081
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3519788192
Short name T46
Test name
Test status
Simulation time 44922576032 ps
CPU time 502.58 seconds
Started May 21 12:38:41 PM PDT 24
Finished May 21 12:47:15 PM PDT 24
Peak memory 237792 kb
Host smart-c3d3e1fb-344c-406e-9983-39bc01b6661f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519788192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3519788192
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3742620125
Short name T276
Test name
Test status
Simulation time 79395816169 ps
CPU time 54.77 seconds
Started May 21 12:38:50 PM PDT 24
Finished May 21 12:39:57 PM PDT 24
Peak memory 215172 kb
Host smart-b1fc3522-feb0-49ff-838b-97c217d96239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742620125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3742620125
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.878339146
Short name T337
Test name
Test status
Simulation time 12253933627 ps
CPU time 28.59 seconds
Started May 21 12:38:31 PM PDT 24
Finished May 21 12:39:12 PM PDT 24
Peak memory 211644 kb
Host smart-313bda47-c1a3-47f2-b1e9-26c67e390453
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=878339146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.878339146
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2273395140
Short name T291
Test name
Test status
Simulation time 4459807592 ps
CPU time 61.13 seconds
Started May 21 12:38:30 PM PDT 24
Finished May 21 12:39:43 PM PDT 24
Peak memory 215508 kb
Host smart-7d71b1cd-0cf8-410e-85ef-10bf1af0b171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273395140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2273395140
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1493947277
Short name T202
Test name
Test status
Simulation time 7194529726 ps
CPU time 28.44 seconds
Started May 21 12:39:41 PM PDT 24
Finished May 21 12:40:19 PM PDT 24
Peak memory 212232 kb
Host smart-de673eb2-bc5a-4cbe-8a7c-ce087ea9af1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493947277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1493947277
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.485538164
Short name T270
Test name
Test status
Simulation time 5663543644 ps
CPU time 365.92 seconds
Started May 21 12:39:42 PM PDT 24
Finished May 21 12:45:58 PM PDT 24
Peak memory 217944 kb
Host smart-435a4c14-333d-4b10-b948-2fe69f61e368
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485538164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.485538164
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3521359005
Short name T143
Test name
Test status
Simulation time 496587487 ps
CPU time 21.77 seconds
Started May 21 12:39:48 PM PDT 24
Finished May 21 12:40:20 PM PDT 24
Peak memory 214516 kb
Host smart-635a5291-1d72-4dd1-a25d-48d53d63ddcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521359005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3521359005
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2400508302
Short name T317
Test name
Test status
Simulation time 4096333443 ps
CPU time 22.55 seconds
Started May 21 12:38:45 PM PDT 24
Finished May 21 12:39:19 PM PDT 24
Peak memory 211440 kb
Host smart-a0b83086-2a5f-4a9d-9af7-9222df5c5875
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2400508302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2400508302
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2856650609
Short name T292
Test name
Test status
Simulation time 1542174862 ps
CPU time 31.92 seconds
Started May 21 12:38:38 PM PDT 24
Finished May 21 12:39:20 PM PDT 24
Peak memory 216540 kb
Host smart-0ed3a650-1714-4b1f-898e-3e10f1dd50b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856650609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2856650609
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1312784880
Short name T239
Test name
Test status
Simulation time 31634818429 ps
CPU time 91.05 seconds
Started May 21 12:38:47 PM PDT 24
Finished May 21 12:40:30 PM PDT 24
Peak memory 219356 kb
Host smart-62d51bbf-745b-45f2-ac63-40131e8679f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312784880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1312784880
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1738671714
Short name T332
Test name
Test status
Simulation time 25736444731 ps
CPU time 32.03 seconds
Started May 21 12:38:36 PM PDT 24
Finished May 21 12:39:18 PM PDT 24
Peak memory 212372 kb
Host smart-30cf7f94-34be-450b-846a-87375e58c7ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738671714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1738671714
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3158911411
Short name T40
Test name
Test status
Simulation time 403579530882 ps
CPU time 740.88 seconds
Started May 21 12:38:47 PM PDT 24
Finished May 21 12:51:20 PM PDT 24
Peak memory 217824 kb
Host smart-18225147-ac2f-497d-a67d-5997eb627284
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158911411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3158911411
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1876946646
Short name T181
Test name
Test status
Simulation time 8231685866 ps
CPU time 22.61 seconds
Started May 21 12:38:48 PM PDT 24
Finished May 21 12:39:23 PM PDT 24
Peak memory 212824 kb
Host smart-69c567b9-ca57-4ab2-9515-42d00a1e21e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1876946646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1876946646
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.4075118143
Short name T112
Test name
Test status
Simulation time 344714337 ps
CPU time 20.13 seconds
Started May 21 12:38:48 PM PDT 24
Finished May 21 12:39:21 PM PDT 24
Peak memory 215712 kb
Host smart-4d73488a-32b2-432d-92d8-8f1f9e8d2f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075118143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.4075118143
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1049450837
Short name T126
Test name
Test status
Simulation time 7898246092 ps
CPU time 31.2 seconds
Started May 21 12:38:46 PM PDT 24
Finished May 21 12:39:30 PM PDT 24
Peak memory 212588 kb
Host smart-af7338ce-0169-414a-9a30-7b56a520d20d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049450837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1049450837
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2473685282
Short name T190
Test name
Test status
Simulation time 19198721202 ps
CPU time 256.1 seconds
Started May 21 12:38:47 PM PDT 24
Finished May 21 12:43:16 PM PDT 24
Peak memory 240056 kb
Host smart-1f7101e1-cba6-4687-98ef-9015b1095a73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473685282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2473685282
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2255282720
Short name T192
Test name
Test status
Simulation time 6567297931 ps
CPU time 30.37 seconds
Started May 21 12:39:04 PM PDT 24
Finished May 21 12:39:44 PM PDT 24
Peak memory 215448 kb
Host smart-68edffcb-0ab9-4d0a-a6e7-9ce18fc836c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255282720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2255282720
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3090669021
Short name T288
Test name
Test status
Simulation time 351708013 ps
CPU time 10.46 seconds
Started May 21 12:38:50 PM PDT 24
Finished May 21 12:39:14 PM PDT 24
Peak memory 212244 kb
Host smart-0c78a9d8-ef28-4c55-97b7-fe064208500d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3090669021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3090669021
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2176526497
Short name T311
Test name
Test status
Simulation time 17636835202 ps
CPU time 170.88 seconds
Started May 21 12:38:47 PM PDT 24
Finished May 21 12:41:51 PM PDT 24
Peak memory 219360 kb
Host smart-cab80107-1ebc-4efc-8b44-b0be0037722a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176526497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2176526497
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2329003863
Short name T28
Test name
Test status
Simulation time 17703618274 ps
CPU time 663.07 seconds
Started May 21 12:38:49 PM PDT 24
Finished May 21 12:50:06 PM PDT 24
Peak memory 235812 kb
Host smart-90e8aae5-242d-44d2-8f67-55f1329a98ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329003863 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2329003863
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1575873732
Short name T354
Test name
Test status
Simulation time 1148585245 ps
CPU time 16.54 seconds
Started May 21 12:38:47 PM PDT 24
Finished May 21 12:39:17 PM PDT 24
Peak memory 211360 kb
Host smart-9574e413-bfd4-43bf-8e04-48b00389f421
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575873732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1575873732
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.979593250
Short name T258
Test name
Test status
Simulation time 19313691785 ps
CPU time 281.98 seconds
Started May 21 12:38:39 PM PDT 24
Finished May 21 12:43:32 PM PDT 24
Peak memory 217808 kb
Host smart-d662dfe4-805d-48db-a66d-029de130b148
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979593250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.979593250
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2283914899
Short name T346
Test name
Test status
Simulation time 1503864154 ps
CPU time 19.09 seconds
Started May 21 12:38:46 PM PDT 24
Finished May 21 12:39:17 PM PDT 24
Peak memory 215160 kb
Host smart-61923291-2c19-4002-8980-a8dae430d07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283914899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2283914899
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2796389435
Short name T256
Test name
Test status
Simulation time 4166594264 ps
CPU time 33.29 seconds
Started May 21 12:38:47 PM PDT 24
Finished May 21 12:39:33 PM PDT 24
Peak memory 212248 kb
Host smart-4b06dd1e-d25d-4ebb-93c9-4970dd1e22ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2796389435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2796389435
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3503732034
Short name T195
Test name
Test status
Simulation time 25470306359 ps
CPU time 63.53 seconds
Started May 21 12:38:47 PM PDT 24
Finished May 21 12:40:03 PM PDT 24
Peak memory 215636 kb
Host smart-fd0c9357-1781-4bd9-964f-c93dfaf9f38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503732034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3503732034
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3510874886
Short name T266
Test name
Test status
Simulation time 6779627175 ps
CPU time 33.95 seconds
Started May 21 12:39:48 PM PDT 24
Finished May 21 12:40:33 PM PDT 24
Peak memory 218960 kb
Host smart-6e26c1b5-7be6-44ce-987c-d19c7ca74a5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510874886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3510874886
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3926032684
Short name T242
Test name
Test status
Simulation time 2903054481 ps
CPU time 24.38 seconds
Started May 21 12:39:53 PM PDT 24
Finished May 21 12:40:27 PM PDT 24
Peak memory 211048 kb
Host smart-d88d2218-2248-43d9-9edb-6dd2426bf257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926032684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3926032684
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3747092341
Short name T186
Test name
Test status
Simulation time 148053549421 ps
CPU time 288.91 seconds
Started May 21 12:38:41 PM PDT 24
Finished May 21 12:43:41 PM PDT 24
Peak memory 225720 kb
Host smart-fd4ef548-73b3-4555-8b56-a2f8cf5acb3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747092341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3747092341
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3456515646
Short name T134
Test name
Test status
Simulation time 4931548928 ps
CPU time 47.57 seconds
Started May 21 12:38:45 PM PDT 24
Finished May 21 12:39:44 PM PDT 24
Peak memory 215120 kb
Host smart-c67dde95-d556-4499-9696-2b33116a2e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456515646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3456515646
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4153732412
Short name T12
Test name
Test status
Simulation time 3758102172 ps
CPU time 23.39 seconds
Started May 21 12:38:44 PM PDT 24
Finished May 21 12:39:19 PM PDT 24
Peak memory 212076 kb
Host smart-8fc78b0d-e37c-4ea0-8902-32f482ff46e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4153732412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4153732412
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1231912958
Short name T329
Test name
Test status
Simulation time 356365009 ps
CPU time 19.53 seconds
Started May 21 12:39:44 PM PDT 24
Finished May 21 12:40:14 PM PDT 24
Peak memory 214932 kb
Host smart-c1dc515b-b3ae-428b-8af4-c81e1642e86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231912958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1231912958
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.888693699
Short name T73
Test name
Test status
Simulation time 3694223566 ps
CPU time 49.9 seconds
Started May 21 12:38:44 PM PDT 24
Finished May 21 12:39:46 PM PDT 24
Peak memory 219392 kb
Host smart-b61f4ba7-d469-4bca-9268-4b7f649674d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888693699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.888693699
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.331262787
Short name T232
Test name
Test status
Simulation time 1780715300 ps
CPU time 14.58 seconds
Started May 21 12:38:25 PM PDT 24
Finished May 21 12:38:52 PM PDT 24
Peak memory 211252 kb
Host smart-d03e663b-400d-4a60-ad6c-466c352d4d08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331262787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.331262787
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1256784276
Short name T180
Test name
Test status
Simulation time 113103737710 ps
CPU time 320.43 seconds
Started May 21 12:38:41 PM PDT 24
Finished May 21 12:44:12 PM PDT 24
Peak memory 239816 kb
Host smart-98b319c5-baec-49a3-bf91-83034e733c13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256784276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1256784276
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1577050923
Short name T227
Test name
Test status
Simulation time 25502425288 ps
CPU time 47.84 seconds
Started May 21 12:38:46 PM PDT 24
Finished May 21 12:39:47 PM PDT 24
Peak memory 215096 kb
Host smart-3f6dcefd-799f-46ea-bdef-6f1966940716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577050923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1577050923
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2205106232
Short name T122
Test name
Test status
Simulation time 11339536597 ps
CPU time 26.51 seconds
Started May 21 12:38:39 PM PDT 24
Finished May 21 12:39:16 PM PDT 24
Peak memory 211744 kb
Host smart-430606a1-394e-4da6-88a5-e34ae701d602
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2205106232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2205106232
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1743529600
Short name T37
Test name
Test status
Simulation time 7140383749 ps
CPU time 128.4 seconds
Started May 21 12:38:41 PM PDT 24
Finished May 21 12:41:00 PM PDT 24
Peak memory 237924 kb
Host smart-9c33052f-feee-44a3-8352-7190eae5ef18
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743529600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1743529600
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1301140531
Short name T309
Test name
Test status
Simulation time 7428493309 ps
CPU time 69.61 seconds
Started May 21 12:38:26 PM PDT 24
Finished May 21 12:39:48 PM PDT 24
Peak memory 217524 kb
Host smart-fdbf3e45-38c7-464d-951a-a67c03ef476f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301140531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1301140531
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2786972906
Short name T303
Test name
Test status
Simulation time 27101545729 ps
CPU time 61.58 seconds
Started May 21 12:38:26 PM PDT 24
Finished May 21 12:39:40 PM PDT 24
Peak memory 218272 kb
Host smart-37e514a7-55a5-4589-bc9f-deaef5be601c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786972906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2786972906
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1548839816
Short name T318
Test name
Test status
Simulation time 101091435579 ps
CPU time 1262.12 seconds
Started May 21 12:38:44 PM PDT 24
Finished May 21 12:59:58 PM PDT 24
Peak memory 236660 kb
Host smart-e7f4fba6-1f17-4df0-aab2-2ed20f901f85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548839816 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1548839816
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2066152690
Short name T198
Test name
Test status
Simulation time 2256230506 ps
CPU time 10.12 seconds
Started May 21 12:38:44 PM PDT 24
Finished May 21 12:39:05 PM PDT 24
Peak memory 211484 kb
Host smart-50ef272d-b03d-49f5-ab1d-f597efeb23d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066152690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2066152690
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1005952894
Short name T336
Test name
Test status
Simulation time 278036359685 ps
CPU time 532.32 seconds
Started May 21 12:38:37 PM PDT 24
Finished May 21 12:47:40 PM PDT 24
Peak memory 234652 kb
Host smart-ae46df23-678e-4270-be13-d00efa45cb13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005952894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1005952894
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2496247148
Short name T130
Test name
Test status
Simulation time 23178952987 ps
CPU time 52.15 seconds
Started May 21 12:38:51 PM PDT 24
Finished May 21 12:39:56 PM PDT 24
Peak memory 215168 kb
Host smart-7f7e018d-6cfc-407f-ae7a-e7147c043c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496247148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2496247148
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1488573612
Short name T120
Test name
Test status
Simulation time 4993879505 ps
CPU time 33.62 seconds
Started May 21 12:38:46 PM PDT 24
Finished May 21 12:39:32 PM PDT 24
Peak memory 211488 kb
Host smart-04927e85-564b-4bd3-b0ae-d59a3b0fa778
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1488573612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1488573612
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2031176551
Short name T283
Test name
Test status
Simulation time 8203168103 ps
CPU time 39.14 seconds
Started May 21 12:38:45 PM PDT 24
Finished May 21 12:39:36 PM PDT 24
Peak memory 218712 kb
Host smart-1182fcbe-54df-41e9-b15f-783faed8ae88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031176551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2031176551
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.425099760
Short name T128
Test name
Test status
Simulation time 10037926492 ps
CPU time 100.24 seconds
Started May 21 12:38:47 PM PDT 24
Finished May 21 12:40:40 PM PDT 24
Peak memory 218812 kb
Host smart-1b066beb-0a2f-4c57-99cf-a20d22bb2823
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425099760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.425099760
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2865458021
Short name T62
Test name
Test status
Simulation time 2435804127 ps
CPU time 22.51 seconds
Started May 21 12:39:41 PM PDT 24
Finished May 21 12:40:13 PM PDT 24
Peak memory 211392 kb
Host smart-bcb92d40-bb84-4c80-b757-7f51e6cb92c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865458021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2865458021
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.654036498
Short name T324
Test name
Test status
Simulation time 137237432810 ps
CPU time 366.9 seconds
Started May 21 12:38:47 PM PDT 24
Finished May 21 12:45:07 PM PDT 24
Peak memory 236732 kb
Host smart-711eaf59-e3ba-4b93-9ac7-b1dc25e3e82e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654036498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.654036498
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2206226220
Short name T348
Test name
Test status
Simulation time 25599685866 ps
CPU time 55.74 seconds
Started May 21 12:38:45 PM PDT 24
Finished May 21 12:39:52 PM PDT 24
Peak memory 214080 kb
Host smart-a7bdf824-56f1-4769-91d7-57b722b72e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206226220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2206226220
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.4185591516
Short name T221
Test name
Test status
Simulation time 870897969 ps
CPU time 12.81 seconds
Started May 21 12:38:43 PM PDT 24
Finished May 21 12:39:06 PM PDT 24
Peak memory 211236 kb
Host smart-60ccbd19-b512-4b1b-99a4-ca2fd922ac85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4185591516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.4185591516
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.218627141
Short name T284
Test name
Test status
Simulation time 7591188946 ps
CPU time 62.53 seconds
Started May 21 12:38:45 PM PDT 24
Finished May 21 12:40:00 PM PDT 24
Peak memory 216784 kb
Host smart-7cca8aed-0ce9-411e-a6bd-374e9e9a0318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218627141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.218627141
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.434742187
Short name T79
Test name
Test status
Simulation time 6415470504 ps
CPU time 90.68 seconds
Started May 21 12:38:52 PM PDT 24
Finished May 21 12:40:35 PM PDT 24
Peak memory 220000 kb
Host smart-4ea43865-c3d9-45ff-adee-bfdd0f29fe66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434742187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.434742187
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2181849489
Short name T158
Test name
Test status
Simulation time 3589533072 ps
CPU time 27.9 seconds
Started May 21 12:38:47 PM PDT 24
Finished May 21 12:39:28 PM PDT 24
Peak memory 212088 kb
Host smart-8322c367-5a35-47fb-b846-b667cd158237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181849489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2181849489
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2684594613
Short name T248
Test name
Test status
Simulation time 79614936968 ps
CPU time 783.95 seconds
Started May 21 12:38:53 PM PDT 24
Finished May 21 12:52:09 PM PDT 24
Peak memory 217028 kb
Host smart-da9e2adb-c8fc-4c78-9e79-2db938c8cd32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684594613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2684594613
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1655484495
Short name T14
Test name
Test status
Simulation time 350108007 ps
CPU time 18.5 seconds
Started May 21 12:39:53 PM PDT 24
Finished May 21 12:40:21 PM PDT 24
Peak memory 214036 kb
Host smart-2df76342-303c-4ff8-9df6-d6792d41eb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655484495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1655484495
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2939002414
Short name T138
Test name
Test status
Simulation time 1022997219 ps
CPU time 16.44 seconds
Started May 21 12:39:48 PM PDT 24
Finished May 21 12:40:15 PM PDT 24
Peak memory 212032 kb
Host smart-96c44164-86c6-4a98-b45f-b31f867f6e7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2939002414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2939002414
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1241106199
Short name T197
Test name
Test status
Simulation time 1031317380 ps
CPU time 24.33 seconds
Started May 21 12:38:49 PM PDT 24
Finished May 21 12:39:26 PM PDT 24
Peak memory 217596 kb
Host smart-a2f04b12-abb3-4b18-a66d-dd7f1917a9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241106199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1241106199
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1037650311
Short name T330
Test name
Test status
Simulation time 3245082165 ps
CPU time 53.43 seconds
Started May 21 12:38:44 PM PDT 24
Finished May 21 12:39:49 PM PDT 24
Peak memory 219428 kb
Host smart-a46645c6-9e0d-43d6-a69a-48346c30dd06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037650311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1037650311
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3494689918
Short name T162
Test name
Test status
Simulation time 3757367138 ps
CPU time 29.54 seconds
Started May 21 12:38:54 PM PDT 24
Finished May 21 12:39:36 PM PDT 24
Peak memory 211992 kb
Host smart-e3acd6aa-a7e7-40ee-aeb8-0ca9a037a9c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494689918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3494689918
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1375451039
Short name T23
Test name
Test status
Simulation time 20322968393 ps
CPU time 316.69 seconds
Started May 21 12:38:46 PM PDT 24
Finished May 21 12:44:16 PM PDT 24
Peak memory 240960 kb
Host smart-d632f072-45d6-459e-bb1d-7af0eaa10177
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375451039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1375451039
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2377779323
Short name T295
Test name
Test status
Simulation time 3298393871 ps
CPU time 18.89 seconds
Started May 21 12:38:48 PM PDT 24
Finished May 21 12:39:20 PM PDT 24
Peak memory 214868 kb
Host smart-9dfa950e-ed16-4cde-8d88-2fb74921bd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377779323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2377779323
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2815591045
Short name T255
Test name
Test status
Simulation time 17790681561 ps
CPU time 33.4 seconds
Started May 21 12:38:50 PM PDT 24
Finished May 21 12:39:36 PM PDT 24
Peak memory 212744 kb
Host smart-3e2ecfcb-543b-42e5-9f3a-3ff0379bb1ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2815591045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2815591045
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2805769683
Short name T260
Test name
Test status
Simulation time 14755932182 ps
CPU time 68.37 seconds
Started May 21 12:39:11 PM PDT 24
Finished May 21 12:40:28 PM PDT 24
Peak memory 217764 kb
Host smart-2b91d545-d0c9-4bf7-8f1e-b417969a935b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805769683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2805769683
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1338373406
Short name T189
Test name
Test status
Simulation time 2675467575 ps
CPU time 83.01 seconds
Started May 21 12:38:49 PM PDT 24
Finished May 21 12:40:25 PM PDT 24
Peak memory 219380 kb
Host smart-e7ab6bc6-6a72-4a00-a313-5467007e591d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338373406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1338373406
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.4146616022
Short name T209
Test name
Test status
Simulation time 4130350841 ps
CPU time 11.55 seconds
Started May 21 12:38:50 PM PDT 24
Finished May 21 12:39:15 PM PDT 24
Peak memory 211484 kb
Host smart-9054b70f-e66f-4b51-8244-3aa09e1035be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146616022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.4146616022
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2962577216
Short name T219
Test name
Test status
Simulation time 16551171855 ps
CPU time 164.74 seconds
Started May 21 12:38:47 PM PDT 24
Finished May 21 12:41:44 PM PDT 24
Peak memory 224744 kb
Host smart-4190a626-1d1c-444b-9d59-7b70821f3ec9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962577216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2962577216
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1437271
Short name T323
Test name
Test status
Simulation time 1971308211 ps
CPU time 31.29 seconds
Started May 21 12:38:50 PM PDT 24
Finished May 21 12:39:34 PM PDT 24
Peak memory 214644 kb
Host smart-bb96558d-f3dd-4b49-8f35-bba144eb297d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1437271
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3701805812
Short name T191
Test name
Test status
Simulation time 5576081155 ps
CPU time 27.15 seconds
Started May 21 12:38:52 PM PDT 24
Finished May 21 12:39:32 PM PDT 24
Peak memory 212892 kb
Host smart-ab434203-eb4c-41f3-979a-38bff3b1a90d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3701805812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3701805812
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3234913398
Short name T75
Test name
Test status
Simulation time 2802247981 ps
CPU time 20.71 seconds
Started May 21 12:38:42 PM PDT 24
Finished May 21 12:39:13 PM PDT 24
Peak memory 217056 kb
Host smart-9c7e64ec-f982-43fd-b9ba-22e327e0cbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234913398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3234913398
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.955263956
Short name T233
Test name
Test status
Simulation time 10119536138 ps
CPU time 108.6 seconds
Started May 21 12:38:50 PM PDT 24
Finished May 21 12:40:51 PM PDT 24
Peak memory 219420 kb
Host smart-1be4a3ec-cc87-4f3c-a708-bc25e553cf51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955263956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.955263956
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1676926856
Short name T315
Test name
Test status
Simulation time 915817191 ps
CPU time 8.46 seconds
Started May 21 12:38:52 PM PDT 24
Finished May 21 12:39:13 PM PDT 24
Peak memory 211300 kb
Host smart-dc9eada8-a834-4523-a786-def2b05cae3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676926856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1676926856
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.250158827
Short name T345
Test name
Test status
Simulation time 217888072817 ps
CPU time 230.48 seconds
Started May 21 12:38:48 PM PDT 24
Finished May 21 12:42:51 PM PDT 24
Peak memory 240520 kb
Host smart-70c1bc07-9c40-4f26-860f-3cf2d1693623
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250158827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.250158827
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2268162481
Short name T331
Test name
Test status
Simulation time 10610977511 ps
CPU time 49.88 seconds
Started May 21 12:38:49 PM PDT 24
Finished May 21 12:39:52 PM PDT 24
Peak memory 213984 kb
Host smart-d40ba731-026d-448b-a231-cc84b2b31a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268162481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2268162481
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1782016389
Short name T113
Test name
Test status
Simulation time 1590341000 ps
CPU time 14.77 seconds
Started May 21 12:38:50 PM PDT 24
Finished May 21 12:39:18 PM PDT 24
Peak memory 212256 kb
Host smart-5aab5b53-4427-4ec4-a16d-b358ee4cad22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1782016389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1782016389
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.230722716
Short name T9
Test name
Test status
Simulation time 4444798199 ps
CPU time 50.4 seconds
Started May 21 12:39:05 PM PDT 24
Finished May 21 12:40:05 PM PDT 24
Peak memory 217752 kb
Host smart-61473a2c-c9d4-4f38-b0fa-18ff1bfc63c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230722716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.230722716
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2327189158
Short name T230
Test name
Test status
Simulation time 5057202053 ps
CPU time 61.85 seconds
Started May 21 12:39:00 PM PDT 24
Finished May 21 12:40:12 PM PDT 24
Peak memory 219464 kb
Host smart-04c09766-de25-47b1-b20d-a108cb414168
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327189158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2327189158
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.821310163
Short name T61
Test name
Test status
Simulation time 25718862170 ps
CPU time 20.17 seconds
Started May 21 12:38:48 PM PDT 24
Finished May 21 12:39:21 PM PDT 24
Peak memory 212356 kb
Host smart-f42475be-944a-4eff-bf58-de4f75661a15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821310163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.821310163
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3495674112
Short name T129
Test name
Test status
Simulation time 139508771478 ps
CPU time 615.21 seconds
Started May 21 12:39:53 PM PDT 24
Finished May 21 12:50:18 PM PDT 24
Peak memory 224776 kb
Host smart-d4c3964b-7b3e-4880-a931-e8a840a23a74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495674112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3495674112
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3469604775
Short name T183
Test name
Test status
Simulation time 16372552302 ps
CPU time 42.13 seconds
Started May 21 12:39:53 PM PDT 24
Finished May 21 12:40:45 PM PDT 24
Peak memory 212588 kb
Host smart-34e2aaff-8055-4701-b4c6-871c655405d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469604775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3469604775
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3980673308
Short name T200
Test name
Test status
Simulation time 754911270 ps
CPU time 14.43 seconds
Started May 21 12:39:52 PM PDT 24
Finished May 21 12:40:17 PM PDT 24
Peak memory 211740 kb
Host smart-6b9c3eb4-762e-4368-a830-0551bc01379e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3980673308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3980673308
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.762968260
Short name T78
Test name
Test status
Simulation time 2867748359 ps
CPU time 39.07 seconds
Started May 21 12:38:50 PM PDT 24
Finished May 21 12:39:46 PM PDT 24
Peak memory 216844 kb
Host smart-f7e4284a-549b-4e3b-a1d3-0a29b7280001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762968260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.762968260
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1233150622
Short name T31
Test name
Test status
Simulation time 211471439574 ps
CPU time 1955.58 seconds
Started May 21 12:38:54 PM PDT 24
Finished May 21 01:11:42 PM PDT 24
Peak memory 238900 kb
Host smart-d8753438-bd0d-419b-b43e-5ade2c080b2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233150622 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1233150622
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1026412287
Short name T36
Test name
Test status
Simulation time 3273496410 ps
CPU time 18.44 seconds
Started May 21 12:38:54 PM PDT 24
Finished May 21 12:39:25 PM PDT 24
Peak memory 212024 kb
Host smart-d77e9b6d-8a00-4425-96f9-a3c704f0bc03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026412287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1026412287
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3004119083
Short name T243
Test name
Test status
Simulation time 113428953160 ps
CPU time 446.47 seconds
Started May 21 12:38:48 PM PDT 24
Finished May 21 12:46:27 PM PDT 24
Peak memory 216756 kb
Host smart-6186f8e9-1137-4566-8d2b-4053643e3560
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004119083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3004119083
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3461272820
Short name T116
Test name
Test status
Simulation time 33931334724 ps
CPU time 70.61 seconds
Started May 21 12:38:53 PM PDT 24
Finished May 21 12:40:16 PM PDT 24
Peak memory 215124 kb
Host smart-571d228c-06c2-4426-bf8b-cd89a9704b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461272820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3461272820
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3082253010
Short name T343
Test name
Test status
Simulation time 941020341 ps
CPU time 13.71 seconds
Started May 21 12:39:53 PM PDT 24
Finished May 21 12:40:17 PM PDT 24
Peak memory 211756 kb
Host smart-3c1a9752-1575-4e4f-bd5e-126b37565f80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3082253010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3082253010
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3341737684
Short name T296
Test name
Test status
Simulation time 360135630 ps
CPU time 20.04 seconds
Started May 21 12:38:55 PM PDT 24
Finished May 21 12:39:27 PM PDT 24
Peak memory 216904 kb
Host smart-2fd4218c-29a0-4d41-bd75-1e79c86821e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341737684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3341737684
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.73609045
Short name T275
Test name
Test status
Simulation time 107170071931 ps
CPU time 79.18 seconds
Started May 21 12:38:51 PM PDT 24
Finished May 21 12:40:23 PM PDT 24
Peak memory 219572 kb
Host smart-132d98ea-c746-4010-bcc7-d1f1baa7ea0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73609045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 27.rom_ctrl_stress_all.73609045
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2806746640
Short name T304
Test name
Test status
Simulation time 3404221788 ps
CPU time 25.09 seconds
Started May 21 12:38:48 PM PDT 24
Finished May 21 12:39:26 PM PDT 24
Peak memory 211484 kb
Host smart-64401f96-d985-4504-8352-62ae280f578c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806746640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2806746640
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.4123876815
Short name T117
Test name
Test status
Simulation time 903451894057 ps
CPU time 883.91 seconds
Started May 21 12:39:53 PM PDT 24
Finished May 21 12:54:46 PM PDT 24
Peak memory 229212 kb
Host smart-78b35ba6-ea49-4809-9e8a-65db8e0c6d54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123876815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.4123876815
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1168932695
Short name T226
Test name
Test status
Simulation time 703529910 ps
CPU time 18.88 seconds
Started May 21 12:38:47 PM PDT 24
Finished May 21 12:39:19 PM PDT 24
Peak memory 214608 kb
Host smart-9acbae2a-ac9f-4c83-babe-a1d676ab712a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168932695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1168932695
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1103471403
Short name T339
Test name
Test status
Simulation time 183431333 ps
CPU time 10.08 seconds
Started May 21 12:38:50 PM PDT 24
Finished May 21 12:39:13 PM PDT 24
Peak memory 212056 kb
Host smart-8ee81b0b-ab20-4aa3-87cd-2f3da6f19841
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103471403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1103471403
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.36488444
Short name T272
Test name
Test status
Simulation time 5220507994 ps
CPU time 25.79 seconds
Started May 21 12:38:51 PM PDT 24
Finished May 21 12:39:29 PM PDT 24
Peak memory 217272 kb
Host smart-3423ef33-4cba-4c9d-b3b1-bb53b06d755c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36488444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.36488444
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1656756417
Short name T263
Test name
Test status
Simulation time 7700324321 ps
CPU time 72.3 seconds
Started May 21 12:39:53 PM PDT 24
Finished May 21 12:41:15 PM PDT 24
Peak memory 215332 kb
Host smart-8873cb77-0f08-4f8e-aaa4-8ff7c6a27895
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656756417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1656756417
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3991917213
Short name T196
Test name
Test status
Simulation time 1539726721 ps
CPU time 17.98 seconds
Started May 21 12:39:08 PM PDT 24
Finished May 21 12:39:36 PM PDT 24
Peak memory 211372 kb
Host smart-dd7df870-64af-4bb3-bd7b-43f3bd6b1277
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991917213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3991917213
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2055604164
Short name T342
Test name
Test status
Simulation time 111875788411 ps
CPU time 59.8 seconds
Started May 21 12:38:50 PM PDT 24
Finished May 21 12:40:03 PM PDT 24
Peak memory 215152 kb
Host smart-43ef2059-2c13-48e6-b799-3356f344df2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055604164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2055604164
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.560546459
Short name T261
Test name
Test status
Simulation time 347358860 ps
CPU time 10.3 seconds
Started May 21 12:38:50 PM PDT 24
Finished May 21 12:39:13 PM PDT 24
Peak memory 212440 kb
Host smart-43b14539-2027-4a98-9dab-c491b9f1f443
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=560546459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.560546459
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2764250602
Short name T364
Test name
Test status
Simulation time 22304264891 ps
CPU time 56.55 seconds
Started May 21 12:38:53 PM PDT 24
Finished May 21 12:40:02 PM PDT 24
Peak memory 218684 kb
Host smart-0ad5d03f-9903-43f3-a774-90c9aa46fa9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764250602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2764250602
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.329127111
Short name T334
Test name
Test status
Simulation time 6192665125 ps
CPU time 62.03 seconds
Started May 21 12:39:23 PM PDT 24
Finished May 21 12:40:35 PM PDT 24
Peak memory 218876 kb
Host smart-23795c47-d04e-44db-a7a9-d339e1857542
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329127111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.329127111
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1124693201
Short name T27
Test name
Test status
Simulation time 28501242669 ps
CPU time 1059.95 seconds
Started May 21 12:38:48 PM PDT 24
Finished May 21 12:56:41 PM PDT 24
Peak memory 236508 kb
Host smart-f6c3d79f-89ca-4db8-bb94-535df421cf1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124693201 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1124693201
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2443318759
Short name T306
Test name
Test status
Simulation time 519026124 ps
CPU time 10.06 seconds
Started May 21 12:38:31 PM PDT 24
Finished May 21 12:38:53 PM PDT 24
Peak memory 211356 kb
Host smart-acf839cb-08b6-42f6-b8d3-c52978547e9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443318759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2443318759
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3590945558
Short name T271
Test name
Test status
Simulation time 21665670798 ps
CPU time 262.97 seconds
Started May 21 12:38:22 PM PDT 24
Finished May 21 12:42:58 PM PDT 24
Peak memory 216780 kb
Host smart-a3d53984-d611-4470-b12d-8c0476f3eaa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590945558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3590945558
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1808252907
Short name T140
Test name
Test status
Simulation time 689633609 ps
CPU time 18.82 seconds
Started May 21 12:38:26 PM PDT 24
Finished May 21 12:38:57 PM PDT 24
Peak memory 214672 kb
Host smart-5873850c-fbe5-477b-8b84-a37d3a645f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808252907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1808252907
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3432597330
Short name T338
Test name
Test status
Simulation time 8215526081 ps
CPU time 22.01 seconds
Started May 21 12:38:31 PM PDT 24
Finished May 21 12:39:05 PM PDT 24
Peak memory 211516 kb
Host smart-cdd96990-5170-47bd-ba32-c49fc4fe343b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3432597330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3432597330
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2969542985
Short name T199
Test name
Test status
Simulation time 17211564374 ps
CPU time 52.68 seconds
Started May 21 12:38:24 PM PDT 24
Finished May 21 12:39:29 PM PDT 24
Peak memory 218292 kb
Host smart-20c730b8-8edb-4a58-85df-2b44d5aabd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969542985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2969542985
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1007504499
Short name T125
Test name
Test status
Simulation time 226621799 ps
CPU time 11.28 seconds
Started May 21 12:38:34 PM PDT 24
Finished May 21 12:38:56 PM PDT 24
Peak memory 213880 kb
Host smart-87e03927-7249-4157-b36c-4b5589c9a739
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007504499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1007504499
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3070352632
Short name T357
Test name
Test status
Simulation time 1829560202 ps
CPU time 12.89 seconds
Started May 21 12:39:05 PM PDT 24
Finished May 21 12:39:28 PM PDT 24
Peak memory 211336 kb
Host smart-57315e68-040d-4209-a455-ae88b653b10e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070352632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3070352632
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1418046632
Short name T335
Test name
Test status
Simulation time 232519690780 ps
CPU time 549.91 seconds
Started May 21 12:38:51 PM PDT 24
Finished May 21 12:48:14 PM PDT 24
Peak memory 239008 kb
Host smart-e2a8bfd6-387d-44e4-b6a5-d6d252fcdde6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418046632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1418046632
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1988199210
Short name T1
Test name
Test status
Simulation time 11043166358 ps
CPU time 49.77 seconds
Started May 21 12:38:48 PM PDT 24
Finished May 21 12:39:51 PM PDT 24
Peak memory 214076 kb
Host smart-aad22a46-9c03-410a-83c5-43ad692b3334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988199210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1988199210
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.759672680
Short name T249
Test name
Test status
Simulation time 6314896767 ps
CPU time 25.24 seconds
Started May 21 12:38:47 PM PDT 24
Finished May 21 12:39:26 PM PDT 24
Peak memory 211764 kb
Host smart-3d1054aa-97b9-4f87-89fe-e2cfcd43d61b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=759672680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.759672680
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1787406568
Short name T151
Test name
Test status
Simulation time 348629776 ps
CPU time 19.82 seconds
Started May 21 12:38:56 PM PDT 24
Finished May 21 12:39:27 PM PDT 24
Peak memory 214936 kb
Host smart-5502aa91-6a7b-4062-a01b-606fe54ded03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787406568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1787406568
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.4005393377
Short name T123
Test name
Test status
Simulation time 40693409121 ps
CPU time 85.88 seconds
Started May 21 12:38:52 PM PDT 24
Finished May 21 12:40:31 PM PDT 24
Peak memory 219360 kb
Host smart-62aeca08-5c3c-46b8-8504-131f07a15cd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005393377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.4005393377
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.906792896
Short name T240
Test name
Test status
Simulation time 22351138035 ps
CPU time 33.33 seconds
Started May 21 12:38:58 PM PDT 24
Finished May 21 12:39:42 PM PDT 24
Peak memory 212172 kb
Host smart-2f964ebb-be7d-4b7a-b1f9-117d136920c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906792896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.906792896
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2650906266
Short name T286
Test name
Test status
Simulation time 61479546941 ps
CPU time 284.8 seconds
Started May 21 12:38:46 PM PDT 24
Finished May 21 12:43:43 PM PDT 24
Peak memory 240028 kb
Host smart-0666239a-c8ff-468e-91b9-bccb2be7ba2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650906266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2650906266
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1479760462
Short name T3
Test name
Test status
Simulation time 8717795908 ps
CPU time 45.32 seconds
Started May 21 12:39:02 PM PDT 24
Finished May 21 12:39:57 PM PDT 24
Peak memory 213128 kb
Host smart-491ba967-76b9-4f6a-945d-220da98d3e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479760462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1479760462
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3270800384
Short name T235
Test name
Test status
Simulation time 5184324338 ps
CPU time 18.38 seconds
Started May 21 12:38:51 PM PDT 24
Finished May 21 12:39:22 PM PDT 24
Peak memory 212932 kb
Host smart-b5129957-61cc-4e8e-ac5f-b09dffa9b82f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3270800384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3270800384
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3534505039
Short name T154
Test name
Test status
Simulation time 3601981397 ps
CPU time 40.44 seconds
Started May 21 12:38:48 PM PDT 24
Finished May 21 12:39:41 PM PDT 24
Peak memory 215820 kb
Host smart-d8a8b55e-b9f4-41c4-9ecd-454de9983847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534505039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3534505039
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.4063580201
Short name T142
Test name
Test status
Simulation time 25919198013 ps
CPU time 223.11 seconds
Started May 21 12:38:49 PM PDT 24
Finished May 21 12:42:45 PM PDT 24
Peak memory 221960 kb
Host smart-3a74c7fd-dbce-4737-be85-a7c854713212
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063580201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.4063580201
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3415892231
Short name T222
Test name
Test status
Simulation time 172485925 ps
CPU time 8.24 seconds
Started May 21 12:38:48 PM PDT 24
Finished May 21 12:39:09 PM PDT 24
Peak memory 211376 kb
Host smart-29b085e3-6d8c-4bdc-af11-ec70183948c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415892231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3415892231
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3610843229
Short name T169
Test name
Test status
Simulation time 4187340182 ps
CPU time 241.55 seconds
Started May 21 12:39:03 PM PDT 24
Finished May 21 12:43:14 PM PDT 24
Peak memory 217808 kb
Host smart-9969902f-11b2-4b64-ab07-65fd133f3efb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610843229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3610843229
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2912863965
Short name T223
Test name
Test status
Simulation time 8348985338 ps
CPU time 65.02 seconds
Started May 21 12:39:16 PM PDT 24
Finished May 21 12:40:32 PM PDT 24
Peak memory 215204 kb
Host smart-887e7e5e-74a2-41d6-b180-ef0e4c12cc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912863965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2912863965
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3782059274
Short name T234
Test name
Test status
Simulation time 184559278 ps
CPU time 10.19 seconds
Started May 21 12:39:57 PM PDT 24
Finished May 21 12:40:16 PM PDT 24
Peak memory 210400 kb
Host smart-c9e82e28-b862-4059-919c-184397850279
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3782059274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3782059274
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.634157729
Short name T238
Test name
Test status
Simulation time 14114118745 ps
CPU time 58.83 seconds
Started May 21 12:39:57 PM PDT 24
Finished May 21 12:41:04 PM PDT 24
Peak memory 216252 kb
Host smart-692e3bde-b80a-4975-a982-dfea25cc8911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634157729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.634157729
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1916240979
Short name T74
Test name
Test status
Simulation time 6961503779 ps
CPU time 123.45 seconds
Started May 21 12:38:48 PM PDT 24
Finished May 21 12:41:05 PM PDT 24
Peak memory 222628 kb
Host smart-3b38d362-3339-490d-b4ad-73d419b1c20c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916240979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1916240979
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3166622516
Short name T316
Test name
Test status
Simulation time 4342132881 ps
CPU time 32.32 seconds
Started May 21 12:39:08 PM PDT 24
Finished May 21 12:39:50 PM PDT 24
Peak memory 211704 kb
Host smart-f08aac82-f718-4f35-8bc5-c42f942ee21f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166622516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3166622516
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2157143776
Short name T21
Test name
Test status
Simulation time 8446836186 ps
CPU time 172.14 seconds
Started May 21 12:38:59 PM PDT 24
Finished May 21 12:42:02 PM PDT 24
Peak memory 229764 kb
Host smart-b8d51a60-ef26-4e93-946b-09248ffdd969
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157143776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2157143776
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1366337916
Short name T133
Test name
Test status
Simulation time 3750160560 ps
CPU time 31.97 seconds
Started May 21 12:39:11 PM PDT 24
Finished May 21 12:39:53 PM PDT 24
Peak memory 215040 kb
Host smart-1ee03027-af54-4669-8477-f7c9ad4d3284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366337916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1366337916
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.106796176
Short name T321
Test name
Test status
Simulation time 4104998815 ps
CPU time 33.33 seconds
Started May 21 12:38:54 PM PDT 24
Finished May 21 12:39:40 PM PDT 24
Peak memory 212328 kb
Host smart-79a02f43-997a-4704-9c8d-efdad84bc2b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106796176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.106796176
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3889262520
Short name T161
Test name
Test status
Simulation time 8359626332 ps
CPU time 78.08 seconds
Started May 21 12:39:19 PM PDT 24
Finished May 21 12:40:47 PM PDT 24
Peak memory 215172 kb
Host smart-1073dd8c-19ac-4117-a129-c0caee8dbc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889262520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3889262520
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3124359619
Short name T53
Test name
Test status
Simulation time 18783956715 ps
CPU time 42.3 seconds
Started May 21 12:39:02 PM PDT 24
Finished May 21 12:39:54 PM PDT 24
Peak memory 214420 kb
Host smart-94993a26-9cf4-4360-85a7-dc70256a554e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124359619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3124359619
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2665275612
Short name T49
Test name
Test status
Simulation time 389480112868 ps
CPU time 3411.51 seconds
Started May 21 12:39:57 PM PDT 24
Finished May 21 01:36:57 PM PDT 24
Peak memory 247832 kb
Host smart-ba63b9da-99e0-4cf1-a191-cb683ef62c1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665275612 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2665275612
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1612695322
Short name T63
Test name
Test status
Simulation time 845004958 ps
CPU time 14.41 seconds
Started May 21 12:38:52 PM PDT 24
Finished May 21 12:39:18 PM PDT 24
Peak memory 211400 kb
Host smart-56b0a499-a052-46ed-9bb7-da10dfbffc7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612695322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1612695322
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3634950609
Short name T166
Test name
Test status
Simulation time 19897418178 ps
CPU time 347.37 seconds
Started May 21 12:38:53 PM PDT 24
Finished May 21 12:44:53 PM PDT 24
Peak memory 238056 kb
Host smart-86bbd362-ffa6-4748-9bd4-c6f850c1ddcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634950609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3634950609
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.593290859
Short name T351
Test name
Test status
Simulation time 10908041332 ps
CPU time 50.48 seconds
Started May 21 12:38:51 PM PDT 24
Finished May 21 12:39:54 PM PDT 24
Peak memory 215096 kb
Host smart-7c2062fc-9730-4a56-aa42-8d2c81805071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593290859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.593290859
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1048853325
Short name T310
Test name
Test status
Simulation time 11100843743 ps
CPU time 26.93 seconds
Started May 21 12:38:54 PM PDT 24
Finished May 21 12:39:33 PM PDT 24
Peak memory 212848 kb
Host smart-d62a6f7a-0838-49b7-84fa-89e8d6c03eab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1048853325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1048853325
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.139601337
Short name T159
Test name
Test status
Simulation time 5831848501 ps
CPU time 69.25 seconds
Started May 21 12:39:12 PM PDT 24
Finished May 21 12:40:32 PM PDT 24
Peak memory 217876 kb
Host smart-b9605d0a-ee50-4c83-a84b-188780585e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139601337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.139601337
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3933055547
Short name T307
Test name
Test status
Simulation time 86831512167 ps
CPU time 175.78 seconds
Started May 21 12:38:57 PM PDT 24
Finished May 21 12:42:04 PM PDT 24
Peak memory 219444 kb
Host smart-ad3f5abf-6538-435c-b1d8-6c4ff8ccbf7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933055547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3933055547
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2683819304
Short name T48
Test name
Test status
Simulation time 190084513960 ps
CPU time 1900.7 seconds
Started May 21 12:39:03 PM PDT 24
Finished May 21 01:10:53 PM PDT 24
Peak memory 252340 kb
Host smart-cabb75f9-5bcc-414a-ad42-cd24d486e1ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683819304 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2683819304
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.829089264
Short name T54
Test name
Test status
Simulation time 3864124918 ps
CPU time 30.93 seconds
Started May 21 12:38:55 PM PDT 24
Finished May 21 12:39:38 PM PDT 24
Peak memory 211884 kb
Host smart-9fd8aff2-c60f-437f-a8a5-d0324cadb3e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829089264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.829089264
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.434761515
Short name T277
Test name
Test status
Simulation time 68739161909 ps
CPU time 428.88 seconds
Started May 21 12:39:53 PM PDT 24
Finished May 21 12:47:12 PM PDT 24
Peak memory 218212 kb
Host smart-4d4bcb3b-a28a-457b-86ac-48da8b876067
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434761515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.434761515
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2041416322
Short name T340
Test name
Test status
Simulation time 6995535620 ps
CPU time 54.71 seconds
Started May 21 12:38:49 PM PDT 24
Finished May 21 12:39:56 PM PDT 24
Peak memory 215180 kb
Host smart-94884be5-559a-4680-b2bb-6dacd85a44ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041416322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2041416322
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.377309045
Short name T137
Test name
Test status
Simulation time 40963996759 ps
CPU time 27.45 seconds
Started May 21 12:39:16 PM PDT 24
Finished May 21 12:39:54 PM PDT 24
Peak memory 211828 kb
Host smart-1275f4df-9d42-475e-94fe-6b0cd6bec74e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=377309045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.377309045
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3203374419
Short name T279
Test name
Test status
Simulation time 10283378337 ps
CPU time 53.5 seconds
Started May 21 12:38:52 PM PDT 24
Finished May 21 12:39:58 PM PDT 24
Peak memory 217980 kb
Host smart-af779892-218a-4768-b1c6-f66ecb35e728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203374419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3203374419
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1275652689
Short name T150
Test name
Test status
Simulation time 2866521466 ps
CPU time 19.55 seconds
Started May 21 12:38:51 PM PDT 24
Finished May 21 12:39:23 PM PDT 24
Peak memory 217488 kb
Host smart-5f6d37e0-9644-4232-bf5f-fc71f54c153b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275652689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1275652689
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1422283219
Short name T168
Test name
Test status
Simulation time 3774247218 ps
CPU time 14.57 seconds
Started May 21 12:39:01 PM PDT 24
Finished May 21 12:39:26 PM PDT 24
Peak memory 211560 kb
Host smart-8a434ce1-42e7-4f32-b7dd-ca63e9abdfce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422283219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1422283219
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3713734919
Short name T20
Test name
Test status
Simulation time 6206328808 ps
CPU time 318.31 seconds
Started May 21 12:38:47 PM PDT 24
Finished May 21 12:44:18 PM PDT 24
Peak memory 239916 kb
Host smart-1dcdb7dd-1bc2-480b-a331-3a3c91617d60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713734919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3713734919
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.569003063
Short name T294
Test name
Test status
Simulation time 27179194857 ps
CPU time 56.4 seconds
Started May 21 12:39:57 PM PDT 24
Finished May 21 12:41:02 PM PDT 24
Peak memory 212292 kb
Host smart-c16ce235-0610-443a-b75b-4c67d4c9ae81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569003063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.569003063
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2968311378
Short name T217
Test name
Test status
Simulation time 935633573 ps
CPU time 16.25 seconds
Started May 21 12:38:52 PM PDT 24
Finished May 21 12:39:21 PM PDT 24
Peak memory 212452 kb
Host smart-2e0dea99-5312-46c2-b287-7123b3e83413
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2968311378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2968311378
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1379896647
Short name T220
Test name
Test status
Simulation time 15834398090 ps
CPU time 65.06 seconds
Started May 21 12:39:09 PM PDT 24
Finished May 21 12:40:24 PM PDT 24
Peak memory 217120 kb
Host smart-916e2b54-d03f-4dd3-8c95-80aabd301a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379896647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1379896647
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.313094406
Short name T124
Test name
Test status
Simulation time 17808730431 ps
CPU time 71.58 seconds
Started May 21 12:39:06 PM PDT 24
Finished May 21 12:40:27 PM PDT 24
Peak memory 219348 kb
Host smart-ac23bd89-e2f9-4a88-baf7-57e6c6389048
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313094406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.313094406
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.734337118
Short name T51
Test name
Test status
Simulation time 412149492355 ps
CPU time 3827.35 seconds
Started May 21 12:40:11 PM PDT 24
Finished May 21 01:44:02 PM PDT 24
Peak memory 250088 kb
Host smart-cbb6b87d-b3f1-4c76-8bf7-d1ad1f5f9dfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734337118 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.734337118
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1962067702
Short name T298
Test name
Test status
Simulation time 2467895005 ps
CPU time 22.83 seconds
Started May 21 12:39:18 PM PDT 24
Finished May 21 12:39:51 PM PDT 24
Peak memory 211548 kb
Host smart-00e60e03-1f59-40e6-82ca-b30e6a273bb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962067702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1962067702
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.702684980
Short name T236
Test name
Test status
Simulation time 87600695231 ps
CPU time 917.58 seconds
Started May 21 12:38:50 PM PDT 24
Finished May 21 12:54:21 PM PDT 24
Peak memory 237600 kb
Host smart-d5274679-ede4-4528-846c-7b11e7e851c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702684980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.702684980
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.210333044
Short name T7
Test name
Test status
Simulation time 25584304771 ps
CPU time 53.34 seconds
Started May 21 12:39:21 PM PDT 24
Finished May 21 12:40:25 PM PDT 24
Peak memory 215180 kb
Host smart-59552328-ae4f-4207-b92b-618b8b7a34ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210333044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.210333044
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.246415599
Short name T172
Test name
Test status
Simulation time 3636739859 ps
CPU time 20.92 seconds
Started May 21 12:38:55 PM PDT 24
Finished May 21 12:39:28 PM PDT 24
Peak memory 212460 kb
Host smart-8b1e3817-60db-4869-8bd6-c6fed00d92a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246415599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.246415599
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2251890165
Short name T201
Test name
Test status
Simulation time 4608639393 ps
CPU time 61.16 seconds
Started May 21 12:39:19 PM PDT 24
Finished May 21 12:40:30 PM PDT 24
Peak memory 217204 kb
Host smart-8b75be4e-07c5-4d19-8353-17033ba14bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251890165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2251890165
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2583030557
Short name T44
Test name
Test status
Simulation time 1061616159 ps
CPU time 34.05 seconds
Started May 21 12:38:49 PM PDT 24
Finished May 21 12:39:36 PM PDT 24
Peak memory 216676 kb
Host smart-cc137b38-9287-400d-ae88-250a4ae5754a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583030557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2583030557
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.4175365605
Short name T155
Test name
Test status
Simulation time 500899677 ps
CPU time 8.26 seconds
Started May 21 12:39:10 PM PDT 24
Finished May 21 12:39:27 PM PDT 24
Peak memory 211380 kb
Host smart-7437d779-320c-48ca-9ad2-8a8219c75e0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175365605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.4175365605
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2127313067
Short name T252
Test name
Test status
Simulation time 6648519985 ps
CPU time 203.4 seconds
Started May 21 12:39:23 PM PDT 24
Finished May 21 12:42:57 PM PDT 24
Peak memory 239028 kb
Host smart-fa64a6f7-6d6c-42cf-a058-df61d699e0e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127313067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2127313067
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2781151039
Short name T245
Test name
Test status
Simulation time 8837838777 ps
CPU time 47.57 seconds
Started May 21 12:39:17 PM PDT 24
Finished May 21 12:40:16 PM PDT 24
Peak memory 215092 kb
Host smart-a39b5d33-2c93-4ea8-a12c-6224807f1340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781151039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2781151039
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4234121877
Short name T179
Test name
Test status
Simulation time 13673630692 ps
CPU time 29.73 seconds
Started May 21 12:39:10 PM PDT 24
Finished May 21 12:39:49 PM PDT 24
Peak memory 211788 kb
Host smart-74dd41b2-f26b-4517-a7af-958064d60c99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4234121877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.4234121877
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3560906708
Short name T356
Test name
Test status
Simulation time 355583916 ps
CPU time 20.22 seconds
Started May 21 12:39:16 PM PDT 24
Finished May 21 12:39:48 PM PDT 24
Peak memory 216712 kb
Host smart-9bbffcd2-0e8a-4bb4-bb04-f23cc722f71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560906708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3560906708
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2898814683
Short name T163
Test name
Test status
Simulation time 7933710712 ps
CPU time 106.89 seconds
Started May 21 12:38:55 PM PDT 24
Finished May 21 12:40:54 PM PDT 24
Peak memory 221308 kb
Host smart-be4f3f2f-c89a-47b3-a0ba-effe7014c3e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898814683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2898814683
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2811758197
Short name T185
Test name
Test status
Simulation time 1374783897 ps
CPU time 10.58 seconds
Started May 21 12:39:24 PM PDT 24
Finished May 21 12:39:44 PM PDT 24
Peak memory 211424 kb
Host smart-17975a20-ef10-42b4-b43a-c8f857895fef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811758197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2811758197
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4619331
Short name T207
Test name
Test status
Simulation time 158335678544 ps
CPU time 361.3 seconds
Started May 21 12:39:11 PM PDT 24
Finished May 21 12:45:22 PM PDT 24
Peak memory 216760 kb
Host smart-a0204080-6c20-4090-a82c-b4a439f05e0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4619331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_s
ig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_cor
rupt_sig_fatal_chk.4619331
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1672117213
Short name T224
Test name
Test status
Simulation time 5188544839 ps
CPU time 50.67 seconds
Started May 21 12:39:08 PM PDT 24
Finished May 21 12:40:09 PM PDT 24
Peak memory 215140 kb
Host smart-a5585e29-6cde-4ce2-86eb-3382c012509f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672117213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1672117213
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.733698196
Short name T39
Test name
Test status
Simulation time 7250117486 ps
CPU time 21.02 seconds
Started May 21 12:38:58 PM PDT 24
Finished May 21 12:39:30 PM PDT 24
Peak memory 211700 kb
Host smart-b975c99f-a336-4d49-b8b7-96930177ddae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=733698196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.733698196
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3868924335
Short name T187
Test name
Test status
Simulation time 882805223 ps
CPU time 20.37 seconds
Started May 21 12:39:13 PM PDT 24
Finished May 21 12:39:44 PM PDT 24
Peak memory 216968 kb
Host smart-5335f917-4dd7-485f-9df4-0c8287c3b1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868924335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3868924335
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3165391164
Short name T213
Test name
Test status
Simulation time 44388237135 ps
CPU time 113.05 seconds
Started May 21 12:39:12 PM PDT 24
Finished May 21 12:41:16 PM PDT 24
Peak memory 219560 kb
Host smart-871e9a6d-5b1c-4c4e-91dd-510fd6a7c383
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165391164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3165391164
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3453714235
Short name T241
Test name
Test status
Simulation time 1313973002 ps
CPU time 13.49 seconds
Started May 21 12:38:43 PM PDT 24
Finished May 21 12:39:07 PM PDT 24
Peak memory 211424 kb
Host smart-2e1a8e18-0c79-4ada-ad0d-74d418f47682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453714235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3453714235
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3734820548
Short name T173
Test name
Test status
Simulation time 188517557897 ps
CPU time 683.19 seconds
Started May 21 12:38:45 PM PDT 24
Finished May 21 12:50:20 PM PDT 24
Peak memory 240788 kb
Host smart-5bacdee8-2c0a-4cb0-9f70-198ea142fe59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734820548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3734820548
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3575156833
Short name T264
Test name
Test status
Simulation time 4908380909 ps
CPU time 46.44 seconds
Started May 21 12:38:26 PM PDT 24
Finished May 21 12:39:25 PM PDT 24
Peak memory 215176 kb
Host smart-8e41edba-c77b-4552-be0f-fcf6ac67f227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575156833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3575156833
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3954239866
Short name T237
Test name
Test status
Simulation time 359388754 ps
CPU time 10.01 seconds
Started May 21 12:38:39 PM PDT 24
Finished May 21 12:38:58 PM PDT 24
Peak memory 212120 kb
Host smart-5de45599-346d-4db9-8dbe-59d7c5614f7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3954239866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3954239866
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2484700478
Short name T38
Test name
Test status
Simulation time 1121917031 ps
CPU time 121.69 seconds
Started May 21 12:38:22 PM PDT 24
Finished May 21 12:40:36 PM PDT 24
Peak memory 239600 kb
Host smart-0a3d129d-9e00-44b0-945a-a5c6aefed9f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484700478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2484700478
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3230303578
Short name T41
Test name
Test status
Simulation time 10303116371 ps
CPU time 34.19 seconds
Started May 21 12:38:30 PM PDT 24
Finished May 21 12:39:15 PM PDT 24
Peak memory 216592 kb
Host smart-df469874-b8fa-429a-b670-ef4820840613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230303578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3230303578
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.993746449
Short name T302
Test name
Test status
Simulation time 3592756680 ps
CPU time 31.34 seconds
Started May 21 12:38:25 PM PDT 24
Finished May 21 12:39:09 PM PDT 24
Peak memory 212448 kb
Host smart-88d943af-2fdc-4745-a388-4520e4e510d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993746449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.993746449
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1903480248
Short name T344
Test name
Test status
Simulation time 3256508964 ps
CPU time 26.73 seconds
Started May 21 12:39:08 PM PDT 24
Finished May 21 12:39:44 PM PDT 24
Peak memory 211996 kb
Host smart-9f7ffc9c-3e8c-4fdc-af71-365b004319c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903480248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1903480248
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3626216245
Short name T204
Test name
Test status
Simulation time 3135385658 ps
CPU time 222.85 seconds
Started May 21 12:39:03 PM PDT 24
Finished May 21 12:42:55 PM PDT 24
Peak memory 240368 kb
Host smart-ef2fa7a0-57b9-4938-a115-746ee3e5b73a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626216245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3626216245
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3571560632
Short name T141
Test name
Test status
Simulation time 1375541229 ps
CPU time 19.17 seconds
Started May 21 12:38:55 PM PDT 24
Finished May 21 12:39:27 PM PDT 24
Peak memory 214608 kb
Host smart-33b3fc18-9679-4df6-98a1-001984fa675e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571560632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3571560632
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.551940030
Short name T259
Test name
Test status
Simulation time 4503789265 ps
CPU time 22.57 seconds
Started May 21 12:39:00 PM PDT 24
Finished May 21 12:39:33 PM PDT 24
Peak memory 212512 kb
Host smart-df44b97d-beb7-45c7-8fa6-ee80d6ae8cdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=551940030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.551940030
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3653417300
Short name T268
Test name
Test status
Simulation time 5935276060 ps
CPU time 28.16 seconds
Started May 21 12:39:04 PM PDT 24
Finished May 21 12:39:42 PM PDT 24
Peak memory 217192 kb
Host smart-5348adf9-5465-4d36-a0ac-11a5c713ea1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653417300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3653417300
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3656146054
Short name T206
Test name
Test status
Simulation time 10404653810 ps
CPU time 96.8 seconds
Started May 21 12:39:18 PM PDT 24
Finished May 21 12:41:06 PM PDT 24
Peak memory 219464 kb
Host smart-e58b7df8-d2d4-4ef7-bcc5-8221ef784137
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656146054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3656146054
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3801879615
Short name T52
Test name
Test status
Simulation time 242579443435 ps
CPU time 3206.98 seconds
Started May 21 12:39:19 PM PDT 24
Finished May 21 01:32:57 PM PDT 24
Peak memory 233608 kb
Host smart-573a567e-0234-4992-9954-ec95fff21021
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801879615 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.3801879615
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.71720791
Short name T132
Test name
Test status
Simulation time 8225114175 ps
CPU time 21.03 seconds
Started May 21 12:39:06 PM PDT 24
Finished May 21 12:39:37 PM PDT 24
Peak memory 211500 kb
Host smart-3f5e1104-14ed-4e49-af4c-d3ed7640bf78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71720791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.71720791
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2782738277
Short name T301
Test name
Test status
Simulation time 80913586700 ps
CPU time 800.6 seconds
Started May 21 12:39:09 PM PDT 24
Finished May 21 12:52:40 PM PDT 24
Peak memory 237936 kb
Host smart-6ca2401d-030b-4f20-82f4-ac683eb8c286
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782738277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2782738277
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3699882602
Short name T218
Test name
Test status
Simulation time 9083557855 ps
CPU time 47.16 seconds
Started May 21 12:38:56 PM PDT 24
Finished May 21 12:39:55 PM PDT 24
Peak memory 215080 kb
Host smart-ce479454-9e4a-446a-b600-532688e3c404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699882602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3699882602
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3992524227
Short name T228
Test name
Test status
Simulation time 7877033146 ps
CPU time 21.79 seconds
Started May 21 12:39:12 PM PDT 24
Finished May 21 12:39:44 PM PDT 24
Peak memory 212832 kb
Host smart-2a7a628a-0cc8-4e2e-8350-ff02168c2676
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3992524227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3992524227
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3466134571
Short name T6
Test name
Test status
Simulation time 5513046823 ps
CPU time 52.1 seconds
Started May 21 12:39:16 PM PDT 24
Finished May 21 12:40:19 PM PDT 24
Peak memory 216156 kb
Host smart-f4420662-e92f-44bd-81e3-7baa43821422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466134571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3466134571
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3616452882
Short name T326
Test name
Test status
Simulation time 15722945021 ps
CPU time 36.56 seconds
Started May 21 12:39:06 PM PDT 24
Finished May 21 12:39:52 PM PDT 24
Peak memory 214168 kb
Host smart-917572f1-dd24-4c7c-8452-73a1fa7451ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616452882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3616452882
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2565757701
Short name T299
Test name
Test status
Simulation time 3088751146 ps
CPU time 13.39 seconds
Started May 21 12:38:58 PM PDT 24
Finished May 21 12:39:23 PM PDT 24
Peak memory 211436 kb
Host smart-ef7932bc-c685-4bbc-8a1c-42268910908e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565757701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2565757701
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2239274858
Short name T115
Test name
Test status
Simulation time 197234761659 ps
CPU time 442.69 seconds
Started May 21 12:39:15 PM PDT 24
Finished May 21 12:46:48 PM PDT 24
Peak memory 239956 kb
Host smart-937991e0-137d-4a6b-91a4-58ac4900232f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239274858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2239274858
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2890123219
Short name T216
Test name
Test status
Simulation time 5973978918 ps
CPU time 56.85 seconds
Started May 21 12:39:04 PM PDT 24
Finished May 21 12:40:10 PM PDT 24
Peak memory 215212 kb
Host smart-9319d328-6b66-408d-90b5-521d884bb8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890123219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2890123219
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2472875703
Short name T282
Test name
Test status
Simulation time 6763778760 ps
CPU time 19.53 seconds
Started May 21 12:39:03 PM PDT 24
Finished May 21 12:39:32 PM PDT 24
Peak memory 212820 kb
Host smart-7b14f940-2d6d-421c-8661-ba8ef5ea0388
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2472875703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2472875703
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.4263701206
Short name T247
Test name
Test status
Simulation time 4969489552 ps
CPU time 54.26 seconds
Started May 21 12:39:12 PM PDT 24
Finished May 21 12:40:17 PM PDT 24
Peak memory 215788 kb
Host smart-6f3a2ab9-4ebd-4e95-9942-700c412366ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263701206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.4263701206
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.954429374
Short name T362
Test name
Test status
Simulation time 3192175506 ps
CPU time 42.64 seconds
Started May 21 12:39:18 PM PDT 24
Finished May 21 12:40:12 PM PDT 24
Peak memory 217836 kb
Host smart-7ac6bf6b-f9a1-4ed9-b27b-b6d5d7f69da8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954429374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.954429374
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1679707218
Short name T171
Test name
Test status
Simulation time 3533074172 ps
CPU time 29.31 seconds
Started May 21 12:39:14 PM PDT 24
Finished May 21 12:39:54 PM PDT 24
Peak memory 211972 kb
Host smart-dcc5c7e7-deac-4ecf-a25c-13271bd931d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679707218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1679707218
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1156053305
Short name T287
Test name
Test status
Simulation time 5507607937 ps
CPU time 151.26 seconds
Started May 21 12:39:26 PM PDT 24
Finished May 21 12:42:06 PM PDT 24
Peak memory 237576 kb
Host smart-22c7a118-abc7-4587-8a12-1f2f0fff6423
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156053305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1156053305
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2970147308
Short name T262
Test name
Test status
Simulation time 4736839701 ps
CPU time 46.54 seconds
Started May 21 12:39:30 PM PDT 24
Finished May 21 12:40:25 PM PDT 24
Peak memory 215288 kb
Host smart-fb801fb9-ee76-4b72-b8ef-859fe5647e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970147308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2970147308
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1503877402
Short name T358
Test name
Test status
Simulation time 227426563 ps
CPU time 10.27 seconds
Started May 21 12:39:08 PM PDT 24
Finished May 21 12:39:28 PM PDT 24
Peak memory 212176 kb
Host smart-64db401c-2e02-4f34-ab2c-9f422cb83216
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1503877402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1503877402
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3098689977
Short name T314
Test name
Test status
Simulation time 4474162354 ps
CPU time 44.9 seconds
Started May 21 12:39:16 PM PDT 24
Finished May 21 12:40:12 PM PDT 24
Peak memory 218172 kb
Host smart-a0aebb5d-06c0-443b-8a18-58a42cab6f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098689977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3098689977
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3772978744
Short name T114
Test name
Test status
Simulation time 32104235253 ps
CPU time 60.94 seconds
Started May 21 12:38:54 PM PDT 24
Finished May 21 12:40:08 PM PDT 24
Peak memory 218932 kb
Host smart-c77f683a-40b2-48a2-8ccf-faffd631e98f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772978744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3772978744
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1799793955
Short name T146
Test name
Test status
Simulation time 8546937247 ps
CPU time 32.68 seconds
Started May 21 12:39:11 PM PDT 24
Finished May 21 12:39:54 PM PDT 24
Peak memory 211508 kb
Host smart-f8e4e7b3-c63d-4dc0-b34d-2dca51684794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799793955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1799793955
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1353293290
Short name T265
Test name
Test status
Simulation time 32986956271 ps
CPU time 194.99 seconds
Started May 21 12:39:15 PM PDT 24
Finished May 21 12:42:41 PM PDT 24
Peak memory 237936 kb
Host smart-3f1c9ecc-90c4-4fe9-9569-9e52aa0a46fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353293290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1353293290
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3313866687
Short name T267
Test name
Test status
Simulation time 3859204492 ps
CPU time 33.65 seconds
Started May 21 12:39:07 PM PDT 24
Finished May 21 12:39:50 PM PDT 24
Peak memory 214916 kb
Host smart-2a8caca3-bc2b-490d-9ff1-c7d9fff06a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313866687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3313866687
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2970737041
Short name T175
Test name
Test status
Simulation time 6627458661 ps
CPU time 26.61 seconds
Started May 21 12:39:15 PM PDT 24
Finished May 21 12:39:52 PM PDT 24
Peak memory 212780 kb
Host smart-1f7c6577-de52-44d2-9717-d662a1cc456f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2970737041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2970737041
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.632185555
Short name T257
Test name
Test status
Simulation time 13586799800 ps
CPU time 79.39 seconds
Started May 21 12:39:15 PM PDT 24
Finished May 21 12:40:45 PM PDT 24
Peak memory 217264 kb
Host smart-20bb50c1-4554-4b1d-a011-dfb29b6037b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632185555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.632185555
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3355985518
Short name T153
Test name
Test status
Simulation time 1413881072 ps
CPU time 46.01 seconds
Started May 21 12:39:12 PM PDT 24
Finished May 21 12:40:08 PM PDT 24
Peak memory 215496 kb
Host smart-f0780a66-76ba-4a87-ad50-437607f8d120
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355985518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3355985518
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.153810890
Short name T139
Test name
Test status
Simulation time 9919600411 ps
CPU time 21.89 seconds
Started May 21 12:39:11 PM PDT 24
Finished May 21 12:39:43 PM PDT 24
Peak memory 212276 kb
Host smart-ec8e8148-4056-496a-84b6-5485109394ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153810890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.153810890
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1900915515
Short name T244
Test name
Test status
Simulation time 15891700184 ps
CPU time 181.8 seconds
Started May 21 12:39:00 PM PDT 24
Finished May 21 12:42:13 PM PDT 24
Peak memory 224744 kb
Host smart-83f74eeb-fac4-464e-9d48-e5da8b11a120
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900915515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1900915515
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1085977524
Short name T211
Test name
Test status
Simulation time 23458886566 ps
CPU time 28.34 seconds
Started May 21 12:39:01 PM PDT 24
Finished May 21 12:39:39 PM PDT 24
Peak memory 211868 kb
Host smart-871f17fe-3471-4435-90f7-45f58afa8fa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1085977524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1085977524
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2904116272
Short name T121
Test name
Test status
Simulation time 21263842827 ps
CPU time 48.66 seconds
Started May 21 12:39:18 PM PDT 24
Finished May 21 12:40:17 PM PDT 24
Peak memory 216960 kb
Host smart-d1312d4f-9784-413f-b980-7fbee100be20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904116272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2904116272
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2317201635
Short name T194
Test name
Test status
Simulation time 15675877876 ps
CPU time 80.24 seconds
Started May 21 12:38:59 PM PDT 24
Finished May 21 12:40:31 PM PDT 24
Peak memory 220860 kb
Host smart-77ce8528-6d13-4c65-b59f-b53b94325544
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317201635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2317201635
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.367997341
Short name T353
Test name
Test status
Simulation time 169051430 ps
CPU time 8.23 seconds
Started May 21 12:39:17 PM PDT 24
Finished May 21 12:39:36 PM PDT 24
Peak memory 211324 kb
Host smart-7059a804-5fde-44c9-b5f0-958b17123131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367997341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.367997341
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3029782674
Short name T184
Test name
Test status
Simulation time 2679052726 ps
CPU time 207.82 seconds
Started May 21 12:39:05 PM PDT 24
Finished May 21 12:42:43 PM PDT 24
Peak memory 229064 kb
Host smart-1ade5121-47a3-4e88-8010-272030383b4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029782674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3029782674
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1022675715
Short name T131
Test name
Test status
Simulation time 4604722843 ps
CPU time 46.83 seconds
Started May 21 12:39:34 PM PDT 24
Finished May 21 12:40:30 PM PDT 24
Peak memory 215152 kb
Host smart-163c8838-ec22-40d4-9df2-a92976742156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022675715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1022675715
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.300494709
Short name T42
Test name
Test status
Simulation time 8223349232 ps
CPU time 34.36 seconds
Started May 21 12:39:00 PM PDT 24
Finished May 21 12:39:45 PM PDT 24
Peak memory 211828 kb
Host smart-6f8f6c71-ac39-44d4-9144-6df61aaaee2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=300494709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.300494709
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3442406332
Short name T320
Test name
Test status
Simulation time 1358663288 ps
CPU time 19.4 seconds
Started May 21 12:39:18 PM PDT 24
Finished May 21 12:39:48 PM PDT 24
Peak memory 215752 kb
Host smart-12617fe8-ff4c-4c32-910e-866eba2f360c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442406332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3442406332
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1941516614
Short name T352
Test name
Test status
Simulation time 12013392171 ps
CPU time 134.42 seconds
Started May 21 12:39:00 PM PDT 24
Finished May 21 12:41:25 PM PDT 24
Peak memory 219444 kb
Host smart-21f9674f-a3d5-43cb-b253-462bf2e9320e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941516614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1941516614
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1703744105
Short name T300
Test name
Test status
Simulation time 32761792729 ps
CPU time 1249.75 seconds
Started May 21 12:39:05 PM PDT 24
Finished May 21 01:00:04 PM PDT 24
Peak memory 232652 kb
Host smart-8ecdeefc-3a85-417e-9948-c58fa3f2bdf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703744105 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1703744105
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3259105142
Short name T35
Test name
Test status
Simulation time 5956933297 ps
CPU time 22.83 seconds
Started May 21 12:39:10 PM PDT 24
Finished May 21 12:39:43 PM PDT 24
Peak memory 211516 kb
Host smart-c78cfee1-6975-435f-90e4-6a679432a464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259105142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3259105142
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1613407232
Short name T312
Test name
Test status
Simulation time 19364147016 ps
CPU time 408.41 seconds
Started May 21 12:39:13 PM PDT 24
Finished May 21 12:46:12 PM PDT 24
Peak memory 217472 kb
Host smart-8c4fce4d-e3d5-49b9-aabe-4cbc82d5a8bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613407232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1613407232
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1515559182
Short name T210
Test name
Test status
Simulation time 18594838380 ps
CPU time 44.26 seconds
Started May 21 12:39:11 PM PDT 24
Finished May 21 12:40:04 PM PDT 24
Peak memory 215080 kb
Host smart-49a68b0b-d544-4a81-9734-9f163c58cb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515559182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1515559182
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1489274626
Short name T225
Test name
Test status
Simulation time 12630703488 ps
CPU time 28.95 seconds
Started May 21 12:39:20 PM PDT 24
Finished May 21 12:40:00 PM PDT 24
Peak memory 212532 kb
Host smart-1cd3aefb-ece3-4f1f-94cd-c58218c54a45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1489274626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1489274626
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2578026354
Short name T174
Test name
Test status
Simulation time 2639962100 ps
CPU time 40.6 seconds
Started May 21 12:39:14 PM PDT 24
Finished May 21 12:40:05 PM PDT 24
Peak memory 217656 kb
Host smart-6730819f-f668-4a70-9f39-2b5c58112896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578026354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2578026354
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1488431906
Short name T5
Test name
Test status
Simulation time 23127214615 ps
CPU time 103.15 seconds
Started May 21 12:39:10 PM PDT 24
Finished May 21 12:41:02 PM PDT 24
Peak memory 219364 kb
Host smart-bc1c7054-0e4b-4db3-8048-72aed9b017a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488431906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1488431906
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3330325135
Short name T205
Test name
Test status
Simulation time 1971038351 ps
CPU time 20.22 seconds
Started May 21 12:38:56 PM PDT 24
Finished May 21 12:39:28 PM PDT 24
Peak memory 211896 kb
Host smart-c1edb9c2-2596-4e2e-ad52-ec884aeddb32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330325135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3330325135
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3155622721
Short name T145
Test name
Test status
Simulation time 32156295778 ps
CPU time 448.89 seconds
Started May 21 12:39:19 PM PDT 24
Finished May 21 12:46:58 PM PDT 24
Peak memory 234276 kb
Host smart-42170c82-7956-4fad-b86f-97ef6c4de328
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155622721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3155622721
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2448773838
Short name T152
Test name
Test status
Simulation time 38387385384 ps
CPU time 62.26 seconds
Started May 21 12:39:13 PM PDT 24
Finished May 21 12:40:25 PM PDT 24
Peak memory 215204 kb
Host smart-a9935d06-bc59-451a-9211-0be9678d6a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448773838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2448773838
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1844848319
Short name T149
Test name
Test status
Simulation time 3995207080 ps
CPU time 32.11 seconds
Started May 21 12:39:12 PM PDT 24
Finished May 21 12:39:54 PM PDT 24
Peak memory 211276 kb
Host smart-c6dbb9d2-406e-4bf7-9991-550d0678931e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1844848319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1844848319
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2870339304
Short name T208
Test name
Test status
Simulation time 5964241122 ps
CPU time 28.98 seconds
Started May 21 12:39:15 PM PDT 24
Finished May 21 12:39:54 PM PDT 24
Peak memory 218332 kb
Host smart-77e2bb3f-c247-4ef6-9565-17e06f4917ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870339304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2870339304
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2061682877
Short name T182
Test name
Test status
Simulation time 2486993570 ps
CPU time 25.49 seconds
Started May 21 12:39:11 PM PDT 24
Finished May 21 12:39:46 PM PDT 24
Peak memory 213588 kb
Host smart-b6ed367a-7806-4c9f-9579-32dd188955e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061682877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2061682877
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2103920707
Short name T50
Test name
Test status
Simulation time 208345605051 ps
CPU time 1960.11 seconds
Started May 21 12:39:34 PM PDT 24
Finished May 21 01:12:24 PM PDT 24
Peak memory 235968 kb
Host smart-9d377638-2735-4496-9c2f-44524191a566
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103920707 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2103920707
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1906444859
Short name T297
Test name
Test status
Simulation time 15020312274 ps
CPU time 28.71 seconds
Started May 21 12:39:11 PM PDT 24
Finished May 21 12:39:50 PM PDT 24
Peak memory 211940 kb
Host smart-f696914a-c5c2-4a15-9227-eb630a629c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906444859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1906444859
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2456580843
Short name T144
Test name
Test status
Simulation time 152487566096 ps
CPU time 248.43 seconds
Started May 21 12:39:16 PM PDT 24
Finished May 21 12:43:35 PM PDT 24
Peak memory 217684 kb
Host smart-7d21ecc7-dda7-4803-96b9-352fcdb96f11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456580843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2456580843
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3963441988
Short name T15
Test name
Test status
Simulation time 332481802 ps
CPU time 18.91 seconds
Started May 21 12:39:08 PM PDT 24
Finished May 21 12:39:36 PM PDT 24
Peak memory 214708 kb
Host smart-5dc4f6be-5d03-44b4-8c46-ab0cd89c02d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963441988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3963441988
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3911769031
Short name T119
Test name
Test status
Simulation time 1481295085 ps
CPU time 19.06 seconds
Started May 21 12:39:11 PM PDT 24
Finished May 21 12:39:40 PM PDT 24
Peak memory 211152 kb
Host smart-59a47d81-c8ed-4167-b9e1-c97afce82b08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3911769031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3911769031
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2470759360
Short name T305
Test name
Test status
Simulation time 5148448947 ps
CPU time 50.31 seconds
Started May 21 12:39:07 PM PDT 24
Finished May 21 12:40:06 PM PDT 24
Peak memory 217228 kb
Host smart-e0b7a89e-7dcc-43d2-884f-942ad1386417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470759360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2470759360
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.761177558
Short name T319
Test name
Test status
Simulation time 82518803797 ps
CPU time 3578.35 seconds
Started May 21 12:39:18 PM PDT 24
Finished May 21 01:39:07 PM PDT 24
Peak memory 260492 kb
Host smart-e1a72201-890e-40ef-8c61-4ff3a7943769
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761177558 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.761177558
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.490092278
Short name T127
Test name
Test status
Simulation time 2781919034 ps
CPU time 24.68 seconds
Started May 21 12:38:24 PM PDT 24
Finished May 21 12:39:01 PM PDT 24
Peak memory 211544 kb
Host smart-c8c85235-697d-4469-826e-62e4a58c8943
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490092278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.490092278
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3167689396
Short name T273
Test name
Test status
Simulation time 16934821592 ps
CPU time 52.35 seconds
Started May 21 12:38:45 PM PDT 24
Finished May 21 12:39:49 PM PDT 24
Peak memory 215080 kb
Host smart-b71e7018-95fc-48b3-8845-38468fb413af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167689396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3167689396
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1575952328
Short name T177
Test name
Test status
Simulation time 12050544918 ps
CPU time 24.17 seconds
Started May 21 12:38:46 PM PDT 24
Finished May 21 12:39:23 PM PDT 24
Peak memory 212864 kb
Host smart-fc5577d6-242d-4b52-91c5-c0ef037b7c48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1575952328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1575952328
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1230099048
Short name T274
Test name
Test status
Simulation time 17680708273 ps
CPU time 52.08 seconds
Started May 21 12:38:25 PM PDT 24
Finished May 21 12:39:30 PM PDT 24
Peak memory 216724 kb
Host smart-fbfa6d21-80cb-4503-9a77-c64c1bf44d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230099048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1230099048
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1096713601
Short name T43
Test name
Test status
Simulation time 18582233086 ps
CPU time 72.08 seconds
Started May 21 12:38:21 PM PDT 24
Finished May 21 12:39:46 PM PDT 24
Peak memory 221044 kb
Host smart-6c25ade0-c8d3-4883-8974-f93e91af2dca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096713601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1096713601
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3210875314
Short name T188
Test name
Test status
Simulation time 7986356074 ps
CPU time 32.11 seconds
Started May 21 12:38:21 PM PDT 24
Finished May 21 12:39:06 PM PDT 24
Peak memory 212280 kb
Host smart-1e7ce672-e506-4cb7-b7ea-36984e06fb8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210875314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3210875314
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3249063165
Short name T361
Test name
Test status
Simulation time 69125767435 ps
CPU time 745.77 seconds
Started May 21 12:38:44 PM PDT 24
Finished May 21 12:51:21 PM PDT 24
Peak memory 238228 kb
Host smart-8f927ea1-6ca0-4026-8572-024163a4f3dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249063165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3249063165
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1454873466
Short name T118
Test name
Test status
Simulation time 10959927748 ps
CPU time 50.05 seconds
Started May 21 12:38:30 PM PDT 24
Finished May 21 12:39:31 PM PDT 24
Peak memory 215208 kb
Host smart-f33c4086-4ca2-408c-8bbd-e150a0a2cd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454873466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1454873466
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.916601546
Short name T167
Test name
Test status
Simulation time 2563770095 ps
CPU time 25.44 seconds
Started May 21 12:38:23 PM PDT 24
Finished May 21 12:39:01 PM PDT 24
Peak memory 211292 kb
Host smart-17237950-916c-492e-a885-966a4edf3e68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=916601546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.916601546
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2651025455
Short name T170
Test name
Test status
Simulation time 1438181789 ps
CPU time 20.82 seconds
Started May 21 12:38:24 PM PDT 24
Finished May 21 12:38:57 PM PDT 24
Peak memory 216800 kb
Host smart-468c2849-0aba-411e-80f7-8242b31d2c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651025455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2651025455
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3409221617
Short name T327
Test name
Test status
Simulation time 10370562586 ps
CPU time 41.27 seconds
Started May 21 12:38:25 PM PDT 24
Finished May 21 12:39:19 PM PDT 24
Peak memory 218984 kb
Host smart-3e18eb4a-cd10-403e-9a9d-62f7628c3d8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409221617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3409221617
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.688947399
Short name T328
Test name
Test status
Simulation time 13581253981 ps
CPU time 27.62 seconds
Started May 21 12:38:27 PM PDT 24
Finished May 21 12:39:07 PM PDT 24
Peak memory 212384 kb
Host smart-b7e4105f-a962-4513-a2b2-51d7691c442d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688947399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.688947399
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2493706755
Short name T160
Test name
Test status
Simulation time 29440168069 ps
CPU time 450.73 seconds
Started May 21 12:38:59 PM PDT 24
Finished May 21 12:46:41 PM PDT 24
Peak memory 234916 kb
Host smart-e3a80053-d44d-456b-b01e-77979d05082e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493706755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2493706755
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.198330798
Short name T16
Test name
Test status
Simulation time 1322107607 ps
CPU time 19.58 seconds
Started May 21 12:38:48 PM PDT 24
Finished May 21 12:39:20 PM PDT 24
Peak memory 214828 kb
Host smart-01f4993e-f16d-4835-9a08-8fda31bda006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198330798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.198330798
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3270874210
Short name T2
Test name
Test status
Simulation time 15046925863 ps
CPU time 30.62 seconds
Started May 21 12:38:31 PM PDT 24
Finished May 21 12:39:13 PM PDT 24
Peak memory 212496 kb
Host smart-7a06a965-e7c8-48a2-8ab1-ea3b86cbe67e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3270874210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3270874210
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.4270567432
Short name T193
Test name
Test status
Simulation time 8749112392 ps
CPU time 47.95 seconds
Started May 21 12:38:25 PM PDT 24
Finished May 21 12:39:25 PM PDT 24
Peak memory 218428 kb
Host smart-a9240aee-95ca-4371-a329-c3449e51e25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270567432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.4270567432
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2424371467
Short name T11
Test name
Test status
Simulation time 32030061532 ps
CPU time 84.56 seconds
Started May 21 12:38:37 PM PDT 24
Finished May 21 12:40:12 PM PDT 24
Peak memory 219452 kb
Host smart-9aaa560c-5d67-4697-9bb5-7b68b8674b7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424371467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2424371467
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1596111277
Short name T157
Test name
Test status
Simulation time 167445956 ps
CPU time 8.25 seconds
Started May 21 12:38:54 PM PDT 24
Finished May 21 12:39:15 PM PDT 24
Peak memory 211388 kb
Host smart-a5623c7a-a3f8-45d2-b2b6-791381f39191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596111277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1596111277
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2408546874
Short name T250
Test name
Test status
Simulation time 14552537970 ps
CPU time 269.06 seconds
Started May 21 12:38:45 PM PDT 24
Finished May 21 12:43:26 PM PDT 24
Peak memory 228540 kb
Host smart-e8b20cad-f7d3-4f89-9f9d-d37cfc57fb32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408546874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2408546874
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3082894891
Short name T290
Test name
Test status
Simulation time 2060597174 ps
CPU time 22.03 seconds
Started May 21 12:38:31 PM PDT 24
Finished May 21 12:39:05 PM PDT 24
Peak memory 212668 kb
Host smart-5ee1faf8-a027-4dfd-857a-f39ffcba75dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082894891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3082894891
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1058623184
Short name T148
Test name
Test status
Simulation time 834751798 ps
CPU time 15.56 seconds
Started May 21 12:38:26 PM PDT 24
Finished May 21 12:38:54 PM PDT 24
Peak memory 212336 kb
Host smart-6e8fcfb2-ba40-4287-ad98-8009e783fe97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1058623184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1058623184
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.656428567
Short name T76
Test name
Test status
Simulation time 5748894457 ps
CPU time 58.45 seconds
Started May 21 12:38:40 PM PDT 24
Finished May 21 12:39:49 PM PDT 24
Peak memory 217680 kb
Host smart-a9654e50-2a5b-4f7f-ad9f-efc7bf670a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656428567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.656428567
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2688790893
Short name T333
Test name
Test status
Simulation time 84031403229 ps
CPU time 153.16 seconds
Started May 21 12:38:26 PM PDT 24
Finished May 21 12:41:12 PM PDT 24
Peak memory 219380 kb
Host smart-71c04691-9fa8-4e53-8142-e30f23d4450b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688790893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2688790893
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1056241767
Short name T313
Test name
Test status
Simulation time 516485236 ps
CPU time 8.48 seconds
Started May 21 12:38:27 PM PDT 24
Finished May 21 12:38:48 PM PDT 24
Peak memory 211388 kb
Host smart-b466a0c0-0ea0-48a1-8cc9-864dee0f5c33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056241767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1056241767
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3455357086
Short name T18
Test name
Test status
Simulation time 68243967695 ps
CPU time 453.06 seconds
Started May 21 12:38:47 PM PDT 24
Finished May 21 12:46:33 PM PDT 24
Peak memory 240952 kb
Host smart-8890f725-40a7-4c50-a93b-e93d6862da29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455357086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3455357086
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1592389904
Short name T135
Test name
Test status
Simulation time 675464414 ps
CPU time 19.34 seconds
Started May 21 12:38:39 PM PDT 24
Finished May 21 12:39:09 PM PDT 24
Peak memory 214796 kb
Host smart-1afff5f0-50e4-48d6-9e9b-6a0eb4114963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592389904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1592389904
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4170887821
Short name T350
Test name
Test status
Simulation time 13389017282 ps
CPU time 29.66 seconds
Started May 21 12:38:38 PM PDT 24
Finished May 21 12:39:18 PM PDT 24
Peak memory 211832 kb
Host smart-af0c0e15-f177-484f-8a56-0c39fad97a1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4170887821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4170887821
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1723319136
Short name T360
Test name
Test status
Simulation time 4518404194 ps
CPU time 58.67 seconds
Started May 21 12:38:34 PM PDT 24
Finished May 21 12:39:43 PM PDT 24
Peak memory 216536 kb
Host smart-73854832-5a9a-4c21-85d7-f94780f4f450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723319136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1723319136
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.833296292
Short name T77
Test name
Test status
Simulation time 679226786 ps
CPU time 30.89 seconds
Started May 21 12:39:00 PM PDT 24
Finished May 21 12:39:41 PM PDT 24
Peak memory 216276 kb
Host smart-d9d7f747-04cf-4cff-a015-01518d02e328
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833296292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.833296292
Directory /workspace/9.rom_ctrl_stress_all/latest
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