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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.59 96.97 93.15 97.88 100.00 98.69 98.03 98.37


Total test records in report: 455
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T303 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2355794132 May 23 01:37:28 PM PDT 24 May 23 01:37:57 PM PDT 24 3046727323 ps
T304 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.112035532 May 23 01:37:09 PM PDT 24 May 23 01:42:08 PM PDT 24 18061742923 ps
T305 /workspace/coverage/default/0.rom_ctrl_stress_all.3953506920 May 23 01:36:54 PM PDT 24 May 23 01:38:02 PM PDT 24 26141609301 ps
T306 /workspace/coverage/default/25.rom_ctrl_stress_all.551274186 May 23 01:37:32 PM PDT 24 May 23 01:39:03 PM PDT 24 76241009377 ps
T307 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.785956097 May 23 01:38:08 PM PDT 24 May 23 01:38:40 PM PDT 24 1661447997 ps
T308 /workspace/coverage/default/44.rom_ctrl_alert_test.3307328209 May 23 01:38:11 PM PDT 24 May 23 01:38:30 PM PDT 24 9425541075 ps
T309 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.252384002 May 23 01:37:39 PM PDT 24 May 23 01:38:41 PM PDT 24 6991753245 ps
T310 /workspace/coverage/default/42.rom_ctrl_stress_all.667109147 May 23 01:38:09 PM PDT 24 May 23 01:39:51 PM PDT 24 23972452220 ps
T21 /workspace/coverage/default/16.rom_ctrl_stress_all.802201200 May 23 01:37:17 PM PDT 24 May 23 01:37:54 PM PDT 24 4245460624 ps
T311 /workspace/coverage/default/38.rom_ctrl_smoke.3348813250 May 23 01:37:54 PM PDT 24 May 23 01:39:06 PM PDT 24 7791196319 ps
T312 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1590821219 May 23 01:37:19 PM PDT 24 May 23 01:37:45 PM PDT 24 3305715457 ps
T33 /workspace/coverage/default/1.rom_ctrl_sec_cm.936951327 May 23 01:36:53 PM PDT 24 May 23 01:39:00 PM PDT 24 1948092177 ps
T313 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4181603067 May 23 01:37:11 PM PDT 24 May 23 01:38:15 PM PDT 24 7621790744 ps
T314 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.821013476 May 23 01:37:54 PM PDT 24 May 23 01:39:46 PM PDT 24 3609210532 ps
T315 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3619230426 May 23 01:37:41 PM PDT 24 May 23 01:37:55 PM PDT 24 713506528 ps
T316 /workspace/coverage/default/10.rom_ctrl_alert_test.1192313657 May 23 01:37:08 PM PDT 24 May 23 01:37:28 PM PDT 24 5742966769 ps
T317 /workspace/coverage/default/5.rom_ctrl_alert_test.1248588691 May 23 01:37:04 PM PDT 24 May 23 01:37:16 PM PDT 24 174251685 ps
T318 /workspace/coverage/default/45.rom_ctrl_smoke.394359470 May 23 01:38:10 PM PDT 24 May 23 01:38:47 PM PDT 24 7636527722 ps
T319 /workspace/coverage/default/27.rom_ctrl_stress_all.1306446625 May 23 01:37:44 PM PDT 24 May 23 01:38:44 PM PDT 24 866753743 ps
T320 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2608634703 May 23 01:36:56 PM PDT 24 May 23 01:41:39 PM PDT 24 20587854946 ps
T321 /workspace/coverage/default/34.rom_ctrl_alert_test.3773840680 May 23 01:37:54 PM PDT 24 May 23 01:38:24 PM PDT 24 4760111797 ps
T322 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1246820460 May 23 01:37:53 PM PDT 24 May 23 01:39:10 PM PDT 24 8668303660 ps
T323 /workspace/coverage/default/42.rom_ctrl_alert_test.3863006500 May 23 01:38:10 PM PDT 24 May 23 01:38:35 PM PDT 24 2446311850 ps
T324 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1738841353 May 23 01:37:03 PM PDT 24 May 23 01:41:55 PM PDT 24 34502164822 ps
T325 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3629822740 May 23 01:38:10 PM PDT 24 May 23 01:38:50 PM PDT 24 2782209093 ps
T326 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.77934676 May 23 01:37:17 PM PDT 24 May 23 01:41:57 PM PDT 24 4192850819 ps
T327 /workspace/coverage/default/27.rom_ctrl_smoke.3716211626 May 23 01:37:30 PM PDT 24 May 23 01:38:27 PM PDT 24 13598131659 ps
T328 /workspace/coverage/default/1.rom_ctrl_smoke.1882779932 May 23 01:36:53 PM PDT 24 May 23 01:38:03 PM PDT 24 30879823619 ps
T329 /workspace/coverage/default/36.rom_ctrl_stress_all.2293542025 May 23 01:37:55 PM PDT 24 May 23 01:38:13 PM PDT 24 823597079 ps
T330 /workspace/coverage/default/7.rom_ctrl_stress_all.3470839823 May 23 01:37:03 PM PDT 24 May 23 01:37:37 PM PDT 24 2760335003 ps
T331 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1964854771 May 23 01:37:29 PM PDT 24 May 23 01:38:08 PM PDT 24 6767379407 ps
T332 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3120616778 May 23 01:37:56 PM PDT 24 May 23 01:38:22 PM PDT 24 1944601541 ps
T333 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.4050030798 May 23 01:36:55 PM PDT 24 May 23 01:38:06 PM PDT 24 8265099429 ps
T334 /workspace/coverage/default/26.rom_ctrl_stress_all.1222046561 May 23 01:37:30 PM PDT 24 May 23 01:38:36 PM PDT 24 70376047413 ps
T335 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4281678575 May 23 01:37:03 PM PDT 24 May 23 01:49:45 PM PDT 24 149777058938 ps
T336 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1902391612 May 23 01:38:14 PM PDT 24 May 23 01:42:30 PM PDT 24 20484269180 ps
T337 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1352120168 May 23 01:37:19 PM PDT 24 May 23 01:37:44 PM PDT 24 2058470382 ps
T338 /workspace/coverage/default/43.rom_ctrl_alert_test.1147556588 May 23 01:38:10 PM PDT 24 May 23 01:38:20 PM PDT 24 660481218 ps
T339 /workspace/coverage/default/43.rom_ctrl_stress_all.1886256513 May 23 01:38:09 PM PDT 24 May 23 01:38:53 PM PDT 24 2097958685 ps
T340 /workspace/coverage/default/17.rom_ctrl_stress_all.1019411668 May 23 01:37:19 PM PDT 24 May 23 01:38:20 PM PDT 24 11616133505 ps
T341 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1438561653 May 23 01:38:26 PM PDT 24 May 23 01:39:12 PM PDT 24 3911950260 ps
T342 /workspace/coverage/default/32.rom_ctrl_stress_all.3648243463 May 23 01:37:53 PM PDT 24 May 23 01:39:42 PM PDT 24 23131454135 ps
T343 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3967301805 May 23 01:37:05 PM PDT 24 May 23 01:37:35 PM PDT 24 11014671684 ps
T344 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2280512703 May 23 01:37:16 PM PDT 24 May 23 01:37:53 PM PDT 24 16986004709 ps
T345 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.302734248 May 23 01:38:11 PM PDT 24 May 23 01:38:33 PM PDT 24 1842289077 ps
T346 /workspace/coverage/default/39.rom_ctrl_alert_test.3536130972 May 23 01:38:08 PM PDT 24 May 23 01:38:30 PM PDT 24 9792989628 ps
T347 /workspace/coverage/default/46.rom_ctrl_smoke.3879494267 May 23 01:38:10 PM PDT 24 May 23 01:39:08 PM PDT 24 13447096256 ps
T348 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3579984016 May 23 01:37:04 PM PDT 24 May 23 01:37:31 PM PDT 24 2362670261 ps
T349 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1475067592 May 23 01:37:41 PM PDT 24 May 23 01:38:05 PM PDT 24 332604905 ps
T350 /workspace/coverage/default/18.rom_ctrl_smoke.2821432472 May 23 01:37:20 PM PDT 24 May 23 01:38:10 PM PDT 24 8547618252 ps
T351 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2435626607 May 23 01:37:08 PM PDT 24 May 23 01:38:03 PM PDT 24 6161640061 ps
T352 /workspace/coverage/default/2.rom_ctrl_alert_test.1191395537 May 23 01:37:04 PM PDT 24 May 23 01:37:23 PM PDT 24 1024591386 ps
T353 /workspace/coverage/default/30.rom_ctrl_stress_all.1158509518 May 23 01:37:40 PM PDT 24 May 23 01:38:52 PM PDT 24 7852153079 ps
T354 /workspace/coverage/default/17.rom_ctrl_smoke.3199075510 May 23 01:37:17 PM PDT 24 May 23 01:38:31 PM PDT 24 7033853358 ps
T22 /workspace/coverage/default/28.rom_ctrl_smoke.2574401656 May 23 01:37:29 PM PDT 24 May 23 01:38:46 PM PDT 24 21475169694 ps
T355 /workspace/coverage/default/19.rom_ctrl_smoke.2043855658 May 23 01:37:19 PM PDT 24 May 23 01:37:43 PM PDT 24 1436701160 ps
T356 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1894461208 May 23 01:38:10 PM PDT 24 May 23 01:38:37 PM PDT 24 3580607600 ps
T357 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1076949997 May 23 01:37:30 PM PDT 24 May 23 01:48:56 PM PDT 24 383044387654 ps
T358 /workspace/coverage/default/44.rom_ctrl_stress_all.1894230654 May 23 01:38:11 PM PDT 24 May 23 01:40:34 PM PDT 24 15642500133 ps
T359 /workspace/coverage/default/43.rom_ctrl_smoke.921193696 May 23 01:38:08 PM PDT 24 May 23 01:38:36 PM PDT 24 1710689963 ps
T50 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1986148185 May 23 01:36:53 PM PDT 24 May 23 01:37:28 PM PDT 24 8598989346 ps
T55 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1824944963 May 23 01:36:29 PM PDT 24 May 23 01:37:03 PM PDT 24 19104594872 ps
T51 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1400482585 May 23 01:36:31 PM PDT 24 May 23 01:39:25 PM PDT 24 5880674696 ps
T102 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1017248347 May 23 01:36:43 PM PDT 24 May 23 01:37:11 PM PDT 24 2369074876 ps
T52 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1960067740 May 23 01:36:47 PM PDT 24 May 23 01:37:20 PM PDT 24 4838445817 ps
T68 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.333037987 May 23 01:36:40 PM PDT 24 May 23 01:36:59 PM PDT 24 3286634063 ps
T69 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1809353364 May 23 01:36:59 PM PDT 24 May 23 01:37:09 PM PDT 24 332075469 ps
T53 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2967840952 May 23 01:36:46 PM PDT 24 May 23 01:38:09 PM PDT 24 247798724 ps
T96 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2907894034 May 23 01:36:51 PM PDT 24 May 23 01:37:03 PM PDT 24 167511798 ps
T54 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3754239513 May 23 01:36:43 PM PDT 24 May 23 01:39:43 PM PDT 24 56561466864 ps
T70 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4199714090 May 23 01:36:44 PM PDT 24 May 23 01:37:17 PM PDT 24 13432072424 ps
T60 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2335993266 May 23 01:36:56 PM PDT 24 May 23 01:37:10 PM PDT 24 339202060 ps
T62 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1523756142 May 23 01:36:59 PM PDT 24 May 23 01:38:41 PM PDT 24 9272810334 ps
T112 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1732401581 May 23 01:36:29 PM PDT 24 May 23 01:39:14 PM PDT 24 1432155586 ps
T97 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3064428376 May 23 01:36:58 PM PDT 24 May 23 01:37:30 PM PDT 24 3770873152 ps
T71 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3315301956 May 23 01:36:48 PM PDT 24 May 23 01:37:18 PM PDT 24 3030865761 ps
T105 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.838305617 May 23 01:36:55 PM PDT 24 May 23 01:38:33 PM PDT 24 10697213140 ps
T61 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2226586284 May 23 01:36:53 PM PDT 24 May 23 01:37:08 PM PDT 24 368651663 ps
T360 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2868152249 May 23 01:36:56 PM PDT 24 May 23 01:37:19 PM PDT 24 13550385825 ps
T361 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1808184198 May 23 01:36:46 PM PDT 24 May 23 01:37:03 PM PDT 24 2794514938 ps
T113 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2257247503 May 23 01:36:44 PM PDT 24 May 23 01:38:31 PM PDT 24 4495131810 ps
T362 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4105397941 May 23 01:36:43 PM PDT 24 May 23 01:37:22 PM PDT 24 3930915740 ps
T98 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3653042388 May 23 01:36:43 PM PDT 24 May 23 01:37:17 PM PDT 24 8571246593 ps
T363 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2940355543 May 23 01:36:58 PM PDT 24 May 23 01:37:33 PM PDT 24 4215252657 ps
T99 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.954692596 May 23 01:36:39 PM PDT 24 May 23 01:37:07 PM PDT 24 17913763872 ps
T109 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3964209872 May 23 01:36:45 PM PDT 24 May 23 01:38:26 PM PDT 24 2800694636 ps
T100 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1148922742 May 23 01:36:45 PM PDT 24 May 23 01:36:58 PM PDT 24 332446830 ps
T364 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2203986981 May 23 01:36:28 PM PDT 24 May 23 01:36:56 PM PDT 24 1625168731 ps
T365 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2013119303 May 23 01:36:44 PM PDT 24 May 23 01:37:06 PM PDT 24 941034108 ps
T366 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1986068071 May 23 01:36:41 PM PDT 24 May 23 01:37:20 PM PDT 24 18017987705 ps
T72 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3098412569 May 23 01:36:39 PM PDT 24 May 23 01:39:07 PM PDT 24 31477380686 ps
T114 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.886657798 May 23 01:36:42 PM PDT 24 May 23 01:38:29 PM PDT 24 16571853513 ps
T103 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1592195726 May 23 01:36:42 PM PDT 24 May 23 01:39:03 PM PDT 24 13997248886 ps
T367 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2003293568 May 23 01:36:45 PM PDT 24 May 23 01:37:23 PM PDT 24 3461047773 ps
T101 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4128528515 May 23 01:36:42 PM PDT 24 May 23 01:37:16 PM PDT 24 7477267432 ps
T368 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3725466886 May 23 01:36:41 PM PDT 24 May 23 01:37:08 PM PDT 24 2507124231 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3681710413 May 23 01:36:30 PM PDT 24 May 23 01:36:48 PM PDT 24 4147013044 ps
T370 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.878958412 May 23 01:36:41 PM PDT 24 May 23 01:37:03 PM PDT 24 1889188557 ps
T73 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1401045823 May 23 01:36:44 PM PDT 24 May 23 01:37:02 PM PDT 24 822394715 ps
T371 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2075678778 May 23 01:36:45 PM PDT 24 May 23 01:37:00 PM PDT 24 1434334983 ps
T372 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2134924344 May 23 01:36:40 PM PDT 24 May 23 01:36:51 PM PDT 24 194224185 ps
T74 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4285828993 May 23 01:36:43 PM PDT 24 May 23 01:40:04 PM PDT 24 25579345951 ps
T373 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3319193656 May 23 01:36:45 PM PDT 24 May 23 01:37:02 PM PDT 24 3072699451 ps
T374 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3567726809 May 23 01:36:47 PM PDT 24 May 23 01:37:07 PM PDT 24 3730274977 ps
T75 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3848194063 May 23 01:36:44 PM PDT 24 May 23 01:36:57 PM PDT 24 688611188 ps
T375 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2914920228 May 23 01:36:53 PM PDT 24 May 23 01:38:35 PM PDT 24 10460694086 ps
T376 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2781395648 May 23 01:36:45 PM PDT 24 May 23 01:37:08 PM PDT 24 26065864981 ps
T377 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.5761392 May 23 01:36:41 PM PDT 24 May 23 01:37:09 PM PDT 24 2995622002 ps
T378 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3427834491 May 23 01:36:32 PM PDT 24 May 23 01:37:00 PM PDT 24 6863042446 ps
T104 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1160541981 May 23 01:36:59 PM PDT 24 May 23 01:40:20 PM PDT 24 24208869443 ps
T107 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3818695575 May 23 01:36:56 PM PDT 24 May 23 01:39:41 PM PDT 24 12810834640 ps
T379 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1261121434 May 23 01:36:43 PM PDT 24 May 23 01:37:12 PM PDT 24 12252382871 ps
T380 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3094826724 May 23 01:36:29 PM PDT 24 May 23 01:36:43 PM PDT 24 411756183 ps
T381 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4068656491 May 23 01:36:30 PM PDT 24 May 23 01:36:42 PM PDT 24 500865675 ps
T382 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2772030355 May 23 01:36:43 PM PDT 24 May 23 01:37:18 PM PDT 24 4299678112 ps
T108 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.989608393 May 23 01:36:44 PM PDT 24 May 23 01:38:26 PM PDT 24 32586674302 ps
T383 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.39523761 May 23 01:36:46 PM PDT 24 May 23 01:37:22 PM PDT 24 37662731693 ps
T384 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3271425291 May 23 01:36:43 PM PDT 24 May 23 01:36:58 PM PDT 24 478831628 ps
T76 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.220445420 May 23 01:36:52 PM PDT 24 May 23 01:37:14 PM PDT 24 1645403548 ps
T385 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4105339293 May 23 01:36:47 PM PDT 24 May 23 01:37:25 PM PDT 24 4190625684 ps
T386 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.392463588 May 23 01:36:29 PM PDT 24 May 23 01:36:54 PM PDT 24 3353918294 ps
T387 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.410958536 May 23 01:36:56 PM PDT 24 May 23 01:37:21 PM PDT 24 6744327078 ps
T388 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3391616039 May 23 01:36:41 PM PDT 24 May 23 01:37:09 PM PDT 24 10643575063 ps
T115 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.422744442 May 23 01:36:40 PM PDT 24 May 23 01:39:21 PM PDT 24 4767018014 ps
T389 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.404532795 May 23 01:36:30 PM PDT 24 May 23 01:36:41 PM PDT 24 319701932 ps
T390 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.644376186 May 23 01:36:51 PM PDT 24 May 23 01:37:03 PM PDT 24 733766926 ps
T391 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3070277628 May 23 01:36:57 PM PDT 24 May 23 01:37:07 PM PDT 24 1373633209 ps
T77 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.852286766 May 23 01:36:53 PM PDT 24 May 23 01:40:17 PM PDT 24 25147431642 ps
T392 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4038817056 May 23 01:36:53 PM PDT 24 May 23 01:37:29 PM PDT 24 5373832757 ps
T393 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2931314014 May 23 01:36:29 PM PDT 24 May 23 01:36:41 PM PDT 24 174387343 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3653559180 May 23 01:36:39 PM PDT 24 May 23 01:36:50 PM PDT 24 332600063 ps
T395 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1381468441 May 23 01:36:43 PM PDT 24 May 23 01:37:00 PM PDT 24 2761208592 ps
T396 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3243268445 May 23 01:36:41 PM PDT 24 May 23 01:37:24 PM PDT 24 7489643101 ps
T397 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1321931568 May 23 01:36:44 PM PDT 24 May 23 01:36:59 PM PDT 24 496196131 ps
T82 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.444694416 May 23 01:36:42 PM PDT 24 May 23 01:38:19 PM PDT 24 55999659814 ps
T398 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1715981880 May 23 01:36:43 PM PDT 24 May 23 01:36:59 PM PDT 24 184571998 ps
T399 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1403413214 May 23 01:36:57 PM PDT 24 May 23 01:37:07 PM PDT 24 661778633 ps
T400 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3020801014 May 23 01:36:53 PM PDT 24 May 23 01:37:10 PM PDT 24 851446508 ps
T401 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.96815521 May 23 01:36:53 PM PDT 24 May 23 01:37:25 PM PDT 24 9851369053 ps
T402 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2773937554 May 23 01:36:40 PM PDT 24 May 23 01:37:02 PM PDT 24 10593361603 ps
T403 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2277014061 May 23 01:36:43 PM PDT 24 May 23 01:37:00 PM PDT 24 750499648 ps
T83 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4032024829 May 23 01:36:48 PM PDT 24 May 23 01:36:59 PM PDT 24 176374154 ps
T111 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1795669616 May 23 01:36:52 PM PDT 24 May 23 01:38:34 PM PDT 24 12054353589 ps
T404 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2470923282 May 23 01:36:42 PM PDT 24 May 23 01:37:16 PM PDT 24 15559211271 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2468880672 May 23 01:36:40 PM PDT 24 May 23 01:37:13 PM PDT 24 3322358425 ps
T110 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2250603586 May 23 01:36:58 PM PDT 24 May 23 01:39:32 PM PDT 24 613857227 ps
T406 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.463350546 May 23 01:36:43 PM PDT 24 May 23 01:37:01 PM PDT 24 3762361838 ps
T407 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3290051899 May 23 01:36:42 PM PDT 24 May 23 01:37:11 PM PDT 24 2828041054 ps
T88 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.619783547 May 23 01:36:54 PM PDT 24 May 23 01:37:10 PM PDT 24 1178157738 ps
T408 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2610830763 May 23 01:36:54 PM PDT 24 May 23 01:37:06 PM PDT 24 544740798 ps
T409 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.406612382 May 23 01:36:53 PM PDT 24 May 23 01:37:23 PM PDT 24 2461053038 ps
T87 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.521849215 May 23 01:36:29 PM PDT 24 May 23 01:39:54 PM PDT 24 144447489671 ps
T410 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.494866307 May 23 01:36:39 PM PDT 24 May 23 01:37:13 PM PDT 24 10515109984 ps
T411 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4131297814 May 23 01:36:53 PM PDT 24 May 23 01:37:18 PM PDT 24 2392487305 ps
T412 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3758733174 May 23 01:36:44 PM PDT 24 May 23 01:38:12 PM PDT 24 677894214 ps
T413 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3684063938 May 23 01:36:54 PM PDT 24 May 23 01:38:21 PM PDT 24 2341249277 ps
T414 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3362812658 May 23 01:36:44 PM PDT 24 May 23 01:36:57 PM PDT 24 960935326 ps
T84 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2196462086 May 23 01:36:40 PM PDT 24 May 23 01:37:03 PM PDT 24 2354119751 ps
T415 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1824377922 May 23 01:36:40 PM PDT 24 May 23 01:36:56 PM PDT 24 517972310 ps
T416 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1965402482 May 23 01:36:58 PM PDT 24 May 23 01:37:14 PM PDT 24 814765566 ps
T116 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2378529707 May 23 01:36:40 PM PDT 24 May 23 01:38:24 PM PDT 24 3893595780 ps
T417 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2585063459 May 23 01:36:56 PM PDT 24 May 23 01:39:51 PM PDT 24 73624322711 ps
T106 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.220220019 May 23 01:36:42 PM PDT 24 May 23 01:39:37 PM PDT 24 8404714053 ps
T418 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1719226783 May 23 01:36:53 PM PDT 24 May 23 01:37:30 PM PDT 24 3422467265 ps
T419 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3442038411 May 23 01:36:47 PM PDT 24 May 23 01:37:22 PM PDT 24 15107284162 ps
T89 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1514201377 May 23 01:36:29 PM PDT 24 May 23 01:39:12 PM PDT 24 71024454124 ps
T420 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4017625172 May 23 01:36:52 PM PDT 24 May 23 01:37:08 PM PDT 24 3597974673 ps
T421 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.64921720 May 23 01:36:54 PM PDT 24 May 23 01:37:28 PM PDT 24 4277907979 ps
T422 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2130152091 May 23 01:36:48 PM PDT 24 May 23 01:37:30 PM PDT 24 694285164 ps
T423 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.644607937 May 23 01:36:43 PM PDT 24 May 23 01:37:25 PM PDT 24 1442969467 ps
T424 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.946749087 May 23 01:36:45 PM PDT 24 May 23 01:37:01 PM PDT 24 516399483 ps
T425 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3355692744 May 23 01:36:52 PM PDT 24 May 23 01:38:12 PM PDT 24 27455961852 ps
T426 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2694727864 May 23 01:36:42 PM PDT 24 May 23 01:37:05 PM PDT 24 1217927161 ps
T427 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.607689563 May 23 01:36:47 PM PDT 24 May 23 01:39:10 PM PDT 24 92774820906 ps
T428 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3992040190 May 23 01:36:26 PM PDT 24 May 23 01:36:39 PM PDT 24 678057112 ps
T429 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3900789519 May 23 01:36:54 PM PDT 24 May 23 01:37:20 PM PDT 24 2416429920 ps
T430 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.151592777 May 23 01:36:45 PM PDT 24 May 23 01:37:08 PM PDT 24 3436666334 ps
T431 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2934982866 May 23 01:36:54 PM PDT 24 May 23 01:37:25 PM PDT 24 2909242103 ps
T432 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.135556408 May 23 01:36:41 PM PDT 24 May 23 01:37:03 PM PDT 24 3045977961 ps
T433 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3154260176 May 23 01:36:48 PM PDT 24 May 23 01:37:20 PM PDT 24 14361993663 ps
T434 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3513470958 May 23 01:36:27 PM PDT 24 May 23 01:36:57 PM PDT 24 2653343158 ps
T435 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1595469250 May 23 01:36:44 PM PDT 24 May 23 01:37:14 PM PDT 24 5244736524 ps
T436 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1074520278 May 23 01:36:53 PM PDT 24 May 23 01:37:05 PM PDT 24 332399365 ps
T437 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1126623736 May 23 01:36:54 PM PDT 24 May 23 01:39:30 PM PDT 24 19130640058 ps
T438 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3582625459 May 23 01:36:53 PM PDT 24 May 23 01:37:12 PM PDT 24 1201436777 ps
T90 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3395856620 May 23 01:36:44 PM PDT 24 May 23 01:37:03 PM PDT 24 1236819304 ps
T439 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.292108180 May 23 01:36:58 PM PDT 24 May 23 01:37:22 PM PDT 24 9570306839 ps
T440 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3841520615 May 23 01:36:43 PM PDT 24 May 23 01:38:05 PM PDT 24 28787111425 ps
T441 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3250908075 May 23 01:36:53 PM PDT 24 May 23 01:37:09 PM PDT 24 551986409 ps
T442 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2117978216 May 23 01:36:44 PM PDT 24 May 23 01:37:14 PM PDT 24 3098460478 ps
T85 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2810959257 May 23 01:36:42 PM PDT 24 May 23 01:38:46 PM PDT 24 104254488191 ps
T86 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2791369896 May 23 01:36:41 PM PDT 24 May 23 01:39:29 PM PDT 24 18970996224 ps
T443 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.347405560 May 23 01:36:29 PM PDT 24 May 23 01:36:47 PM PDT 24 993027669 ps
T444 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3865070752 May 23 01:36:43 PM PDT 24 May 23 01:40:14 PM PDT 24 86543553886 ps
T445 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4270030543 May 23 01:36:43 PM PDT 24 May 23 01:37:00 PM PDT 24 1671892351 ps
T446 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3999468626 May 23 01:36:52 PM PDT 24 May 23 01:37:11 PM PDT 24 613172664 ps
T447 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.821180755 May 23 01:36:40 PM PDT 24 May 23 01:37:16 PM PDT 24 16704634512 ps
T448 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2935771835 May 23 01:36:40 PM PDT 24 May 23 01:37:13 PM PDT 24 4083876344 ps
T449 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.272189296 May 23 01:36:48 PM PDT 24 May 23 01:37:23 PM PDT 24 18771850297 ps
T450 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.634214018 May 23 01:36:53 PM PDT 24 May 23 01:37:08 PM PDT 24 1835975850 ps
T451 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3405132486 May 23 01:36:54 PM PDT 24 May 23 01:38:25 PM PDT 24 4031392299 ps
T452 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.870111485 May 23 01:36:52 PM PDT 24 May 23 01:37:45 PM PDT 24 1746636812 ps
T453 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4267367108 May 23 01:36:40 PM PDT 24 May 23 01:37:09 PM PDT 24 3136497580 ps
T454 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3551967367 May 23 01:36:58 PM PDT 24 May 23 01:37:37 PM PDT 24 783838276 ps
T455 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3392265936 May 23 01:36:41 PM PDT 24 May 23 01:36:53 PM PDT 24 2743826016 ps

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3357304431
Short name T3
Test name
Test status
Simulation time 55942525047 ps
CPU time 6381.22 seconds
Started May 23 01:37:54 PM PDT 24
Finished May 23 03:24:24 PM PDT 24
Peak memory 235956 kb
Host smart-4fc48873-896d-46fd-aec7-d42b675e6fe0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357304431 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.3357304431
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2519069219
Short name T27
Test name
Test status
Simulation time 103202657198 ps
CPU time 364.92 seconds
Started May 23 01:37:55 PM PDT 24
Finished May 23 01:44:07 PM PDT 24
Peak memory 240960 kb
Host smart-72e46b2b-fa37-4a96-b561-329325ca6e97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519069219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2519069219
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3604954591
Short name T20
Test name
Test status
Simulation time 27780180794 ps
CPU time 30.74 seconds
Started May 23 01:38:25 PM PDT 24
Finished May 23 01:38:56 PM PDT 24
Peak memory 212260 kb
Host smart-95367a4e-b5f3-4cb5-9731-9fc8c3a7cea8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604954591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3604954591
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3754239513
Short name T54
Test name
Test status
Simulation time 56561466864 ps
CPU time 176.65 seconds
Started May 23 01:36:43 PM PDT 24
Finished May 23 01:39:43 PM PDT 24
Peak memory 214284 kb
Host smart-dc3dd4a9-2c11-414c-bf80-0aafb432b57e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754239513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3754239513
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.4068914694
Short name T12
Test name
Test status
Simulation time 60316418457 ps
CPU time 763.28 seconds
Started May 23 01:38:08 PM PDT 24
Finished May 23 01:50:53 PM PDT 24
Peak memory 229692 kb
Host smart-b52c5b94-3d1c-4d1e-ab26-a1d8484a8ef5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068914694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.4068914694
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1040653138
Short name T29
Test name
Test status
Simulation time 8734836269 ps
CPU time 237.83 seconds
Started May 23 01:37:06 PM PDT 24
Finished May 23 01:41:08 PM PDT 24
Peak memory 236868 kb
Host smart-e54a62be-6d63-4999-96fd-3abe151825e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040653138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1040653138
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3098412569
Short name T72
Test name
Test status
Simulation time 31477380686 ps
CPU time 146.1 seconds
Started May 23 01:36:39 PM PDT 24
Finished May 23 01:39:07 PM PDT 24
Peak memory 215532 kb
Host smart-4128b866-9c7a-4319-ae7a-c4b856943cdb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098412569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3098412569
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.220220019
Short name T106
Test name
Test status
Simulation time 8404714053 ps
CPU time 170.85 seconds
Started May 23 01:36:42 PM PDT 24
Finished May 23 01:39:37 PM PDT 24
Peak memory 215188 kb
Host smart-2965aba9-f838-49bd-bc6c-d9166a4e07f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220220019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.220220019
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.848037600
Short name T41
Test name
Test status
Simulation time 3930200468 ps
CPU time 56.48 seconds
Started May 23 01:37:03 PM PDT 24
Finished May 23 01:38:03 PM PDT 24
Peak memory 217324 kb
Host smart-3d46047e-b914-4cb1-b0dd-f1379dd30e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848037600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.848037600
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4037403781
Short name T47
Test name
Test status
Simulation time 7096548574 ps
CPU time 30.77 seconds
Started May 23 01:37:29 PM PDT 24
Finished May 23 01:38:02 PM PDT 24
Peak memory 211348 kb
Host smart-8f657906-7c1b-4ccd-943d-49d373222aee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4037403781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4037403781
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2110797772
Short name T155
Test name
Test status
Simulation time 335555720 ps
CPU time 19.44 seconds
Started May 23 01:37:15 PM PDT 24
Finished May 23 01:37:37 PM PDT 24
Peak memory 214712 kb
Host smart-48a0f8c3-3937-48f8-ae5a-bb8d65377922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110797772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2110797772
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.919405596
Short name T182
Test name
Test status
Simulation time 13821510533 ps
CPU time 61.24 seconds
Started May 23 01:37:18 PM PDT 24
Finished May 23 01:38:23 PM PDT 24
Peak memory 214108 kb
Host smart-09f5c91d-026d-46fe-b8b8-2456629069f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919405596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.919405596
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3188856321
Short name T23
Test name
Test status
Simulation time 23659202578 ps
CPU time 55.12 seconds
Started May 23 01:37:03 PM PDT 24
Finished May 23 01:38:02 PM PDT 24
Peak memory 213980 kb
Host smart-4c7f7ad0-ae16-4565-b42d-f135678a2fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188856321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3188856321
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3818695575
Short name T107
Test name
Test status
Simulation time 12810834640 ps
CPU time 163.45 seconds
Started May 23 01:36:56 PM PDT 24
Finished May 23 01:39:41 PM PDT 24
Peak memory 214388 kb
Host smart-223e6350-dfaa-402b-bd78-054f7c368a33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818695575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3818695575
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.724331831
Short name T130
Test name
Test status
Simulation time 70963169323 ps
CPU time 358.56 seconds
Started May 23 01:37:18 PM PDT 24
Finished May 23 01:43:20 PM PDT 24
Peak memory 240712 kb
Host smart-e0c66e7d-4c5d-4b7b-a964-000eb389217e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724331831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.724331831
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1514201377
Short name T89
Test name
Test status
Simulation time 71024454124 ps
CPU time 160.56 seconds
Started May 23 01:36:29 PM PDT 24
Finished May 23 01:39:12 PM PDT 24
Peak memory 215436 kb
Host smart-314e0a24-3daa-49a4-b2da-693068d0983b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514201377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1514201377
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1824944963
Short name T55
Test name
Test status
Simulation time 19104594872 ps
CPU time 30.34 seconds
Started May 23 01:36:29 PM PDT 24
Finished May 23 01:37:03 PM PDT 24
Peak memory 212828 kb
Host smart-546b45f1-11fa-483c-8a61-831d618ab2b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824944963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1824944963
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3576771292
Short name T44
Test name
Test status
Simulation time 8134978491 ps
CPU time 15.22 seconds
Started May 23 01:37:01 PM PDT 24
Finished May 23 01:37:18 PM PDT 24
Peak memory 211440 kb
Host smart-a1cb183a-a5c8-4eb6-9fb5-ec40d12a9a74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576771292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3576771292
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4068656491
Short name T381
Test name
Test status
Simulation time 500865675 ps
CPU time 8.46 seconds
Started May 23 01:36:30 PM PDT 24
Finished May 23 01:36:42 PM PDT 24
Peak memory 211280 kb
Host smart-46aff12b-71e4-4ad4-bbaf-8032c9706eff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068656491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.4068656491
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.347405560
Short name T443
Test name
Test status
Simulation time 993027669 ps
CPU time 15.17 seconds
Started May 23 01:36:29 PM PDT 24
Finished May 23 01:36:47 PM PDT 24
Peak memory 211328 kb
Host smart-95e3f264-227f-4266-986f-38d486e0582c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347405560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.347405560
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2203986981
Short name T364
Test name
Test status
Simulation time 1625168731 ps
CPU time 25.35 seconds
Started May 23 01:36:28 PM PDT 24
Finished May 23 01:36:56 PM PDT 24
Peak memory 212056 kb
Host smart-0ee270b9-a8cb-4e06-a0da-418c9d37d6d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203986981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2203986981
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3681710413
Short name T369
Test name
Test status
Simulation time 4147013044 ps
CPU time 15.13 seconds
Started May 23 01:36:30 PM PDT 24
Finished May 23 01:36:48 PM PDT 24
Peak memory 216528 kb
Host smart-ef7af1c6-48e3-4d7d-819c-6e9d5bdbe299
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681710413 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3681710413
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3427834491
Short name T378
Test name
Test status
Simulation time 6863042446 ps
CPU time 26.38 seconds
Started May 23 01:36:32 PM PDT 24
Finished May 23 01:37:00 PM PDT 24
Peak memory 212348 kb
Host smart-b9da6e73-6dc8-48fb-aba8-58973cb71cad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427834491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3427834491
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3094826724
Short name T380
Test name
Test status
Simulation time 411756183 ps
CPU time 10.99 seconds
Started May 23 01:36:29 PM PDT 24
Finished May 23 01:36:43 PM PDT 24
Peak memory 211196 kb
Host smart-fed02eab-32c6-49b4-9652-8dd244325f68
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094826724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3094826724
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2931314014
Short name T393
Test name
Test status
Simulation time 174387343 ps
CPU time 8.24 seconds
Started May 23 01:36:29 PM PDT 24
Finished May 23 01:36:41 PM PDT 24
Peak memory 211228 kb
Host smart-e9933197-7ee2-44cf-b69f-cc3324e30f37
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931314014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2931314014
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.392463588
Short name T386
Test name
Test status
Simulation time 3353918294 ps
CPU time 21.79 seconds
Started May 23 01:36:29 PM PDT 24
Finished May 23 01:36:54 PM PDT 24
Peak memory 218616 kb
Host smart-80d4fdc7-2a9f-4773-a9c6-9e9850ac8064
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392463588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.392463588
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1732401581
Short name T112
Test name
Test status
Simulation time 1432155586 ps
CPU time 161.95 seconds
Started May 23 01:36:29 PM PDT 24
Finished May 23 01:39:14 PM PDT 24
Peak memory 214996 kb
Host smart-8478fde3-cce0-4f71-9321-3e5179d5b8a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732401581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1732401581
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3392265936
Short name T455
Test name
Test status
Simulation time 2743826016 ps
CPU time 8.5 seconds
Started May 23 01:36:41 PM PDT 24
Finished May 23 01:36:53 PM PDT 24
Peak memory 211264 kb
Host smart-83b7ea8b-32fa-4c02-9d5c-b6bbd5b0768d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392265936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3392265936
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3653559180
Short name T394
Test name
Test status
Simulation time 332600063 ps
CPU time 8.59 seconds
Started May 23 01:36:39 PM PDT 24
Finished May 23 01:36:50 PM PDT 24
Peak memory 211224 kb
Host smart-1ba31bac-1176-4951-a666-be543ea2a1e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653559180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3653559180
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3243268445
Short name T396
Test name
Test status
Simulation time 7489643101 ps
CPU time 38.03 seconds
Started May 23 01:36:41 PM PDT 24
Finished May 23 01:37:24 PM PDT 24
Peak memory 212360 kb
Host smart-56db824e-6876-4b08-8c38-7c5bbee64ba8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243268445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3243268445
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.494866307
Short name T410
Test name
Test status
Simulation time 10515109984 ps
CPU time 32.36 seconds
Started May 23 01:36:39 PM PDT 24
Finished May 23 01:37:13 PM PDT 24
Peak memory 218392 kb
Host smart-6bf6d1e1-331e-40b5-99e8-c921d210f34f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494866307 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.494866307
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2773937554
Short name T402
Test name
Test status
Simulation time 10593361603 ps
CPU time 18.69 seconds
Started May 23 01:36:40 PM PDT 24
Finished May 23 01:37:02 PM PDT 24
Peak memory 212348 kb
Host smart-229ce0e4-8fda-4df8-ba60-84125b91ff9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773937554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2773937554
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3992040190
Short name T428
Test name
Test status
Simulation time 678057112 ps
CPU time 12.23 seconds
Started May 23 01:36:26 PM PDT 24
Finished May 23 01:36:39 PM PDT 24
Peak memory 211124 kb
Host smart-10e46f98-8d48-4288-a646-df30c4b68567
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992040190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3992040190
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.404532795
Short name T389
Test name
Test status
Simulation time 319701932 ps
CPU time 8.4 seconds
Started May 23 01:36:30 PM PDT 24
Finished May 23 01:36:41 PM PDT 24
Peak memory 211180 kb
Host smart-1a6dd8f6-e8e2-4e8f-9f5f-5e4eb5f0aa0c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404532795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
404532795
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.521849215
Short name T87
Test name
Test status
Simulation time 144447489671 ps
CPU time 202.76 seconds
Started May 23 01:36:29 PM PDT 24
Finished May 23 01:39:54 PM PDT 24
Peak memory 215492 kb
Host smart-9b886c6b-024d-47a9-8d8c-e0380837ee20
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521849215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.521849215
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3319193656
Short name T373
Test name
Test status
Simulation time 3072699451 ps
CPU time 13.26 seconds
Started May 23 01:36:45 PM PDT 24
Finished May 23 01:37:02 PM PDT 24
Peak memory 211304 kb
Host smart-f468a0be-80e3-4919-8e2a-b17ffb770ce8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319193656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3319193656
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3513470958
Short name T434
Test name
Test status
Simulation time 2653343158 ps
CPU time 26.4 seconds
Started May 23 01:36:27 PM PDT 24
Finished May 23 01:36:57 PM PDT 24
Peak memory 219608 kb
Host smart-bcdfb4c4-806d-4fc3-994c-9dfe604ea7da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513470958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3513470958
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1400482585
Short name T51
Test name
Test status
Simulation time 5880674696 ps
CPU time 171.12 seconds
Started May 23 01:36:31 PM PDT 24
Finished May 23 01:39:25 PM PDT 24
Peak memory 215316 kb
Host smart-4a8efef0-c59e-4d03-a9fa-7cc1cf314fa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400482585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1400482585
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3290051899
Short name T407
Test name
Test status
Simulation time 2828041054 ps
CPU time 24.48 seconds
Started May 23 01:36:42 PM PDT 24
Finished May 23 01:37:11 PM PDT 24
Peak memory 217128 kb
Host smart-3b1955ca-1aa3-409b-837f-a100231a5613
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290051899 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3290051899
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3315301956
Short name T71
Test name
Test status
Simulation time 3030865761 ps
CPU time 26.1 seconds
Started May 23 01:36:48 PM PDT 24
Finished May 23 01:37:18 PM PDT 24
Peak memory 211840 kb
Host smart-0da81f32-fefe-46dd-85a9-962ed44112e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315301956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3315301956
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4285828993
Short name T74
Test name
Test status
Simulation time 25579345951 ps
CPU time 197.11 seconds
Started May 23 01:36:43 PM PDT 24
Finished May 23 01:40:04 PM PDT 24
Peak memory 215400 kb
Host smart-3db319e0-9af5-4e52-8859-2b87d273b82b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285828993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.4285828993
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1595469250
Short name T435
Test name
Test status
Simulation time 5244736524 ps
CPU time 25.23 seconds
Started May 23 01:36:44 PM PDT 24
Finished May 23 01:37:14 PM PDT 24
Peak memory 212812 kb
Host smart-ddb492ca-9c91-4ba9-bf83-3269044f5747
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595469250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1595469250
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.39523761
Short name T383
Test name
Test status
Simulation time 37662731693 ps
CPU time 32.05 seconds
Started May 23 01:36:46 PM PDT 24
Finished May 23 01:37:22 PM PDT 24
Peak memory 219644 kb
Host smart-6b0eec70-8b45-49d0-960c-512fff2632b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39523761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.39523761
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2257247503
Short name T113
Test name
Test status
Simulation time 4495131810 ps
CPU time 102.37 seconds
Started May 23 01:36:44 PM PDT 24
Finished May 23 01:38:31 PM PDT 24
Peak memory 213960 kb
Host smart-f4a28f1d-3b2e-4e4c-be06-8dc2a43f9806
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257247503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2257247503
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1381468441
Short name T395
Test name
Test status
Simulation time 2761208592 ps
CPU time 12.65 seconds
Started May 23 01:36:43 PM PDT 24
Finished May 23 01:37:00 PM PDT 24
Peak memory 215304 kb
Host smart-9a40868c-73c3-4357-a5ce-5cc81f09d54d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381468441 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1381468441
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3391616039
Short name T388
Test name
Test status
Simulation time 10643575063 ps
CPU time 24.76 seconds
Started May 23 01:36:41 PM PDT 24
Finished May 23 01:37:09 PM PDT 24
Peak memory 212496 kb
Host smart-6fb28e56-2097-479f-980b-8d35e170b223
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391616039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3391616039
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2791369896
Short name T86
Test name
Test status
Simulation time 18970996224 ps
CPU time 163.82 seconds
Started May 23 01:36:41 PM PDT 24
Finished May 23 01:39:29 PM PDT 24
Peak memory 215640 kb
Host smart-54dbc609-987b-4ab4-9023-bb84d3ef5652
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791369896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2791369896
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1148922742
Short name T100
Test name
Test status
Simulation time 332446830 ps
CPU time 8.5 seconds
Started May 23 01:36:45 PM PDT 24
Finished May 23 01:36:58 PM PDT 24
Peak memory 211296 kb
Host smart-41e14e5a-1151-4c16-a1e1-7619fc5489e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148922742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1148922742
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2277014061
Short name T403
Test name
Test status
Simulation time 750499648 ps
CPU time 13.23 seconds
Started May 23 01:36:43 PM PDT 24
Finished May 23 01:37:00 PM PDT 24
Peak memory 217528 kb
Host smart-08513a16-8f4d-4d14-be9b-02152be9676c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277014061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2277014061
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.886657798
Short name T114
Test name
Test status
Simulation time 16571853513 ps
CPU time 103.34 seconds
Started May 23 01:36:42 PM PDT 24
Finished May 23 01:38:29 PM PDT 24
Peak memory 214080 kb
Host smart-cd806524-ffc0-4580-9555-3065f4b0694f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886657798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.886657798
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3900789519
Short name T429
Test name
Test status
Simulation time 2416429920 ps
CPU time 22.88 seconds
Started May 23 01:36:54 PM PDT 24
Finished May 23 01:37:20 PM PDT 24
Peak memory 217628 kb
Host smart-31e48c34-86da-43f7-99cf-572e24d6ba74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900789519 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3900789519
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.220445420
Short name T76
Test name
Test status
Simulation time 1645403548 ps
CPU time 18.92 seconds
Started May 23 01:36:52 PM PDT 24
Finished May 23 01:37:14 PM PDT 24
Peak memory 211516 kb
Host smart-bdec87d6-071d-4517-9eb6-249e20b4b3b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220445420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.220445420
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3841520615
Short name T440
Test name
Test status
Simulation time 28787111425 ps
CPU time 78.28 seconds
Started May 23 01:36:43 PM PDT 24
Finished May 23 01:38:05 PM PDT 24
Peak memory 213496 kb
Host smart-f534e26b-f47e-4fde-a08d-8d93f0cf4a56
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841520615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3841520615
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4017625172
Short name T420
Test name
Test status
Simulation time 3597974673 ps
CPU time 12.27 seconds
Started May 23 01:36:52 PM PDT 24
Finished May 23 01:37:08 PM PDT 24
Peak memory 211448 kb
Host smart-b6a9b1c3-72d0-4df2-9921-02cbf2b62f62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017625172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.4017625172
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3250908075
Short name T441
Test name
Test status
Simulation time 551986409 ps
CPU time 12.12 seconds
Started May 23 01:36:53 PM PDT 24
Finished May 23 01:37:09 PM PDT 24
Peak memory 217456 kb
Host smart-ad51932d-ddca-4c28-951c-3f8ee0db5da5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250908075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3250908075
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2914920228
Short name T375
Test name
Test status
Simulation time 10460694086 ps
CPU time 98.67 seconds
Started May 23 01:36:53 PM PDT 24
Finished May 23 01:38:35 PM PDT 24
Peak memory 213952 kb
Host smart-2938c3bd-32de-417d-855e-f2e7d22e870b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914920228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2914920228
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.644376186
Short name T390
Test name
Test status
Simulation time 733766926 ps
CPU time 8.79 seconds
Started May 23 01:36:51 PM PDT 24
Finished May 23 01:37:03 PM PDT 24
Peak memory 213960 kb
Host smart-00d35c4d-3d50-4379-97b9-87c6b67bf4ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644376186 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.644376186
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3070277628
Short name T391
Test name
Test status
Simulation time 1373633209 ps
CPU time 8.04 seconds
Started May 23 01:36:57 PM PDT 24
Finished May 23 01:37:07 PM PDT 24
Peak memory 211328 kb
Host smart-04ce7dd9-2b51-4afc-9b92-754d4ec50439
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070277628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3070277628
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.870111485
Short name T452
Test name
Test status
Simulation time 1746636812 ps
CPU time 49.47 seconds
Started May 23 01:36:52 PM PDT 24
Finished May 23 01:37:45 PM PDT 24
Peak memory 213384 kb
Host smart-2555bbcc-e3f4-41c7-b66b-3fb08ed9da4e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870111485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.870111485
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3582625459
Short name T438
Test name
Test status
Simulation time 1201436777 ps
CPU time 16.09 seconds
Started May 23 01:36:53 PM PDT 24
Finished May 23 01:37:12 PM PDT 24
Peak memory 211316 kb
Host smart-fbed8960-2591-4021-8d1f-833008d4dca4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582625459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3582625459
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2335993266
Short name T60
Test name
Test status
Simulation time 339202060 ps
CPU time 11.84 seconds
Started May 23 01:36:56 PM PDT 24
Finished May 23 01:37:10 PM PDT 24
Peak memory 217480 kb
Host smart-04d12ee1-f37e-4d42-9372-1714727a26f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335993266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2335993266
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3684063938
Short name T413
Test name
Test status
Simulation time 2341249277 ps
CPU time 84.34 seconds
Started May 23 01:36:54 PM PDT 24
Finished May 23 01:38:21 PM PDT 24
Peak memory 214524 kb
Host smart-bc6e81e0-d865-4ef6-9f8b-c9ea7e875d9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684063938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3684063938
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.292108180
Short name T439
Test name
Test status
Simulation time 9570306839 ps
CPU time 22.85 seconds
Started May 23 01:36:58 PM PDT 24
Finished May 23 01:37:22 PM PDT 24
Peak memory 219536 kb
Host smart-bfed6fb1-e9f8-4446-96d8-797f0ca914cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292108180 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.292108180
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.64921720
Short name T421
Test name
Test status
Simulation time 4277907979 ps
CPU time 31.78 seconds
Started May 23 01:36:54 PM PDT 24
Finished May 23 01:37:28 PM PDT 24
Peak memory 211900 kb
Host smart-9daabefa-d597-4f82-9839-b80ff3fdb56e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64921720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.64921720
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3355692744
Short name T425
Test name
Test status
Simulation time 27455961852 ps
CPU time 77.17 seconds
Started May 23 01:36:52 PM PDT 24
Finished May 23 01:38:12 PM PDT 24
Peak memory 214480 kb
Host smart-284907b8-35dc-4cef-816f-67a8f295e11e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355692744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3355692744
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.406612382
Short name T409
Test name
Test status
Simulation time 2461053038 ps
CPU time 26.71 seconds
Started May 23 01:36:53 PM PDT 24
Finished May 23 01:37:23 PM PDT 24
Peak memory 212308 kb
Host smart-5e825290-dea7-41ec-944b-96de59934b3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406612382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.406612382
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4038817056
Short name T392
Test name
Test status
Simulation time 5373832757 ps
CPU time 32.49 seconds
Started May 23 01:36:53 PM PDT 24
Finished May 23 01:37:29 PM PDT 24
Peak memory 218796 kb
Host smart-e0c8bb7f-a47d-4267-b5ae-7845eb1b2aca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038817056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.4038817056
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.838305617
Short name T105
Test name
Test status
Simulation time 10697213140 ps
CPU time 95.74 seconds
Started May 23 01:36:55 PM PDT 24
Finished May 23 01:38:33 PM PDT 24
Peak memory 212660 kb
Host smart-95d9c833-ad86-47b6-b9ec-428e072b265d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838305617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.838305617
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2868152249
Short name T360
Test name
Test status
Simulation time 13550385825 ps
CPU time 20.84 seconds
Started May 23 01:36:56 PM PDT 24
Finished May 23 01:37:19 PM PDT 24
Peak memory 219448 kb
Host smart-601c6fbe-cf28-4606-b295-4b1d531e3564
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868152249 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2868152249
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.619783547
Short name T88
Test name
Test status
Simulation time 1178157738 ps
CPU time 12.5 seconds
Started May 23 01:36:54 PM PDT 24
Finished May 23 01:37:10 PM PDT 24
Peak memory 211256 kb
Host smart-796444ac-d608-418d-b0d7-e9e5a9c0aa08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619783547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.619783547
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.852286766
Short name T77
Test name
Test status
Simulation time 25147431642 ps
CPU time 200.72 seconds
Started May 23 01:36:53 PM PDT 24
Finished May 23 01:40:17 PM PDT 24
Peak memory 215496 kb
Host smart-fb758cf9-3f92-4f81-972f-3c37c0aebace
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852286766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.852286766
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3999468626
Short name T446
Test name
Test status
Simulation time 613172664 ps
CPU time 16.06 seconds
Started May 23 01:36:52 PM PDT 24
Finished May 23 01:37:11 PM PDT 24
Peak memory 212496 kb
Host smart-9c2c9827-6262-443b-a994-447a859fccaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999468626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3999468626
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.96815521
Short name T401
Test name
Test status
Simulation time 9851369053 ps
CPU time 28.42 seconds
Started May 23 01:36:53 PM PDT 24
Finished May 23 01:37:25 PM PDT 24
Peak memory 219076 kb
Host smart-c5cb278a-4a4b-4b9c-908e-f2302b3298d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96815521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.96815521
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1795669616
Short name T111
Test name
Test status
Simulation time 12054353589 ps
CPU time 98.24 seconds
Started May 23 01:36:52 PM PDT 24
Finished May 23 01:38:34 PM PDT 24
Peak memory 213720 kb
Host smart-1f3082b8-d9e4-4eb8-9f91-a6b8c6620d65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795669616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1795669616
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3020801014
Short name T400
Test name
Test status
Simulation time 851446508 ps
CPU time 14.31 seconds
Started May 23 01:36:53 PM PDT 24
Finished May 23 01:37:10 PM PDT 24
Peak memory 217636 kb
Host smart-09b8e2f7-9c5c-411c-9f98-7a7ae32251ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020801014 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3020801014
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.634214018
Short name T450
Test name
Test status
Simulation time 1835975850 ps
CPU time 11.83 seconds
Started May 23 01:36:53 PM PDT 24
Finished May 23 01:37:08 PM PDT 24
Peak memory 211172 kb
Host smart-5a2ce2c8-8e50-4155-8dfa-1ce27bf65172
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634214018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.634214018
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1160541981
Short name T104
Test name
Test status
Simulation time 24208869443 ps
CPU time 198.57 seconds
Started May 23 01:36:59 PM PDT 24
Finished May 23 01:40:20 PM PDT 24
Peak memory 215788 kb
Host smart-2864b460-68d0-4519-8347-6750af59a40e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160541981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1160541981
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2907894034
Short name T96
Test name
Test status
Simulation time 167511798 ps
CPU time 8.22 seconds
Started May 23 01:36:51 PM PDT 24
Finished May 23 01:37:03 PM PDT 24
Peak memory 211304 kb
Host smart-a24943c9-beba-4a8f-819f-5b151f3ffc5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907894034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2907894034
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2934982866
Short name T431
Test name
Test status
Simulation time 2909242103 ps
CPU time 28.13 seconds
Started May 23 01:36:54 PM PDT 24
Finished May 23 01:37:25 PM PDT 24
Peak memory 218560 kb
Host smart-35377cb8-bd0c-43a8-bc75-0f0b7d59c384
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934982866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2934982866
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1986148185
Short name T50
Test name
Test status
Simulation time 8598989346 ps
CPU time 32.28 seconds
Started May 23 01:36:53 PM PDT 24
Finished May 23 01:37:28 PM PDT 24
Peak memory 217592 kb
Host smart-86f09320-1f58-4e35-9835-f4d15eb1bdcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986148185 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1986148185
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4131297814
Short name T411
Test name
Test status
Simulation time 2392487305 ps
CPU time 21.53 seconds
Started May 23 01:36:53 PM PDT 24
Finished May 23 01:37:18 PM PDT 24
Peak memory 212104 kb
Host smart-359c9344-fb76-4987-8d30-e9604fd279ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131297814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.4131297814
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3551967367
Short name T454
Test name
Test status
Simulation time 783838276 ps
CPU time 37.24 seconds
Started May 23 01:36:58 PM PDT 24
Finished May 23 01:37:37 PM PDT 24
Peak memory 214444 kb
Host smart-8270d4f4-054d-4d34-9a89-aefb45e24656
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551967367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3551967367
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1965402482
Short name T416
Test name
Test status
Simulation time 814765566 ps
CPU time 13.32 seconds
Started May 23 01:36:58 PM PDT 24
Finished May 23 01:37:14 PM PDT 24
Peak memory 211404 kb
Host smart-47825e4a-0e56-4e76-be80-8fb880574619
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965402482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1965402482
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1719226783
Short name T418
Test name
Test status
Simulation time 3422467265 ps
CPU time 34.62 seconds
Started May 23 01:36:53 PM PDT 24
Finished May 23 01:37:30 PM PDT 24
Peak memory 218656 kb
Host smart-c45be16f-cd6b-4c26-9dec-7943b5f04d71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719226783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1719226783
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3405132486
Short name T451
Test name
Test status
Simulation time 4031392299 ps
CPU time 88 seconds
Started May 23 01:36:54 PM PDT 24
Finished May 23 01:38:25 PM PDT 24
Peak memory 213828 kb
Host smart-14c3f68d-2907-4e5c-b1ab-2daa5a8bf841
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405132486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3405132486
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2940355543
Short name T363
Test name
Test status
Simulation time 4215252657 ps
CPU time 33.32 seconds
Started May 23 01:36:58 PM PDT 24
Finished May 23 01:37:33 PM PDT 24
Peak memory 218180 kb
Host smart-84b57dfe-38f9-4407-9c0c-dd2b90dc56ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940355543 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2940355543
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1809353364
Short name T69
Test name
Test status
Simulation time 332075469 ps
CPU time 8.17 seconds
Started May 23 01:36:59 PM PDT 24
Finished May 23 01:37:09 PM PDT 24
Peak memory 211280 kb
Host smart-a97c1563-2b54-4f94-9150-f367d2889a85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809353364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1809353364
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1126623736
Short name T437
Test name
Test status
Simulation time 19130640058 ps
CPU time 153.05 seconds
Started May 23 01:36:54 PM PDT 24
Finished May 23 01:39:30 PM PDT 24
Peak memory 215388 kb
Host smart-e22865c3-f960-4a88-b4f6-530659263917
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126623736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1126623736
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3064428376
Short name T97
Test name
Test status
Simulation time 3770873152 ps
CPU time 29.69 seconds
Started May 23 01:36:58 PM PDT 24
Finished May 23 01:37:30 PM PDT 24
Peak memory 211856 kb
Host smart-8a83c767-da30-4db8-9c85-5259638a805c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064428376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3064428376
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.410958536
Short name T387
Test name
Test status
Simulation time 6744327078 ps
CPU time 23.05 seconds
Started May 23 01:36:56 PM PDT 24
Finished May 23 01:37:21 PM PDT 24
Peak memory 218652 kb
Host smart-6fbfa366-6832-4155-b471-011e8407140d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410958536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.410958536
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1523756142
Short name T62
Test name
Test status
Simulation time 9272810334 ps
CPU time 100.43 seconds
Started May 23 01:36:59 PM PDT 24
Finished May 23 01:38:41 PM PDT 24
Peak memory 213940 kb
Host smart-5f09141d-5ed3-4962-8988-53a19263f475
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523756142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1523756142
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2610830763
Short name T408
Test name
Test status
Simulation time 544740798 ps
CPU time 8.97 seconds
Started May 23 01:36:54 PM PDT 24
Finished May 23 01:37:06 PM PDT 24
Peak memory 216296 kb
Host smart-5fefc33c-66e1-426b-803d-466f7aba4e63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610830763 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2610830763
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1403413214
Short name T399
Test name
Test status
Simulation time 661778633 ps
CPU time 8.13 seconds
Started May 23 01:36:57 PM PDT 24
Finished May 23 01:37:07 PM PDT 24
Peak memory 211320 kb
Host smart-84cdbee2-c015-42c8-9716-9b0ee4602c17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403413214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1403413214
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2585063459
Short name T417
Test name
Test status
Simulation time 73624322711 ps
CPU time 173 seconds
Started May 23 01:36:56 PM PDT 24
Finished May 23 01:39:51 PM PDT 24
Peak memory 216556 kb
Host smart-7b59ceed-8270-4ea7-9680-987c22f39796
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585063459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2585063459
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1074520278
Short name T436
Test name
Test status
Simulation time 332399365 ps
CPU time 8.25 seconds
Started May 23 01:36:53 PM PDT 24
Finished May 23 01:37:05 PM PDT 24
Peak memory 211296 kb
Host smart-b3eb1fb0-72ad-406b-ae06-49246811a553
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074520278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1074520278
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2226586284
Short name T61
Test name
Test status
Simulation time 368651663 ps
CPU time 11.48 seconds
Started May 23 01:36:53 PM PDT 24
Finished May 23 01:37:08 PM PDT 24
Peak memory 217084 kb
Host smart-11c8b73b-a29e-4487-b6b1-e690b6bdd4f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226586284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2226586284
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2250603586
Short name T110
Test name
Test status
Simulation time 613857227 ps
CPU time 151.85 seconds
Started May 23 01:36:58 PM PDT 24
Finished May 23 01:39:32 PM PDT 24
Peak memory 214028 kb
Host smart-6fcb354f-8599-4983-8ef6-b931bf6864bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250603586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2250603586
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1824377922
Short name T415
Test name
Test status
Simulation time 517972310 ps
CPU time 12.12 seconds
Started May 23 01:36:40 PM PDT 24
Finished May 23 01:36:56 PM PDT 24
Peak memory 211308 kb
Host smart-7d68fe8c-3be0-4c04-95ef-a18a6efeb499
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824377922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1824377922
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.5761392
Short name T377
Test name
Test status
Simulation time 2995622002 ps
CPU time 25.24 seconds
Started May 23 01:36:41 PM PDT 24
Finished May 23 01:37:09 PM PDT 24
Peak memory 211628 kb
Host smart-227d5a6b-f662-4815-ac02-d95c8f3c478d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5761392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bas
h.5761392
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.333037987
Short name T68
Test name
Test status
Simulation time 3286634063 ps
CPU time 16.97 seconds
Started May 23 01:36:40 PM PDT 24
Finished May 23 01:36:59 PM PDT 24
Peak memory 211340 kb
Host smart-a43dbe95-4a62-408f-b578-31350aa405f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333037987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.333037987
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4267367108
Short name T453
Test name
Test status
Simulation time 3136497580 ps
CPU time 27.17 seconds
Started May 23 01:36:40 PM PDT 24
Finished May 23 01:37:09 PM PDT 24
Peak memory 218012 kb
Host smart-143e6ea3-75bd-4ee5-9e35-ade716c25910
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267367108 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.4267367108
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2470923282
Short name T404
Test name
Test status
Simulation time 15559211271 ps
CPU time 30.67 seconds
Started May 23 01:36:42 PM PDT 24
Finished May 23 01:37:16 PM PDT 24
Peak memory 212244 kb
Host smart-b8f56768-0ba3-4bb2-b0e0-bc3a72f5dffe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470923282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2470923282
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.946749087
Short name T424
Test name
Test status
Simulation time 516399483 ps
CPU time 11.83 seconds
Started May 23 01:36:45 PM PDT 24
Finished May 23 01:37:01 PM PDT 24
Peak memory 211192 kb
Host smart-0a30f214-e958-4c82-a44c-1d572b8dade0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946749087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.946749087
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2935771835
Short name T448
Test name
Test status
Simulation time 4083876344 ps
CPU time 29.91 seconds
Started May 23 01:36:40 PM PDT 24
Finished May 23 01:37:13 PM PDT 24
Peak memory 211328 kb
Host smart-1dbe315f-a013-4190-8e86-e9f3b12ebb54
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935771835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2935771835
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1592195726
Short name T103
Test name
Test status
Simulation time 13997248886 ps
CPU time 136.68 seconds
Started May 23 01:36:42 PM PDT 24
Finished May 23 01:39:03 PM PDT 24
Peak memory 215580 kb
Host smart-ab18ee7d-0df8-4a9c-8df2-dbf624c880db
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592195726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1592195726
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.954692596
Short name T99
Test name
Test status
Simulation time 17913763872 ps
CPU time 26.51 seconds
Started May 23 01:36:39 PM PDT 24
Finished May 23 01:37:07 PM PDT 24
Peak memory 212916 kb
Host smart-f2dd2f52-9c9c-4758-8ec8-8afabb3c425b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954692596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.954692596
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2003293568
Short name T367
Test name
Test status
Simulation time 3461047773 ps
CPU time 33.4 seconds
Started May 23 01:36:45 PM PDT 24
Finished May 23 01:37:23 PM PDT 24
Peak memory 219632 kb
Host smart-3a3bf365-6298-407d-9374-bd70cc8a4f80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003293568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2003293568
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1401045823
Short name T73
Test name
Test status
Simulation time 822394715 ps
CPU time 13.97 seconds
Started May 23 01:36:44 PM PDT 24
Finished May 23 01:37:02 PM PDT 24
Peak memory 211288 kb
Host smart-b685076e-8fd6-4b03-aa0a-597e215d9192
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401045823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1401045823
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2772030355
Short name T382
Test name
Test status
Simulation time 4299678112 ps
CPU time 30.37 seconds
Started May 23 01:36:43 PM PDT 24
Finished May 23 01:37:18 PM PDT 24
Peak memory 212180 kb
Host smart-93f64356-3060-47ea-be46-c983d1ca19b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772030355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2772030355
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2196462086
Short name T84
Test name
Test status
Simulation time 2354119751 ps
CPU time 20.63 seconds
Started May 23 01:36:40 PM PDT 24
Finished May 23 01:37:03 PM PDT 24
Peak memory 212056 kb
Host smart-e2f2dc0a-e201-4084-9d04-8f280226d231
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196462086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2196462086
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2117978216
Short name T442
Test name
Test status
Simulation time 3098460478 ps
CPU time 26.16 seconds
Started May 23 01:36:44 PM PDT 24
Finished May 23 01:37:14 PM PDT 24
Peak memory 216384 kb
Host smart-4075b3ac-3e94-4c40-b77c-325133e5151c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117978216 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2117978216
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4199714090
Short name T70
Test name
Test status
Simulation time 13432072424 ps
CPU time 28.86 seconds
Started May 23 01:36:44 PM PDT 24
Finished May 23 01:37:17 PM PDT 24
Peak memory 219532 kb
Host smart-0e0b4d7b-f5c4-4f17-86bb-a1021709cd47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199714090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.4199714090
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.878958412
Short name T370
Test name
Test status
Simulation time 1889188557 ps
CPU time 18.25 seconds
Started May 23 01:36:41 PM PDT 24
Finished May 23 01:37:03 PM PDT 24
Peak memory 211092 kb
Host smart-2dd45ab7-54f2-4c65-b6f7-611d9b72246f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878958412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.878958412
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.821180755
Short name T447
Test name
Test status
Simulation time 16704634512 ps
CPU time 33.1 seconds
Started May 23 01:36:40 PM PDT 24
Finished May 23 01:37:16 PM PDT 24
Peak memory 211336 kb
Host smart-6839ccf6-b762-41e1-a04f-9a2705b7f382
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821180755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
821180755
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3653042388
Short name T98
Test name
Test status
Simulation time 8571246593 ps
CPU time 30.39 seconds
Started May 23 01:36:43 PM PDT 24
Finished May 23 01:37:17 PM PDT 24
Peak memory 212668 kb
Host smart-de0e725f-c528-4c63-b702-711e72872c57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653042388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3653042388
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2468880672
Short name T405
Test name
Test status
Simulation time 3322358425 ps
CPU time 29.99 seconds
Started May 23 01:36:40 PM PDT 24
Finished May 23 01:37:13 PM PDT 24
Peak memory 218480 kb
Host smart-1334b0cd-ee41-4e95-9015-5adec5fe4906
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468880672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2468880672
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2378529707
Short name T116
Test name
Test status
Simulation time 3893595780 ps
CPU time 100.43 seconds
Started May 23 01:36:40 PM PDT 24
Finished May 23 01:38:24 PM PDT 24
Peak memory 213612 kb
Host smart-36932bb2-5a15-4b51-951d-29ce51c35b1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378529707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2378529707
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1017248347
Short name T102
Test name
Test status
Simulation time 2369074876 ps
CPU time 23.4 seconds
Started May 23 01:36:43 PM PDT 24
Finished May 23 01:37:11 PM PDT 24
Peak memory 211864 kb
Host smart-a9b1aa8d-eed2-4aa1-bd0c-41536f37ec78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017248347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1017248347
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1261121434
Short name T379
Test name
Test status
Simulation time 12252382871 ps
CPU time 25.22 seconds
Started May 23 01:36:43 PM PDT 24
Finished May 23 01:37:12 PM PDT 24
Peak memory 219564 kb
Host smart-680571fc-0087-45c6-8900-c46c56e30e58
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261121434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1261121434
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4270030543
Short name T445
Test name
Test status
Simulation time 1671892351 ps
CPU time 13.3 seconds
Started May 23 01:36:43 PM PDT 24
Finished May 23 01:37:00 PM PDT 24
Peak memory 211300 kb
Host smart-7121419e-59c7-449e-a734-f714de622c1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270030543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4270030543
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.463350546
Short name T406
Test name
Test status
Simulation time 3762361838 ps
CPU time 13.83 seconds
Started May 23 01:36:43 PM PDT 24
Finished May 23 01:37:01 PM PDT 24
Peak memory 217036 kb
Host smart-253705c9-1d58-427c-937e-0771544b7abe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463350546 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.463350546
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3848194063
Short name T75
Test name
Test status
Simulation time 688611188 ps
CPU time 8.02 seconds
Started May 23 01:36:44 PM PDT 24
Finished May 23 01:36:57 PM PDT 24
Peak memory 211244 kb
Host smart-25bc4635-4230-4c6b-801e-00978f454be1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848194063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3848194063
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.135556408
Short name T432
Test name
Test status
Simulation time 3045977961 ps
CPU time 18.55 seconds
Started May 23 01:36:41 PM PDT 24
Finished May 23 01:37:03 PM PDT 24
Peak memory 211264 kb
Host smart-21cde284-fede-40c7-87df-8eec78f1380d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135556408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.135556408
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2134924344
Short name T372
Test name
Test status
Simulation time 194224185 ps
CPU time 8.58 seconds
Started May 23 01:36:40 PM PDT 24
Finished May 23 01:36:51 PM PDT 24
Peak memory 211236 kb
Host smart-193a5564-9ae9-4c0b-aa0e-71bc45f8c607
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134924344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2134924344
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3865070752
Short name T444
Test name
Test status
Simulation time 86543553886 ps
CPU time 205.88 seconds
Started May 23 01:36:43 PM PDT 24
Finished May 23 01:40:14 PM PDT 24
Peak memory 215468 kb
Host smart-853a0cc3-706b-43c6-a216-0d037f206656
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865070752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3865070752
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4128528515
Short name T101
Test name
Test status
Simulation time 7477267432 ps
CPU time 29.83 seconds
Started May 23 01:36:42 PM PDT 24
Finished May 23 01:37:16 PM PDT 24
Peak memory 212528 kb
Host smart-29b4f0ca-c6f1-42aa-821d-d976d7675450
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128528515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.4128528515
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1986068071
Short name T366
Test name
Test status
Simulation time 18017987705 ps
CPU time 34.71 seconds
Started May 23 01:36:41 PM PDT 24
Finished May 23 01:37:20 PM PDT 24
Peak memory 217952 kb
Host smart-308f7605-a856-4c77-9a38-03b194f7cb46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986068071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1986068071
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.422744442
Short name T115
Test name
Test status
Simulation time 4767018014 ps
CPU time 158.65 seconds
Started May 23 01:36:40 PM PDT 24
Finished May 23 01:39:21 PM PDT 24
Peak memory 214380 kb
Host smart-31341a40-3d89-4048-bb75-ab7c26dbafd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422744442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.422744442
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2075678778
Short name T371
Test name
Test status
Simulation time 1434334983 ps
CPU time 11.18 seconds
Started May 23 01:36:45 PM PDT 24
Finished May 23 01:37:00 PM PDT 24
Peak memory 216536 kb
Host smart-0bffd110-5731-41cb-8aa2-44666a0f59ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075678778 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2075678778
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1321931568
Short name T397
Test name
Test status
Simulation time 496196131 ps
CPU time 9.92 seconds
Started May 23 01:36:44 PM PDT 24
Finished May 23 01:36:59 PM PDT 24
Peak memory 211276 kb
Host smart-fae54dd8-6845-49ed-a21f-88404482756d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321931568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1321931568
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.444694416
Short name T82
Test name
Test status
Simulation time 55999659814 ps
CPU time 92.82 seconds
Started May 23 01:36:42 PM PDT 24
Finished May 23 01:38:19 PM PDT 24
Peak memory 214464 kb
Host smart-177c04f5-7c5c-4e4c-8d36-1122aec7ddb3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444694416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.444694416
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3725466886
Short name T368
Test name
Test status
Simulation time 2507124231 ps
CPU time 23.9 seconds
Started May 23 01:36:41 PM PDT 24
Finished May 23 01:37:08 PM PDT 24
Peak memory 212268 kb
Host smart-6aec876f-0511-4c8b-9bfc-432289759355
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725466886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3725466886
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2694727864
Short name T426
Test name
Test status
Simulation time 1217927161 ps
CPU time 18.39 seconds
Started May 23 01:36:42 PM PDT 24
Finished May 23 01:37:05 PM PDT 24
Peak memory 218508 kb
Host smart-4a57125c-596a-4246-adf8-7ff37fb9b033
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694727864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2694727864
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.989608393
Short name T108
Test name
Test status
Simulation time 32586674302 ps
CPU time 98.16 seconds
Started May 23 01:36:44 PM PDT 24
Finished May 23 01:38:26 PM PDT 24
Peak memory 213828 kb
Host smart-7b77d8b7-6a42-4904-8537-9292684edf0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989608393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.989608393
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2781395648
Short name T376
Test name
Test status
Simulation time 26065864981 ps
CPU time 18.9 seconds
Started May 23 01:36:45 PM PDT 24
Finished May 23 01:37:08 PM PDT 24
Peak memory 219608 kb
Host smart-54489e36-8119-4abb-a4b4-2f00b7922c47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781395648 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2781395648
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.151592777
Short name T430
Test name
Test status
Simulation time 3436666334 ps
CPU time 18.94 seconds
Started May 23 01:36:45 PM PDT 24
Finished May 23 01:37:08 PM PDT 24
Peak memory 211672 kb
Host smart-0d9d8dd3-b7ca-46ab-9819-18545a9ff9af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151592777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.151592777
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2810959257
Short name T85
Test name
Test status
Simulation time 104254488191 ps
CPU time 120.35 seconds
Started May 23 01:36:42 PM PDT 24
Finished May 23 01:38:46 PM PDT 24
Peak memory 215452 kb
Host smart-3826c9d7-e2db-4ebd-b62f-92ec3b5c3dee
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810959257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2810959257
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3567726809
Short name T374
Test name
Test status
Simulation time 3730274977 ps
CPU time 16.41 seconds
Started May 23 01:36:47 PM PDT 24
Finished May 23 01:37:07 PM PDT 24
Peak memory 211372 kb
Host smart-2ca49285-819d-40c7-80c0-4fef38e5545e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567726809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3567726809
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2013119303
Short name T365
Test name
Test status
Simulation time 941034108 ps
CPU time 17.4 seconds
Started May 23 01:36:44 PM PDT 24
Finished May 23 01:37:06 PM PDT 24
Peak memory 217052 kb
Host smart-8352837b-4d4c-4d88-a0ce-b84d68cde954
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013119303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2013119303
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3758733174
Short name T412
Test name
Test status
Simulation time 677894214 ps
CPU time 83.3 seconds
Started May 23 01:36:44 PM PDT 24
Finished May 23 01:38:12 PM PDT 24
Peak memory 213568 kb
Host smart-4aef8127-7846-41f6-85a9-fa298b25215d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758733174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3758733174
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3362812658
Short name T414
Test name
Test status
Simulation time 960935326 ps
CPU time 8.85 seconds
Started May 23 01:36:44 PM PDT 24
Finished May 23 01:36:57 PM PDT 24
Peak memory 215508 kb
Host smart-03207422-70f4-4fe8-8ced-28e3cee6ded3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362812658 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3362812658
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3395856620
Short name T90
Test name
Test status
Simulation time 1236819304 ps
CPU time 15.69 seconds
Started May 23 01:36:44 PM PDT 24
Finished May 23 01:37:03 PM PDT 24
Peak memory 211376 kb
Host smart-16fcbf1a-b740-4cc3-8df8-94e1720bbd53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395856620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3395856620
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.644607937
Short name T423
Test name
Test status
Simulation time 1442969467 ps
CPU time 37.72 seconds
Started May 23 01:36:43 PM PDT 24
Finished May 23 01:37:25 PM PDT 24
Peak memory 213368 kb
Host smart-67b406b2-2277-40eb-9c5e-f43cde71c300
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644607937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.644607937
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1715981880
Short name T398
Test name
Test status
Simulation time 184571998 ps
CPU time 12.36 seconds
Started May 23 01:36:43 PM PDT 24
Finished May 23 01:36:59 PM PDT 24
Peak memory 212636 kb
Host smart-a8a9bdd6-fb21-4082-93c4-d3fb306c1dca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715981880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1715981880
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4105339293
Short name T385
Test name
Test status
Simulation time 4190625684 ps
CPU time 34.74 seconds
Started May 23 01:36:47 PM PDT 24
Finished May 23 01:37:25 PM PDT 24
Peak memory 217572 kb
Host smart-93b78639-effa-4132-9dd6-f69cebe36976
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105339293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.4105339293
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3964209872
Short name T109
Test name
Test status
Simulation time 2800694636 ps
CPU time 96.52 seconds
Started May 23 01:36:45 PM PDT 24
Finished May 23 01:38:26 PM PDT 24
Peak memory 213612 kb
Host smart-c9ead184-2461-4394-a409-240519d2294f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964209872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3964209872
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.272189296
Short name T449
Test name
Test status
Simulation time 18771850297 ps
CPU time 31.61 seconds
Started May 23 01:36:48 PM PDT 24
Finished May 23 01:37:23 PM PDT 24
Peak memory 217744 kb
Host smart-cadf5082-934e-4f0f-8950-87f590131c01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272189296 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.272189296
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3442038411
Short name T419
Test name
Test status
Simulation time 15107284162 ps
CPU time 31.01 seconds
Started May 23 01:36:47 PM PDT 24
Finished May 23 01:37:22 PM PDT 24
Peak memory 212612 kb
Host smart-681c327a-e5e8-440f-a65f-83fba4f4a3bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442038411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3442038411
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.607689563
Short name T427
Test name
Test status
Simulation time 92774820906 ps
CPU time 138.94 seconds
Started May 23 01:36:47 PM PDT 24
Finished May 23 01:39:10 PM PDT 24
Peak memory 214412 kb
Host smart-a413b80a-d2ca-4084-a7fc-c1109c9dba3a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607689563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.607689563
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3271425291
Short name T384
Test name
Test status
Simulation time 478831628 ps
CPU time 9.94 seconds
Started May 23 01:36:43 PM PDT 24
Finished May 23 01:36:58 PM PDT 24
Peak memory 211356 kb
Host smart-109f1bd9-0e4c-4eb8-8ed9-0dc7dde6b11f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271425291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3271425291
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1960067740
Short name T52
Test name
Test status
Simulation time 4838445817 ps
CPU time 28.91 seconds
Started May 23 01:36:47 PM PDT 24
Finished May 23 01:37:20 PM PDT 24
Peak memory 218040 kb
Host smart-98101a55-ae66-4edb-8430-496c381dc4c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960067740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1960067740
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1808184198
Short name T361
Test name
Test status
Simulation time 2794514938 ps
CPU time 13.43 seconds
Started May 23 01:36:46 PM PDT 24
Finished May 23 01:37:03 PM PDT 24
Peak memory 215652 kb
Host smart-c88fc2d7-4d1d-49d6-abfb-8f8a37537ef2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808184198 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1808184198
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4032024829
Short name T83
Test name
Test status
Simulation time 176374154 ps
CPU time 8.24 seconds
Started May 23 01:36:48 PM PDT 24
Finished May 23 01:36:59 PM PDT 24
Peak memory 211300 kb
Host smart-e42bdb23-c5c6-46c0-b677-44f9b186fbc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032024829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.4032024829
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2130152091
Short name T422
Test name
Test status
Simulation time 694285164 ps
CPU time 38.55 seconds
Started May 23 01:36:48 PM PDT 24
Finished May 23 01:37:30 PM PDT 24
Peak memory 213680 kb
Host smart-a2f5e64b-14ce-499d-88f7-538fe6d1c00b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130152091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2130152091
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3154260176
Short name T433
Test name
Test status
Simulation time 14361993663 ps
CPU time 29.19 seconds
Started May 23 01:36:48 PM PDT 24
Finished May 23 01:37:20 PM PDT 24
Peak memory 212612 kb
Host smart-5b9150e3-057f-49f5-8005-02b94bd0812a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154260176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3154260176
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4105397941
Short name T362
Test name
Test status
Simulation time 3930915740 ps
CPU time 34.96 seconds
Started May 23 01:36:43 PM PDT 24
Finished May 23 01:37:22 PM PDT 24
Peak memory 219556 kb
Host smart-a5779b08-2e3c-427a-a91e-82b61bd5c7a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105397941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.4105397941
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2967840952
Short name T53
Test name
Test status
Simulation time 247798724 ps
CPU time 79.63 seconds
Started May 23 01:36:46 PM PDT 24
Finished May 23 01:38:09 PM PDT 24
Peak memory 213772 kb
Host smart-bdcdfd13-04cd-4fd7-ac1f-39dc4178a70d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967840952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2967840952
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3832079539
Short name T123
Test name
Test status
Simulation time 2561611416 ps
CPU time 22.61 seconds
Started May 23 01:36:56 PM PDT 24
Finished May 23 01:37:21 PM PDT 24
Peak memory 211432 kb
Host smart-d31e3537-6270-4707-b3fa-2773f5a40bc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832079539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3832079539
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3063346922
Short name T146
Test name
Test status
Simulation time 9232079474 ps
CPU time 198.63 seconds
Started May 23 01:36:58 PM PDT 24
Finished May 23 01:40:18 PM PDT 24
Peak memory 225848 kb
Host smart-6cfecd70-ce30-4883-b748-fcdbb5b0ebec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063346922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3063346922
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2219969165
Short name T277
Test name
Test status
Simulation time 8087508676 ps
CPU time 67.16 seconds
Started May 23 01:37:03 PM PDT 24
Finished May 23 01:38:13 PM PDT 24
Peak memory 214944 kb
Host smart-b6934857-302a-4a1d-ace3-367381826fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219969165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2219969165
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1665246887
Short name T65
Test name
Test status
Simulation time 678741994 ps
CPU time 10.65 seconds
Started May 23 01:36:56 PM PDT 24
Finished May 23 01:37:09 PM PDT 24
Peak memory 211480 kb
Host smart-4732955f-48be-471b-a190-49060af5dcd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1665246887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1665246887
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3577904981
Short name T32
Test name
Test status
Simulation time 1374268660 ps
CPU time 225.65 seconds
Started May 23 01:36:56 PM PDT 24
Finished May 23 01:40:44 PM PDT 24
Peak memory 239888 kb
Host smart-bc048319-1075-4208-a1c6-53c47fa7cabe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577904981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3577904981
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1240380222
Short name T137
Test name
Test status
Simulation time 7717832585 ps
CPU time 63.39 seconds
Started May 23 01:36:57 PM PDT 24
Finished May 23 01:38:02 PM PDT 24
Peak memory 217768 kb
Host smart-fff41bc2-e02b-4eb8-801f-8d450281fcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240380222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1240380222
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3953506920
Short name T305
Test name
Test status
Simulation time 26141609301 ps
CPU time 65.38 seconds
Started May 23 01:36:54 PM PDT 24
Finished May 23 01:38:02 PM PDT 24
Peak memory 218748 kb
Host smart-814d8bfc-5250-4163-bb39-aefaf7422ddc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953506920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3953506920
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1738841353
Short name T324
Test name
Test status
Simulation time 34502164822 ps
CPU time 289.22 seconds
Started May 23 01:37:03 PM PDT 24
Finished May 23 01:41:55 PM PDT 24
Peak memory 238984 kb
Host smart-ca1d9b56-a8c8-4ec7-a8fa-2b02b60624b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738841353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1738841353
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.4050030798
Short name T333
Test name
Test status
Simulation time 8265099429 ps
CPU time 68.12 seconds
Started May 23 01:36:55 PM PDT 24
Finished May 23 01:38:06 PM PDT 24
Peak memory 215080 kb
Host smart-32267850-c93c-438c-bcdc-5b0d1c0187dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050030798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.4050030798
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.4211218704
Short name T221
Test name
Test status
Simulation time 4230426858 ps
CPU time 22.36 seconds
Started May 23 01:37:02 PM PDT 24
Finished May 23 01:37:27 PM PDT 24
Peak memory 211588 kb
Host smart-142cc19c-6231-4fa2-82c0-e3fa20769cb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4211218704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.4211218704
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.936951327
Short name T33
Test name
Test status
Simulation time 1948092177 ps
CPU time 124.19 seconds
Started May 23 01:36:53 PM PDT 24
Finished May 23 01:39:00 PM PDT 24
Peak memory 238516 kb
Host smart-55ba34af-4684-473e-acc4-ddaca7f3b31e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936951327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.936951327
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1882779932
Short name T328
Test name
Test status
Simulation time 30879823619 ps
CPU time 66.81 seconds
Started May 23 01:36:53 PM PDT 24
Finished May 23 01:38:03 PM PDT 24
Peak memory 218272 kb
Host smart-552ef349-2f1f-46fb-b147-c1c8000ef804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882779932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1882779932
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1898751397
Short name T179
Test name
Test status
Simulation time 4583384766 ps
CPU time 47.07 seconds
Started May 23 01:37:03 PM PDT 24
Finished May 23 01:37:53 PM PDT 24
Peak memory 219380 kb
Host smart-fcc4c2c3-10a8-4222-8fb5-a609746d079f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898751397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1898751397
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3418989883
Short name T49
Test name
Test status
Simulation time 60356963971 ps
CPU time 7472.79 seconds
Started May 23 01:36:54 PM PDT 24
Finished May 23 03:41:31 PM PDT 24
Peak memory 239060 kb
Host smart-1c34ce68-4bd1-4227-9fa4-bcdf9bcc546b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418989883 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.3418989883
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1192313657
Short name T316
Test name
Test status
Simulation time 5742966769 ps
CPU time 16.45 seconds
Started May 23 01:37:08 PM PDT 24
Finished May 23 01:37:28 PM PDT 24
Peak memory 211504 kb
Host smart-8e91e206-118d-42cd-a9ad-3dd654a33f7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192313657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1192313657
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3219119234
Short name T224
Test name
Test status
Simulation time 8627387503 ps
CPU time 144.86 seconds
Started May 23 01:37:10 PM PDT 24
Finished May 23 01:39:38 PM PDT 24
Peak memory 240428 kb
Host smart-13a17d5d-6cca-4bb6-9e3f-01c4b76e2a25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219119234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3219119234
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3508840582
Short name T257
Test name
Test status
Simulation time 8622302262 ps
CPU time 30.72 seconds
Started May 23 01:37:04 PM PDT 24
Finished May 23 01:37:39 PM PDT 24
Peak memory 215376 kb
Host smart-d0626653-2ac5-44d4-be87-b506b91aa224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508840582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3508840582
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3141961953
Short name T226
Test name
Test status
Simulation time 6282930114 ps
CPU time 20.26 seconds
Started May 23 01:37:11 PM PDT 24
Finished May 23 01:37:34 PM PDT 24
Peak memory 211480 kb
Host smart-efab7f71-9c32-4314-a9ed-44cfb4b39bbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3141961953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3141961953
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1583520072
Short name T121
Test name
Test status
Simulation time 20103770423 ps
CPU time 53.8 seconds
Started May 23 01:37:08 PM PDT 24
Finished May 23 01:38:06 PM PDT 24
Peak memory 216712 kb
Host smart-483b25a1-88d3-445b-9093-8ada58282273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583520072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1583520072
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.360583780
Short name T64
Test name
Test status
Simulation time 35557467730 ps
CPU time 98.29 seconds
Started May 23 01:37:06 PM PDT 24
Finished May 23 01:38:49 PM PDT 24
Peak memory 219612 kb
Host smart-3987c3ce-b716-4c9f-b38b-fbae5ebf39d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360583780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.360583780
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3093329319
Short name T48
Test name
Test status
Simulation time 197652973436 ps
CPU time 1876.97 seconds
Started May 23 01:37:10 PM PDT 24
Finished May 23 02:08:31 PM PDT 24
Peak memory 245776 kb
Host smart-33120894-85d2-4555-850b-60074c56f326
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093329319 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3093329319
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1587981605
Short name T255
Test name
Test status
Simulation time 167458824 ps
CPU time 8.41 seconds
Started May 23 01:37:16 PM PDT 24
Finished May 23 01:37:28 PM PDT 24
Peak memory 211364 kb
Host smart-517c42f8-c3e8-4e02-b5e7-bea3e9a7e3a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587981605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1587981605
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1615494913
Short name T150
Test name
Test status
Simulation time 15588507006 ps
CPU time 233.36 seconds
Started May 23 01:37:10 PM PDT 24
Finished May 23 01:41:07 PM PDT 24
Peak memory 237908 kb
Host smart-6a8d94d9-99e8-4d26-b789-adef47a74917
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615494913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1615494913
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2435626607
Short name T351
Test name
Test status
Simulation time 6161640061 ps
CPU time 51.49 seconds
Started May 23 01:37:08 PM PDT 24
Finished May 23 01:38:03 PM PDT 24
Peak memory 215064 kb
Host smart-205e5fff-d16c-4f62-8a94-ab9a19e4ae67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435626607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2435626607
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.387591791
Short name T136
Test name
Test status
Simulation time 5099767579 ps
CPU time 26.36 seconds
Started May 23 01:37:06 PM PDT 24
Finished May 23 01:37:36 PM PDT 24
Peak memory 212752 kb
Host smart-56c708fb-adfd-4b14-b5db-da089cb61c85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=387591791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.387591791
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1423268962
Short name T251
Test name
Test status
Simulation time 10629664473 ps
CPU time 36.7 seconds
Started May 23 01:37:11 PM PDT 24
Finished May 23 01:37:50 PM PDT 24
Peak memory 216212 kb
Host smart-e2467e65-a70f-4201-91a8-78ad2a70ff67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423268962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1423268962
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1728762417
Short name T278
Test name
Test status
Simulation time 17773790515 ps
CPU time 83.02 seconds
Started May 23 01:37:06 PM PDT 24
Finished May 23 01:38:34 PM PDT 24
Peak memory 219556 kb
Host smart-d8e83a85-490f-4e57-b34c-cfbfa0ee6ec9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728762417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1728762417
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2239145903
Short name T245
Test name
Test status
Simulation time 1421044960 ps
CPU time 11.49 seconds
Started May 23 01:37:16 PM PDT 24
Finished May 23 01:37:31 PM PDT 24
Peak memory 211372 kb
Host smart-eb33d719-cb63-460e-b3b3-b40e7207e0a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239145903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2239145903
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2928290024
Short name T168
Test name
Test status
Simulation time 52507859648 ps
CPU time 531.88 seconds
Started May 23 01:37:17 PM PDT 24
Finished May 23 01:46:11 PM PDT 24
Peak memory 237804 kb
Host smart-3d80ccda-9843-4647-805e-d83813bd15f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928290024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2928290024
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1352120168
Short name T337
Test name
Test status
Simulation time 2058470382 ps
CPU time 22.51 seconds
Started May 23 01:37:19 PM PDT 24
Finished May 23 01:37:44 PM PDT 24
Peak memory 211208 kb
Host smart-43961e08-0acd-4005-90ce-95f69f381667
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1352120168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1352120168
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2574680234
Short name T4
Test name
Test status
Simulation time 8912548415 ps
CPU time 48.05 seconds
Started May 23 01:37:18 PM PDT 24
Finished May 23 01:38:09 PM PDT 24
Peak memory 217780 kb
Host smart-a6f58651-c460-49f5-b357-bca0c709892d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574680234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2574680234
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.123433126
Short name T10
Test name
Test status
Simulation time 4513548348 ps
CPU time 68.61 seconds
Started May 23 01:37:16 PM PDT 24
Finished May 23 01:38:28 PM PDT 24
Peak memory 219388 kb
Host smart-c659b523-0693-41e7-8ac1-0724eb416bc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123433126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.123433126
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.475053335
Short name T289
Test name
Test status
Simulation time 869609795 ps
CPU time 8.34 seconds
Started May 23 01:37:19 PM PDT 24
Finished May 23 01:37:30 PM PDT 24
Peak memory 210984 kb
Host smart-f1f3cef9-3e6b-4898-9cff-52d685eb5e2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475053335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.475053335
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1438324070
Short name T192
Test name
Test status
Simulation time 41969144881 ps
CPU time 327.1 seconds
Started May 23 01:37:18 PM PDT 24
Finished May 23 01:42:48 PM PDT 24
Peak memory 230292 kb
Host smart-3e7c1950-2d1e-486a-bfad-d30e3b833d97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438324070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1438324070
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1590821219
Short name T312
Test name
Test status
Simulation time 3305715457 ps
CPU time 22.46 seconds
Started May 23 01:37:19 PM PDT 24
Finished May 23 01:37:45 PM PDT 24
Peak memory 215004 kb
Host smart-39850108-f342-4a7b-920e-6f0b634b078f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590821219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1590821219
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1643420578
Short name T263
Test name
Test status
Simulation time 186092134 ps
CPU time 10.26 seconds
Started May 23 01:37:18 PM PDT 24
Finished May 23 01:37:31 PM PDT 24
Peak memory 212312 kb
Host smart-af95e2e8-302a-4a02-96d6-ab6977ee4a16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1643420578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1643420578
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2422388380
Short name T7
Test name
Test status
Simulation time 2682620960 ps
CPU time 24.35 seconds
Started May 23 01:37:19 PM PDT 24
Finished May 23 01:37:46 PM PDT 24
Peak memory 217664 kb
Host smart-d3f9b0eb-42b6-4cbf-a50f-095d4a3597b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422388380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2422388380
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3966933815
Short name T185
Test name
Test status
Simulation time 2270714391 ps
CPU time 30.77 seconds
Started May 23 01:37:21 PM PDT 24
Finished May 23 01:37:54 PM PDT 24
Peak memory 219460 kb
Host smart-29ac5df9-785d-435c-b8ad-fc8df3960212
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966933815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3966933815
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3615398757
Short name T162
Test name
Test status
Simulation time 4221680124 ps
CPU time 28.03 seconds
Started May 23 01:37:17 PM PDT 24
Finished May 23 01:37:48 PM PDT 24
Peak memory 211436 kb
Host smart-181debb5-2c3a-47bb-9dfc-da09330cee2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615398757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3615398757
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3920881806
Short name T227
Test name
Test status
Simulation time 213551748819 ps
CPU time 441.73 seconds
Started May 23 01:37:17 PM PDT 24
Finished May 23 01:44:41 PM PDT 24
Peak memory 228740 kb
Host smart-162642bf-d721-4c17-8dbc-d1903a16a124
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920881806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3920881806
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1528992532
Short name T254
Test name
Test status
Simulation time 12652163679 ps
CPU time 55.89 seconds
Started May 23 01:37:18 PM PDT 24
Finished May 23 01:38:17 PM PDT 24
Peak memory 215216 kb
Host smart-6f319d52-8b94-49b4-90c2-557cab443c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528992532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1528992532
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2121213158
Short name T276
Test name
Test status
Simulation time 186002243 ps
CPU time 10.35 seconds
Started May 23 01:37:15 PM PDT 24
Finished May 23 01:37:29 PM PDT 24
Peak memory 212600 kb
Host smart-1a2fa39c-0b9d-4ac7-b30e-aeddb7027ad9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2121213158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2121213158
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3563586199
Short name T294
Test name
Test status
Simulation time 4481015208 ps
CPU time 28.2 seconds
Started May 23 01:37:19 PM PDT 24
Finished May 23 01:37:51 PM PDT 24
Peak memory 217720 kb
Host smart-3299191c-6b8d-4674-86a9-89680754d93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563586199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3563586199
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.298051901
Short name T67
Test name
Test status
Simulation time 83946689386 ps
CPU time 167.41 seconds
Started May 23 01:37:19 PM PDT 24
Finished May 23 01:40:09 PM PDT 24
Peak memory 219416 kb
Host smart-f96426e3-17b3-404d-b6b0-c33404974261
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298051901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.298051901
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1012221323
Short name T17
Test name
Test status
Simulation time 37818495685 ps
CPU time 742.11 seconds
Started May 23 01:37:16 PM PDT 24
Finished May 23 01:49:41 PM PDT 24
Peak memory 235940 kb
Host smart-7b4ce7d7-57b1-4247-88b3-cdb008e9ba45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012221323 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1012221323
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2029712915
Short name T157
Test name
Test status
Simulation time 7392561113 ps
CPU time 28.91 seconds
Started May 23 01:37:22 PM PDT 24
Finished May 23 01:37:52 PM PDT 24
Peak memory 212304 kb
Host smart-3c81cb5c-459f-4bdb-b257-3d2979acf1ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029712915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2029712915
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4243482607
Short name T253
Test name
Test status
Simulation time 67790976386 ps
CPU time 51.23 seconds
Started May 23 01:37:17 PM PDT 24
Finished May 23 01:38:12 PM PDT 24
Peak memory 215268 kb
Host smart-e1c316e3-9cbf-416e-aec7-bf7df154e4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243482607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.4243482607
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3348540519
Short name T218
Test name
Test status
Simulation time 32892081373 ps
CPU time 32.74 seconds
Started May 23 01:37:16 PM PDT 24
Finished May 23 01:37:52 PM PDT 24
Peak memory 211260 kb
Host smart-45f8392c-b92d-40f5-b848-4c018b476387
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3348540519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3348540519
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3541071732
Short name T147
Test name
Test status
Simulation time 1497348890 ps
CPU time 20.42 seconds
Started May 23 01:37:18 PM PDT 24
Finished May 23 01:37:41 PM PDT 24
Peak memory 217048 kb
Host smart-fc077000-2a9c-4de5-aeb1-b501fce0e1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541071732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3541071732
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.492904433
Short name T154
Test name
Test status
Simulation time 16427090633 ps
CPU time 65.94 seconds
Started May 23 01:37:15 PM PDT 24
Finished May 23 01:38:24 PM PDT 24
Peak memory 218984 kb
Host smart-df375f24-b081-4771-a345-94eab1798fb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492904433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.492904433
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.845770290
Short name T139
Test name
Test status
Simulation time 41013846833 ps
CPU time 34.68 seconds
Started May 23 01:37:19 PM PDT 24
Finished May 23 01:37:57 PM PDT 24
Peak memory 211896 kb
Host smart-9106a9b3-5b55-4a84-8bce-b33c39144be4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845770290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.845770290
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2349522792
Short name T232
Test name
Test status
Simulation time 32555508242 ps
CPU time 285.24 seconds
Started May 23 01:37:17 PM PDT 24
Finished May 23 01:42:05 PM PDT 24
Peak memory 229748 kb
Host smart-07a30004-b9db-4626-b5a7-39b81b5a076e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349522792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2349522792
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3116107309
Short name T275
Test name
Test status
Simulation time 11337755630 ps
CPU time 26.26 seconds
Started May 23 01:37:18 PM PDT 24
Finished May 23 01:37:48 PM PDT 24
Peak memory 211812 kb
Host smart-16e30518-9244-4017-8e04-d641fe594cb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3116107309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3116107309
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3357668088
Short name T283
Test name
Test status
Simulation time 1705257726 ps
CPU time 19.43 seconds
Started May 23 01:37:16 PM PDT 24
Finished May 23 01:37:38 PM PDT 24
Peak memory 216908 kb
Host smart-92c7c75d-91ad-4087-80bd-b76f6444c59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357668088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3357668088
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.802201200
Short name T21
Test name
Test status
Simulation time 4245460624 ps
CPU time 34.27 seconds
Started May 23 01:37:17 PM PDT 24
Finished May 23 01:37:54 PM PDT 24
Peak memory 213716 kb
Host smart-c3a41bcb-bf02-4c24-962d-52f3fe132fb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802201200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.802201200
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3417949354
Short name T149
Test name
Test status
Simulation time 12131465128 ps
CPU time 27.51 seconds
Started May 23 01:37:21 PM PDT 24
Finished May 23 01:37:51 PM PDT 24
Peak memory 212288 kb
Host smart-35285439-7987-4ba9-ad73-92274379ec08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417949354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3417949354
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.77934676
Short name T326
Test name
Test status
Simulation time 4192850819 ps
CPU time 276.33 seconds
Started May 23 01:37:17 PM PDT 24
Finished May 23 01:41:57 PM PDT 24
Peak memory 229824 kb
Host smart-b0ec251e-586a-4180-847e-b9e0cc3ddda7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77934676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_co
rrupt_sig_fatal_chk.77934676
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2330951498
Short name T267
Test name
Test status
Simulation time 24588069443 ps
CPU time 42.3 seconds
Started May 23 01:37:17 PM PDT 24
Finished May 23 01:38:03 PM PDT 24
Peak memory 214012 kb
Host smart-3d1d800b-c391-465d-b8d7-59cd6bb8e423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330951498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2330951498
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2280512703
Short name T344
Test name
Test status
Simulation time 16986004709 ps
CPU time 34.68 seconds
Started May 23 01:37:16 PM PDT 24
Finished May 23 01:37:53 PM PDT 24
Peak memory 211736 kb
Host smart-b2866755-a830-4f08-9979-d6ff48f732fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2280512703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2280512703
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3199075510
Short name T354
Test name
Test status
Simulation time 7033853358 ps
CPU time 70.27 seconds
Started May 23 01:37:17 PM PDT 24
Finished May 23 01:38:31 PM PDT 24
Peak memory 217188 kb
Host smart-f2079bb6-ce52-4f95-ba01-a5109f92738b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199075510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3199075510
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1019411668
Short name T340
Test name
Test status
Simulation time 11616133505 ps
CPU time 57.52 seconds
Started May 23 01:37:19 PM PDT 24
Finished May 23 01:38:20 PM PDT 24
Peak memory 219752 kb
Host smart-f7cedc57-edef-4802-abe3-b93fe96a9945
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019411668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1019411668
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1973446489
Short name T211
Test name
Test status
Simulation time 1582689391 ps
CPU time 18.25 seconds
Started May 23 01:37:21 PM PDT 24
Finished May 23 01:37:42 PM PDT 24
Peak memory 211828 kb
Host smart-dcb43171-1a15-4643-b3b7-e6c5d5e30f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973446489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1973446489
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.398424383
Short name T183
Test name
Test status
Simulation time 182734132751 ps
CPU time 535.3 seconds
Started May 23 01:37:19 PM PDT 24
Finished May 23 01:46:17 PM PDT 24
Peak memory 224776 kb
Host smart-d1e7397e-fa20-4d8d-ab9c-52c2fe833034
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398424383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.398424383
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3473729539
Short name T280
Test name
Test status
Simulation time 31405524123 ps
CPU time 63.6 seconds
Started May 23 01:37:19 PM PDT 24
Finished May 23 01:38:26 PM PDT 24
Peak memory 213800 kb
Host smart-1704d4f6-c13b-4047-b467-1187a0f72642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473729539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3473729539
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1507053868
Short name T181
Test name
Test status
Simulation time 2219290468 ps
CPU time 18.24 seconds
Started May 23 01:37:15 PM PDT 24
Finished May 23 01:37:36 PM PDT 24
Peak memory 212656 kb
Host smart-168ae99c-be10-4a52-a653-006ed6b33ecf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1507053868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1507053868
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2821432472
Short name T350
Test name
Test status
Simulation time 8547618252 ps
CPU time 46.89 seconds
Started May 23 01:37:20 PM PDT 24
Finished May 23 01:38:10 PM PDT 24
Peak memory 218640 kb
Host smart-e81acaa0-a774-4634-89a3-331d849c8948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821432472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2821432472
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3140767383
Short name T204
Test name
Test status
Simulation time 6078402943 ps
CPU time 48.87 seconds
Started May 23 01:37:18 PM PDT 24
Finished May 23 01:38:10 PM PDT 24
Peak memory 219892 kb
Host smart-fdf1b510-a05c-4ae7-9781-77f2a6d75030
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140767383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3140767383
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3223162030
Short name T134
Test name
Test status
Simulation time 612167666 ps
CPU time 8.54 seconds
Started May 23 01:37:24 PM PDT 24
Finished May 23 01:37:34 PM PDT 24
Peak memory 211400 kb
Host smart-c464a810-141a-43e4-beae-69e23d8d10ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223162030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3223162030
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2908024010
Short name T39
Test name
Test status
Simulation time 23002825225 ps
CPU time 375.64 seconds
Started May 23 01:37:25 PM PDT 24
Finished May 23 01:43:42 PM PDT 24
Peak memory 236636 kb
Host smart-a9bdaec2-2d57-4ad9-9260-586fd68ca804
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908024010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2908024010
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3440434931
Short name T126
Test name
Test status
Simulation time 24560497964 ps
CPU time 44.1 seconds
Started May 23 01:37:24 PM PDT 24
Finished May 23 01:38:10 PM PDT 24
Peak memory 215112 kb
Host smart-1685f804-6a21-4a11-9afc-1611aea954c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440434931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3440434931
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3499789212
Short name T261
Test name
Test status
Simulation time 704604813 ps
CPU time 13.41 seconds
Started May 23 01:37:24 PM PDT 24
Finished May 23 01:37:39 PM PDT 24
Peak memory 211248 kb
Host smart-97a9c1ed-250f-4efa-9d7f-035d3f3a2ee1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3499789212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3499789212
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2043855658
Short name T355
Test name
Test status
Simulation time 1436701160 ps
CPU time 20.26 seconds
Started May 23 01:37:19 PM PDT 24
Finished May 23 01:37:43 PM PDT 24
Peak memory 215560 kb
Host smart-8cd28b36-9dfc-45c9-bcbf-44ac67c41ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043855658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2043855658
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3502770916
Short name T78
Test name
Test status
Simulation time 8115295441 ps
CPU time 47.51 seconds
Started May 23 01:37:23 PM PDT 24
Finished May 23 01:38:13 PM PDT 24
Peak memory 213096 kb
Host smart-66692a13-2496-4567-97cf-84bbd533ae65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502770916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3502770916
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1191395537
Short name T352
Test name
Test status
Simulation time 1024591386 ps
CPU time 14.78 seconds
Started May 23 01:37:04 PM PDT 24
Finished May 23 01:37:23 PM PDT 24
Peak memory 211388 kb
Host smart-a6394bf3-b896-4e48-a1de-5ed157c18e4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191395537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1191395537
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2608634703
Short name T320
Test name
Test status
Simulation time 20587854946 ps
CPU time 281.37 seconds
Started May 23 01:36:56 PM PDT 24
Finished May 23 01:41:39 PM PDT 24
Peak memory 238892 kb
Host smart-2927a987-8c83-4bf8-bad1-fd725c3e19fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608634703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2608634703
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1500721303
Short name T201
Test name
Test status
Simulation time 2057657071 ps
CPU time 26.71 seconds
Started May 23 01:36:54 PM PDT 24
Finished May 23 01:37:24 PM PDT 24
Peak memory 214672 kb
Host smart-018f824e-4b75-4b17-b16b-f8e26e71a9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500721303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1500721303
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.868389421
Short name T242
Test name
Test status
Simulation time 425273846 ps
CPU time 13.16 seconds
Started May 23 01:36:56 PM PDT 24
Finished May 23 01:37:11 PM PDT 24
Peak memory 211240 kb
Host smart-4171c1f8-fc72-4d9f-a0d3-55d4cde7f302
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=868389421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.868389421
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.264600272
Short name T31
Test name
Test status
Simulation time 4614150355 ps
CPU time 117.79 seconds
Started May 23 01:37:06 PM PDT 24
Finished May 23 01:39:08 PM PDT 24
Peak memory 239504 kb
Host smart-6f03a8df-9f2f-49e7-9a75-afaed95df8dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264600272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.264600272
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.641435378
Short name T177
Test name
Test status
Simulation time 3051034377 ps
CPU time 20.71 seconds
Started May 23 01:37:03 PM PDT 24
Finished May 23 01:37:27 PM PDT 24
Peak memory 217956 kb
Host smart-100fbc10-c943-4675-8786-0d77947cfc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641435378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.641435378
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2751615651
Short name T186
Test name
Test status
Simulation time 70408139937 ps
CPU time 155.1 seconds
Started May 23 01:36:53 PM PDT 24
Finished May 23 01:39:32 PM PDT 24
Peak memory 222740 kb
Host smart-5b59cd9e-a837-4fb9-95ac-5fa98662a9c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751615651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2751615651
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3079774321
Short name T273
Test name
Test status
Simulation time 2522992816 ps
CPU time 17.07 seconds
Started May 23 01:37:27 PM PDT 24
Finished May 23 01:37:46 PM PDT 24
Peak memory 211520 kb
Host smart-c314984f-9837-487c-a31e-84ff2d8e3c37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079774321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3079774321
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3077679868
Short name T272
Test name
Test status
Simulation time 15030510366 ps
CPU time 230.02 seconds
Started May 23 01:37:28 PM PDT 24
Finished May 23 01:41:20 PM PDT 24
Peak memory 239968 kb
Host smart-729a6c31-f6b9-4e51-9a37-d01f688dea82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077679868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3077679868
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3467187802
Short name T8
Test name
Test status
Simulation time 509957801 ps
CPU time 19.27 seconds
Started May 23 01:37:28 PM PDT 24
Finished May 23 01:37:50 PM PDT 24
Peak memory 214908 kb
Host smart-a6eba0a2-238c-40f5-81da-cc770a395920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467187802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3467187802
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.4031961880
Short name T197
Test name
Test status
Simulation time 4202929872 ps
CPU time 33.84 seconds
Started May 23 01:37:27 PM PDT 24
Finished May 23 01:38:03 PM PDT 24
Peak memory 211296 kb
Host smart-0c798ca8-87b1-4f6e-a1d6-e3878d779567
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4031961880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.4031961880
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3670943121
Short name T11
Test name
Test status
Simulation time 59854959380 ps
CPU time 66.93 seconds
Started May 23 01:37:27 PM PDT 24
Finished May 23 01:38:36 PM PDT 24
Peak memory 215136 kb
Host smart-d6d9640a-e3ed-4900-8150-0f3b36302954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670943121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3670943121
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1317885391
Short name T94
Test name
Test status
Simulation time 418943802 ps
CPU time 21.36 seconds
Started May 23 01:37:29 PM PDT 24
Finished May 23 01:37:53 PM PDT 24
Peak memory 217988 kb
Host smart-744ea313-5553-48cc-895b-df74509a8610
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317885391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1317885391
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3974273797
Short name T165
Test name
Test status
Simulation time 23895849251 ps
CPU time 32.96 seconds
Started May 23 01:37:27 PM PDT 24
Finished May 23 01:38:01 PM PDT 24
Peak memory 212248 kb
Host smart-f7006f7b-d379-4325-8040-d23630497514
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974273797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3974273797
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3512789384
Short name T247
Test name
Test status
Simulation time 33495027494 ps
CPU time 223.74 seconds
Started May 23 01:37:29 PM PDT 24
Finished May 23 01:41:15 PM PDT 24
Peak memory 237992 kb
Host smart-1ff5f066-d7b8-4801-a09c-88f1b0bafa29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512789384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3512789384
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1946493342
Short name T24
Test name
Test status
Simulation time 957031252 ps
CPU time 24.34 seconds
Started May 23 01:37:27 PM PDT 24
Finished May 23 01:37:53 PM PDT 24
Peak memory 214720 kb
Host smart-0d8ecdc3-2532-4f6f-9872-1d3fcfb376cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946493342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1946493342
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2355794132
Short name T303
Test name
Test status
Simulation time 3046727323 ps
CPU time 27.61 seconds
Started May 23 01:37:28 PM PDT 24
Finished May 23 01:37:57 PM PDT 24
Peak memory 211360 kb
Host smart-15929621-9400-4808-8a8f-02b66e1474a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2355794132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2355794132
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.994196140
Short name T209
Test name
Test status
Simulation time 37616728468 ps
CPU time 59.82 seconds
Started May 23 01:37:28 PM PDT 24
Finished May 23 01:38:30 PM PDT 24
Peak memory 215924 kb
Host smart-b1298f1f-24a1-4f7e-9903-e77eb550257c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994196140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.994196140
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3787279542
Short name T180
Test name
Test status
Simulation time 5461898443 ps
CPU time 63.03 seconds
Started May 23 01:37:28 PM PDT 24
Finished May 23 01:38:33 PM PDT 24
Peak memory 221360 kb
Host smart-40d0f150-4f7f-4195-9442-ee0bbce72b9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787279542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3787279542
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1292167305
Short name T9
Test name
Test status
Simulation time 2746455238 ps
CPU time 8.49 seconds
Started May 23 01:37:30 PM PDT 24
Finished May 23 01:37:41 PM PDT 24
Peak memory 211524 kb
Host smart-00d62fa1-09a3-442a-b494-35a42eb2d218
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292167305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1292167305
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3282465534
Short name T240
Test name
Test status
Simulation time 5743158203 ps
CPU time 224.78 seconds
Started May 23 01:37:28 PM PDT 24
Finished May 23 01:41:14 PM PDT 24
Peak memory 237964 kb
Host smart-ca9a57bf-56e0-4058-9618-4a2af9714f86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282465534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3282465534
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3455034995
Short name T158
Test name
Test status
Simulation time 10808981501 ps
CPU time 50.74 seconds
Started May 23 01:37:30 PM PDT 24
Finished May 23 01:38:23 PM PDT 24
Peak memory 215036 kb
Host smart-0b7345b5-288d-4e71-bf84-4569c5b21e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455034995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3455034995
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1446757715
Short name T208
Test name
Test status
Simulation time 1991739156 ps
CPU time 21.34 seconds
Started May 23 01:37:27 PM PDT 24
Finished May 23 01:37:50 PM PDT 24
Peak memory 211208 kb
Host smart-c066b782-8539-423e-a8cd-c03eb241f991
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1446757715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1446757715
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.149255750
Short name T35
Test name
Test status
Simulation time 7172547857 ps
CPU time 69.62 seconds
Started May 23 01:37:28 PM PDT 24
Finished May 23 01:38:39 PM PDT 24
Peak memory 217276 kb
Host smart-db8f5118-78ab-4855-aab1-5ae91f9db377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149255750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.149255750
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3310484193
Short name T148
Test name
Test status
Simulation time 16415273817 ps
CPU time 137.67 seconds
Started May 23 01:37:26 PM PDT 24
Finished May 23 01:39:45 PM PDT 24
Peak memory 221140 kb
Host smart-2de0a59c-f0ff-4517-bb03-df619aec52a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310484193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3310484193
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1351217086
Short name T59
Test name
Test status
Simulation time 3768958784 ps
CPU time 30.24 seconds
Started May 23 01:37:29 PM PDT 24
Finished May 23 01:38:02 PM PDT 24
Peak memory 211968 kb
Host smart-248b3926-7edd-41ee-b301-dc54c7c428cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351217086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1351217086
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2827118901
Short name T178
Test name
Test status
Simulation time 53734378038 ps
CPU time 336.6 seconds
Started May 23 01:37:30 PM PDT 24
Finished May 23 01:43:10 PM PDT 24
Peak memory 240460 kb
Host smart-a923259e-9159-4604-86e4-045b279cbc90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827118901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2827118901
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3512458907
Short name T300
Test name
Test status
Simulation time 6485421850 ps
CPU time 58.35 seconds
Started May 23 01:37:29 PM PDT 24
Finished May 23 01:38:29 PM PDT 24
Peak memory 215140 kb
Host smart-ece9422e-17e4-46d9-a0b8-ff14c21fa46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512458907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3512458907
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3417065339
Short name T125
Test name
Test status
Simulation time 7326143130 ps
CPU time 36 seconds
Started May 23 01:37:30 PM PDT 24
Finished May 23 01:38:09 PM PDT 24
Peak memory 211720 kb
Host smart-a459fcd3-8350-4cfd-9ee8-28b197a2f460
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3417065339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3417065339
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1421893758
Short name T66
Test name
Test status
Simulation time 11521635572 ps
CPU time 60.71 seconds
Started May 23 01:37:29 PM PDT 24
Finished May 23 01:38:33 PM PDT 24
Peak memory 217872 kb
Host smart-3345c293-aeba-4cf5-8072-c36798a0a504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421893758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1421893758
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2458788051
Short name T132
Test name
Test status
Simulation time 9617264343 ps
CPU time 82.54 seconds
Started May 23 01:37:30 PM PDT 24
Finished May 23 01:38:55 PM PDT 24
Peak memory 219384 kb
Host smart-eade865d-343b-4036-bbb7-e1d1ed2ffcee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458788051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2458788051
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.951165662
Short name T57
Test name
Test status
Simulation time 6502948285 ps
CPU time 29.43 seconds
Started May 23 01:37:30 PM PDT 24
Finished May 23 01:38:02 PM PDT 24
Peak memory 212272 kb
Host smart-937ab437-ddaf-4a73-9d9a-942566b68f87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951165662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.951165662
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1614433442
Short name T15
Test name
Test status
Simulation time 59443082082 ps
CPU time 401.25 seconds
Started May 23 01:37:30 PM PDT 24
Finished May 23 01:44:14 PM PDT 24
Peak memory 240876 kb
Host smart-5daec07e-5bef-4b28-ba81-088fc8e69b1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614433442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1614433442
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3806992739
Short name T25
Test name
Test status
Simulation time 5427930563 ps
CPU time 49.5 seconds
Started May 23 01:37:31 PM PDT 24
Finished May 23 01:38:23 PM PDT 24
Peak memory 215080 kb
Host smart-c2ec4f8e-2656-4d1d-9807-5405212ebf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806992739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3806992739
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3994114380
Short name T293
Test name
Test status
Simulation time 4657037408 ps
CPU time 24.69 seconds
Started May 23 01:37:30 PM PDT 24
Finished May 23 01:37:57 PM PDT 24
Peak memory 212920 kb
Host smart-70a71ae2-0807-4090-a5b0-86fad723155e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3994114380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3994114380
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2858924775
Short name T264
Test name
Test status
Simulation time 1046320687 ps
CPU time 20.03 seconds
Started May 23 01:37:30 PM PDT 24
Finished May 23 01:37:53 PM PDT 24
Peak memory 217420 kb
Host smart-913bea92-01db-49f3-9236-22db71cd1191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858924775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2858924775
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2832696443
Short name T118
Test name
Test status
Simulation time 7646545813 ps
CPU time 30.01 seconds
Started May 23 01:37:29 PM PDT 24
Finished May 23 01:38:01 PM PDT 24
Peak memory 213404 kb
Host smart-2cd49c12-cf89-4c6c-9987-93ed521568b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832696443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2832696443
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1719288548
Short name T1
Test name
Test status
Simulation time 2627514696 ps
CPU time 16.66 seconds
Started May 23 01:37:44 PM PDT 24
Finished May 23 01:38:04 PM PDT 24
Peak memory 211524 kb
Host smart-99f23576-0c0c-4e0f-8796-425247f4ed4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719288548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1719288548
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1076949997
Short name T357
Test name
Test status
Simulation time 383044387654 ps
CPU time 683.34 seconds
Started May 23 01:37:30 PM PDT 24
Finished May 23 01:48:56 PM PDT 24
Peak memory 237888 kb
Host smart-e4d7c1a4-66f3-40bd-bf91-9f8dd2a45f8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076949997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1076949997
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1964854771
Short name T331
Test name
Test status
Simulation time 6767379407 ps
CPU time 36.19 seconds
Started May 23 01:37:29 PM PDT 24
Finished May 23 01:38:08 PM PDT 24
Peak memory 214868 kb
Host smart-494e4342-46b9-4da1-9c7b-adcc4786c85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964854771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1964854771
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3419033509
Short name T119
Test name
Test status
Simulation time 3497388105 ps
CPU time 30.2 seconds
Started May 23 01:37:44 PM PDT 24
Finished May 23 01:38:17 PM PDT 24
Peak memory 212288 kb
Host smart-0b565fb8-6577-44e5-bdff-87042a6b49e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3419033509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3419033509
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.311457505
Short name T213
Test name
Test status
Simulation time 17153661943 ps
CPU time 47.43 seconds
Started May 23 01:37:44 PM PDT 24
Finished May 23 01:38:35 PM PDT 24
Peak memory 216884 kb
Host smart-60d902c9-0790-460f-9c38-dacd1aa222cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311457505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.311457505
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.551274186
Short name T306
Test name
Test status
Simulation time 76241009377 ps
CPU time 88.78 seconds
Started May 23 01:37:32 PM PDT 24
Finished May 23 01:39:03 PM PDT 24
Peak memory 217320 kb
Host smart-e983bf8c-2bba-428b-b989-643187f76945
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551274186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.551274186
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1251182216
Short name T222
Test name
Test status
Simulation time 3500082618 ps
CPU time 19.97 seconds
Started May 23 01:37:31 PM PDT 24
Finished May 23 01:37:53 PM PDT 24
Peak memory 211572 kb
Host smart-3163ea2a-cbb0-4f19-9fe7-dce3d0864e3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251182216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1251182216
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1464563094
Short name T28
Test name
Test status
Simulation time 7876921682 ps
CPU time 244.99 seconds
Started May 23 01:37:31 PM PDT 24
Finished May 23 01:41:38 PM PDT 24
Peak memory 219388 kb
Host smart-a9c672b8-f7e3-45e6-9cbb-c3d10e76344b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464563094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1464563094
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4077566693
Short name T6
Test name
Test status
Simulation time 3465052247 ps
CPU time 42.16 seconds
Started May 23 01:37:32 PM PDT 24
Finished May 23 01:38:16 PM PDT 24
Peak memory 214764 kb
Host smart-a7d63a48-b523-471a-b526-e37d2b5255b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077566693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4077566693
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3022327966
Short name T142
Test name
Test status
Simulation time 615856394 ps
CPU time 14.43 seconds
Started May 23 01:37:30 PM PDT 24
Finished May 23 01:37:47 PM PDT 24
Peak memory 211308 kb
Host smart-2f3cfa0c-2b43-4714-b1f8-e195990f7254
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3022327966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3022327966
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2688440819
Short name T285
Test name
Test status
Simulation time 344928548 ps
CPU time 19.86 seconds
Started May 23 01:37:44 PM PDT 24
Finished May 23 01:38:07 PM PDT 24
Peak memory 216408 kb
Host smart-c3dd522f-eb63-42ea-9f0f-c54630749bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688440819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2688440819
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1222046561
Short name T334
Test name
Test status
Simulation time 70376047413 ps
CPU time 62.89 seconds
Started May 23 01:37:30 PM PDT 24
Finished May 23 01:38:36 PM PDT 24
Peak memory 218156 kb
Host smart-00713650-0c42-4f96-8acc-393a53583654
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222046561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1222046561
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.955202795
Short name T259
Test name
Test status
Simulation time 63658129713 ps
CPU time 28.44 seconds
Started May 23 01:37:29 PM PDT 24
Finished May 23 01:38:00 PM PDT 24
Peak memory 212184 kb
Host smart-55c5f66d-85fe-4448-b842-89a6b31c4853
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955202795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.955202795
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1656106117
Short name T292
Test name
Test status
Simulation time 15298986988 ps
CPU time 255.35 seconds
Started May 23 01:37:44 PM PDT 24
Finished May 23 01:42:03 PM PDT 24
Peak memory 240392 kb
Host smart-eb73cbfa-345a-4703-8b6c-02ff24ebf9b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656106117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1656106117
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3375644266
Short name T266
Test name
Test status
Simulation time 6545890810 ps
CPU time 38.74 seconds
Started May 23 01:37:30 PM PDT 24
Finished May 23 01:38:11 PM PDT 24
Peak memory 215472 kb
Host smart-996f2d21-67f2-4f56-8bd1-8617f32fb0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375644266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3375644266
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3716211626
Short name T327
Test name
Test status
Simulation time 13598131659 ps
CPU time 54.85 seconds
Started May 23 01:37:30 PM PDT 24
Finished May 23 01:38:27 PM PDT 24
Peak memory 218228 kb
Host smart-482e3ef1-6225-4788-894a-407d47d8b0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716211626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3716211626
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1306446625
Short name T319
Test name
Test status
Simulation time 866753743 ps
CPU time 56.32 seconds
Started May 23 01:37:44 PM PDT 24
Finished May 23 01:38:44 PM PDT 24
Peak memory 219336 kb
Host smart-ab66b10d-ba8c-419b-b575-c03253057378
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306446625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1306446625
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3162120047
Short name T237
Test name
Test status
Simulation time 2745969301 ps
CPU time 13.17 seconds
Started May 23 01:37:38 PM PDT 24
Finished May 23 01:37:53 PM PDT 24
Peak memory 211508 kb
Host smart-de5d7fef-aa05-43fd-bd54-6a7192c43cd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162120047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3162120047
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.4104612826
Short name T173
Test name
Test status
Simulation time 138534108579 ps
CPU time 607.85 seconds
Started May 23 01:37:41 PM PDT 24
Finished May 23 01:47:53 PM PDT 24
Peak memory 234044 kb
Host smart-3111eb26-5241-4be8-83dc-b69cb47334ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104612826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.4104612826
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2768613214
Short name T140
Test name
Test status
Simulation time 6107363753 ps
CPU time 55.93 seconds
Started May 23 01:37:41 PM PDT 24
Finished May 23 01:38:41 PM PDT 24
Peak memory 214008 kb
Host smart-8913a8f8-38aa-4075-ac87-08457b115bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768613214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2768613214
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1239262952
Short name T63
Test name
Test status
Simulation time 705568123 ps
CPU time 10.65 seconds
Started May 23 01:37:39 PM PDT 24
Finished May 23 01:37:51 PM PDT 24
Peak memory 212540 kb
Host smart-bd5a1495-15b7-45ba-93c7-68f529542b89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1239262952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1239262952
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2574401656
Short name T22
Test name
Test status
Simulation time 21475169694 ps
CPU time 74.19 seconds
Started May 23 01:37:29 PM PDT 24
Finished May 23 01:38:46 PM PDT 24
Peak memory 217192 kb
Host smart-5c1d84ae-eb0c-4214-a69e-df8c9d445588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574401656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2574401656
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1670360462
Short name T91
Test name
Test status
Simulation time 7205856555 ps
CPU time 34.81 seconds
Started May 23 01:37:42 PM PDT 24
Finished May 23 01:38:21 PM PDT 24
Peak memory 213412 kb
Host smart-6b9cb70a-a68e-4018-9024-aa027b390759
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670360462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1670360462
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2960851084
Short name T56
Test name
Test status
Simulation time 2227868383 ps
CPU time 21.85 seconds
Started May 23 01:37:40 PM PDT 24
Finished May 23 01:38:06 PM PDT 24
Peak memory 211908 kb
Host smart-3faaf193-beb6-4756-a817-b6e1fde68127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960851084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2960851084
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1596818703
Short name T249
Test name
Test status
Simulation time 137866699168 ps
CPU time 684.96 seconds
Started May 23 01:37:39 PM PDT 24
Finished May 23 01:49:07 PM PDT 24
Peak memory 216948 kb
Host smart-699e1fe4-ef21-4fe6-a742-cb6bea28fc16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596818703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1596818703
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.252384002
Short name T309
Test name
Test status
Simulation time 6991753245 ps
CPU time 60.88 seconds
Started May 23 01:37:39 PM PDT 24
Finished May 23 01:38:41 PM PDT 24
Peak memory 215028 kb
Host smart-9d519f8b-9c35-42ce-967f-22658288b862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252384002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.252384002
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3496781173
Short name T161
Test name
Test status
Simulation time 4986309625 ps
CPU time 25.04 seconds
Started May 23 01:37:41 PM PDT 24
Finished May 23 01:38:10 PM PDT 24
Peak memory 211772 kb
Host smart-69cb0a2b-fc7c-45ea-a196-0069b6790d00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3496781173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3496781173
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1531441312
Short name T295
Test name
Test status
Simulation time 8210195093 ps
CPU time 63.73 seconds
Started May 23 01:37:41 PM PDT 24
Finished May 23 01:38:48 PM PDT 24
Peak memory 218124 kb
Host smart-6f819931-6ba0-4e2e-8cc2-f73e9fd14cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531441312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1531441312
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2394025914
Short name T230
Test name
Test status
Simulation time 13089005707 ps
CPU time 44.8 seconds
Started May 23 01:37:39 PM PDT 24
Finished May 23 01:38:26 PM PDT 24
Peak memory 216188 kb
Host smart-70e636cd-41ae-447f-ad81-fd7f8bf1f8d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394025914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2394025914
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1824589345
Short name T234
Test name
Test status
Simulation time 22002114033 ps
CPU time 30.13 seconds
Started May 23 01:37:06 PM PDT 24
Finished May 23 01:37:41 PM PDT 24
Peak memory 211496 kb
Host smart-2631b0d2-2a73-4bf9-9c7a-7a00b3aab4aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824589345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1824589345
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4281678575
Short name T335
Test name
Test status
Simulation time 149777058938 ps
CPU time 758.36 seconds
Started May 23 01:37:03 PM PDT 24
Finished May 23 01:49:45 PM PDT 24
Peak memory 238640 kb
Host smart-8158772e-54a1-4767-815d-2d6a97f0cf7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281678575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.4281678575
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.601484599
Short name T199
Test name
Test status
Simulation time 680763188 ps
CPU time 24.68 seconds
Started May 23 01:37:04 PM PDT 24
Finished May 23 01:37:32 PM PDT 24
Peak memory 214780 kb
Host smart-2592031a-1c25-4945-931e-1d0f82f1e2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601484599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.601484599
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3553730180
Short name T194
Test name
Test status
Simulation time 34399247494 ps
CPU time 32.17 seconds
Started May 23 01:37:04 PM PDT 24
Finished May 23 01:37:39 PM PDT 24
Peak memory 211732 kb
Host smart-b420e73c-cf00-4a21-9f84-7b7da8f0a576
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3553730180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3553730180
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.879712645
Short name T30
Test name
Test status
Simulation time 898830255 ps
CPU time 120.94 seconds
Started May 23 01:37:05 PM PDT 24
Finished May 23 01:39:10 PM PDT 24
Peak memory 237412 kb
Host smart-50a29b56-59f2-4f98-88d6-4707c2ac4425
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879712645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.879712645
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2521928361
Short name T36
Test name
Test status
Simulation time 519451250 ps
CPU time 22.76 seconds
Started May 23 01:37:05 PM PDT 24
Finished May 23 01:37:32 PM PDT 24
Peak memory 216832 kb
Host smart-2c0a7b77-a328-4582-8d80-7a570e323baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521928361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2521928361
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3020432701
Short name T215
Test name
Test status
Simulation time 17037040312 ps
CPU time 106.25 seconds
Started May 23 01:37:03 PM PDT 24
Finished May 23 01:38:53 PM PDT 24
Peak memory 219452 kb
Host smart-50606477-0be9-4e59-8929-ff283facdb77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020432701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3020432701
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1479498199
Short name T58
Test name
Test status
Simulation time 2747741088 ps
CPU time 11.93 seconds
Started May 23 01:37:39 PM PDT 24
Finished May 23 01:37:53 PM PDT 24
Peak memory 211520 kb
Host smart-4bd572a2-a644-430f-acbc-496a58ab3e65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479498199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1479498199
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1878161012
Short name T212
Test name
Test status
Simulation time 3662786077 ps
CPU time 265.34 seconds
Started May 23 01:37:41 PM PDT 24
Finished May 23 01:42:11 PM PDT 24
Peak memory 240408 kb
Host smart-de496032-e2bc-4ef3-adbd-0da2043ff4a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878161012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1878161012
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1475067592
Short name T349
Test name
Test status
Simulation time 332604905 ps
CPU time 19.48 seconds
Started May 23 01:37:41 PM PDT 24
Finished May 23 01:38:05 PM PDT 24
Peak memory 214712 kb
Host smart-45011a85-47cf-4a0b-8174-674a1ac12ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475067592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1475067592
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2464953572
Short name T171
Test name
Test status
Simulation time 2605831978 ps
CPU time 25.12 seconds
Started May 23 01:37:40 PM PDT 24
Finished May 23 01:38:09 PM PDT 24
Peak memory 211372 kb
Host smart-f45b9b28-0341-4946-95b7-4522b71eb836
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2464953572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2464953572
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2171490093
Short name T241
Test name
Test status
Simulation time 65808707070 ps
CPU time 60.33 seconds
Started May 23 01:37:39 PM PDT 24
Finished May 23 01:38:42 PM PDT 24
Peak memory 218040 kb
Host smart-b946260a-fd85-4f1a-9bcf-8873139e6f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171490093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2171490093
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1158509518
Short name T353
Test name
Test status
Simulation time 7852153079 ps
CPU time 67.74 seconds
Started May 23 01:37:40 PM PDT 24
Finished May 23 01:38:52 PM PDT 24
Peak memory 218104 kb
Host smart-32a33a77-13b8-4d5d-b7c6-ffad99921df2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158509518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1158509518
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.376513292
Short name T135
Test name
Test status
Simulation time 174303822 ps
CPU time 8.57 seconds
Started May 23 01:37:41 PM PDT 24
Finished May 23 01:37:52 PM PDT 24
Peak memory 211368 kb
Host smart-74a5c08a-b70f-45ac-95be-0d5d5d651003
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376513292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.376513292
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2694601642
Short name T43
Test name
Test status
Simulation time 117823932731 ps
CPU time 374.68 seconds
Started May 23 01:37:42 PM PDT 24
Finished May 23 01:44:00 PM PDT 24
Peak memory 240792 kb
Host smart-f2ea2fe0-f30c-4e93-a9a9-00fe065a63e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694601642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2694601642
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1795000280
Short name T298
Test name
Test status
Simulation time 1376719771 ps
CPU time 19.01 seconds
Started May 23 01:37:42 PM PDT 24
Finished May 23 01:38:05 PM PDT 24
Peak memory 214792 kb
Host smart-d609412c-c9b5-46a6-9632-a7cbdf365c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795000280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1795000280
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3619230426
Short name T315
Test name
Test status
Simulation time 713506528 ps
CPU time 10.18 seconds
Started May 23 01:37:41 PM PDT 24
Finished May 23 01:37:55 PM PDT 24
Peak memory 212516 kb
Host smart-1713f2be-0555-496f-8548-06f6e9fce5c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3619230426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3619230426
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1531073151
Short name T79
Test name
Test status
Simulation time 18747891744 ps
CPU time 75.72 seconds
Started May 23 01:37:41 PM PDT 24
Finished May 23 01:39:01 PM PDT 24
Peak memory 217384 kb
Host smart-3f21942b-8933-49e5-a9c2-52c1485c53aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531073151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1531073151
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.966496926
Short name T258
Test name
Test status
Simulation time 9032285888 ps
CPU time 30.23 seconds
Started May 23 01:37:40 PM PDT 24
Finished May 23 01:38:13 PM PDT 24
Peak memory 213920 kb
Host smart-f71c13ae-b4a0-41f9-b42f-a621564af806
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966496926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.966496926
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1599851636
Short name T243
Test name
Test status
Simulation time 3761747764 ps
CPU time 30.43 seconds
Started May 23 01:37:53 PM PDT 24
Finished May 23 01:38:31 PM PDT 24
Peak memory 212064 kb
Host smart-d0fc4783-4f41-4370-ac67-43c8c5d86d69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599851636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1599851636
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3296456183
Short name T216
Test name
Test status
Simulation time 3762864572 ps
CPU time 43.03 seconds
Started May 23 01:37:52 PM PDT 24
Finished May 23 01:38:41 PM PDT 24
Peak memory 214776 kb
Host smart-294e9b91-3b2a-445a-996e-a8134739b63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296456183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3296456183
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2487652037
Short name T288
Test name
Test status
Simulation time 2094783633 ps
CPU time 13.12 seconds
Started May 23 01:37:57 PM PDT 24
Finished May 23 01:38:16 PM PDT 24
Peak memory 212308 kb
Host smart-2d68308f-5a44-44e3-aa9e-ee0cd040041a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2487652037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2487652037
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2889482654
Short name T302
Test name
Test status
Simulation time 3401145417 ps
CPU time 19.71 seconds
Started May 23 01:37:39 PM PDT 24
Finished May 23 01:38:00 PM PDT 24
Peak memory 217196 kb
Host smart-f0c241a7-3c4a-4a6a-bce9-0c81eb239dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889482654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2889482654
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3648243463
Short name T342
Test name
Test status
Simulation time 23131454135 ps
CPU time 102.27 seconds
Started May 23 01:37:53 PM PDT 24
Finished May 23 01:39:42 PM PDT 24
Peak memory 219452 kb
Host smart-051dbbe3-7da1-4e6e-889a-c6c18da2c7ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648243463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3648243463
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3170067691
Short name T268
Test name
Test status
Simulation time 39004864519 ps
CPU time 30.37 seconds
Started May 23 01:37:55 PM PDT 24
Finished May 23 01:38:32 PM PDT 24
Peak memory 212244 kb
Host smart-57699213-3219-4393-b776-02ff6d9af0e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170067691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3170067691
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.821013476
Short name T314
Test name
Test status
Simulation time 3609210532 ps
CPU time 104.28 seconds
Started May 23 01:37:54 PM PDT 24
Finished May 23 01:39:46 PM PDT 24
Peak memory 218604 kb
Host smart-6eabe64c-3108-475f-bda4-a72c60c9a916
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821013476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.821013476
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3557970691
Short name T271
Test name
Test status
Simulation time 828509011 ps
CPU time 26.16 seconds
Started May 23 01:37:54 PM PDT 24
Finished May 23 01:38:28 PM PDT 24
Peak memory 214672 kb
Host smart-8f39f9c7-126f-4e8d-90f1-95606400a751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557970691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3557970691
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3157502620
Short name T196
Test name
Test status
Simulation time 2479161792 ps
CPU time 25.14 seconds
Started May 23 01:37:53 PM PDT 24
Finished May 23 01:38:26 PM PDT 24
Peak memory 211392 kb
Host smart-fbd50493-e74b-4dbf-91d2-9371c1908f67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3157502620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3157502620
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3638515290
Short name T260
Test name
Test status
Simulation time 7575139058 ps
CPU time 40.59 seconds
Started May 23 01:37:58 PM PDT 24
Finished May 23 01:38:44 PM PDT 24
Peak memory 217536 kb
Host smart-fb36504b-6708-4320-baa0-8410de0d5c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638515290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3638515290
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2517052310
Short name T205
Test name
Test status
Simulation time 1880124978 ps
CPU time 25.65 seconds
Started May 23 01:37:54 PM PDT 24
Finished May 23 01:38:27 PM PDT 24
Peak memory 211416 kb
Host smart-108ed059-9870-4600-b909-2b302ab1af0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517052310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2517052310
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3773840680
Short name T321
Test name
Test status
Simulation time 4760111797 ps
CPU time 22.22 seconds
Started May 23 01:37:54 PM PDT 24
Finished May 23 01:38:24 PM PDT 24
Peak memory 212452 kb
Host smart-bc2480b2-3b87-4a1c-bf25-9478b5b001a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773840680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3773840680
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.81235598
Short name T153
Test name
Test status
Simulation time 25651698478 ps
CPU time 146.49 seconds
Started May 23 01:37:53 PM PDT 24
Finished May 23 01:40:26 PM PDT 24
Peak memory 229756 kb
Host smart-03a90a8f-dd3a-4549-ad42-855e1aae38ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81235598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_co
rrupt_sig_fatal_chk.81235598
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3295200186
Short name T233
Test name
Test status
Simulation time 346603586 ps
CPU time 19.69 seconds
Started May 23 01:37:55 PM PDT 24
Finished May 23 01:38:21 PM PDT 24
Peak memory 215120 kb
Host smart-d870779d-be37-4b85-9d17-88aaad90ae84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295200186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3295200186
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3763700329
Short name T145
Test name
Test status
Simulation time 728363044 ps
CPU time 10.32 seconds
Started May 23 01:37:58 PM PDT 24
Finished May 23 01:38:14 PM PDT 24
Peak memory 212444 kb
Host smart-dcb83828-4b08-4be9-bd76-c2b48a6c6526
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3763700329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3763700329
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3885084220
Short name T92
Test name
Test status
Simulation time 1433457760 ps
CPU time 19.73 seconds
Started May 23 01:37:57 PM PDT 24
Finished May 23 01:38:23 PM PDT 24
Peak memory 216724 kb
Host smart-1c205431-70c4-46bc-9e08-c4dc067f4dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885084220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3885084220
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.4113394008
Short name T133
Test name
Test status
Simulation time 556381577 ps
CPU time 29.77 seconds
Started May 23 01:37:55 PM PDT 24
Finished May 23 01:38:32 PM PDT 24
Peak memory 219224 kb
Host smart-a4954fc7-3720-4b80-ab51-ee63f16e14bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113394008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.4113394008
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1114646028
Short name T238
Test name
Test status
Simulation time 7154657155 ps
CPU time 29.07 seconds
Started May 23 01:37:53 PM PDT 24
Finished May 23 01:38:29 PM PDT 24
Peak memory 211736 kb
Host smart-86b7eec4-aae4-4d2e-962d-e717bde1569b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114646028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1114646028
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2314213375
Short name T95
Test name
Test status
Simulation time 895083262989 ps
CPU time 467.69 seconds
Started May 23 01:37:54 PM PDT 24
Finished May 23 01:45:49 PM PDT 24
Peak memory 240824 kb
Host smart-09e1cee5-ff45-4f17-bab3-58d5ebedfc06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314213375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2314213375
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1327358784
Short name T164
Test name
Test status
Simulation time 2173912141 ps
CPU time 33.97 seconds
Started May 23 01:37:54 PM PDT 24
Finished May 23 01:38:35 PM PDT 24
Peak memory 213804 kb
Host smart-24311f4c-e846-4f56-bc6a-7956d23385b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327358784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1327358784
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3120616778
Short name T332
Test name
Test status
Simulation time 1944601541 ps
CPU time 19.6 seconds
Started May 23 01:37:56 PM PDT 24
Finished May 23 01:38:22 PM PDT 24
Peak memory 212116 kb
Host smart-d9969169-a96c-4513-ac67-2e820267dab7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3120616778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3120616778
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1235028103
Short name T286
Test name
Test status
Simulation time 23207502402 ps
CPU time 51.88 seconds
Started May 23 01:37:53 PM PDT 24
Finished May 23 01:38:52 PM PDT 24
Peak memory 216896 kb
Host smart-eabf243d-40af-4187-ab5a-6fbd1822e63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235028103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1235028103
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.223942549
Short name T122
Test name
Test status
Simulation time 27075292783 ps
CPU time 96.81 seconds
Started May 23 01:37:53 PM PDT 24
Finished May 23 01:39:36 PM PDT 24
Peak memory 219872 kb
Host smart-d2c8ef08-0178-49f2-a47a-d7aaa0c4e036
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223942549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.223942549
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2293832350
Short name T174
Test name
Test status
Simulation time 5466873879 ps
CPU time 16.21 seconds
Started May 23 01:37:53 PM PDT 24
Finished May 23 01:38:17 PM PDT 24
Peak memory 211472 kb
Host smart-15aff601-e9f2-47ba-9a93-47d1a17fd59b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293832350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2293832350
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2599682113
Short name T207
Test name
Test status
Simulation time 35868604850 ps
CPU time 274.69 seconds
Started May 23 01:37:53 PM PDT 24
Finished May 23 01:42:34 PM PDT 24
Peak memory 237984 kb
Host smart-2dca534c-4f15-444d-8ea4-b447ecd3dc7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599682113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2599682113
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1349784471
Short name T228
Test name
Test status
Simulation time 30241233597 ps
CPU time 63.35 seconds
Started May 23 01:37:56 PM PDT 24
Finished May 23 01:39:05 PM PDT 24
Peak memory 215260 kb
Host smart-b1d538a1-18a6-45e9-97d5-20f38aa066a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349784471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1349784471
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2344213379
Short name T13
Test name
Test status
Simulation time 24732970553 ps
CPU time 18.69 seconds
Started May 23 01:37:53 PM PDT 24
Finished May 23 01:38:19 PM PDT 24
Peak memory 212920 kb
Host smart-be44f241-2fc0-44b3-a5f2-3efaf218602a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2344213379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2344213379
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1821002685
Short name T143
Test name
Test status
Simulation time 735279365 ps
CPU time 20.71 seconds
Started May 23 01:37:52 PM PDT 24
Finished May 23 01:38:20 PM PDT 24
Peak memory 213768 kb
Host smart-6652195c-f07b-4875-8077-cab8776cc448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821002685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1821002685
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2293542025
Short name T329
Test name
Test status
Simulation time 823597079 ps
CPU time 11.3 seconds
Started May 23 01:37:55 PM PDT 24
Finished May 23 01:38:13 PM PDT 24
Peak memory 213776 kb
Host smart-b21f0183-c606-465e-81ad-e5159d424966
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293542025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2293542025
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.989069753
Short name T223
Test name
Test status
Simulation time 350455316 ps
CPU time 10.78 seconds
Started May 23 01:37:52 PM PDT 24
Finished May 23 01:38:10 PM PDT 24
Peak memory 211396 kb
Host smart-e15f6be4-4bba-4649-aac5-61e9d5a4426c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989069753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.989069753
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.585382297
Short name T220
Test name
Test status
Simulation time 30426648280 ps
CPU time 612.89 seconds
Started May 23 01:37:57 PM PDT 24
Finished May 23 01:48:16 PM PDT 24
Peak memory 217764 kb
Host smart-e755e669-c354-424d-a679-e588ea5fc9c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585382297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.585382297
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1246820460
Short name T322
Test name
Test status
Simulation time 8668303660 ps
CPU time 68.92 seconds
Started May 23 01:37:53 PM PDT 24
Finished May 23 01:39:10 PM PDT 24
Peak memory 214140 kb
Host smart-7adc0786-9745-4a0e-bca2-b1b543e72460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246820460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1246820460
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.741093455
Short name T195
Test name
Test status
Simulation time 9869411584 ps
CPU time 25.47 seconds
Started May 23 01:37:54 PM PDT 24
Finished May 23 01:38:27 PM PDT 24
Peak memory 211740 kb
Host smart-fbb5b342-0c10-4de5-9dee-70f0bdb549dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=741093455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.741093455
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1424818607
Short name T117
Test name
Test status
Simulation time 4262687792 ps
CPU time 45.81 seconds
Started May 23 01:37:55 PM PDT 24
Finished May 23 01:38:48 PM PDT 24
Peak memory 216804 kb
Host smart-cc0ebe9a-a318-41f0-8ca8-9aac14a30f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424818607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1424818607
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3985463621
Short name T235
Test name
Test status
Simulation time 20524274015 ps
CPU time 204.5 seconds
Started May 23 01:37:53 PM PDT 24
Finished May 23 01:41:25 PM PDT 24
Peak memory 219660 kb
Host smart-e0ca300b-f280-4e0e-9ccb-1fd940365d17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985463621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3985463621
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1223092666
Short name T189
Test name
Test status
Simulation time 3661707558 ps
CPU time 13.07 seconds
Started May 23 01:37:56 PM PDT 24
Finished May 23 01:38:16 PM PDT 24
Peak memory 211448 kb
Host smart-fb644327-8453-4dc7-b85a-537db940c0fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223092666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1223092666
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2055888996
Short name T144
Test name
Test status
Simulation time 16550927179 ps
CPU time 255.03 seconds
Started May 23 01:37:55 PM PDT 24
Finished May 23 01:42:17 PM PDT 24
Peak memory 225796 kb
Host smart-43098e5d-3bd5-458a-a78b-c83c6660848c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055888996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2055888996
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3012399629
Short name T19
Test name
Test status
Simulation time 675053093 ps
CPU time 19.29 seconds
Started May 23 01:37:54 PM PDT 24
Finished May 23 01:38:21 PM PDT 24
Peak memory 214680 kb
Host smart-fdc001ac-a455-40bb-ada4-2f25a287f694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012399629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3012399629
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.545067997
Short name T299
Test name
Test status
Simulation time 3084775839 ps
CPU time 28.08 seconds
Started May 23 01:37:54 PM PDT 24
Finished May 23 01:38:29 PM PDT 24
Peak memory 211440 kb
Host smart-0d18c125-3601-4dba-8e78-33777120ff24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=545067997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.545067997
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3348813250
Short name T311
Test name
Test status
Simulation time 7791196319 ps
CPU time 63.73 seconds
Started May 23 01:37:54 PM PDT 24
Finished May 23 01:39:06 PM PDT 24
Peak memory 217188 kb
Host smart-2359fbd6-6888-4b97-8296-7f94146962e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348813250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3348813250
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3156723866
Short name T45
Test name
Test status
Simulation time 16939711287 ps
CPU time 154.14 seconds
Started May 23 01:37:58 PM PDT 24
Finished May 23 01:40:37 PM PDT 24
Peak memory 220300 kb
Host smart-bda645a6-750e-4c41-9bba-e4c2c8d62754
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156723866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3156723866
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3536130972
Short name T346
Test name
Test status
Simulation time 9792989628 ps
CPU time 20.92 seconds
Started May 23 01:38:08 PM PDT 24
Finished May 23 01:38:30 PM PDT 24
Peak memory 211512 kb
Host smart-65501caf-bc47-469e-a9b9-75184c07168f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536130972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3536130972
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.903069004
Short name T193
Test name
Test status
Simulation time 292364985809 ps
CPU time 692.76 seconds
Started May 23 01:38:09 PM PDT 24
Finished May 23 01:49:43 PM PDT 24
Peak memory 227072 kb
Host smart-3edd2089-1bc5-4336-a9b2-c7dbf419a67a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903069004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.903069004
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.705226545
Short name T301
Test name
Test status
Simulation time 1321270351 ps
CPU time 18.91 seconds
Started May 23 01:38:09 PM PDT 24
Finished May 23 01:38:30 PM PDT 24
Peak memory 214632 kb
Host smart-0e9746d9-562b-45f5-93fb-5ea36b028bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705226545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.705226545
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2449410770
Short name T152
Test name
Test status
Simulation time 3640406025 ps
CPU time 16.77 seconds
Started May 23 01:37:55 PM PDT 24
Finished May 23 01:38:19 PM PDT 24
Peak memory 211688 kb
Host smart-9085a990-2b95-440a-b5dc-15babb0e43ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2449410770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2449410770
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3771832203
Short name T120
Test name
Test status
Simulation time 1354650732 ps
CPU time 19.64 seconds
Started May 23 01:37:54 PM PDT 24
Finished May 23 01:38:21 PM PDT 24
Peak memory 216500 kb
Host smart-43d49c59-ec26-460c-9023-fa1827ef2fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771832203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3771832203
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1987978494
Short name T236
Test name
Test status
Simulation time 22181452029 ps
CPU time 130.55 seconds
Started May 23 01:37:57 PM PDT 24
Finished May 23 01:40:14 PM PDT 24
Peak memory 220900 kb
Host smart-abd47689-a2a6-4efb-93fa-338403f076a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987978494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1987978494
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.717523791
Short name T176
Test name
Test status
Simulation time 7251710975 ps
CPU time 29.68 seconds
Started May 23 01:37:06 PM PDT 24
Finished May 23 01:37:40 PM PDT 24
Peak memory 212376 kb
Host smart-94a5859f-d170-482c-8f49-16163f7d3081
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717523791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.717523791
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3884610363
Short name T256
Test name
Test status
Simulation time 235332146157 ps
CPU time 625.24 seconds
Started May 23 01:37:06 PM PDT 24
Finished May 23 01:47:36 PM PDT 24
Peak memory 233844 kb
Host smart-05f9e901-8efb-4477-86c1-320a3ce192ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884610363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3884610363
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3039648694
Short name T200
Test name
Test status
Simulation time 6434571044 ps
CPU time 57.26 seconds
Started May 23 01:37:03 PM PDT 24
Finished May 23 01:38:04 PM PDT 24
Peak memory 215216 kb
Host smart-fbb8dabd-102e-47ea-9bbb-e0c69f851698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039648694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3039648694
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3967301805
Short name T343
Test name
Test status
Simulation time 11014671684 ps
CPU time 26.51 seconds
Started May 23 01:37:05 PM PDT 24
Finished May 23 01:37:35 PM PDT 24
Peak memory 211796 kb
Host smart-e6f2609c-326e-4aae-8c79-aaf2c7998039
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3967301805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3967301805
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.597277193
Short name T239
Test name
Test status
Simulation time 3868612076 ps
CPU time 47.98 seconds
Started May 23 01:37:05 PM PDT 24
Finished May 23 01:37:57 PM PDT 24
Peak memory 216488 kb
Host smart-217eebb3-3915-47fe-9bd9-bd2fba0e6d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597277193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.597277193
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3719090004
Short name T159
Test name
Test status
Simulation time 63089264123 ps
CPU time 170.28 seconds
Started May 23 01:37:05 PM PDT 24
Finished May 23 01:39:59 PM PDT 24
Peak memory 219380 kb
Host smart-6c99eb05-894a-47e7-9dc3-dfcc17f9aa19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719090004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3719090004
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1566802361
Short name T187
Test name
Test status
Simulation time 15020677458 ps
CPU time 30.89 seconds
Started May 23 01:38:10 PM PDT 24
Finished May 23 01:38:42 PM PDT 24
Peak memory 212352 kb
Host smart-a72c8642-58f8-4afd-af71-bd3a155a0527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566802361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1566802361
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.785956097
Short name T307
Test name
Test status
Simulation time 1661447997 ps
CPU time 30.62 seconds
Started May 23 01:38:08 PM PDT 24
Finished May 23 01:38:40 PM PDT 24
Peak memory 214784 kb
Host smart-7f5e9444-c967-4188-9f87-54d1cc5727f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785956097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.785956097
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3932342470
Short name T279
Test name
Test status
Simulation time 67409088226 ps
CPU time 30.88 seconds
Started May 23 01:38:08 PM PDT 24
Finished May 23 01:38:40 PM PDT 24
Peak memory 212916 kb
Host smart-fb2a3fd1-ff4f-48ca-b105-5e7be2c4c491
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3932342470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3932342470
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3240446262
Short name T46
Test name
Test status
Simulation time 4719083693 ps
CPU time 37.67 seconds
Started May 23 01:38:10 PM PDT 24
Finished May 23 01:38:49 PM PDT 24
Peak memory 217836 kb
Host smart-aabc302a-c5e6-4c31-a71b-4119dfa0f8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240446262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3240446262
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2999345008
Short name T250
Test name
Test status
Simulation time 257517798 ps
CPU time 12.3 seconds
Started May 23 01:38:08 PM PDT 24
Finished May 23 01:38:22 PM PDT 24
Peak memory 213488 kb
Host smart-798836a8-db3f-454d-8496-4f5f53122bf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999345008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2999345008
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2529367933
Short name T246
Test name
Test status
Simulation time 14638995103 ps
CPU time 28.71 seconds
Started May 23 01:38:09 PM PDT 24
Finished May 23 01:38:40 PM PDT 24
Peak memory 212324 kb
Host smart-f4798b62-2064-4466-9221-0cb436f82da8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529367933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2529367933
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.840207675
Short name T217
Test name
Test status
Simulation time 9809504306 ps
CPU time 178.55 seconds
Started May 23 01:38:09 PM PDT 24
Finished May 23 01:41:09 PM PDT 24
Peak memory 239000 kb
Host smart-f71426f4-774a-4eaf-af77-adf91877020e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840207675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.840207675
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3945559051
Short name T244
Test name
Test status
Simulation time 1224800554 ps
CPU time 19.12 seconds
Started May 23 01:38:09 PM PDT 24
Finished May 23 01:38:30 PM PDT 24
Peak memory 215200 kb
Host smart-ac2492ff-4459-4e9e-a14f-2f590066b94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945559051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3945559051
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2987450104
Short name T172
Test name
Test status
Simulation time 3094941672 ps
CPU time 27.78 seconds
Started May 23 01:38:08 PM PDT 24
Finished May 23 01:38:37 PM PDT 24
Peak memory 211428 kb
Host smart-2fef9e2b-660d-4b50-95aa-5cc0710aa0a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2987450104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2987450104
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3809836719
Short name T138
Test name
Test status
Simulation time 12670269911 ps
CPU time 54.1 seconds
Started May 23 01:38:09 PM PDT 24
Finished May 23 01:39:05 PM PDT 24
Peak memory 217872 kb
Host smart-358c8cbb-bb58-44cd-81cd-84911bed22db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809836719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3809836719
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.342984695
Short name T184
Test name
Test status
Simulation time 423808221 ps
CPU time 11.68 seconds
Started May 23 01:38:07 PM PDT 24
Finished May 23 01:38:21 PM PDT 24
Peak memory 212288 kb
Host smart-24560a0f-eae6-4e57-b293-e7b07e8b3385
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342984695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.342984695
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3863006500
Short name T323
Test name
Test status
Simulation time 2446311850 ps
CPU time 22.73 seconds
Started May 23 01:38:10 PM PDT 24
Finished May 23 01:38:35 PM PDT 24
Peak memory 211500 kb
Host smart-78e00c2f-77bb-457e-8704-a52829bda2a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863006500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3863006500
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2891700175
Short name T214
Test name
Test status
Simulation time 20747039599 ps
CPU time 316.8 seconds
Started May 23 01:38:09 PM PDT 24
Finished May 23 01:43:27 PM PDT 24
Peak memory 234780 kb
Host smart-02e7a75d-8989-4db6-a10d-1f7af2d05c2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891700175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2891700175
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3629822740
Short name T325
Test name
Test status
Simulation time 2782209093 ps
CPU time 38.02 seconds
Started May 23 01:38:10 PM PDT 24
Finished May 23 01:38:50 PM PDT 24
Peak memory 215044 kb
Host smart-d9423e4c-578a-4eb4-b07e-54098263d8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629822740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3629822740
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.302734248
Short name T345
Test name
Test status
Simulation time 1842289077 ps
CPU time 20.97 seconds
Started May 23 01:38:11 PM PDT 24
Finished May 23 01:38:33 PM PDT 24
Peak memory 211216 kb
Host smart-764acf31-8375-4057-8edd-acc9d4a8269c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=302734248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.302734248
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2112426821
Short name T81
Test name
Test status
Simulation time 2048577769 ps
CPU time 28.88 seconds
Started May 23 01:38:09 PM PDT 24
Finished May 23 01:38:40 PM PDT 24
Peak memory 216792 kb
Host smart-51bf4914-e33c-490a-83e6-bb6e296afa97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112426821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2112426821
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.667109147
Short name T310
Test name
Test status
Simulation time 23972452220 ps
CPU time 100.43 seconds
Started May 23 01:38:09 PM PDT 24
Finished May 23 01:39:51 PM PDT 24
Peak memory 220084 kb
Host smart-b72715f8-66e9-4f90-a55b-2edb0b43a0e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667109147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.667109147
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1147556588
Short name T338
Test name
Test status
Simulation time 660481218 ps
CPU time 8.28 seconds
Started May 23 01:38:10 PM PDT 24
Finished May 23 01:38:20 PM PDT 24
Peak memory 211384 kb
Host smart-59c58761-c537-43f1-bb33-0c4db9bfa4e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147556588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1147556588
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1654081122
Short name T202
Test name
Test status
Simulation time 4801346904 ps
CPU time 154.62 seconds
Started May 23 01:38:09 PM PDT 24
Finished May 23 01:40:46 PM PDT 24
Peak memory 240268 kb
Host smart-08472237-d62e-4f61-9ec5-ad26086a3ef6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654081122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1654081122
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1894461208
Short name T356
Test name
Test status
Simulation time 3580607600 ps
CPU time 25.25 seconds
Started May 23 01:38:10 PM PDT 24
Finished May 23 01:38:37 PM PDT 24
Peak memory 214888 kb
Host smart-48a61ffb-443a-4b54-b6ce-f3fa52038ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894461208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1894461208
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2149478417
Short name T252
Test name
Test status
Simulation time 6806183076 ps
CPU time 26.1 seconds
Started May 23 01:38:13 PM PDT 24
Finished May 23 01:38:40 PM PDT 24
Peak memory 212536 kb
Host smart-a1a6b4c5-731f-4611-b975-4ac60aa58556
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2149478417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2149478417
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.921193696
Short name T359
Test name
Test status
Simulation time 1710689963 ps
CPU time 26.32 seconds
Started May 23 01:38:08 PM PDT 24
Finished May 23 01:38:36 PM PDT 24
Peak memory 215588 kb
Host smart-3c453dbd-23cc-48ea-b8c4-87029efcd836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921193696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.921193696
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1886256513
Short name T339
Test name
Test status
Simulation time 2097958685 ps
CPU time 42.01 seconds
Started May 23 01:38:09 PM PDT 24
Finished May 23 01:38:53 PM PDT 24
Peak memory 219296 kb
Host smart-ff38ffbc-4206-4059-80f8-423e06eb2e69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886256513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1886256513
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3307328209
Short name T308
Test name
Test status
Simulation time 9425541075 ps
CPU time 17.06 seconds
Started May 23 01:38:11 PM PDT 24
Finished May 23 01:38:30 PM PDT 24
Peak memory 211520 kb
Host smart-ec9e9594-d992-4943-92dc-d565746dde5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307328209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3307328209
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.802387256
Short name T248
Test name
Test status
Simulation time 32464248444 ps
CPU time 275.15 seconds
Started May 23 01:38:12 PM PDT 24
Finished May 23 01:42:49 PM PDT 24
Peak memory 218192 kb
Host smart-4b816674-7dfe-41c3-8342-d487e486b6d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802387256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.802387256
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.875701574
Short name T282
Test name
Test status
Simulation time 345814176 ps
CPU time 19.65 seconds
Started May 23 01:38:11 PM PDT 24
Finished May 23 01:38:32 PM PDT 24
Peak memory 214696 kb
Host smart-03e1d421-18be-409a-86da-cd53c866c5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875701574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.875701574
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2040861541
Short name T166
Test name
Test status
Simulation time 601300887 ps
CPU time 10.25 seconds
Started May 23 01:38:11 PM PDT 24
Finished May 23 01:38:23 PM PDT 24
Peak memory 212320 kb
Host smart-b47b1cbc-1e4c-425f-aa92-ff24d413d637
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2040861541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2040861541
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.153990701
Short name T262
Test name
Test status
Simulation time 3483260643 ps
CPU time 39.91 seconds
Started May 23 01:38:10 PM PDT 24
Finished May 23 01:38:52 PM PDT 24
Peak memory 214868 kb
Host smart-1e96dba1-eee1-4085-b489-b816b46675b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153990701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.153990701
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1894230654
Short name T358
Test name
Test status
Simulation time 15642500133 ps
CPU time 140.93 seconds
Started May 23 01:38:11 PM PDT 24
Finished May 23 01:40:34 PM PDT 24
Peak memory 221008 kb
Host smart-082c2749-5213-4bbf-88b7-343e18996c45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894230654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1894230654
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2685389927
Short name T16
Test name
Test status
Simulation time 178762565686 ps
CPU time 3394.27 seconds
Started May 23 01:38:12 PM PDT 24
Finished May 23 02:34:48 PM PDT 24
Peak memory 245264 kb
Host smart-fff9eb70-2d06-451e-9dd1-a0ac49b0f45a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685389927 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2685389927
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3345530349
Short name T265
Test name
Test status
Simulation time 7862792995 ps
CPU time 21.1 seconds
Started May 23 01:38:13 PM PDT 24
Finished May 23 01:38:36 PM PDT 24
Peak memory 212276 kb
Host smart-efbb4bb2-1f87-4373-9b7f-f5fbab2e8600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345530349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3345530349
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1925400436
Short name T131
Test name
Test status
Simulation time 509712657199 ps
CPU time 1285.01 seconds
Started May 23 01:38:10 PM PDT 24
Finished May 23 01:59:37 PM PDT 24
Peak memory 240164 kb
Host smart-92fbec80-7fd4-4572-b178-4af2f24597c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925400436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1925400436
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3524879346
Short name T18
Test name
Test status
Simulation time 377349008 ps
CPU time 18.94 seconds
Started May 23 01:38:14 PM PDT 24
Finished May 23 01:38:34 PM PDT 24
Peak memory 214620 kb
Host smart-14d773b5-7884-4117-b37b-e912b9f8b214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524879346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3524879346
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1185872233
Short name T190
Test name
Test status
Simulation time 8678702699 ps
CPU time 34.81 seconds
Started May 23 01:38:09 PM PDT 24
Finished May 23 01:38:46 PM PDT 24
Peak memory 211712 kb
Host smart-6e60248a-01d2-404d-aee9-15698573ad81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1185872233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1185872233
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.394359470
Short name T318
Test name
Test status
Simulation time 7636527722 ps
CPU time 35.6 seconds
Started May 23 01:38:10 PM PDT 24
Finished May 23 01:38:47 PM PDT 24
Peak memory 218408 kb
Host smart-e5046583-b1b2-49f6-995b-a787db2c9cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394359470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.394359470
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3878607131
Short name T80
Test name
Test status
Simulation time 2980909042 ps
CPU time 37.33 seconds
Started May 23 01:38:11 PM PDT 24
Finished May 23 01:38:50 PM PDT 24
Peak memory 219408 kb
Host smart-c98e4bd7-c300-4dea-9eba-f47aee461cb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878607131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3878607131
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1902391612
Short name T336
Test name
Test status
Simulation time 20484269180 ps
CPU time 254.89 seconds
Started May 23 01:38:14 PM PDT 24
Finished May 23 01:42:30 PM PDT 24
Peak memory 228684 kb
Host smart-ffdb5c83-9e6a-4312-a645-e52d237c9f98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902391612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1902391612
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4010330532
Short name T225
Test name
Test status
Simulation time 6879701118 ps
CPU time 41.44 seconds
Started May 23 01:38:10 PM PDT 24
Finished May 23 01:38:53 PM PDT 24
Peak memory 215036 kb
Host smart-ad771780-de7e-4ac1-82bb-7dc05f11a7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010330532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4010330532
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2030611771
Short name T5
Test name
Test status
Simulation time 1890854786 ps
CPU time 21.73 seconds
Started May 23 01:38:13 PM PDT 24
Finished May 23 01:38:36 PM PDT 24
Peak memory 211468 kb
Host smart-50c0ca0e-fe5f-4358-8836-e50810089164
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2030611771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2030611771
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3879494267
Short name T347
Test name
Test status
Simulation time 13447096256 ps
CPU time 56.5 seconds
Started May 23 01:38:10 PM PDT 24
Finished May 23 01:39:08 PM PDT 24
Peak memory 215172 kb
Host smart-7e1485bc-7f89-407b-aa4c-d5ce9ae38848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879494267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3879494267
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.85998216
Short name T297
Test name
Test status
Simulation time 2390826248 ps
CPU time 33.69 seconds
Started May 23 01:38:14 PM PDT 24
Finished May 23 01:38:48 PM PDT 24
Peak memory 219400 kb
Host smart-09116986-7be6-4b17-b37e-03f86556141a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85998216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 46.rom_ctrl_stress_all.85998216
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2375101985
Short name T274
Test name
Test status
Simulation time 1375463231 ps
CPU time 8.23 seconds
Started May 23 01:38:26 PM PDT 24
Finished May 23 01:38:36 PM PDT 24
Peak memory 211372 kb
Host smart-6bdff050-4e52-41e6-bb55-dd34c19e22e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375101985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2375101985
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2546400211
Short name T191
Test name
Test status
Simulation time 38676479089 ps
CPU time 405.29 seconds
Started May 23 01:38:24 PM PDT 24
Finished May 23 01:45:11 PM PDT 24
Peak memory 237860 kb
Host smart-6db9cd5e-7f19-401b-bf70-eea6c8d6dcfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546400211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2546400211
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2175345085
Short name T38
Test name
Test status
Simulation time 2665154203 ps
CPU time 37.37 seconds
Started May 23 01:38:25 PM PDT 24
Finished May 23 01:39:03 PM PDT 24
Peak memory 214908 kb
Host smart-e1e5719e-d3e3-40f5-b0ff-79341c24944d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175345085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2175345085
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2172216666
Short name T124
Test name
Test status
Simulation time 1839366402 ps
CPU time 20.83 seconds
Started May 23 01:38:24 PM PDT 24
Finished May 23 01:38:46 PM PDT 24
Peak memory 211232 kb
Host smart-35945830-8150-4707-b257-f4293b7d0306
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2172216666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2172216666
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1089487955
Short name T156
Test name
Test status
Simulation time 350772053 ps
CPU time 20.35 seconds
Started May 23 01:38:25 PM PDT 24
Finished May 23 01:38:46 PM PDT 24
Peak memory 216900 kb
Host smart-423fd016-9ae3-4ddd-86a7-2deb69c80d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089487955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1089487955
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.79662736
Short name T188
Test name
Test status
Simulation time 14887309034 ps
CPU time 77.6 seconds
Started May 23 01:38:25 PM PDT 24
Finished May 23 01:39:44 PM PDT 24
Peak memory 219432 kb
Host smart-7fe371ea-e3db-406b-bc50-d1929ddb690c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79662736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 47.rom_ctrl_stress_all.79662736
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1511504659
Short name T170
Test name
Test status
Simulation time 1619796788 ps
CPU time 19.63 seconds
Started May 23 01:38:25 PM PDT 24
Finished May 23 01:38:45 PM PDT 24
Peak memory 211448 kb
Host smart-f8e91d8d-0812-4ac5-ab7c-3819370f6226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511504659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1511504659
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2499079231
Short name T163
Test name
Test status
Simulation time 10010789004 ps
CPU time 229.42 seconds
Started May 23 01:38:25 PM PDT 24
Finished May 23 01:42:15 PM PDT 24
Peak memory 228312 kb
Host smart-57afc7de-0689-4513-b918-9e90ad3c4c2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499079231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2499079231
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1438561653
Short name T341
Test name
Test status
Simulation time 3911950260 ps
CPU time 43.91 seconds
Started May 23 01:38:26 PM PDT 24
Finished May 23 01:39:12 PM PDT 24
Peak memory 214880 kb
Host smart-950e5c1a-62d5-43c4-b16d-fd16e3608307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438561653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1438561653
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1126481220
Short name T129
Test name
Test status
Simulation time 5831495108 ps
CPU time 19.31 seconds
Started May 23 01:38:25 PM PDT 24
Finished May 23 01:38:45 PM PDT 24
Peak memory 211764 kb
Host smart-92d4d871-a5bd-40b2-88c8-1610ace197ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1126481220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1126481220
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2368418654
Short name T296
Test name
Test status
Simulation time 4235717462 ps
CPU time 46.54 seconds
Started May 23 01:38:24 PM PDT 24
Finished May 23 01:39:11 PM PDT 24
Peak memory 217508 kb
Host smart-5982c587-6a61-4fd8-87c3-797076fb2300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368418654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2368418654
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1401922412
Short name T14
Test name
Test status
Simulation time 14194680104 ps
CPU time 127.86 seconds
Started May 23 01:38:23 PM PDT 24
Finished May 23 01:40:31 PM PDT 24
Peak memory 219720 kb
Host smart-516c22b4-11fc-4e14-93bf-2fd02073bd48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401922412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1401922412
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.796719646
Short name T2
Test name
Test status
Simulation time 636794869 ps
CPU time 8.34 seconds
Started May 23 01:38:25 PM PDT 24
Finished May 23 01:38:34 PM PDT 24
Peak memory 211368 kb
Host smart-53d21384-a0b2-48b6-b2e4-827443fe4586
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796719646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.796719646
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3518884722
Short name T26
Test name
Test status
Simulation time 190607591289 ps
CPU time 480.29 seconds
Started May 23 01:38:25 PM PDT 24
Finished May 23 01:46:27 PM PDT 24
Peak memory 232928 kb
Host smart-dff72ae0-e401-4f32-8c03-028b7b490139
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518884722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3518884722
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2195983760
Short name T269
Test name
Test status
Simulation time 1222510185 ps
CPU time 19.24 seconds
Started May 23 01:38:26 PM PDT 24
Finished May 23 01:38:47 PM PDT 24
Peak memory 214608 kb
Host smart-2c9d37ec-3d5a-4598-b113-54098899d9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195983760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2195983760
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3864286089
Short name T141
Test name
Test status
Simulation time 6081374353 ps
CPU time 33.57 seconds
Started May 23 01:38:24 PM PDT 24
Finished May 23 01:38:58 PM PDT 24
Peak memory 211728 kb
Host smart-2d5bd5f1-0ac9-446f-84ba-f51a6a7fc004
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3864286089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3864286089
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3139173610
Short name T198
Test name
Test status
Simulation time 8570389854 ps
CPU time 50.37 seconds
Started May 23 01:38:26 PM PDT 24
Finished May 23 01:39:18 PM PDT 24
Peak memory 215432 kb
Host smart-7032438f-36e6-44a2-b1fb-4c94db8d5e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139173610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3139173610
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2535756609
Short name T40
Test name
Test status
Simulation time 92333794573 ps
CPU time 128.75 seconds
Started May 23 01:38:23 PM PDT 24
Finished May 23 01:40:33 PM PDT 24
Peak memory 219456 kb
Host smart-b8770bba-0bfd-4b9d-9669-945ccff1313c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535756609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2535756609
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1248588691
Short name T317
Test name
Test status
Simulation time 174251685 ps
CPU time 8.64 seconds
Started May 23 01:37:04 PM PDT 24
Finished May 23 01:37:16 PM PDT 24
Peak memory 211328 kb
Host smart-7c269826-0f26-493e-a1c2-609b48e9008d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248588691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1248588691
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.112035532
Short name T304
Test name
Test status
Simulation time 18061742923 ps
CPU time 295.27 seconds
Started May 23 01:37:09 PM PDT 24
Finished May 23 01:42:08 PM PDT 24
Peak memory 237956 kb
Host smart-71f0af3d-4e8e-43d4-b893-576919acdd94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112035532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.112035532
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3579984016
Short name T348
Test name
Test status
Simulation time 2362670261 ps
CPU time 23.27 seconds
Started May 23 01:37:04 PM PDT 24
Finished May 23 01:37:31 PM PDT 24
Peak memory 211592 kb
Host smart-5063b23c-c189-4190-8d18-a74361404b9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3579984016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3579984016
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.441431414
Short name T290
Test name
Test status
Simulation time 1046570190 ps
CPU time 27.19 seconds
Started May 23 01:37:04 PM PDT 24
Finished May 23 01:37:36 PM PDT 24
Peak memory 216660 kb
Host smart-20c4e333-0ec1-4a2d-9358-74a7c8a3e7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441431414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.441431414
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3829582822
Short name T160
Test name
Test status
Simulation time 134588112792 ps
CPU time 142.96 seconds
Started May 23 01:37:04 PM PDT 24
Finished May 23 01:39:31 PM PDT 24
Peak memory 220496 kb
Host smart-cd2d3c55-f1db-40e5-9546-03e0d8d8daa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829582822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3829582822
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3347837537
Short name T270
Test name
Test status
Simulation time 4382818731 ps
CPU time 28.52 seconds
Started May 23 01:37:06 PM PDT 24
Finished May 23 01:37:38 PM PDT 24
Peak memory 212252 kb
Host smart-70a95fe4-19ed-4f4b-bb83-8d19b4aebc28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347837537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3347837537
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1076990325
Short name T284
Test name
Test status
Simulation time 133710403217 ps
CPU time 365.26 seconds
Started May 23 01:37:08 PM PDT 24
Finished May 23 01:43:17 PM PDT 24
Peak memory 225352 kb
Host smart-62bb9313-8df5-4050-b0a8-537cb3d38a4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076990325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1076990325
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.379496254
Short name T229
Test name
Test status
Simulation time 1941833835 ps
CPU time 19.21 seconds
Started May 23 01:37:05 PM PDT 24
Finished May 23 01:37:28 PM PDT 24
Peak memory 215192 kb
Host smart-85c04d5e-f8e0-485c-9eaf-5eac86d98082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379496254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.379496254
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2915250723
Short name T151
Test name
Test status
Simulation time 4548023129 ps
CPU time 23.06 seconds
Started May 23 01:37:04 PM PDT 24
Finished May 23 01:37:31 PM PDT 24
Peak memory 211720 kb
Host smart-68fd69d8-4179-43d7-87f4-b5339b7f719d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2915250723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2915250723
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2535679937
Short name T219
Test name
Test status
Simulation time 11960107584 ps
CPU time 55.71 seconds
Started May 23 01:37:05 PM PDT 24
Finished May 23 01:38:05 PM PDT 24
Peak memory 217392 kb
Host smart-9a0a7c77-b528-49af-9471-1b6fa325bfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535679937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2535679937
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.80879324
Short name T127
Test name
Test status
Simulation time 12868595144 ps
CPU time 57.55 seconds
Started May 23 01:37:03 PM PDT 24
Finished May 23 01:38:04 PM PDT 24
Peak memory 219252 kb
Host smart-44821553-b546-4a0e-ac91-af16c5418a8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80879324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 6.rom_ctrl_stress_all.80879324
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3894405617
Short name T291
Test name
Test status
Simulation time 3773357645 ps
CPU time 31.74 seconds
Started May 23 01:37:08 PM PDT 24
Finished May 23 01:37:44 PM PDT 24
Peak memory 212068 kb
Host smart-cb681165-5771-477c-aa12-328e0589107d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894405617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3894405617
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3987510279
Short name T42
Test name
Test status
Simulation time 86451182096 ps
CPU time 663.23 seconds
Started May 23 01:37:07 PM PDT 24
Finished May 23 01:48:14 PM PDT 24
Peak memory 228964 kb
Host smart-097d0b6c-392c-408b-97c4-87279257bb60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987510279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3987510279
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3327858295
Short name T210
Test name
Test status
Simulation time 1320340067 ps
CPU time 19.26 seconds
Started May 23 01:37:07 PM PDT 24
Finished May 23 01:37:30 PM PDT 24
Peak memory 214712 kb
Host smart-9030a5e9-26ef-44f5-9cb1-3a1d3dbb1c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327858295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3327858295
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1568606485
Short name T93
Test name
Test status
Simulation time 339732020 ps
CPU time 10.53 seconds
Started May 23 01:37:07 PM PDT 24
Finished May 23 01:37:22 PM PDT 24
Peak memory 212452 kb
Host smart-7c62bed5-5960-4cf8-a436-f0e5dd3fc168
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1568606485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1568606485
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3470839823
Short name T330
Test name
Test status
Simulation time 2760335003 ps
CPU time 30.08 seconds
Started May 23 01:37:03 PM PDT 24
Finished May 23 01:37:37 PM PDT 24
Peak memory 213816 kb
Host smart-826445f2-1d77-4fc2-a345-abb7f02a5675
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470839823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3470839823
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2532522877
Short name T287
Test name
Test status
Simulation time 4115462927 ps
CPU time 31.83 seconds
Started May 23 01:37:06 PM PDT 24
Finished May 23 01:37:42 PM PDT 24
Peak memory 211508 kb
Host smart-2dfba96f-970e-4cfe-b6c4-0acedaa026e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532522877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2532522877
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3707369210
Short name T203
Test name
Test status
Simulation time 84749187993 ps
CPU time 540.08 seconds
Started May 23 01:37:05 PM PDT 24
Finished May 23 01:46:09 PM PDT 24
Peak memory 216724 kb
Host smart-54db3002-ce53-43aa-8bb0-2840ec31e689
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707369210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3707369210
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1469353111
Short name T206
Test name
Test status
Simulation time 54893378205 ps
CPU time 47.22 seconds
Started May 23 01:37:06 PM PDT 24
Finished May 23 01:37:58 PM PDT 24
Peak memory 214668 kb
Host smart-7ebcfb8e-6742-44e9-9dc0-4a90e13bfbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469353111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1469353111
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.992563422
Short name T37
Test name
Test status
Simulation time 5542631659 ps
CPU time 16.38 seconds
Started May 23 01:37:11 PM PDT 24
Finished May 23 01:37:31 PM PDT 24
Peak memory 211748 kb
Host smart-19e09427-d1b5-490d-a9c7-e14452be6996
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=992563422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.992563422
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.73768333
Short name T175
Test name
Test status
Simulation time 17229909120 ps
CPU time 50.44 seconds
Started May 23 01:37:03 PM PDT 24
Finished May 23 01:37:56 PM PDT 24
Peak memory 217816 kb
Host smart-ea8afd80-b18e-44f9-9d69-2472fe88fa4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73768333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.73768333
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3291131510
Short name T169
Test name
Test status
Simulation time 17726981850 ps
CPU time 72.87 seconds
Started May 23 01:37:04 PM PDT 24
Finished May 23 01:38:20 PM PDT 24
Peak memory 227668 kb
Host smart-02a23178-8594-47fa-a8fc-050eb2cdf36b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291131510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3291131510
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3372645230
Short name T128
Test name
Test status
Simulation time 3122771416 ps
CPU time 27.51 seconds
Started May 23 01:37:04 PM PDT 24
Finished May 23 01:37:35 PM PDT 24
Peak memory 211440 kb
Host smart-d93b3de9-4d38-4478-80d5-70402be780d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372645230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3372645230
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3901764594
Short name T34
Test name
Test status
Simulation time 72560580784 ps
CPU time 766.29 seconds
Started May 23 01:37:04 PM PDT 24
Finished May 23 01:49:54 PM PDT 24
Peak memory 239924 kb
Host smart-c2b22ba4-a957-4808-b390-4d2fbd52a2d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901764594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3901764594
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4181603067
Short name T313
Test name
Test status
Simulation time 7621790744 ps
CPU time 60.95 seconds
Started May 23 01:37:11 PM PDT 24
Finished May 23 01:38:15 PM PDT 24
Peak memory 215228 kb
Host smart-88d24aeb-040c-4fc2-8286-15ca0ad15539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181603067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.4181603067
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1383536110
Short name T281
Test name
Test status
Simulation time 430501123 ps
CPU time 13.11 seconds
Started May 23 01:37:08 PM PDT 24
Finished May 23 01:37:25 PM PDT 24
Peak memory 211428 kb
Host smart-3c5c7555-5d41-4ba2-893f-e70d8df1bdca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1383536110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1383536110
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2459052961
Short name T231
Test name
Test status
Simulation time 701135260 ps
CPU time 20.05 seconds
Started May 23 01:37:05 PM PDT 24
Finished May 23 01:37:29 PM PDT 24
Peak memory 216668 kb
Host smart-6fb4c5af-c4a7-4c9b-989a-355865310fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459052961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2459052961
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2702467669
Short name T167
Test name
Test status
Simulation time 40368796021 ps
CPU time 197.71 seconds
Started May 23 01:37:05 PM PDT 24
Finished May 23 01:40:27 PM PDT 24
Peak memory 221012 kb
Host smart-9276f382-06e5-480c-832e-9de14dc49729
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702467669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2702467669
Directory /workspace/9.rom_ctrl_stress_all/latest
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