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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.57 96.97 93.02 97.88 100.00 98.69 98.04 98.37


Total test records in report: 455
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T301 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2600934776 May 26 01:58:34 PM PDT 24 May 26 02:05:05 PM PDT 24 43067527255 ps
T302 /workspace/coverage/default/27.rom_ctrl_smoke.316762713 May 26 01:58:27 PM PDT 24 May 26 01:58:48 PM PDT 24 705631430 ps
T303 /workspace/coverage/default/46.rom_ctrl_smoke.174342487 May 26 01:59:00 PM PDT 24 May 26 01:59:51 PM PDT 24 6295180327 ps
T304 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1372371796 May 26 01:58:18 PM PDT 24 May 26 02:04:55 PM PDT 24 36488119035 ps
T305 /workspace/coverage/default/34.rom_ctrl_alert_test.3466142034 May 26 01:58:38 PM PDT 24 May 26 01:59:05 PM PDT 24 15539713622 ps
T306 /workspace/coverage/default/17.rom_ctrl_smoke.2657864713 May 26 01:58:15 PM PDT 24 May 26 01:58:44 PM PDT 24 3993015977 ps
T307 /workspace/coverage/default/20.rom_ctrl_alert_test.505046473 May 26 01:58:21 PM PDT 24 May 26 01:58:46 PM PDT 24 2559292655 ps
T308 /workspace/coverage/default/0.rom_ctrl_stress_all.1219543311 May 26 01:57:49 PM PDT 24 May 26 01:58:13 PM PDT 24 18137351977 ps
T309 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.883620320 May 26 01:58:12 PM PDT 24 May 26 01:58:47 PM PDT 24 3993155904 ps
T310 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3116915875 May 26 01:58:23 PM PDT 24 May 26 01:58:46 PM PDT 24 1983248267 ps
T311 /workspace/coverage/default/37.rom_ctrl_stress_all.3225264947 May 26 01:58:48 PM PDT 24 May 26 02:00:48 PM PDT 24 5311624849 ps
T312 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1571382581 May 26 01:58:27 PM PDT 24 May 26 02:02:59 PM PDT 24 14828038201 ps
T313 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.996793813 May 26 01:59:08 PM PDT 24 May 26 02:11:45 PM PDT 24 374289117490 ps
T314 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1141026875 May 26 01:59:00 PM PDT 24 May 26 02:00:09 PM PDT 24 16769973834 ps
T315 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1067387896 May 26 01:58:44 PM PDT 24 May 26 01:59:42 PM PDT 24 12996025616 ps
T316 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1631823747 May 26 01:58:22 PM PDT 24 May 26 02:13:06 PM PDT 24 93480396282 ps
T317 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1770353069 May 26 01:58:22 PM PDT 24 May 26 01:59:20 PM PDT 24 26111239801 ps
T318 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.966975775 May 26 01:58:01 PM PDT 24 May 26 02:09:15 PM PDT 24 114021209541 ps
T319 /workspace/coverage/default/30.rom_ctrl_alert_test.3848847441 May 26 01:58:39 PM PDT 24 May 26 01:58:59 PM PDT 24 1754662452 ps
T320 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2912909362 May 26 01:58:03 PM PDT 24 May 26 01:58:25 PM PDT 24 2357146567 ps
T64 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.729596166 May 26 01:57:55 PM PDT 24 May 26 04:53:42 PM PDT 24 57785740665 ps
T321 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1788167501 May 26 01:58:29 PM PDT 24 May 26 02:04:47 PM PDT 24 33149116925 ps
T322 /workspace/coverage/default/36.rom_ctrl_alert_test.1800777627 May 26 01:58:46 PM PDT 24 May 26 01:59:01 PM PDT 24 3291219980 ps
T323 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1080672149 May 26 01:58:47 PM PDT 24 May 26 01:59:28 PM PDT 24 3270761731 ps
T324 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.4103836460 May 26 01:57:51 PM PDT 24 May 26 01:58:22 PM PDT 24 6735878471 ps
T23 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.261545599 May 26 01:59:11 PM PDT 24 May 26 01:59:41 PM PDT 24 5251616079 ps
T325 /workspace/coverage/default/30.rom_ctrl_smoke.3389405366 May 26 01:58:38 PM PDT 24 May 26 01:59:25 PM PDT 24 8903513247 ps
T326 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.4239923572 May 26 01:58:01 PM PDT 24 May 26 01:58:22 PM PDT 24 18520547245 ps
T327 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.364094651 May 26 01:58:16 PM PDT 24 May 26 01:59:13 PM PDT 24 67676923654 ps
T328 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2267718138 May 26 01:58:37 PM PDT 24 May 26 01:58:48 PM PDT 24 718310954 ps
T329 /workspace/coverage/default/31.rom_ctrl_stress_all.3074850504 May 26 01:58:37 PM PDT 24 May 26 01:59:45 PM PDT 24 18978529467 ps
T330 /workspace/coverage/default/35.rom_ctrl_stress_all.1460032726 May 26 01:58:38 PM PDT 24 May 26 01:59:28 PM PDT 24 10021141574 ps
T331 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3480641908 May 26 01:58:47 PM PDT 24 May 26 01:59:04 PM PDT 24 4144608674 ps
T332 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.861450535 May 26 01:58:28 PM PDT 24 May 26 02:03:29 PM PDT 24 23913056776 ps
T333 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.729914834 May 26 01:58:01 PM PDT 24 May 26 02:02:03 PM PDT 24 157747845475 ps
T334 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.466898119 May 26 01:58:38 PM PDT 24 May 26 01:58:59 PM PDT 24 339278450 ps
T335 /workspace/coverage/default/31.rom_ctrl_alert_test.3803348423 May 26 01:58:40 PM PDT 24 May 26 01:59:01 PM PDT 24 4092211042 ps
T336 /workspace/coverage/default/37.rom_ctrl_alert_test.3744119148 May 26 01:58:45 PM PDT 24 May 26 01:59:00 PM PDT 24 775146760 ps
T337 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1209839065 May 26 01:58:21 PM PDT 24 May 26 01:58:47 PM PDT 24 8833025878 ps
T338 /workspace/coverage/default/17.rom_ctrl_alert_test.2354463220 May 26 01:58:14 PM PDT 24 May 26 01:58:35 PM PDT 24 1905936715 ps
T339 /workspace/coverage/default/38.rom_ctrl_alert_test.4191838367 May 26 01:58:44 PM PDT 24 May 26 01:59:07 PM PDT 24 4423462683 ps
T340 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.520531313 May 26 01:59:08 PM PDT 24 May 26 01:59:42 PM PDT 24 28470189644 ps
T40 /workspace/coverage/default/3.rom_ctrl_sec_cm.2564131115 May 26 01:57:50 PM PDT 24 May 26 02:02:00 PM PDT 24 61625874302 ps
T341 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1270014614 May 26 01:57:53 PM PDT 24 May 26 02:11:45 PM PDT 24 339729665699 ps
T342 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1192952952 May 26 01:58:38 PM PDT 24 May 26 01:59:23 PM PDT 24 7717070142 ps
T343 /workspace/coverage/default/39.rom_ctrl_alert_test.3913745143 May 26 01:58:47 PM PDT 24 May 26 01:58:56 PM PDT 24 169024132 ps
T344 /workspace/coverage/default/7.rom_ctrl_alert_test.1150021059 May 26 01:58:02 PM PDT 24 May 26 01:58:38 PM PDT 24 17880184460 ps
T345 /workspace/coverage/default/45.rom_ctrl_smoke.732554556 May 26 01:59:01 PM PDT 24 May 26 02:00:11 PM PDT 24 8355280874 ps
T346 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3338583045 May 26 01:58:28 PM PDT 24 May 26 01:58:56 PM PDT 24 6332272615 ps
T347 /workspace/coverage/default/5.rom_ctrl_smoke.2599881853 May 26 01:57:54 PM PDT 24 May 26 01:58:36 PM PDT 24 3074161517 ps
T348 /workspace/coverage/default/9.rom_ctrl_alert_test.1653532756 May 26 01:58:06 PM PDT 24 May 26 01:58:30 PM PDT 24 9548276302 ps
T349 /workspace/coverage/default/49.rom_ctrl_alert_test.2516702012 May 26 01:59:15 PM PDT 24 May 26 01:59:49 PM PDT 24 4186002627 ps
T350 /workspace/coverage/default/35.rom_ctrl_alert_test.406291551 May 26 01:58:48 PM PDT 24 May 26 01:59:14 PM PDT 24 2633206949 ps
T351 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.210696841 May 26 01:57:54 PM PDT 24 May 26 01:58:36 PM PDT 24 13602237912 ps
T352 /workspace/coverage/default/36.rom_ctrl_stress_all.1968019249 May 26 01:58:45 PM PDT 24 May 26 01:59:36 PM PDT 24 8574274901 ps
T353 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1397008519 May 26 01:58:47 PM PDT 24 May 26 01:58:59 PM PDT 24 177355250 ps
T354 /workspace/coverage/default/26.rom_ctrl_alert_test.711093311 May 26 01:58:29 PM PDT 24 May 26 01:58:59 PM PDT 24 6871328444 ps
T355 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.95944512 May 26 01:58:53 PM PDT 24 May 26 01:59:48 PM PDT 24 6015534572 ps
T356 /workspace/coverage/default/18.rom_ctrl_alert_test.2652446407 May 26 01:58:13 PM PDT 24 May 26 01:58:39 PM PDT 24 2841006138 ps
T357 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1559835541 May 26 01:58:37 PM PDT 24 May 26 01:59:40 PM PDT 24 7034900881 ps
T358 /workspace/coverage/default/25.rom_ctrl_smoke.1338266130 May 26 01:58:32 PM PDT 24 May 26 01:59:36 PM PDT 24 5563474236 ps
T77 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2004636288 May 26 01:57:39 PM PDT 24 May 26 01:57:58 PM PDT 24 3473045187 ps
T359 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1558007696 May 26 01:57:32 PM PDT 24 May 26 01:57:45 PM PDT 24 1026704022 ps
T78 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3040146330 May 26 01:57:42 PM PDT 24 May 26 01:58:01 PM PDT 24 1611895701 ps
T79 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3189823537 May 26 01:57:36 PM PDT 24 May 26 01:57:52 PM PDT 24 1010083574 ps
T86 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3946235015 May 26 01:57:31 PM PDT 24 May 26 01:57:55 PM PDT 24 9499032182 ps
T65 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3991675668 May 26 01:57:41 PM PDT 24 May 26 01:58:02 PM PDT 24 5343607765 ps
T114 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2325087350 May 26 01:57:43 PM PDT 24 May 26 01:58:13 PM PDT 24 4089232271 ps
T87 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.770781293 May 26 01:57:44 PM PDT 24 May 26 01:57:58 PM PDT 24 597938333 ps
T66 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.340206861 May 26 01:57:37 PM PDT 24 May 26 01:58:16 PM PDT 24 26005921236 ps
T360 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2624941976 May 26 01:57:43 PM PDT 24 May 26 01:58:18 PM PDT 24 16409939170 ps
T361 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2781122435 May 26 01:57:32 PM PDT 24 May 26 01:57:47 PM PDT 24 2423948229 ps
T362 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2332105613 May 26 01:57:33 PM PDT 24 May 26 01:57:54 PM PDT 24 7729286485 ps
T88 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2025998167 May 26 01:58:07 PM PDT 24 May 26 01:58:16 PM PDT 24 292077579 ps
T74 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3291766053 May 26 01:57:37 PM PDT 24 May 26 01:59:16 PM PDT 24 3079951768 ps
T75 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3169269300 May 26 01:57:38 PM PDT 24 May 26 01:59:03 PM PDT 24 507449982 ps
T115 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2492114836 May 26 01:57:48 PM PDT 24 May 26 01:58:03 PM PDT 24 941654827 ps
T116 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.543282563 May 26 01:57:39 PM PDT 24 May 26 01:58:34 PM PDT 24 2357565064 ps
T117 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.301353671 May 26 01:57:43 PM PDT 24 May 26 01:59:59 PM PDT 24 32926512489 ps
T363 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2712174683 May 26 01:57:37 PM PDT 24 May 26 01:57:58 PM PDT 24 8606486179 ps
T364 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.129917840 May 26 01:57:36 PM PDT 24 May 26 01:57:46 PM PDT 24 180967190 ps
T365 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3757160854 May 26 01:57:30 PM PDT 24 May 26 01:58:01 PM PDT 24 2819925229 ps
T110 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3350294885 May 26 01:57:31 PM PDT 24 May 26 01:58:02 PM PDT 24 8775771010 ps
T89 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3503266808 May 26 01:57:44 PM PDT 24 May 26 01:59:27 PM PDT 24 43990154525 ps
T76 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.170128666 May 26 01:57:46 PM PDT 24 May 26 02:00:27 PM PDT 24 841121392 ps
T90 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3648168437 May 26 01:57:29 PM PDT 24 May 26 01:58:02 PM PDT 24 12458602606 ps
T121 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3176288397 May 26 01:57:28 PM PDT 24 May 26 01:59:09 PM PDT 24 3263589078 ps
T111 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3256666672 May 26 01:57:44 PM PDT 24 May 26 01:58:17 PM PDT 24 72108025410 ps
T122 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.503780178 May 26 01:57:33 PM PDT 24 May 26 01:59:20 PM PDT 24 3953950840 ps
T366 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.108640714 May 26 01:57:34 PM PDT 24 May 26 01:59:41 PM PDT 24 45341298812 ps
T367 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3339358137 May 26 01:57:34 PM PDT 24 May 26 01:57:45 PM PDT 24 167807602 ps
T368 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3340812194 May 26 01:57:42 PM PDT 24 May 26 01:58:02 PM PDT 24 6664216426 ps
T112 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1137229335 May 26 01:57:39 PM PDT 24 May 26 01:58:04 PM PDT 24 3781534080 ps
T91 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3160275592 May 26 01:57:46 PM PDT 24 May 26 01:58:03 PM PDT 24 4787308166 ps
T92 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3327841914 May 26 01:57:36 PM PDT 24 May 26 02:00:24 PM PDT 24 37959767748 ps
T120 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.4217092181 May 26 01:57:32 PM PDT 24 May 26 01:58:45 PM PDT 24 17637851111 ps
T369 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.44766506 May 26 01:57:32 PM PDT 24 May 26 01:57:55 PM PDT 24 1822652394 ps
T125 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.802160841 May 26 01:57:39 PM PDT 24 May 26 01:59:21 PM PDT 24 7878580068 ps
T370 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.930468148 May 26 01:57:31 PM PDT 24 May 26 01:57:59 PM PDT 24 1968920426 ps
T371 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.271458062 May 26 01:57:31 PM PDT 24 May 26 01:57:56 PM PDT 24 10227619393 ps
T372 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1724863556 May 26 01:57:38 PM PDT 24 May 26 01:58:11 PM PDT 24 3956206844 ps
T93 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.119466841 May 26 01:57:37 PM PDT 24 May 26 01:58:06 PM PDT 24 14207828456 ps
T373 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2301918320 May 26 01:57:47 PM PDT 24 May 26 01:58:00 PM PDT 24 167806456 ps
T133 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.277608747 May 26 01:57:39 PM PDT 24 May 26 02:00:30 PM PDT 24 12969205424 ps
T374 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3933352838 May 26 01:57:39 PM PDT 24 May 26 01:57:52 PM PDT 24 419940521 ps
T375 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3339734398 May 26 01:57:38 PM PDT 24 May 26 01:58:10 PM PDT 24 15430784549 ps
T376 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2493347194 May 26 01:57:37 PM PDT 24 May 26 01:59:26 PM PDT 24 72290311764 ps
T94 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3352329713 May 26 01:57:30 PM PDT 24 May 26 01:57:59 PM PDT 24 5510787401 ps
T377 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2723312696 May 26 01:57:30 PM PDT 24 May 26 01:58:02 PM PDT 24 7327745100 ps
T378 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2078292476 May 26 01:57:32 PM PDT 24 May 26 01:57:57 PM PDT 24 24529999205 ps
T379 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2514479348 May 26 01:57:30 PM PDT 24 May 26 01:57:48 PM PDT 24 1096238947 ps
T95 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3916965357 May 26 01:57:33 PM PDT 24 May 26 01:59:44 PM PDT 24 16913318563 ps
T380 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3510391899 May 26 01:57:31 PM PDT 24 May 26 01:58:00 PM PDT 24 5566615741 ps
T381 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4001823092 May 26 01:57:44 PM PDT 24 May 26 01:58:01 PM PDT 24 1923141739 ps
T382 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2368572441 May 26 01:57:33 PM PDT 24 May 26 01:57:59 PM PDT 24 9965746176 ps
T383 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.754158168 May 26 01:57:46 PM PDT 24 May 26 01:57:58 PM PDT 24 3072583392 ps
T384 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1526861293 May 26 01:57:37 PM PDT 24 May 26 01:58:25 PM PDT 24 7064118831 ps
T98 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4151183222 May 26 01:57:30 PM PDT 24 May 26 01:57:45 PM PDT 24 1396471872 ps
T99 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2098374625 May 26 01:57:30 PM PDT 24 May 26 01:58:02 PM PDT 24 3580888364 ps
T385 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2413180210 May 26 01:57:36 PM PDT 24 May 26 01:57:59 PM PDT 24 42490230776 ps
T124 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.123564963 May 26 01:57:47 PM PDT 24 May 26 02:00:38 PM PDT 24 38170715894 ps
T386 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1271017945 May 26 01:57:42 PM PDT 24 May 26 01:57:50 PM PDT 24 345296220 ps
T134 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1632705392 May 26 01:57:39 PM PDT 24 May 26 01:59:13 PM PDT 24 16633962837 ps
T387 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.154602257 May 26 01:57:45 PM PDT 24 May 26 01:58:00 PM PDT 24 689244281 ps
T388 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3829546173 May 26 01:57:37 PM PDT 24 May 26 01:58:06 PM PDT 24 6413514035 ps
T100 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2257847798 May 26 01:57:38 PM PDT 24 May 26 01:59:34 PM PDT 24 26284257878 ps
T389 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1794994621 May 26 01:57:35 PM PDT 24 May 26 01:57:56 PM PDT 24 2181208403 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3256176355 May 26 01:57:31 PM PDT 24 May 26 01:57:58 PM PDT 24 12075849349 ps
T391 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3734018411 May 26 01:57:32 PM PDT 24 May 26 01:58:05 PM PDT 24 7497651144 ps
T392 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3992664732 May 26 01:57:33 PM PDT 24 May 26 01:58:01 PM PDT 24 5686718095 ps
T393 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.37346024 May 26 01:57:31 PM PDT 24 May 26 01:57:46 PM PDT 24 167438094 ps
T394 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2450016457 May 26 01:57:37 PM PDT 24 May 26 01:58:08 PM PDT 24 16476714862 ps
T130 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1427516210 May 26 01:57:34 PM PDT 24 May 26 01:59:11 PM PDT 24 4394546579 ps
T395 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1011892814 May 26 01:57:33 PM PDT 24 May 26 01:58:03 PM PDT 24 6851562178 ps
T396 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1685373298 May 26 01:57:37 PM PDT 24 May 26 01:58:09 PM PDT 24 19461657040 ps
T397 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.620912288 May 26 01:57:33 PM PDT 24 May 26 01:58:03 PM PDT 24 3098970267 ps
T398 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.579627252 May 26 01:57:34 PM PDT 24 May 26 01:57:49 PM PDT 24 524549641 ps
T399 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.686659114 May 26 01:57:31 PM PDT 24 May 26 01:58:05 PM PDT 24 3779016924 ps
T400 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2984961192 May 26 01:57:37 PM PDT 24 May 26 01:58:17 PM PDT 24 2988180585 ps
T131 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3715202078 May 26 01:57:29 PM PDT 24 May 26 02:00:18 PM PDT 24 706637121 ps
T126 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2211185977 May 26 01:57:42 PM PDT 24 May 26 01:59:23 PM PDT 24 3365829299 ps
T127 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3660309447 May 26 01:57:43 PM PDT 24 May 26 01:59:18 PM PDT 24 2390064044 ps
T401 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2779792974 May 26 01:57:44 PM PDT 24 May 26 01:57:59 PM PDT 24 3311401414 ps
T402 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.175970926 May 26 01:57:31 PM PDT 24 May 26 01:57:52 PM PDT 24 12308457091 ps
T403 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1046536475 May 26 01:57:46 PM PDT 24 May 26 01:58:10 PM PDT 24 3574148006 ps
T404 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3396976815 May 26 01:57:30 PM PDT 24 May 26 01:58:04 PM PDT 24 8462510901 ps
T405 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4222728317 May 26 01:57:30 PM PDT 24 May 26 01:57:49 PM PDT 24 931624039 ps
T406 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2022699478 May 26 01:57:37 PM PDT 24 May 26 01:57:59 PM PDT 24 3007180850 ps
T407 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3585643449 May 26 01:57:44 PM PDT 24 May 26 01:57:53 PM PDT 24 738541847 ps
T408 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4161823345 May 26 01:57:30 PM PDT 24 May 26 01:57:57 PM PDT 24 4809066903 ps
T409 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1964647911 May 26 01:57:31 PM PDT 24 May 26 01:57:57 PM PDT 24 8597974656 ps
T410 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1608407108 May 26 01:57:40 PM PDT 24 May 26 01:57:56 PM PDT 24 1754888150 ps
T411 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.31528711 May 26 01:57:33 PM PDT 24 May 26 01:57:49 PM PDT 24 585955894 ps
T412 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1304440266 May 26 01:57:37 PM PDT 24 May 26 01:57:52 PM PDT 24 170973927 ps
T413 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4105456288 May 26 01:57:37 PM PDT 24 May 26 01:57:57 PM PDT 24 1810403379 ps
T414 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4032963667 May 26 01:57:39 PM PDT 24 May 26 01:58:36 PM PDT 24 1076220920 ps
T128 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.898737798 May 26 01:57:42 PM PDT 24 May 26 01:59:22 PM PDT 24 12675078782 ps
T101 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.158893966 May 26 01:57:45 PM PDT 24 May 26 01:58:23 PM PDT 24 1375728510 ps
T415 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3782136317 May 26 01:57:32 PM PDT 24 May 26 01:58:04 PM PDT 24 10909201998 ps
T416 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2448872306 May 26 01:57:46 PM PDT 24 May 26 01:58:04 PM PDT 24 5414286368 ps
T417 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3486428098 May 26 01:57:33 PM PDT 24 May 26 01:57:51 PM PDT 24 2173504476 ps
T418 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.213809485 May 26 01:57:33 PM PDT 24 May 26 01:58:01 PM PDT 24 2571342292 ps
T419 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3520983373 May 26 01:57:33 PM PDT 24 May 26 01:58:03 PM PDT 24 6646628692 ps
T420 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3131879030 May 26 01:57:32 PM PDT 24 May 26 01:59:22 PM PDT 24 16241167950 ps
T421 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3210816351 May 26 01:57:33 PM PDT 24 May 26 01:57:51 PM PDT 24 2154899978 ps
T422 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1278647346 May 26 01:57:31 PM PDT 24 May 26 01:57:45 PM PDT 24 2732386033 ps
T423 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.883060885 May 26 01:57:39 PM PDT 24 May 26 01:58:12 PM PDT 24 25198237316 ps
T424 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3527172801 May 26 01:57:31 PM PDT 24 May 26 01:58:00 PM PDT 24 4026270229 ps
T132 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1022935449 May 26 01:57:37 PM PDT 24 May 26 02:00:25 PM PDT 24 10676355914 ps
T425 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2183112756 May 26 01:57:34 PM PDT 24 May 26 01:57:45 PM PDT 24 331916710 ps
T426 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1991191166 May 26 01:57:46 PM PDT 24 May 26 01:58:09 PM PDT 24 2607397398 ps
T427 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1408399449 May 26 01:57:38 PM PDT 24 May 26 01:58:02 PM PDT 24 5009490393 ps
T428 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.400094147 May 26 01:57:40 PM PDT 24 May 26 01:57:52 PM PDT 24 869526499 ps
T429 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2892304418 May 26 01:57:46 PM PDT 24 May 26 01:58:57 PM PDT 24 10314960197 ps
T430 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3294986271 May 26 01:57:48 PM PDT 24 May 26 01:59:09 PM PDT 24 285031354 ps
T431 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.606790690 May 26 01:57:46 PM PDT 24 May 26 01:58:08 PM PDT 24 4308538389 ps
T432 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2701566353 May 26 01:57:32 PM PDT 24 May 26 01:57:56 PM PDT 24 12936990361 ps
T129 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.620751212 May 26 01:57:43 PM PDT 24 May 26 02:00:28 PM PDT 24 4169397185 ps
T102 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1204887686 May 26 01:57:37 PM PDT 24 May 26 01:58:09 PM PDT 24 16179501109 ps
T433 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3052550349 May 26 01:57:43 PM PDT 24 May 26 01:58:23 PM PDT 24 725364553 ps
T434 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.206708940 May 26 01:57:37 PM PDT 24 May 26 01:57:48 PM PDT 24 201798802 ps
T435 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2549684382 May 26 01:57:33 PM PDT 24 May 26 01:58:47 PM PDT 24 4950479615 ps
T436 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1447333335 May 26 01:57:40 PM PDT 24 May 26 01:57:57 PM PDT 24 2066670230 ps
T437 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.468879765 May 26 01:57:33 PM PDT 24 May 26 01:59:01 PM PDT 24 596294705 ps
T438 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.479072617 May 26 01:57:33 PM PDT 24 May 26 01:58:05 PM PDT 24 2954360692 ps
T439 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1157812132 May 26 01:57:40 PM PDT 24 May 26 01:58:14 PM PDT 24 15203950405 ps
T440 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3059453830 May 26 01:57:50 PM PDT 24 May 26 01:59:25 PM PDT 24 51118373336 ps
T441 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3965688083 May 26 01:57:45 PM PDT 24 May 26 01:58:20 PM PDT 24 14765527094 ps
T442 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2759893737 May 26 01:57:32 PM PDT 24 May 26 01:57:44 PM PDT 24 214126632 ps
T443 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.80129105 May 26 01:57:39 PM PDT 24 May 26 01:57:51 PM PDT 24 494689766 ps
T103 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.834893195 May 26 01:57:39 PM PDT 24 May 26 01:57:49 PM PDT 24 338762523 ps
T444 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1238011263 May 26 01:57:30 PM PDT 24 May 26 01:58:23 PM PDT 24 2126729340 ps
T104 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2283797516 May 26 01:57:47 PM PDT 24 May 26 01:58:15 PM PDT 24 53409004140 ps
T445 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3771041682 May 26 01:57:38 PM PDT 24 May 26 01:57:52 PM PDT 24 688927834 ps
T446 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3187127297 May 26 01:57:37 PM PDT 24 May 26 01:57:49 PM PDT 24 1704717713 ps
T447 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.114173562 May 26 01:57:39 PM PDT 24 May 26 01:58:02 PM PDT 24 4352870734 ps
T448 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4247695924 May 26 01:57:39 PM PDT 24 May 26 01:58:03 PM PDT 24 4455543350 ps
T449 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3215141969 May 26 01:57:31 PM PDT 24 May 26 01:57:52 PM PDT 24 6193905138 ps
T450 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1155072414 May 26 01:57:34 PM PDT 24 May 26 01:58:09 PM PDT 24 13748498173 ps
T123 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2909805648 May 26 01:57:43 PM PDT 24 May 26 02:00:24 PM PDT 24 5616856421 ps
T451 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2183306093 May 26 01:57:38 PM PDT 24 May 26 01:58:04 PM PDT 24 4535929541 ps
T452 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1509744120 May 26 01:57:33 PM PDT 24 May 26 01:58:00 PM PDT 24 5527144583 ps
T453 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1071383009 May 26 01:57:30 PM PDT 24 May 26 01:57:45 PM PDT 24 169248576 ps
T454 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1567497977 May 26 01:57:34 PM PDT 24 May 26 01:57:59 PM PDT 24 9320412504 ps
T455 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1465804486 May 26 01:57:32 PM PDT 24 May 26 02:00:52 PM PDT 24 92694834345 ps

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2024865789
Short name T2
Test name
Test status
Simulation time 13711877477 ps
CPU time 136.65 seconds
Started May 26 01:57:52 PM PDT 24
Finished May 26 02:00:10 PM PDT 24
Peak memory 220608 kb
Host smart-b0e14e61-3bec-4b75-86cd-b1f24990e814
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024865789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2024865789
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3177981768
Short name T15
Test name
Test status
Simulation time 383093206095 ps
CPU time 3507.42 seconds
Started May 26 01:58:17 PM PDT 24
Finished May 26 02:56:45 PM PDT 24
Peak memory 247456 kb
Host smart-33b9f835-3fb4-4606-a2fe-b99662c3e00f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177981768 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.3177981768
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.4026869576
Short name T27
Test name
Test status
Simulation time 148692528230 ps
CPU time 701.45 seconds
Started May 26 01:57:48 PM PDT 24
Finished May 26 02:09:30 PM PDT 24
Peak memory 225028 kb
Host smart-08c49804-28fc-4802-a92c-a4a24cbba134
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026869576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.4026869576
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3819730536
Short name T20
Test name
Test status
Simulation time 3123768875 ps
CPU time 61.94 seconds
Started May 26 01:58:34 PM PDT 24
Finished May 26 01:59:36 PM PDT 24
Peak memory 219204 kb
Host smart-1d00f5ac-bf92-4a66-8c84-afc8c5bc25f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819730536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3819730536
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3291766053
Short name T74
Test name
Test status
Simulation time 3079951768 ps
CPU time 98.06 seconds
Started May 26 01:57:37 PM PDT 24
Finished May 26 01:59:16 PM PDT 24
Peak memory 214616 kb
Host smart-465f9256-3524-4059-9785-8a0678f6b9ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291766053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3291766053
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2905991810
Short name T31
Test name
Test status
Simulation time 1750124911 ps
CPU time 239.71 seconds
Started May 26 01:57:45 PM PDT 24
Finished May 26 02:01:46 PM PDT 24
Peak memory 237792 kb
Host smart-300cfc84-86b8-4122-83d5-6b217370dfc0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905991810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2905991810
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3445001427
Short name T14
Test name
Test status
Simulation time 44372596358 ps
CPU time 123.86 seconds
Started May 26 01:57:55 PM PDT 24
Finished May 26 02:00:00 PM PDT 24
Peak memory 221568 kb
Host smart-3883e3b0-8286-4bf6-83b8-97b7e756cdd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445001427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3445001427
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3327841914
Short name T92
Test name
Test status
Simulation time 37959767748 ps
CPU time 166.92 seconds
Started May 26 01:57:36 PM PDT 24
Finished May 26 02:00:24 PM PDT 24
Peak memory 215452 kb
Host smart-5a88824c-d78a-476b-926e-ae40562b68c6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327841914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3327841914
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3715202078
Short name T131
Test name
Test status
Simulation time 706637121 ps
CPU time 166.15 seconds
Started May 26 01:57:29 PM PDT 24
Finished May 26 02:00:18 PM PDT 24
Peak memory 214120 kb
Host smart-991eb25f-667f-4341-b877-309162b172b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715202078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3715202078
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1022935449
Short name T132
Test name
Test status
Simulation time 10676355914 ps
CPU time 166.58 seconds
Started May 26 01:57:37 PM PDT 24
Finished May 26 02:00:25 PM PDT 24
Peak memory 214276 kb
Host smart-08819cf4-c51f-4d22-b876-b6c5d89f407f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022935449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1022935449
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.746940312
Short name T34
Test name
Test status
Simulation time 1964891721 ps
CPU time 15.03 seconds
Started May 26 01:58:35 PM PDT 24
Finished May 26 01:58:51 PM PDT 24
Peak memory 211752 kb
Host smart-686df1c3-8b9e-4196-9f91-99c7cf5e1a2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746940312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.746940312
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3948424311
Short name T18
Test name
Test status
Simulation time 703823066 ps
CPU time 18.83 seconds
Started May 26 01:58:03 PM PDT 24
Finished May 26 01:58:24 PM PDT 24
Peak memory 214572 kb
Host smart-16b78680-e0a9-4d76-be32-69042b111980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948424311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3948424311
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1812762196
Short name T156
Test name
Test status
Simulation time 6818098218 ps
CPU time 30.18 seconds
Started May 26 01:57:49 PM PDT 24
Finished May 26 01:58:20 PM PDT 24
Peak memory 214336 kb
Host smart-307af976-9152-4eba-9d01-922941827c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812762196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1812762196
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.261545599
Short name T23
Test name
Test status
Simulation time 5251616079 ps
CPU time 28.72 seconds
Started May 26 01:59:11 PM PDT 24
Finished May 26 01:59:41 PM PDT 24
Peak memory 213836 kb
Host smart-90ca5352-fd92-475a-b899-ebca95112d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261545599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.261545599
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.620751212
Short name T129
Test name
Test status
Simulation time 4169397185 ps
CPU time 163.66 seconds
Started May 26 01:57:43 PM PDT 24
Finished May 26 02:00:28 PM PDT 24
Peak memory 213996 kb
Host smart-b5ad79b0-b0c1-48b0-adb7-d6ce1ca208a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620751212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.620751212
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.301353671
Short name T117
Test name
Test status
Simulation time 32926512489 ps
CPU time 134.73 seconds
Started May 26 01:57:43 PM PDT 24
Finished May 26 01:59:59 PM PDT 24
Peak memory 215408 kb
Host smart-f4703686-1502-4514-b242-68a12aa050b0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301353671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.301353671
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2866543661
Short name T16
Test name
Test status
Simulation time 181812723541 ps
CPU time 1745.16 seconds
Started May 26 01:59:18 PM PDT 24
Finished May 26 02:28:24 PM PDT 24
Peak memory 238528 kb
Host smart-1654057f-e080-42e4-8278-f0d5b6f3c890
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866543661 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2866543661
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2909805648
Short name T123
Test name
Test status
Simulation time 5616856421 ps
CPU time 160.26 seconds
Started May 26 01:57:43 PM PDT 24
Finished May 26 02:00:24 PM PDT 24
Peak memory 214404 kb
Host smart-075987b7-bfdd-4954-b622-492aeb544d06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909805648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2909805648
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2283797516
Short name T104
Test name
Test status
Simulation time 53409004140 ps
CPU time 27.02 seconds
Started May 26 01:57:47 PM PDT 24
Finished May 26 01:58:15 PM PDT 24
Peak memory 212428 kb
Host smart-13d7a44b-3eaa-4053-b5c0-76368b7cee06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283797516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2283797516
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3998015485
Short name T105
Test name
Test status
Simulation time 2368136338 ps
CPU time 24.77 seconds
Started May 26 01:58:01 PM PDT 24
Finished May 26 01:58:28 PM PDT 24
Peak memory 211232 kb
Host smart-522e07c1-a0c9-46e0-bd99-ecb18e873d5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3998015485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3998015485
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3352329713
Short name T94
Test name
Test status
Simulation time 5510787401 ps
CPU time 25.27 seconds
Started May 26 01:57:30 PM PDT 24
Finished May 26 01:57:59 PM PDT 24
Peak memory 212288 kb
Host smart-82597b01-c4aa-4ab0-9ab7-c3154049ed2e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352329713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3352329713
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2712174683
Short name T363
Test name
Test status
Simulation time 8606486179 ps
CPU time 19.54 seconds
Started May 26 01:57:37 PM PDT 24
Finished May 26 01:57:58 PM PDT 24
Peak memory 211948 kb
Host smart-71173479-cbd6-44b5-ad72-c9ff2e881f15
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712174683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2712174683
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4151183222
Short name T98
Test name
Test status
Simulation time 1396471872 ps
CPU time 11.96 seconds
Started May 26 01:57:30 PM PDT 24
Finished May 26 01:57:45 PM PDT 24
Peak memory 211848 kb
Host smart-ce248a53-15dd-4651-9954-489df89f3a9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151183222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.4151183222
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4222728317
Short name T405
Test name
Test status
Simulation time 931624039 ps
CPU time 16.19 seconds
Started May 26 01:57:30 PM PDT 24
Finished May 26 01:57:49 PM PDT 24
Peak memory 217820 kb
Host smart-62ed7b03-28e9-4891-8c63-29f8c97b3687
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222728317 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.4222728317
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2025998167
Short name T88
Test name
Test status
Simulation time 292077579 ps
CPU time 8.49 seconds
Started May 26 01:58:07 PM PDT 24
Finished May 26 01:58:16 PM PDT 24
Peak memory 211332 kb
Host smart-e78cefb6-4e4e-46cc-b2a1-81ab71a03a3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025998167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2025998167
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2332105613
Short name T362
Test name
Test status
Simulation time 7729286485 ps
CPU time 17.4 seconds
Started May 26 01:57:33 PM PDT 24
Finished May 26 01:57:54 PM PDT 24
Peak memory 211252 kb
Host smart-610c6a21-9cf2-4e41-852a-0d408aa79c67
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332105613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2332105613
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2723312696
Short name T377
Test name
Test status
Simulation time 7327745100 ps
CPU time 28.6 seconds
Started May 26 01:57:30 PM PDT 24
Finished May 26 01:58:02 PM PDT 24
Peak memory 211332 kb
Host smart-b000e36b-e717-4916-95f9-04fe98174a5b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723312696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2723312696
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1238011263
Short name T444
Test name
Test status
Simulation time 2126729340 ps
CPU time 50.63 seconds
Started May 26 01:57:30 PM PDT 24
Finished May 26 01:58:23 PM PDT 24
Peak memory 213356 kb
Host smart-050e3540-56d1-4f0c-8751-c8cd5e9e8c6b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238011263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1238011263
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1278647346
Short name T422
Test name
Test status
Simulation time 2732386033 ps
CPU time 10.73 seconds
Started May 26 01:57:31 PM PDT 24
Finished May 26 01:57:45 PM PDT 24
Peak memory 211732 kb
Host smart-8586a172-1a8d-4739-b251-35e3012c6976
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278647346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1278647346
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.37346024
Short name T393
Test name
Test status
Simulation time 167438094 ps
CPU time 11.62 seconds
Started May 26 01:57:31 PM PDT 24
Finished May 26 01:57:46 PM PDT 24
Peak memory 217412 kb
Host smart-eca3f429-c538-4663-a402-20d0340c57c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37346024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.37346024
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3131879030
Short name T420
Test name
Test status
Simulation time 16241167950 ps
CPU time 106.5 seconds
Started May 26 01:57:32 PM PDT 24
Finished May 26 01:59:22 PM PDT 24
Peak memory 219564 kb
Host smart-55a6f5ce-8808-44b5-ac1f-e6527a4873ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131879030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3131879030
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2759893737
Short name T442
Test name
Test status
Simulation time 214126632 ps
CPU time 8.23 seconds
Started May 26 01:57:32 PM PDT 24
Finished May 26 01:57:44 PM PDT 24
Peak memory 211252 kb
Host smart-47c69e4a-15d4-4243-8dd5-3753e0f64617
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759893737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2759893737
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3734018411
Short name T391
Test name
Test status
Simulation time 7497651144 ps
CPU time 29.93 seconds
Started May 26 01:57:32 PM PDT 24
Finished May 26 01:58:05 PM PDT 24
Peak memory 212480 kb
Host smart-0774a5a2-9881-4f91-afc0-da84b9d2870a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734018411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3734018411
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.479072617
Short name T438
Test name
Test status
Simulation time 2954360692 ps
CPU time 28.76 seconds
Started May 26 01:57:33 PM PDT 24
Finished May 26 01:58:05 PM PDT 24
Peak memory 212040 kb
Host smart-2246e269-aafa-4ed0-84a2-7838712b81d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479072617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.479072617
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3215141969
Short name T449
Test name
Test status
Simulation time 6193905138 ps
CPU time 17.56 seconds
Started May 26 01:57:31 PM PDT 24
Finished May 26 01:57:52 PM PDT 24
Peak memory 214240 kb
Host smart-653b11f0-c1d5-4775-8ef8-786f280ced5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215141969 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3215141969
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3648168437
Short name T90
Test name
Test status
Simulation time 12458602606 ps
CPU time 29.71 seconds
Started May 26 01:57:29 PM PDT 24
Finished May 26 01:58:02 PM PDT 24
Peak memory 212232 kb
Host smart-ad6086d7-b13a-4b99-98c1-561f7945ee21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648168437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3648168437
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2781122435
Short name T361
Test name
Test status
Simulation time 2423948229 ps
CPU time 12.31 seconds
Started May 26 01:57:32 PM PDT 24
Finished May 26 01:57:47 PM PDT 24
Peak memory 211268 kb
Host smart-fd7e6b77-0b36-478d-9a86-459ee5de2ce1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781122435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2781122435
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3396976815
Short name T404
Test name
Test status
Simulation time 8462510901 ps
CPU time 31.01 seconds
Started May 26 01:57:30 PM PDT 24
Finished May 26 01:58:04 PM PDT 24
Peak memory 211316 kb
Host smart-5c789d44-b257-4cf7-8b16-0884b85d5f4a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396976815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3396976815
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1465804486
Short name T455
Test name
Test status
Simulation time 92694834345 ps
CPU time 196.78 seconds
Started May 26 01:57:32 PM PDT 24
Finished May 26 02:00:52 PM PDT 24
Peak memory 215592 kb
Host smart-e2d837d4-f87f-4830-9e21-20d56fc3674f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465804486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1465804486
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3189823537
Short name T79
Test name
Test status
Simulation time 1010083574 ps
CPU time 14.46 seconds
Started May 26 01:57:36 PM PDT 24
Finished May 26 01:57:52 PM PDT 24
Peak memory 211076 kb
Host smart-f60407b0-0ab1-4f51-85f1-9fc06b3ca388
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189823537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3189823537
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1071383009
Short name T453
Test name
Test status
Simulation time 169248576 ps
CPU time 11.78 seconds
Started May 26 01:57:30 PM PDT 24
Finished May 26 01:57:45 PM PDT 24
Peak memory 217252 kb
Host smart-b2daf627-6ce4-4727-abb8-efba34907b74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071383009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1071383009
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3176288397
Short name T121
Test name
Test status
Simulation time 3263589078 ps
CPU time 98.52 seconds
Started May 26 01:57:28 PM PDT 24
Finished May 26 01:59:09 PM PDT 24
Peak memory 213440 kb
Host smart-408468ea-a5d4-48f7-8125-62d36e788963
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176288397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3176288397
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2448872306
Short name T416
Test name
Test status
Simulation time 5414286368 ps
CPU time 17.68 seconds
Started May 26 01:57:46 PM PDT 24
Finished May 26 01:58:04 PM PDT 24
Peak memory 218196 kb
Host smart-24f90d2d-bb83-4c3e-b6df-cc0cd8d3313e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448872306 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2448872306
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2325087350
Short name T114
Test name
Test status
Simulation time 4089232271 ps
CPU time 28.24 seconds
Started May 26 01:57:43 PM PDT 24
Finished May 26 01:58:13 PM PDT 24
Peak memory 211556 kb
Host smart-28e8a460-e7c9-405f-a663-f32d027a5bb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325087350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2325087350
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1408399449
Short name T427
Test name
Test status
Simulation time 5009490393 ps
CPU time 22.39 seconds
Started May 26 01:57:38 PM PDT 24
Finished May 26 01:58:02 PM PDT 24
Peak memory 212720 kb
Host smart-77584cf3-81bc-4ae4-9bd7-3a9ff853200d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408399449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1408399449
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.340206861
Short name T66
Test name
Test status
Simulation time 26005921236 ps
CPU time 37.34 seconds
Started May 26 01:57:37 PM PDT 24
Finished May 26 01:58:16 PM PDT 24
Peak memory 217720 kb
Host smart-866d5bd6-c7cc-46f3-a3a0-a7222551851d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340206861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.340206861
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3339734398
Short name T375
Test name
Test status
Simulation time 15430784549 ps
CPU time 30.92 seconds
Started May 26 01:57:38 PM PDT 24
Finished May 26 01:58:10 PM PDT 24
Peak memory 219644 kb
Host smart-1a857b0a-a9a7-45fc-83b0-6fab29d49a66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339734398 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3339734398
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3933352838
Short name T374
Test name
Test status
Simulation time 419940521 ps
CPU time 11.31 seconds
Started May 26 01:57:39 PM PDT 24
Finished May 26 01:57:52 PM PDT 24
Peak memory 211328 kb
Host smart-072df43a-04d2-4bb4-979b-7aaa783928c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933352838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3933352838
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2493347194
Short name T376
Test name
Test status
Simulation time 72290311764 ps
CPU time 107.24 seconds
Started May 26 01:57:37 PM PDT 24
Finished May 26 01:59:26 PM PDT 24
Peak memory 213408 kb
Host smart-8d2af0b3-6fae-403d-ba21-3109eec95def
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493347194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2493347194
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2004636288
Short name T77
Test name
Test status
Simulation time 3473045187 ps
CPU time 17.79 seconds
Started May 26 01:57:39 PM PDT 24
Finished May 26 01:57:58 PM PDT 24
Peak memory 212696 kb
Host smart-c39f14c3-8d06-4830-b2e4-d84bd437f00d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004636288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2004636288
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.400094147
Short name T428
Test name
Test status
Simulation time 869526499 ps
CPU time 11.3 seconds
Started May 26 01:57:40 PM PDT 24
Finished May 26 01:57:52 PM PDT 24
Peak memory 217380 kb
Host smart-1b28adb2-df2f-4eac-8aff-d2753667598b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400094147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.400094147
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.802160841
Short name T125
Test name
Test status
Simulation time 7878580068 ps
CPU time 100.77 seconds
Started May 26 01:57:39 PM PDT 24
Finished May 26 01:59:21 PM PDT 24
Peak memory 219560 kb
Host smart-23e0eaf4-6112-4b9e-8e3e-36fad817bed8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802160841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.802160841
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2624941976
Short name T360
Test name
Test status
Simulation time 16409939170 ps
CPU time 33.56 seconds
Started May 26 01:57:43 PM PDT 24
Finished May 26 01:58:18 PM PDT 24
Peak memory 217568 kb
Host smart-4304694a-ed5f-49b9-9d4d-20f749fa959c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624941976 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2624941976
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1271017945
Short name T386
Test name
Test status
Simulation time 345296220 ps
CPU time 8.17 seconds
Started May 26 01:57:42 PM PDT 24
Finished May 26 01:57:50 PM PDT 24
Peak memory 211316 kb
Host smart-d3827f9f-9007-49c1-b503-f0f52727a4e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271017945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1271017945
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.114173562
Short name T447
Test name
Test status
Simulation time 4352870734 ps
CPU time 21.81 seconds
Started May 26 01:57:39 PM PDT 24
Finished May 26 01:58:02 PM PDT 24
Peak memory 212664 kb
Host smart-f8afcd08-cf9f-477d-91d8-37ce5f21ed0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114173562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.114173562
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1447333335
Short name T436
Test name
Test status
Simulation time 2066670230 ps
CPU time 16.52 seconds
Started May 26 01:57:40 PM PDT 24
Finished May 26 01:57:57 PM PDT 24
Peak memory 218548 kb
Host smart-173276b5-5856-417a-80b8-bd3a9c59abf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447333335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1447333335
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.170128666
Short name T76
Test name
Test status
Simulation time 841121392 ps
CPU time 160.31 seconds
Started May 26 01:57:46 PM PDT 24
Finished May 26 02:00:27 PM PDT 24
Peak memory 214152 kb
Host smart-39474471-9132-47f5-93b7-e39449266001
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170128666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.170128666
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.206708940
Short name T434
Test name
Test status
Simulation time 201798802 ps
CPU time 9.48 seconds
Started May 26 01:57:37 PM PDT 24
Finished May 26 01:57:48 PM PDT 24
Peak memory 217096 kb
Host smart-c04c3b60-d6e6-4e66-9d68-0e8944dd233b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206708940 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.206708940
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1157812132
Short name T439
Test name
Test status
Simulation time 15203950405 ps
CPU time 32.94 seconds
Started May 26 01:57:40 PM PDT 24
Finished May 26 01:58:14 PM PDT 24
Peak memory 212200 kb
Host smart-fd7d1fa1-59a6-4e61-876a-e5457cfcbd16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157812132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1157812132
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.543282563
Short name T116
Test name
Test status
Simulation time 2357565064 ps
CPU time 53.56 seconds
Started May 26 01:57:39 PM PDT 24
Finished May 26 01:58:34 PM PDT 24
Peak memory 213460 kb
Host smart-a1e8a1e3-b9ef-44ae-913b-e70e0994ca48
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543282563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.543282563
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3187127297
Short name T446
Test name
Test status
Simulation time 1704717713 ps
CPU time 11.25 seconds
Started May 26 01:57:37 PM PDT 24
Finished May 26 01:57:49 PM PDT 24
Peak memory 211332 kb
Host smart-12bea88c-24c3-4093-917e-5ac40afc139a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187127297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3187127297
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2183306093
Short name T451
Test name
Test status
Simulation time 4535929541 ps
CPU time 24.69 seconds
Started May 26 01:57:38 PM PDT 24
Finished May 26 01:58:04 PM PDT 24
Peak memory 218972 kb
Host smart-ae30117e-b708-4d36-b7ed-0ad939e10f8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183306093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2183306093
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3660309447
Short name T127
Test name
Test status
Simulation time 2390064044 ps
CPU time 93.4 seconds
Started May 26 01:57:43 PM PDT 24
Finished May 26 01:59:18 PM PDT 24
Peak memory 212508 kb
Host smart-0cb9168f-316c-43a5-b122-0511aa086771
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660309447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3660309447
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.129917840
Short name T364
Test name
Test status
Simulation time 180967190 ps
CPU time 9.02 seconds
Started May 26 01:57:36 PM PDT 24
Finished May 26 01:57:46 PM PDT 24
Peak memory 219576 kb
Host smart-12a27542-180e-4d6f-b17b-43daafb7a4cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129917840 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.129917840
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.834893195
Short name T103
Test name
Test status
Simulation time 338762523 ps
CPU time 8.25 seconds
Started May 26 01:57:39 PM PDT 24
Finished May 26 01:57:49 PM PDT 24
Peak memory 211320 kb
Host smart-d4c47b34-9dee-41ca-971c-188332d9eb82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834893195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.834893195
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4032963667
Short name T414
Test name
Test status
Simulation time 1076220920 ps
CPU time 56.53 seconds
Started May 26 01:57:39 PM PDT 24
Finished May 26 01:58:36 PM PDT 24
Peak memory 213380 kb
Host smart-1042c922-5b9b-4a31-8b5c-03e3d3007d6a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032963667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.4032963667
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3256666672
Short name T111
Test name
Test status
Simulation time 72108025410 ps
CPU time 31.54 seconds
Started May 26 01:57:44 PM PDT 24
Finished May 26 01:58:17 PM PDT 24
Peak memory 212832 kb
Host smart-69c91a85-9649-46d6-b273-a65aeb241eb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256666672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3256666672
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3965688083
Short name T441
Test name
Test status
Simulation time 14765527094 ps
CPU time 33.73 seconds
Started May 26 01:57:45 PM PDT 24
Finished May 26 01:58:20 PM PDT 24
Peak memory 218972 kb
Host smart-20441486-c024-406e-b5b1-89b0ef7d9b2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965688083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3965688083
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.898737798
Short name T128
Test name
Test status
Simulation time 12675078782 ps
CPU time 100.05 seconds
Started May 26 01:57:42 PM PDT 24
Finished May 26 01:59:22 PM PDT 24
Peak memory 214704 kb
Host smart-960d753c-2e14-4adb-86a7-427fefe51a78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898737798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.898737798
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3829546173
Short name T388
Test name
Test status
Simulation time 6413514035 ps
CPU time 28.31 seconds
Started May 26 01:57:37 PM PDT 24
Finished May 26 01:58:06 PM PDT 24
Peak memory 219588 kb
Host smart-7ffb946a-9627-48f2-a033-734485dd3452
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829546173 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3829546173
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1204887686
Short name T102
Test name
Test status
Simulation time 16179501109 ps
CPU time 30.38 seconds
Started May 26 01:57:37 PM PDT 24
Finished May 26 01:58:09 PM PDT 24
Peak memory 212272 kb
Host smart-8eb59b90-b110-4d01-8fb1-041f829d5172
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204887686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1204887686
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2892304418
Short name T429
Test name
Test status
Simulation time 10314960197 ps
CPU time 70.31 seconds
Started May 26 01:57:46 PM PDT 24
Finished May 26 01:58:57 PM PDT 24
Peak memory 215460 kb
Host smart-41311b45-2c68-4b66-b1de-c2f65c573e6a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892304418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2892304418
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1608407108
Short name T410
Test name
Test status
Simulation time 1754888150 ps
CPU time 15.12 seconds
Started May 26 01:57:40 PM PDT 24
Finished May 26 01:57:56 PM PDT 24
Peak memory 211308 kb
Host smart-ce68fbac-e04c-49e6-a35a-b7431c760335
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608407108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1608407108
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.154602257
Short name T387
Test name
Test status
Simulation time 689244281 ps
CPU time 13.2 seconds
Started May 26 01:57:45 PM PDT 24
Finished May 26 01:58:00 PM PDT 24
Peak memory 217604 kb
Host smart-b8d197e6-b488-4826-8041-38cd75f1ded7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154602257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.154602257
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.754158168
Short name T383
Test name
Test status
Simulation time 3072583392 ps
CPU time 11.12 seconds
Started May 26 01:57:46 PM PDT 24
Finished May 26 01:57:58 PM PDT 24
Peak memory 219632 kb
Host smart-9ab39827-242a-4ce9-8684-91a9e0071dfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754158168 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.754158168
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1991191166
Short name T426
Test name
Test status
Simulation time 2607397398 ps
CPU time 22.61 seconds
Started May 26 01:57:46 PM PDT 24
Finished May 26 01:58:09 PM PDT 24
Peak memory 212080 kb
Host smart-43b2abd1-e63f-4420-a9d1-d1df9ee8c203
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991191166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1991191166
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3052550349
Short name T433
Test name
Test status
Simulation time 725364553 ps
CPU time 38.72 seconds
Started May 26 01:57:43 PM PDT 24
Finished May 26 01:58:23 PM PDT 24
Peak memory 213124 kb
Host smart-641908aa-aba6-43ee-aed7-c5ee5f65a676
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052550349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3052550349
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1137229335
Short name T112
Test name
Test status
Simulation time 3781534080 ps
CPU time 23.9 seconds
Started May 26 01:57:39 PM PDT 24
Finished May 26 01:58:04 PM PDT 24
Peak memory 212520 kb
Host smart-2e226041-a65e-4f11-8b1e-0ef5c5988bae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137229335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1137229335
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3991675668
Short name T65
Test name
Test status
Simulation time 5343607765 ps
CPU time 19.66 seconds
Started May 26 01:57:41 PM PDT 24
Finished May 26 01:58:02 PM PDT 24
Peak memory 218788 kb
Host smart-c49cf1e9-f9fe-420c-ab30-85c2a32998b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991675668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3991675668
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.277608747
Short name T133
Test name
Test status
Simulation time 12969205424 ps
CPU time 169.57 seconds
Started May 26 01:57:39 PM PDT 24
Finished May 26 02:00:30 PM PDT 24
Peak memory 214292 kb
Host smart-598579f5-39de-4dfb-a8bb-8b12c9d13b4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277608747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.277608747
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1724863556
Short name T372
Test name
Test status
Simulation time 3956206844 ps
CPU time 31.8 seconds
Started May 26 01:57:38 PM PDT 24
Finished May 26 01:58:11 PM PDT 24
Peak memory 215404 kb
Host smart-57c882e8-4584-4b78-8f43-8c0f97d839e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724863556 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1724863556
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3340812194
Short name T368
Test name
Test status
Simulation time 6664216426 ps
CPU time 19.55 seconds
Started May 26 01:57:42 PM PDT 24
Finished May 26 01:58:02 PM PDT 24
Peak memory 212432 kb
Host smart-de10decf-2ce3-4a2a-9b82-e690085b703e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340812194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3340812194
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3503266808
Short name T89
Test name
Test status
Simulation time 43990154525 ps
CPU time 101.48 seconds
Started May 26 01:57:44 PM PDT 24
Finished May 26 01:59:27 PM PDT 24
Peak memory 214536 kb
Host smart-3d51d016-a279-40e7-8f64-e067395083d8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503266808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3503266808
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.770781293
Short name T87
Test name
Test status
Simulation time 597938333 ps
CPU time 12.28 seconds
Started May 26 01:57:44 PM PDT 24
Finished May 26 01:57:58 PM PDT 24
Peak memory 211484 kb
Host smart-47227328-5853-4be5-bef9-f65389113d68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770781293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.770781293
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1304440266
Short name T412
Test name
Test status
Simulation time 170973927 ps
CPU time 13.12 seconds
Started May 26 01:57:37 PM PDT 24
Finished May 26 01:57:52 PM PDT 24
Peak memory 217568 kb
Host smart-84d1e61d-968f-4f7f-869b-53fe57c0bd73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304440266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1304440266
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2211185977
Short name T126
Test name
Test status
Simulation time 3365829299 ps
CPU time 100.34 seconds
Started May 26 01:57:42 PM PDT 24
Finished May 26 01:59:23 PM PDT 24
Peak memory 213576 kb
Host smart-79267c70-f533-400b-b6b4-b97228366845
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211185977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2211185977
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2779792974
Short name T401
Test name
Test status
Simulation time 3311401414 ps
CPU time 14.56 seconds
Started May 26 01:57:44 PM PDT 24
Finished May 26 01:57:59 PM PDT 24
Peak memory 216788 kb
Host smart-51aa0109-0df3-4c02-bed2-ef500d5192fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779792974 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2779792974
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2492114836
Short name T115
Test name
Test status
Simulation time 941654827 ps
CPU time 14.36 seconds
Started May 26 01:57:48 PM PDT 24
Finished May 26 01:58:03 PM PDT 24
Peak memory 211308 kb
Host smart-6d0fefa4-c408-4bb1-bbb5-6683c80733a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492114836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2492114836
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.158893966
Short name T101
Test name
Test status
Simulation time 1375728510 ps
CPU time 37.27 seconds
Started May 26 01:57:45 PM PDT 24
Finished May 26 01:58:23 PM PDT 24
Peak memory 213748 kb
Host smart-dea9dc1c-d749-492d-9fb9-679fd1732919
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158893966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.158893966
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3160275592
Short name T91
Test name
Test status
Simulation time 4787308166 ps
CPU time 16.11 seconds
Started May 26 01:57:46 PM PDT 24
Finished May 26 01:58:03 PM PDT 24
Peak memory 212880 kb
Host smart-87500354-ece7-4558-b995-15e95689f173
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160275592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3160275592
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1046536475
Short name T403
Test name
Test status
Simulation time 3574148006 ps
CPU time 22.55 seconds
Started May 26 01:57:46 PM PDT 24
Finished May 26 01:58:10 PM PDT 24
Peak memory 217568 kb
Host smart-2b2a6b03-d1ed-4209-97ad-4539aa6b57fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046536475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1046536475
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3294986271
Short name T430
Test name
Test status
Simulation time 285031354 ps
CPU time 80.11 seconds
Started May 26 01:57:48 PM PDT 24
Finished May 26 01:59:09 PM PDT 24
Peak memory 213852 kb
Host smart-a55faf06-83f6-40b5-aab2-fbf41abb3377
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294986271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3294986271
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.606790690
Short name T431
Test name
Test status
Simulation time 4308538389 ps
CPU time 20.93 seconds
Started May 26 01:57:46 PM PDT 24
Finished May 26 01:58:08 PM PDT 24
Peak memory 218908 kb
Host smart-3c3e69b8-7558-4428-9f92-4adb61cff6de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606790690 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.606790690
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3059453830
Short name T440
Test name
Test status
Simulation time 51118373336 ps
CPU time 94.98 seconds
Started May 26 01:57:50 PM PDT 24
Finished May 26 01:59:25 PM PDT 24
Peak memory 213800 kb
Host smart-d8e27836-1cb9-4266-ab6b-ee746d2fb59b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059453830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3059453830
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4001823092
Short name T381
Test name
Test status
Simulation time 1923141739 ps
CPU time 14.94 seconds
Started May 26 01:57:44 PM PDT 24
Finished May 26 01:58:01 PM PDT 24
Peak memory 211396 kb
Host smart-e425894b-87bd-4a7f-8d0a-803244f0ea2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001823092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.4001823092
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2301918320
Short name T373
Test name
Test status
Simulation time 167806456 ps
CPU time 11.73 seconds
Started May 26 01:57:47 PM PDT 24
Finished May 26 01:58:00 PM PDT 24
Peak memory 217180 kb
Host smart-fdb33cc5-6d9f-49c9-b57f-ff39b6ff7926
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301918320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2301918320
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.123564963
Short name T124
Test name
Test status
Simulation time 38170715894 ps
CPU time 170.11 seconds
Started May 26 01:57:47 PM PDT 24
Finished May 26 02:00:38 PM PDT 24
Peak memory 214156 kb
Host smart-4a83d1c4-54e0-435f-ae3f-02e2c19caec9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123564963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.123564963
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3510391899
Short name T380
Test name
Test status
Simulation time 5566615741 ps
CPU time 25.77 seconds
Started May 26 01:57:31 PM PDT 24
Finished May 26 01:58:00 PM PDT 24
Peak memory 212240 kb
Host smart-b64af66f-2e8b-4b41-8966-7b76affb43f5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510391899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3510391899
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.620912288
Short name T397
Test name
Test status
Simulation time 3098970267 ps
CPU time 26.86 seconds
Started May 26 01:57:33 PM PDT 24
Finished May 26 01:58:03 PM PDT 24
Peak memory 211404 kb
Host smart-6317146f-5452-4f18-b3df-dd00fa4bdab0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620912288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.620912288
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1794994621
Short name T389
Test name
Test status
Simulation time 2181208403 ps
CPU time 18.82 seconds
Started May 26 01:57:35 PM PDT 24
Finished May 26 01:57:56 PM PDT 24
Peak memory 211752 kb
Host smart-5497bf61-d3a0-450c-a348-60d37891ab80
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794994621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1794994621
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2701566353
Short name T432
Test name
Test status
Simulation time 12936990361 ps
CPU time 21.15 seconds
Started May 26 01:57:32 PM PDT 24
Finished May 26 01:57:56 PM PDT 24
Peak memory 216772 kb
Host smart-b5f60b19-49d9-45a8-aee3-64d117cce0fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701566353 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2701566353
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2098374625
Short name T99
Test name
Test status
Simulation time 3580888364 ps
CPU time 28.55 seconds
Started May 26 01:57:30 PM PDT 24
Finished May 26 01:58:02 PM PDT 24
Peak memory 211800 kb
Host smart-c7db9fcc-26fb-46a3-9ac9-4d90cf9c27ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098374625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2098374625
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.686659114
Short name T399
Test name
Test status
Simulation time 3779016924 ps
CPU time 30.42 seconds
Started May 26 01:57:31 PM PDT 24
Finished May 26 01:58:05 PM PDT 24
Peak memory 211236 kb
Host smart-e09ba270-c1c8-48cb-a6d5-3b3a8d9b4847
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686659114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.686659114
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1558007696
Short name T359
Test name
Test status
Simulation time 1026704022 ps
CPU time 9.82 seconds
Started May 26 01:57:32 PM PDT 24
Finished May 26 01:57:45 PM PDT 24
Peak memory 211236 kb
Host smart-a6592f6d-877e-4317-b9b2-939be60308db
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558007696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1558007696
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2549684382
Short name T435
Test name
Test status
Simulation time 4950479615 ps
CPU time 71.38 seconds
Started May 26 01:57:33 PM PDT 24
Finished May 26 01:58:47 PM PDT 24
Peak memory 214456 kb
Host smart-1aab245c-087f-40fc-9996-3fb2993c0a11
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549684382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2549684382
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3210816351
Short name T421
Test name
Test status
Simulation time 2154899978 ps
CPU time 15.53 seconds
Started May 26 01:57:33 PM PDT 24
Finished May 26 01:57:51 PM PDT 24
Peak memory 211528 kb
Host smart-11caa58a-1fda-4393-a05c-ea810a68aedc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210816351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3210816351
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.930468148
Short name T370
Test name
Test status
Simulation time 1968920426 ps
CPU time 25.27 seconds
Started May 26 01:57:31 PM PDT 24
Finished May 26 01:57:59 PM PDT 24
Peak memory 217464 kb
Host smart-78da6457-ac3f-41c7-b2c2-0605a8a1bfe9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930468148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.930468148
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4161823345
Short name T408
Test name
Test status
Simulation time 4809066903 ps
CPU time 23.44 seconds
Started May 26 01:57:30 PM PDT 24
Finished May 26 01:57:57 PM PDT 24
Peak memory 212032 kb
Host smart-42908941-92c1-4d13-ac82-e706a1170973
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161823345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.4161823345
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1155072414
Short name T450
Test name
Test status
Simulation time 13748498173 ps
CPU time 32.79 seconds
Started May 26 01:57:34 PM PDT 24
Finished May 26 01:58:09 PM PDT 24
Peak memory 212260 kb
Host smart-3e55abe1-470b-46d4-a9e4-4db68ac46366
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155072414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1155072414
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3782136317
Short name T415
Test name
Test status
Simulation time 10909201998 ps
CPU time 27.99 seconds
Started May 26 01:57:32 PM PDT 24
Finished May 26 01:58:04 PM PDT 24
Peak memory 211920 kb
Host smart-1741dc33-61b8-470e-8b9a-95440e08436f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782136317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3782136317
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.44766506
Short name T369
Test name
Test status
Simulation time 1822652394 ps
CPU time 19.57 seconds
Started May 26 01:57:32 PM PDT 24
Finished May 26 01:57:55 PM PDT 24
Peak memory 214436 kb
Host smart-38a178bf-764b-4670-92ad-0244eb661ca0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44766506 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.44766506
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1509744120
Short name T452
Test name
Test status
Simulation time 5527144583 ps
CPU time 24.21 seconds
Started May 26 01:57:33 PM PDT 24
Finished May 26 01:58:00 PM PDT 24
Peak memory 212120 kb
Host smart-3fb37a5c-c4c4-460e-b863-49b4e2c566fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509744120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1509744120
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2514479348
Short name T379
Test name
Test status
Simulation time 1096238947 ps
CPU time 14.57 seconds
Started May 26 01:57:30 PM PDT 24
Finished May 26 01:57:48 PM PDT 24
Peak memory 211144 kb
Host smart-c0d4d50a-9a36-4c50-98a4-0e0dde2b34da
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514479348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2514479348
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.271458062
Short name T371
Test name
Test status
Simulation time 10227619393 ps
CPU time 22.06 seconds
Started May 26 01:57:31 PM PDT 24
Finished May 26 01:57:56 PM PDT 24
Peak memory 211304 kb
Host smart-8ff50fbe-093a-4c25-8d83-63f20cb7e891
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271458062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
271458062
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3916965357
Short name T95
Test name
Test status
Simulation time 16913318563 ps
CPU time 128.09 seconds
Started May 26 01:57:33 PM PDT 24
Finished May 26 01:59:44 PM PDT 24
Peak memory 213524 kb
Host smart-a4111fd2-9b9f-41b6-99dd-926aa48238f6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916965357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3916965357
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3350294885
Short name T110
Test name
Test status
Simulation time 8775771010 ps
CPU time 28.23 seconds
Started May 26 01:57:31 PM PDT 24
Finished May 26 01:58:02 PM PDT 24
Peak memory 212696 kb
Host smart-f8f3f3fd-9ef9-4843-b7e0-e3742b2a059d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350294885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3350294885
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2078292476
Short name T378
Test name
Test status
Simulation time 24529999205 ps
CPU time 21.66 seconds
Started May 26 01:57:32 PM PDT 24
Finished May 26 01:57:57 PM PDT 24
Peak memory 217688 kb
Host smart-1d7bbf67-7b44-4e18-a624-d0e8749659e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078292476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2078292476
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.468879765
Short name T437
Test name
Test status
Simulation time 596294705 ps
CPU time 85.01 seconds
Started May 26 01:57:33 PM PDT 24
Finished May 26 01:59:01 PM PDT 24
Peak memory 213460 kb
Host smart-84bf2589-5175-4e9c-9779-96dff14236ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468879765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.468879765
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1011892814
Short name T395
Test name
Test status
Simulation time 6851562178 ps
CPU time 27.01 seconds
Started May 26 01:57:33 PM PDT 24
Finished May 26 01:58:03 PM PDT 24
Peak memory 211772 kb
Host smart-9444bf92-22f9-404f-a68d-ca325cb6e8d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011892814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1011892814
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3486428098
Short name T417
Test name
Test status
Simulation time 2173504476 ps
CPU time 15.31 seconds
Started May 26 01:57:33 PM PDT 24
Finished May 26 01:57:51 PM PDT 24
Peak memory 211368 kb
Host smart-c06e7aa5-52f3-4d5a-a7bd-a84d1aa665c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486428098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3486428098
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4247695924
Short name T448
Test name
Test status
Simulation time 4455543350 ps
CPU time 22.55 seconds
Started May 26 01:57:39 PM PDT 24
Finished May 26 01:58:03 PM PDT 24
Peak memory 212548 kb
Host smart-9988e55b-68e6-498e-968c-57f031cf9cae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247695924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4247695924
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.213809485
Short name T418
Test name
Test status
Simulation time 2571342292 ps
CPU time 24.26 seconds
Started May 26 01:57:33 PM PDT 24
Finished May 26 01:58:01 PM PDT 24
Peak memory 217368 kb
Host smart-be1175d6-3734-4a80-ad08-b23ea9cfb202
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213809485 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.213809485
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.80129105
Short name T443
Test name
Test status
Simulation time 494689766 ps
CPU time 11.61 seconds
Started May 26 01:57:39 PM PDT 24
Finished May 26 01:57:51 PM PDT 24
Peak memory 211284 kb
Host smart-0e392b1c-bab7-404c-9677-b883f7b007a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80129105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.80129105
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3520983373
Short name T419
Test name
Test status
Simulation time 6646628692 ps
CPU time 26.34 seconds
Started May 26 01:57:33 PM PDT 24
Finished May 26 01:58:03 PM PDT 24
Peak memory 211232 kb
Host smart-2c51befb-c3bc-43e6-97ea-cfa867db8dba
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520983373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3520983373
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3256176355
Short name T390
Test name
Test status
Simulation time 12075849349 ps
CPU time 23.94 seconds
Started May 26 01:57:31 PM PDT 24
Finished May 26 01:57:58 PM PDT 24
Peak memory 211300 kb
Host smart-4248ec97-384e-450a-b2c8-2a7e2390004e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256176355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3256176355
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.4217092181
Short name T120
Test name
Test status
Simulation time 17637851111 ps
CPU time 69.2 seconds
Started May 26 01:57:32 PM PDT 24
Finished May 26 01:58:45 PM PDT 24
Peak memory 214472 kb
Host smart-57b52857-f5d4-4f4d-80fc-078205724cab
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217092181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.4217092181
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3992664732
Short name T392
Test name
Test status
Simulation time 5686718095 ps
CPU time 24.83 seconds
Started May 26 01:57:33 PM PDT 24
Finished May 26 01:58:01 PM PDT 24
Peak memory 212296 kb
Host smart-ad3885ed-f639-4252-8b74-3a527aa77875
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992664732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3992664732
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1964647911
Short name T409
Test name
Test status
Simulation time 8597974656 ps
CPU time 22.47 seconds
Started May 26 01:57:31 PM PDT 24
Finished May 26 01:57:57 PM PDT 24
Peak memory 217736 kb
Host smart-f9105706-36b2-476d-94eb-fadbc67bfd8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964647911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1964647911
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1632705392
Short name T134
Test name
Test status
Simulation time 16633962837 ps
CPU time 92.31 seconds
Started May 26 01:57:39 PM PDT 24
Finished May 26 01:59:13 PM PDT 24
Peak memory 213968 kb
Host smart-8c8ba168-5bce-436e-a1c6-a769db441f68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632705392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1632705392
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.31528711
Short name T411
Test name
Test status
Simulation time 585955894 ps
CPU time 12.33 seconds
Started May 26 01:57:33 PM PDT 24
Finished May 26 01:57:49 PM PDT 24
Peak memory 213972 kb
Host smart-14979139-0fb4-4c73-9a41-7e1d9de84d79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31528711 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.31528711
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2413180210
Short name T385
Test name
Test status
Simulation time 42490230776 ps
CPU time 21.7 seconds
Started May 26 01:57:36 PM PDT 24
Finished May 26 01:57:59 PM PDT 24
Peak memory 212352 kb
Host smart-bba889d3-688b-4a90-829a-f645bc22cca2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413180210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2413180210
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2257847798
Short name T100
Test name
Test status
Simulation time 26284257878 ps
CPU time 114.52 seconds
Started May 26 01:57:38 PM PDT 24
Finished May 26 01:59:34 PM PDT 24
Peak memory 214464 kb
Host smart-5861e41a-70bb-4827-a1d9-bfeed5364c4e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257847798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2257847798
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2183112756
Short name T425
Test name
Test status
Simulation time 331916710 ps
CPU time 8.4 seconds
Started May 26 01:57:34 PM PDT 24
Finished May 26 01:57:45 PM PDT 24
Peak memory 211608 kb
Host smart-934f3cf1-c7bb-49fe-a727-65693bc0ef2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183112756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2183112756
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3757160854
Short name T365
Test name
Test status
Simulation time 2819925229 ps
CPU time 27.92 seconds
Started May 26 01:57:30 PM PDT 24
Finished May 26 01:58:01 PM PDT 24
Peak memory 216988 kb
Host smart-f07aa5bf-d4f6-4be1-947c-58d50c1f5b37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757160854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3757160854
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.503780178
Short name T122
Test name
Test status
Simulation time 3953950840 ps
CPU time 103.22 seconds
Started May 26 01:57:33 PM PDT 24
Finished May 26 01:59:20 PM PDT 24
Peak memory 213788 kb
Host smart-02865759-ad0b-4806-94cf-d629a6adf992
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503780178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.503780178
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1567497977
Short name T454
Test name
Test status
Simulation time 9320412504 ps
CPU time 22.45 seconds
Started May 26 01:57:34 PM PDT 24
Finished May 26 01:57:59 PM PDT 24
Peak memory 217220 kb
Host smart-91828efd-c385-4257-b740-7c1a8daab87e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567497977 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1567497977
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3339358137
Short name T367
Test name
Test status
Simulation time 167807602 ps
CPU time 8.45 seconds
Started May 26 01:57:34 PM PDT 24
Finished May 26 01:57:45 PM PDT 24
Peak memory 211316 kb
Host smart-46996861-4110-44be-ad60-6f31c25eb871
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339358137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3339358137
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.108640714
Short name T366
Test name
Test status
Simulation time 45341298812 ps
CPU time 124.38 seconds
Started May 26 01:57:34 PM PDT 24
Finished May 26 01:59:41 PM PDT 24
Peak memory 215556 kb
Host smart-572b7ad4-384b-4613-b9a9-52273378c3ed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108640714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.108640714
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.119466841
Short name T93
Test name
Test status
Simulation time 14207828456 ps
CPU time 27.68 seconds
Started May 26 01:57:37 PM PDT 24
Finished May 26 01:58:06 PM PDT 24
Peak memory 212756 kb
Host smart-cee5b0a1-5b26-46fb-9e38-f2e0f71c569b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119466841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.119466841
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3527172801
Short name T424
Test name
Test status
Simulation time 4026270229 ps
CPU time 25.12 seconds
Started May 26 01:57:31 PM PDT 24
Finished May 26 01:58:00 PM PDT 24
Peak memory 217564 kb
Host smart-95665d5f-3a77-46dc-8815-57d5d210dd27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527172801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3527172801
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1427516210
Short name T130
Test name
Test status
Simulation time 4394546579 ps
CPU time 94.19 seconds
Started May 26 01:57:34 PM PDT 24
Finished May 26 01:59:11 PM PDT 24
Peak memory 213668 kb
Host smart-7981f3a7-1d3a-4d84-bda9-dbf61d2ee916
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427516210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1427516210
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2368572441
Short name T382
Test name
Test status
Simulation time 9965746176 ps
CPU time 22.68 seconds
Started May 26 01:57:33 PM PDT 24
Finished May 26 01:57:59 PM PDT 24
Peak memory 217156 kb
Host smart-3e6ab631-51e7-4b1f-b1da-63eebc1fc209
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368572441 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2368572441
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2450016457
Short name T394
Test name
Test status
Simulation time 16476714862 ps
CPU time 29.61 seconds
Started May 26 01:57:37 PM PDT 24
Finished May 26 01:58:08 PM PDT 24
Peak memory 212412 kb
Host smart-f2d8d017-ef5d-4101-a24b-767e660a4134
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450016457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2450016457
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2984961192
Short name T400
Test name
Test status
Simulation time 2988180585 ps
CPU time 38.25 seconds
Started May 26 01:57:37 PM PDT 24
Finished May 26 01:58:17 PM PDT 24
Peak memory 213628 kb
Host smart-82e11d7b-fea2-4b6b-a4ab-9b7a8ad90364
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984961192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2984961192
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.579627252
Short name T398
Test name
Test status
Simulation time 524549641 ps
CPU time 11.97 seconds
Started May 26 01:57:34 PM PDT 24
Finished May 26 01:57:49 PM PDT 24
Peak memory 211416 kb
Host smart-507866f1-25f6-487b-9b04-4bf254fc5b71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579627252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.579627252
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1685373298
Short name T396
Test name
Test status
Simulation time 19461657040 ps
CPU time 30.77 seconds
Started May 26 01:57:37 PM PDT 24
Finished May 26 01:58:09 PM PDT 24
Peak memory 217764 kb
Host smart-1cdd44b7-352f-4c44-8dae-119db5b56f54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685373298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1685373298
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4105456288
Short name T413
Test name
Test status
Simulation time 1810403379 ps
CPU time 19.06 seconds
Started May 26 01:57:37 PM PDT 24
Finished May 26 01:57:57 PM PDT 24
Peak memory 214364 kb
Host smart-740e9b5d-5530-49a4-8f8a-ddd7f1c4edb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105456288 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.4105456288
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.175970926
Short name T402
Test name
Test status
Simulation time 12308457091 ps
CPU time 17.53 seconds
Started May 26 01:57:31 PM PDT 24
Finished May 26 01:57:52 PM PDT 24
Peak memory 212388 kb
Host smart-3362879d-8850-4c25-85b0-e071716d98f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175970926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.175970926
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1526861293
Short name T384
Test name
Test status
Simulation time 7064118831 ps
CPU time 46.85 seconds
Started May 26 01:57:37 PM PDT 24
Finished May 26 01:58:25 PM PDT 24
Peak memory 214464 kb
Host smart-1374c9ea-3854-49fd-a3fd-9d2a2680b313
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526861293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1526861293
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3946235015
Short name T86
Test name
Test status
Simulation time 9499032182 ps
CPU time 19.96 seconds
Started May 26 01:57:31 PM PDT 24
Finished May 26 01:57:55 PM PDT 24
Peak memory 212644 kb
Host smart-ff4d1b7f-6985-4d65-9a86-f4e38c8b5059
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946235015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3946235015
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2022699478
Short name T406
Test name
Test status
Simulation time 3007180850 ps
CPU time 20.74 seconds
Started May 26 01:57:37 PM PDT 24
Finished May 26 01:57:59 PM PDT 24
Peak memory 218696 kb
Host smart-9bfa6726-8458-418e-b237-19192ff564df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022699478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2022699478
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3585643449
Short name T407
Test name
Test status
Simulation time 738541847 ps
CPU time 8.75 seconds
Started May 26 01:57:44 PM PDT 24
Finished May 26 01:57:53 PM PDT 24
Peak memory 216476 kb
Host smart-018b30f3-255e-4ea3-9548-1691ea8d85fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585643449 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3585643449
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.883060885
Short name T423
Test name
Test status
Simulation time 25198237316 ps
CPU time 32.16 seconds
Started May 26 01:57:39 PM PDT 24
Finished May 26 01:58:12 PM PDT 24
Peak memory 212404 kb
Host smart-2651e2d6-7804-4280-8db3-71d2b7118ddc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883060885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.883060885
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3040146330
Short name T78
Test name
Test status
Simulation time 1611895701 ps
CPU time 18.06 seconds
Started May 26 01:57:42 PM PDT 24
Finished May 26 01:58:01 PM PDT 24
Peak memory 212376 kb
Host smart-39cfde57-7718-4b20-aa95-9c151cf392dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040146330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3040146330
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3771041682
Short name T445
Test name
Test status
Simulation time 688927834 ps
CPU time 12.65 seconds
Started May 26 01:57:38 PM PDT 24
Finished May 26 01:57:52 PM PDT 24
Peak memory 217520 kb
Host smart-69736d57-b62b-45ca-b099-2b149522202e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771041682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3771041682
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3169269300
Short name T75
Test name
Test status
Simulation time 507449982 ps
CPU time 84.19 seconds
Started May 26 01:57:38 PM PDT 24
Finished May 26 01:59:03 PM PDT 24
Peak memory 213636 kb
Host smart-3f98e767-4e5d-43e8-a7a3-1c5b8a3b6ca1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169269300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3169269300
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.345498020
Short name T82
Test name
Test status
Simulation time 1208826474 ps
CPU time 16.1 seconds
Started May 26 01:57:46 PM PDT 24
Finished May 26 01:58:03 PM PDT 24
Peak memory 211256 kb
Host smart-c3143d96-9499-4519-9118-cf7cced4d58b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345498020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.345498020
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.237262995
Short name T221
Test name
Test status
Simulation time 471308889753 ps
CPU time 910.28 seconds
Started May 26 01:57:47 PM PDT 24
Finished May 26 02:12:58 PM PDT 24
Peak memory 237232 kb
Host smart-5a7f1fe0-d13a-4404-8495-5c9073b4f015
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237262995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.237262995
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.991029822
Short name T228
Test name
Test status
Simulation time 11878770230 ps
CPU time 64.34 seconds
Started May 26 01:57:52 PM PDT 24
Finished May 26 01:58:57 PM PDT 24
Peak memory 214936 kb
Host smart-a7ae6c90-dff6-44f0-9efd-b070cdfed9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991029822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.991029822
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.4103836460
Short name T324
Test name
Test status
Simulation time 6735878471 ps
CPU time 30.55 seconds
Started May 26 01:57:51 PM PDT 24
Finished May 26 01:58:22 PM PDT 24
Peak memory 211440 kb
Host smart-49a6795c-d76d-4ac4-996e-2d869757e9cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4103836460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.4103836460
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3528632812
Short name T180
Test name
Test status
Simulation time 4657018727 ps
CPU time 30.36 seconds
Started May 26 01:57:47 PM PDT 24
Finished May 26 01:58:19 PM PDT 24
Peak memory 217236 kb
Host smart-bfc5dd7f-a1c5-49b2-8c47-116c17bd8161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528632812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3528632812
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1219543311
Short name T308
Test name
Test status
Simulation time 18137351977 ps
CPU time 23.17 seconds
Started May 26 01:57:49 PM PDT 24
Finished May 26 01:58:13 PM PDT 24
Peak memory 214260 kb
Host smart-2f36ffbd-9337-4e8b-ab5e-0fd0fb755da2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219543311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1219543311
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2177091296
Short name T17
Test name
Test status
Simulation time 121837356413 ps
CPU time 1095.36 seconds
Started May 26 01:57:48 PM PDT 24
Finished May 26 02:16:04 PM PDT 24
Peak memory 235744 kb
Host smart-a98d307f-d4c7-4d77-ad62-70e2168fe90a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177091296 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.2177091296
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4246530765
Short name T290
Test name
Test status
Simulation time 1937599119 ps
CPU time 20.65 seconds
Started May 26 01:57:52 PM PDT 24
Finished May 26 01:58:13 PM PDT 24
Peak memory 211408 kb
Host smart-5d4858fe-649b-46f9-9a10-e81187d32336
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246530765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4246530765
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1248308804
Short name T185
Test name
Test status
Simulation time 2080236690 ps
CPU time 22.77 seconds
Started May 26 01:57:47 PM PDT 24
Finished May 26 01:58:10 PM PDT 24
Peak memory 211196 kb
Host smart-c87c2fa2-e01c-449a-8e4f-9e4fc39cf4ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1248308804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1248308804
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.309180906
Short name T33
Test name
Test status
Simulation time 2465869637 ps
CPU time 228.96 seconds
Started May 26 01:57:52 PM PDT 24
Finished May 26 02:01:42 PM PDT 24
Peak memory 237780 kb
Host smart-76162e3d-b7e1-4a00-af11-fbf9c05d207f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309180906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.309180906
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2343735092
Short name T5
Test name
Test status
Simulation time 28004301636 ps
CPU time 75.43 seconds
Started May 26 01:57:51 PM PDT 24
Finished May 26 01:59:07 PM PDT 24
Peak memory 217468 kb
Host smart-30c7432a-cc58-4929-a49a-477fda3141fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343735092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2343735092
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2094851658
Short name T145
Test name
Test status
Simulation time 174392395 ps
CPU time 8.58 seconds
Started May 26 01:58:00 PM PDT 24
Finished May 26 01:58:09 PM PDT 24
Peak memory 211144 kb
Host smart-b8cf206f-4960-409d-94ae-8e8fbd967131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094851658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2094851658
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.973953808
Short name T200
Test name
Test status
Simulation time 14575478526 ps
CPU time 267.81 seconds
Started May 26 01:58:01 PM PDT 24
Finished May 26 02:02:30 PM PDT 24
Peak memory 237548 kb
Host smart-87504a1c-a1ab-494d-bd27-20d6ed287329
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973953808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.973953808
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2013343967
Short name T237
Test name
Test status
Simulation time 525414992 ps
CPU time 14.44 seconds
Started May 26 01:58:00 PM PDT 24
Finished May 26 01:58:15 PM PDT 24
Peak memory 211248 kb
Host smart-79aeeabb-ed05-449a-8ecc-6cc6df4d857e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2013343967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2013343967
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1767935474
Short name T250
Test name
Test status
Simulation time 25109821314 ps
CPU time 57.76 seconds
Started May 26 01:58:03 PM PDT 24
Finished May 26 01:59:03 PM PDT 24
Peak memory 218000 kb
Host smart-d543a75c-0acd-4c41-8459-3d62109accea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767935474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1767935474
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3094895677
Short name T197
Test name
Test status
Simulation time 57448655261 ps
CPU time 33.31 seconds
Started May 26 01:58:03 PM PDT 24
Finished May 26 01:58:38 PM PDT 24
Peak memory 212104 kb
Host smart-7ba9fba1-b5dd-43b8-9904-086ebf621dcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094895677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3094895677
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.966975775
Short name T318
Test name
Test status
Simulation time 114021209541 ps
CPU time 671.15 seconds
Started May 26 01:58:01 PM PDT 24
Finished May 26 02:09:15 PM PDT 24
Peak memory 240412 kb
Host smart-90577128-682d-457e-948c-c0c373b06c87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966975775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.966975775
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1207152543
Short name T216
Test name
Test status
Simulation time 28761229737 ps
CPU time 61.03 seconds
Started May 26 01:58:04 PM PDT 24
Finished May 26 01:59:06 PM PDT 24
Peak memory 214772 kb
Host smart-43005a15-05fa-49d6-bb35-53008272f263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207152543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1207152543
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3008697934
Short name T22
Test name
Test status
Simulation time 6914168017 ps
CPU time 32.11 seconds
Started May 26 01:58:02 PM PDT 24
Finished May 26 01:58:37 PM PDT 24
Peak memory 218072 kb
Host smart-81e9b3bc-cc7e-43e5-b1a8-d6cab2a15c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008697934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3008697934
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1460199902
Short name T3
Test name
Test status
Simulation time 47370122917 ps
CPU time 149.1 seconds
Started May 26 01:58:02 PM PDT 24
Finished May 26 02:00:34 PM PDT 24
Peak memory 219212 kb
Host smart-a6781816-c7e3-45d0-9eb9-5d551fba4ff7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460199902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1460199902
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2618397830
Short name T157
Test name
Test status
Simulation time 10254065591 ps
CPU time 23.62 seconds
Started May 26 01:58:16 PM PDT 24
Finished May 26 01:58:41 PM PDT 24
Peak memory 212252 kb
Host smart-9ca65644-568d-43dc-aec5-fbeb52a3e28a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618397830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2618397830
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3580908540
Short name T272
Test name
Test status
Simulation time 482801460848 ps
CPU time 966.77 seconds
Started May 26 01:58:14 PM PDT 24
Finished May 26 02:14:22 PM PDT 24
Peak memory 225032 kb
Host smart-1e938301-4225-4497-9444-e0f89d85f329
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580908540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3580908540
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2139681635
Short name T162
Test name
Test status
Simulation time 38156405382 ps
CPU time 69.07 seconds
Started May 26 01:58:13 PM PDT 24
Finished May 26 01:59:23 PM PDT 24
Peak memory 213924 kb
Host smart-f3b18a5c-7901-4e2b-aaef-bd503c52580b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139681635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2139681635
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3252650249
Short name T140
Test name
Test status
Simulation time 3528468265 ps
CPU time 10.77 seconds
Started May 26 01:58:18 PM PDT 24
Finished May 26 01:58:30 PM PDT 24
Peak memory 212612 kb
Host smart-7356fb22-db25-458b-b015-57b83cc922db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3252650249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3252650249
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.998432054
Short name T189
Test name
Test status
Simulation time 49330794572 ps
CPU time 62.59 seconds
Started May 26 01:58:12 PM PDT 24
Finished May 26 01:59:15 PM PDT 24
Peak memory 217300 kb
Host smart-4c8b3ecb-da68-46af-a871-6e8e913bb30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998432054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.998432054
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3644916503
Short name T198
Test name
Test status
Simulation time 2965735991 ps
CPU time 49.14 seconds
Started May 26 01:58:12 PM PDT 24
Finished May 26 01:59:02 PM PDT 24
Peak memory 219200 kb
Host smart-55f9f697-ba41-4b72-9e0e-90b9e263e7bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644916503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3644916503
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2239575537
Short name T67
Test name
Test status
Simulation time 7661879379 ps
CPU time 29.66 seconds
Started May 26 01:58:13 PM PDT 24
Finished May 26 01:58:44 PM PDT 24
Peak memory 212124 kb
Host smart-d19723e8-007a-4a3e-9c40-625145a91a18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239575537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2239575537
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1372371796
Short name T304
Test name
Test status
Simulation time 36488119035 ps
CPU time 395.89 seconds
Started May 26 01:58:18 PM PDT 24
Finished May 26 02:04:55 PM PDT 24
Peak memory 228588 kb
Host smart-06b7944e-8ead-461e-b9fa-8ca6b4458efa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372371796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1372371796
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.100445123
Short name T164
Test name
Test status
Simulation time 6808673001 ps
CPU time 58 seconds
Started May 26 01:58:15 PM PDT 24
Finished May 26 01:59:14 PM PDT 24
Peak memory 214980 kb
Host smart-5d6d462f-6220-4e62-b56a-62d71b759611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100445123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.100445123
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1228704701
Short name T107
Test name
Test status
Simulation time 14904556302 ps
CPU time 24.33 seconds
Started May 26 01:58:12 PM PDT 24
Finished May 26 01:58:37 PM PDT 24
Peak memory 211580 kb
Host smart-e0b07974-f0d5-407b-b968-c1f5ce951467
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1228704701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1228704701
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.4253863120
Short name T254
Test name
Test status
Simulation time 7524260259 ps
CPU time 75.63 seconds
Started May 26 01:58:12 PM PDT 24
Finished May 26 01:59:28 PM PDT 24
Peak memory 216980 kb
Host smart-7690282b-e736-4e08-ba40-c6ee711bfe37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253863120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.4253863120
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3202438277
Short name T201
Test name
Test status
Simulation time 25356127498 ps
CPU time 242.56 seconds
Started May 26 01:58:16 PM PDT 24
Finished May 26 02:02:20 PM PDT 24
Peak memory 221180 kb
Host smart-986b9e57-42da-41d1-858f-ae53698ac278
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202438277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3202438277
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2925493499
Short name T61
Test name
Test status
Simulation time 45100676439 ps
CPU time 1796.38 seconds
Started May 26 01:58:14 PM PDT 24
Finished May 26 02:28:12 PM PDT 24
Peak memory 243820 kb
Host smart-1f4a1b87-edaf-437c-b239-d7dc112988e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925493499 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.2925493499
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2883299349
Short name T136
Test name
Test status
Simulation time 660940629 ps
CPU time 8.33 seconds
Started May 26 01:58:13 PM PDT 24
Finished May 26 01:58:22 PM PDT 24
Peak memory 211200 kb
Host smart-93214d63-6826-4159-877f-80ce1a154e4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883299349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2883299349
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.963466725
Short name T271
Test name
Test status
Simulation time 29174590878 ps
CPU time 224.4 seconds
Started May 26 01:58:14 PM PDT 24
Finished May 26 02:01:59 PM PDT 24
Peak memory 234280 kb
Host smart-593a167e-1552-4fb4-b0bd-9fba906a0416
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963466725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.963466725
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2072057374
Short name T19
Test name
Test status
Simulation time 1320298997 ps
CPU time 18.91 seconds
Started May 26 01:58:17 PM PDT 24
Finished May 26 01:58:37 PM PDT 24
Peak memory 214500 kb
Host smart-539609ab-90c7-43c8-9676-dcb37d0298f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072057374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2072057374
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.609870468
Short name T118
Test name
Test status
Simulation time 304437736 ps
CPU time 10.77 seconds
Started May 26 01:58:11 PM PDT 24
Finished May 26 01:58:23 PM PDT 24
Peak memory 212164 kb
Host smart-013f25ad-bb08-4439-af1f-44ab202e1b1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=609870468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.609870468
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1110899699
Short name T4
Test name
Test status
Simulation time 24021560741 ps
CPU time 56.27 seconds
Started May 26 01:58:14 PM PDT 24
Finished May 26 01:59:11 PM PDT 24
Peak memory 217892 kb
Host smart-310339c6-9368-4fe9-b3ec-d35395854756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110899699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1110899699
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1254882989
Short name T42
Test name
Test status
Simulation time 21826104015 ps
CPU time 101.26 seconds
Started May 26 01:58:20 PM PDT 24
Finished May 26 02:00:02 PM PDT 24
Peak memory 219204 kb
Host smart-05076eba-3c34-4e01-be77-3cdf6d686325
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254882989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1254882989
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1207684578
Short name T210
Test name
Test status
Simulation time 2569827219 ps
CPU time 22.95 seconds
Started May 26 01:58:19 PM PDT 24
Finished May 26 01:58:42 PM PDT 24
Peak memory 211260 kb
Host smart-4a9078d0-f69d-4523-a6e8-226c7ae235f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207684578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1207684578
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3589427766
Short name T286
Test name
Test status
Simulation time 76139217096 ps
CPU time 945.05 seconds
Started May 26 01:58:15 PM PDT 24
Finished May 26 02:14:01 PM PDT 24
Peak memory 226556 kb
Host smart-efe34bf3-8acd-4c1d-ac37-d593eada03c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589427766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3589427766
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1297911793
Short name T280
Test name
Test status
Simulation time 346159877 ps
CPU time 19.22 seconds
Started May 26 01:58:20 PM PDT 24
Finished May 26 01:58:40 PM PDT 24
Peak memory 214832 kb
Host smart-4df9139c-6d28-48fe-bc43-68c54acfd51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297911793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1297911793
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1423887389
Short name T153
Test name
Test status
Simulation time 12436893470 ps
CPU time 32.42 seconds
Started May 26 01:58:17 PM PDT 24
Finished May 26 01:58:50 PM PDT 24
Peak memory 212756 kb
Host smart-b8e9bfdd-c517-4a82-b7cb-ca8093c9c863
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1423887389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1423887389
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.351656228
Short name T97
Test name
Test status
Simulation time 1695823487 ps
CPU time 32.49 seconds
Started May 26 01:58:18 PM PDT 24
Finished May 26 01:58:51 PM PDT 24
Peak memory 213876 kb
Host smart-020c9087-bfeb-4881-8713-3b24b074b228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351656228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.351656228
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1616838261
Short name T230
Test name
Test status
Simulation time 29457986607 ps
CPU time 68.69 seconds
Started May 26 01:58:15 PM PDT 24
Finished May 26 01:59:25 PM PDT 24
Peak memory 217080 kb
Host smart-2e9414e6-e3f9-405a-8451-f1eccb624c57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616838261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1616838261
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3956864919
Short name T214
Test name
Test status
Simulation time 56663172153 ps
CPU time 32.94 seconds
Started May 26 01:58:12 PM PDT 24
Finished May 26 01:58:45 PM PDT 24
Peak memory 212116 kb
Host smart-ef066724-29e0-41b6-bddb-188ab70bac02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956864919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3956864919
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.4177252029
Short name T202
Test name
Test status
Simulation time 170150574599 ps
CPU time 487.63 seconds
Started May 26 01:58:13 PM PDT 24
Finished May 26 02:06:21 PM PDT 24
Peak memory 237596 kb
Host smart-b0ac1bb9-897f-4da2-b133-875215c61cc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177252029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.4177252029
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.198790118
Short name T289
Test name
Test status
Simulation time 30060198991 ps
CPU time 66.15 seconds
Started May 26 01:58:15 PM PDT 24
Finished May 26 01:59:23 PM PDT 24
Peak memory 214792 kb
Host smart-3a94031d-f273-4650-a8ad-9bd07f5fd8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198790118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.198790118
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.883620320
Short name T309
Test name
Test status
Simulation time 3993155904 ps
CPU time 33.56 seconds
Started May 26 01:58:12 PM PDT 24
Finished May 26 01:58:47 PM PDT 24
Peak memory 211328 kb
Host smart-50515f7b-6cd2-466d-ac73-922bcbdb4ea8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=883620320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.883620320
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1164989577
Short name T168
Test name
Test status
Simulation time 5066529054 ps
CPU time 48.92 seconds
Started May 26 01:58:19 PM PDT 24
Finished May 26 01:59:09 PM PDT 24
Peak memory 217472 kb
Host smart-3549fa5d-3b5e-4e35-9e36-fb54a9e324eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164989577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1164989577
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1059509550
Short name T243
Test name
Test status
Simulation time 105079122102 ps
CPU time 81.51 seconds
Started May 26 01:58:13 PM PDT 24
Finished May 26 01:59:36 PM PDT 24
Peak memory 219244 kb
Host smart-037e10a2-c126-45c0-98a9-c52adff48cc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059509550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1059509550
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2354463220
Short name T338
Test name
Test status
Simulation time 1905936715 ps
CPU time 20.5 seconds
Started May 26 01:58:14 PM PDT 24
Finished May 26 01:58:35 PM PDT 24
Peak memory 211744 kb
Host smart-b3c01e2b-84bf-4950-8ee7-7b5a1622d9fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354463220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2354463220
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.111855220
Short name T199
Test name
Test status
Simulation time 305483458568 ps
CPU time 747.79 seconds
Started May 26 01:58:15 PM PDT 24
Finished May 26 02:10:45 PM PDT 24
Peak memory 225144 kb
Host smart-721671c6-3112-4cc0-b874-b9a017074054
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111855220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.111855220
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.836315150
Short name T277
Test name
Test status
Simulation time 2123846546 ps
CPU time 28.75 seconds
Started May 26 01:58:15 PM PDT 24
Finished May 26 01:58:45 PM PDT 24
Peak memory 214480 kb
Host smart-5619ea2c-85fb-41e0-9e3b-ec7b001076f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836315150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.836315150
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2353069121
Short name T21
Test name
Test status
Simulation time 4191872340 ps
CPU time 35.36 seconds
Started May 26 01:58:15 PM PDT 24
Finished May 26 01:58:52 PM PDT 24
Peak memory 212240 kb
Host smart-ac848f6d-0e88-441b-bde8-61d380e1753a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2353069121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2353069121
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2657864713
Short name T306
Test name
Test status
Simulation time 3993015977 ps
CPU time 27.93 seconds
Started May 26 01:58:15 PM PDT 24
Finished May 26 01:58:44 PM PDT 24
Peak memory 217164 kb
Host smart-69606f8b-0687-45f2-9bbd-f0e1feaa8ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657864713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2657864713
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3297378792
Short name T84
Test name
Test status
Simulation time 37777087094 ps
CPU time 213.48 seconds
Started May 26 01:58:18 PM PDT 24
Finished May 26 02:01:52 PM PDT 24
Peak memory 221212 kb
Host smart-a69c210c-77cb-4d27-b658-a1cecf99027e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297378792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3297378792
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2652446407
Short name T356
Test name
Test status
Simulation time 2841006138 ps
CPU time 26.13 seconds
Started May 26 01:58:13 PM PDT 24
Finished May 26 01:58:39 PM PDT 24
Peak memory 211276 kb
Host smart-d9491104-b68b-4f9e-82b7-2df0b3b386fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652446407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2652446407
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.96821716
Short name T169
Test name
Test status
Simulation time 57326061703 ps
CPU time 533.41 seconds
Started May 26 01:58:19 PM PDT 24
Finished May 26 02:07:14 PM PDT 24
Peak memory 233548 kb
Host smart-8574c6de-c60a-4142-8e8e-51aa8bf12a62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96821716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_co
rrupt_sig_fatal_chk.96821716
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.767308258
Short name T285
Test name
Test status
Simulation time 2064216439 ps
CPU time 18.99 seconds
Started May 26 01:58:19 PM PDT 24
Finished May 26 01:58:39 PM PDT 24
Peak memory 214680 kb
Host smart-20bbcde8-d9e9-4398-8e0e-113c77751ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767308258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.767308258
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1315711241
Short name T10
Test name
Test status
Simulation time 17144888668 ps
CPU time 36.89 seconds
Started May 26 01:58:13 PM PDT 24
Finished May 26 01:58:51 PM PDT 24
Peak memory 212724 kb
Host smart-369572e8-181d-48ab-b286-c0ea9ba8adcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1315711241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1315711241
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.207921708
Short name T295
Test name
Test status
Simulation time 31599690965 ps
CPU time 54.36 seconds
Started May 26 01:58:13 PM PDT 24
Finished May 26 01:59:08 PM PDT 24
Peak memory 218108 kb
Host smart-13fe67f8-422d-4e09-915e-b13ed026210e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207921708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.207921708
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3664662261
Short name T183
Test name
Test status
Simulation time 2832069235 ps
CPU time 46.45 seconds
Started May 26 01:58:13 PM PDT 24
Finished May 26 01:59:01 PM PDT 24
Peak memory 219244 kb
Host smart-70558a62-67d3-48c1-94c9-491caeea9e80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664662261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3664662261
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1390643008
Short name T299
Test name
Test status
Simulation time 11357324691 ps
CPU time 24.76 seconds
Started May 26 01:58:16 PM PDT 24
Finished May 26 01:58:42 PM PDT 24
Peak memory 212044 kb
Host smart-f19e14ea-dde8-461c-859a-a7c7e3434ef9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390643008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1390643008
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1040056078
Short name T26
Test name
Test status
Simulation time 608848618117 ps
CPU time 607.42 seconds
Started May 26 01:58:12 PM PDT 24
Finished May 26 02:08:20 PM PDT 24
Peak memory 240592 kb
Host smart-651101bd-a674-4558-8b90-147a2efa04af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040056078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1040056078
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2203215974
Short name T177
Test name
Test status
Simulation time 18383379661 ps
CPU time 46.31 seconds
Started May 26 01:58:18 PM PDT 24
Finished May 26 01:59:05 PM PDT 24
Peak memory 213820 kb
Host smart-c1ecac71-6a5a-41b6-8bbc-6b7b0f3a107b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203215974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2203215974
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.961417098
Short name T47
Test name
Test status
Simulation time 189790020 ps
CPU time 10.64 seconds
Started May 26 01:58:16 PM PDT 24
Finished May 26 01:58:28 PM PDT 24
Peak memory 212268 kb
Host smart-b20d0d0b-a8c3-4aab-ac2e-8e60782e4362
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=961417098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.961417098
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2618373612
Short name T194
Test name
Test status
Simulation time 34792773915 ps
CPU time 77.03 seconds
Started May 26 01:58:17 PM PDT 24
Finished May 26 01:59:35 PM PDT 24
Peak memory 217804 kb
Host smart-55370606-e69b-4675-9db4-575f14105aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618373612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2618373612
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1788927696
Short name T261
Test name
Test status
Simulation time 1174266967 ps
CPU time 29.5 seconds
Started May 26 01:58:14 PM PDT 24
Finished May 26 01:58:45 PM PDT 24
Peak memory 213688 kb
Host smart-31939546-9604-4a53-a01d-ee5aaf13e49e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788927696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1788927696
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3299126098
Short name T195
Test name
Test status
Simulation time 8499667173 ps
CPU time 32.83 seconds
Started May 26 01:57:55 PM PDT 24
Finished May 26 01:58:29 PM PDT 24
Peak memory 211980 kb
Host smart-b173e32f-5bae-4b06-b875-6c528e0d4eeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299126098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3299126098
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1270014614
Short name T341
Test name
Test status
Simulation time 339729665699 ps
CPU time 830.45 seconds
Started May 26 01:57:53 PM PDT 24
Finished May 26 02:11:45 PM PDT 24
Peak memory 233696 kb
Host smart-d1e5525d-d9c9-4d63-8e69-3bf9200160ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270014614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1270014614
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.210696841
Short name T351
Test name
Test status
Simulation time 13602237912 ps
CPU time 40.34 seconds
Started May 26 01:57:54 PM PDT 24
Finished May 26 01:58:36 PM PDT 24
Peak memory 215000 kb
Host smart-7084000b-39e0-4a66-aca9-0839608f1408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210696841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.210696841
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3944297185
Short name T43
Test name
Test status
Simulation time 1916831320 ps
CPU time 10.55 seconds
Started May 26 01:57:52 PM PDT 24
Finished May 26 01:58:03 PM PDT 24
Peak memory 211456 kb
Host smart-281e9e46-a71c-4ab6-a5d5-36ad9bafce1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3944297185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3944297185
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3148347329
Short name T39
Test name
Test status
Simulation time 2602303657 ps
CPU time 122.58 seconds
Started May 26 01:57:56 PM PDT 24
Finished May 26 02:00:00 PM PDT 24
Peak memory 237032 kb
Host smart-833fcfd6-e61e-4b0f-be72-e42a4348e938
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148347329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3148347329
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1748992559
Short name T283
Test name
Test status
Simulation time 15141100687 ps
CPU time 65.56 seconds
Started May 26 01:57:54 PM PDT 24
Finished May 26 01:59:01 PM PDT 24
Peak memory 217792 kb
Host smart-49128269-5dfb-4cca-aad2-d904e53e719a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748992559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1748992559
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2032047810
Short name T248
Test name
Test status
Simulation time 9165180904 ps
CPU time 32.13 seconds
Started May 26 01:57:55 PM PDT 24
Finished May 26 01:58:28 PM PDT 24
Peak memory 211700 kb
Host smart-2b3bf6e5-9485-462d-95b1-b9f932f28d13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032047810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2032047810
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.729596166
Short name T64
Test name
Test status
Simulation time 57785740665 ps
CPU time 10544.9 seconds
Started May 26 01:57:55 PM PDT 24
Finished May 26 04:53:42 PM PDT 24
Peak memory 235676 kb
Host smart-5fbb19d9-1da3-480b-8a78-3bfe9012b1f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729596166 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.729596166
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.505046473
Short name T307
Test name
Test status
Simulation time 2559292655 ps
CPU time 23.81 seconds
Started May 26 01:58:21 PM PDT 24
Finished May 26 01:58:46 PM PDT 24
Peak memory 211252 kb
Host smart-7007b421-7a2a-4330-87dc-5ab2cd781ab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505046473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.505046473
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3227418841
Short name T51
Test name
Test status
Simulation time 14224889906 ps
CPU time 270.54 seconds
Started May 26 01:58:13 PM PDT 24
Finished May 26 02:02:44 PM PDT 24
Peak memory 219184 kb
Host smart-72989ece-8482-4b5d-90de-72e21354b4b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227418841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3227418841
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.364094651
Short name T327
Test name
Test status
Simulation time 67676923654 ps
CPU time 55.31 seconds
Started May 26 01:58:16 PM PDT 24
Finished May 26 01:59:13 PM PDT 24
Peak memory 213812 kb
Host smart-4205c8d5-a1b3-4448-8652-6002775ac0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364094651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.364094651
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3931161766
Short name T293
Test name
Test status
Simulation time 7148825172 ps
CPU time 21.29 seconds
Started May 26 01:58:15 PM PDT 24
Finished May 26 01:58:38 PM PDT 24
Peak memory 211744 kb
Host smart-2782baeb-4779-4b0d-b4e0-e9d3f2ee951a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3931161766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3931161766
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.4051763625
Short name T172
Test name
Test status
Simulation time 358900120 ps
CPU time 20.14 seconds
Started May 26 01:58:16 PM PDT 24
Finished May 26 01:58:37 PM PDT 24
Peak memory 216948 kb
Host smart-e017811c-ef84-4a0a-9da5-f38093e9a21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051763625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.4051763625
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2914992196
Short name T215
Test name
Test status
Simulation time 10540097181 ps
CPU time 64.75 seconds
Started May 26 01:58:18 PM PDT 24
Finished May 26 01:59:24 PM PDT 24
Peak memory 219188 kb
Host smart-280ecc98-0f5d-4142-b151-804d1c9fe044
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914992196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2914992196
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3675468820
Short name T63
Test name
Test status
Simulation time 32399012124 ps
CPU time 10724.2 seconds
Started May 26 01:58:16 PM PDT 24
Finished May 26 04:57:02 PM PDT 24
Peak memory 237724 kb
Host smart-ce032a12-4f63-41b6-ae3a-51287e27cdd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675468820 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.3675468820
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1353454760
Short name T46
Test name
Test status
Simulation time 424436939 ps
CPU time 8.41 seconds
Started May 26 01:58:23 PM PDT 24
Finished May 26 01:58:32 PM PDT 24
Peak memory 211248 kb
Host smart-eba44f15-58fa-42ac-b096-8a203db29d58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353454760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1353454760
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1571382581
Short name T312
Test name
Test status
Simulation time 14828038201 ps
CPU time 271.76 seconds
Started May 26 01:58:27 PM PDT 24
Finished May 26 02:02:59 PM PDT 24
Peak memory 224340 kb
Host smart-cf84b01b-73f4-4be0-a48f-b660c56f6dcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571382581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1571382581
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1770353069
Short name T317
Test name
Test status
Simulation time 26111239801 ps
CPU time 56.76 seconds
Started May 26 01:58:22 PM PDT 24
Finished May 26 01:59:20 PM PDT 24
Peak memory 215128 kb
Host smart-bfb251e0-6ace-4a79-a956-3f1447292533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770353069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1770353069
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1209839065
Short name T337
Test name
Test status
Simulation time 8833025878 ps
CPU time 24.42 seconds
Started May 26 01:58:21 PM PDT 24
Finished May 26 01:58:47 PM PDT 24
Peak memory 212524 kb
Host smart-8b31af1f-92eb-49ba-bf7d-fe6953bd4f51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1209839065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1209839065
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1448806507
Short name T186
Test name
Test status
Simulation time 33656921883 ps
CPU time 62.65 seconds
Started May 26 01:58:23 PM PDT 24
Finished May 26 01:59:27 PM PDT 24
Peak memory 217272 kb
Host smart-f80dc4b5-7275-4a80-ab8b-a71e75257ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448806507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1448806507
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.703715233
Short name T163
Test name
Test status
Simulation time 387155234 ps
CPU time 24.81 seconds
Started May 26 01:58:24 PM PDT 24
Finished May 26 01:58:49 PM PDT 24
Peak memory 218448 kb
Host smart-85a4dea3-37e3-4786-b5f2-b365b30a562f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703715233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.703715233
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3349994509
Short name T155
Test name
Test status
Simulation time 750540307 ps
CPU time 8.55 seconds
Started May 26 01:58:20 PM PDT 24
Finished May 26 01:58:30 PM PDT 24
Peak memory 211228 kb
Host smart-e66cafd3-2436-4f6b-95ef-63272a9be09e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349994509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3349994509
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1631823747
Short name T316
Test name
Test status
Simulation time 93480396282 ps
CPU time 883.3 seconds
Started May 26 01:58:22 PM PDT 24
Finished May 26 02:13:06 PM PDT 24
Peak memory 230552 kb
Host smart-b51d1f58-fa46-463f-a5fd-3fba2108f551
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631823747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1631823747
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1379320676
Short name T71
Test name
Test status
Simulation time 1384489817 ps
CPU time 28.55 seconds
Started May 26 01:58:22 PM PDT 24
Finished May 26 01:58:51 PM PDT 24
Peak memory 213492 kb
Host smart-4961abf4-d89c-41b2-9a32-8bbbf2498519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379320676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1379320676
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3116915875
Short name T310
Test name
Test status
Simulation time 1983248267 ps
CPU time 23.02 seconds
Started May 26 01:58:23 PM PDT 24
Finished May 26 01:58:46 PM PDT 24
Peak memory 211088 kb
Host smart-ce454a0a-8386-4690-8002-9bb1dab378aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3116915875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3116915875
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2079377487
Short name T56
Test name
Test status
Simulation time 8068781256 ps
CPU time 65.62 seconds
Started May 26 01:58:25 PM PDT 24
Finished May 26 01:59:31 PM PDT 24
Peak memory 216240 kb
Host smart-9b5012f1-4453-41e6-8541-586e50870cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079377487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2079377487
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1437332736
Short name T161
Test name
Test status
Simulation time 553409346 ps
CPU time 29.72 seconds
Started May 26 01:58:21 PM PDT 24
Finished May 26 01:58:51 PM PDT 24
Peak memory 219184 kb
Host smart-903e36e0-2f4f-4c37-bd77-7e5bd9eda9e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437332736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1437332736
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.690035707
Short name T231
Test name
Test status
Simulation time 2393656326 ps
CPU time 12.78 seconds
Started May 26 01:58:19 PM PDT 24
Finished May 26 01:58:32 PM PDT 24
Peak memory 211316 kb
Host smart-c29dbabc-6e8d-4b92-9a99-e75fbd22ce1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690035707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.690035707
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3543513430
Short name T52
Test name
Test status
Simulation time 102611542846 ps
CPU time 956.01 seconds
Started May 26 01:58:20 PM PDT 24
Finished May 26 02:14:17 PM PDT 24
Peak memory 234096 kb
Host smart-23f81c43-afa6-420c-b5df-626d07706e11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543513430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3543513430
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.4041518577
Short name T167
Test name
Test status
Simulation time 53095534256 ps
CPU time 46.27 seconds
Started May 26 01:58:23 PM PDT 24
Finished May 26 01:59:09 PM PDT 24
Peak memory 213796 kb
Host smart-2cf6aa66-9247-4ab1-875e-dcc9fc545e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041518577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.4041518577
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1364397116
Short name T106
Test name
Test status
Simulation time 3617462183 ps
CPU time 32.13 seconds
Started May 26 01:58:27 PM PDT 24
Finished May 26 01:58:59 PM PDT 24
Peak memory 211252 kb
Host smart-e0752aa1-8d80-49d2-a673-7b88995b3c1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1364397116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1364397116
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1684517216
Short name T70
Test name
Test status
Simulation time 5988003263 ps
CPU time 61.85 seconds
Started May 26 01:58:22 PM PDT 24
Finished May 26 01:59:24 PM PDT 24
Peak memory 217372 kb
Host smart-8b6f1d66-6823-4277-a612-680d5905eac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684517216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1684517216
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1479783114
Short name T160
Test name
Test status
Simulation time 14625546039 ps
CPU time 87.49 seconds
Started May 26 01:58:22 PM PDT 24
Finished May 26 01:59:50 PM PDT 24
Peak memory 221916 kb
Host smart-f7967447-0366-471f-8b86-1a4f946e2bfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479783114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1479783114
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3338384383
Short name T36
Test name
Test status
Simulation time 4392420867 ps
CPU time 21.37 seconds
Started May 26 01:58:27 PM PDT 24
Finished May 26 01:58:49 PM PDT 24
Peak memory 211240 kb
Host smart-5b791190-d5e8-4f80-ba4d-8d6d1e94578e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338384383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3338384383
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3479525880
Short name T54
Test name
Test status
Simulation time 39916462818 ps
CPU time 382.18 seconds
Started May 26 01:58:23 PM PDT 24
Finished May 26 02:04:45 PM PDT 24
Peak memory 233476 kb
Host smart-4ac03db2-a0fa-4633-9276-05ad6d18a6f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479525880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3479525880
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2788118199
Short name T218
Test name
Test status
Simulation time 31340368470 ps
CPU time 65.52 seconds
Started May 26 01:58:22 PM PDT 24
Finished May 26 01:59:28 PM PDT 24
Peak memory 213876 kb
Host smart-21093673-6d13-4bfe-81ec-5d7ffe04e2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788118199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2788118199
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1561265363
Short name T273
Test name
Test status
Simulation time 9652329968 ps
CPU time 24.49 seconds
Started May 26 01:58:20 PM PDT 24
Finished May 26 01:58:46 PM PDT 24
Peak memory 212680 kb
Host smart-77fa2452-09bb-4af1-b864-cca84b7f8fd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1561265363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1561265363
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3064983813
Short name T184
Test name
Test status
Simulation time 4981547597 ps
CPU time 54.99 seconds
Started May 26 01:58:24 PM PDT 24
Finished May 26 01:59:19 PM PDT 24
Peak memory 217320 kb
Host smart-533060b5-0fd2-4f15-8e59-5d5ac1332d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064983813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3064983813
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1195834114
Short name T12
Test name
Test status
Simulation time 12782546799 ps
CPU time 71.91 seconds
Started May 26 01:58:24 PM PDT 24
Finished May 26 01:59:36 PM PDT 24
Peak memory 219036 kb
Host smart-353fd467-c15b-42f0-8ca9-5deaa49aa6ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195834114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1195834114
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1785381735
Short name T165
Test name
Test status
Simulation time 8556926435 ps
CPU time 21.11 seconds
Started May 26 01:58:31 PM PDT 24
Finished May 26 01:58:52 PM PDT 24
Peak memory 212124 kb
Host smart-a8783764-18f2-4f21-99a0-ef9c88d4ad7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785381735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1785381735
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2600934776
Short name T301
Test name
Test status
Simulation time 43067527255 ps
CPU time 390.41 seconds
Started May 26 01:58:34 PM PDT 24
Finished May 26 02:05:05 PM PDT 24
Peak memory 234620 kb
Host smart-17d037f2-de57-4dec-a296-e1d4f09df4b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600934776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2600934776
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1651522387
Short name T276
Test name
Test status
Simulation time 13014246042 ps
CPU time 39.96 seconds
Started May 26 01:58:31 PM PDT 24
Finished May 26 01:59:12 PM PDT 24
Peak memory 214784 kb
Host smart-baea4975-4a23-442e-a73e-57125fd2fd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651522387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1651522387
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3033162084
Short name T37
Test name
Test status
Simulation time 41864366865 ps
CPU time 36.22 seconds
Started May 26 01:58:30 PM PDT 24
Finished May 26 01:59:07 PM PDT 24
Peak memory 211204 kb
Host smart-c17f8f10-e8c4-4512-9757-a8ae59c2f6b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3033162084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3033162084
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1338266130
Short name T358
Test name
Test status
Simulation time 5563474236 ps
CPU time 63.12 seconds
Started May 26 01:58:32 PM PDT 24
Finished May 26 01:59:36 PM PDT 24
Peak memory 218064 kb
Host smart-c4ae4b51-2674-4ef6-910f-46d9af758e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338266130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1338266130
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.685744737
Short name T260
Test name
Test status
Simulation time 8060061799 ps
CPU time 40.37 seconds
Started May 26 01:58:35 PM PDT 24
Finished May 26 01:59:16 PM PDT 24
Peak memory 219208 kb
Host smart-0c959f30-c926-43d3-bc9e-aa94740bd833
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685744737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.685744737
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.4189069792
Short name T60
Test name
Test status
Simulation time 28695073166 ps
CPU time 1243.25 seconds
Started May 26 01:58:31 PM PDT 24
Finished May 26 02:19:15 PM PDT 24
Peak memory 235736 kb
Host smart-93fb03da-23a6-4bde-aeb9-44cc12dbc493
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189069792 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.4189069792
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.711093311
Short name T354
Test name
Test status
Simulation time 6871328444 ps
CPU time 28.94 seconds
Started May 26 01:58:29 PM PDT 24
Finished May 26 01:58:59 PM PDT 24
Peak memory 211988 kb
Host smart-ad057a6a-e919-40d6-b3f0-27dc53edd0bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711093311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.711093311
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1788167501
Short name T321
Test name
Test status
Simulation time 33149116925 ps
CPU time 378.15 seconds
Started May 26 01:58:29 PM PDT 24
Finished May 26 02:04:47 PM PDT 24
Peak memory 235776 kb
Host smart-0ca7ad6e-65cd-4b9a-a105-128ef7a27000
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788167501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1788167501
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4233850448
Short name T279
Test name
Test status
Simulation time 5138431610 ps
CPU time 31.54 seconds
Started May 26 01:58:30 PM PDT 24
Finished May 26 01:59:02 PM PDT 24
Peak memory 214896 kb
Host smart-0bbc8d6a-daac-46fb-b194-62347f319a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233850448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4233850448
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3338583045
Short name T346
Test name
Test status
Simulation time 6332272615 ps
CPU time 27.76 seconds
Started May 26 01:58:28 PM PDT 24
Finished May 26 01:58:56 PM PDT 24
Peak memory 212748 kb
Host smart-3d14897d-9b0d-4e6c-bf11-28d63e367ad3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3338583045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3338583045
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2943129007
Short name T259
Test name
Test status
Simulation time 4320986702 ps
CPU time 44.45 seconds
Started May 26 01:58:35 PM PDT 24
Finished May 26 01:59:21 PM PDT 24
Peak memory 214872 kb
Host smart-27248906-22b6-48a7-a5f1-904ca8c1e99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943129007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2943129007
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3655985242
Short name T267
Test name
Test status
Simulation time 16043540952 ps
CPU time 34.84 seconds
Started May 26 01:58:28 PM PDT 24
Finished May 26 01:59:04 PM PDT 24
Peak memory 211952 kb
Host smart-c39f409a-7399-4203-9222-49a00632f5eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655985242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3655985242
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.861450535
Short name T332
Test name
Test status
Simulation time 23913056776 ps
CPU time 299.76 seconds
Started May 26 01:58:28 PM PDT 24
Finished May 26 02:03:29 PM PDT 24
Peak memory 237712 kb
Host smart-5c132887-5a6b-4abf-ad18-b0d1e23026f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861450535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.861450535
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1751623214
Short name T232
Test name
Test status
Simulation time 13101791165 ps
CPU time 37.35 seconds
Started May 26 01:58:34 PM PDT 24
Finished May 26 01:59:12 PM PDT 24
Peak memory 214804 kb
Host smart-c94881dd-6acd-4837-9e00-de05198024d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751623214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1751623214
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2896174032
Short name T83
Test name
Test status
Simulation time 38648334120 ps
CPU time 35.14 seconds
Started May 26 01:58:32 PM PDT 24
Finished May 26 01:59:07 PM PDT 24
Peak memory 211764 kb
Host smart-f50aa6c9-2e6d-41d2-8c8c-2ff8b5410dc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2896174032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2896174032
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.316762713
Short name T302
Test name
Test status
Simulation time 705631430 ps
CPU time 19.87 seconds
Started May 26 01:58:27 PM PDT 24
Finished May 26 01:58:48 PM PDT 24
Peak memory 214760 kb
Host smart-041f8c74-903c-4c66-a564-c44139675d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316762713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.316762713
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1591798081
Short name T212
Test name
Test status
Simulation time 34180556501 ps
CPU time 75.27 seconds
Started May 26 01:58:32 PM PDT 24
Finished May 26 01:59:48 PM PDT 24
Peak memory 217668 kb
Host smart-35abcdde-7f82-400e-af65-0aa8671c9607
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591798081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1591798081
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.480206567
Short name T193
Test name
Test status
Simulation time 2745592274 ps
CPU time 8.67 seconds
Started May 26 01:58:39 PM PDT 24
Finished May 26 01:58:49 PM PDT 24
Peak memory 211296 kb
Host smart-117df3a6-4b26-4e44-98ba-d2bde231be2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480206567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.480206567
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.767495686
Short name T247
Test name
Test status
Simulation time 20076934928 ps
CPU time 311.83 seconds
Started May 26 01:58:29 PM PDT 24
Finished May 26 02:03:42 PM PDT 24
Peak memory 218040 kb
Host smart-2a6f2666-3701-4627-a1dc-6a100683cf24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767495686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.767495686
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.330856671
Short name T206
Test name
Test status
Simulation time 661351025 ps
CPU time 19.37 seconds
Started May 26 01:58:41 PM PDT 24
Finished May 26 01:59:00 PM PDT 24
Peak memory 214592 kb
Host smart-4cd91c65-cc7c-45a9-946e-9ff99ce62faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330856671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.330856671
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1506127238
Short name T159
Test name
Test status
Simulation time 4025949158 ps
CPU time 22.04 seconds
Started May 26 01:58:35 PM PDT 24
Finished May 26 01:58:58 PM PDT 24
Peak memory 212248 kb
Host smart-0ceea437-cd3e-49f5-b78b-e5a76e35a62e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1506127238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1506127238
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2450291177
Short name T265
Test name
Test status
Simulation time 1816814827 ps
CPU time 23.45 seconds
Started May 26 01:58:32 PM PDT 24
Finished May 26 01:58:56 PM PDT 24
Peak memory 217692 kb
Host smart-22a2c087-8cb7-4dbf-8452-01086d07abf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450291177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2450291177
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.4018507658
Short name T80
Test name
Test status
Simulation time 3070399733 ps
CPU time 13.92 seconds
Started May 26 01:58:38 PM PDT 24
Finished May 26 01:58:54 PM PDT 24
Peak memory 211308 kb
Host smart-f6549e87-d440-426b-90ca-fb72dd6b9636
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018507658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.4018507658
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1474354815
Short name T135
Test name
Test status
Simulation time 49962621618 ps
CPU time 557.84 seconds
Started May 26 01:58:38 PM PDT 24
Finished May 26 02:07:58 PM PDT 24
Peak memory 237620 kb
Host smart-bb7c3d6a-898a-4c79-a54e-3c3ceb88c0fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474354815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1474354815
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.466898119
Short name T334
Test name
Test status
Simulation time 339278450 ps
CPU time 19.82 seconds
Started May 26 01:58:38 PM PDT 24
Finished May 26 01:58:59 PM PDT 24
Peak memory 214468 kb
Host smart-c716d48d-3893-44f2-a3aa-0598d97e935a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466898119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.466898119
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2300710924
Short name T48
Test name
Test status
Simulation time 2436985202 ps
CPU time 14.68 seconds
Started May 26 01:58:38 PM PDT 24
Finished May 26 01:58:54 PM PDT 24
Peak memory 211600 kb
Host smart-5bbd798e-8638-4c9f-8fc4-ffbaa3126572
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2300710924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2300710924
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3075347302
Short name T235
Test name
Test status
Simulation time 24790340211 ps
CPU time 64.94 seconds
Started May 26 01:58:38 PM PDT 24
Finished May 26 01:59:44 PM PDT 24
Peak memory 217268 kb
Host smart-ec2aa866-3901-468d-abc6-e37b18343b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075347302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3075347302
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1482701245
Short name T219
Test name
Test status
Simulation time 102436681932 ps
CPU time 168.14 seconds
Started May 26 01:58:39 PM PDT 24
Finished May 26 02:01:28 PM PDT 24
Peak memory 227620 kb
Host smart-37edb4d5-2d8e-402d-8b9f-2de7356feae2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482701245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1482701245
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2491887606
Short name T166
Test name
Test status
Simulation time 13257469391 ps
CPU time 28.08 seconds
Started May 26 01:57:53 PM PDT 24
Finished May 26 01:58:22 PM PDT 24
Peak memory 212012 kb
Host smart-7a38b5a7-b9c0-4f47-810d-3a174f5ae874
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491887606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2491887606
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1670796124
Short name T41
Test name
Test status
Simulation time 4044895195 ps
CPU time 276.51 seconds
Started May 26 01:57:54 PM PDT 24
Finished May 26 02:02:31 PM PDT 24
Peak memory 240568 kb
Host smart-bec31a81-0306-4d6c-91c3-e321547bf743
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670796124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1670796124
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4014832740
Short name T141
Test name
Test status
Simulation time 9706046687 ps
CPU time 35.9 seconds
Started May 26 01:57:55 PM PDT 24
Finished May 26 01:58:32 PM PDT 24
Peak memory 215696 kb
Host smart-16b56563-1e98-464f-8d05-ddafe2d9e251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014832740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4014832740
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2401589647
Short name T139
Test name
Test status
Simulation time 9316255963 ps
CPU time 31.05 seconds
Started May 26 01:57:53 PM PDT 24
Finished May 26 01:58:25 PM PDT 24
Peak memory 211524 kb
Host smart-1cddf7ce-8374-4106-b912-230783032350
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2401589647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2401589647
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2564131115
Short name T40
Test name
Test status
Simulation time 61625874302 ps
CPU time 248.91 seconds
Started May 26 01:57:50 PM PDT 24
Finished May 26 02:02:00 PM PDT 24
Peak memory 238164 kb
Host smart-f546ae30-8f1a-4c10-afd2-2f25cc1db22e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564131115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2564131115
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2481863111
Short name T225
Test name
Test status
Simulation time 3361989394 ps
CPU time 19.26 seconds
Started May 26 01:57:54 PM PDT 24
Finished May 26 01:58:14 PM PDT 24
Peak memory 215760 kb
Host smart-d9735d5a-ac07-4fbc-a8d6-529c396bbcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481863111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2481863111
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3600277322
Short name T72
Test name
Test status
Simulation time 61704987867 ps
CPU time 183.83 seconds
Started May 26 01:57:52 PM PDT 24
Finished May 26 02:00:57 PM PDT 24
Peak memory 221020 kb
Host smart-80be5ef6-384b-444a-90cd-b47520003973
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600277322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3600277322
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3848847441
Short name T319
Test name
Test status
Simulation time 1754662452 ps
CPU time 19.41 seconds
Started May 26 01:58:39 PM PDT 24
Finished May 26 01:58:59 PM PDT 24
Peak memory 211216 kb
Host smart-d8f09e02-b627-44fe-935b-3de7010a42c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848847441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3848847441
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1354761468
Short name T50
Test name
Test status
Simulation time 36286528892 ps
CPU time 180.97 seconds
Started May 26 01:58:40 PM PDT 24
Finished May 26 02:01:42 PM PDT 24
Peak memory 224396 kb
Host smart-97d4b792-27f1-4b8f-9592-aa8aff6b5386
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354761468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1354761468
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1192952952
Short name T342
Test name
Test status
Simulation time 7717070142 ps
CPU time 43.91 seconds
Started May 26 01:58:38 PM PDT 24
Finished May 26 01:59:23 PM PDT 24
Peak memory 214884 kb
Host smart-6492dc13-1da4-437b-8833-fd6662350db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192952952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1192952952
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3669149878
Short name T113
Test name
Test status
Simulation time 262658316 ps
CPU time 12.06 seconds
Started May 26 01:58:37 PM PDT 24
Finished May 26 01:58:50 PM PDT 24
Peak memory 212208 kb
Host smart-09386d04-2572-4b45-a6c5-c377a74f5546
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3669149878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3669149878
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3389405366
Short name T325
Test name
Test status
Simulation time 8903513247 ps
CPU time 45.35 seconds
Started May 26 01:58:38 PM PDT 24
Finished May 26 01:59:25 PM PDT 24
Peak memory 216940 kb
Host smart-20f8781d-3f83-4602-be50-4262a1de22f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389405366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3389405366
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3032878135
Short name T13
Test name
Test status
Simulation time 24709176801 ps
CPU time 75.42 seconds
Started May 26 01:58:37 PM PDT 24
Finished May 26 01:59:54 PM PDT 24
Peak memory 219236 kb
Host smart-9cc3d2ad-d0c2-4a02-ac5b-87237d08dec0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032878135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3032878135
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3803348423
Short name T335
Test name
Test status
Simulation time 4092211042 ps
CPU time 20.12 seconds
Started May 26 01:58:40 PM PDT 24
Finished May 26 01:59:01 PM PDT 24
Peak memory 211284 kb
Host smart-8664b473-a14c-4818-bd51-2f98341d0262
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803348423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3803348423
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2160036689
Short name T242
Test name
Test status
Simulation time 32238133741 ps
CPU time 324.51 seconds
Started May 26 01:58:37 PM PDT 24
Finished May 26 02:04:03 PM PDT 24
Peak memory 239108 kb
Host smart-4010227f-3a14-4ba2-ad15-58eaaa9303c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160036689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2160036689
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.424874833
Short name T192
Test name
Test status
Simulation time 12478410620 ps
CPU time 36.8 seconds
Started May 26 01:58:38 PM PDT 24
Finished May 26 01:59:16 PM PDT 24
Peak memory 214956 kb
Host smart-4bb5e705-4bf0-4e1f-bd0b-29b4e0cc0c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424874833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.424874833
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.609719028
Short name T298
Test name
Test status
Simulation time 20522144165 ps
CPU time 20.64 seconds
Started May 26 01:58:41 PM PDT 24
Finished May 26 01:59:02 PM PDT 24
Peak memory 211696 kb
Host smart-e531a42b-13ee-4db3-99f2-927a0e5baff0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=609719028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.609719028
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1692206267
Short name T96
Test name
Test status
Simulation time 1169922175 ps
CPU time 29.9 seconds
Started May 26 01:58:36 PM PDT 24
Finished May 26 01:59:07 PM PDT 24
Peak memory 216956 kb
Host smart-76db342a-2674-45a5-9b3f-5a0b826ebfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692206267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1692206267
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3074850504
Short name T329
Test name
Test status
Simulation time 18978529467 ps
CPU time 68.19 seconds
Started May 26 01:58:37 PM PDT 24
Finished May 26 01:59:45 PM PDT 24
Peak memory 215140 kb
Host smart-4eff0b0a-c6f5-4080-8523-80439f13aadc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074850504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3074850504
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.645190276
Short name T208
Test name
Test status
Simulation time 3454391384 ps
CPU time 28.98 seconds
Started May 26 01:58:37 PM PDT 24
Finished May 26 01:59:07 PM PDT 24
Peak memory 211760 kb
Host smart-9a35d810-8aa7-4204-a1a6-8cb2eddd78d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645190276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.645190276
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1000285514
Short name T209
Test name
Test status
Simulation time 47258058633 ps
CPU time 365.21 seconds
Started May 26 01:58:36 PM PDT 24
Finished May 26 02:04:41 PM PDT 24
Peak memory 239976 kb
Host smart-84c23799-9e15-432f-aa95-f23260ef3b0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000285514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1000285514
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.818947885
Short name T239
Test name
Test status
Simulation time 63708483359 ps
CPU time 60.76 seconds
Started May 26 01:58:38 PM PDT 24
Finished May 26 01:59:40 PM PDT 24
Peak memory 213836 kb
Host smart-188c0388-92ed-4598-8a66-a4a6bf3d07fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818947885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.818947885
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3128477196
Short name T151
Test name
Test status
Simulation time 537989684 ps
CPU time 12.12 seconds
Started May 26 01:58:38 PM PDT 24
Finished May 26 01:58:51 PM PDT 24
Peak memory 212532 kb
Host smart-ee6fb304-c50b-4a86-9489-d80821a19258
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3128477196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3128477196
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2482098191
Short name T227
Test name
Test status
Simulation time 21693702231 ps
CPU time 56.76 seconds
Started May 26 01:58:38 PM PDT 24
Finished May 26 01:59:36 PM PDT 24
Peak memory 217020 kb
Host smart-5c5342e0-6e3d-4129-ba4d-b394bd2c6fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482098191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2482098191
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3337025936
Short name T220
Test name
Test status
Simulation time 10330390176 ps
CPU time 137.7 seconds
Started May 26 01:58:38 PM PDT 24
Finished May 26 02:00:57 PM PDT 24
Peak memory 220632 kb
Host smart-b0ac2320-05f1-4d5a-8f5f-8d9c12968df6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337025936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3337025936
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.374131679
Short name T58
Test name
Test status
Simulation time 17296301081 ps
CPU time 34.24 seconds
Started May 26 01:58:41 PM PDT 24
Finished May 26 01:59:15 PM PDT 24
Peak memory 212056 kb
Host smart-3db7ca16-b895-4723-8647-535f0b2eb838
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374131679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.374131679
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3347364356
Short name T59
Test name
Test status
Simulation time 75971751318 ps
CPU time 369.4 seconds
Started May 26 01:58:37 PM PDT 24
Finished May 26 02:04:48 PM PDT 24
Peak memory 228808 kb
Host smart-004d6f24-6317-4ef7-b442-bfe2497921ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347364356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3347364356
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1559835541
Short name T357
Test name
Test status
Simulation time 7034900881 ps
CPU time 61.05 seconds
Started May 26 01:58:37 PM PDT 24
Finished May 26 01:59:40 PM PDT 24
Peak memory 214760 kb
Host smart-c69e225e-7683-4bf6-8394-796600aedbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559835541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1559835541
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2674303798
Short name T249
Test name
Test status
Simulation time 1440756847 ps
CPU time 15.4 seconds
Started May 26 01:58:39 PM PDT 24
Finished May 26 01:58:56 PM PDT 24
Peak memory 212296 kb
Host smart-79f80ddb-f1cc-41e0-8b8a-c55d51e072e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2674303798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2674303798
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.963978200
Short name T8
Test name
Test status
Simulation time 6616466009 ps
CPU time 55.55 seconds
Started May 26 01:58:38 PM PDT 24
Finished May 26 01:59:35 PM PDT 24
Peak memory 217768 kb
Host smart-a829dae9-b6b0-4a94-9c5f-5fadf757b6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963978200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.963978200
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2059736953
Short name T297
Test name
Test status
Simulation time 8051125328 ps
CPU time 66.31 seconds
Started May 26 01:58:37 PM PDT 24
Finished May 26 01:59:45 PM PDT 24
Peak memory 218876 kb
Host smart-b3088bb4-6d40-4886-a44c-60841eea5a36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059736953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2059736953
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3466142034
Short name T305
Test name
Test status
Simulation time 15539713622 ps
CPU time 25.81 seconds
Started May 26 01:58:38 PM PDT 24
Finished May 26 01:59:05 PM PDT 24
Peak memory 212136 kb
Host smart-27cd849f-4ef9-4659-9770-3992c8e869ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466142034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3466142034
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.706449753
Short name T223
Test name
Test status
Simulation time 1619666195 ps
CPU time 120.7 seconds
Started May 26 01:58:37 PM PDT 24
Finished May 26 02:00:39 PM PDT 24
Peak memory 236604 kb
Host smart-b363fd5f-6cdf-41f8-9bd6-d295f2ad6eb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706449753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.706449753
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.505009791
Short name T108
Test name
Test status
Simulation time 5727564074 ps
CPU time 53.04 seconds
Started May 26 01:58:39 PM PDT 24
Finished May 26 01:59:33 PM PDT 24
Peak memory 215044 kb
Host smart-92acfe4a-0628-41ff-9b79-88dde5bfa671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505009791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.505009791
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2267718138
Short name T328
Test name
Test status
Simulation time 718310954 ps
CPU time 10.37 seconds
Started May 26 01:58:37 PM PDT 24
Finished May 26 01:58:48 PM PDT 24
Peak memory 211492 kb
Host smart-b9d7dae6-8eec-4671-ad51-47c3b921b088
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2267718138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2267718138
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3389525142
Short name T175
Test name
Test status
Simulation time 7620800021 ps
CPU time 65.96 seconds
Started May 26 01:58:40 PM PDT 24
Finished May 26 01:59:47 PM PDT 24
Peak memory 216880 kb
Host smart-298cfe4d-0d54-4817-97c5-70764d1b93b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389525142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3389525142
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2741869701
Short name T262
Test name
Test status
Simulation time 34836096625 ps
CPU time 76.77 seconds
Started May 26 01:58:40 PM PDT 24
Finished May 26 01:59:58 PM PDT 24
Peak memory 218184 kb
Host smart-be336324-070d-44e5-b08d-9250fca4a91b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741869701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2741869701
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.406291551
Short name T350
Test name
Test status
Simulation time 2633206949 ps
CPU time 24.88 seconds
Started May 26 01:58:48 PM PDT 24
Finished May 26 01:59:14 PM PDT 24
Peak memory 211852 kb
Host smart-65729d13-b505-4c1c-b27d-efd557ae364c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406291551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.406291551
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1185457749
Short name T28
Test name
Test status
Simulation time 218228138126 ps
CPU time 422.5 seconds
Started May 26 01:58:39 PM PDT 24
Finished May 26 02:05:42 PM PDT 24
Peak memory 235676 kb
Host smart-803b171d-cab1-4e53-bdd3-0091a69d7508
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185457749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1185457749
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.315245217
Short name T217
Test name
Test status
Simulation time 2494280198 ps
CPU time 27.67 seconds
Started May 26 01:58:38 PM PDT 24
Finished May 26 01:59:07 PM PDT 24
Peak memory 214620 kb
Host smart-9d376c8c-7c37-41bf-973a-642e90addd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315245217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.315245217
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.176317189
Short name T69
Test name
Test status
Simulation time 3931554467 ps
CPU time 33.07 seconds
Started May 26 01:58:40 PM PDT 24
Finished May 26 01:59:14 PM PDT 24
Peak memory 211236 kb
Host smart-b1663396-c9c0-4cd8-ace5-b84da0baa7ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=176317189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.176317189
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2584566027
Short name T137
Test name
Test status
Simulation time 7548274477 ps
CPU time 65.99 seconds
Started May 26 01:58:37 PM PDT 24
Finished May 26 01:59:43 PM PDT 24
Peak memory 214112 kb
Host smart-ad764ffe-1a1c-4043-9956-2764eb952fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584566027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2584566027
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1460032726
Short name T330
Test name
Test status
Simulation time 10021141574 ps
CPU time 48.89 seconds
Started May 26 01:58:38 PM PDT 24
Finished May 26 01:59:28 PM PDT 24
Peak memory 219680 kb
Host smart-3e466b43-149e-4d5f-8bfc-b65d929959f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460032726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1460032726
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1800777627
Short name T322
Test name
Test status
Simulation time 3291219980 ps
CPU time 14.25 seconds
Started May 26 01:58:46 PM PDT 24
Finished May 26 01:59:01 PM PDT 24
Peak memory 211312 kb
Host smart-b343156b-6097-40f2-8ada-6d9c1ccf8c93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800777627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1800777627
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1139284365
Short name T234
Test name
Test status
Simulation time 45434595961 ps
CPU time 584.45 seconds
Started May 26 01:58:44 PM PDT 24
Finished May 26 02:08:29 PM PDT 24
Peak memory 233644 kb
Host smart-9e9abba4-420d-4795-9359-f6ada34632d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139284365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1139284365
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2414118664
Short name T190
Test name
Test status
Simulation time 3866257301 ps
CPU time 40.54 seconds
Started May 26 01:58:45 PM PDT 24
Finished May 26 01:59:26 PM PDT 24
Peak memory 214504 kb
Host smart-0c7be96d-3011-4197-ad8c-b1decc64f656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414118664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2414118664
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2897821486
Short name T119
Test name
Test status
Simulation time 18775044212 ps
CPU time 30.43 seconds
Started May 26 01:58:46 PM PDT 24
Finished May 26 01:59:17 PM PDT 24
Peak memory 211664 kb
Host smart-42ac2fcb-59af-4926-b5bf-65bb03d80da7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2897821486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2897821486
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1827857455
Short name T158
Test name
Test status
Simulation time 6615205271 ps
CPU time 55.5 seconds
Started May 26 01:58:47 PM PDT 24
Finished May 26 01:59:43 PM PDT 24
Peak memory 217372 kb
Host smart-2c501795-0ec3-4385-b398-8d0d81e119f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827857455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1827857455
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1968019249
Short name T352
Test name
Test status
Simulation time 8574274901 ps
CPU time 50.44 seconds
Started May 26 01:58:45 PM PDT 24
Finished May 26 01:59:36 PM PDT 24
Peak memory 217152 kb
Host smart-260efa7b-3984-4ca4-bd0b-2aef6f08aaf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968019249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1968019249
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3744119148
Short name T336
Test name
Test status
Simulation time 775146760 ps
CPU time 14.06 seconds
Started May 26 01:58:45 PM PDT 24
Finished May 26 01:59:00 PM PDT 24
Peak memory 211232 kb
Host smart-1a2cfc68-91b2-4e46-8051-3daf160908a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744119148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3744119148
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.314348474
Short name T244
Test name
Test status
Simulation time 19902323311 ps
CPU time 272.93 seconds
Started May 26 01:58:48 PM PDT 24
Finished May 26 02:03:22 PM PDT 24
Peak memory 239896 kb
Host smart-4ceb8e54-0d58-4caa-9d81-382fa81c7609
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314348474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.314348474
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1080672149
Short name T323
Test name
Test status
Simulation time 3270761731 ps
CPU time 39.73 seconds
Started May 26 01:58:47 PM PDT 24
Finished May 26 01:59:28 PM PDT 24
Peak memory 214588 kb
Host smart-a2c96030-2e68-4c57-a0b9-8e2a6d90da36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080672149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1080672149
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1397008519
Short name T353
Test name
Test status
Simulation time 177355250 ps
CPU time 10.66 seconds
Started May 26 01:58:47 PM PDT 24
Finished May 26 01:58:59 PM PDT 24
Peak memory 212404 kb
Host smart-598107a8-a8cf-4437-8508-22c455b9f20b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1397008519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1397008519
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.559001534
Short name T154
Test name
Test status
Simulation time 17011385693 ps
CPU time 67.73 seconds
Started May 26 01:58:46 PM PDT 24
Finished May 26 01:59:55 PM PDT 24
Peak memory 216904 kb
Host smart-41790bca-cf10-41d5-bcc6-94048f0672e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559001534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.559001534
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3225264947
Short name T311
Test name
Test status
Simulation time 5311624849 ps
CPU time 118.75 seconds
Started May 26 01:58:48 PM PDT 24
Finished May 26 02:00:48 PM PDT 24
Peak memory 227444 kb
Host smart-83126017-1885-4602-8272-af02d49214a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225264947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3225264947
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.4191838367
Short name T339
Test name
Test status
Simulation time 4423462683 ps
CPU time 22.48 seconds
Started May 26 01:58:44 PM PDT 24
Finished May 26 01:59:07 PM PDT 24
Peak memory 211264 kb
Host smart-37fa7404-0f55-4481-801a-aa28013a130b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191838367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.4191838367
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2001909745
Short name T30
Test name
Test status
Simulation time 68449168826 ps
CPU time 757.36 seconds
Started May 26 01:58:46 PM PDT 24
Finished May 26 02:11:24 PM PDT 24
Peak memory 238324 kb
Host smart-85a24702-e252-4baf-8a23-7b556381c98a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001909745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2001909745
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1208588006
Short name T256
Test name
Test status
Simulation time 1978238037 ps
CPU time 26.24 seconds
Started May 26 01:58:47 PM PDT 24
Finished May 26 01:59:14 PM PDT 24
Peak memory 214576 kb
Host smart-6630648c-807a-489b-97e6-d0ba56ab5924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208588006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1208588006
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.893423522
Short name T85
Test name
Test status
Simulation time 12985447460 ps
CPU time 29.73 seconds
Started May 26 01:58:45 PM PDT 24
Finished May 26 01:59:16 PM PDT 24
Peak memory 211396 kb
Host smart-de2eb896-1f79-491e-8b41-71126ea28ff1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=893423522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.893423522
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2975406712
Short name T253
Test name
Test status
Simulation time 350492605 ps
CPU time 19.77 seconds
Started May 26 01:58:48 PM PDT 24
Finished May 26 01:59:09 PM PDT 24
Peak memory 215044 kb
Host smart-77f8e6b3-6b83-4b31-a1df-5a271255f279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975406712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2975406712
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.490401544
Short name T149
Test name
Test status
Simulation time 2729333873 ps
CPU time 32.47 seconds
Started May 26 01:58:44 PM PDT 24
Finished May 26 01:59:17 PM PDT 24
Peak memory 212652 kb
Host smart-258f0c95-e43f-463a-9f18-c3deb8356ef9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490401544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.490401544
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3913745143
Short name T343
Test name
Test status
Simulation time 169024132 ps
CPU time 8.39 seconds
Started May 26 01:58:47 PM PDT 24
Finished May 26 01:58:56 PM PDT 24
Peak memory 211272 kb
Host smart-7a2e161f-dc0f-4d46-9090-3587bacc405d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913745143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3913745143
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2508147182
Short name T255
Test name
Test status
Simulation time 410417039376 ps
CPU time 643.69 seconds
Started May 26 01:58:47 PM PDT 24
Finished May 26 02:09:32 PM PDT 24
Peak memory 239368 kb
Host smart-7368fb57-c89b-44e7-931a-5f9f5ed328bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508147182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2508147182
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3129092132
Short name T1
Test name
Test status
Simulation time 17065319657 ps
CPU time 50.13 seconds
Started May 26 01:58:48 PM PDT 24
Finished May 26 01:59:40 PM PDT 24
Peak memory 214792 kb
Host smart-f2e503de-adbe-4e0b-affe-b47e6e046381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129092132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3129092132
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1310267757
Short name T152
Test name
Test status
Simulation time 4695959041 ps
CPU time 17.41 seconds
Started May 26 01:58:48 PM PDT 24
Finished May 26 01:59:07 PM PDT 24
Peak memory 211644 kb
Host smart-4fa76f5c-afab-4284-88fb-4709198a3702
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1310267757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1310267757
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2515484946
Short name T6
Test name
Test status
Simulation time 1487529047 ps
CPU time 32.34 seconds
Started May 26 01:58:45 PM PDT 24
Finished May 26 01:59:18 PM PDT 24
Peak memory 214832 kb
Host smart-9a4169e5-cabf-4ffa-ba97-3d433ca12c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515484946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2515484946
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.531522535
Short name T226
Test name
Test status
Simulation time 5746598758 ps
CPU time 53.6 seconds
Started May 26 01:58:46 PM PDT 24
Finished May 26 01:59:41 PM PDT 24
Peak memory 219244 kb
Host smart-5e3f103d-2aff-4092-8caf-39927bc45371
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531522535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.531522535
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.974236101
Short name T81
Test name
Test status
Simulation time 10594922292 ps
CPU time 26.3 seconds
Started May 26 01:57:52 PM PDT 24
Finished May 26 01:58:19 PM PDT 24
Peak memory 212124 kb
Host smart-ea226e6a-a3cc-4013-99f7-673b35eb9279
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974236101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.974236101
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2148717313
Short name T49
Test name
Test status
Simulation time 6488272964 ps
CPU time 289.03 seconds
Started May 26 01:57:52 PM PDT 24
Finished May 26 02:02:42 PM PDT 24
Peak memory 240348 kb
Host smart-658708aa-4430-4ac0-b29e-6205ef8a5e8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148717313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2148717313
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1266277537
Short name T211
Test name
Test status
Simulation time 3149604924 ps
CPU time 40.87 seconds
Started May 26 01:57:52 PM PDT 24
Finished May 26 01:58:34 PM PDT 24
Peak memory 214516 kb
Host smart-48fc68f1-5f87-4b9e-8569-53d3f3c2ee7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266277537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1266277537
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1242407991
Short name T240
Test name
Test status
Simulation time 651885117 ps
CPU time 10.47 seconds
Started May 26 01:57:53 PM PDT 24
Finished May 26 01:58:04 PM PDT 24
Peak memory 211320 kb
Host smart-a10a9ce2-d0a6-4683-8beb-583100d37e8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1242407991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1242407991
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3187997162
Short name T32
Test name
Test status
Simulation time 33669001147 ps
CPU time 252.27 seconds
Started May 26 01:57:53 PM PDT 24
Finished May 26 02:02:06 PM PDT 24
Peak memory 238048 kb
Host smart-808f638f-a064-4cf1-9892-8cfb1af83c64
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187997162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3187997162
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.317329287
Short name T196
Test name
Test status
Simulation time 3396752274 ps
CPU time 24.01 seconds
Started May 26 01:57:52 PM PDT 24
Finished May 26 01:58:17 PM PDT 24
Peak memory 216696 kb
Host smart-549042e6-6fae-49a8-aad4-5671c80efab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317329287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.317329287
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2345881535
Short name T38
Test name
Test status
Simulation time 3127602422 ps
CPU time 38.21 seconds
Started May 26 01:57:55 PM PDT 24
Finished May 26 01:58:34 PM PDT 24
Peak memory 219224 kb
Host smart-b9dc3146-4bcd-423b-ba46-73501ff41006
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345881535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2345881535
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3261043960
Short name T204
Test name
Test status
Simulation time 1029433329 ps
CPU time 10 seconds
Started May 26 01:58:47 PM PDT 24
Finished May 26 01:58:59 PM PDT 24
Peak memory 211216 kb
Host smart-2945defb-8408-43ab-a8f2-dc8ddadcda9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261043960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3261043960
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2441727803
Short name T29
Test name
Test status
Simulation time 2469658164 ps
CPU time 161.46 seconds
Started May 26 01:58:44 PM PDT 24
Finished May 26 02:01:27 PM PDT 24
Peak memory 216604 kb
Host smart-e9c92790-30ea-47e2-afd8-4c159b4b408a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441727803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2441727803
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1067387896
Short name T315
Test name
Test status
Simulation time 12996025616 ps
CPU time 56.8 seconds
Started May 26 01:58:44 PM PDT 24
Finished May 26 01:59:42 PM PDT 24
Peak memory 214788 kb
Host smart-b3cb0f06-7935-42ff-a468-78d86cb664fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067387896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1067387896
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3480641908
Short name T331
Test name
Test status
Simulation time 4144608674 ps
CPU time 16.4 seconds
Started May 26 01:58:47 PM PDT 24
Finished May 26 01:59:04 PM PDT 24
Peak memory 211232 kb
Host smart-e8152770-2cf8-4b3f-8f64-9a76f1dadb93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3480641908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3480641908
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.4275733766
Short name T11
Test name
Test status
Simulation time 7751775760 ps
CPU time 63.02 seconds
Started May 26 01:58:46 PM PDT 24
Finished May 26 01:59:50 PM PDT 24
Peak memory 215080 kb
Host smart-a940bf16-d21a-4a54-b6f4-46a95a491101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275733766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.4275733766
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3818888803
Short name T224
Test name
Test status
Simulation time 725138116 ps
CPU time 21.24 seconds
Started May 26 01:58:46 PM PDT 24
Finished May 26 01:59:08 PM PDT 24
Peak memory 211652 kb
Host smart-c8eeba1b-02a1-4090-aa5b-aa44e2a32a5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818888803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3818888803
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.252693080
Short name T179
Test name
Test status
Simulation time 2222662709 ps
CPU time 22.33 seconds
Started May 26 01:58:55 PM PDT 24
Finished May 26 01:59:17 PM PDT 24
Peak memory 211280 kb
Host smart-aebbe4fd-6423-49d2-93f3-f65fda25afcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252693080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.252693080
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3466839291
Short name T291
Test name
Test status
Simulation time 155167420370 ps
CPU time 816 seconds
Started May 26 01:58:55 PM PDT 24
Finished May 26 02:12:31 PM PDT 24
Peak memory 236568 kb
Host smart-281cef49-ae68-4fb3-a044-0eec8579a582
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466839291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3466839291
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2612244031
Short name T25
Test name
Test status
Simulation time 7492868731 ps
CPU time 58.9 seconds
Started May 26 01:58:54 PM PDT 24
Finished May 26 01:59:54 PM PDT 24
Peak memory 214008 kb
Host smart-b69dc93a-26af-48f3-8bb2-463216618816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612244031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2612244031
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2312479543
Short name T143
Test name
Test status
Simulation time 5475294706 ps
CPU time 27.04 seconds
Started May 26 01:58:53 PM PDT 24
Finished May 26 01:59:20 PM PDT 24
Peak memory 211252 kb
Host smart-32b87d15-9b11-4cfd-ad87-30f51df7176d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2312479543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2312479543
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2979245688
Short name T252
Test name
Test status
Simulation time 25981425259 ps
CPU time 61.84 seconds
Started May 26 01:58:54 PM PDT 24
Finished May 26 01:59:56 PM PDT 24
Peak memory 216940 kb
Host smart-4b557515-299c-449f-92d2-34370a15dca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979245688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2979245688
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.770727953
Short name T264
Test name
Test status
Simulation time 376793162 ps
CPU time 24.66 seconds
Started May 26 01:58:52 PM PDT 24
Finished May 26 01:59:17 PM PDT 24
Peak memory 217916 kb
Host smart-6686d8e6-0271-4d40-9f3a-e1143937f7c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770727953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.770727953
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4270852089
Short name T181
Test name
Test status
Simulation time 677555148 ps
CPU time 12.85 seconds
Started May 26 01:58:52 PM PDT 24
Finished May 26 01:59:05 PM PDT 24
Peak memory 211224 kb
Host smart-afd40cc1-661a-4c04-8e0b-fb61ce9bcd60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270852089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4270852089
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.766653406
Short name T207
Test name
Test status
Simulation time 127169572218 ps
CPU time 408.93 seconds
Started May 26 01:58:52 PM PDT 24
Finished May 26 02:05:41 PM PDT 24
Peak memory 240244 kb
Host smart-d94fba09-769b-46c1-91e2-900fe005a8f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766653406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.766653406
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.95944512
Short name T355
Test name
Test status
Simulation time 6015534572 ps
CPU time 54.39 seconds
Started May 26 01:58:53 PM PDT 24
Finished May 26 01:59:48 PM PDT 24
Peak memory 214688 kb
Host smart-ba2abb62-a48d-479d-b6fd-66e250721df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95944512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.95944512
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3650045302
Short name T9
Test name
Test status
Simulation time 605040682 ps
CPU time 14.71 seconds
Started May 26 01:58:53 PM PDT 24
Finished May 26 01:59:08 PM PDT 24
Peak memory 212348 kb
Host smart-f4b2ae3c-8324-4acd-833a-1652e4f70d8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3650045302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3650045302
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3410664409
Short name T109
Test name
Test status
Simulation time 4001047887 ps
CPU time 28.48 seconds
Started May 26 01:58:51 PM PDT 24
Finished May 26 01:59:20 PM PDT 24
Peak memory 216420 kb
Host smart-91f8f906-950c-4f37-b99b-bfb05140be9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410664409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3410664409
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3846340585
Short name T257
Test name
Test status
Simulation time 6611664175 ps
CPU time 53.48 seconds
Started May 26 01:58:52 PM PDT 24
Finished May 26 01:59:46 PM PDT 24
Peak memory 219236 kb
Host smart-27dc7026-187c-4943-8ecc-c781e777e46a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846340585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3846340585
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1047205391
Short name T182
Test name
Test status
Simulation time 2421921508 ps
CPU time 23.43 seconds
Started May 26 01:58:51 PM PDT 24
Finished May 26 01:59:15 PM PDT 24
Peak memory 211288 kb
Host smart-4029035c-c880-4726-a5e1-0d48fcbe1589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047205391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1047205391
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1204388554
Short name T266
Test name
Test status
Simulation time 48353207941 ps
CPU time 423.94 seconds
Started May 26 01:58:53 PM PDT 24
Finished May 26 02:05:58 PM PDT 24
Peak memory 240064 kb
Host smart-84ec7e05-32c8-4d9f-b36c-662458393eb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204388554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1204388554
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2096207351
Short name T268
Test name
Test status
Simulation time 6154898332 ps
CPU time 38.99 seconds
Started May 26 01:58:51 PM PDT 24
Finished May 26 01:59:31 PM PDT 24
Peak memory 215160 kb
Host smart-2c79e087-4f1a-4d01-aa0a-566eefa0e927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096207351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2096207351
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2478612597
Short name T294
Test name
Test status
Simulation time 4117391726 ps
CPU time 24.91 seconds
Started May 26 01:58:52 PM PDT 24
Finished May 26 01:59:17 PM PDT 24
Peak memory 211432 kb
Host smart-4515cafb-9191-4f8f-aa44-a7ee30a1085c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2478612597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2478612597
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3309985551
Short name T146
Test name
Test status
Simulation time 21931607073 ps
CPU time 52.88 seconds
Started May 26 01:58:53 PM PDT 24
Finished May 26 01:59:46 PM PDT 24
Peak memory 217040 kb
Host smart-265d324f-9787-4baa-9ebb-0974f0f3b161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309985551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3309985551
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1969629901
Short name T138
Test name
Test status
Simulation time 4297214860 ps
CPU time 23.82 seconds
Started May 26 01:58:53 PM PDT 24
Finished May 26 01:59:17 PM PDT 24
Peak memory 213640 kb
Host smart-203cf1ec-9745-4d7e-9ae7-91ce5c9795e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969629901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1969629901
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1875939610
Short name T35
Test name
Test status
Simulation time 360950008 ps
CPU time 8.41 seconds
Started May 26 01:59:02 PM PDT 24
Finished May 26 01:59:11 PM PDT 24
Peak memory 211224 kb
Host smart-a9ed9ace-8606-4960-a1a2-ce6994f699bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875939610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1875939610
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2233489591
Short name T284
Test name
Test status
Simulation time 54865500582 ps
CPU time 340.65 seconds
Started May 26 01:58:59 PM PDT 24
Finished May 26 02:04:41 PM PDT 24
Peak memory 240576 kb
Host smart-f17cbb6c-300a-4e7c-a838-161b308f1bb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233489591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2233489591
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3323341302
Short name T205
Test name
Test status
Simulation time 2655064445 ps
CPU time 32.31 seconds
Started May 26 01:59:01 PM PDT 24
Finished May 26 01:59:35 PM PDT 24
Peak memory 214688 kb
Host smart-0d90d45e-cbd0-42b1-a9a9-c6c4f92fe6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323341302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3323341302
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2812976744
Short name T278
Test name
Test status
Simulation time 3089786512 ps
CPU time 20.09 seconds
Started May 26 01:59:01 PM PDT 24
Finished May 26 01:59:22 PM PDT 24
Peak memory 212528 kb
Host smart-f38adcfd-6466-46e1-972f-6a04dea5b1d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2812976744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2812976744
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1895314484
Short name T203
Test name
Test status
Simulation time 705748905 ps
CPU time 21.2 seconds
Started May 26 01:58:52 PM PDT 24
Finished May 26 01:59:13 PM PDT 24
Peak memory 216376 kb
Host smart-217cdfd4-7373-46e1-8891-4665ed1b42da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895314484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1895314484
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4074027748
Short name T187
Test name
Test status
Simulation time 4072957813 ps
CPU time 59.62 seconds
Started May 26 01:58:53 PM PDT 24
Finished May 26 01:59:53 PM PDT 24
Peak memory 215876 kb
Host smart-cd4eddb2-f8b8-468c-94a8-6864a52b68d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074027748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4074027748
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2476336217
Short name T274
Test name
Test status
Simulation time 345506133 ps
CPU time 8.24 seconds
Started May 26 01:59:01 PM PDT 24
Finished May 26 01:59:10 PM PDT 24
Peak memory 211192 kb
Host smart-84c0c770-4473-42e0-8f54-7c676bb00fde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476336217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2476336217
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3412139225
Short name T229
Test name
Test status
Simulation time 137616308847 ps
CPU time 254.41 seconds
Started May 26 01:59:00 PM PDT 24
Finished May 26 02:03:15 PM PDT 24
Peak memory 228972 kb
Host smart-d53a4c92-61dc-4832-a684-783f2a4d8fc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412139225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3412139225
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1141026875
Short name T314
Test name
Test status
Simulation time 16769973834 ps
CPU time 68.5 seconds
Started May 26 01:59:00 PM PDT 24
Finished May 26 02:00:09 PM PDT 24
Peak memory 214744 kb
Host smart-2c883518-3ab5-4aab-ac41-71a491b41003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141026875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1141026875
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1677121431
Short name T148
Test name
Test status
Simulation time 3771472607 ps
CPU time 22.47 seconds
Started May 26 01:58:59 PM PDT 24
Finished May 26 01:59:22 PM PDT 24
Peak memory 211464 kb
Host smart-dc25b893-9c1f-495d-8d23-b7b27adfa2cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1677121431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1677121431
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.732554556
Short name T345
Test name
Test status
Simulation time 8355280874 ps
CPU time 68.4 seconds
Started May 26 01:59:01 PM PDT 24
Finished May 26 02:00:11 PM PDT 24
Peak memory 218048 kb
Host smart-db61e2da-8c52-4935-b2cf-4dfc9e0369a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732554556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.732554556
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2327320120
Short name T170
Test name
Test status
Simulation time 1133585644 ps
CPU time 11.45 seconds
Started May 26 01:58:59 PM PDT 24
Finished May 26 01:59:12 PM PDT 24
Peak memory 213044 kb
Host smart-f1437e8b-16ea-4d82-b1af-5b972879465e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327320120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2327320120
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2504555238
Short name T241
Test name
Test status
Simulation time 1992258794 ps
CPU time 21.5 seconds
Started May 26 01:59:01 PM PDT 24
Finished May 26 01:59:23 PM PDT 24
Peak memory 211636 kb
Host smart-8b95deca-cfc9-4ecd-b441-84a9364b31a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504555238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2504555238
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2882838028
Short name T282
Test name
Test status
Simulation time 32045999372 ps
CPU time 547.75 seconds
Started May 26 01:59:01 PM PDT 24
Finished May 26 02:08:10 PM PDT 24
Peak memory 237608 kb
Host smart-1353b2a0-22de-4bb4-945b-10c4a7088526
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882838028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2882838028
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2407265959
Short name T45
Test name
Test status
Simulation time 7655716277 ps
CPU time 66 seconds
Started May 26 01:59:01 PM PDT 24
Finished May 26 02:00:08 PM PDT 24
Peak memory 212792 kb
Host smart-0184644d-a4ef-41b1-a066-96643764b06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407265959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2407265959
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2417955399
Short name T178
Test name
Test status
Simulation time 5865317009 ps
CPU time 19.64 seconds
Started May 26 01:58:59 PM PDT 24
Finished May 26 01:59:20 PM PDT 24
Peak memory 212756 kb
Host smart-f3a2e9c3-4179-4f5f-9608-44778335d69b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2417955399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2417955399
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.174342487
Short name T303
Test name
Test status
Simulation time 6295180327 ps
CPU time 49.78 seconds
Started May 26 01:59:00 PM PDT 24
Finished May 26 01:59:51 PM PDT 24
Peak memory 217704 kb
Host smart-24824ff5-9a1e-48d4-99c6-187b43116b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174342487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.174342487
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2076311342
Short name T142
Test name
Test status
Simulation time 17663208548 ps
CPU time 92.06 seconds
Started May 26 01:59:00 PM PDT 24
Finished May 26 02:00:33 PM PDT 24
Peak memory 219264 kb
Host smart-ed21c29c-19a9-45e9-8bd0-92debcbe9339
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076311342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2076311342
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.800267656
Short name T288
Test name
Test status
Simulation time 13319627344 ps
CPU time 31.41 seconds
Started May 26 01:59:08 PM PDT 24
Finished May 26 01:59:41 PM PDT 24
Peak memory 211968 kb
Host smart-d3f269b9-e835-493a-be52-69c7f5b787fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800267656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.800267656
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.996793813
Short name T313
Test name
Test status
Simulation time 374289117490 ps
CPU time 756.15 seconds
Started May 26 01:59:08 PM PDT 24
Finished May 26 02:11:45 PM PDT 24
Peak memory 217120 kb
Host smart-6aa3ca67-21ed-4f4b-82e2-352f7c403778
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996793813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.996793813
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2785375424
Short name T270
Test name
Test status
Simulation time 3252718394 ps
CPU time 29.06 seconds
Started May 26 01:59:08 PM PDT 24
Finished May 26 01:59:39 PM PDT 24
Peak memory 211196 kb
Host smart-fd6a6ed8-ab0c-408d-9bb7-00f3bd4075f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2785375424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2785375424
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.4277714341
Short name T281
Test name
Test status
Simulation time 4074560734 ps
CPU time 48.37 seconds
Started May 26 01:59:01 PM PDT 24
Finished May 26 01:59:51 PM PDT 24
Peak memory 215748 kb
Host smart-9603646c-5696-49ed-911d-be84475f4aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277714341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.4277714341
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2548014409
Short name T296
Test name
Test status
Simulation time 28576935309 ps
CPU time 85.83 seconds
Started May 26 01:59:07 PM PDT 24
Finished May 26 02:00:33 PM PDT 24
Peak memory 218104 kb
Host smart-cb479d95-13ab-49a4-b781-256e92db6ad1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548014409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2548014409
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.303691395
Short name T238
Test name
Test status
Simulation time 11264097546 ps
CPU time 25.03 seconds
Started May 26 01:59:08 PM PDT 24
Finished May 26 01:59:35 PM PDT 24
Peak memory 211284 kb
Host smart-70d938a0-e9ed-4781-b71f-ad977535281b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303691395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.303691395
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1727356243
Short name T275
Test name
Test status
Simulation time 9551414694 ps
CPU time 150.18 seconds
Started May 26 01:59:10 PM PDT 24
Finished May 26 02:01:40 PM PDT 24
Peak memory 237672 kb
Host smart-5e0f239b-12ff-43cd-99da-49a74a6ab8e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727356243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1727356243
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2636171974
Short name T246
Test name
Test status
Simulation time 3760542184 ps
CPU time 43.37 seconds
Started May 26 01:59:08 PM PDT 24
Finished May 26 01:59:53 PM PDT 24
Peak memory 214608 kb
Host smart-0b18f3b4-a270-4a34-a8e3-bc857f02dcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636171974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2636171974
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.520531313
Short name T340
Test name
Test status
Simulation time 28470189644 ps
CPU time 32.36 seconds
Started May 26 01:59:08 PM PDT 24
Finished May 26 01:59:42 PM PDT 24
Peak memory 211608 kb
Host smart-2a1d8b33-97ca-4f40-8f91-da3d054356fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=520531313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.520531313
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2627294357
Short name T236
Test name
Test status
Simulation time 5915720096 ps
CPU time 29.66 seconds
Started May 26 01:59:09 PM PDT 24
Finished May 26 01:59:40 PM PDT 24
Peak memory 217440 kb
Host smart-bfe30ca6-5300-411f-94d0-a07bbeac841e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627294357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2627294357
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3607079951
Short name T188
Test name
Test status
Simulation time 9679651229 ps
CPU time 35.2 seconds
Started May 26 01:59:07 PM PDT 24
Finished May 26 01:59:43 PM PDT 24
Peak memory 218900 kb
Host smart-c59debb8-a0b2-4742-a002-e235c4c1a95e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607079951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3607079951
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2516702012
Short name T349
Test name
Test status
Simulation time 4186002627 ps
CPU time 33.74 seconds
Started May 26 01:59:15 PM PDT 24
Finished May 26 01:59:49 PM PDT 24
Peak memory 211804 kb
Host smart-075c16dd-c253-43f1-9e5d-a5ffafcaae48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516702012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2516702012
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1807398861
Short name T53
Test name
Test status
Simulation time 107704921366 ps
CPU time 319.57 seconds
Started May 26 01:59:11 PM PDT 24
Finished May 26 02:04:32 PM PDT 24
Peak memory 218892 kb
Host smart-6a730cd6-b4be-41bc-bd24-6b6d6ac39ad0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807398861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1807398861
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2420254122
Short name T144
Test name
Test status
Simulation time 55556475694 ps
CPU time 64.67 seconds
Started May 26 01:59:07 PM PDT 24
Finished May 26 02:00:13 PM PDT 24
Peak memory 214852 kb
Host smart-4efc8972-808d-46d6-b8c5-041da2b49041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420254122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2420254122
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2035936693
Short name T213
Test name
Test status
Simulation time 179858455 ps
CPU time 10.62 seconds
Started May 26 01:59:07 PM PDT 24
Finished May 26 01:59:18 PM PDT 24
Peak memory 212148 kb
Host smart-16a03522-de53-4f0e-9eec-76ddbccb5851
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2035936693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2035936693
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2198281428
Short name T269
Test name
Test status
Simulation time 5602217232 ps
CPU time 53.07 seconds
Started May 26 01:59:08 PM PDT 24
Finished May 26 02:00:02 PM PDT 24
Peak memory 217432 kb
Host smart-7c49e46d-4e14-4492-b6b8-8ccd2315c606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198281428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2198281428
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2927074728
Short name T44
Test name
Test status
Simulation time 9124118155 ps
CPU time 92.79 seconds
Started May 26 01:59:11 PM PDT 24
Finished May 26 02:00:45 PM PDT 24
Peak memory 214732 kb
Host smart-d0cc7a6e-206e-4b2d-a69b-c197b90d0fc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927074728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2927074728
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.792835472
Short name T245
Test name
Test status
Simulation time 6607100228 ps
CPU time 17.79 seconds
Started May 26 01:58:02 PM PDT 24
Finished May 26 01:58:22 PM PDT 24
Peak memory 212196 kb
Host smart-bf4fd7f1-dbb1-47a7-b97d-91f20d0d0dc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792835472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.792835472
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.550403178
Short name T292
Test name
Test status
Simulation time 127241936708 ps
CPU time 647.6 seconds
Started May 26 01:58:00 PM PDT 24
Finished May 26 02:08:49 PM PDT 24
Peak memory 234720 kb
Host smart-638bffe9-d34b-4e96-91ef-523e720830c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550403178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.550403178
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.171405313
Short name T150
Test name
Test status
Simulation time 38657923922 ps
CPU time 52.71 seconds
Started May 26 01:58:03 PM PDT 24
Finished May 26 01:58:58 PM PDT 24
Peak memory 214976 kb
Host smart-e630a917-57f6-4182-921b-312f25d351a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171405313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.171405313
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1246500301
Short name T68
Test name
Test status
Simulation time 851220433 ps
CPU time 16.25 seconds
Started May 26 01:57:52 PM PDT 24
Finished May 26 01:58:09 PM PDT 24
Peak memory 212144 kb
Host smart-0166a74a-d744-4d14-9aea-398cd3f31fad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1246500301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1246500301
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2599881853
Short name T347
Test name
Test status
Simulation time 3074161517 ps
CPU time 42.23 seconds
Started May 26 01:57:54 PM PDT 24
Finished May 26 01:58:36 PM PDT 24
Peak memory 215688 kb
Host smart-0155b559-3aa9-41aa-bff8-05a27ae92210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599881853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2599881853
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2525877812
Short name T73
Test name
Test status
Simulation time 14686513806 ps
CPU time 33.32 seconds
Started May 26 01:58:01 PM PDT 24
Finished May 26 01:58:36 PM PDT 24
Peak memory 212016 kb
Host smart-6799935f-d09a-4275-abc4-24af8c668abb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525877812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2525877812
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3980106976
Short name T222
Test name
Test status
Simulation time 75132539647 ps
CPU time 745.67 seconds
Started May 26 01:58:04 PM PDT 24
Finished May 26 02:10:31 PM PDT 24
Peak memory 236600 kb
Host smart-99b7efa3-f07c-45d9-b715-9dcefb16f791
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980106976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3980106976
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1483009751
Short name T300
Test name
Test status
Simulation time 6624462272 ps
CPU time 57.16 seconds
Started May 26 01:58:01 PM PDT 24
Finished May 26 01:58:59 PM PDT 24
Peak memory 214096 kb
Host smart-ed35b98e-2a81-4280-9456-a9abf0ec3829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483009751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1483009751
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1381727360
Short name T171
Test name
Test status
Simulation time 189452708 ps
CPU time 10.91 seconds
Started May 26 01:58:03 PM PDT 24
Finished May 26 01:58:16 PM PDT 24
Peak memory 212192 kb
Host smart-ec2365eb-f102-4c63-90e8-afb67079a907
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1381727360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1381727360
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3152745372
Short name T287
Test name
Test status
Simulation time 3110428106 ps
CPU time 30.61 seconds
Started May 26 01:58:02 PM PDT 24
Finished May 26 01:58:35 PM PDT 24
Peak memory 216632 kb
Host smart-39e9b106-ffd4-4f0c-874a-444b016ef82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152745372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3152745372
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1340257119
Short name T55
Test name
Test status
Simulation time 2555713708 ps
CPU time 28.42 seconds
Started May 26 01:58:00 PM PDT 24
Finished May 26 01:58:30 PM PDT 24
Peak memory 213508 kb
Host smart-4f71734d-54c5-44f3-9845-ef4810ed1df1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340257119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1340257119
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.161798008
Short name T62
Test name
Test status
Simulation time 43665570488 ps
CPU time 1704.76 seconds
Started May 26 01:58:06 PM PDT 24
Finished May 26 02:26:31 PM PDT 24
Peak memory 235668 kb
Host smart-2767ea3e-cc2a-4a9d-b0cb-d3000ab4a41b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161798008 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.161798008
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1150021059
Short name T344
Test name
Test status
Simulation time 17880184460 ps
CPU time 34.22 seconds
Started May 26 01:58:02 PM PDT 24
Finished May 26 01:58:38 PM PDT 24
Peak memory 212004 kb
Host smart-64a90860-f5a6-4659-8bd0-57a37029148e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150021059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1150021059
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2562678064
Short name T24
Test name
Test status
Simulation time 21272398967 ps
CPU time 65.12 seconds
Started May 26 01:58:02 PM PDT 24
Finished May 26 01:59:10 PM PDT 24
Peak memory 215016 kb
Host smart-c390f8cb-65c7-4344-b48b-3616740549ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562678064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2562678064
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.4239923572
Short name T326
Test name
Test status
Simulation time 18520547245 ps
CPU time 20.32 seconds
Started May 26 01:58:01 PM PDT 24
Finished May 26 01:58:22 PM PDT 24
Peak memory 212672 kb
Host smart-5cb85d00-3093-4560-aa33-c197394e0f93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4239923572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.4239923572
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1873375584
Short name T173
Test name
Test status
Simulation time 15011589721 ps
CPU time 72.76 seconds
Started May 26 01:58:03 PM PDT 24
Finished May 26 01:59:18 PM PDT 24
Peak memory 216996 kb
Host smart-903778bd-adc4-40ea-bc33-b258b52fc2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873375584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1873375584
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.4253598052
Short name T263
Test name
Test status
Simulation time 2713579871 ps
CPU time 30.58 seconds
Started May 26 01:58:02 PM PDT 24
Finished May 26 01:58:35 PM PDT 24
Peak memory 212100 kb
Host smart-0c17a893-6904-4f29-9e2e-04c9dfe8f3ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253598052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.4253598052
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4207428004
Short name T191
Test name
Test status
Simulation time 4108663276 ps
CPU time 22.16 seconds
Started May 26 01:58:02 PM PDT 24
Finished May 26 01:58:27 PM PDT 24
Peak memory 211732 kb
Host smart-2e23ed11-85fe-4bc2-9cd5-5db26717734f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207428004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4207428004
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.729914834
Short name T333
Test name
Test status
Simulation time 157747845475 ps
CPU time 240.29 seconds
Started May 26 01:58:01 PM PDT 24
Finished May 26 02:02:03 PM PDT 24
Peak memory 239816 kb
Host smart-446b2517-3473-4d0b-a0ed-db0bc7476cbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729914834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.729914834
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2912909362
Short name T320
Test name
Test status
Simulation time 2357146567 ps
CPU time 19.54 seconds
Started May 26 01:58:03 PM PDT 24
Finished May 26 01:58:25 PM PDT 24
Peak memory 214608 kb
Host smart-590e603a-0cb9-42f1-b07e-5b878f1917f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912909362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2912909362
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2332591094
Short name T147
Test name
Test status
Simulation time 368074557 ps
CPU time 10.44 seconds
Started May 26 01:58:00 PM PDT 24
Finished May 26 01:58:12 PM PDT 24
Peak memory 212400 kb
Host smart-70c18fb2-55c0-4b06-b455-c169920b8701
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2332591094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2332591094
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3634419802
Short name T57
Test name
Test status
Simulation time 13903500752 ps
CPU time 41.24 seconds
Started May 26 01:58:02 PM PDT 24
Finished May 26 01:58:46 PM PDT 24
Peak memory 217504 kb
Host smart-c6610fa9-a526-44ca-ba65-f136915cb285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634419802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3634419802
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2803768538
Short name T176
Test name
Test status
Simulation time 10359023052 ps
CPU time 93.02 seconds
Started May 26 01:58:01 PM PDT 24
Finished May 26 01:59:35 PM PDT 24
Peak memory 219116 kb
Host smart-b9db5bea-92c0-4d6f-8cfe-24bdcb58dd05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803768538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2803768538
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1653532756
Short name T348
Test name
Test status
Simulation time 9548276302 ps
CPU time 23.29 seconds
Started May 26 01:58:06 PM PDT 24
Finished May 26 01:58:30 PM PDT 24
Peak memory 212156 kb
Host smart-20b6f0d7-d0da-45c6-8a0a-1648382d3316
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653532756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1653532756
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1667473682
Short name T251
Test name
Test status
Simulation time 48976365887 ps
CPU time 602.73 seconds
Started May 26 01:58:02 PM PDT 24
Finished May 26 02:08:07 PM PDT 24
Peak memory 239824 kb
Host smart-2d2603de-eb45-4337-bef1-e5fe57f8a76f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667473682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1667473682
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4218822832
Short name T7
Test name
Test status
Simulation time 719525730 ps
CPU time 19.3 seconds
Started May 26 01:58:03 PM PDT 24
Finished May 26 01:58:24 PM PDT 24
Peak memory 214452 kb
Host smart-72a94d38-ed2c-4e67-baa2-81a817dde257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218822832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.4218822832
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1150311212
Short name T233
Test name
Test status
Simulation time 2895782735 ps
CPU time 26.69 seconds
Started May 26 01:58:05 PM PDT 24
Finished May 26 01:58:33 PM PDT 24
Peak memory 211180 kb
Host smart-e640e1bf-b8f6-4c88-a375-9650185388da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1150311212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1150311212
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2873575422
Short name T174
Test name
Test status
Simulation time 29166619709 ps
CPU time 47.02 seconds
Started May 26 01:58:02 PM PDT 24
Finished May 26 01:58:51 PM PDT 24
Peak memory 215604 kb
Host smart-01f5e91e-df46-4663-8118-2b29d7eea176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873575422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2873575422
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2612678520
Short name T258
Test name
Test status
Simulation time 15803012810 ps
CPU time 71 seconds
Started May 26 01:58:00 PM PDT 24
Finished May 26 01:59:12 PM PDT 24
Peak memory 217676 kb
Host smart-fc65a540-8a45-4196-9ea9-af5ec977290d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612678520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2612678520
Directory /workspace/9.rom_ctrl_stress_all/latest
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