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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.59 96.97 93.30 97.88 100.00 98.69 97.89 98.37


Total test records in report: 448
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T304 /workspace/coverage/default/37.rom_ctrl_alert_test.1741085488 May 28 01:45:58 PM PDT 24 May 28 01:46:25 PM PDT 24 10851296330 ps
T305 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.66925924 May 28 01:46:09 PM PDT 24 May 28 01:47:19 PM PDT 24 5699012676 ps
T306 /workspace/coverage/default/45.rom_ctrl_alert_test.278321214 May 28 01:46:18 PM PDT 24 May 28 01:46:47 PM PDT 24 688576642 ps
T307 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.494361649 May 28 01:46:20 PM PDT 24 May 28 01:46:58 PM PDT 24 674537741 ps
T308 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.981383917 May 28 01:45:17 PM PDT 24 May 28 01:45:43 PM PDT 24 8234926674 ps
T309 /workspace/coverage/default/22.rom_ctrl_smoke.250405958 May 28 01:45:17 PM PDT 24 May 28 01:45:39 PM PDT 24 531952295 ps
T310 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.658845730 May 28 01:45:18 PM PDT 24 May 28 01:45:47 PM PDT 24 22460987450 ps
T311 /workspace/coverage/default/10.rom_ctrl_smoke.1298689347 May 28 01:44:48 PM PDT 24 May 28 01:45:14 PM PDT 24 677282201 ps
T312 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3063198299 May 28 01:46:18 PM PDT 24 May 28 01:53:06 PM PDT 24 86637406377 ps
T313 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3320535996 May 28 01:45:33 PM PDT 24 May 28 01:49:11 PM PDT 24 4941034652 ps
T314 /workspace/coverage/default/8.rom_ctrl_alert_test.1119429799 May 28 01:44:47 PM PDT 24 May 28 01:45:03 PM PDT 24 1543618135 ps
T315 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.182623338 May 28 01:45:27 PM PDT 24 May 28 01:45:39 PM PDT 24 184289253 ps
T316 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3241407949 May 28 01:45:19 PM PDT 24 May 28 01:52:35 PM PDT 24 41884734889 ps
T317 /workspace/coverage/default/39.rom_ctrl_smoke.964787244 May 28 01:45:57 PM PDT 24 May 28 01:46:23 PM PDT 24 673345158 ps
T318 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2558987990 May 28 01:44:45 PM PDT 24 May 28 01:45:48 PM PDT 24 13480496321 ps
T319 /workspace/coverage/default/19.rom_ctrl_stress_all.3960747645 May 28 01:45:21 PM PDT 24 May 28 01:46:10 PM PDT 24 755978966 ps
T320 /workspace/coverage/default/44.rom_ctrl_alert_test.1398883051 May 28 01:46:18 PM PDT 24 May 28 01:47:00 PM PDT 24 8541454663 ps
T321 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.756420669 May 28 01:46:09 PM PDT 24 May 28 01:47:30 PM PDT 24 110948732928 ps
T322 /workspace/coverage/default/2.rom_ctrl_alert_test.1675286582 May 28 01:44:36 PM PDT 24 May 28 01:44:53 PM PDT 24 7475567286 ps
T323 /workspace/coverage/default/22.rom_ctrl_alert_test.1232954365 May 28 01:45:19 PM PDT 24 May 28 01:45:29 PM PDT 24 360188248 ps
T324 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3663882123 May 28 01:45:18 PM PDT 24 May 28 01:45:39 PM PDT 24 5999274079 ps
T325 /workspace/coverage/default/28.rom_ctrl_stress_all.963266722 May 28 01:45:27 PM PDT 24 May 28 01:46:16 PM PDT 24 2364430971 ps
T326 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.250876693 May 28 01:44:38 PM PDT 24 May 28 01:45:11 PM PDT 24 3593337508 ps
T327 /workspace/coverage/default/14.rom_ctrl_stress_all.51726061 May 28 01:46:11 PM PDT 24 May 28 01:49:39 PM PDT 24 20562486724 ps
T328 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2757392131 May 28 01:46:20 PM PDT 24 May 28 01:49:04 PM PDT 24 12822924071 ps
T329 /workspace/coverage/default/24.rom_ctrl_alert_test.398490956 May 28 01:45:22 PM PDT 24 May 28 01:45:42 PM PDT 24 1452165652 ps
T330 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1661882605 May 28 01:44:39 PM PDT 24 May 28 01:45:09 PM PDT 24 5574223715 ps
T331 /workspace/coverage/default/40.rom_ctrl_stress_all.2278435154 May 28 01:46:06 PM PDT 24 May 28 01:47:27 PM PDT 24 2014019167 ps
T332 /workspace/coverage/default/31.rom_ctrl_smoke.1848101161 May 28 01:45:36 PM PDT 24 May 28 01:46:26 PM PDT 24 20775029682 ps
T333 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3705522027 May 28 01:45:34 PM PDT 24 May 28 01:45:45 PM PDT 24 263104612 ps
T334 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.371264190 May 28 01:46:06 PM PDT 24 May 28 01:54:08 PM PDT 24 121593907482 ps
T335 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1690602453 May 28 01:46:29 PM PDT 24 May 28 01:50:24 PM PDT 24 34918314952 ps
T336 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1230371820 May 28 01:44:37 PM PDT 24 May 28 01:45:12 PM PDT 24 14859931756 ps
T337 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2681363218 May 28 01:44:47 PM PDT 24 May 28 01:45:07 PM PDT 24 1374557727 ps
T338 /workspace/coverage/default/15.rom_ctrl_smoke.1609647003 May 28 01:45:16 PM PDT 24 May 28 01:46:24 PM PDT 24 6484750454 ps
T339 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.4047432000 May 28 01:45:55 PM PDT 24 May 28 01:53:01 PM PDT 24 38282258793 ps
T340 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1267424678 May 28 01:45:18 PM PDT 24 May 28 01:45:30 PM PDT 24 692563749 ps
T341 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.730702416 May 28 01:46:31 PM PDT 24 May 28 01:47:28 PM PDT 24 7577706165 ps
T342 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1619703921 May 28 01:44:38 PM PDT 24 May 28 01:45:44 PM PDT 24 6870489490 ps
T343 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.816380751 May 28 01:45:21 PM PDT 24 May 28 01:45:58 PM PDT 24 4127637398 ps
T344 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2699178995 May 28 01:46:18 PM PDT 24 May 28 01:59:26 PM PDT 24 61978913283 ps
T345 /workspace/coverage/default/32.rom_ctrl_smoke.696105118 May 28 01:45:43 PM PDT 24 May 28 01:46:05 PM PDT 24 1432290197 ps
T346 /workspace/coverage/default/7.rom_ctrl_stress_all.1395882868 May 28 01:44:46 PM PDT 24 May 28 01:45:44 PM PDT 24 2358678164 ps
T347 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.4150861448 May 28 01:45:42 PM PDT 24 May 28 01:46:37 PM PDT 24 6189644199 ps
T348 /workspace/coverage/default/31.rom_ctrl_stress_all.1103990487 May 28 01:45:36 PM PDT 24 May 28 01:46:29 PM PDT 24 4246104500 ps
T349 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3094811774 May 28 01:45:15 PM PDT 24 May 28 01:48:52 PM PDT 24 98027159939 ps
T350 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2815128698 May 28 01:45:58 PM PDT 24 May 28 01:53:31 PM PDT 24 163863568908 ps
T44 /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.4018964402 May 28 01:46:18 PM PDT 24 May 28 02:37:03 PM PDT 24 188143632160 ps
T351 /workspace/coverage/default/37.rom_ctrl_stress_all.2321718211 May 28 01:45:57 PM PDT 24 May 28 01:47:08 PM PDT 24 1090438531 ps
T352 /workspace/coverage/default/44.rom_ctrl_stress_all.3195981445 May 28 01:46:17 PM PDT 24 May 28 01:47:41 PM PDT 24 4657634244 ps
T353 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.116068730 May 28 01:45:33 PM PDT 24 May 28 01:46:28 PM PDT 24 22362976891 ps
T354 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2988221552 May 28 01:44:41 PM PDT 24 May 28 01:44:52 PM PDT 24 179847671 ps
T355 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.870119228 May 28 01:45:18 PM PDT 24 May 28 01:48:31 PM PDT 24 20606495315 ps
T356 /workspace/coverage/default/17.rom_ctrl_smoke.474229898 May 28 01:45:21 PM PDT 24 May 28 01:45:57 PM PDT 24 3353710154 ps
T357 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.22573944 May 28 01:34:04 PM PDT 24 May 28 01:34:30 PM PDT 24 9455719610 ps
T45 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3419599913 May 28 01:35:00 PM PDT 24 May 28 01:36:47 PM PDT 24 4348357276 ps
T46 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2153180013 May 28 01:34:16 PM PDT 24 May 28 01:34:52 PM PDT 24 7517000504 ps
T59 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.216495576 May 28 01:34:59 PM PDT 24 May 28 01:36:39 PM PDT 24 21190997361 ps
T60 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2953825660 May 28 01:34:58 PM PDT 24 May 28 01:35:32 PM PDT 24 29157039921 ps
T95 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4256896796 May 28 01:35:19 PM PDT 24 May 28 01:35:34 PM PDT 24 2737643905 ps
T70 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1483646402 May 28 01:34:32 PM PDT 24 May 28 01:36:07 PM PDT 24 21850966212 ps
T96 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2579453578 May 28 01:34:05 PM PDT 24 May 28 01:34:38 PM PDT 24 4263986638 ps
T47 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2695087072 May 28 01:34:05 PM PDT 24 May 28 01:34:20 PM PDT 24 670871832 ps
T48 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.942574168 May 28 01:35:00 PM PDT 24 May 28 01:35:39 PM PDT 24 3995797678 ps
T49 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.513800235 May 28 01:35:02 PM PDT 24 May 28 01:37:40 PM PDT 24 834764635 ps
T58 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3718007125 May 28 01:35:15 PM PDT 24 May 28 01:36:57 PM PDT 24 15113511559 ps
T100 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3824645708 May 28 01:35:01 PM PDT 24 May 28 01:36:28 PM PDT 24 125690172017 ps
T71 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.652756187 May 28 01:34:43 PM PDT 24 May 28 01:34:52 PM PDT 24 171113448 ps
T358 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1528886208 May 28 01:34:16 PM PDT 24 May 28 01:34:29 PM PDT 24 258421082 ps
T101 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1868454823 May 28 01:34:09 PM PDT 24 May 28 01:34:23 PM PDT 24 1135074238 ps
T67 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3787276084 May 28 01:34:58 PM PDT 24 May 28 01:36:22 PM PDT 24 281403775 ps
T359 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.614290140 May 28 01:34:18 PM PDT 24 May 28 01:34:39 PM PDT 24 3687308563 ps
T72 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3489484373 May 28 01:34:46 PM PDT 24 May 28 01:34:56 PM PDT 24 169386928 ps
T68 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.858362420 May 28 01:34:58 PM PDT 24 May 28 01:35:31 PM PDT 24 8518077503 ps
T69 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.69792649 May 28 01:34:19 PM PDT 24 May 28 01:34:33 PM PDT 24 689615636 ps
T360 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.431762224 May 28 01:34:16 PM PDT 24 May 28 01:34:50 PM PDT 24 4447243802 ps
T361 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2798943201 May 28 01:34:05 PM PDT 24 May 28 01:34:33 PM PDT 24 19687253867 ps
T102 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3127998004 May 28 01:34:30 PM PDT 24 May 28 01:35:30 PM PDT 24 1326826904 ps
T106 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1452122481 May 28 01:34:44 PM PDT 24 May 28 01:36:18 PM PDT 24 19453951878 ps
T362 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3039492899 May 28 01:34:31 PM PDT 24 May 28 01:34:50 PM PDT 24 1312936997 ps
T363 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1055506262 May 28 01:34:58 PM PDT 24 May 28 01:35:25 PM PDT 24 4368531433 ps
T97 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2564507764 May 28 01:34:44 PM PDT 24 May 28 01:34:54 PM PDT 24 331904036 ps
T364 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.189904165 May 28 01:34:45 PM PDT 24 May 28 01:35:22 PM PDT 24 4129434740 ps
T73 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2679531298 May 28 01:34:46 PM PDT 24 May 28 01:35:07 PM PDT 24 3711360279 ps
T365 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1708471833 May 28 01:35:17 PM PDT 24 May 28 01:35:47 PM PDT 24 3115872763 ps
T366 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2328130217 May 28 01:35:17 PM PDT 24 May 28 01:35:49 PM PDT 24 7014731751 ps
T74 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.583828351 May 28 01:35:17 PM PDT 24 May 28 01:36:37 PM PDT 24 6101310581 ps
T367 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3531046100 May 28 01:35:00 PM PDT 24 May 28 01:35:10 PM PDT 24 184077341 ps
T368 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1632100667 May 28 01:35:16 PM PDT 24 May 28 01:35:35 PM PDT 24 1978054717 ps
T75 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3111370228 May 28 01:35:17 PM PDT 24 May 28 01:37:33 PM PDT 24 64461490370 ps
T76 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1541478757 May 28 01:34:44 PM PDT 24 May 28 01:35:17 PM PDT 24 4109023886 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3161448750 May 28 01:34:06 PM PDT 24 May 28 01:34:26 PM PDT 24 24508851954 ps
T370 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1437052853 May 28 01:35:00 PM PDT 24 May 28 01:36:29 PM PDT 24 4213845326 ps
T371 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2238264420 May 28 01:34:05 PM PDT 24 May 28 01:34:19 PM PDT 24 2748295103 ps
T372 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2156196207 May 28 01:34:30 PM PDT 24 May 28 01:34:58 PM PDT 24 3145843684 ps
T373 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3049659367 May 28 01:34:29 PM PDT 24 May 28 01:35:04 PM PDT 24 9394125371 ps
T374 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3106434474 May 28 01:35:17 PM PDT 24 May 28 01:35:31 PM PDT 24 174545858 ps
T375 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3660403283 May 28 01:35:00 PM PDT 24 May 28 01:35:58 PM PDT 24 2146356171 ps
T376 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.510283331 May 28 01:34:05 PM PDT 24 May 28 01:34:32 PM PDT 24 4777649133 ps
T377 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.794920639 May 28 01:34:15 PM PDT 24 May 28 01:34:25 PM PDT 24 174566332 ps
T77 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1504065465 May 28 01:34:16 PM PDT 24 May 28 01:34:30 PM PDT 24 336016572 ps
T378 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.282218511 May 28 01:34:17 PM PDT 24 May 28 01:34:34 PM PDT 24 2093522540 ps
T112 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2965812775 May 28 01:34:08 PM PDT 24 May 28 01:35:31 PM PDT 24 507148291 ps
T379 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1225391564 May 28 01:34:09 PM PDT 24 May 28 01:34:43 PM PDT 24 17345547092 ps
T380 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3735474806 May 28 01:35:15 PM PDT 24 May 28 01:35:43 PM PDT 24 5279886229 ps
T381 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3877022380 May 28 01:34:45 PM PDT 24 May 28 01:35:18 PM PDT 24 17192731038 ps
T382 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3894814267 May 28 01:35:17 PM PDT 24 May 28 01:35:34 PM PDT 24 2458994811 ps
T383 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2203753663 May 28 01:35:16 PM PDT 24 May 28 01:35:29 PM PDT 24 380350802 ps
T384 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2894067564 May 28 01:34:43 PM PDT 24 May 28 01:34:53 PM PDT 24 635399369 ps
T78 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3205338288 May 28 01:35:19 PM PDT 24 May 28 01:35:40 PM PDT 24 8668387187 ps
T108 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3976714926 May 28 01:34:44 PM PDT 24 May 28 01:36:23 PM PDT 24 13411784179 ps
T98 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3191630693 May 28 01:34:16 PM PDT 24 May 28 01:34:43 PM PDT 24 31972722394 ps
T109 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2070284143 May 28 01:34:44 PM PDT 24 May 28 01:37:23 PM PDT 24 1304734099 ps
T107 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.481152746 May 28 01:35:18 PM PDT 24 May 28 01:36:59 PM PDT 24 2901326164 ps
T385 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1227509529 May 28 01:34:31 PM PDT 24 May 28 01:34:45 PM PDT 24 444369030 ps
T386 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4121300060 May 28 01:34:45 PM PDT 24 May 28 01:35:14 PM PDT 24 4597397997 ps
T387 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1014965877 May 28 01:34:05 PM PDT 24 May 28 01:34:19 PM PDT 24 9198833069 ps
T82 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.967460894 May 28 01:34:17 PM PDT 24 May 28 01:34:58 PM PDT 24 34319804863 ps
T388 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3880644391 May 28 01:34:44 PM PDT 24 May 28 01:35:10 PM PDT 24 3616197934 ps
T389 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4002776215 May 28 01:35:24 PM PDT 24 May 28 01:35:50 PM PDT 24 5742816321 ps
T83 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3466942104 May 28 01:35:16 PM PDT 24 May 28 01:35:32 PM PDT 24 9584826442 ps
T99 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2603540522 May 28 01:34:29 PM PDT 24 May 28 01:34:53 PM PDT 24 5140259659 ps
T84 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.719351421 May 28 01:35:15 PM PDT 24 May 28 01:35:41 PM PDT 24 2246479262 ps
T390 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2212428304 May 28 01:34:59 PM PDT 24 May 28 01:35:17 PM PDT 24 2742011418 ps
T110 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2411436615 May 28 01:35:17 PM PDT 24 May 28 01:36:51 PM PDT 24 1642912182 ps
T391 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1394004195 May 28 01:34:05 PM PDT 24 May 28 01:34:17 PM PDT 24 2353878754 ps
T392 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1343510422 May 28 01:34:17 PM PDT 24 May 28 01:34:41 PM PDT 24 4786413782 ps
T393 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1486041845 May 28 01:35:18 PM PDT 24 May 28 01:35:30 PM PDT 24 338680008 ps
T394 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2194627530 May 28 01:35:17 PM PDT 24 May 28 01:35:49 PM PDT 24 2855334736 ps
T395 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2717101384 May 28 01:34:31 PM PDT 24 May 28 01:35:00 PM PDT 24 4039645883 ps
T91 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2025606947 May 28 01:34:30 PM PDT 24 May 28 01:35:10 PM PDT 24 7054973554 ps
T396 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1120458413 May 28 01:34:45 PM PDT 24 May 28 01:35:44 PM PDT 24 3014520420 ps
T397 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4018090472 May 28 01:34:30 PM PDT 24 May 28 01:34:55 PM PDT 24 4546114872 ps
T398 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3357487709 May 28 01:35:00 PM PDT 24 May 28 01:35:25 PM PDT 24 5106601645 ps
T399 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4092381876 May 28 01:34:05 PM PDT 24 May 28 01:34:15 PM PDT 24 1029915731 ps
T400 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.101151557 May 28 01:34:59 PM PDT 24 May 28 01:35:09 PM PDT 24 719465145 ps
T401 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1068932535 May 28 01:34:04 PM PDT 24 May 28 01:34:32 PM PDT 24 2399706086 ps
T402 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2562870408 May 28 01:34:16 PM PDT 24 May 28 01:34:27 PM PDT 24 167656636 ps
T114 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4180831167 May 28 01:34:29 PM PDT 24 May 28 01:35:59 PM PDT 24 1012092852 ps
T403 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2900824515 May 28 01:34:44 PM PDT 24 May 28 01:35:42 PM PDT 24 4311717060 ps
T85 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.404967414 May 28 01:34:58 PM PDT 24 May 28 01:37:03 PM PDT 24 58925583378 ps
T86 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.169182192 May 28 01:34:17 PM PDT 24 May 28 01:34:44 PM PDT 24 5787928778 ps
T87 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2912055408 May 28 01:35:15 PM PDT 24 May 28 01:38:04 PM PDT 24 18483111928 ps
T404 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3774941515 May 28 01:35:18 PM PDT 24 May 28 01:35:42 PM PDT 24 7596134717 ps
T88 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.361146187 May 28 01:34:06 PM PDT 24 May 28 01:35:05 PM PDT 24 4495879943 ps
T405 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.908047333 May 28 01:35:18 PM PDT 24 May 28 01:35:42 PM PDT 24 8892081125 ps
T406 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2123705892 May 28 01:34:44 PM PDT 24 May 28 01:35:03 PM PDT 24 4485624794 ps
T407 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1203624436 May 28 01:34:58 PM PDT 24 May 28 01:35:13 PM PDT 24 181735402 ps
T408 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3848705895 May 28 01:35:16 PM PDT 24 May 28 01:36:30 PM PDT 24 11935040246 ps
T409 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1196108628 May 28 01:34:30 PM PDT 24 May 28 01:34:50 PM PDT 24 2835232099 ps
T410 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2345670311 May 28 01:35:00 PM PDT 24 May 28 01:35:24 PM PDT 24 1485871009 ps
T92 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.390969651 May 28 01:34:47 PM PDT 24 May 28 01:36:17 PM PDT 24 5060837952 ps
T411 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.546122525 May 28 01:34:44 PM PDT 24 May 28 01:35:11 PM PDT 24 5208118291 ps
T412 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.68132124 May 28 01:35:17 PM PDT 24 May 28 01:35:58 PM PDT 24 17776104237 ps
T413 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2859204020 May 28 01:35:01 PM PDT 24 May 28 01:35:30 PM PDT 24 17461223362 ps
T414 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3626361568 May 28 01:34:57 PM PDT 24 May 28 01:35:21 PM PDT 24 9486656562 ps
T415 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.436256448 May 28 01:34:30 PM PDT 24 May 28 01:34:53 PM PDT 24 1890914169 ps
T416 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1732312580 May 28 01:34:17 PM PDT 24 May 28 01:34:27 PM PDT 24 345751158 ps
T417 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1011483792 May 28 01:34:44 PM PDT 24 May 28 01:35:17 PM PDT 24 3905043289 ps
T418 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4290095504 May 28 01:34:05 PM PDT 24 May 28 01:34:38 PM PDT 24 11238416881 ps
T419 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3242463814 May 28 01:34:32 PM PDT 24 May 28 01:34:55 PM PDT 24 8546036682 ps
T420 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2629508300 May 28 01:34:57 PM PDT 24 May 28 01:35:14 PM PDT 24 2398986203 ps
T421 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.808957392 May 28 01:34:18 PM PDT 24 May 28 01:34:32 PM PDT 24 3873488632 ps
T93 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1548953923 May 28 01:35:00 PM PDT 24 May 28 01:35:23 PM PDT 24 2441493770 ps
T422 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1006627840 May 28 01:35:00 PM PDT 24 May 28 01:35:26 PM PDT 24 7892237633 ps
T423 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3909306195 May 28 01:35:19 PM PDT 24 May 28 01:35:30 PM PDT 24 171624913 ps
T424 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2502258243 May 28 01:35:17 PM PDT 24 May 28 01:35:40 PM PDT 24 4016933756 ps
T425 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1161500261 May 28 01:34:16 PM PDT 24 May 28 01:34:32 PM PDT 24 3233412591 ps
T426 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.270895350 May 28 01:35:15 PM PDT 24 May 28 01:35:38 PM PDT 24 1934598019 ps
T94 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.564957976 May 28 01:35:18 PM PDT 24 May 28 01:38:17 PM PDT 24 67779774033 ps
T89 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2721947595 May 28 01:35:17 PM PDT 24 May 28 01:35:58 PM PDT 24 694313651 ps
T427 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1045664046 May 28 01:35:19 PM PDT 24 May 28 01:35:30 PM PDT 24 338863032 ps
T428 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1275725154 May 28 01:34:31 PM PDT 24 May 28 01:36:17 PM PDT 24 31689704410 ps
T429 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.67236782 May 28 01:34:30 PM PDT 24 May 28 01:34:41 PM PDT 24 167545980 ps
T430 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.825250321 May 28 01:34:32 PM PDT 24 May 28 01:35:01 PM PDT 24 13221544748 ps
T431 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1232252930 May 28 01:34:45 PM PDT 24 May 28 01:35:15 PM PDT 24 34821400821 ps
T432 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1840684715 May 28 01:34:05 PM PDT 24 May 28 01:36:22 PM PDT 24 34186969220 ps
T433 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.689298838 May 28 01:34:16 PM PDT 24 May 28 01:35:16 PM PDT 24 3116787543 ps
T434 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1504716012 May 28 01:35:17 PM PDT 24 May 28 01:35:40 PM PDT 24 3567711797 ps
T90 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1512197202 May 28 01:34:05 PM PDT 24 May 28 01:34:21 PM PDT 24 902603027 ps
T435 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1541013780 May 28 01:35:19 PM PDT 24 May 28 01:35:40 PM PDT 24 7808823267 ps
T436 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2922731620 May 28 01:34:45 PM PDT 24 May 28 01:36:29 PM PDT 24 39750833351 ps
T437 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2141911939 May 28 01:35:01 PM PDT 24 May 28 01:35:19 PM PDT 24 1316229834 ps
T113 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.124632463 May 28 01:35:17 PM PDT 24 May 28 01:36:45 PM PDT 24 605573697 ps
T438 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3130796965 May 28 01:34:05 PM PDT 24 May 28 01:34:37 PM PDT 24 15754659200 ps
T439 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3673146831 May 28 01:35:15 PM PDT 24 May 28 01:35:25 PM PDT 24 319895048 ps
T440 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4125516607 May 28 01:34:16 PM PDT 24 May 28 01:34:39 PM PDT 24 10635820644 ps
T111 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1789440259 May 28 01:35:22 PM PDT 24 May 28 01:36:58 PM PDT 24 9185681055 ps
T441 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2383762576 May 28 01:35:16 PM PDT 24 May 28 01:35:57 PM PDT 24 18992238534 ps
T442 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3395268194 May 28 01:34:15 PM PDT 24 May 28 01:35:42 PM PDT 24 2634595204 ps
T104 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1589659976 May 28 01:34:16 PM PDT 24 May 28 01:37:13 PM PDT 24 8000532354 ps
T443 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2081501772 May 28 01:35:18 PM PDT 24 May 28 01:37:57 PM PDT 24 645218522 ps
T105 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2482177731 May 28 01:34:06 PM PDT 24 May 28 01:36:57 PM PDT 24 2632935255 ps
T444 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1628463119 May 28 01:34:19 PM PDT 24 May 28 01:34:48 PM PDT 24 6845758865 ps
T445 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2073956906 May 28 01:34:31 PM PDT 24 May 28 01:36:12 PM PDT 24 22077846360 ps
T446 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3156429858 May 28 01:34:05 PM PDT 24 May 28 01:34:39 PM PDT 24 4173947183 ps
T447 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3965478458 May 28 01:34:46 PM PDT 24 May 28 01:35:20 PM PDT 24 17779745038 ps
T448 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1591546383 May 28 01:34:03 PM PDT 24 May 28 01:34:25 PM PDT 24 7910825316 ps

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2380181440
Short name T1
Test name
Test status
Simulation time 44430140722 ps
CPU time 381.82 seconds
Started May 28 01:46:04 PM PDT 24
Finished May 28 01:52:36 PM PDT 24
Peak memory 237548 kb
Host smart-d02dda6a-4172-401e-8e99-6c638c1b3ca4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380181440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2380181440
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2684064200
Short name T26
Test name
Test status
Simulation time 57020221420 ps
CPU time 2634.91 seconds
Started May 28 01:45:40 PM PDT 24
Finished May 28 02:29:36 PM PDT 24
Peak memory 235672 kb
Host smart-a866c4cb-e08d-455e-83ef-682a3ebeeb3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684064200 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.2684064200
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.4014674054
Short name T12
Test name
Test status
Simulation time 4791205583 ps
CPU time 51.96 seconds
Started May 28 01:44:47 PM PDT 24
Finished May 28 01:45:41 PM PDT 24
Peak memory 220380 kb
Host smart-f2e32f89-dc29-4c82-8ef8-057a0c6d5dfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014674054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.4014674054
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3510472831
Short name T23
Test name
Test status
Simulation time 2685890272 ps
CPU time 125.29 seconds
Started May 28 01:44:37 PM PDT 24
Finished May 28 01:46:45 PM PDT 24
Peak memory 237048 kb
Host smart-96ec74a8-616c-498f-a498-dd40fe6c22d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510472831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3510472831
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2070284143
Short name T109
Test name
Test status
Simulation time 1304734099 ps
CPU time 157.34 seconds
Started May 28 01:34:44 PM PDT 24
Finished May 28 01:37:23 PM PDT 24
Peak memory 215056 kb
Host smart-c46faca4-4982-4052-8d12-aa511fdf15b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070284143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2070284143
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.583828351
Short name T74
Test name
Test status
Simulation time 6101310581 ps
CPU time 76.32 seconds
Started May 28 01:35:17 PM PDT 24
Finished May 28 01:36:37 PM PDT 24
Peak memory 214404 kb
Host smart-515af52d-b3b5-416c-bc6b-aaf4d8ecba5e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583828351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.583828351
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2949507183
Short name T24
Test name
Test status
Simulation time 751910498 ps
CPU time 27.68 seconds
Started May 28 01:45:17 PM PDT 24
Finished May 28 01:45:46 PM PDT 24
Peak memory 215292 kb
Host smart-cb429998-6f36-445d-bcd0-e6900d833149
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949507183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2949507183
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.481152746
Short name T107
Test name
Test status
Simulation time 2901326164 ps
CPU time 97.86 seconds
Started May 28 01:35:18 PM PDT 24
Finished May 28 01:36:59 PM PDT 24
Peak memory 213644 kb
Host smart-35e2133d-ccb9-42ea-bcd6-9d3c4fbcd601
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481152746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.481152746
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.690252156
Short name T27
Test name
Test status
Simulation time 80435373701 ps
CPU time 1508.09 seconds
Started May 28 01:45:21 PM PDT 24
Finished May 28 02:10:32 PM PDT 24
Peak memory 235760 kb
Host smart-801df7da-6917-4846-922e-ab6ea417ac81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690252156 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.690252156
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.498257662
Short name T32
Test name
Test status
Simulation time 6442397790 ps
CPU time 16.48 seconds
Started May 28 01:45:21 PM PDT 24
Finished May 28 01:45:40 PM PDT 24
Peak memory 212072 kb
Host smart-95a75827-e68d-4a09-81af-9afb3a961adf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498257662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.498257662
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2006836022
Short name T52
Test name
Test status
Simulation time 24353585734 ps
CPU time 70.48 seconds
Started May 28 01:44:36 PM PDT 24
Finished May 28 01:45:49 PM PDT 24
Peak memory 214816 kb
Host smart-c8d30f03-bc4b-4470-95e4-53ee50fbf9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006836022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2006836022
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.826237715
Short name T15
Test name
Test status
Simulation time 16704254993 ps
CPU time 68.96 seconds
Started May 28 01:45:16 PM PDT 24
Finished May 28 01:46:25 PM PDT 24
Peak memory 214864 kb
Host smart-d4e9e767-13f4-4284-9ec1-b197fd9f58c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826237715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.826237715
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1589659976
Short name T104
Test name
Test status
Simulation time 8000532354 ps
CPU time 174.24 seconds
Started May 28 01:34:16 PM PDT 24
Finished May 28 01:37:13 PM PDT 24
Peak memory 214384 kb
Host smart-e6032bd0-cc30-4640-a81c-8bd1f90be288
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589659976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1589659976
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1452122481
Short name T106
Test name
Test status
Simulation time 19453951878 ps
CPU time 92.9 seconds
Started May 28 01:34:44 PM PDT 24
Finished May 28 01:36:18 PM PDT 24
Peak memory 213932 kb
Host smart-ce546ea0-9e35-4ac2-a001-288347374144
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452122481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1452122481
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.513800235
Short name T49
Test name
Test status
Simulation time 834764635 ps
CPU time 156.88 seconds
Started May 28 01:35:02 PM PDT 24
Finished May 28 01:37:40 PM PDT 24
Peak memory 213872 kb
Host smart-dfe6972b-843e-40c7-9f32-789fd95e45d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513800235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.513800235
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.361146187
Short name T88
Test name
Test status
Simulation time 4495879943 ps
CPU time 58.24 seconds
Started May 28 01:34:06 PM PDT 24
Finished May 28 01:35:05 PM PDT 24
Peak memory 219556 kb
Host smart-a2565333-ceac-48cd-92e5-64f7382136a7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361146187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.361146187
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4121584249
Short name T166
Test name
Test status
Simulation time 14181719996 ps
CPU time 233.56 seconds
Started May 28 01:45:15 PM PDT 24
Finished May 28 01:49:09 PM PDT 24
Peak memory 225272 kb
Host smart-145fb182-2250-467a-8baa-95bdd9579342
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121584249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.4121584249
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1868454823
Short name T101
Test name
Test status
Simulation time 1135074238 ps
CPU time 13.14 seconds
Started May 28 01:34:09 PM PDT 24
Finished May 28 01:34:23 PM PDT 24
Peak memory 211252 kb
Host smart-d094f447-28fc-4ff8-bc25-5da449a488e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868454823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1868454823
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2238264420
Short name T371
Test name
Test status
Simulation time 2748295103 ps
CPU time 13.12 seconds
Started May 28 01:34:05 PM PDT 24
Finished May 28 01:34:19 PM PDT 24
Peak memory 211316 kb
Host smart-a93e332e-ecd2-4b42-88a8-58f259840a20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238264420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2238264420
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3161448750
Short name T369
Test name
Test status
Simulation time 24508851954 ps
CPU time 18.63 seconds
Started May 28 01:34:06 PM PDT 24
Finished May 28 01:34:26 PM PDT 24
Peak memory 212084 kb
Host smart-a66f44e3-dbbc-428e-8543-ab16e3ebe0e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161448750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3161448750
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1591546383
Short name T448
Test name
Test status
Simulation time 7910825316 ps
CPU time 20.42 seconds
Started May 28 01:34:03 PM PDT 24
Finished May 28 01:34:25 PM PDT 24
Peak memory 218360 kb
Host smart-36056328-b2c4-476b-86b2-a10ad023b3d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591546383 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1591546383
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1225391564
Short name T379
Test name
Test status
Simulation time 17345547092 ps
CPU time 33.32 seconds
Started May 28 01:34:09 PM PDT 24
Finished May 28 01:34:43 PM PDT 24
Peak memory 212212 kb
Host smart-3020bf49-4281-4cdf-81b5-ffdee6f5f924
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225391564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1225391564
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.510283331
Short name T376
Test name
Test status
Simulation time 4777649133 ps
CPU time 24.94 seconds
Started May 28 01:34:05 PM PDT 24
Finished May 28 01:34:32 PM PDT 24
Peak memory 211240 kb
Host smart-f9910d43-3f63-4b51-9148-cc46af81af6d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510283331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.510283331
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.22573944
Short name T357
Test name
Test status
Simulation time 9455719610 ps
CPU time 25.42 seconds
Started May 28 01:34:04 PM PDT 24
Finished May 28 01:34:30 PM PDT 24
Peak memory 211272 kb
Host smart-b21e502d-7b9f-4aa2-aba7-d985502bc8b3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22573944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.22573944
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2579453578
Short name T96
Test name
Test status
Simulation time 4263986638 ps
CPU time 30.9 seconds
Started May 28 01:34:05 PM PDT 24
Finished May 28 01:34:38 PM PDT 24
Peak memory 212156 kb
Host smart-53e866fc-3d51-45e7-9300-dbd75011fa8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579453578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2579453578
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1394004195
Short name T391
Test name
Test status
Simulation time 2353878754 ps
CPU time 11.44 seconds
Started May 28 01:34:05 PM PDT 24
Finished May 28 01:34:17 PM PDT 24
Peak memory 217052 kb
Host smart-9ebef3db-239a-40cd-ad7c-8f90e3934f94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394004195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1394004195
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2482177731
Short name T105
Test name
Test status
Simulation time 2632935255 ps
CPU time 169.72 seconds
Started May 28 01:34:06 PM PDT 24
Finished May 28 01:36:57 PM PDT 24
Peak memory 215024 kb
Host smart-d393c308-d133-4529-8d1b-3f3aa2e80036
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482177731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2482177731
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1512197202
Short name T90
Test name
Test status
Simulation time 902603027 ps
CPU time 14.27 seconds
Started May 28 01:34:05 PM PDT 24
Finished May 28 01:34:21 PM PDT 24
Peak memory 211268 kb
Host smart-68bf83fa-a13b-4218-a3ab-132fa7e60c17
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512197202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1512197202
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1014965877
Short name T387
Test name
Test status
Simulation time 9198833069 ps
CPU time 12.84 seconds
Started May 28 01:34:05 PM PDT 24
Finished May 28 01:34:19 PM PDT 24
Peak memory 211268 kb
Host smart-75945acd-d188-496a-bcf7-bd709cbd6caf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014965877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1014965877
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1068932535
Short name T401
Test name
Test status
Simulation time 2399706086 ps
CPU time 26.55 seconds
Started May 28 01:34:04 PM PDT 24
Finished May 28 01:34:32 PM PDT 24
Peak memory 211732 kb
Host smart-ee318f94-d451-4c72-80dd-380c6a793ab9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068932535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1068932535
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2798943201
Short name T361
Test name
Test status
Simulation time 19687253867 ps
CPU time 26.17 seconds
Started May 28 01:34:05 PM PDT 24
Finished May 28 01:34:33 PM PDT 24
Peak memory 216432 kb
Host smart-0c8392c5-19e3-4aef-8c67-f076d845c96e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798943201 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2798943201
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4092381876
Short name T399
Test name
Test status
Simulation time 1029915731 ps
CPU time 8.35 seconds
Started May 28 01:34:05 PM PDT 24
Finished May 28 01:34:15 PM PDT 24
Peak memory 211292 kb
Host smart-8c67f8df-b57c-45db-8cd7-64dd9a43de46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092381876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4092381876
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3156429858
Short name T446
Test name
Test status
Simulation time 4173947183 ps
CPU time 32.01 seconds
Started May 28 01:34:05 PM PDT 24
Finished May 28 01:34:39 PM PDT 24
Peak memory 211196 kb
Host smart-5a5e8c39-a155-44a4-bc08-98f95b7e0fa4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156429858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3156429858
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4290095504
Short name T418
Test name
Test status
Simulation time 11238416881 ps
CPU time 32.19 seconds
Started May 28 01:34:05 PM PDT 24
Finished May 28 01:34:38 PM PDT 24
Peak memory 211200 kb
Host smart-805ed8db-cf2d-4c2e-a0a4-f38006a8b48c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290095504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.4290095504
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3130796965
Short name T438
Test name
Test status
Simulation time 15754659200 ps
CPU time 30.91 seconds
Started May 28 01:34:05 PM PDT 24
Finished May 28 01:34:37 PM PDT 24
Peak memory 212696 kb
Host smart-ee3e6cd7-b331-4766-8436-fb66d53dc6f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130796965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3130796965
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2695087072
Short name T47
Test name
Test status
Simulation time 670871832 ps
CPU time 13.96 seconds
Started May 28 01:34:05 PM PDT 24
Finished May 28 01:34:20 PM PDT 24
Peak memory 217492 kb
Host smart-4f2a8c40-fd3a-4ed1-b6c2-2923e12f6fb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695087072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2695087072
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2965812775
Short name T112
Test name
Test status
Simulation time 507148291 ps
CPU time 82.33 seconds
Started May 28 01:34:08 PM PDT 24
Finished May 28 01:35:31 PM PDT 24
Peak memory 213588 kb
Host smart-ec04a338-bc1f-4f43-ab20-6d8d5837dbff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965812775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2965812775
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3626361568
Short name T414
Test name
Test status
Simulation time 9486656562 ps
CPU time 22.31 seconds
Started May 28 01:34:57 PM PDT 24
Finished May 28 01:35:21 PM PDT 24
Peak memory 214880 kb
Host smart-b73e0f67-d13a-4f1d-b6eb-150d5bf36cb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626361568 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3626361568
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.101151557
Short name T400
Test name
Test status
Simulation time 719465145 ps
CPU time 8.45 seconds
Started May 28 01:34:59 PM PDT 24
Finished May 28 01:35:09 PM PDT 24
Peak memory 211164 kb
Host smart-85e6ed7a-5a61-410f-93bc-63c566dc2693
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101151557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.101151557
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3660403283
Short name T375
Test name
Test status
Simulation time 2146356171 ps
CPU time 56.42 seconds
Started May 28 01:35:00 PM PDT 24
Finished May 28 01:35:58 PM PDT 24
Peak memory 215420 kb
Host smart-ae9dfee0-14db-4026-8694-90f4b7b10d50
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660403283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3660403283
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2212428304
Short name T390
Test name
Test status
Simulation time 2742011418 ps
CPU time 16.59 seconds
Started May 28 01:34:59 PM PDT 24
Finished May 28 01:35:17 PM PDT 24
Peak memory 212236 kb
Host smart-54832568-ac14-41f3-8723-05491028230b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212428304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2212428304
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.942574168
Short name T48
Test name
Test status
Simulation time 3995797678 ps
CPU time 37.72 seconds
Started May 28 01:35:00 PM PDT 24
Finished May 28 01:35:39 PM PDT 24
Peak memory 218776 kb
Host smart-84b00ed8-287a-4e5e-a47f-285b2db1f586
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942574168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.942574168
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3787276084
Short name T67
Test name
Test status
Simulation time 281403775 ps
CPU time 82.41 seconds
Started May 28 01:34:58 PM PDT 24
Finished May 28 01:36:22 PM PDT 24
Peak memory 213708 kb
Host smart-48933099-87a0-40e5-9bec-f15a811914bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787276084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3787276084
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.858362420
Short name T68
Test name
Test status
Simulation time 8518077503 ps
CPU time 31.69 seconds
Started May 28 01:34:58 PM PDT 24
Finished May 28 01:35:31 PM PDT 24
Peak memory 218344 kb
Host smart-44b8fc44-d3bc-4ec6-bac2-14f81c525e8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858362420 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.858362420
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2953825660
Short name T60
Test name
Test status
Simulation time 29157039921 ps
CPU time 32.71 seconds
Started May 28 01:34:58 PM PDT 24
Finished May 28 01:35:32 PM PDT 24
Peak memory 212328 kb
Host smart-c53b4be8-0027-4317-a651-1dd49b9bd381
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953825660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2953825660
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.216495576
Short name T59
Test name
Test status
Simulation time 21190997361 ps
CPU time 98.75 seconds
Started May 28 01:34:59 PM PDT 24
Finished May 28 01:36:39 PM PDT 24
Peak memory 213900 kb
Host smart-e73e10f9-59e4-425f-8751-421dfec7bc2e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216495576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.216495576
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3357487709
Short name T398
Test name
Test status
Simulation time 5106601645 ps
CPU time 22.88 seconds
Started May 28 01:35:00 PM PDT 24
Finished May 28 01:35:25 PM PDT 24
Peak memory 212132 kb
Host smart-872b9112-685c-471d-9624-369f1eb96219
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357487709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3357487709
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1203624436
Short name T407
Test name
Test status
Simulation time 181735402 ps
CPU time 13.65 seconds
Started May 28 01:34:58 PM PDT 24
Finished May 28 01:35:13 PM PDT 24
Peak memory 217732 kb
Host smart-fef37684-521e-43a4-a8c1-9a1b9d8bb2e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203624436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1203624436
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1437052853
Short name T370
Test name
Test status
Simulation time 4213845326 ps
CPU time 87.67 seconds
Started May 28 01:35:00 PM PDT 24
Finished May 28 01:36:29 PM PDT 24
Peak memory 213708 kb
Host smart-4cac9645-7cae-4aa4-a61b-f3ba46dc0c78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437052853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1437052853
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1055506262
Short name T363
Test name
Test status
Simulation time 4368531433 ps
CPU time 24.74 seconds
Started May 28 01:34:58 PM PDT 24
Finished May 28 01:35:25 PM PDT 24
Peak memory 216936 kb
Host smart-706f5d5d-1021-4c4c-86be-944218b78828
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055506262 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1055506262
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1548953923
Short name T93
Test name
Test status
Simulation time 2441493770 ps
CPU time 20.78 seconds
Started May 28 01:35:00 PM PDT 24
Finished May 28 01:35:23 PM PDT 24
Peak memory 212080 kb
Host smart-1caef984-ba5e-4c1f-b8ca-a8e37da07ba3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548953923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1548953923
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3824645708
Short name T100
Test name
Test status
Simulation time 125690172017 ps
CPU time 85.72 seconds
Started May 28 01:35:01 PM PDT 24
Finished May 28 01:36:28 PM PDT 24
Peak memory 213468 kb
Host smart-d080c456-1de3-43cf-8ad8-4775a1b7675f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824645708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3824645708
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2629508300
Short name T420
Test name
Test status
Simulation time 2398986203 ps
CPU time 15.8 seconds
Started May 28 01:34:57 PM PDT 24
Finished May 28 01:35:14 PM PDT 24
Peak memory 212380 kb
Host smart-f2a31c8f-89cb-4fc3-9248-b1dbfd387e65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629508300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2629508300
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2859204020
Short name T413
Test name
Test status
Simulation time 17461223362 ps
CPU time 27.49 seconds
Started May 28 01:35:01 PM PDT 24
Finished May 28 01:35:30 PM PDT 24
Peak memory 218480 kb
Host smart-c7515089-a590-40db-94ce-caac813cd2ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859204020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2859204020
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3419599913
Short name T45
Test name
Test status
Simulation time 4348357276 ps
CPU time 105.3 seconds
Started May 28 01:35:00 PM PDT 24
Finished May 28 01:36:47 PM PDT 24
Peak memory 214768 kb
Host smart-0aa95fa5-2c4c-4057-b69b-a30e06e791fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419599913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3419599913
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3774941515
Short name T404
Test name
Test status
Simulation time 7596134717 ps
CPU time 20.82 seconds
Started May 28 01:35:18 PM PDT 24
Finished May 28 01:35:42 PM PDT 24
Peak memory 218968 kb
Host smart-b93ac7d1-397c-4c91-8c77-ecadbf08cc5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774941515 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3774941515
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2141911939
Short name T437
Test name
Test status
Simulation time 1316229834 ps
CPU time 16.41 seconds
Started May 28 01:35:01 PM PDT 24
Finished May 28 01:35:19 PM PDT 24
Peak memory 211304 kb
Host smart-eadbdac9-6faa-40fe-8054-cd43cff73601
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141911939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2141911939
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.404967414
Short name T85
Test name
Test status
Simulation time 58925583378 ps
CPU time 123.51 seconds
Started May 28 01:34:58 PM PDT 24
Finished May 28 01:37:03 PM PDT 24
Peak memory 213408 kb
Host smart-a04b5578-e91b-4129-bde2-c061631f0b37
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404967414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.404967414
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1006627840
Short name T422
Test name
Test status
Simulation time 7892237633 ps
CPU time 24.73 seconds
Started May 28 01:35:00 PM PDT 24
Finished May 28 01:35:26 PM PDT 24
Peak memory 212752 kb
Host smart-90b56759-957e-4097-878b-d05b9c25c6c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006627840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1006627840
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2345670311
Short name T410
Test name
Test status
Simulation time 1485871009 ps
CPU time 23.02 seconds
Started May 28 01:35:00 PM PDT 24
Finished May 28 01:35:24 PM PDT 24
Peak memory 217288 kb
Host smart-422f8ced-5fec-49db-8adb-cace6269ca1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345670311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2345670311
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3735474806
Short name T380
Test name
Test status
Simulation time 5279886229 ps
CPU time 24.51 seconds
Started May 28 01:35:15 PM PDT 24
Finished May 28 01:35:43 PM PDT 24
Peak memory 218392 kb
Host smart-b68e3c3f-d89b-4e6f-8033-dd6e9a3611a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735474806 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3735474806
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.908047333
Short name T405
Test name
Test status
Simulation time 8892081125 ps
CPU time 21.23 seconds
Started May 28 01:35:18 PM PDT 24
Finished May 28 01:35:42 PM PDT 24
Peak memory 212328 kb
Host smart-e784adcd-7bda-4b22-8f7f-7d0233cca7ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908047333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.908047333
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3848705895
Short name T408
Test name
Test status
Simulation time 11935040246 ps
CPU time 70.89 seconds
Started May 28 01:35:16 PM PDT 24
Finished May 28 01:36:30 PM PDT 24
Peak memory 219428 kb
Host smart-857e70cd-8fbb-42c1-a45a-8682db5bf1af
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848705895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3848705895
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1486041845
Short name T393
Test name
Test status
Simulation time 338680008 ps
CPU time 8.51 seconds
Started May 28 01:35:18 PM PDT 24
Finished May 28 01:35:30 PM PDT 24
Peak memory 211404 kb
Host smart-7617f40e-72c5-404d-9589-3f65f7dfec20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486041845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1486041845
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.68132124
Short name T412
Test name
Test status
Simulation time 17776104237 ps
CPU time 38.23 seconds
Started May 28 01:35:17 PM PDT 24
Finished May 28 01:35:58 PM PDT 24
Peak memory 219620 kb
Host smart-23feca14-f490-4303-ac86-d4c1623fc2a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68132124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.68132124
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3718007125
Short name T58
Test name
Test status
Simulation time 15113511559 ps
CPU time 99.41 seconds
Started May 28 01:35:15 PM PDT 24
Finished May 28 01:36:57 PM PDT 24
Peak memory 219440 kb
Host smart-e741e9b2-c48d-406c-adff-3d9980dd03ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718007125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3718007125
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1708471833
Short name T365
Test name
Test status
Simulation time 3115872763 ps
CPU time 26.5 seconds
Started May 28 01:35:17 PM PDT 24
Finished May 28 01:35:47 PM PDT 24
Peak memory 217936 kb
Host smart-1e195ea9-718f-46b6-9a60-b1c3f39932c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708471833 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1708471833
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1541013780
Short name T435
Test name
Test status
Simulation time 7808823267 ps
CPU time 18.12 seconds
Started May 28 01:35:19 PM PDT 24
Finished May 28 01:35:40 PM PDT 24
Peak memory 212184 kb
Host smart-40b78be6-d436-40a1-92d0-2670f0c601f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541013780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1541013780
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1045664046
Short name T427
Test name
Test status
Simulation time 338863032 ps
CPU time 8.4 seconds
Started May 28 01:35:19 PM PDT 24
Finished May 28 01:35:30 PM PDT 24
Peak memory 211276 kb
Host smart-bfe59b50-617a-4810-8ccb-92da5bbea071
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045664046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1045664046
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1632100667
Short name T368
Test name
Test status
Simulation time 1978054717 ps
CPU time 15.27 seconds
Started May 28 01:35:16 PM PDT 24
Finished May 28 01:35:35 PM PDT 24
Peak memory 217288 kb
Host smart-2643e242-dc01-4501-8482-3431a698ff41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632100667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1632100667
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2081501772
Short name T443
Test name
Test status
Simulation time 645218522 ps
CPU time 155.45 seconds
Started May 28 01:35:18 PM PDT 24
Finished May 28 01:37:57 PM PDT 24
Peak memory 214100 kb
Host smart-9dbd89ef-669d-45b7-9dc7-b57985bcf2ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081501772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2081501772
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2203753663
Short name T383
Test name
Test status
Simulation time 380350802 ps
CPU time 9.1 seconds
Started May 28 01:35:16 PM PDT 24
Finished May 28 01:35:29 PM PDT 24
Peak memory 216788 kb
Host smart-9766c761-5a05-4b22-ac6c-153ee496d456
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203753663 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2203753663
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.719351421
Short name T84
Test name
Test status
Simulation time 2246479262 ps
CPU time 22.77 seconds
Started May 28 01:35:15 PM PDT 24
Finished May 28 01:35:41 PM PDT 24
Peak memory 212100 kb
Host smart-0f16dfb4-0a78-477f-b651-15f334f0f1cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719351421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.719351421
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2721947595
Short name T89
Test name
Test status
Simulation time 694313651 ps
CPU time 37.67 seconds
Started May 28 01:35:17 PM PDT 24
Finished May 28 01:35:58 PM PDT 24
Peak memory 213632 kb
Host smart-7d4f9f68-eeb8-414b-bd98-8766c37ac61a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721947595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2721947595
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3205338288
Short name T78
Test name
Test status
Simulation time 8668387187 ps
CPU time 18.91 seconds
Started May 28 01:35:19 PM PDT 24
Finished May 28 01:35:40 PM PDT 24
Peak memory 212740 kb
Host smart-1b09938c-7441-45d0-bce9-aa9c2503e3c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205338288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3205338288
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3894814267
Short name T382
Test name
Test status
Simulation time 2458994811 ps
CPU time 14.03 seconds
Started May 28 01:35:17 PM PDT 24
Finished May 28 01:35:34 PM PDT 24
Peak memory 217600 kb
Host smart-7cee3107-7bb9-4188-b66c-d70b614ce080
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894814267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3894814267
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1789440259
Short name T111
Test name
Test status
Simulation time 9185681055 ps
CPU time 94.58 seconds
Started May 28 01:35:22 PM PDT 24
Finished May 28 01:36:58 PM PDT 24
Peak memory 214224 kb
Host smart-5ae1229f-2f30-4621-9d91-4c10c22b21ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789440259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1789440259
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2502258243
Short name T424
Test name
Test status
Simulation time 4016933756 ps
CPU time 19.77 seconds
Started May 28 01:35:17 PM PDT 24
Finished May 28 01:35:40 PM PDT 24
Peak memory 214368 kb
Host smart-04da630d-7ce3-4fac-b5f4-a15bbbc3e611
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502258243 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2502258243
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3466942104
Short name T83
Test name
Test status
Simulation time 9584826442 ps
CPU time 12.47 seconds
Started May 28 01:35:16 PM PDT 24
Finished May 28 01:35:32 PM PDT 24
Peak memory 211360 kb
Host smart-bdd9368a-a215-40ad-bae3-f7a6339f1d86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466942104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3466942104
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2912055408
Short name T87
Test name
Test status
Simulation time 18483111928 ps
CPU time 167 seconds
Started May 28 01:35:15 PM PDT 24
Finished May 28 01:38:04 PM PDT 24
Peak memory 215656 kb
Host smart-35d438da-1426-48c7-a954-119e6e821df1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912055408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2912055408
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4256896796
Short name T95
Test name
Test status
Simulation time 2737643905 ps
CPU time 12.12 seconds
Started May 28 01:35:19 PM PDT 24
Finished May 28 01:35:34 PM PDT 24
Peak memory 211372 kb
Host smart-0ac5e873-f370-4671-966c-83cdb6dd4d4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256896796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.4256896796
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1504716012
Short name T434
Test name
Test status
Simulation time 3567711797 ps
CPU time 19.05 seconds
Started May 28 01:35:17 PM PDT 24
Finished May 28 01:35:40 PM PDT 24
Peak memory 218568 kb
Host smart-093425c4-e82a-4c44-ba4a-3db88de3e182
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504716012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1504716012
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.124632463
Short name T113
Test name
Test status
Simulation time 605573697 ps
CPU time 84.72 seconds
Started May 28 01:35:17 PM PDT 24
Finished May 28 01:36:45 PM PDT 24
Peak memory 213392 kb
Host smart-28cee5fd-c3f5-4d30-a765-20d8bb7b47ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124632463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.124632463
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3909306195
Short name T423
Test name
Test status
Simulation time 171624913 ps
CPU time 8.45 seconds
Started May 28 01:35:19 PM PDT 24
Finished May 28 01:35:30 PM PDT 24
Peak memory 213508 kb
Host smart-1f379173-23eb-4366-b1c6-36807f1fd07b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909306195 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3909306195
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3673146831
Short name T439
Test name
Test status
Simulation time 319895048 ps
CPU time 8.28 seconds
Started May 28 01:35:15 PM PDT 24
Finished May 28 01:35:25 PM PDT 24
Peak memory 211280 kb
Host smart-12c5406b-be58-4bf3-9021-c40865493c83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673146831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3673146831
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3111370228
Short name T75
Test name
Test status
Simulation time 64461490370 ps
CPU time 132.53 seconds
Started May 28 01:35:17 PM PDT 24
Finished May 28 01:37:33 PM PDT 24
Peak memory 219560 kb
Host smart-663cd964-2a30-4360-9a0c-538198a58bac
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111370228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3111370228
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2194627530
Short name T394
Test name
Test status
Simulation time 2855334736 ps
CPU time 27.8 seconds
Started May 28 01:35:17 PM PDT 24
Finished May 28 01:35:49 PM PDT 24
Peak memory 212436 kb
Host smart-eba1aee7-1ce0-4975-8d72-973bad593bfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194627530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2194627530
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2383762576
Short name T441
Test name
Test status
Simulation time 18992238534 ps
CPU time 37.38 seconds
Started May 28 01:35:16 PM PDT 24
Finished May 28 01:35:57 PM PDT 24
Peak memory 219648 kb
Host smart-b134ea60-b1e8-48cc-bf3f-638314f875c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383762576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2383762576
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2328130217
Short name T366
Test name
Test status
Simulation time 7014731751 ps
CPU time 28.29 seconds
Started May 28 01:35:17 PM PDT 24
Finished May 28 01:35:49 PM PDT 24
Peak memory 216092 kb
Host smart-551670fc-7630-4903-8529-681d36ddb572
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328130217 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2328130217
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4002776215
Short name T389
Test name
Test status
Simulation time 5742816321 ps
CPU time 25.36 seconds
Started May 28 01:35:24 PM PDT 24
Finished May 28 01:35:50 PM PDT 24
Peak memory 212272 kb
Host smart-556b1727-db85-4453-9207-225d420d34cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002776215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.4002776215
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.564957976
Short name T94
Test name
Test status
Simulation time 67779774033 ps
CPU time 176.02 seconds
Started May 28 01:35:18 PM PDT 24
Finished May 28 01:38:17 PM PDT 24
Peak memory 215432 kb
Host smart-a1279bab-7f7a-4308-b5ab-21c030f0a8ae
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564957976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.564957976
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.270895350
Short name T426
Test name
Test status
Simulation time 1934598019 ps
CPU time 20.08 seconds
Started May 28 01:35:15 PM PDT 24
Finished May 28 01:35:38 PM PDT 24
Peak memory 212152 kb
Host smart-f59eee60-64e3-459e-899d-d058cf13fb67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270895350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.270895350
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3106434474
Short name T374
Test name
Test status
Simulation time 174545858 ps
CPU time 11.12 seconds
Started May 28 01:35:17 PM PDT 24
Finished May 28 01:35:31 PM PDT 24
Peak memory 217432 kb
Host smart-f4dc8a4e-0cad-4c88-ad4e-824a3c2233f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106434474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3106434474
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2411436615
Short name T110
Test name
Test status
Simulation time 1642912182 ps
CPU time 90.06 seconds
Started May 28 01:35:17 PM PDT 24
Finished May 28 01:36:51 PM PDT 24
Peak memory 213732 kb
Host smart-4684d6ea-c674-402f-8d41-305b96c25d3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411436615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2411436615
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.169182192
Short name T86
Test name
Test status
Simulation time 5787928778 ps
CPU time 24.67 seconds
Started May 28 01:34:17 PM PDT 24
Finished May 28 01:34:44 PM PDT 24
Peak memory 211876 kb
Host smart-73b76530-40ec-414a-b01f-765ed8a4a4b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169182192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.169182192
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1528886208
Short name T358
Test name
Test status
Simulation time 258421082 ps
CPU time 10.6 seconds
Started May 28 01:34:16 PM PDT 24
Finished May 28 01:34:29 PM PDT 24
Peak memory 211212 kb
Host smart-29ee98b7-5599-47e4-8e97-3bd7e9201305
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528886208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1528886208
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.967460894
Short name T82
Test name
Test status
Simulation time 34319804863 ps
CPU time 38.78 seconds
Started May 28 01:34:17 PM PDT 24
Finished May 28 01:34:58 PM PDT 24
Peak memory 212196 kb
Host smart-89ece2f1-53df-46f4-9a62-221a65c3ba11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967460894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.967460894
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.808957392
Short name T421
Test name
Test status
Simulation time 3873488632 ps
CPU time 12.16 seconds
Started May 28 01:34:18 PM PDT 24
Finished May 28 01:34:32 PM PDT 24
Peak memory 216188 kb
Host smart-7c008532-2702-4cc9-b9a8-9139b2e5ad05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808957392 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.808957392
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2562870408
Short name T402
Test name
Test status
Simulation time 167656636 ps
CPU time 8.39 seconds
Started May 28 01:34:16 PM PDT 24
Finished May 28 01:34:27 PM PDT 24
Peak memory 211300 kb
Host smart-c4a197a6-9b8c-44bf-bcb8-a0aee3cd38f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562870408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2562870408
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1628463119
Short name T444
Test name
Test status
Simulation time 6845758865 ps
CPU time 27.39 seconds
Started May 28 01:34:19 PM PDT 24
Finished May 28 01:34:48 PM PDT 24
Peak memory 211208 kb
Host smart-179fa7cc-ca11-4e60-b4ae-639d4efc9647
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628463119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1628463119
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4125516607
Short name T440
Test name
Test status
Simulation time 10635820644 ps
CPU time 21.11 seconds
Started May 28 01:34:16 PM PDT 24
Finished May 28 01:34:39 PM PDT 24
Peak memory 211200 kb
Host smart-522665cb-11a0-4cc2-9daf-cf045cb79572
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125516607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.4125516607
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1840684715
Short name T432
Test name
Test status
Simulation time 34186969220 ps
CPU time 135.52 seconds
Started May 28 01:34:05 PM PDT 24
Finished May 28 01:36:22 PM PDT 24
Peak memory 214384 kb
Host smart-30c0d850-cc89-4b74-a62e-33228c8731ba
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840684715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1840684715
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1161500261
Short name T425
Test name
Test status
Simulation time 3233412591 ps
CPU time 15.13 seconds
Started May 28 01:34:16 PM PDT 24
Finished May 28 01:34:32 PM PDT 24
Peak memory 212624 kb
Host smart-aa2c4b3e-a1e4-4b14-967e-e9f61afceb61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161500261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1161500261
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.69792649
Short name T69
Test name
Test status
Simulation time 689615636 ps
CPU time 13.16 seconds
Started May 28 01:34:19 PM PDT 24
Finished May 28 01:34:33 PM PDT 24
Peak memory 217636 kb
Host smart-1e3bf1ed-81f1-4dc3-a16f-c91d7243dd36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69792649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.69792649
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1732312580
Short name T416
Test name
Test status
Simulation time 345751158 ps
CPU time 8.35 seconds
Started May 28 01:34:17 PM PDT 24
Finished May 28 01:34:27 PM PDT 24
Peak memory 211248 kb
Host smart-a06ace2b-0ecd-403c-a621-39d41dcdd07d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732312580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1732312580
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.794920639
Short name T377
Test name
Test status
Simulation time 174566332 ps
CPU time 8.56 seconds
Started May 28 01:34:15 PM PDT 24
Finished May 28 01:34:25 PM PDT 24
Peak memory 211216 kb
Host smart-8d021e8f-fe35-49e2-b65d-692551c5f165
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794920639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.794920639
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1504065465
Short name T77
Test name
Test status
Simulation time 336016572 ps
CPU time 11.76 seconds
Started May 28 01:34:16 PM PDT 24
Finished May 28 01:34:30 PM PDT 24
Peak memory 212036 kb
Host smart-1d56e08c-e1e0-457b-b6f3-c077c0eeff01
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504065465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1504065465
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.431762224
Short name T360
Test name
Test status
Simulation time 4447243802 ps
CPU time 32.83 seconds
Started May 28 01:34:16 PM PDT 24
Finished May 28 01:34:50 PM PDT 24
Peak memory 214992 kb
Host smart-44f6f46d-e8ab-431c-8f11-b8209a83c032
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431762224 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.431762224
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1343510422
Short name T392
Test name
Test status
Simulation time 4786413782 ps
CPU time 21.6 seconds
Started May 28 01:34:17 PM PDT 24
Finished May 28 01:34:41 PM PDT 24
Peak memory 212104 kb
Host smart-4b1c859e-7ffd-437f-9bce-3598e65f1421
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343510422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1343510422
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.282218511
Short name T378
Test name
Test status
Simulation time 2093522540 ps
CPU time 15.22 seconds
Started May 28 01:34:17 PM PDT 24
Finished May 28 01:34:34 PM PDT 24
Peak memory 211160 kb
Host smart-38572cee-4a75-48dc-afbd-59439a93b79f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282218511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.282218511
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.614290140
Short name T359
Test name
Test status
Simulation time 3687308563 ps
CPU time 19.53 seconds
Started May 28 01:34:18 PM PDT 24
Finished May 28 01:34:39 PM PDT 24
Peak memory 211272 kb
Host smart-9f93cec8-3f13-4d0d-ae0e-81c7d9e420db
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614290140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
614290140
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.689298838
Short name T433
Test name
Test status
Simulation time 3116787543 ps
CPU time 58.27 seconds
Started May 28 01:34:16 PM PDT 24
Finished May 28 01:35:16 PM PDT 24
Peak memory 213436 kb
Host smart-da0b366a-9600-48a9-8f06-48518d38af2c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689298838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.689298838
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3191630693
Short name T98
Test name
Test status
Simulation time 31972722394 ps
CPU time 26.47 seconds
Started May 28 01:34:16 PM PDT 24
Finished May 28 01:34:43 PM PDT 24
Peak memory 212312 kb
Host smart-d1b0b4b5-f843-4788-84bf-c99eda940baa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191630693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3191630693
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2153180013
Short name T46
Test name
Test status
Simulation time 7517000504 ps
CPU time 32.77 seconds
Started May 28 01:34:16 PM PDT 24
Finished May 28 01:34:52 PM PDT 24
Peak memory 217644 kb
Host smart-fdfabb64-d173-47e5-87d0-bd0131b00cc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153180013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2153180013
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3395268194
Short name T442
Test name
Test status
Simulation time 2634595204 ps
CPU time 85.14 seconds
Started May 28 01:34:15 PM PDT 24
Finished May 28 01:35:42 PM PDT 24
Peak memory 213688 kb
Host smart-52348827-b730-48ad-aca2-13cbee8ecee2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395268194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3395268194
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.825250321
Short name T430
Test name
Test status
Simulation time 13221544748 ps
CPU time 26.86 seconds
Started May 28 01:34:32 PM PDT 24
Finished May 28 01:35:01 PM PDT 24
Peak memory 212080 kb
Host smart-c91bfe99-99bf-4eb5-b895-8da2cdcf8774
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825250321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.825250321
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3039492899
Short name T362
Test name
Test status
Simulation time 1312936997 ps
CPU time 16.13 seconds
Started May 28 01:34:31 PM PDT 24
Finished May 28 01:34:50 PM PDT 24
Peak memory 211260 kb
Host smart-de86a366-d1b1-40a1-a580-7049ecec3c0f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039492899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3039492899
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2025606947
Short name T91
Test name
Test status
Simulation time 7054973554 ps
CPU time 37.45 seconds
Started May 28 01:34:30 PM PDT 24
Finished May 28 01:35:10 PM PDT 24
Peak memory 212116 kb
Host smart-2f22abe9-08f1-4f12-b8cd-feba5cbed021
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025606947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2025606947
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1227509529
Short name T385
Test name
Test status
Simulation time 444369030 ps
CPU time 11.85 seconds
Started May 28 01:34:31 PM PDT 24
Finished May 28 01:34:45 PM PDT 24
Peak memory 215892 kb
Host smart-274503d0-4736-4ddb-8db7-1c8f34807f33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227509529 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1227509529
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.67236782
Short name T429
Test name
Test status
Simulation time 167545980 ps
CPU time 8.23 seconds
Started May 28 01:34:30 PM PDT 24
Finished May 28 01:34:41 PM PDT 24
Peak memory 211312 kb
Host smart-c395a31a-c0d0-4573-9133-b5518adff2f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67236782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.67236782
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2156196207
Short name T372
Test name
Test status
Simulation time 3145843684 ps
CPU time 25.26 seconds
Started May 28 01:34:30 PM PDT 24
Finished May 28 01:34:58 PM PDT 24
Peak memory 211244 kb
Host smart-270b7245-19a2-494f-b19e-abf14b188f26
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156196207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2156196207
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3242463814
Short name T419
Test name
Test status
Simulation time 8546036682 ps
CPU time 21.09 seconds
Started May 28 01:34:32 PM PDT 24
Finished May 28 01:34:55 PM PDT 24
Peak memory 211304 kb
Host smart-0ec8c25e-63ea-43b2-99bb-cc9965f708ce
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242463814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3242463814
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1275725154
Short name T428
Test name
Test status
Simulation time 31689704410 ps
CPU time 103.33 seconds
Started May 28 01:34:31 PM PDT 24
Finished May 28 01:36:17 PM PDT 24
Peak memory 215564 kb
Host smart-f7eee5ab-6492-4e5f-8097-0d0129436366
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275725154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1275725154
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1196108628
Short name T409
Test name
Test status
Simulation time 2835232099 ps
CPU time 16.89 seconds
Started May 28 01:34:30 PM PDT 24
Finished May 28 01:34:50 PM PDT 24
Peak memory 219540 kb
Host smart-10795568-3034-46f9-bbbd-33dc99850f0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196108628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1196108628
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2717101384
Short name T395
Test name
Test status
Simulation time 4039645883 ps
CPU time 26.84 seconds
Started May 28 01:34:31 PM PDT 24
Finished May 28 01:35:00 PM PDT 24
Peak memory 218444 kb
Host smart-f497aa9b-0ab2-459e-8b72-b949f4232178
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717101384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2717101384
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2073956906
Short name T445
Test name
Test status
Simulation time 22077846360 ps
CPU time 98.28 seconds
Started May 28 01:34:31 PM PDT 24
Finished May 28 01:36:12 PM PDT 24
Peak memory 219484 kb
Host smart-377ba421-ed4e-4e11-b521-705475d98c79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073956906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2073956906
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.436256448
Short name T415
Test name
Test status
Simulation time 1890914169 ps
CPU time 20.4 seconds
Started May 28 01:34:30 PM PDT 24
Finished May 28 01:34:53 PM PDT 24
Peak memory 216340 kb
Host smart-2b29fff2-3262-4530-ad25-f9424084f972
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436256448 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.436256448
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.4018090472
Short name T397
Test name
Test status
Simulation time 4546114872 ps
CPU time 22.18 seconds
Started May 28 01:34:30 PM PDT 24
Finished May 28 01:34:55 PM PDT 24
Peak memory 211896 kb
Host smart-7af7d5fc-ef7c-426e-a2a3-bf65e8cadb51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018090472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.4018090472
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3127998004
Short name T102
Test name
Test status
Simulation time 1326826904 ps
CPU time 57.78 seconds
Started May 28 01:34:30 PM PDT 24
Finished May 28 01:35:30 PM PDT 24
Peak memory 214376 kb
Host smart-9deeb622-f420-4786-911b-6e8238593a29
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127998004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3127998004
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2603540522
Short name T99
Test name
Test status
Simulation time 5140259659 ps
CPU time 23.38 seconds
Started May 28 01:34:29 PM PDT 24
Finished May 28 01:34:53 PM PDT 24
Peak memory 212560 kb
Host smart-4bda19f6-e9c9-47f7-8bea-648bb0252c69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603540522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2603540522
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3049659367
Short name T373
Test name
Test status
Simulation time 9394125371 ps
CPU time 32.34 seconds
Started May 28 01:34:29 PM PDT 24
Finished May 28 01:35:04 PM PDT 24
Peak memory 217604 kb
Host smart-a6143a50-3e39-412c-ab08-26de3977d50b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049659367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3049659367
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4180831167
Short name T114
Test name
Test status
Simulation time 1012092852 ps
CPU time 87.76 seconds
Started May 28 01:34:29 PM PDT 24
Finished May 28 01:35:59 PM PDT 24
Peak memory 213620 kb
Host smart-3e3bb9f5-19d3-4e98-94b6-3d25b829a5bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180831167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.4180831167
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2123705892
Short name T406
Test name
Test status
Simulation time 4485624794 ps
CPU time 17.12 seconds
Started May 28 01:34:44 PM PDT 24
Finished May 28 01:35:03 PM PDT 24
Peak memory 217436 kb
Host smart-7a1d47df-ca1c-4d8c-be8e-b44da877f8ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123705892 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2123705892
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.652756187
Short name T71
Test name
Test status
Simulation time 171113448 ps
CPU time 8.18 seconds
Started May 28 01:34:43 PM PDT 24
Finished May 28 01:34:52 PM PDT 24
Peak memory 211292 kb
Host smart-312fb294-d60f-428e-9174-55c8abf52ce6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652756187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.652756187
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1483646402
Short name T70
Test name
Test status
Simulation time 21850966212 ps
CPU time 92.8 seconds
Started May 28 01:34:32 PM PDT 24
Finished May 28 01:36:07 PM PDT 24
Peak memory 215628 kb
Host smart-491884a2-55b9-4004-96f4-29336b5028f6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483646402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1483646402
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2564507764
Short name T97
Test name
Test status
Simulation time 331904036 ps
CPU time 8.54 seconds
Started May 28 01:34:44 PM PDT 24
Finished May 28 01:34:54 PM PDT 24
Peak memory 211308 kb
Host smart-47452155-9ae2-4104-8d55-974f30f8c626
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564507764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2564507764
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.4121300060
Short name T386
Test name
Test status
Simulation time 4597397997 ps
CPU time 27.44 seconds
Started May 28 01:34:45 PM PDT 24
Finished May 28 01:35:14 PM PDT 24
Peak memory 218980 kb
Host smart-1a651682-5b92-486b-83b3-f3b6401d345c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121300060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.4121300060
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1232252930
Short name T431
Test name
Test status
Simulation time 34821400821 ps
CPU time 28.67 seconds
Started May 28 01:34:45 PM PDT 24
Finished May 28 01:35:15 PM PDT 24
Peak memory 219648 kb
Host smart-6698fdcf-d997-41d0-acba-497096d7b2f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232252930 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1232252930
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3965478458
Short name T447
Test name
Test status
Simulation time 17779745038 ps
CPU time 32.21 seconds
Started May 28 01:34:46 PM PDT 24
Finished May 28 01:35:20 PM PDT 24
Peak memory 212060 kb
Host smart-59f8eef9-cc81-4c76-85c6-1352e02d9c59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965478458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3965478458
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.390969651
Short name T92
Test name
Test status
Simulation time 5060837952 ps
CPU time 89.42 seconds
Started May 28 01:34:47 PM PDT 24
Finished May 28 01:36:17 PM PDT 24
Peak memory 215472 kb
Host smart-d4be1ad6-d9f9-4db9-a8bb-63ec45dc47cb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390969651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.390969651
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.546122525
Short name T411
Test name
Test status
Simulation time 5208118291 ps
CPU time 25.01 seconds
Started May 28 01:34:44 PM PDT 24
Finished May 28 01:35:11 PM PDT 24
Peak memory 212808 kb
Host smart-6f39763e-300b-431f-8367-bb296e02eb11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546122525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.546122525
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3880644391
Short name T388
Test name
Test status
Simulation time 3616197934 ps
CPU time 24.35 seconds
Started May 28 01:34:44 PM PDT 24
Finished May 28 01:35:10 PM PDT 24
Peak memory 218604 kb
Host smart-af02c402-ef36-47f1-9247-3a6bde686732
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880644391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3880644391
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2922731620
Short name T436
Test name
Test status
Simulation time 39750833351 ps
CPU time 102.06 seconds
Started May 28 01:34:45 PM PDT 24
Finished May 28 01:36:29 PM PDT 24
Peak memory 213800 kb
Host smart-9fb008ba-d8bb-47a2-9775-267b8cb85cdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922731620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2922731620
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2894067564
Short name T384
Test name
Test status
Simulation time 635399369 ps
CPU time 8.6 seconds
Started May 28 01:34:43 PM PDT 24
Finished May 28 01:34:53 PM PDT 24
Peak memory 214576 kb
Host smart-c535a5f1-13c6-4e9b-bc46-d744f219766e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894067564 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2894067564
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1541478757
Short name T76
Test name
Test status
Simulation time 4109023886 ps
CPU time 31.97 seconds
Started May 28 01:34:44 PM PDT 24
Finished May 28 01:35:17 PM PDT 24
Peak memory 211956 kb
Host smart-e0623603-4520-417a-a5e1-8be07a20dfd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541478757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1541478757
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1120458413
Short name T396
Test name
Test status
Simulation time 3014520420 ps
CPU time 57.55 seconds
Started May 28 01:34:45 PM PDT 24
Finished May 28 01:35:44 PM PDT 24
Peak memory 213812 kb
Host smart-9a88c868-3498-48f4-bf5e-3518d8bb135a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120458413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1120458413
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2679531298
Short name T73
Test name
Test status
Simulation time 3711360279 ps
CPU time 19.49 seconds
Started May 28 01:34:46 PM PDT 24
Finished May 28 01:35:07 PM PDT 24
Peak memory 212492 kb
Host smart-9eb276e0-0561-4bb2-ba27-bba3dcdd6104
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679531298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2679531298
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.189904165
Short name T364
Test name
Test status
Simulation time 4129434740 ps
CPU time 34.96 seconds
Started May 28 01:34:45 PM PDT 24
Finished May 28 01:35:22 PM PDT 24
Peak memory 217432 kb
Host smart-99b20c10-4915-448f-b371-e0ca4382ca7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189904165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.189904165
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3976714926
Short name T108
Test name
Test status
Simulation time 13411784179 ps
CPU time 97.38 seconds
Started May 28 01:34:44 PM PDT 24
Finished May 28 01:36:23 PM PDT 24
Peak memory 213624 kb
Host smart-97d1f486-3662-480e-8acd-0900c566d284
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976714926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3976714926
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3531046100
Short name T367
Test name
Test status
Simulation time 184077341 ps
CPU time 9.1 seconds
Started May 28 01:35:00 PM PDT 24
Finished May 28 01:35:10 PM PDT 24
Peak memory 216616 kb
Host smart-8ae976fe-8469-458a-b094-d1cfd00a2ae2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531046100 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3531046100
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3489484373
Short name T72
Test name
Test status
Simulation time 169386928 ps
CPU time 8.3 seconds
Started May 28 01:34:46 PM PDT 24
Finished May 28 01:34:56 PM PDT 24
Peak memory 211284 kb
Host smart-1802944c-8eff-4839-8b8c-70e58717f8cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489484373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3489484373
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2900824515
Short name T403
Test name
Test status
Simulation time 4311717060 ps
CPU time 56.94 seconds
Started May 28 01:34:44 PM PDT 24
Finished May 28 01:35:42 PM PDT 24
Peak memory 215328 kb
Host smart-3b463b75-7f91-47b0-ac83-4f2413a83a87
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900824515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2900824515
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1011483792
Short name T417
Test name
Test status
Simulation time 3905043289 ps
CPU time 30.69 seconds
Started May 28 01:34:44 PM PDT 24
Finished May 28 01:35:17 PM PDT 24
Peak memory 212068 kb
Host smart-f4d3421c-5cb9-47eb-95ff-78fcebc18b56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011483792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1011483792
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3877022380
Short name T381
Test name
Test status
Simulation time 17192731038 ps
CPU time 31.9 seconds
Started May 28 01:34:45 PM PDT 24
Finished May 28 01:35:18 PM PDT 24
Peak memory 218444 kb
Host smart-9e8f570a-a6c5-4a74-8ac5-af73c4e29d1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877022380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3877022380
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2968369055
Short name T169
Test name
Test status
Simulation time 5279096361 ps
CPU time 23.67 seconds
Started May 28 01:44:37 PM PDT 24
Finished May 28 01:45:03 PM PDT 24
Peak memory 211268 kb
Host smart-9ab01532-b784-42ef-8825-b84bafb6b6b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968369055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2968369055
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.984313954
Short name T262
Test name
Test status
Simulation time 288966293261 ps
CPU time 476.16 seconds
Started May 28 01:44:42 PM PDT 24
Finished May 28 01:52:39 PM PDT 24
Peak memory 237652 kb
Host smart-d75feca3-1429-494e-8c13-5d985bc0b2b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984313954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.984313954
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3691223865
Short name T206
Test name
Test status
Simulation time 9585339337 ps
CPU time 23.92 seconds
Started May 28 01:44:35 PM PDT 24
Finished May 28 01:45:00 PM PDT 24
Peak memory 212788 kb
Host smart-cde013ec-38d6-417f-a40f-437303231d45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3691223865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3691223865
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3442142878
Short name T33
Test name
Test status
Simulation time 15933338017 ps
CPU time 249.96 seconds
Started May 28 01:44:39 PM PDT 24
Finished May 28 01:48:51 PM PDT 24
Peak memory 238192 kb
Host smart-6d5cfa51-7619-4396-a08f-15eff9d23460
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442142878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3442142878
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1783483896
Short name T282
Test name
Test status
Simulation time 33076795483 ps
CPU time 50.18 seconds
Started May 28 01:44:35 PM PDT 24
Finished May 28 01:45:27 PM PDT 24
Peak memory 217492 kb
Host smart-eaf1c4cc-45f3-4e32-b203-dca5e69f293f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783483896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1783483896
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.4139870046
Short name T103
Test name
Test status
Simulation time 373890269 ps
CPU time 24.92 seconds
Started May 28 01:44:28 PM PDT 24
Finished May 28 01:44:53 PM PDT 24
Peak memory 217932 kb
Host smart-670fccfd-7e00-4825-8acd-3b321143a1b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139870046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.4139870046
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.175625098
Short name T268
Test name
Test status
Simulation time 9728503599 ps
CPU time 22.22 seconds
Started May 28 01:44:37 PM PDT 24
Finished May 28 01:45:02 PM PDT 24
Peak memory 212228 kb
Host smart-1d34d2c1-06fc-4239-875f-0e24954652be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175625098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.175625098
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1175639516
Short name T208
Test name
Test status
Simulation time 113049714798 ps
CPU time 268.49 seconds
Started May 28 01:44:37 PM PDT 24
Finished May 28 01:49:08 PM PDT 24
Peak memory 224436 kb
Host smart-70e6bf24-1a1c-42d9-9c03-d0bdab85e501
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175639516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1175639516
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2867682653
Short name T249
Test name
Test status
Simulation time 33954268175 ps
CPU time 70.25 seconds
Started May 28 01:44:36 PM PDT 24
Finished May 28 01:45:48 PM PDT 24
Peak memory 214888 kb
Host smart-e4271dee-94e6-49c5-a7e9-ba51bd866ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867682653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2867682653
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1230371820
Short name T336
Test name
Test status
Simulation time 14859931756 ps
CPU time 32.61 seconds
Started May 28 01:44:37 PM PDT 24
Finished May 28 01:45:12 PM PDT 24
Peak memory 212700 kb
Host smart-a158ff41-d951-4f06-a1b8-3f1be7cbc7b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1230371820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1230371820
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.109443440
Short name T291
Test name
Test status
Simulation time 4447718975 ps
CPU time 51.95 seconds
Started May 28 01:44:38 PM PDT 24
Finished May 28 01:45:32 PM PDT 24
Peak memory 217092 kb
Host smart-54cf1dc8-809b-42d7-b828-5413f102e59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109443440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.109443440
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1217704578
Short name T122
Test name
Test status
Simulation time 4733867865 ps
CPU time 78.09 seconds
Started May 28 01:44:36 PM PDT 24
Finished May 28 01:45:56 PM PDT 24
Peak memory 219236 kb
Host smart-4dddee92-bd8e-47dd-aa81-27d64e76c04d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217704578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1217704578
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.205345261
Short name T185
Test name
Test status
Simulation time 579980534 ps
CPU time 12.38 seconds
Started May 28 01:44:52 PM PDT 24
Finished May 28 01:45:06 PM PDT 24
Peak memory 211248 kb
Host smart-aeb6a05b-8372-4f98-8d62-5aeaaf6485c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205345261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.205345261
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3534332108
Short name T56
Test name
Test status
Simulation time 5917207052 ps
CPU time 27.51 seconds
Started May 28 01:44:47 PM PDT 24
Finished May 28 01:45:16 PM PDT 24
Peak memory 212484 kb
Host smart-0f9fba06-88c8-4c8b-993e-44918c5f9f34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3534332108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3534332108
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1298689347
Short name T311
Test name
Test status
Simulation time 677282201 ps
CPU time 24.8 seconds
Started May 28 01:44:48 PM PDT 24
Finished May 28 01:45:14 PM PDT 24
Peak memory 216896 kb
Host smart-9734bf43-d50f-4e7c-88a1-b8dff37a3fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298689347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1298689347
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1796005747
Short name T283
Test name
Test status
Simulation time 5940373851 ps
CPU time 22.92 seconds
Started May 28 01:44:47 PM PDT 24
Finished May 28 01:45:10 PM PDT 24
Peak memory 212040 kb
Host smart-1126a90a-4a40-4c77-9d52-9793a94e9d75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796005747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1796005747
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1178985336
Short name T253
Test name
Test status
Simulation time 49402128664 ps
CPU time 451.21 seconds
Started May 28 01:44:48 PM PDT 24
Finished May 28 01:52:21 PM PDT 24
Peak memory 217352 kb
Host smart-1d71bda4-50a4-469c-a88f-1e6a80c8bb54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178985336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1178985336
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1604880825
Short name T20
Test name
Test status
Simulation time 6587638301 ps
CPU time 58.57 seconds
Started May 28 01:44:52 PM PDT 24
Finished May 28 01:45:52 PM PDT 24
Peak memory 214804 kb
Host smart-55dfb895-59db-468f-a2f8-9b98182d15d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604880825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1604880825
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1321023450
Short name T183
Test name
Test status
Simulation time 13828468821 ps
CPU time 16.24 seconds
Started May 28 01:44:47 PM PDT 24
Finished May 28 01:45:05 PM PDT 24
Peak memory 211712 kb
Host smart-e372e15a-1b33-4670-8989-5e51a489dea7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1321023450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1321023450
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1342209642
Short name T171
Test name
Test status
Simulation time 2959936859 ps
CPU time 36.93 seconds
Started May 28 01:44:52 PM PDT 24
Finished May 28 01:45:30 PM PDT 24
Peak memory 215776 kb
Host smart-2d1273e7-ea91-43fb-8f1c-54c406db090f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342209642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1342209642
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.403501554
Short name T25
Test name
Test status
Simulation time 222905254 ps
CPU time 11.9 seconds
Started May 28 01:44:52 PM PDT 24
Finished May 28 01:45:06 PM PDT 24
Peak memory 212416 kb
Host smart-1529e0a8-2239-4f04-88fd-27f3c3a71a6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403501554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.403501554
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3162356304
Short name T168
Test name
Test status
Simulation time 4323562378 ps
CPU time 31.96 seconds
Started May 28 01:46:16 PM PDT 24
Finished May 28 01:47:09 PM PDT 24
Peak memory 211304 kb
Host smart-4af50bc2-2af4-49c5-bd58-d7f154bbe8e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162356304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3162356304
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3063198299
Short name T312
Test name
Test status
Simulation time 86637406377 ps
CPU time 386.81 seconds
Started May 28 01:46:18 PM PDT 24
Finished May 28 01:53:06 PM PDT 24
Peak memory 240228 kb
Host smart-55031a36-c2c4-45d8-9ca1-2b95f03eb15c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063198299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3063198299
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1645237810
Short name T129
Test name
Test status
Simulation time 11634221021 ps
CPU time 36.51 seconds
Started May 28 01:46:16 PM PDT 24
Finished May 28 01:47:13 PM PDT 24
Peak memory 214948 kb
Host smart-d90aebc2-776a-4592-858c-f575a60e787e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645237810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1645237810
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1495090077
Short name T136
Test name
Test status
Simulation time 1425886000 ps
CPU time 14.82 seconds
Started May 28 01:46:02 PM PDT 24
Finished May 28 01:46:23 PM PDT 24
Peak memory 211284 kb
Host smart-365e2c95-da1d-4209-a4be-5759d9ddbff2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1495090077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1495090077
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1219256305
Short name T123
Test name
Test status
Simulation time 1765523904 ps
CPU time 29.43 seconds
Started May 28 01:44:46 PM PDT 24
Finished May 28 01:45:17 PM PDT 24
Peak memory 216308 kb
Host smart-1cfe2b0b-c690-4323-bd9b-14ba8497c415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219256305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1219256305
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1190227698
Short name T55
Test name
Test status
Simulation time 4560660553 ps
CPU time 65.94 seconds
Started May 28 01:46:18 PM PDT 24
Finished May 28 01:47:45 PM PDT 24
Peak memory 216876 kb
Host smart-840242ec-9e02-4001-88b5-36ff32af03d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190227698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1190227698
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3765182442
Short name T197
Test name
Test status
Simulation time 9472162003 ps
CPU time 23.52 seconds
Started May 28 01:45:41 PM PDT 24
Finished May 28 01:46:05 PM PDT 24
Peak memory 211272 kb
Host smart-0b1d4f8d-5451-496c-aef3-3ba8c8a5c133
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765182442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3765182442
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.756420669
Short name T321
Test name
Test status
Simulation time 110948732928 ps
CPU time 62.17 seconds
Started May 28 01:46:09 PM PDT 24
Finished May 28 01:47:30 PM PDT 24
Peak memory 214900 kb
Host smart-dc27c32b-ad09-40b5-8984-5310adf67f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756420669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.756420669
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.317942013
Short name T173
Test name
Test status
Simulation time 1905589341 ps
CPU time 16.67 seconds
Started May 28 01:46:09 PM PDT 24
Finished May 28 01:46:44 PM PDT 24
Peak memory 212288 kb
Host smart-c6345689-c3e1-4fb4-ba37-3bbd9936a0a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=317942013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.317942013
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3024759996
Short name T264
Test name
Test status
Simulation time 719794559 ps
CPU time 20.1 seconds
Started May 28 01:46:03 PM PDT 24
Finished May 28 01:46:30 PM PDT 24
Peak memory 216636 kb
Host smart-68bd60e9-7be4-475d-b2c5-7c76f6d2f855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024759996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3024759996
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.4101611866
Short name T6
Test name
Test status
Simulation time 1800015909 ps
CPU time 54.49 seconds
Started May 28 01:46:10 PM PDT 24
Finished May 28 01:47:23 PM PDT 24
Peak memory 219172 kb
Host smart-fac6c834-7cac-4db1-b9d6-4eaac7a9872d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101611866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.4101611866
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2797619570
Short name T267
Test name
Test status
Simulation time 174573090 ps
CPU time 8.44 seconds
Started May 28 01:45:16 PM PDT 24
Finished May 28 01:45:25 PM PDT 24
Peak memory 211248 kb
Host smart-94176109-cf1f-4bda-8652-e5ef316337f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797619570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2797619570
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.450104
Short name T297
Test name
Test status
Simulation time 7972181753 ps
CPU time 52.03 seconds
Started May 28 01:45:17 PM PDT 24
Finished May 28 01:46:11 PM PDT 24
Peak memory 214832 kb
Host smart-3cd1c76b-4682-47d8-acc3-fb34e4850a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.450104
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3663882123
Short name T324
Test name
Test status
Simulation time 5999274079 ps
CPU time 19.06 seconds
Started May 28 01:45:18 PM PDT 24
Finished May 28 01:45:39 PM PDT 24
Peak memory 212660 kb
Host smart-a6abb34c-769a-492f-abac-e5ade4758da0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3663882123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3663882123
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1117576589
Short name T269
Test name
Test status
Simulation time 7709918044 ps
CPU time 51.86 seconds
Started May 28 01:46:04 PM PDT 24
Finished May 28 01:47:06 PM PDT 24
Peak memory 217476 kb
Host smart-e7589d0c-7fd9-4f8d-b39d-7d1fcd34fd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117576589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1117576589
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.51726061
Short name T327
Test name
Test status
Simulation time 20562486724 ps
CPU time 190.11 seconds
Started May 28 01:46:11 PM PDT 24
Finished May 28 01:49:39 PM PDT 24
Peak memory 219852 kb
Host smart-eb025d38-9857-4c00-9df1-238110cf826c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51726061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 14.rom_ctrl_stress_all.51726061
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.154648354
Short name T66
Test name
Test status
Simulation time 10790851535 ps
CPU time 25.12 seconds
Started May 28 01:45:19 PM PDT 24
Finished May 28 01:45:47 PM PDT 24
Peak memory 212124 kb
Host smart-9b1e8dbe-935e-4797-9777-a48cc1cd7989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154648354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.154648354
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3094811774
Short name T349
Test name
Test status
Simulation time 98027159939 ps
CPU time 215.37 seconds
Started May 28 01:45:15 PM PDT 24
Finished May 28 01:48:52 PM PDT 24
Peak memory 236172 kb
Host smart-ffd8fb45-9a1f-4e90-869e-1e1a758e6d2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094811774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3094811774
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1107483076
Short name T141
Test name
Test status
Simulation time 4205931896 ps
CPU time 35.38 seconds
Started May 28 01:45:18 PM PDT 24
Finished May 28 01:45:56 PM PDT 24
Peak memory 211308 kb
Host smart-9a1153eb-af2c-4667-b4b7-7179f69807fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1107483076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1107483076
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1609647003
Short name T338
Test name
Test status
Simulation time 6484750454 ps
CPU time 66.48 seconds
Started May 28 01:45:16 PM PDT 24
Finished May 28 01:46:24 PM PDT 24
Peak memory 217424 kb
Host smart-460e20f1-5e21-429e-93a7-a38282662dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609647003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1609647003
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3369214476
Short name T250
Test name
Test status
Simulation time 1769093082 ps
CPU time 12.2 seconds
Started May 28 01:45:18 PM PDT 24
Finished May 28 01:45:33 PM PDT 24
Peak memory 211220 kb
Host smart-d85b9a16-42e6-46bc-8b04-5e0fc5729c5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369214476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3369214476
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3554271156
Short name T303
Test name
Test status
Simulation time 32816806488 ps
CPU time 188.21 seconds
Started May 28 01:45:17 PM PDT 24
Finished May 28 01:48:28 PM PDT 24
Peak memory 234324 kb
Host smart-0bd6242a-158c-4734-be58-b6b35de599a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554271156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3554271156
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2944319842
Short name T288
Test name
Test status
Simulation time 16405073253 ps
CPU time 45.22 seconds
Started May 28 01:45:19 PM PDT 24
Finished May 28 01:46:07 PM PDT 24
Peak memory 214896 kb
Host smart-e57bb20d-257b-4c51-b1d7-e26301062f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944319842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2944319842
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.38471910
Short name T36
Test name
Test status
Simulation time 8881276978 ps
CPU time 23.3 seconds
Started May 28 01:45:18 PM PDT 24
Finished May 28 01:45:44 PM PDT 24
Peak memory 211724 kb
Host smart-0b979f9e-2020-4a5d-bafc-2b480c974858
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=38471910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.38471910
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2002860562
Short name T150
Test name
Test status
Simulation time 520623899 ps
CPU time 23.94 seconds
Started May 28 01:45:18 PM PDT 24
Finished May 28 01:45:45 PM PDT 24
Peak memory 216632 kb
Host smart-ee944dc0-7b6f-440e-843a-f48f87bc9146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002860562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2002860562
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3174472439
Short name T207
Test name
Test status
Simulation time 3197408488 ps
CPU time 31.35 seconds
Started May 28 01:45:17 PM PDT 24
Finished May 28 01:45:50 PM PDT 24
Peak memory 212204 kb
Host smart-02f4bd0a-770f-4db9-885f-a3671aabe234
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174472439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3174472439
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3033923479
Short name T229
Test name
Test status
Simulation time 13083855216 ps
CPU time 24.53 seconds
Started May 28 01:45:22 PM PDT 24
Finished May 28 01:45:49 PM PDT 24
Peak memory 212124 kb
Host smart-4f47197a-297e-4e36-85ee-d6ba9aec1343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033923479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3033923479
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3241407949
Short name T316
Test name
Test status
Simulation time 41884734889 ps
CPU time 433.75 seconds
Started May 28 01:45:19 PM PDT 24
Finished May 28 01:52:35 PM PDT 24
Peak memory 232548 kb
Host smart-74578c21-b9f1-4d49-bfd3-8d65ac963463
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241407949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3241407949
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2065442161
Short name T247
Test name
Test status
Simulation time 10017616826 ps
CPU time 49.63 seconds
Started May 28 01:45:21 PM PDT 24
Finished May 28 01:46:14 PM PDT 24
Peak memory 213124 kb
Host smart-282c18d2-e7b5-4e49-b994-d4f8ee296f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065442161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2065442161
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.816380751
Short name T343
Test name
Test status
Simulation time 4127637398 ps
CPU time 33.99 seconds
Started May 28 01:45:21 PM PDT 24
Finished May 28 01:45:58 PM PDT 24
Peak memory 211456 kb
Host smart-756af358-12a0-4e4c-a3a8-7948b6575dbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=816380751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.816380751
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.474229898
Short name T356
Test name
Test status
Simulation time 3353710154 ps
CPU time 33.35 seconds
Started May 28 01:45:21 PM PDT 24
Finished May 28 01:45:57 PM PDT 24
Peak memory 214604 kb
Host smart-cb64d44d-a6b3-4205-8d37-b71d7bb18087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474229898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.474229898
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1264435171
Short name T242
Test name
Test status
Simulation time 9964547539 ps
CPU time 73.39 seconds
Started May 28 01:45:18 PM PDT 24
Finished May 28 01:46:34 PM PDT 24
Peak memory 218080 kb
Host smart-3e56aab5-a4da-4863-aaa8-b5fb91d6b556
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264435171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1264435171
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1280126048
Short name T294
Test name
Test status
Simulation time 508620888 ps
CPU time 10.14 seconds
Started May 28 01:45:22 PM PDT 24
Finished May 28 01:45:34 PM PDT 24
Peak memory 211244 kb
Host smart-a226602d-28d2-45a3-a711-0b57fdd294ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280126048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1280126048
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2494251646
Short name T227
Test name
Test status
Simulation time 32656378553 ps
CPU time 440.7 seconds
Started May 28 01:45:22 PM PDT 24
Finished May 28 01:52:45 PM PDT 24
Peak memory 217280 kb
Host smart-c98b1007-0882-4de1-925d-10c6e6f223f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494251646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2494251646
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1301608190
Short name T209
Test name
Test status
Simulation time 23068709620 ps
CPU time 27.55 seconds
Started May 28 01:45:22 PM PDT 24
Finished May 28 01:45:52 PM PDT 24
Peak memory 214868 kb
Host smart-ee490364-d6a0-428a-8b16-c3f9597ee35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301608190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1301608190
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.658845730
Short name T310
Test name
Test status
Simulation time 22460987450 ps
CPU time 26.4 seconds
Started May 28 01:45:18 PM PDT 24
Finished May 28 01:45:47 PM PDT 24
Peak memory 211232 kb
Host smart-093d479a-d226-47ce-bfff-3778f3fbb634
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=658845730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.658845730
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.667219133
Short name T176
Test name
Test status
Simulation time 22990039131 ps
CPU time 53.93 seconds
Started May 28 01:45:19 PM PDT 24
Finished May 28 01:46:16 PM PDT 24
Peak memory 217884 kb
Host smart-56e0f041-8d07-4ef9-bdd5-29df889716ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667219133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.667219133
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2742573069
Short name T148
Test name
Test status
Simulation time 17972488324 ps
CPU time 69.84 seconds
Started May 28 01:45:21 PM PDT 24
Finished May 28 01:46:34 PM PDT 24
Peak memory 220888 kb
Host smart-56dcd03d-fd01-4e51-95d4-029106ec56a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742573069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2742573069
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3131932018
Short name T179
Test name
Test status
Simulation time 150198052978 ps
CPU time 385.7 seconds
Started May 28 01:45:22 PM PDT 24
Finished May 28 01:51:50 PM PDT 24
Peak memory 237640 kb
Host smart-88e30fe7-be9b-4f50-bb9f-50e3ef3ce01c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131932018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3131932018
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1848110191
Short name T254
Test name
Test status
Simulation time 18786189913 ps
CPU time 50.3 seconds
Started May 28 01:45:21 PM PDT 24
Finished May 28 01:46:15 PM PDT 24
Peak memory 214408 kb
Host smart-e6c9eac9-98e0-46f1-a88f-a16a91117a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848110191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1848110191
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.493129837
Short name T234
Test name
Test status
Simulation time 703909532 ps
CPU time 10.69 seconds
Started May 28 01:45:20 PM PDT 24
Finished May 28 01:45:33 PM PDT 24
Peak memory 212324 kb
Host smart-574a1655-5b61-4fef-bf16-3de4867897f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=493129837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.493129837
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1053073304
Short name T285
Test name
Test status
Simulation time 16125908462 ps
CPU time 90.61 seconds
Started May 28 01:45:22 PM PDT 24
Finished May 28 01:46:55 PM PDT 24
Peak memory 217528 kb
Host smart-6f75f122-f953-4e09-b5b6-2ca7c30713cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053073304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1053073304
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3960747645
Short name T319
Test name
Test status
Simulation time 755978966 ps
CPU time 46.65 seconds
Started May 28 01:45:21 PM PDT 24
Finished May 28 01:46:10 PM PDT 24
Peak memory 219176 kb
Host smart-bcd0a5bb-6b80-462e-8ff8-ef8ed7757f0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960747645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3960747645
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1675286582
Short name T322
Test name
Test status
Simulation time 7475567286 ps
CPU time 14.55 seconds
Started May 28 01:44:36 PM PDT 24
Finished May 28 01:44:53 PM PDT 24
Peak memory 211224 kb
Host smart-e1352704-95ed-4b49-9b10-96bedd765ab5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675286582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1675286582
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1477675712
Short name T223
Test name
Test status
Simulation time 4652877693 ps
CPU time 323.56 seconds
Started May 28 01:44:41 PM PDT 24
Finished May 28 01:50:06 PM PDT 24
Peak memory 225136 kb
Host smart-318cf88e-a843-4971-9949-14b96b44898a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477675712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1477675712
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1712988740
Short name T13
Test name
Test status
Simulation time 1434784318 ps
CPU time 19.5 seconds
Started May 28 01:44:35 PM PDT 24
Finished May 28 01:44:55 PM PDT 24
Peak memory 214568 kb
Host smart-4bfcce5f-da1d-4e46-a584-6d7ff3925295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712988740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1712988740
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3182472906
Short name T134
Test name
Test status
Simulation time 16213429533 ps
CPU time 34.76 seconds
Started May 28 01:44:38 PM PDT 24
Finished May 28 01:45:15 PM PDT 24
Peak memory 211380 kb
Host smart-8f8804d1-6b67-41ce-83ac-344befddef42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3182472906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3182472906
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3099167110
Short name T34
Test name
Test status
Simulation time 987347349 ps
CPU time 117.24 seconds
Started May 28 01:44:39 PM PDT 24
Finished May 28 01:46:38 PM PDT 24
Peak memory 238128 kb
Host smart-13d3289b-7d5d-4e27-9112-8d7749875c8e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099167110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3099167110
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.797459538
Short name T216
Test name
Test status
Simulation time 5230812177 ps
CPU time 51.16 seconds
Started May 28 01:44:36 PM PDT 24
Finished May 28 01:45:30 PM PDT 24
Peak memory 217820 kb
Host smart-f6fc757c-71d2-41e7-a7e9-e9dfc17443b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797459538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.797459538
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.15662742
Short name T118
Test name
Test status
Simulation time 732334879 ps
CPU time 45.75 seconds
Started May 28 01:44:39 PM PDT 24
Finished May 28 01:45:26 PM PDT 24
Peak memory 219168 kb
Host smart-909da443-f837-42e6-8507-a59a5afb262b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15662742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.rom_ctrl_stress_all.15662742
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3143470564
Short name T280
Test name
Test status
Simulation time 4871771492 ps
CPU time 24.28 seconds
Started May 28 01:45:23 PM PDT 24
Finished May 28 01:45:49 PM PDT 24
Peak memory 212092 kb
Host smart-f659ca22-600d-405d-aa10-05140a17786d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143470564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3143470564
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2840995080
Short name T261
Test name
Test status
Simulation time 25478770211 ps
CPU time 58.96 seconds
Started May 28 01:45:21 PM PDT 24
Finished May 28 01:46:23 PM PDT 24
Peak memory 214864 kb
Host smart-8a53c447-d132-45ab-9ec7-8ef1096250a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840995080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2840995080
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3496882874
Short name T133
Test name
Test status
Simulation time 13535421211 ps
CPU time 31.62 seconds
Started May 28 01:45:23 PM PDT 24
Finished May 28 01:45:57 PM PDT 24
Peak memory 211192 kb
Host smart-fbefee72-38d4-4d1a-8061-a118fffe5f4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3496882874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3496882874
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3094055740
Short name T115
Test name
Test status
Simulation time 21036800102 ps
CPU time 52.89 seconds
Started May 28 01:45:25 PM PDT 24
Finished May 28 01:46:19 PM PDT 24
Peak memory 218540 kb
Host smart-6c129d14-a12d-47e3-a6bc-751308c66a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094055740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3094055740
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3203022886
Short name T199
Test name
Test status
Simulation time 375404023 ps
CPU time 24.45 seconds
Started May 28 01:45:23 PM PDT 24
Finished May 28 01:45:49 PM PDT 24
Peak memory 218340 kb
Host smart-d4e2db01-5ba1-4e0d-a037-26e8de6cf5c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203022886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3203022886
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3189355286
Short name T144
Test name
Test status
Simulation time 7256476154 ps
CPU time 19.29 seconds
Started May 28 01:45:17 PM PDT 24
Finished May 28 01:45:39 PM PDT 24
Peak memory 211504 kb
Host smart-d38b081e-059a-4e21-a2fe-62a3cf53e595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189355286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3189355286
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2843600264
Short name T248
Test name
Test status
Simulation time 60326072772 ps
CPU time 611.44 seconds
Started May 28 01:45:18 PM PDT 24
Finished May 28 01:55:32 PM PDT 24
Peak memory 224560 kb
Host smart-e6e4cd7a-de49-451c-898c-a3a506bb7402
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843600264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2843600264
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.917299568
Short name T295
Test name
Test status
Simulation time 10907551169 ps
CPU time 51.09 seconds
Started May 28 01:45:18 PM PDT 24
Finished May 28 01:46:11 PM PDT 24
Peak memory 214980 kb
Host smart-c539b523-c5df-4cc2-bb16-a11f36fff156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917299568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.917299568
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2219221010
Short name T192
Test name
Test status
Simulation time 720834914 ps
CPU time 10.35 seconds
Started May 28 01:45:21 PM PDT 24
Finished May 28 01:45:35 PM PDT 24
Peak memory 211156 kb
Host smart-06a3e45e-b928-43e1-8dbe-63290d3245ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2219221010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2219221010
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3538160251
Short name T9
Test name
Test status
Simulation time 1378406487 ps
CPU time 19.57 seconds
Started May 28 01:45:21 PM PDT 24
Finished May 28 01:45:43 PM PDT 24
Peak memory 216512 kb
Host smart-c0098696-e4c3-4d27-977a-7eac7e6a3996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538160251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3538160251
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.145662688
Short name T130
Test name
Test status
Simulation time 2104021167 ps
CPU time 37.29 seconds
Started May 28 01:45:21 PM PDT 24
Finished May 28 01:46:01 PM PDT 24
Peak memory 215896 kb
Host smart-aec2ee30-d6a8-45a6-9b3f-010948c08e21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145662688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.145662688
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1232954365
Short name T323
Test name
Test status
Simulation time 360188248 ps
CPU time 8.41 seconds
Started May 28 01:45:19 PM PDT 24
Finished May 28 01:45:29 PM PDT 24
Peak memory 211304 kb
Host smart-438487e9-2b01-4b06-a552-cb7a570439b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232954365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1232954365
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4265262823
Short name T177
Test name
Test status
Simulation time 282305281244 ps
CPU time 591.55 seconds
Started May 28 01:45:17 PM PDT 24
Finished May 28 01:55:11 PM PDT 24
Peak memory 215856 kb
Host smart-6bfefeb6-6285-4077-8399-624a2e637df4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265262823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.4265262823
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3180470904
Short name T195
Test name
Test status
Simulation time 8182068257 ps
CPU time 67.52 seconds
Started May 28 01:45:17 PM PDT 24
Finished May 28 01:46:26 PM PDT 24
Peak memory 213920 kb
Host smart-bd06c249-d491-4e3e-bef3-fbaa9734c9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180470904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3180470904
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1002456608
Short name T231
Test name
Test status
Simulation time 3961317619 ps
CPU time 16.13 seconds
Started May 28 01:45:17 PM PDT 24
Finished May 28 01:45:35 PM PDT 24
Peak memory 211540 kb
Host smart-757979d5-77b0-40ca-bd2c-b109dc2d7c26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1002456608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1002456608
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.250405958
Short name T309
Test name
Test status
Simulation time 531952295 ps
CPU time 20.08 seconds
Started May 28 01:45:17 PM PDT 24
Finished May 28 01:45:39 PM PDT 24
Peak memory 216992 kb
Host smart-c9f1fbff-22ad-4fad-be88-7f994e7f7f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250405958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.250405958
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.693687316
Short name T65
Test name
Test status
Simulation time 10409829461 ps
CPU time 26.65 seconds
Started May 28 01:45:17 PM PDT 24
Finished May 28 01:45:46 PM PDT 24
Peak memory 212164 kb
Host smart-5ee53317-8108-4635-8574-49800414f5e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693687316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.693687316
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.870119228
Short name T355
Test name
Test status
Simulation time 20606495315 ps
CPU time 190.54 seconds
Started May 28 01:45:18 PM PDT 24
Finished May 28 01:48:31 PM PDT 24
Peak memory 237608 kb
Host smart-19824f1e-bd2e-4d24-9b6b-81e05cd77d1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870119228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.870119228
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3797393611
Short name T298
Test name
Test status
Simulation time 6163543065 ps
CPU time 53.54 seconds
Started May 28 01:45:17 PM PDT 24
Finished May 28 01:46:12 PM PDT 24
Peak memory 215012 kb
Host smart-d88d7de9-5e32-4c1f-b3d1-0b38883160e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797393611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3797393611
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1267424678
Short name T340
Test name
Test status
Simulation time 692563749 ps
CPU time 9.94 seconds
Started May 28 01:45:18 PM PDT 24
Finished May 28 01:45:30 PM PDT 24
Peak memory 212132 kb
Host smart-ca4158fa-6076-4e87-9601-f73418d597ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1267424678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1267424678
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2550879490
Short name T200
Test name
Test status
Simulation time 355789399 ps
CPU time 21.26 seconds
Started May 28 01:45:17 PM PDT 24
Finished May 28 01:45:41 PM PDT 24
Peak memory 216208 kb
Host smart-09e1dbe2-8866-4438-81d4-a0745dbce61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550879490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2550879490
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2725758449
Short name T159
Test name
Test status
Simulation time 25591881176 ps
CPU time 57.88 seconds
Started May 28 01:45:19 PM PDT 24
Finished May 28 01:46:20 PM PDT 24
Peak memory 218680 kb
Host smart-7ea56289-564d-452f-8885-4eb1c05e421a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725758449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2725758449
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.398490956
Short name T329
Test name
Test status
Simulation time 1452165652 ps
CPU time 17.47 seconds
Started May 28 01:45:22 PM PDT 24
Finished May 28 01:45:42 PM PDT 24
Peak memory 211788 kb
Host smart-1e062308-9320-411f-90c3-8fea31d69f61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398490956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.398490956
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3660253803
Short name T161
Test name
Test status
Simulation time 17979357230 ps
CPU time 248.38 seconds
Started May 28 01:45:21 PM PDT 24
Finished May 28 01:49:32 PM PDT 24
Peak memory 238708 kb
Host smart-03e67a07-216a-49f4-ad57-84e5050fe52b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660253803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3660253803
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.999874647
Short name T204
Test name
Test status
Simulation time 19756342940 ps
CPU time 49.23 seconds
Started May 28 01:45:21 PM PDT 24
Finished May 28 01:46:13 PM PDT 24
Peak memory 214924 kb
Host smart-c83ed164-cc8d-452f-8b43-cf0917cb389d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999874647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.999874647
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.981383917
Short name T308
Test name
Test status
Simulation time 8234926674 ps
CPU time 22.55 seconds
Started May 28 01:45:17 PM PDT 24
Finished May 28 01:45:43 PM PDT 24
Peak memory 211252 kb
Host smart-8a59cd1b-fb3c-42ae-a778-f603f56f8aa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=981383917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.981383917
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3703921889
Short name T279
Test name
Test status
Simulation time 17103563054 ps
CPU time 49.62 seconds
Started May 28 01:45:17 PM PDT 24
Finished May 28 01:46:09 PM PDT 24
Peak memory 216096 kb
Host smart-5c85671a-4a03-4ff9-aeae-0f1a28b39be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703921889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3703921889
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3556845137
Short name T53
Test name
Test status
Simulation time 29069604782 ps
CPU time 121.85 seconds
Started May 28 01:45:20 PM PDT 24
Finished May 28 01:47:24 PM PDT 24
Peak memory 219236 kb
Host smart-47d2f80e-d7a4-450c-9aa3-4c4b77db6737
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556845137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3556845137
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2068573898
Short name T233
Test name
Test status
Simulation time 174582415 ps
CPU time 8.45 seconds
Started May 28 01:45:23 PM PDT 24
Finished May 28 01:45:33 PM PDT 24
Peak memory 211480 kb
Host smart-9683f671-0f80-4991-ab1c-b3fea1829cb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068573898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2068573898
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.21586380
Short name T157
Test name
Test status
Simulation time 39451569383 ps
CPU time 404.73 seconds
Started May 28 01:45:20 PM PDT 24
Finished May 28 01:52:08 PM PDT 24
Peak memory 237564 kb
Host smart-f9fd84d2-dcad-4bf6-a725-407d6bf52eca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21586380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_co
rrupt_sig_fatal_chk.21586380
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1365421540
Short name T277
Test name
Test status
Simulation time 22867281217 ps
CPU time 54.87 seconds
Started May 28 01:45:18 PM PDT 24
Finished May 28 01:46:16 PM PDT 24
Peak memory 215064 kb
Host smart-9ddc6577-10f7-4656-a2a2-cc79a8973344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365421540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1365421540
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.4143467831
Short name T189
Test name
Test status
Simulation time 2912596551 ps
CPU time 27.24 seconds
Started May 28 01:45:21 PM PDT 24
Finished May 28 01:45:51 PM PDT 24
Peak memory 210604 kb
Host smart-c6eb3565-0b1d-44b9-bca7-a724589c24c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4143467831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.4143467831
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3363232522
Short name T190
Test name
Test status
Simulation time 18359372671 ps
CPU time 48.73 seconds
Started May 28 01:45:22 PM PDT 24
Finished May 28 01:46:13 PM PDT 24
Peak memory 217512 kb
Host smart-ad03ac01-41a8-4d13-abc8-fc6fecb23efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363232522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3363232522
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1451761788
Short name T232
Test name
Test status
Simulation time 11636143027 ps
CPU time 68.52 seconds
Started May 28 01:45:21 PM PDT 24
Finished May 28 01:46:32 PM PDT 24
Peak memory 218804 kb
Host smart-0905e318-816e-4cec-9220-5baaa1b7f341
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451761788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1451761788
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1698594772
Short name T237
Test name
Test status
Simulation time 13677083113 ps
CPU time 26.63 seconds
Started May 28 01:45:27 PM PDT 24
Finished May 28 01:45:54 PM PDT 24
Peak memory 211424 kb
Host smart-a9bdd388-ed64-42dd-87f3-c8a25290e8a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698594772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1698594772
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2424690082
Short name T42
Test name
Test status
Simulation time 11662507535 ps
CPU time 191.94 seconds
Started May 28 01:45:28 PM PDT 24
Finished May 28 01:48:41 PM PDT 24
Peak memory 224416 kb
Host smart-915dcd76-70d0-4115-b2a1-df77e1b2634b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424690082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2424690082
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.116068730
Short name T353
Test name
Test status
Simulation time 22362976891 ps
CPU time 54.06 seconds
Started May 28 01:45:33 PM PDT 24
Finished May 28 01:46:28 PM PDT 24
Peak memory 214564 kb
Host smart-03c9277c-c0a9-4e0c-a0bd-eb7b2f29c5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116068730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.116068730
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.182623338
Short name T315
Test name
Test status
Simulation time 184289253 ps
CPU time 10.44 seconds
Started May 28 01:45:27 PM PDT 24
Finished May 28 01:45:39 PM PDT 24
Peak memory 212472 kb
Host smart-c6a926a8-4165-4b32-8b3a-6d1be3fa7c2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=182623338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.182623338
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1898081329
Short name T273
Test name
Test status
Simulation time 6991282702 ps
CPU time 58.87 seconds
Started May 28 01:45:23 PM PDT 24
Finished May 28 01:46:24 PM PDT 24
Peak memory 216876 kb
Host smart-9571abba-2c53-4a49-a00f-bbf35008444b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898081329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1898081329
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.297030530
Short name T54
Test name
Test status
Simulation time 9980532513 ps
CPU time 73.86 seconds
Started May 28 01:45:27 PM PDT 24
Finished May 28 01:46:42 PM PDT 24
Peak memory 220656 kb
Host smart-f0dd3201-b7cd-4ce0-8c00-29980b8e3859
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297030530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.297030530
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.548918448
Short name T61
Test name
Test status
Simulation time 4365974204 ps
CPU time 22.37 seconds
Started May 28 01:45:36 PM PDT 24
Finished May 28 01:46:00 PM PDT 24
Peak memory 211196 kb
Host smart-7f4f11bf-75bd-4b55-9a1c-c79f1947cdeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548918448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.548918448
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1451875226
Short name T4
Test name
Test status
Simulation time 5130078212 ps
CPU time 183.35 seconds
Started May 28 01:45:30 PM PDT 24
Finished May 28 01:48:34 PM PDT 24
Peak memory 225672 kb
Host smart-0141616f-f8ee-48ea-afa4-7cfa8cd46140
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451875226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1451875226
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.67827356
Short name T230
Test name
Test status
Simulation time 16375678163 ps
CPU time 45.43 seconds
Started May 28 01:45:33 PM PDT 24
Finished May 28 01:46:20 PM PDT 24
Peak memory 213768 kb
Host smart-7d5402a9-a4e5-416b-b461-f703109cc91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67827356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.67827356
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4171324259
Short name T214
Test name
Test status
Simulation time 424856016 ps
CPU time 13.64 seconds
Started May 28 01:45:36 PM PDT 24
Finished May 28 01:45:51 PM PDT 24
Peak memory 211088 kb
Host smart-d88a261b-ea0d-41ad-a8bf-c08380432e91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4171324259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4171324259
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1018306171
Short name T142
Test name
Test status
Simulation time 363334733 ps
CPU time 20.77 seconds
Started May 28 01:45:36 PM PDT 24
Finished May 28 01:45:58 PM PDT 24
Peak memory 216680 kb
Host smart-84001f09-3cae-4f91-bcf0-4a5c6faff4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018306171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1018306171
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1347196208
Short name T226
Test name
Test status
Simulation time 39283865204 ps
CPU time 86.41 seconds
Started May 28 01:45:33 PM PDT 24
Finished May 28 01:47:00 PM PDT 24
Peak memory 218964 kb
Host smart-871f3c2d-23b6-4d47-908f-8dfa2a62c908
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347196208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1347196208
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.508447183
Short name T31
Test name
Test status
Simulation time 5941226539 ps
CPU time 16.89 seconds
Started May 28 01:45:33 PM PDT 24
Finished May 28 01:45:52 PM PDT 24
Peak memory 211300 kb
Host smart-7500efd4-2516-41f8-afab-43a4d715c211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508447183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.508447183
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3474679247
Short name T165
Test name
Test status
Simulation time 35193938383 ps
CPU time 442.11 seconds
Started May 28 01:45:36 PM PDT 24
Finished May 28 01:53:00 PM PDT 24
Peak memory 240452 kb
Host smart-429d0f0d-ad44-4869-9202-879ce778aeba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474679247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3474679247
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.4217496240
Short name T225
Test name
Test status
Simulation time 19117204644 ps
CPU time 48.54 seconds
Started May 28 01:45:36 PM PDT 24
Finished May 28 01:46:26 PM PDT 24
Peak memory 214824 kb
Host smart-731596c3-8ef1-4681-8025-714891484108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217496240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.4217496240
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.51530154
Short name T217
Test name
Test status
Simulation time 11564940892 ps
CPU time 29.66 seconds
Started May 28 01:45:33 PM PDT 24
Finished May 28 01:46:04 PM PDT 24
Peak memory 211244 kb
Host smart-f32e19fe-b9c2-451f-8202-10a9e36675c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=51530154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.51530154
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.975934249
Short name T38
Test name
Test status
Simulation time 4913439493 ps
CPU time 47.3 seconds
Started May 28 01:45:30 PM PDT 24
Finished May 28 01:46:18 PM PDT 24
Peak memory 216544 kb
Host smart-8ddbd01e-6d6b-4ad0-8e9f-ee9f6535626d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975934249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.975934249
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.963266722
Short name T325
Test name
Test status
Simulation time 2364430971 ps
CPU time 48.48 seconds
Started May 28 01:45:27 PM PDT 24
Finished May 28 01:46:16 PM PDT 24
Peak memory 219044 kb
Host smart-fe0d5735-e4da-40ee-bfb2-6f1cf9da1cb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963266722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.963266722
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3658482054
Short name T180
Test name
Test status
Simulation time 48946855029 ps
CPU time 29.74 seconds
Started May 28 01:45:29 PM PDT 24
Finished May 28 01:46:00 PM PDT 24
Peak memory 211744 kb
Host smart-257ebe7a-0b0d-4df3-a3c5-78130e052251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658482054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3658482054
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3320535996
Short name T313
Test name
Test status
Simulation time 4941034652 ps
CPU time 216.32 seconds
Started May 28 01:45:33 PM PDT 24
Finished May 28 01:49:11 PM PDT 24
Peak memory 236684 kb
Host smart-09ceab99-76e7-4bf1-a6db-927750c77943
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320535996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3320535996
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2114690267
Short name T124
Test name
Test status
Simulation time 33029922049 ps
CPU time 59.9 seconds
Started May 28 01:45:32 PM PDT 24
Finished May 28 01:46:33 PM PDT 24
Peak memory 213852 kb
Host smart-af66990b-3e71-462f-b7a8-91e349808bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114690267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2114690267
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2951463079
Short name T205
Test name
Test status
Simulation time 3881213726 ps
CPU time 21.96 seconds
Started May 28 01:45:32 PM PDT 24
Finished May 28 01:45:55 PM PDT 24
Peak memory 211432 kb
Host smart-68f11ab9-b148-4a0a-9b01-acb2ea9a46cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2951463079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2951463079
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1662977651
Short name T257
Test name
Test status
Simulation time 8354037264 ps
CPU time 72.87 seconds
Started May 28 01:45:34 PM PDT 24
Finished May 28 01:46:48 PM PDT 24
Peak memory 217812 kb
Host smart-d9545d8c-4f5b-4b82-a436-d0437be32adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662977651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1662977651
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1725126412
Short name T196
Test name
Test status
Simulation time 11639452373 ps
CPU time 118.05 seconds
Started May 28 01:45:34 PM PDT 24
Finished May 28 01:47:33 PM PDT 24
Peak memory 218468 kb
Host smart-c2399d9b-16a0-4e13-94e3-529f79bc95ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725126412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1725126412
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.337760324
Short name T287
Test name
Test status
Simulation time 2604499087 ps
CPU time 23.85 seconds
Started May 28 01:44:37 PM PDT 24
Finished May 28 01:45:03 PM PDT 24
Peak memory 211768 kb
Host smart-a4ea4939-8034-4199-931c-b445ca20cce0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337760324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.337760324
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1772656142
Short name T17
Test name
Test status
Simulation time 34060306592 ps
CPU time 389.03 seconds
Started May 28 01:44:40 PM PDT 24
Finished May 28 01:51:10 PM PDT 24
Peak memory 229440 kb
Host smart-740daa4a-e351-4823-a8f1-54575e269c06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772656142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1772656142
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1619703921
Short name T342
Test name
Test status
Simulation time 6870489490 ps
CPU time 63.82 seconds
Started May 28 01:44:38 PM PDT 24
Finished May 28 01:45:44 PM PDT 24
Peak memory 214792 kb
Host smart-4f051b50-eb0c-4e12-bde4-59c9a3447f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619703921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1619703921
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2473011598
Short name T198
Test name
Test status
Simulation time 1833838211 ps
CPU time 16.94 seconds
Started May 28 01:44:36 PM PDT 24
Finished May 28 01:44:55 PM PDT 24
Peak memory 211380 kb
Host smart-d92fd18e-0a57-4812-8897-547aefd34073
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2473011598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2473011598
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3967061449
Short name T29
Test name
Test status
Simulation time 3552535786 ps
CPU time 235.7 seconds
Started May 28 01:44:39 PM PDT 24
Finished May 28 01:48:36 PM PDT 24
Peak memory 238808 kb
Host smart-9d055fa1-2f91-4a30-83ba-6214b861b63b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967061449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3967061449
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.4035056439
Short name T39
Test name
Test status
Simulation time 5775211348 ps
CPU time 29.4 seconds
Started May 28 01:44:36 PM PDT 24
Finished May 28 01:45:08 PM PDT 24
Peak memory 217520 kb
Host smart-1d74a53f-70b6-4783-8306-aa60a2e2181c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035056439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.4035056439
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1398631143
Short name T201
Test name
Test status
Simulation time 11100740782 ps
CPU time 34.52 seconds
Started May 28 01:44:38 PM PDT 24
Finished May 28 01:45:14 PM PDT 24
Peak memory 213732 kb
Host smart-7f0b4daa-d2c6-46bf-80f7-7756bb1e6841
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398631143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1398631143
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2800517830
Short name T193
Test name
Test status
Simulation time 68525448473 ps
CPU time 32.83 seconds
Started May 28 01:45:35 PM PDT 24
Finished May 28 01:46:09 PM PDT 24
Peak memory 212088 kb
Host smart-f17d01e8-94f4-4e3d-885b-5b4b46e732eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800517830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2800517830
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3225787214
Short name T174
Test name
Test status
Simulation time 74663265336 ps
CPU time 363.12 seconds
Started May 28 01:45:29 PM PDT 24
Finished May 28 01:51:33 PM PDT 24
Peak memory 224824 kb
Host smart-59aabffe-8b2f-4b35-ba59-6e0a87d65728
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225787214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3225787214
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2509375666
Short name T160
Test name
Test status
Simulation time 4116612000 ps
CPU time 45.4 seconds
Started May 28 01:45:34 PM PDT 24
Finished May 28 01:46:21 PM PDT 24
Peak memory 214524 kb
Host smart-9b44e702-605a-4419-8bcd-531c15039df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509375666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2509375666
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3705522027
Short name T333
Test name
Test status
Simulation time 263104612 ps
CPU time 10.38 seconds
Started May 28 01:45:34 PM PDT 24
Finished May 28 01:45:45 PM PDT 24
Peak memory 212516 kb
Host smart-e8c2b8b4-95de-4dc7-825b-8a12e84f5d98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3705522027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3705522027
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3221492348
Short name T222
Test name
Test status
Simulation time 8394396245 ps
CPU time 69.64 seconds
Started May 28 01:45:33 PM PDT 24
Finished May 28 01:46:44 PM PDT 24
Peak memory 216684 kb
Host smart-0e149801-07dd-440c-85f3-2f7a6a572226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221492348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3221492348
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2945898120
Short name T224
Test name
Test status
Simulation time 277503925 ps
CPU time 8.45 seconds
Started May 28 01:45:40 PM PDT 24
Finished May 28 01:45:50 PM PDT 24
Peak memory 211240 kb
Host smart-6ea7e643-5a99-4c47-a952-9490c9763f23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945898120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2945898120
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1037803045
Short name T188
Test name
Test status
Simulation time 240988308418 ps
CPU time 413.93 seconds
Started May 28 01:45:41 PM PDT 24
Finished May 28 01:52:36 PM PDT 24
Peak memory 215796 kb
Host smart-b1e2883c-9b5d-4f88-9edf-23f89b3365e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037803045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1037803045
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.4056366252
Short name T228
Test name
Test status
Simulation time 37439082353 ps
CPU time 67.6 seconds
Started May 28 01:45:39 PM PDT 24
Finished May 28 01:46:49 PM PDT 24
Peak memory 214880 kb
Host smart-6dc3c282-b2e5-4a85-936a-cdeee925267b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056366252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.4056366252
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2830199699
Short name T151
Test name
Test status
Simulation time 14312074400 ps
CPU time 34.06 seconds
Started May 28 01:45:35 PM PDT 24
Finished May 28 01:46:10 PM PDT 24
Peak memory 212744 kb
Host smart-b353b7d4-c9e8-4677-a782-a12459164684
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2830199699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2830199699
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1848101161
Short name T332
Test name
Test status
Simulation time 20775029682 ps
CPU time 49.36 seconds
Started May 28 01:45:36 PM PDT 24
Finished May 28 01:46:26 PM PDT 24
Peak memory 217212 kb
Host smart-f01be257-56a7-4d3e-a449-365e659eda30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848101161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1848101161
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1103990487
Short name T348
Test name
Test status
Simulation time 4246104500 ps
CPU time 51.58 seconds
Started May 28 01:45:36 PM PDT 24
Finished May 28 01:46:29 PM PDT 24
Peak memory 215184 kb
Host smart-4d39827c-fc6b-459c-8b58-5c2db8e4b0e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103990487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1103990487
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3162341298
Short name T235
Test name
Test status
Simulation time 8468492618 ps
CPU time 23.15 seconds
Started May 28 01:45:39 PM PDT 24
Finished May 28 01:46:04 PM PDT 24
Peak memory 212056 kb
Host smart-beb140db-5288-4d00-a6a7-9e9ac3d95fcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162341298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3162341298
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2466336781
Short name T119
Test name
Test status
Simulation time 17983557136 ps
CPU time 240.51 seconds
Started May 28 01:45:38 PM PDT 24
Finished May 28 01:49:40 PM PDT 24
Peak memory 233596 kb
Host smart-29f327ae-86af-4677-9dfc-a4ab9c3f4ec7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466336781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2466336781
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1595694208
Short name T184
Test name
Test status
Simulation time 22107702458 ps
CPU time 54.44 seconds
Started May 28 01:45:38 PM PDT 24
Finished May 28 01:46:34 PM PDT 24
Peak memory 214916 kb
Host smart-e53437af-2d4d-4adc-aec5-173cbd7d5087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595694208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1595694208
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2753684253
Short name T221
Test name
Test status
Simulation time 178329925 ps
CPU time 10.43 seconds
Started May 28 01:45:38 PM PDT 24
Finished May 28 01:45:51 PM PDT 24
Peak memory 212196 kb
Host smart-619ba704-80c0-4fcd-a125-e144eca690ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2753684253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2753684253
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.696105118
Short name T345
Test name
Test status
Simulation time 1432290197 ps
CPU time 20.61 seconds
Started May 28 01:45:43 PM PDT 24
Finished May 28 01:46:05 PM PDT 24
Peak memory 217488 kb
Host smart-e6bb2ecf-87cc-43ef-bee6-f11f6076c4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696105118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.696105118
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3224822239
Short name T191
Test name
Test status
Simulation time 11083259703 ps
CPU time 94.97 seconds
Started May 28 01:45:39 PM PDT 24
Finished May 28 01:47:15 PM PDT 24
Peak memory 219924 kb
Host smart-a33d8f28-08bb-460a-badc-6591e7a98775
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224822239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3224822239
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1707093581
Short name T152
Test name
Test status
Simulation time 11287336803 ps
CPU time 26.68 seconds
Started May 28 01:45:52 PM PDT 24
Finished May 28 01:46:21 PM PDT 24
Peak memory 212132 kb
Host smart-d89e5e91-2bf2-4c0d-95d8-9c9e02043d87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707093581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1707093581
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4142644841
Short name T16
Test name
Test status
Simulation time 34079426071 ps
CPU time 508.32 seconds
Started May 28 01:45:39 PM PDT 24
Finished May 28 01:54:09 PM PDT 24
Peak memory 216588 kb
Host smart-a45d58f9-c5ac-4884-ab5a-cfa138a91db7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142644841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.4142644841
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.4150861448
Short name T347
Test name
Test status
Simulation time 6189644199 ps
CPU time 54.67 seconds
Started May 28 01:45:42 PM PDT 24
Finished May 28 01:46:37 PM PDT 24
Peak memory 214944 kb
Host smart-f982fca2-964a-4e0e-a21c-c9b2905cf04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150861448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.4150861448
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.786247693
Short name T132
Test name
Test status
Simulation time 2967749126 ps
CPU time 19.44 seconds
Started May 28 01:45:41 PM PDT 24
Finished May 28 01:46:01 PM PDT 24
Peak memory 212216 kb
Host smart-68daf3f4-c007-448c-b04e-35d091d46502
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=786247693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.786247693
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3335394416
Short name T117
Test name
Test status
Simulation time 13676849843 ps
CPU time 55.54 seconds
Started May 28 01:45:39 PM PDT 24
Finished May 28 01:46:36 PM PDT 24
Peak memory 216624 kb
Host smart-19fe673f-9e6d-4deb-ae79-889e9a4d4382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335394416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3335394416
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3006534608
Short name T8
Test name
Test status
Simulation time 367015357 ps
CPU time 11.49 seconds
Started May 28 01:45:40 PM PDT 24
Finished May 28 01:45:53 PM PDT 24
Peak memory 213720 kb
Host smart-0739dd25-21d0-4405-93fa-736d8fee549e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006534608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3006534608
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4115225377
Short name T245
Test name
Test status
Simulation time 689323234 ps
CPU time 8.3 seconds
Started May 28 01:45:53 PM PDT 24
Finished May 28 01:46:04 PM PDT 24
Peak memory 211180 kb
Host smart-3d7bcd1c-b1da-4dfe-bba4-4f0dbbc039d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115225377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4115225377
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2605993816
Short name T244
Test name
Test status
Simulation time 60346206612 ps
CPU time 353.28 seconds
Started May 28 01:45:52 PM PDT 24
Finished May 28 01:51:48 PM PDT 24
Peak memory 237748 kb
Host smart-092a0855-00e5-4a33-8b0b-cc23bcc9d778
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605993816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2605993816
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.89343874
Short name T218
Test name
Test status
Simulation time 5597789203 ps
CPU time 53.82 seconds
Started May 28 01:45:52 PM PDT 24
Finished May 28 01:46:48 PM PDT 24
Peak memory 214860 kb
Host smart-92e2deb4-56ef-409c-8387-42b5cf643d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89343874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.89343874
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.4003377118
Short name T265
Test name
Test status
Simulation time 1158501445 ps
CPU time 18.2 seconds
Started May 28 01:45:54 PM PDT 24
Finished May 28 01:46:14 PM PDT 24
Peak memory 211108 kb
Host smart-3726d797-8368-4dd2-a925-021dd825d29d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4003377118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.4003377118
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.102445347
Short name T211
Test name
Test status
Simulation time 3046310453 ps
CPU time 40.34 seconds
Started May 28 01:45:54 PM PDT 24
Finished May 28 01:46:36 PM PDT 24
Peak memory 216844 kb
Host smart-e1246cbd-cea6-4426-bc3e-7ebc634d3784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102445347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.102445347
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.4119081137
Short name T186
Test name
Test status
Simulation time 31351943895 ps
CPU time 71.64 seconds
Started May 28 01:45:54 PM PDT 24
Finished May 28 01:47:08 PM PDT 24
Peak memory 215616 kb
Host smart-a1549ceb-6110-44f2-a01a-90523e05782d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119081137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.4119081137
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1782462711
Short name T43
Test name
Test status
Simulation time 84639029559 ps
CPU time 2748.6 seconds
Started May 28 01:45:52 PM PDT 24
Finished May 28 02:31:43 PM PDT 24
Peak memory 235680 kb
Host smart-fe0f23e9-006f-4243-a466-89824e81f3cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782462711 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.1782462711
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3595120641
Short name T62
Test name
Test status
Simulation time 3675072989 ps
CPU time 22.38 seconds
Started May 28 01:45:52 PM PDT 24
Finished May 28 01:46:17 PM PDT 24
Peak memory 211300 kb
Host smart-4b71cfb7-0b91-46dd-8ecf-d8956b1f4e26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595120641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3595120641
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1503058356
Short name T178
Test name
Test status
Simulation time 96108218037 ps
CPU time 323.68 seconds
Started May 28 01:45:53 PM PDT 24
Finished May 28 01:51:18 PM PDT 24
Peak memory 227448 kb
Host smart-6c116a26-2431-4f93-b494-a488c52b9141
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503058356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1503058356
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2230714534
Short name T251
Test name
Test status
Simulation time 3876912266 ps
CPU time 43.41 seconds
Started May 28 01:45:53 PM PDT 24
Finished May 28 01:46:39 PM PDT 24
Peak memory 214536 kb
Host smart-e1d69dcc-51d8-4322-a15b-1aa9f269e432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230714534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2230714534
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.875133953
Short name T236
Test name
Test status
Simulation time 4456975689 ps
CPU time 29.1 seconds
Started May 28 01:45:54 PM PDT 24
Finished May 28 01:46:26 PM PDT 24
Peak memory 211252 kb
Host smart-087943d8-515f-4f2c-810d-1478850d1254
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=875133953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.875133953
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1255723864
Short name T275
Test name
Test status
Simulation time 9235862572 ps
CPU time 46.63 seconds
Started May 28 01:45:53 PM PDT 24
Finished May 28 01:46:42 PM PDT 24
Peak memory 217044 kb
Host smart-1ee35e42-ee16-4b39-9d37-758a135c3f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255723864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1255723864
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3522194894
Short name T120
Test name
Test status
Simulation time 68570672956 ps
CPU time 156.8 seconds
Started May 28 01:45:53 PM PDT 24
Finished May 28 01:48:32 PM PDT 24
Peak memory 219244 kb
Host smart-d688a4a7-f16b-4706-aec1-5fcc744fcf97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522194894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3522194894
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.814039897
Short name T215
Test name
Test status
Simulation time 1648590851 ps
CPU time 18.78 seconds
Started May 28 01:45:55 PM PDT 24
Finished May 28 01:46:16 PM PDT 24
Peak memory 211244 kb
Host smart-72fd19e0-0bd9-41b6-88f5-7272749f49f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814039897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.814039897
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.4047432000
Short name T339
Test name
Test status
Simulation time 38282258793 ps
CPU time 422.99 seconds
Started May 28 01:45:55 PM PDT 24
Finished May 28 01:53:01 PM PDT 24
Peak memory 236700 kb
Host smart-702088a4-0d60-4b75-aa67-740ca50f2b09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047432000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.4047432000
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.64377701
Short name T246
Test name
Test status
Simulation time 7323529373 ps
CPU time 31.75 seconds
Started May 28 01:45:53 PM PDT 24
Finished May 28 01:46:27 PM PDT 24
Peak memory 211724 kb
Host smart-df02eca9-5ae1-4f1e-87d4-f7bcd5f36bc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64377701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.64377701
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1642405705
Short name T281
Test name
Test status
Simulation time 6162791051 ps
CPU time 51.76 seconds
Started May 28 01:45:53 PM PDT 24
Finished May 28 01:46:47 PM PDT 24
Peak memory 217304 kb
Host smart-0ef74fd5-6447-49d2-8e19-f9d104cb4013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642405705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1642405705
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3793372991
Short name T10
Test name
Test status
Simulation time 18747107817 ps
CPU time 69.66 seconds
Started May 28 01:45:54 PM PDT 24
Finished May 28 01:47:06 PM PDT 24
Peak memory 217136 kb
Host smart-88e1e55f-f343-4bd5-840b-72fb9ac32625
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793372991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3793372991
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1741085488
Short name T304
Test name
Test status
Simulation time 10851296330 ps
CPU time 24.67 seconds
Started May 28 01:45:58 PM PDT 24
Finished May 28 01:46:25 PM PDT 24
Peak memory 211280 kb
Host smart-92fd495b-b540-423d-8bd3-f9abdbae68ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741085488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1741085488
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.27442604
Short name T11
Test name
Test status
Simulation time 62773286900 ps
CPU time 571.26 seconds
Started May 28 01:45:56 PM PDT 24
Finished May 28 01:55:29 PM PDT 24
Peak memory 233984 kb
Host smart-40e47d2d-cb8e-48db-ba4c-71641d145ee5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27442604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_co
rrupt_sig_fatal_chk.27442604
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.974730071
Short name T131
Test name
Test status
Simulation time 53393631237 ps
CPU time 70.47 seconds
Started May 28 01:45:56 PM PDT 24
Finished May 28 01:47:08 PM PDT 24
Peak memory 213764 kb
Host smart-7930d51d-4fef-4488-9e4c-505ac4108d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974730071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.974730071
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2752224000
Short name T125
Test name
Test status
Simulation time 3076927866 ps
CPU time 28.11 seconds
Started May 28 01:45:57 PM PDT 24
Finished May 28 01:46:26 PM PDT 24
Peak memory 211260 kb
Host smart-39256f72-5f9d-4609-ade8-282c3b577141
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2752224000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2752224000
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.744247331
Short name T238
Test name
Test status
Simulation time 4135186161 ps
CPU time 45.03 seconds
Started May 28 01:45:59 PM PDT 24
Finished May 28 01:46:46 PM PDT 24
Peak memory 216716 kb
Host smart-8adec426-c26e-4dbc-9f94-00dbe63ef7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744247331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.744247331
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2321718211
Short name T351
Test name
Test status
Simulation time 1090438531 ps
CPU time 69.32 seconds
Started May 28 01:45:57 PM PDT 24
Finished May 28 01:47:08 PM PDT 24
Peak memory 220428 kb
Host smart-0169f71d-2b34-4584-8b41-4e6d1c62529e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321718211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2321718211
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2508451147
Short name T274
Test name
Test status
Simulation time 6672018788 ps
CPU time 26.69 seconds
Started May 28 01:46:00 PM PDT 24
Finished May 28 01:46:29 PM PDT 24
Peak memory 212148 kb
Host smart-c8b5ca16-9982-4ddb-b08c-50c15872da3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508451147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2508451147
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2815128698
Short name T350
Test name
Test status
Simulation time 163863568908 ps
CPU time 450.34 seconds
Started May 28 01:45:58 PM PDT 24
Finished May 28 01:53:31 PM PDT 24
Peak memory 228552 kb
Host smart-2852eba1-de48-45ec-b17a-cbfe517dbd81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815128698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2815128698
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3502840819
Short name T181
Test name
Test status
Simulation time 6877561459 ps
CPU time 38.98 seconds
Started May 28 01:45:56 PM PDT 24
Finished May 28 01:46:37 PM PDT 24
Peak memory 215100 kb
Host smart-070f60f8-2eb4-42bd-9f63-832feda3623e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502840819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3502840819
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.793848607
Short name T51
Test name
Test status
Simulation time 1396144019 ps
CPU time 18.8 seconds
Started May 28 01:45:56 PM PDT 24
Finished May 28 01:46:16 PM PDT 24
Peak memory 212052 kb
Host smart-85ddc2dd-ba27-41eb-b50f-89f55a8904dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=793848607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.793848607
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1012107790
Short name T170
Test name
Test status
Simulation time 23420591224 ps
CPU time 60.62 seconds
Started May 28 01:45:59 PM PDT 24
Finished May 28 01:47:01 PM PDT 24
Peak memory 217508 kb
Host smart-0b10e29e-8581-4f66-b042-4b3ff4980ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012107790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1012107790
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2044546866
Short name T255
Test name
Test status
Simulation time 2122175731 ps
CPU time 34.19 seconds
Started May 28 01:45:56 PM PDT 24
Finished May 28 01:46:32 PM PDT 24
Peak memory 215448 kb
Host smart-f1bb6d39-b9f3-4cd7-b2b9-8ea23583062d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044546866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2044546866
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.294635876
Short name T63
Test name
Test status
Simulation time 178008586 ps
CPU time 8.23 seconds
Started May 28 01:46:06 PM PDT 24
Finished May 28 01:46:28 PM PDT 24
Peak memory 211248 kb
Host smart-a643e054-f0d6-4c83-a488-065d8d6066a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294635876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.294635876
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1801171147
Short name T266
Test name
Test status
Simulation time 76236736013 ps
CPU time 280.57 seconds
Started May 28 01:46:14 PM PDT 24
Finished May 28 01:51:15 PM PDT 24
Peak memory 224996 kb
Host smart-078bfd41-803e-479b-9916-dae8b4cc1b68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801171147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1801171147
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.66925924
Short name T305
Test name
Test status
Simulation time 5699012676 ps
CPU time 52.04 seconds
Started May 28 01:46:09 PM PDT 24
Finished May 28 01:47:19 PM PDT 24
Peak memory 217596 kb
Host smart-0b3699e5-d43b-4798-b8d3-6b0adfb6126f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66925924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.66925924
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2057830707
Short name T212
Test name
Test status
Simulation time 3791744646 ps
CPU time 21.3 seconds
Started May 28 01:46:16 PM PDT 24
Finished May 28 01:46:59 PM PDT 24
Peak memory 212220 kb
Host smart-cd94c730-df26-476d-acdc-c6039732b28a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2057830707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2057830707
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.964787244
Short name T317
Test name
Test status
Simulation time 673345158 ps
CPU time 24.98 seconds
Started May 28 01:45:57 PM PDT 24
Finished May 28 01:46:23 PM PDT 24
Peak memory 216856 kb
Host smart-eb4b8335-8b53-4d27-b598-2bb9c6d31db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964787244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.964787244
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3345336757
Short name T50
Test name
Test status
Simulation time 11936269119 ps
CPU time 35.32 seconds
Started May 28 01:46:14 PM PDT 24
Finished May 28 01:47:10 PM PDT 24
Peak memory 212740 kb
Host smart-c76a09f1-7df0-4772-8162-4aa99e45a1f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345336757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3345336757
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.76643709
Short name T156
Test name
Test status
Simulation time 660313452 ps
CPU time 8.3 seconds
Started May 28 01:44:36 PM PDT 24
Finished May 28 01:44:46 PM PDT 24
Peak memory 211264 kb
Host smart-89e3df86-f480-46b1-a3c3-545863fe23bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76643709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.76643709
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3427668347
Short name T276
Test name
Test status
Simulation time 61326048733 ps
CPU time 681.85 seconds
Started May 28 01:44:36 PM PDT 24
Finished May 28 01:56:01 PM PDT 24
Peak memory 240540 kb
Host smart-440f6765-40f8-4b32-a1f5-870d32253ed0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427668347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3427668347
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3315125139
Short name T127
Test name
Test status
Simulation time 13595718123 ps
CPU time 40.08 seconds
Started May 28 01:44:36 PM PDT 24
Finished May 28 01:45:17 PM PDT 24
Peak memory 215272 kb
Host smart-e2028046-cd3a-4225-8670-9ae4a3aaa2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315125139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3315125139
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1661882605
Short name T330
Test name
Test status
Simulation time 5574223715 ps
CPU time 27.97 seconds
Started May 28 01:44:39 PM PDT 24
Finished May 28 01:45:09 PM PDT 24
Peak memory 211244 kb
Host smart-14e980dd-7393-48c4-aad5-7477a20df984
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1661882605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1661882605
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.41568143
Short name T30
Test name
Test status
Simulation time 17277198542 ps
CPU time 255.16 seconds
Started May 28 01:44:37 PM PDT 24
Finished May 28 01:48:54 PM PDT 24
Peak memory 238188 kb
Host smart-d1c9bc3f-3a4e-4306-9f3d-eff3bd606793
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41568143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.41568143
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2885734577
Short name T79
Test name
Test status
Simulation time 343530584 ps
CPU time 20.57 seconds
Started May 28 01:44:39 PM PDT 24
Finished May 28 01:45:01 PM PDT 24
Peak memory 216988 kb
Host smart-b8f819a3-7a94-4acd-9adb-4604d0535aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885734577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2885734577
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2128156264
Short name T80
Test name
Test status
Simulation time 14406060292 ps
CPU time 135.81 seconds
Started May 28 01:44:38 PM PDT 24
Finished May 28 01:46:56 PM PDT 24
Peak memory 220460 kb
Host smart-815cfaab-7112-49ea-9f22-80525faf87be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128156264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2128156264
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.202007604
Short name T64
Test name
Test status
Simulation time 3769934262 ps
CPU time 29.43 seconds
Started May 28 01:46:17 PM PDT 24
Finished May 28 01:47:08 PM PDT 24
Peak memory 211208 kb
Host smart-598e6bb0-1292-44f5-99ac-84f38df555d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202007604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.202007604
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3596518232
Short name T22
Test name
Test status
Simulation time 89492453713 ps
CPU time 837.21 seconds
Started May 28 01:46:17 PM PDT 24
Finished May 28 02:00:36 PM PDT 24
Peak memory 238792 kb
Host smart-661f387c-21f6-4dbc-aac3-fc2f1e973221
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596518232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3596518232
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3041742917
Short name T18
Test name
Test status
Simulation time 10857795407 ps
CPU time 62.93 seconds
Started May 28 01:46:16 PM PDT 24
Finished May 28 01:47:40 PM PDT 24
Peak memory 214868 kb
Host smart-0e9a06a2-5e01-4539-b8e7-dc430a34e04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041742917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3041742917
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2151247876
Short name T116
Test name
Test status
Simulation time 3981891637 ps
CPU time 33.58 seconds
Started May 28 01:46:14 PM PDT 24
Finished May 28 01:47:08 PM PDT 24
Peak memory 211248 kb
Host smart-94fc4c8a-7570-492c-98ec-1fb49f909e9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2151247876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2151247876
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3839585154
Short name T37
Test name
Test status
Simulation time 692028073 ps
CPU time 19.8 seconds
Started May 28 01:46:08 PM PDT 24
Finished May 28 01:46:46 PM PDT 24
Peak memory 217420 kb
Host smart-2f66869c-629a-48ce-9f72-fc38d5b5a831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839585154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3839585154
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2278435154
Short name T331
Test name
Test status
Simulation time 2014019167 ps
CPU time 66.77 seconds
Started May 28 01:46:06 PM PDT 24
Finished May 28 01:47:27 PM PDT 24
Peak memory 219176 kb
Host smart-ec0361d8-248c-4130-800f-8e786b1e0e1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278435154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2278435154
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.683657344
Short name T162
Test name
Test status
Simulation time 3423507015 ps
CPU time 18.36 seconds
Started May 28 01:46:09 PM PDT 24
Finished May 28 01:46:45 PM PDT 24
Peak memory 211316 kb
Host smart-b124f4e4-e6c0-4960-bb4f-35118972d074
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683657344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.683657344
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.371264190
Short name T334
Test name
Test status
Simulation time 121593907482 ps
CPU time 467.64 seconds
Started May 28 01:46:06 PM PDT 24
Finished May 28 01:54:08 PM PDT 24
Peak memory 224836 kb
Host smart-1d8d5665-cad3-4ed8-9cb5-4149885546dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371264190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.371264190
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.947568472
Short name T210
Test name
Test status
Simulation time 89866781475 ps
CPU time 65 seconds
Started May 28 01:46:16 PM PDT 24
Finished May 28 01:47:43 PM PDT 24
Peak memory 214728 kb
Host smart-431ccc5a-2d2d-4f03-8e3e-a808dc1c3993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947568472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.947568472
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3606025305
Short name T270
Test name
Test status
Simulation time 8644944243 ps
CPU time 22.02 seconds
Started May 28 01:46:18 PM PDT 24
Finished May 28 01:47:01 PM PDT 24
Peak memory 211656 kb
Host smart-e346c48a-0391-4eb2-a59d-f20f8cfcd129
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3606025305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3606025305
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2846681757
Short name T147
Test name
Test status
Simulation time 1433202856 ps
CPU time 20.45 seconds
Started May 28 01:46:14 PM PDT 24
Finished May 28 01:46:55 PM PDT 24
Peak memory 217720 kb
Host smart-59f336b7-db69-4d93-95a4-7aaa9a3ceb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846681757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2846681757
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.536782190
Short name T163
Test name
Test status
Simulation time 40052351396 ps
CPU time 81.04 seconds
Started May 28 01:46:06 PM PDT 24
Finished May 28 01:47:42 PM PDT 24
Peak memory 227352 kb
Host smart-8a350168-9b11-4132-9adb-dd53dcb34e14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536782190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.536782190
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2575132465
Short name T167
Test name
Test status
Simulation time 661937353 ps
CPU time 8.18 seconds
Started May 28 01:46:18 PM PDT 24
Finished May 28 01:46:47 PM PDT 24
Peak memory 211252 kb
Host smart-60f1051e-0f7a-4ad0-a069-ff4b8a27d1cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575132465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2575132465
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1155477778
Short name T41
Test name
Test status
Simulation time 4639118589 ps
CPU time 187.36 seconds
Started May 28 01:46:19 PM PDT 24
Finished May 28 01:49:47 PM PDT 24
Peak memory 237564 kb
Host smart-c11559fd-de5a-4733-a499-4c6de1d21681
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155477778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1155477778
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.494361649
Short name T307
Test name
Test status
Simulation time 674537741 ps
CPU time 18.5 seconds
Started May 28 01:46:20 PM PDT 24
Finished May 28 01:46:58 PM PDT 24
Peak memory 214552 kb
Host smart-3275f652-47ae-4422-8fcc-b70c50e7f09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494361649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.494361649
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2266263807
Short name T128
Test name
Test status
Simulation time 15837644550 ps
CPU time 25.51 seconds
Started May 28 01:46:17 PM PDT 24
Finished May 28 01:47:03 PM PDT 24
Peak memory 211704 kb
Host smart-0f1aa831-0403-4500-940a-45d650c08cf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2266263807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2266263807
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1876155533
Short name T194
Test name
Test status
Simulation time 348657460 ps
CPU time 20.36 seconds
Started May 28 01:46:16 PM PDT 24
Finished May 28 01:46:58 PM PDT 24
Peak memory 217568 kb
Host smart-6073bbda-e27c-4552-aa38-ddff388e52e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876155533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1876155533
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1201173518
Short name T203
Test name
Test status
Simulation time 27430585228 ps
CPU time 143.48 seconds
Started May 28 01:46:17 PM PDT 24
Finished May 28 01:49:02 PM PDT 24
Peak memory 221472 kb
Host smart-a9c1cba5-2538-4c9f-8303-837d79b5f43e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201173518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1201173518
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.4018964402
Short name T44
Test name
Test status
Simulation time 188143632160 ps
CPU time 3023.42 seconds
Started May 28 01:46:18 PM PDT 24
Finished May 28 02:37:03 PM PDT 24
Peak memory 243936 kb
Host smart-236e42a1-79cf-4afe-81c3-a5e26327ab2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018964402 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.4018964402
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1915036003
Short name T138
Test name
Test status
Simulation time 1510297579 ps
CPU time 18.42 seconds
Started May 28 01:46:18 PM PDT 24
Finished May 28 01:46:57 PM PDT 24
Peak memory 211268 kb
Host smart-6d7f005d-6c23-48ae-9295-633821a05cc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915036003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1915036003
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1149184000
Short name T258
Test name
Test status
Simulation time 160774284744 ps
CPU time 643.58 seconds
Started May 28 01:46:22 PM PDT 24
Finished May 28 01:57:24 PM PDT 24
Peak memory 217820 kb
Host smart-b8d7f31e-918e-42d7-9bb4-ab136c4c7b92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149184000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1149184000
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3765245653
Short name T284
Test name
Test status
Simulation time 20107332800 ps
CPU time 57.33 seconds
Started May 28 01:46:18 PM PDT 24
Finished May 28 01:47:36 PM PDT 24
Peak memory 212780 kb
Host smart-84d47ea3-cbe0-4d61-bf77-00a8604d98c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765245653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3765245653
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2613629254
Short name T35
Test name
Test status
Simulation time 3692329889 ps
CPU time 30.85 seconds
Started May 28 01:46:19 PM PDT 24
Finished May 28 01:47:10 PM PDT 24
Peak memory 212228 kb
Host smart-f1e6ebe5-f105-46e6-b460-cd5759627454
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2613629254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2613629254
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2395359956
Short name T40
Test name
Test status
Simulation time 7575874663 ps
CPU time 32.1 seconds
Started May 28 01:46:17 PM PDT 24
Finished May 28 01:47:11 PM PDT 24
Peak memory 217440 kb
Host smart-8d37bde3-295c-402e-9e8d-9634e4ad8346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395359956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2395359956
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1924823409
Short name T213
Test name
Test status
Simulation time 3870439942 ps
CPU time 33.95 seconds
Started May 28 01:46:16 PM PDT 24
Finished May 28 01:47:12 PM PDT 24
Peak memory 212084 kb
Host smart-574551fd-7259-465d-882e-be006991ff6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924823409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1924823409
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1398883051
Short name T320
Test name
Test status
Simulation time 8541454663 ps
CPU time 20.93 seconds
Started May 28 01:46:18 PM PDT 24
Finished May 28 01:47:00 PM PDT 24
Peak memory 212132 kb
Host smart-5a41a098-beea-4a7f-9331-03d996afb96f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398883051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1398883051
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2699178995
Short name T344
Test name
Test status
Simulation time 61978913283 ps
CPU time 766.88 seconds
Started May 28 01:46:18 PM PDT 24
Finished May 28 01:59:26 PM PDT 24
Peak memory 234024 kb
Host smart-d2be2b0b-a1fc-4b66-a70e-324e328ac77e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699178995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2699178995
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2578402532
Short name T175
Test name
Test status
Simulation time 15733449044 ps
CPU time 45.77 seconds
Started May 28 01:46:17 PM PDT 24
Finished May 28 01:47:24 PM PDT 24
Peak memory 214864 kb
Host smart-f9d40946-3f8c-40a5-9b98-157560ca7999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578402532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2578402532
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2634908547
Short name T139
Test name
Test status
Simulation time 184566085 ps
CPU time 10.67 seconds
Started May 28 01:46:21 PM PDT 24
Finished May 28 01:46:51 PM PDT 24
Peak memory 212452 kb
Host smart-7777b575-6c5e-4202-a861-7ddf4f22e285
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2634908547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2634908547
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2443951427
Short name T57
Test name
Test status
Simulation time 2023793440 ps
CPU time 19.89 seconds
Started May 28 01:46:17 PM PDT 24
Finished May 28 01:46:59 PM PDT 24
Peak memory 217588 kb
Host smart-ec571be8-f277-4b7a-b182-85419f786164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443951427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2443951427
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3195981445
Short name T352
Test name
Test status
Simulation time 4657634244 ps
CPU time 63.03 seconds
Started May 28 01:46:17 PM PDT 24
Finished May 28 01:47:41 PM PDT 24
Peak memory 219280 kb
Host smart-35507e95-6b55-420e-b573-ac3e77694019
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195981445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3195981445
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.278321214
Short name T306
Test name
Test status
Simulation time 688576642 ps
CPU time 8.39 seconds
Started May 28 01:46:18 PM PDT 24
Finished May 28 01:46:47 PM PDT 24
Peak memory 211244 kb
Host smart-42243231-20bb-4c93-9aa1-9940925228eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278321214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.278321214
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2757392131
Short name T328
Test name
Test status
Simulation time 12822924071 ps
CPU time 144.63 seconds
Started May 28 01:46:20 PM PDT 24
Finished May 28 01:49:04 PM PDT 24
Peak memory 229492 kb
Host smart-83e11bab-c281-42fe-8ebf-f047f3ba9363
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757392131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2757392131
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2594293115
Short name T252
Test name
Test status
Simulation time 54047622964 ps
CPU time 44.3 seconds
Started May 28 01:46:18 PM PDT 24
Finished May 28 01:47:23 PM PDT 24
Peak memory 215148 kb
Host smart-b69bec2a-caa8-4304-9b5a-fdc4ef956012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594293115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2594293115
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2127838020
Short name T3
Test name
Test status
Simulation time 433618915 ps
CPU time 10.31 seconds
Started May 28 01:46:18 PM PDT 24
Finished May 28 01:46:49 PM PDT 24
Peak memory 212256 kb
Host smart-c8d09e7a-1835-4402-a7a2-4949d08e7d29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2127838020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2127838020
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.527305185
Short name T263
Test name
Test status
Simulation time 6100677705 ps
CPU time 46.45 seconds
Started May 28 01:46:16 PM PDT 24
Finished May 28 01:47:24 PM PDT 24
Peak memory 218260 kb
Host smart-dcf36aa6-2a40-40b5-954a-71726f8c86c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527305185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.527305185
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3698061412
Short name T259
Test name
Test status
Simulation time 19531094869 ps
CPU time 71.39 seconds
Started May 28 01:46:19 PM PDT 24
Finished May 28 01:47:51 PM PDT 24
Peak memory 219232 kb
Host smart-d26513c5-56c7-4e92-8b09-1b3dbc5b5a9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698061412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3698061412
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1366528479
Short name T239
Test name
Test status
Simulation time 7220683601 ps
CPU time 23.89 seconds
Started May 28 01:46:28 PM PDT 24
Finished May 28 01:47:06 PM PDT 24
Peak memory 212128 kb
Host smart-18b55545-c6d1-4c4f-bbfc-7c93d5648a0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366528479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1366528479
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1690602453
Short name T335
Test name
Test status
Simulation time 34918314952 ps
CPU time 221.01 seconds
Started May 28 01:46:29 PM PDT 24
Finished May 28 01:50:24 PM PDT 24
Peak memory 228628 kb
Host smart-85998d41-941e-4714-9684-978a5266c716
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690602453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1690602453
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.662313672
Short name T219
Test name
Test status
Simulation time 26932564453 ps
CPU time 59.96 seconds
Started May 28 01:46:28 PM PDT 24
Finished May 28 01:47:42 PM PDT 24
Peak memory 213848 kb
Host smart-4e574771-b19d-46b9-9d07-b98ee3e8a4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662313672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.662313672
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1694751840
Short name T272
Test name
Test status
Simulation time 342677704 ps
CPU time 13.29 seconds
Started May 28 01:46:32 PM PDT 24
Finished May 28 01:46:57 PM PDT 24
Peak memory 211400 kb
Host smart-c856e2c6-197a-46ce-b20a-7b62298823d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1694751840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1694751840
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3953981018
Short name T243
Test name
Test status
Simulation time 5610543457 ps
CPU time 34.59 seconds
Started May 28 01:46:18 PM PDT 24
Finished May 28 01:47:14 PM PDT 24
Peak memory 216520 kb
Host smart-9d30d71b-6a76-4133-ad4a-83d38f65d6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953981018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3953981018
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2190035768
Short name T182
Test name
Test status
Simulation time 17473930207 ps
CPU time 78.6 seconds
Started May 28 01:46:18 PM PDT 24
Finished May 28 01:47:58 PM PDT 24
Peak memory 219408 kb
Host smart-ac67dcea-d118-40e3-b001-67917fbc1b88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190035768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2190035768
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3902789871
Short name T154
Test name
Test status
Simulation time 2461720987 ps
CPU time 23.91 seconds
Started May 28 01:46:31 PM PDT 24
Finished May 28 01:47:08 PM PDT 24
Peak memory 211300 kb
Host smart-2885bd2c-cedc-46f1-8af9-830b9f199b5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902789871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3902789871
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2363208260
Short name T21
Test name
Test status
Simulation time 3344421168 ps
CPU time 228.12 seconds
Started May 28 01:46:31 PM PDT 24
Finished May 28 01:50:32 PM PDT 24
Peak memory 225516 kb
Host smart-53bed09d-279a-4fff-87de-fca2411dcc72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363208260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2363208260
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1107563281
Short name T292
Test name
Test status
Simulation time 25367216152 ps
CPU time 56.8 seconds
Started May 28 01:46:30 PM PDT 24
Finished May 28 01:47:40 PM PDT 24
Peak memory 214888 kb
Host smart-a8830757-8c28-43bc-9218-6ce1ed04bb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107563281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1107563281
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2519890069
Short name T146
Test name
Test status
Simulation time 7997991050 ps
CPU time 28.7 seconds
Started May 28 01:46:28 PM PDT 24
Finished May 28 01:47:11 PM PDT 24
Peak memory 211364 kb
Host smart-bb7f1a83-be01-41c5-b418-2fcbb6782bf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2519890069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2519890069
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.815717532
Short name T299
Test name
Test status
Simulation time 14421221203 ps
CPU time 48.55 seconds
Started May 28 01:46:29 PM PDT 24
Finished May 28 01:47:31 PM PDT 24
Peak memory 216940 kb
Host smart-6b962e15-5420-4d3a-a640-baa3bcd6d306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815717532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.815717532
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1970583996
Short name T81
Test name
Test status
Simulation time 3998508806 ps
CPU time 34.52 seconds
Started May 28 01:46:34 PM PDT 24
Finished May 28 01:47:19 PM PDT 24
Peak memory 218020 kb
Host smart-b65b84c4-f005-4c8a-8273-3e769f556b6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970583996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1970583996
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.923512885
Short name T2
Test name
Test status
Simulation time 635871285 ps
CPU time 8.38 seconds
Started May 28 01:46:28 PM PDT 24
Finished May 28 01:46:51 PM PDT 24
Peak memory 211244 kb
Host smart-2a3726ab-7968-45c5-8c08-e49e5be7f073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923512885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.923512885
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2782584995
Short name T202
Test name
Test status
Simulation time 4908112291 ps
CPU time 276.29 seconds
Started May 28 01:46:30 PM PDT 24
Finished May 28 01:51:20 PM PDT 24
Peak memory 239704 kb
Host smart-716b5f0d-8cdf-4f30-96da-6afad12d7afe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782584995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2782584995
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.730702416
Short name T341
Test name
Test status
Simulation time 7577706165 ps
CPU time 44.12 seconds
Started May 28 01:46:31 PM PDT 24
Finished May 28 01:47:28 PM PDT 24
Peak memory 215196 kb
Host smart-2e0d508e-acb1-4803-bdcc-caa4a102cf96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730702416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.730702416
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.4008133795
Short name T302
Test name
Test status
Simulation time 8553667708 ps
CPU time 23.86 seconds
Started May 28 01:46:28 PM PDT 24
Finished May 28 01:47:07 PM PDT 24
Peak memory 212780 kb
Host smart-b9b2f103-c91a-479f-97b9-268b528318a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4008133795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.4008133795
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.658700802
Short name T296
Test name
Test status
Simulation time 680062524 ps
CPU time 25.69 seconds
Started May 28 01:46:30 PM PDT 24
Finished May 28 01:47:09 PM PDT 24
Peak memory 215632 kb
Host smart-a8361669-e92b-43c8-83d1-1959e810d424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658700802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.658700802
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1979323655
Short name T289
Test name
Test status
Simulation time 9049147247 ps
CPU time 129.21 seconds
Started May 28 01:46:31 PM PDT 24
Finished May 28 01:48:53 PM PDT 24
Peak memory 219488 kb
Host smart-acfbf6e3-20f5-4b0c-9806-85f77c1e09b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979323655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1979323655
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1651917245
Short name T135
Test name
Test status
Simulation time 15751091935 ps
CPU time 32.19 seconds
Started May 28 01:46:30 PM PDT 24
Finished May 28 01:47:16 PM PDT 24
Peak memory 212032 kb
Host smart-2e4b7ddd-9386-4efb-8d48-30f48da90a1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651917245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1651917245
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.909506408
Short name T164
Test name
Test status
Simulation time 570661584673 ps
CPU time 542.05 seconds
Started May 28 01:46:29 PM PDT 24
Finished May 28 01:55:46 PM PDT 24
Peak memory 224920 kb
Host smart-181578e1-04c2-43fb-b494-fd5527ee14a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909506408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.909506408
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.894223344
Short name T14
Test name
Test status
Simulation time 688718209 ps
CPU time 19.22 seconds
Started May 28 01:46:29 PM PDT 24
Finished May 28 01:47:02 PM PDT 24
Peak memory 214704 kb
Host smart-74b61ef3-b44b-4575-8116-144dee65c92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894223344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.894223344
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1412728882
Short name T271
Test name
Test status
Simulation time 4486866304 ps
CPU time 23.11 seconds
Started May 28 01:46:31 PM PDT 24
Finished May 28 01:47:07 PM PDT 24
Peak memory 212708 kb
Host smart-968153fb-042d-4df6-8ff1-baa8594ec105
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1412728882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1412728882
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1820938839
Short name T153
Test name
Test status
Simulation time 4097832853 ps
CPU time 43.45 seconds
Started May 28 01:46:31 PM PDT 24
Finished May 28 01:47:27 PM PDT 24
Peak memory 216516 kb
Host smart-1669365a-94e8-4136-9c0a-71aee0404e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820938839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1820938839
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.468271902
Short name T240
Test name
Test status
Simulation time 106842723446 ps
CPU time 179.02 seconds
Started May 28 01:46:28 PM PDT 24
Finished May 28 01:49:42 PM PDT 24
Peak memory 227360 kb
Host smart-b4d0df23-adbe-48cc-beb2-85770491c5bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468271902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.468271902
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.352877589
Short name T149
Test name
Test status
Simulation time 10496351869 ps
CPU time 23.91 seconds
Started May 28 01:44:38 PM PDT 24
Finished May 28 01:45:04 PM PDT 24
Peak memory 211812 kb
Host smart-4775190d-1ba4-4df0-b2be-9962b5262ed0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352877589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.352877589
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.167997159
Short name T172
Test name
Test status
Simulation time 122687835525 ps
CPU time 352.7 seconds
Started May 28 01:44:36 PM PDT 24
Finished May 28 01:50:31 PM PDT 24
Peak memory 233816 kb
Host smart-9cd88dfb-27c3-48db-8dc4-a6fab813935a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167997159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.167997159
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1128868302
Short name T19
Test name
Test status
Simulation time 6280423430 ps
CPU time 55.86 seconds
Started May 28 01:44:36 PM PDT 24
Finished May 28 01:45:34 PM PDT 24
Peak memory 213060 kb
Host smart-bc83c192-092e-4cf1-aa89-09838c273ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128868302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1128868302
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2988221552
Short name T354
Test name
Test status
Simulation time 179847671 ps
CPU time 10.37 seconds
Started May 28 01:44:41 PM PDT 24
Finished May 28 01:44:52 PM PDT 24
Peak memory 211500 kb
Host smart-a63db58e-0eda-4e82-98d4-055dfa9e2a90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2988221552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2988221552
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2994586152
Short name T278
Test name
Test status
Simulation time 481045536 ps
CPU time 19.98 seconds
Started May 28 01:44:37 PM PDT 24
Finished May 28 01:44:59 PM PDT 24
Peak memory 214840 kb
Host smart-c341637e-0114-4318-acf4-5899a8c3165b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994586152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2994586152
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3452267621
Short name T126
Test name
Test status
Simulation time 23724670742 ps
CPU time 117.5 seconds
Started May 28 01:44:37 PM PDT 24
Finished May 28 01:46:37 PM PDT 24
Peak memory 219656 kb
Host smart-958ace9e-240b-4777-9f0b-098d1c0b976e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452267621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3452267621
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.947199695
Short name T187
Test name
Test status
Simulation time 6609513045 ps
CPU time 28.46 seconds
Started May 28 01:44:45 PM PDT 24
Finished May 28 01:45:15 PM PDT 24
Peak memory 212048 kb
Host smart-331ba988-dd6d-4744-9fe9-c28b454b129d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947199695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.947199695
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1420912016
Short name T256
Test name
Test status
Simulation time 4584177884 ps
CPU time 233.5 seconds
Started May 28 01:44:40 PM PDT 24
Finished May 28 01:48:35 PM PDT 24
Peak memory 228480 kb
Host smart-6d763cde-ef3d-423b-bcca-bd1091cb2874
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420912016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1420912016
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2558987990
Short name T318
Test name
Test status
Simulation time 13480496321 ps
CPU time 62 seconds
Started May 28 01:44:45 PM PDT 24
Finished May 28 01:45:48 PM PDT 24
Peak memory 214828 kb
Host smart-ac4384f8-8d00-4ed0-99ec-c9eec82dd118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558987990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2558987990
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.250876693
Short name T326
Test name
Test status
Simulation time 3593337508 ps
CPU time 30.62 seconds
Started May 28 01:44:38 PM PDT 24
Finished May 28 01:45:11 PM PDT 24
Peak memory 212120 kb
Host smart-491bfc9b-48c4-4e6d-b2ba-617545abd994
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=250876693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.250876693
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.671479011
Short name T121
Test name
Test status
Simulation time 36490535623 ps
CPU time 72.4 seconds
Started May 28 01:44:35 PM PDT 24
Finished May 28 01:45:49 PM PDT 24
Peak memory 217256 kb
Host smart-2e401e65-c38e-4d20-b412-50273e1c755b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671479011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.671479011
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1515274739
Short name T7
Test name
Test status
Simulation time 79705629842 ps
CPU time 103.2 seconds
Started May 28 01:44:42 PM PDT 24
Finished May 28 01:46:26 PM PDT 24
Peak memory 220324 kb
Host smart-43b37cac-fd11-4180-8d25-cef3c607674f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515274739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1515274739
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.436583403
Short name T300
Test name
Test status
Simulation time 4095675115 ps
CPU time 21.76 seconds
Started May 28 01:44:45 PM PDT 24
Finished May 28 01:45:07 PM PDT 24
Peak memory 211744 kb
Host smart-943d4403-2341-4580-aa28-ffd7492b34bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436583403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.436583403
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3173923410
Short name T143
Test name
Test status
Simulation time 9019023261 ps
CPU time 163.57 seconds
Started May 28 01:44:45 PM PDT 24
Finished May 28 01:47:30 PM PDT 24
Peak memory 237548 kb
Host smart-630beded-8677-437e-b6d8-04ef1d043891
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173923410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3173923410
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2681363218
Short name T337
Test name
Test status
Simulation time 1374557727 ps
CPU time 19.19 seconds
Started May 28 01:44:47 PM PDT 24
Finished May 28 01:45:07 PM PDT 24
Peak memory 214556 kb
Host smart-706dc37b-e72a-41a6-840e-77456c586ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681363218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2681363218
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3145316131
Short name T140
Test name
Test status
Simulation time 8808863577 ps
CPU time 25.6 seconds
Started May 28 01:44:51 PM PDT 24
Finished May 28 01:45:17 PM PDT 24
Peak memory 211680 kb
Host smart-9fe53d21-2afe-4554-a2dc-1d467de2b4e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3145316131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3145316131
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1547518693
Short name T260
Test name
Test status
Simulation time 1366412325 ps
CPU time 20.65 seconds
Started May 28 01:44:47 PM PDT 24
Finished May 28 01:45:09 PM PDT 24
Peak memory 216164 kb
Host smart-9e452443-8f7f-4580-9d90-c21f540c66d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547518693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1547518693
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1395882868
Short name T346
Test name
Test status
Simulation time 2358678164 ps
CPU time 56.29 seconds
Started May 28 01:44:46 PM PDT 24
Finished May 28 01:45:44 PM PDT 24
Peak memory 219216 kb
Host smart-b4063542-c882-4733-857a-9cf35adb95ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395882868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1395882868
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1119429799
Short name T314
Test name
Test status
Simulation time 1543618135 ps
CPU time 13.92 seconds
Started May 28 01:44:47 PM PDT 24
Finished May 28 01:45:03 PM PDT 24
Peak memory 211252 kb
Host smart-0a5b2d52-aea6-479a-a6c4-04cda85ca3b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119429799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1119429799
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2054609064
Short name T137
Test name
Test status
Simulation time 983988604230 ps
CPU time 968.07 seconds
Started May 28 01:44:50 PM PDT 24
Finished May 28 02:00:59 PM PDT 24
Peak memory 217032 kb
Host smart-e9c0ba58-9409-4d9a-8217-4d2ac4c86200
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054609064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2054609064
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3204759693
Short name T290
Test name
Test status
Simulation time 36585210934 ps
CPU time 48.2 seconds
Started May 28 01:44:48 PM PDT 24
Finished May 28 01:45:37 PM PDT 24
Peak memory 215180 kb
Host smart-14f62c70-e6ab-430b-bc65-6c20e6b941e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204759693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3204759693
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2623375706
Short name T220
Test name
Test status
Simulation time 3178253158 ps
CPU time 21.4 seconds
Started May 28 01:44:47 PM PDT 24
Finished May 28 01:45:09 PM PDT 24
Peak memory 212540 kb
Host smart-b0f23e53-f549-421e-bb73-bbd3303eb92b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2623375706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2623375706
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2522454544
Short name T241
Test name
Test status
Simulation time 35653370270 ps
CPU time 81.33 seconds
Started May 28 01:44:47 PM PDT 24
Finished May 28 01:46:10 PM PDT 24
Peak memory 216800 kb
Host smart-385c08fa-2abf-4a30-9735-38bb4722868e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522454544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2522454544
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.296160692
Short name T155
Test name
Test status
Simulation time 2020815872 ps
CPU time 17.14 seconds
Started May 28 01:44:47 PM PDT 24
Finished May 28 01:45:05 PM PDT 24
Peak memory 213564 kb
Host smart-785746ba-929e-47d2-b4fa-fe5dc680b4bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296160692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.296160692
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1381229197
Short name T28
Test name
Test status
Simulation time 34522111417 ps
CPU time 1033.99 seconds
Started May 28 01:44:47 PM PDT 24
Finished May 28 02:02:02 PM PDT 24
Peak memory 235700 kb
Host smart-93ed08d5-00e0-431e-88a2-c15b97edfa59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381229197 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.1381229197
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1541443516
Short name T158
Test name
Test status
Simulation time 6074851772 ps
CPU time 26.31 seconds
Started May 28 01:44:51 PM PDT 24
Finished May 28 01:45:18 PM PDT 24
Peak memory 212124 kb
Host smart-db90f0ee-5c7b-49b3-8ad9-a593aa77925b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541443516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1541443516
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3048069210
Short name T5
Test name
Test status
Simulation time 26873636373 ps
CPU time 241.43 seconds
Started May 28 01:44:49 PM PDT 24
Finished May 28 01:48:51 PM PDT 24
Peak memory 229792 kb
Host smart-140c886d-a1bf-4301-bc98-93b3a7700a3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048069210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3048069210
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3401140353
Short name T301
Test name
Test status
Simulation time 1942283622 ps
CPU time 19.54 seconds
Started May 28 01:44:47 PM PDT 24
Finished May 28 01:45:08 PM PDT 24
Peak memory 214792 kb
Host smart-f52e6be8-12b7-4d6d-9500-32dd654cb536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401140353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3401140353
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3249997182
Short name T293
Test name
Test status
Simulation time 363691064 ps
CPU time 10.76 seconds
Started May 28 01:44:48 PM PDT 24
Finished May 28 01:45:00 PM PDT 24
Peak memory 212288 kb
Host smart-71212818-80fe-416b-9c31-979c661083c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3249997182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3249997182
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.418419629
Short name T145
Test name
Test status
Simulation time 62925741391 ps
CPU time 64.76 seconds
Started May 28 01:44:46 PM PDT 24
Finished May 28 01:45:52 PM PDT 24
Peak memory 216736 kb
Host smart-23575bff-d993-4d93-810c-9e50bcea0557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418419629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.418419629
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1044278458
Short name T286
Test name
Test status
Simulation time 47405336686 ps
CPU time 220.39 seconds
Started May 28 01:44:47 PM PDT 24
Finished May 28 01:48:29 PM PDT 24
Peak memory 222100 kb
Host smart-1a1fb629-358f-4158-b0cf-26145f094332
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044278458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1044278458
Directory /workspace/9.rom_ctrl_stress_all/latest
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