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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.50 96.97 93.02 97.88 100.00 98.37 97.89 98.37


Total test records in report: 453
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T310 /workspace/coverage/default/5.rom_ctrl_alert_test.458089200 Jun 02 02:41:24 PM PDT 24 Jun 02 02:41:47 PM PDT 24 4190779454 ps
T311 /workspace/coverage/default/5.rom_ctrl_smoke.3433141338 Jun 02 02:41:10 PM PDT 24 Jun 02 02:42:29 PM PDT 24 22476653168 ps
T312 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3706115251 Jun 02 02:42:02 PM PDT 24 Jun 02 02:42:57 PM PDT 24 111359819168 ps
T313 /workspace/coverage/default/20.rom_ctrl_smoke.3412333689 Jun 02 02:41:30 PM PDT 24 Jun 02 02:42:27 PM PDT 24 24463194030 ps
T314 /workspace/coverage/default/0.rom_ctrl_smoke.2044120177 Jun 02 02:41:07 PM PDT 24 Jun 02 02:41:43 PM PDT 24 2594036349 ps
T315 /workspace/coverage/default/9.rom_ctrl_alert_test.1061695851 Jun 02 02:41:18 PM PDT 24 Jun 02 02:41:41 PM PDT 24 10406448257 ps
T316 /workspace/coverage/default/26.rom_ctrl_smoke.3104144394 Jun 02 02:41:39 PM PDT 24 Jun 02 02:42:38 PM PDT 24 46362175186 ps
T317 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1565178667 Jun 02 02:41:31 PM PDT 24 Jun 02 02:44:33 PM PDT 24 10003159111 ps
T318 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.9612128 Jun 02 02:41:51 PM PDT 24 Jun 02 02:47:20 PM PDT 24 145714265811 ps
T319 /workspace/coverage/default/8.rom_ctrl_smoke.2947991720 Jun 02 02:41:17 PM PDT 24 Jun 02 02:41:38 PM PDT 24 1363476639 ps
T320 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2034438979 Jun 02 02:41:25 PM PDT 24 Jun 02 02:50:37 PM PDT 24 43560389071 ps
T321 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.4025723162 Jun 02 02:41:25 PM PDT 24 Jun 02 02:42:08 PM PDT 24 15049358082 ps
T322 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3737634970 Jun 02 02:41:32 PM PDT 24 Jun 02 02:42:44 PM PDT 24 34010488528 ps
T323 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2758061586 Jun 02 02:41:23 PM PDT 24 Jun 02 02:41:57 PM PDT 24 4072074035 ps
T324 /workspace/coverage/default/7.rom_ctrl_stress_all.941251515 Jun 02 02:41:18 PM PDT 24 Jun 02 02:41:47 PM PDT 24 2066836917 ps
T325 /workspace/coverage/default/39.rom_ctrl_alert_test.2216025010 Jun 02 02:41:49 PM PDT 24 Jun 02 02:41:58 PM PDT 24 167501555 ps
T326 /workspace/coverage/default/6.rom_ctrl_smoke.387402855 Jun 02 02:41:23 PM PDT 24 Jun 02 02:42:18 PM PDT 24 51103856863 ps
T327 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2724435140 Jun 02 02:42:00 PM PDT 24 Jun 02 02:57:01 PM PDT 24 179955477796 ps
T328 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1369308497 Jun 02 02:41:56 PM PDT 24 Jun 02 02:42:28 PM PDT 24 3825321250 ps
T329 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2857963086 Jun 02 02:42:03 PM PDT 24 Jun 02 02:43:06 PM PDT 24 7071011964 ps
T330 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.939330070 Jun 02 02:41:45 PM PDT 24 Jun 02 02:46:28 PM PDT 24 132945401507 ps
T331 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.783948432 Jun 02 02:41:30 PM PDT 24 Jun 02 02:42:05 PM PDT 24 3931318200 ps
T48 /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2579215546 Jun 02 02:41:58 PM PDT 24 Jun 02 05:03:13 PM PDT 24 158937703773 ps
T332 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.392446192 Jun 02 02:41:37 PM PDT 24 Jun 02 02:50:40 PM PDT 24 327568547410 ps
T333 /workspace/coverage/default/10.rom_ctrl_smoke.62852144 Jun 02 02:41:18 PM PDT 24 Jun 02 02:42:01 PM PDT 24 3695751276 ps
T334 /workspace/coverage/default/40.rom_ctrl_smoke.2550326018 Jun 02 02:41:56 PM PDT 24 Jun 02 02:43:14 PM PDT 24 28091589720 ps
T335 /workspace/coverage/default/10.rom_ctrl_alert_test.1046006908 Jun 02 02:41:25 PM PDT 24 Jun 02 02:41:34 PM PDT 24 174442775 ps
T336 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1092442732 Jun 02 02:41:58 PM PDT 24 Jun 02 02:46:17 PM PDT 24 35531105978 ps
T337 /workspace/coverage/default/3.rom_ctrl_smoke.274960256 Jun 02 02:41:13 PM PDT 24 Jun 02 02:42:19 PM PDT 24 7735265520 ps
T338 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2341291951 Jun 02 02:41:31 PM PDT 24 Jun 02 02:52:18 PM PDT 24 67716395536 ps
T339 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.352864627 Jun 02 02:41:31 PM PDT 24 Jun 02 02:46:16 PM PDT 24 3405369091 ps
T340 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3578004989 Jun 02 02:41:24 PM PDT 24 Jun 02 02:49:13 PM PDT 24 31033729377 ps
T341 /workspace/coverage/default/33.rom_ctrl_stress_all.2133283354 Jun 02 02:41:45 PM PDT 24 Jun 02 02:44:26 PM PDT 24 14143595113 ps
T342 /workspace/coverage/default/27.rom_ctrl_alert_test.1125299568 Jun 02 02:41:39 PM PDT 24 Jun 02 02:41:51 PM PDT 24 345752176 ps
T343 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3761120950 Jun 02 02:41:46 PM PDT 24 Jun 02 02:42:05 PM PDT 24 3858211485 ps
T344 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3523993855 Jun 02 02:41:34 PM PDT 24 Jun 02 02:41:49 PM PDT 24 1688933881 ps
T345 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.639974705 Jun 02 02:41:38 PM PDT 24 Jun 02 02:41:58 PM PDT 24 1737781180 ps
T346 /workspace/coverage/default/7.rom_ctrl_alert_test.3764734555 Jun 02 02:41:18 PM PDT 24 Jun 02 02:41:41 PM PDT 24 3754557256 ps
T347 /workspace/coverage/default/42.rom_ctrl_stress_all.2472284626 Jun 02 02:42:00 PM PDT 24 Jun 02 02:43:06 PM PDT 24 26934194705 ps
T348 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.960046365 Jun 02 02:41:05 PM PDT 24 Jun 02 02:42:05 PM PDT 24 25897276009 ps
T349 /workspace/coverage/default/14.rom_ctrl_stress_all.2333110181 Jun 02 02:41:25 PM PDT 24 Jun 02 02:42:00 PM PDT 24 2122357454 ps
T350 /workspace/coverage/default/42.rom_ctrl_alert_test.1079499471 Jun 02 02:41:57 PM PDT 24 Jun 02 02:42:29 PM PDT 24 3575590892 ps
T351 /workspace/coverage/default/28.rom_ctrl_alert_test.593060492 Jun 02 02:41:38 PM PDT 24 Jun 02 02:42:13 PM PDT 24 5053127987 ps
T352 /workspace/coverage/default/30.rom_ctrl_alert_test.521687963 Jun 02 02:41:45 PM PDT 24 Jun 02 02:42:00 PM PDT 24 1109046877 ps
T353 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3145293716 Jun 02 02:41:59 PM PDT 24 Jun 02 02:42:39 PM PDT 24 15577376304 ps
T354 /workspace/coverage/default/3.rom_ctrl_alert_test.2005485203 Jun 02 02:41:13 PM PDT 24 Jun 02 02:41:37 PM PDT 24 4961208723 ps
T355 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1720990650 Jun 02 02:41:19 PM PDT 24 Jun 02 02:41:36 PM PDT 24 749161334 ps
T356 /workspace/coverage/default/37.rom_ctrl_stress_all.1953332722 Jun 02 02:42:01 PM PDT 24 Jun 02 02:44:29 PM PDT 24 41786074907 ps
T34 /workspace/coverage/default/2.rom_ctrl_sec_cm.120066304 Jun 02 02:41:11 PM PDT 24 Jun 02 02:45:16 PM PDT 24 7065982323 ps
T357 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.4199004660 Jun 02 02:41:51 PM PDT 24 Jun 02 02:45:31 PM PDT 24 19319203917 ps
T358 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3025113714 Jun 02 02:41:26 PM PDT 24 Jun 02 02:41:55 PM PDT 24 4806070109 ps
T359 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2941200917 Jun 02 02:42:01 PM PDT 24 Jun 02 02:52:19 PM PDT 24 54712210681 ps
T360 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3977112603 Jun 02 02:41:05 PM PDT 24 Jun 02 02:41:25 PM PDT 24 1377363460 ps
T361 /workspace/coverage/default/25.rom_ctrl_smoke.3891993779 Jun 02 02:41:38 PM PDT 24 Jun 02 02:42:42 PM PDT 24 49013980153 ps
T362 /workspace/coverage/default/48.rom_ctrl_alert_test.1283722761 Jun 02 02:42:02 PM PDT 24 Jun 02 02:42:38 PM PDT 24 4360797927 ps
T363 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.250589011 Jun 02 02:41:20 PM PDT 24 Jun 02 02:41:37 PM PDT 24 755684028 ps
T364 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3233580439 Jun 02 02:41:24 PM PDT 24 Jun 02 02:41:35 PM PDT 24 351127846 ps
T365 /workspace/coverage/default/46.rom_ctrl_stress_all.582901118 Jun 02 02:41:58 PM PDT 24 Jun 02 02:43:41 PM PDT 24 42852929451 ps
T366 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.307195283 Jun 02 02:42:00 PM PDT 24 Jun 02 02:48:18 PM PDT 24 66046115480 ps
T58 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1075370543 Jun 02 02:40:42 PM PDT 24 Jun 02 02:41:03 PM PDT 24 6699891859 ps
T49 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1781973711 Jun 02 02:40:55 PM PDT 24 Jun 02 02:43:26 PM PDT 24 563173203 ps
T50 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1707528457 Jun 02 02:40:46 PM PDT 24 Jun 02 02:41:20 PM PDT 24 14458771630 ps
T51 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1673478436 Jun 02 02:41:02 PM PDT 24 Jun 02 02:41:16 PM PDT 24 660195988 ps
T52 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1124680022 Jun 02 02:40:57 PM PDT 24 Jun 02 02:41:10 PM PDT 24 6256616626 ps
T92 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.877735976 Jun 02 02:40:44 PM PDT 24 Jun 02 02:41:07 PM PDT 24 4837177798 ps
T99 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2510366079 Jun 02 02:40:55 PM PDT 24 Jun 02 02:41:16 PM PDT 24 9852035584 ps
T63 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3290750088 Jun 02 02:40:48 PM PDT 24 Jun 02 02:42:59 PM PDT 24 65690272808 ps
T93 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1062777656 Jun 02 02:40:57 PM PDT 24 Jun 02 02:41:06 PM PDT 24 2749747224 ps
T94 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.645324903 Jun 02 02:40:39 PM PDT 24 Jun 02 02:41:00 PM PDT 24 5787056732 ps
T64 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4074325785 Jun 02 02:40:46 PM PDT 24 Jun 02 02:41:15 PM PDT 24 9860387552 ps
T65 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2460412198 Jun 02 02:40:41 PM PDT 24 Jun 02 02:41:15 PM PDT 24 15869961678 ps
T367 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1352479406 Jun 02 02:40:44 PM PDT 24 Jun 02 02:41:02 PM PDT 24 6714047178 ps
T95 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2108331457 Jun 02 02:41:00 PM PDT 24 Jun 02 02:41:12 PM PDT 24 721518102 ps
T66 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2651438702 Jun 02 02:41:00 PM PDT 24 Jun 02 02:41:12 PM PDT 24 176529427 ps
T67 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.625163951 Jun 02 02:40:52 PM PDT 24 Jun 02 02:41:21 PM PDT 24 7907505278 ps
T55 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1326973752 Jun 02 02:40:56 PM PDT 24 Jun 02 02:42:39 PM PDT 24 38182568572 ps
T68 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3228948981 Jun 02 02:40:44 PM PDT 24 Jun 02 02:41:05 PM PDT 24 4964443440 ps
T62 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2322528549 Jun 02 02:41:01 PM PDT 24 Jun 02 02:41:18 PM PDT 24 7102786595 ps
T96 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2499842595 Jun 02 02:41:05 PM PDT 24 Jun 02 02:41:15 PM PDT 24 339244930 ps
T368 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.582783146 Jun 02 02:41:00 PM PDT 24 Jun 02 02:41:29 PM PDT 24 7167136249 ps
T97 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3376899772 Jun 02 02:40:57 PM PDT 24 Jun 02 02:43:54 PM PDT 24 83937298381 ps
T369 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3743126150 Jun 02 02:40:51 PM PDT 24 Jun 02 02:41:18 PM PDT 24 3067906120 ps
T69 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.220928066 Jun 02 02:40:53 PM PDT 24 Jun 02 02:41:07 PM PDT 24 949899376 ps
T370 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2020067303 Jun 02 02:40:53 PM PDT 24 Jun 02 02:41:25 PM PDT 24 15180676707 ps
T70 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2526614448 Jun 02 02:40:45 PM PDT 24 Jun 02 02:44:05 PM PDT 24 47312436230 ps
T71 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1025033769 Jun 02 02:40:52 PM PDT 24 Jun 02 02:41:01 PM PDT 24 345623665 ps
T56 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2549837628 Jun 02 02:40:57 PM PDT 24 Jun 02 02:42:40 PM PDT 24 7502250908 ps
T72 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2002852271 Jun 02 02:41:02 PM PDT 24 Jun 02 02:41:32 PM PDT 24 13607997693 ps
T98 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1692422244 Jun 02 02:40:45 PM PDT 24 Jun 02 02:41:06 PM PDT 24 1211059281 ps
T371 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2235972379 Jun 02 02:40:57 PM PDT 24 Jun 02 02:41:26 PM PDT 24 5301184208 ps
T372 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3986587608 Jun 02 02:40:48 PM PDT 24 Jun 02 02:41:15 PM PDT 24 2336272667 ps
T105 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3891513124 Jun 02 02:40:51 PM PDT 24 Jun 02 02:42:12 PM PDT 24 520379122 ps
T373 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3689516071 Jun 02 02:40:55 PM PDT 24 Jun 02 02:42:55 PM PDT 24 22608488473 ps
T111 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.140487960 Jun 02 02:41:03 PM PDT 24 Jun 02 02:42:30 PM PDT 24 9970714925 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.127458636 Jun 02 02:40:46 PM PDT 24 Jun 02 02:41:19 PM PDT 24 3437483951 ps
T375 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.278158124 Jun 02 02:40:48 PM PDT 24 Jun 02 02:41:21 PM PDT 24 4107049194 ps
T376 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3561555707 Jun 02 02:41:02 PM PDT 24 Jun 02 02:41:16 PM PDT 24 169159774 ps
T377 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2666895573 Jun 02 02:40:56 PM PDT 24 Jun 02 02:41:08 PM PDT 24 533298411 ps
T104 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.921901735 Jun 02 02:41:00 PM PDT 24 Jun 02 02:42:11 PM PDT 24 22919527996 ps
T378 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4141171544 Jun 02 02:41:01 PM PDT 24 Jun 02 02:41:33 PM PDT 24 3214382491 ps
T106 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3209016153 Jun 02 02:40:57 PM PDT 24 Jun 02 02:43:46 PM PDT 24 2910823574 ps
T379 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1170513415 Jun 02 02:40:48 PM PDT 24 Jun 02 02:41:02 PM PDT 24 1268250171 ps
T113 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2124730739 Jun 02 02:41:03 PM PDT 24 Jun 02 02:43:40 PM PDT 24 922577973 ps
T79 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1793009005 Jun 02 02:40:40 PM PDT 24 Jun 02 02:41:05 PM PDT 24 6817635731 ps
T380 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2786147598 Jun 02 02:40:55 PM PDT 24 Jun 02 02:41:18 PM PDT 24 20452670071 ps
T80 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1987800766 Jun 02 02:40:52 PM PDT 24 Jun 02 02:41:45 PM PDT 24 4743103440 ps
T381 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3013470838 Jun 02 02:41:00 PM PDT 24 Jun 02 02:41:21 PM PDT 24 3598480322 ps
T382 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.129236232 Jun 02 02:41:00 PM PDT 24 Jun 02 02:41:13 PM PDT 24 717660505 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3550467826 Jun 02 02:40:48 PM PDT 24 Jun 02 02:40:57 PM PDT 24 167360265 ps
T384 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4089431194 Jun 02 02:41:04 PM PDT 24 Jun 02 02:41:32 PM PDT 24 2637673587 ps
T102 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1111261335 Jun 02 02:41:04 PM PDT 24 Jun 02 02:42:48 PM PDT 24 7515362062 ps
T385 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4211074402 Jun 02 02:40:45 PM PDT 24 Jun 02 02:41:08 PM PDT 24 26809829572 ps
T386 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3758577725 Jun 02 02:40:59 PM PDT 24 Jun 02 02:41:23 PM PDT 24 9764440637 ps
T117 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.388148981 Jun 02 02:40:45 PM PDT 24 Jun 02 02:42:26 PM PDT 24 8987840079 ps
T81 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3998205926 Jun 02 02:41:02 PM PDT 24 Jun 02 02:43:04 PM PDT 24 10796155261 ps
T387 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2024992160 Jun 02 02:40:44 PM PDT 24 Jun 02 02:41:02 PM PDT 24 1331152315 ps
T118 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1669204937 Jun 02 02:40:43 PM PDT 24 Jun 02 02:42:08 PM PDT 24 3000165440 ps
T119 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1871773755 Jun 02 02:40:58 PM PDT 24 Jun 02 02:42:41 PM PDT 24 4938192296 ps
T388 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2158642944 Jun 02 02:40:53 PM PDT 24 Jun 02 02:41:16 PM PDT 24 3333007650 ps
T82 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1994713031 Jun 02 02:40:46 PM PDT 24 Jun 02 02:42:18 PM PDT 24 32852006279 ps
T389 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4090778431 Jun 02 02:40:45 PM PDT 24 Jun 02 02:42:35 PM PDT 24 25407577709 ps
T390 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3151615562 Jun 02 02:40:40 PM PDT 24 Jun 02 02:41:13 PM PDT 24 4066563723 ps
T88 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2645902640 Jun 02 02:40:58 PM PDT 24 Jun 02 02:42:47 PM PDT 24 11986576803 ps
T108 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2868703097 Jun 02 02:40:47 PM PDT 24 Jun 02 02:43:21 PM PDT 24 1129287415 ps
T391 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.505525306 Jun 02 02:41:05 PM PDT 24 Jun 02 02:41:26 PM PDT 24 4111953496 ps
T392 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3607494139 Jun 02 02:40:55 PM PDT 24 Jun 02 02:41:17 PM PDT 24 1327491720 ps
T393 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.983763459 Jun 02 02:40:45 PM PDT 24 Jun 02 02:41:01 PM PDT 24 1060848574 ps
T394 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.448741501 Jun 02 02:40:41 PM PDT 24 Jun 02 02:40:55 PM PDT 24 677417033 ps
T83 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3084309800 Jun 02 02:40:58 PM PDT 24 Jun 02 02:41:07 PM PDT 24 170657326 ps
T395 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.817686334 Jun 02 02:40:50 PM PDT 24 Jun 02 02:41:21 PM PDT 24 3864687237 ps
T109 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3178169405 Jun 02 02:40:59 PM PDT 24 Jun 02 02:43:50 PM PDT 24 7185625278 ps
T90 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2498487720 Jun 02 02:40:44 PM PDT 24 Jun 02 02:40:53 PM PDT 24 167696656 ps
T396 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2099710559 Jun 02 02:40:59 PM PDT 24 Jun 02 02:42:25 PM PDT 24 4071050268 ps
T397 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2668608230 Jun 02 02:40:56 PM PDT 24 Jun 02 02:41:14 PM PDT 24 4856275715 ps
T84 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2496163258 Jun 02 02:40:55 PM PDT 24 Jun 02 02:41:11 PM PDT 24 7646536121 ps
T103 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3562559691 Jun 02 02:40:54 PM PDT 24 Jun 02 02:44:08 PM PDT 24 50146771897 ps
T398 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2365805220 Jun 02 02:41:05 PM PDT 24 Jun 02 02:41:43 PM PDT 24 3127876818 ps
T399 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2210484921 Jun 02 02:40:54 PM PDT 24 Jun 02 02:41:15 PM PDT 24 3908098321 ps
T400 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4258780481 Jun 02 02:40:52 PM PDT 24 Jun 02 02:42:25 PM PDT 24 2001816384 ps
T401 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1648848845 Jun 02 02:40:57 PM PDT 24 Jun 02 02:41:31 PM PDT 24 51924674034 ps
T402 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1647568011 Jun 02 02:41:00 PM PDT 24 Jun 02 02:41:34 PM PDT 24 3861660661 ps
T403 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4193765397 Jun 02 02:40:59 PM PDT 24 Jun 02 02:41:26 PM PDT 24 3138357975 ps
T404 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2205888174 Jun 02 02:40:53 PM PDT 24 Jun 02 02:41:12 PM PDT 24 5217543547 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3836554811 Jun 02 02:40:49 PM PDT 24 Jun 02 02:41:11 PM PDT 24 2128060738 ps
T406 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1198721354 Jun 02 02:40:53 PM PDT 24 Jun 02 02:41:12 PM PDT 24 6395112880 ps
T407 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.15510118 Jun 02 02:40:42 PM PDT 24 Jun 02 02:41:17 PM PDT 24 14735885164 ps
T408 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.592286208 Jun 02 02:40:53 PM PDT 24 Jun 02 02:41:20 PM PDT 24 3235272874 ps
T409 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3623872801 Jun 02 02:41:02 PM PDT 24 Jun 02 02:41:35 PM PDT 24 3394044652 ps
T410 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3110404071 Jun 02 02:40:50 PM PDT 24 Jun 02 02:41:08 PM PDT 24 3751164839 ps
T411 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3003595532 Jun 02 02:41:02 PM PDT 24 Jun 02 02:41:33 PM PDT 24 15769419108 ps
T412 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.641967070 Jun 02 02:41:01 PM PDT 24 Jun 02 02:41:16 PM PDT 24 918414155 ps
T413 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2779997374 Jun 02 02:40:41 PM PDT 24 Jun 02 02:41:06 PM PDT 24 11163023323 ps
T112 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1745749505 Jun 02 02:41:00 PM PDT 24 Jun 02 02:43:58 PM PDT 24 8852109784 ps
T91 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.338521384 Jun 02 02:40:55 PM PDT 24 Jun 02 02:41:17 PM PDT 24 8588502573 ps
T414 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3371189239 Jun 02 02:40:51 PM PDT 24 Jun 02 02:41:13 PM PDT 24 3340565675 ps
T415 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2493479034 Jun 02 02:40:52 PM PDT 24 Jun 02 02:41:15 PM PDT 24 1237679029 ps
T416 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.937218819 Jun 02 02:40:45 PM PDT 24 Jun 02 02:41:09 PM PDT 24 24422847742 ps
T417 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.773389481 Jun 02 02:40:58 PM PDT 24 Jun 02 02:41:24 PM PDT 24 7148317839 ps
T418 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.670703417 Jun 02 02:40:47 PM PDT 24 Jun 02 02:41:15 PM PDT 24 3435528017 ps
T419 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2345962422 Jun 02 02:41:01 PM PDT 24 Jun 02 02:41:32 PM PDT 24 8063022239 ps
T420 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3635613840 Jun 02 02:41:06 PM PDT 24 Jun 02 02:41:40 PM PDT 24 4472857590 ps
T421 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2684803370 Jun 02 02:40:46 PM PDT 24 Jun 02 02:41:06 PM PDT 24 7904730521 ps
T422 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2215484433 Jun 02 02:40:50 PM PDT 24 Jun 02 02:42:21 PM PDT 24 8429491975 ps
T423 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3430253469 Jun 02 02:41:00 PM PDT 24 Jun 02 02:41:15 PM PDT 24 4745485884 ps
T424 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2608191148 Jun 02 02:41:00 PM PDT 24 Jun 02 02:41:09 PM PDT 24 190760008 ps
T425 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.750097774 Jun 02 02:40:57 PM PDT 24 Jun 02 02:41:20 PM PDT 24 2115242227 ps
T426 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3583182905 Jun 02 02:40:39 PM PDT 24 Jun 02 02:40:58 PM PDT 24 3416084587 ps
T427 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4188160484 Jun 02 02:40:51 PM PDT 24 Jun 02 02:41:19 PM PDT 24 3448089246 ps
T428 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2120479024 Jun 02 02:41:06 PM PDT 24 Jun 02 02:41:29 PM PDT 24 5138236073 ps
T110 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3371973745 Jun 02 02:41:00 PM PDT 24 Jun 02 02:42:41 PM PDT 24 3573832648 ps
T429 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2688014229 Jun 02 02:40:51 PM PDT 24 Jun 02 02:43:23 PM PDT 24 112695076517 ps
T85 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3922095428 Jun 02 02:40:53 PM PDT 24 Jun 02 02:43:48 PM PDT 24 80930460281 ps
T430 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3912424168 Jun 02 02:40:51 PM PDT 24 Jun 02 02:41:15 PM PDT 24 4084099990 ps
T114 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1794443210 Jun 02 02:40:43 PM PDT 24 Jun 02 02:43:34 PM PDT 24 3947576992 ps
T431 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.435765361 Jun 02 02:40:51 PM PDT 24 Jun 02 02:41:03 PM PDT 24 1056670016 ps
T432 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.486618762 Jun 02 02:40:58 PM PDT 24 Jun 02 02:41:27 PM PDT 24 14435557024 ps
T433 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1705107701 Jun 02 02:40:57 PM PDT 24 Jun 02 02:41:16 PM PDT 24 832818565 ps
T434 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2979614063 Jun 02 02:41:00 PM PDT 24 Jun 02 02:41:09 PM PDT 24 971173226 ps
T435 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3096703974 Jun 02 02:40:54 PM PDT 24 Jun 02 02:41:18 PM PDT 24 28775466007 ps
T436 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2076404216 Jun 02 02:40:57 PM PDT 24 Jun 02 02:41:23 PM PDT 24 36601733337 ps
T89 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3777678267 Jun 02 02:40:45 PM PDT 24 Jun 02 02:42:52 PM PDT 24 30907970732 ps
T437 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1999190895 Jun 02 02:40:43 PM PDT 24 Jun 02 02:41:19 PM PDT 24 3581736122 ps
T116 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2693241124 Jun 02 02:40:52 PM PDT 24 Jun 02 02:43:45 PM PDT 24 3229949924 ps
T115 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.478576417 Jun 02 02:40:47 PM PDT 24 Jun 02 02:43:29 PM PDT 24 3803908286 ps
T438 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3139422419 Jun 02 02:40:44 PM PDT 24 Jun 02 02:40:53 PM PDT 24 170948964 ps
T439 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3655502680 Jun 02 02:40:57 PM PDT 24 Jun 02 02:41:26 PM PDT 24 3600713080 ps
T440 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2379189659 Jun 02 02:40:46 PM PDT 24 Jun 02 02:41:19 PM PDT 24 16732284643 ps
T441 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1996943957 Jun 02 02:40:51 PM PDT 24 Jun 02 02:41:12 PM PDT 24 1967823035 ps
T442 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2635021414 Jun 02 02:40:47 PM PDT 24 Jun 02 02:41:12 PM PDT 24 10172789104 ps
T443 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3820905923 Jun 02 02:41:09 PM PDT 24 Jun 02 02:41:31 PM PDT 24 2983810410 ps
T107 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1300668806 Jun 02 02:40:54 PM PDT 24 Jun 02 02:43:30 PM PDT 24 4662636825 ps
T444 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2397799593 Jun 02 02:40:45 PM PDT 24 Jun 02 02:41:20 PM PDT 24 17575010874 ps
T445 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.979908628 Jun 02 02:40:45 PM PDT 24 Jun 02 02:41:16 PM PDT 24 6801755033 ps
T446 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1849867217 Jun 02 02:40:57 PM PDT 24 Jun 02 02:41:23 PM PDT 24 23738136280 ps
T86 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1666773433 Jun 02 02:40:59 PM PDT 24 Jun 02 02:42:54 PM PDT 24 13175229705 ps
T447 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2694255786 Jun 02 02:40:56 PM PDT 24 Jun 02 02:41:28 PM PDT 24 6909055213 ps
T448 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2226090407 Jun 02 02:41:02 PM PDT 24 Jun 02 02:41:36 PM PDT 24 8745397410 ps
T449 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2630030146 Jun 02 02:41:00 PM PDT 24 Jun 02 02:41:23 PM PDT 24 2628345091 ps
T87 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1797962164 Jun 02 02:41:01 PM PDT 24 Jun 02 02:41:35 PM PDT 24 4262661793 ps
T450 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.619225499 Jun 02 02:40:50 PM PDT 24 Jun 02 02:40:59 PM PDT 24 332350714 ps
T451 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1545854753 Jun 02 02:40:55 PM PDT 24 Jun 02 02:41:32 PM PDT 24 6973414889 ps
T452 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3962695128 Jun 02 02:40:57 PM PDT 24 Jun 02 02:41:35 PM PDT 24 693216142 ps
T453 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4147694033 Jun 02 02:40:55 PM PDT 24 Jun 02 02:41:21 PM PDT 24 16336624665 ps

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1683507061
Short name T2
Test name
Test status
Simulation time 9393490260 ps
CPU time 186.05 seconds
Started Jun 02 02:41:27 PM PDT 24
Finished Jun 02 02:44:34 PM PDT 24
Peak memory 237720 kb
Host smart-208d5756-3ddd-4f6f-b71e-86f48f176e48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683507061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1683507061
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3886333522
Short name T11
Test name
Test status
Simulation time 77667253307 ps
CPU time 6434.92 seconds
Started Jun 02 02:41:25 PM PDT 24
Finished Jun 02 04:28:42 PM PDT 24
Peak memory 232792 kb
Host smart-b55e77b5-a3e9-49dc-a3b4-cebe72ee1be5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886333522 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3886333522
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3281559215
Short name T26
Test name
Test status
Simulation time 131061916102 ps
CPU time 710.77 seconds
Started Jun 02 02:41:32 PM PDT 24
Finished Jun 02 02:53:24 PM PDT 24
Peak memory 240192 kb
Host smart-a27a8676-0988-4682-8775-f7037306164c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281559215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3281559215
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2916675501
Short name T20
Test name
Test status
Simulation time 3948657171 ps
CPU time 52.92 seconds
Started Jun 02 02:41:39 PM PDT 24
Finished Jun 02 02:42:33 PM PDT 24
Peak memory 215828 kb
Host smart-cbce5602-1380-4e9b-a362-0863ccd1b6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916675501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2916675501
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2549837628
Short name T56
Test name
Test status
Simulation time 7502250908 ps
CPU time 103.1 seconds
Started Jun 02 02:40:57 PM PDT 24
Finished Jun 02 02:42:40 PM PDT 24
Peak memory 214020 kb
Host smart-42032944-aced-4c03-bb42-5a69b629c259
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549837628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2549837628
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1980356862
Short name T14
Test name
Test status
Simulation time 318390666680 ps
CPU time 1270.97 seconds
Started Jun 02 02:41:59 PM PDT 24
Finished Jun 02 03:03:12 PM PDT 24
Peak memory 235860 kb
Host smart-29d62e34-34b6-4ff9-bd0c-3e362086c2ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980356862 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.1980356862
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1249460607
Short name T9
Test name
Test status
Simulation time 16315678991 ps
CPU time 93.67 seconds
Started Jun 02 02:41:37 PM PDT 24
Finished Jun 02 02:43:11 PM PDT 24
Peak memory 219364 kb
Host smart-8a025003-53d0-4930-b840-0aad72fdb875
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249460607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1249460607
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3920401162
Short name T28
Test name
Test status
Simulation time 2787553228 ps
CPU time 136.51 seconds
Started Jun 02 02:41:13 PM PDT 24
Finished Jun 02 02:43:30 PM PDT 24
Peak memory 237076 kb
Host smart-ec0c5ab6-b4b7-4596-920e-0821e2f7d662
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920401162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3920401162
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2460412198
Short name T65
Test name
Test status
Simulation time 15869961678 ps
CPU time 33.42 seconds
Started Jun 02 02:40:41 PM PDT 24
Finished Jun 02 02:41:15 PM PDT 24
Peak memory 211988 kb
Host smart-9bca4e9c-2292-4d90-a5e2-9d6afb1c393c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460412198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2460412198
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1745749505
Short name T112
Test name
Test status
Simulation time 8852109784 ps
CPU time 177.1 seconds
Started Jun 02 02:41:00 PM PDT 24
Finished Jun 02 02:43:58 PM PDT 24
Peak memory 219508 kb
Host smart-43734868-82e9-4e17-8703-1bd5e3aa034d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745749505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1745749505
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3178169405
Short name T109
Test name
Test status
Simulation time 7185625278 ps
CPU time 170.21 seconds
Started Jun 02 02:40:59 PM PDT 24
Finished Jun 02 02:43:50 PM PDT 24
Peak memory 214240 kb
Host smart-b4f2cead-a672-4a3d-b4fd-92fe68bf9e5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178169405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3178169405
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2211221998
Short name T32
Test name
Test status
Simulation time 3776425626 ps
CPU time 28.54 seconds
Started Jun 02 02:41:06 PM PDT 24
Finished Jun 02 02:41:35 PM PDT 24
Peak memory 211912 kb
Host smart-9ec95e29-f17c-4425-833e-334862db96f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211221998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2211221998
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3607070427
Short name T148
Test name
Test status
Simulation time 1033308261 ps
CPU time 19.7 seconds
Started Jun 02 02:41:19 PM PDT 24
Finished Jun 02 02:41:40 PM PDT 24
Peak memory 214692 kb
Host smart-160feaa2-c1a3-45ea-bab5-8f03a3c03eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607070427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3607070427
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2517949034
Short name T163
Test name
Test status
Simulation time 5462458257 ps
CPU time 28.79 seconds
Started Jun 02 02:41:23 PM PDT 24
Finished Jun 02 02:41:52 PM PDT 24
Peak memory 214048 kb
Host smart-3d367a66-10b5-4dd4-a229-e153016bc9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517949034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2517949034
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1300668806
Short name T107
Test name
Test status
Simulation time 4662636825 ps
CPU time 154.86 seconds
Started Jun 02 02:40:54 PM PDT 24
Finished Jun 02 02:43:30 PM PDT 24
Peak memory 214072 kb
Host smart-6ed61484-d6a6-4ac5-bf32-42d2b5dd43b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300668806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1300668806
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3376899772
Short name T97
Test name
Test status
Simulation time 83937298381 ps
CPU time 176.15 seconds
Started Jun 02 02:40:57 PM PDT 24
Finished Jun 02 02:43:54 PM PDT 24
Peak memory 214904 kb
Host smart-c4b53b79-0088-427e-b872-14fbd85780d6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376899772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3376899772
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.241942220
Short name T73
Test name
Test status
Simulation time 11209955079 ps
CPU time 41.64 seconds
Started Jun 02 02:41:30 PM PDT 24
Finished Jun 02 02:42:12 PM PDT 24
Peak memory 218112 kb
Host smart-579da094-8989-4ccc-9cc4-9e03cc89ba55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241942220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.241942220
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1793009005
Short name T79
Test name
Test status
Simulation time 6817635731 ps
CPU time 24.48 seconds
Started Jun 02 02:40:40 PM PDT 24
Finished Jun 02 02:41:05 PM PDT 24
Peak memory 219748 kb
Host smart-9ea8e55a-c34b-4dc3-ae72-760edc43ddae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793009005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1793009005
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.609488199
Short name T16
Test name
Test status
Simulation time 35314747126 ps
CPU time 1243.9 seconds
Started Jun 02 02:41:49 PM PDT 24
Finished Jun 02 03:02:33 PM PDT 24
Peak memory 232136 kb
Host smart-a2b3bb33-9847-4b39-8ae6-6b7f07c83e98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609488199 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.609488199
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1075370543
Short name T58
Test name
Test status
Simulation time 6699891859 ps
CPU time 20.04 seconds
Started Jun 02 02:40:42 PM PDT 24
Finished Jun 02 02:41:03 PM PDT 24
Peak memory 211980 kb
Host smart-90a687d9-c15d-46c9-9ba9-21d129154aa9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075370543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1075370543
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.448741501
Short name T394
Test name
Test status
Simulation time 677417033 ps
CPU time 13.72 seconds
Started Jun 02 02:40:41 PM PDT 24
Finished Jun 02 02:40:55 PM PDT 24
Peak memory 219500 kb
Host smart-5c4682a5-2822-4d7d-a097-ecc115c4b1a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448741501 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.448741501
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.645324903
Short name T94
Test name
Test status
Simulation time 5787056732 ps
CPU time 20.12 seconds
Started Jun 02 02:40:39 PM PDT 24
Finished Jun 02 02:41:00 PM PDT 24
Peak memory 212628 kb
Host smart-dc6c536b-d90d-426e-9085-e95e5d81080a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645324903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.645324903
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4211074402
Short name T385
Test name
Test status
Simulation time 26809829572 ps
CPU time 21.57 seconds
Started Jun 02 02:40:45 PM PDT 24
Finished Jun 02 02:41:08 PM PDT 24
Peak memory 211200 kb
Host smart-349ed113-d276-4986-88dd-d14ac88f6518
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211074402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4211074402
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3151615562
Short name T390
Test name
Test status
Simulation time 4066563723 ps
CPU time 32.92 seconds
Started Jun 02 02:40:40 PM PDT 24
Finished Jun 02 02:41:13 PM PDT 24
Peak memory 211216 kb
Host smart-44b44ee6-9158-46a8-ab0f-7d4a20b842f6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151615562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3151615562
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3777678267
Short name T89
Test name
Test status
Simulation time 30907970732 ps
CPU time 126.2 seconds
Started Jun 02 02:40:45 PM PDT 24
Finished Jun 02 02:42:52 PM PDT 24
Peak memory 214404 kb
Host smart-b337a004-5daf-4353-be0b-2ff4b045368b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777678267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3777678267
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1692422244
Short name T98
Test name
Test status
Simulation time 1211059281 ps
CPU time 19.76 seconds
Started Jun 02 02:40:45 PM PDT 24
Finished Jun 02 02:41:06 PM PDT 24
Peak memory 212372 kb
Host smart-a515276d-1883-4c7d-9918-aa719965aee0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692422244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1692422244
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3583182905
Short name T426
Test name
Test status
Simulation time 3416084587 ps
CPU time 18.65 seconds
Started Jun 02 02:40:39 PM PDT 24
Finished Jun 02 02:40:58 PM PDT 24
Peak memory 217560 kb
Host smart-dec1a0b0-1861-4488-9b74-275cf647c1ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583182905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3583182905
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1669204937
Short name T118
Test name
Test status
Simulation time 3000165440 ps
CPU time 84.18 seconds
Started Jun 02 02:40:43 PM PDT 24
Finished Jun 02 02:42:08 PM PDT 24
Peak memory 213756 kb
Host smart-5cd9f43d-574b-4fe5-872a-81a38f9e60c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669204937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1669204937
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2496163258
Short name T84
Test name
Test status
Simulation time 7646536121 ps
CPU time 15.11 seconds
Started Jun 02 02:40:55 PM PDT 24
Finished Jun 02 02:41:11 PM PDT 24
Peak memory 211248 kb
Host smart-4e167926-3c08-4382-968e-2068d89a9952
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496163258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2496163258
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2635021414
Short name T442
Test name
Test status
Simulation time 10172789104 ps
CPU time 24 seconds
Started Jun 02 02:40:47 PM PDT 24
Finished Jun 02 02:41:12 PM PDT 24
Peak memory 211988 kb
Host smart-04b3807b-7491-4da7-9364-443aea0dbdff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635021414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2635021414
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1999190895
Short name T437
Test name
Test status
Simulation time 3581736122 ps
CPU time 36.2 seconds
Started Jun 02 02:40:43 PM PDT 24
Finished Jun 02 02:41:19 PM PDT 24
Peak memory 211828 kb
Host smart-7ed1ed8c-0bed-4cfb-843b-e4a54a88a609
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999190895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1999190895
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2024992160
Short name T387
Test name
Test status
Simulation time 1331152315 ps
CPU time 16.88 seconds
Started Jun 02 02:40:44 PM PDT 24
Finished Jun 02 02:41:02 PM PDT 24
Peak memory 218512 kb
Host smart-78e61305-47bd-4d0e-9269-92994c623c68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024992160 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2024992160
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2684803370
Short name T421
Test name
Test status
Simulation time 7904730521 ps
CPU time 19.47 seconds
Started Jun 02 02:40:46 PM PDT 24
Finished Jun 02 02:41:06 PM PDT 24
Peak memory 212284 kb
Host smart-b07b59b5-4fa9-42e8-ab68-3e2cc3395bea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684803370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2684803370
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3550467826
Short name T383
Test name
Test status
Simulation time 167360265 ps
CPU time 7.97 seconds
Started Jun 02 02:40:48 PM PDT 24
Finished Jun 02 02:40:57 PM PDT 24
Peak memory 211056 kb
Host smart-b79004eb-eb5f-424b-a2c2-8874748ad389
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550467826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3550467826
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2779997374
Short name T413
Test name
Test status
Simulation time 11163023323 ps
CPU time 24.95 seconds
Started Jun 02 02:40:41 PM PDT 24
Finished Jun 02 02:41:06 PM PDT 24
Peak memory 211236 kb
Host smart-e658d3ea-86bd-48c9-aa91-006833b32fb8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779997374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2779997374
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4090778431
Short name T389
Test name
Test status
Simulation time 25407577709 ps
CPU time 109.09 seconds
Started Jun 02 02:40:45 PM PDT 24
Finished Jun 02 02:42:35 PM PDT 24
Peak memory 214416 kb
Host smart-c33de5ad-22d2-4a45-96ab-861aedd91be8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090778431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.4090778431
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3607494139
Short name T392
Test name
Test status
Simulation time 1327491720 ps
CPU time 20.5 seconds
Started Jun 02 02:40:55 PM PDT 24
Finished Jun 02 02:41:17 PM PDT 24
Peak memory 212332 kb
Host smart-e1ba875c-bb46-4845-9484-094eb946e2b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607494139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3607494139
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.15510118
Short name T407
Test name
Test status
Simulation time 14735885164 ps
CPU time 34.55 seconds
Started Jun 02 02:40:42 PM PDT 24
Finished Jun 02 02:41:17 PM PDT 24
Peak memory 219076 kb
Host smart-69891cc5-44ce-4c3c-99e1-b7b4ff34ea2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15510118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.15510118
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1794443210
Short name T114
Test name
Test status
Simulation time 3947576992 ps
CPU time 170.81 seconds
Started Jun 02 02:40:43 PM PDT 24
Finished Jun 02 02:43:34 PM PDT 24
Peak memory 214780 kb
Host smart-ceddf482-41d3-4ee2-a6c7-1dc20cd6a5ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794443210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1794443210
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3743126150
Short name T369
Test name
Test status
Simulation time 3067906120 ps
CPU time 26.41 seconds
Started Jun 02 02:40:51 PM PDT 24
Finished Jun 02 02:41:18 PM PDT 24
Peak memory 217588 kb
Host smart-3ab4cd66-d0c1-4619-bda7-206ae99fa28a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743126150 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3743126150
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1849867217
Short name T446
Test name
Test status
Simulation time 23738136280 ps
CPU time 26.01 seconds
Started Jun 02 02:40:57 PM PDT 24
Finished Jun 02 02:41:23 PM PDT 24
Peak memory 212112 kb
Host smart-ca8275f3-8488-4c3a-b4ed-aed529749be5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849867217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1849867217
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1987800766
Short name T80
Test name
Test status
Simulation time 4743103440 ps
CPU time 52.31 seconds
Started Jun 02 02:40:52 PM PDT 24
Finished Jun 02 02:41:45 PM PDT 24
Peak memory 214472 kb
Host smart-036caa80-1ba0-40a8-b133-a40f8847fe08
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987800766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1987800766
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3430253469
Short name T423
Test name
Test status
Simulation time 4745485884 ps
CPU time 13.94 seconds
Started Jun 02 02:41:00 PM PDT 24
Finished Jun 02 02:41:15 PM PDT 24
Peak memory 212324 kb
Host smart-0cda8419-7a6a-4faf-96ee-12747b9e3f50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430253469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3430253469
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1705107701
Short name T433
Test name
Test status
Simulation time 832818565 ps
CPU time 17.66 seconds
Started Jun 02 02:40:57 PM PDT 24
Finished Jun 02 02:41:16 PM PDT 24
Peak memory 217396 kb
Host smart-1d557085-fc18-4df9-82d3-77ac601237e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705107701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1705107701
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4258780481
Short name T400
Test name
Test status
Simulation time 2001816384 ps
CPU time 91.76 seconds
Started Jun 02 02:40:52 PM PDT 24
Finished Jun 02 02:42:25 PM PDT 24
Peak memory 214416 kb
Host smart-c2861d7b-ad79-48fa-938e-8a7e6aecd205
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258780481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.4258780481
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2076404216
Short name T436
Test name
Test status
Simulation time 36601733337 ps
CPU time 25.19 seconds
Started Jun 02 02:40:57 PM PDT 24
Finished Jun 02 02:41:23 PM PDT 24
Peak memory 217608 kb
Host smart-0a285c8e-28a8-4aab-bf7e-51fe72050474
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076404216 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2076404216
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.338521384
Short name T91
Test name
Test status
Simulation time 8588502573 ps
CPU time 21.21 seconds
Started Jun 02 02:40:55 PM PDT 24
Finished Jun 02 02:41:17 PM PDT 24
Peak memory 212516 kb
Host smart-5fee385d-c1ca-48b8-a17b-e0b54079caa8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338521384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.338521384
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3922095428
Short name T85
Test name
Test status
Simulation time 80930460281 ps
CPU time 173.84 seconds
Started Jun 02 02:40:53 PM PDT 24
Finished Jun 02 02:43:48 PM PDT 24
Peak memory 215260 kb
Host smart-170ee94b-5eb5-4468-afdf-c7a478c6c8b6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922095428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3922095428
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2235972379
Short name T371
Test name
Test status
Simulation time 5301184208 ps
CPU time 27.87 seconds
Started Jun 02 02:40:57 PM PDT 24
Finished Jun 02 02:41:26 PM PDT 24
Peak memory 212508 kb
Host smart-cf18489e-c73d-4789-beba-021d6bf22b8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235972379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2235972379
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2158642944
Short name T388
Test name
Test status
Simulation time 3333007650 ps
CPU time 22.24 seconds
Started Jun 02 02:40:53 PM PDT 24
Finished Jun 02 02:41:16 PM PDT 24
Peak memory 219324 kb
Host smart-d5eab5bd-8f26-4a74-8b65-a565a3fdd3a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158642944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2158642944
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.641967070
Short name T412
Test name
Test status
Simulation time 918414155 ps
CPU time 14.11 seconds
Started Jun 02 02:41:01 PM PDT 24
Finished Jun 02 02:41:16 PM PDT 24
Peak memory 215196 kb
Host smart-e4b4ea29-089b-47eb-9937-bdb29a0f19b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641967070 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.641967070
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3084309800
Short name T83
Test name
Test status
Simulation time 170657326 ps
CPU time 8.12 seconds
Started Jun 02 02:40:58 PM PDT 24
Finished Jun 02 02:41:07 PM PDT 24
Peak memory 211276 kb
Host smart-629dd8ba-f850-4743-b0af-6034134d3d1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084309800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3084309800
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2688014229
Short name T429
Test name
Test status
Simulation time 112695076517 ps
CPU time 151.19 seconds
Started Jun 02 02:40:51 PM PDT 24
Finished Jun 02 02:43:23 PM PDT 24
Peak memory 215440 kb
Host smart-697dbbb9-f420-4e97-88b1-5573497ce2d6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688014229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2688014229
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3655502680
Short name T439
Test name
Test status
Simulation time 3600713080 ps
CPU time 27.89 seconds
Started Jun 02 02:40:57 PM PDT 24
Finished Jun 02 02:41:26 PM PDT 24
Peak memory 212180 kb
Host smart-bb21c7f3-1e74-4666-a78d-2caa8069477e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655502680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3655502680
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1647568011
Short name T402
Test name
Test status
Simulation time 3861660661 ps
CPU time 33.48 seconds
Started Jun 02 02:41:00 PM PDT 24
Finished Jun 02 02:41:34 PM PDT 24
Peak memory 218696 kb
Host smart-59e6605b-18ed-448c-98db-eac2b2717f5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647568011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1647568011
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2608191148
Short name T424
Test name
Test status
Simulation time 190760008 ps
CPU time 8.91 seconds
Started Jun 02 02:41:00 PM PDT 24
Finished Jun 02 02:41:09 PM PDT 24
Peak memory 217112 kb
Host smart-c829d3eb-4542-48a6-86f1-5c55a38ab86e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608191148 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2608191148
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1797962164
Short name T87
Test name
Test status
Simulation time 4262661793 ps
CPU time 33.1 seconds
Started Jun 02 02:41:01 PM PDT 24
Finished Jun 02 02:41:35 PM PDT 24
Peak memory 211920 kb
Host smart-bbb1e24b-dbdb-47a9-8a04-e6a9857115b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797962164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1797962164
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2645902640
Short name T88
Test name
Test status
Simulation time 11986576803 ps
CPU time 107.4 seconds
Started Jun 02 02:40:58 PM PDT 24
Finished Jun 02 02:42:47 PM PDT 24
Peak memory 214356 kb
Host smart-6460f1ce-d655-4c3f-8b33-60bdc0aa2839
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645902640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2645902640
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3758577725
Short name T386
Test name
Test status
Simulation time 9764440637 ps
CPU time 23.53 seconds
Started Jun 02 02:40:59 PM PDT 24
Finished Jun 02 02:41:23 PM PDT 24
Peak memory 212636 kb
Host smart-f57160dd-4ae5-44c0-ba0c-83c59f883c46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758577725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3758577725
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3623872801
Short name T409
Test name
Test status
Simulation time 3394044652 ps
CPU time 33 seconds
Started Jun 02 02:41:02 PM PDT 24
Finished Jun 02 02:41:35 PM PDT 24
Peak memory 219592 kb
Host smart-3ecd826f-0fd0-4617-8104-c30ed36bd0d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623872801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3623872801
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4193765397
Short name T403
Test name
Test status
Simulation time 3138357975 ps
CPU time 26.23 seconds
Started Jun 02 02:40:59 PM PDT 24
Finished Jun 02 02:41:26 PM PDT 24
Peak memory 214360 kb
Host smart-812c482c-e116-472f-bf20-8578bcea6937
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193765397 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4193765397
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1648848845
Short name T401
Test name
Test status
Simulation time 51924674034 ps
CPU time 32.04 seconds
Started Jun 02 02:40:57 PM PDT 24
Finished Jun 02 02:41:31 PM PDT 24
Peak memory 211952 kb
Host smart-b6cfec51-2d7e-4963-9f4f-f352a8ee270f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648848845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1648848845
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1111261335
Short name T102
Test name
Test status
Simulation time 7515362062 ps
CPU time 104.14 seconds
Started Jun 02 02:41:04 PM PDT 24
Finished Jun 02 02:42:48 PM PDT 24
Peak memory 215628 kb
Host smart-61ae22b4-511e-41ef-8b32-3a2284114934
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111261335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1111261335
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2651438702
Short name T66
Test name
Test status
Simulation time 176529427 ps
CPU time 11.92 seconds
Started Jun 02 02:41:00 PM PDT 24
Finished Jun 02 02:41:12 PM PDT 24
Peak memory 212528 kb
Host smart-a8b51325-049b-456e-b230-eef0499a260f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651438702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2651438702
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4141171544
Short name T378
Test name
Test status
Simulation time 3214382491 ps
CPU time 31.42 seconds
Started Jun 02 02:41:01 PM PDT 24
Finished Jun 02 02:41:33 PM PDT 24
Peak memory 217780 kb
Host smart-e42b1a26-b520-441a-a4b7-4db202869bf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141171544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.4141171544
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3371973745
Short name T110
Test name
Test status
Simulation time 3573832648 ps
CPU time 100.61 seconds
Started Jun 02 02:41:00 PM PDT 24
Finished Jun 02 02:42:41 PM PDT 24
Peak memory 213464 kb
Host smart-1b2de432-9642-47c8-a1e7-2675c8257ea7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371973745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3371973745
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.582783146
Short name T368
Test name
Test status
Simulation time 7167136249 ps
CPU time 29.03 seconds
Started Jun 02 02:41:00 PM PDT 24
Finished Jun 02 02:41:29 PM PDT 24
Peak memory 216336 kb
Host smart-2f524e3f-b31c-42bb-934a-988aa9722333
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582783146 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.582783146
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2630030146
Short name T449
Test name
Test status
Simulation time 2628345091 ps
CPU time 22.98 seconds
Started Jun 02 02:41:00 PM PDT 24
Finished Jun 02 02:41:23 PM PDT 24
Peak memory 211424 kb
Host smart-5a65da7c-ed08-4a53-a918-1378459b05c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630030146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2630030146
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2099710559
Short name T396
Test name
Test status
Simulation time 4071050268 ps
CPU time 84.93 seconds
Started Jun 02 02:40:59 PM PDT 24
Finished Jun 02 02:42:25 PM PDT 24
Peak memory 215536 kb
Host smart-8b73f5c5-16fc-43e2-8711-7148dc30849a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099710559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2099710559
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1062777656
Short name T93
Test name
Test status
Simulation time 2749747224 ps
CPU time 8.34 seconds
Started Jun 02 02:40:57 PM PDT 24
Finished Jun 02 02:41:06 PM PDT 24
Peak memory 211256 kb
Host smart-7ba8402b-45b5-4d4e-a7df-1864a4800cdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062777656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1062777656
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3561555707
Short name T376
Test name
Test status
Simulation time 169159774 ps
CPU time 13.46 seconds
Started Jun 02 02:41:02 PM PDT 24
Finished Jun 02 02:41:16 PM PDT 24
Peak memory 217344 kb
Host smart-a84b7a38-1af8-49e3-9072-917ea5ec1236
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561555707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3561555707
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3635613840
Short name T420
Test name
Test status
Simulation time 4472857590 ps
CPU time 33.66 seconds
Started Jun 02 02:41:06 PM PDT 24
Finished Jun 02 02:41:40 PM PDT 24
Peak memory 216708 kb
Host smart-359d85d5-7403-48dc-9cd7-87365e2e259e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635613840 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3635613840
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2345962422
Short name T419
Test name
Test status
Simulation time 8063022239 ps
CPU time 30.49 seconds
Started Jun 02 02:41:01 PM PDT 24
Finished Jun 02 02:41:32 PM PDT 24
Peak memory 212176 kb
Host smart-b8413551-d630-4f63-a18d-db57a1b47846
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345962422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2345962422
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3998205926
Short name T81
Test name
Test status
Simulation time 10796155261 ps
CPU time 120.86 seconds
Started Jun 02 02:41:02 PM PDT 24
Finished Jun 02 02:43:04 PM PDT 24
Peak memory 215388 kb
Host smart-74711de9-da7b-4686-a3be-0bb42554bca4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998205926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3998205926
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2226090407
Short name T448
Test name
Test status
Simulation time 8745397410 ps
CPU time 33.24 seconds
Started Jun 02 02:41:02 PM PDT 24
Finished Jun 02 02:41:36 PM PDT 24
Peak memory 212676 kb
Host smart-b3859e60-3f4f-46c4-8a5f-0f93812c87f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226090407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2226090407
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.129236232
Short name T382
Test name
Test status
Simulation time 717660505 ps
CPU time 11.43 seconds
Started Jun 02 02:41:00 PM PDT 24
Finished Jun 02 02:41:13 PM PDT 24
Peak memory 217456 kb
Host smart-78b74562-b37e-4c63-a438-893ee4e1dc99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129236232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.129236232
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1871773755
Short name T119
Test name
Test status
Simulation time 4938192296 ps
CPU time 102.78 seconds
Started Jun 02 02:40:58 PM PDT 24
Finished Jun 02 02:42:41 PM PDT 24
Peak memory 214016 kb
Host smart-ed79639d-2cfc-4e8c-a5e1-09dda79c8d65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871773755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1871773755
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.773389481
Short name T417
Test name
Test status
Simulation time 7148317839 ps
CPU time 24.72 seconds
Started Jun 02 02:40:58 PM PDT 24
Finished Jun 02 02:41:24 PM PDT 24
Peak memory 217760 kb
Host smart-d700692f-7d42-4f59-b4b3-b7a0beae5875
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773389481 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.773389481
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3013470838
Short name T381
Test name
Test status
Simulation time 3598480322 ps
CPU time 19.64 seconds
Started Jun 02 02:41:00 PM PDT 24
Finished Jun 02 02:41:21 PM PDT 24
Peak memory 211908 kb
Host smart-9dfef2b0-a788-48db-beec-dd1ef602196f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013470838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3013470838
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3962695128
Short name T452
Test name
Test status
Simulation time 693216142 ps
CPU time 36.97 seconds
Started Jun 02 02:40:57 PM PDT 24
Finished Jun 02 02:41:35 PM PDT 24
Peak memory 213700 kb
Host smart-ad3fdb5c-f594-4019-8ce6-a796e51655fc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962695128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3962695128
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.486618762
Short name T432
Test name
Test status
Simulation time 14435557024 ps
CPU time 27.73 seconds
Started Jun 02 02:40:58 PM PDT 24
Finished Jun 02 02:41:27 PM PDT 24
Peak memory 212820 kb
Host smart-bafece69-c40c-4549-80a6-3287fada436e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486618762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.486618762
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1673478436
Short name T51
Test name
Test status
Simulation time 660195988 ps
CPU time 12.94 seconds
Started Jun 02 02:41:02 PM PDT 24
Finished Jun 02 02:41:16 PM PDT 24
Peak memory 219504 kb
Host smart-9a1d0b97-964c-46df-b2fe-06edb04152a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673478436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1673478436
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.140487960
Short name T111
Test name
Test status
Simulation time 9970714925 ps
CPU time 86.51 seconds
Started Jun 02 02:41:03 PM PDT 24
Finished Jun 02 02:42:30 PM PDT 24
Peak memory 213756 kb
Host smart-94a5d331-dc16-429c-842b-edc6b4c6d11c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140487960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.140487960
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2120479024
Short name T428
Test name
Test status
Simulation time 5138236073 ps
CPU time 22.95 seconds
Started Jun 02 02:41:06 PM PDT 24
Finished Jun 02 02:41:29 PM PDT 24
Peak memory 214716 kb
Host smart-c758234d-52d0-40b1-9695-fc6ba5348849
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120479024 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2120479024
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.505525306
Short name T391
Test name
Test status
Simulation time 4111953496 ps
CPU time 21.09 seconds
Started Jun 02 02:41:05 PM PDT 24
Finished Jun 02 02:41:26 PM PDT 24
Peak memory 211672 kb
Host smart-c20a96d6-ec97-491c-a92c-719ff2084c02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505525306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.505525306
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2499842595
Short name T96
Test name
Test status
Simulation time 339244930 ps
CPU time 8.47 seconds
Started Jun 02 02:41:05 PM PDT 24
Finished Jun 02 02:41:15 PM PDT 24
Peak memory 211272 kb
Host smart-226aa980-a56a-4ab9-af32-a2f8a369dbc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499842595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2499842595
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2322528549
Short name T62
Test name
Test status
Simulation time 7102786595 ps
CPU time 15.89 seconds
Started Jun 02 02:41:01 PM PDT 24
Finished Jun 02 02:41:18 PM PDT 24
Peak memory 217836 kb
Host smart-243b42a3-b8fc-46a3-9218-8d517d01f433
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322528549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2322528549
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3209016153
Short name T106
Test name
Test status
Simulation time 2910823574 ps
CPU time 167.68 seconds
Started Jun 02 02:40:57 PM PDT 24
Finished Jun 02 02:43:46 PM PDT 24
Peak memory 213764 kb
Host smart-fbd06f03-6e79-4b47-ac05-6871d23528de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209016153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3209016153
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3003595532
Short name T411
Test name
Test status
Simulation time 15769419108 ps
CPU time 30.23 seconds
Started Jun 02 02:41:02 PM PDT 24
Finished Jun 02 02:41:33 PM PDT 24
Peak memory 215460 kb
Host smart-354e8f66-cdfa-4ca7-8476-b8f243d547bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003595532 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3003595532
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2002852271
Short name T72
Test name
Test status
Simulation time 13607997693 ps
CPU time 29.31 seconds
Started Jun 02 02:41:02 PM PDT 24
Finished Jun 02 02:41:32 PM PDT 24
Peak memory 212344 kb
Host smart-4ac0113c-fdab-48bb-8e18-ff8ba651b90d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002852271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2002852271
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2365805220
Short name T398
Test name
Test status
Simulation time 3127876818 ps
CPU time 37.76 seconds
Started Jun 02 02:41:05 PM PDT 24
Finished Jun 02 02:41:43 PM PDT 24
Peak memory 213712 kb
Host smart-b2dfd925-086d-44f7-bee7-8e53c779715b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365805220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2365805220
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3820905923
Short name T443
Test name
Test status
Simulation time 2983810410 ps
CPU time 21.68 seconds
Started Jun 02 02:41:09 PM PDT 24
Finished Jun 02 02:41:31 PM PDT 24
Peak memory 212428 kb
Host smart-0e4c3e81-9a82-4bcd-ba1b-9f465ad08f3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820905923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3820905923
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4089431194
Short name T384
Test name
Test status
Simulation time 2637673587 ps
CPU time 27.64 seconds
Started Jun 02 02:41:04 PM PDT 24
Finished Jun 02 02:41:32 PM PDT 24
Peak memory 217164 kb
Host smart-4b1ad33d-a0dc-4c4d-a47c-47dad8180e40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089431194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.4089431194
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2124730739
Short name T113
Test name
Test status
Simulation time 922577973 ps
CPU time 156.39 seconds
Started Jun 02 02:41:03 PM PDT 24
Finished Jun 02 02:43:40 PM PDT 24
Peak memory 213924 kb
Host smart-57b025a7-b2c9-4ba9-b5d4-e4b0b521a393
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124730739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2124730739
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2510366079
Short name T99
Test name
Test status
Simulation time 9852035584 ps
CPU time 20.1 seconds
Started Jun 02 02:40:55 PM PDT 24
Finished Jun 02 02:41:16 PM PDT 24
Peak memory 211156 kb
Host smart-e6272b6f-b356-4061-a4a8-3afc57db8a6a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510366079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2510366079
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.817686334
Short name T395
Test name
Test status
Simulation time 3864687237 ps
CPU time 30.51 seconds
Started Jun 02 02:40:50 PM PDT 24
Finished Jun 02 02:41:21 PM PDT 24
Peak memory 211332 kb
Host smart-ea6fbeac-b8a6-4520-b224-0f40a1f04b06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817686334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.817686334
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4074325785
Short name T64
Test name
Test status
Simulation time 9860387552 ps
CPU time 27.95 seconds
Started Jun 02 02:40:46 PM PDT 24
Finished Jun 02 02:41:15 PM PDT 24
Peak memory 212020 kb
Host smart-fae6c01c-268e-46eb-bbe2-fd7f0e73d2de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074325785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.4074325785
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.670703417
Short name T418
Test name
Test status
Simulation time 3435528017 ps
CPU time 27.28 seconds
Started Jun 02 02:40:47 PM PDT 24
Finished Jun 02 02:41:15 PM PDT 24
Peak memory 217432 kb
Host smart-b01e06fe-e32a-4421-b7ce-54948070537f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670703417 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.670703417
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4147694033
Short name T453
Test name
Test status
Simulation time 16336624665 ps
CPU time 25.24 seconds
Started Jun 02 02:40:55 PM PDT 24
Finished Jun 02 02:41:21 PM PDT 24
Peak memory 211588 kb
Host smart-fff9f33b-fcb4-4500-81a8-0e80f539cdc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147694033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.4147694033
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1352479406
Short name T367
Test name
Test status
Simulation time 6714047178 ps
CPU time 17.39 seconds
Started Jun 02 02:40:44 PM PDT 24
Finished Jun 02 02:41:02 PM PDT 24
Peak memory 211224 kb
Host smart-be5e4b97-2dc2-45b6-9352-5c3d7af5bb88
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352479406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1352479406
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.937218819
Short name T416
Test name
Test status
Simulation time 24422847742 ps
CPU time 23.73 seconds
Started Jun 02 02:40:45 PM PDT 24
Finished Jun 02 02:41:09 PM PDT 24
Peak memory 211268 kb
Host smart-2644c21a-ff49-4756-a7a1-25963abcd0dc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937218819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
937218819
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1994713031
Short name T82
Test name
Test status
Simulation time 32852006279 ps
CPU time 90.91 seconds
Started Jun 02 02:40:46 PM PDT 24
Finished Jun 02 02:42:18 PM PDT 24
Peak memory 214416 kb
Host smart-2b9f5e93-0a25-4bfa-91a4-018d3243a3c3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994713031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1994713031
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3228948981
Short name T68
Test name
Test status
Simulation time 4964443440 ps
CPU time 20.12 seconds
Started Jun 02 02:40:44 PM PDT 24
Finished Jun 02 02:41:05 PM PDT 24
Peak memory 212620 kb
Host smart-28250631-1a6e-43aa-a57d-906b35065780
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228948981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3228948981
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1707528457
Short name T50
Test name
Test status
Simulation time 14458771630 ps
CPU time 33.42 seconds
Started Jun 02 02:40:46 PM PDT 24
Finished Jun 02 02:41:20 PM PDT 24
Peak memory 218728 kb
Host smart-f7a30e93-79fe-4e2f-b831-9aa3aa3d2f52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707528457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1707528457
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.388148981
Short name T117
Test name
Test status
Simulation time 8987840079 ps
CPU time 100.55 seconds
Started Jun 02 02:40:45 PM PDT 24
Finished Jun 02 02:42:26 PM PDT 24
Peak memory 212908 kb
Host smart-737c209e-705f-4b68-927c-091ab091f3a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388148981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.388148981
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2498487720
Short name T90
Test name
Test status
Simulation time 167696656 ps
CPU time 8.43 seconds
Started Jun 02 02:40:44 PM PDT 24
Finished Jun 02 02:40:53 PM PDT 24
Peak memory 211188 kb
Host smart-7a4b2ce7-a821-4e2d-91a7-f0064f2d0187
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498487720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2498487720
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1170513415
Short name T379
Test name
Test status
Simulation time 1268250171 ps
CPU time 13.63 seconds
Started Jun 02 02:40:48 PM PDT 24
Finished Jun 02 02:41:02 PM PDT 24
Peak memory 211248 kb
Host smart-50c34277-8d0a-4f4c-8e04-88e31f8a69ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170513415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1170513415
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.625163951
Short name T67
Test name
Test status
Simulation time 7907505278 ps
CPU time 28.12 seconds
Started Jun 02 02:40:52 PM PDT 24
Finished Jun 02 02:41:21 PM PDT 24
Peak memory 212332 kb
Host smart-bb9ea501-8a12-4871-b238-c0c3b110c651
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625163951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.625163951
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3836554811
Short name T405
Test name
Test status
Simulation time 2128060738 ps
CPU time 21.07 seconds
Started Jun 02 02:40:49 PM PDT 24
Finished Jun 02 02:41:11 PM PDT 24
Peak memory 215984 kb
Host smart-fda46c4d-5933-408f-9466-6389506f468f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836554811 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3836554811
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3139422419
Short name T438
Test name
Test status
Simulation time 170948964 ps
CPU time 8.26 seconds
Started Jun 02 02:40:44 PM PDT 24
Finished Jun 02 02:40:53 PM PDT 24
Peak memory 211260 kb
Host smart-6a001e3f-cdc8-4bef-9459-9ae6f829adaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139422419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3139422419
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2786147598
Short name T380
Test name
Test status
Simulation time 20452670071 ps
CPU time 22.01 seconds
Started Jun 02 02:40:55 PM PDT 24
Finished Jun 02 02:41:18 PM PDT 24
Peak memory 211152 kb
Host smart-2337a838-a921-419e-882b-f137aac9cbd8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786147598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2786147598
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.983763459
Short name T393
Test name
Test status
Simulation time 1060848574 ps
CPU time 15.2 seconds
Started Jun 02 02:40:45 PM PDT 24
Finished Jun 02 02:41:01 PM PDT 24
Peak memory 211144 kb
Host smart-aa925376-12ad-4a8b-9a3d-c986f5668380
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983763459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
983763459
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3290750088
Short name T63
Test name
Test status
Simulation time 65690272808 ps
CPU time 130.69 seconds
Started Jun 02 02:40:48 PM PDT 24
Finished Jun 02 02:42:59 PM PDT 24
Peak memory 213372 kb
Host smart-08dba487-a766-48a9-9666-861c143209a4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290750088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3290750088
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3110404071
Short name T410
Test name
Test status
Simulation time 3751164839 ps
CPU time 17.08 seconds
Started Jun 02 02:40:50 PM PDT 24
Finished Jun 02 02:41:08 PM PDT 24
Peak memory 212280 kb
Host smart-cef053c0-ed67-4489-a538-1b3b3d597569
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110404071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3110404071
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3986587608
Short name T372
Test name
Test status
Simulation time 2336272667 ps
CPU time 25.68 seconds
Started Jun 02 02:40:48 PM PDT 24
Finished Jun 02 02:41:15 PM PDT 24
Peak memory 217620 kb
Host smart-0c22bdfc-9757-42e9-9058-114e1f63c14d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986587608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3986587608
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1781973711
Short name T49
Test name
Test status
Simulation time 563173203 ps
CPU time 150.64 seconds
Started Jun 02 02:40:55 PM PDT 24
Finished Jun 02 02:43:26 PM PDT 24
Peak memory 214064 kb
Host smart-46df5739-4be8-4d8d-8432-ea7ff5016f33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781973711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1781973711
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.278158124
Short name T375
Test name
Test status
Simulation time 4107049194 ps
CPU time 31.75 seconds
Started Jun 02 02:40:48 PM PDT 24
Finished Jun 02 02:41:21 PM PDT 24
Peak memory 211692 kb
Host smart-ea09237a-1661-4a1d-ae70-67e4937565d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278158124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.278158124
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4188160484
Short name T427
Test name
Test status
Simulation time 3448089246 ps
CPU time 27.87 seconds
Started Jun 02 02:40:51 PM PDT 24
Finished Jun 02 02:41:19 PM PDT 24
Peak memory 211760 kb
Host smart-8ec63a1c-920c-4d3a-90e5-3fe25c5667ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188160484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.4188160484
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.127458636
Short name T374
Test name
Test status
Simulation time 3437483951 ps
CPU time 32.18 seconds
Started Jun 02 02:40:46 PM PDT 24
Finished Jun 02 02:41:19 PM PDT 24
Peak memory 211708 kb
Host smart-e7f22e04-e390-48c4-84e7-5de9c745ae61
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127458636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.127458636
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1198721354
Short name T406
Test name
Test status
Simulation time 6395112880 ps
CPU time 18.25 seconds
Started Jun 02 02:40:53 PM PDT 24
Finished Jun 02 02:41:12 PM PDT 24
Peak memory 217588 kb
Host smart-13f60666-f81b-44af-bcf0-3beebb7bc64d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198721354 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1198721354
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.877735976
Short name T92
Test name
Test status
Simulation time 4837177798 ps
CPU time 21.98 seconds
Started Jun 02 02:40:44 PM PDT 24
Finished Jun 02 02:41:07 PM PDT 24
Peak memory 212548 kb
Host smart-8bf4a74f-dc58-456c-89f9-3a92304078ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877735976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.877735976
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.619225499
Short name T450
Test name
Test status
Simulation time 332350714 ps
CPU time 8.42 seconds
Started Jun 02 02:40:50 PM PDT 24
Finished Jun 02 02:40:59 PM PDT 24
Peak memory 211084 kb
Host smart-b81884d4-01bc-4560-a18c-508c084868af
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619225499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.619225499
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2379189659
Short name T440
Test name
Test status
Simulation time 16732284643 ps
CPU time 32.29 seconds
Started Jun 02 02:40:46 PM PDT 24
Finished Jun 02 02:41:19 PM PDT 24
Peak memory 211232 kb
Host smart-e8090c98-3075-4f82-99e4-b2c83fee3cc2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379189659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2379189659
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.979908628
Short name T445
Test name
Test status
Simulation time 6801755033 ps
CPU time 30.68 seconds
Started Jun 02 02:40:45 PM PDT 24
Finished Jun 02 02:41:16 PM PDT 24
Peak memory 212568 kb
Host smart-c29f1d1d-8097-4c9d-a732-314b823da8e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979908628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.979908628
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1545854753
Short name T451
Test name
Test status
Simulation time 6973414889 ps
CPU time 36.74 seconds
Started Jun 02 02:40:55 PM PDT 24
Finished Jun 02 02:41:32 PM PDT 24
Peak memory 217444 kb
Host smart-28cc4dd8-8078-4936-b0b0-c702e69b98b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545854753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1545854753
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.478576417
Short name T115
Test name
Test status
Simulation time 3803908286 ps
CPU time 161.77 seconds
Started Jun 02 02:40:47 PM PDT 24
Finished Jun 02 02:43:29 PM PDT 24
Peak memory 213900 kb
Host smart-ff9cf4bc-0d5e-48e5-8449-0775f2939833
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478576417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.478576417
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1996943957
Short name T441
Test name
Test status
Simulation time 1967823035 ps
CPU time 20.3 seconds
Started Jun 02 02:40:51 PM PDT 24
Finished Jun 02 02:41:12 PM PDT 24
Peak memory 216912 kb
Host smart-7cef9445-ee55-436e-8746-6fe9f015c6c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996943957 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1996943957
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.435765361
Short name T431
Test name
Test status
Simulation time 1056670016 ps
CPU time 10.97 seconds
Started Jun 02 02:40:51 PM PDT 24
Finished Jun 02 02:41:03 PM PDT 24
Peak memory 211800 kb
Host smart-94835382-6dc5-46fe-bac5-4151bce8a3fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435765361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.435765361
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2526614448
Short name T70
Test name
Test status
Simulation time 47312436230 ps
CPU time 198.74 seconds
Started Jun 02 02:40:45 PM PDT 24
Finished Jun 02 02:44:05 PM PDT 24
Peak memory 215092 kb
Host smart-7eb0f935-3070-4196-aba2-838884563b87
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526614448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2526614448
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3096703974
Short name T435
Test name
Test status
Simulation time 28775466007 ps
CPU time 23.06 seconds
Started Jun 02 02:40:54 PM PDT 24
Finished Jun 02 02:41:18 PM PDT 24
Peak memory 212724 kb
Host smart-98164fe6-05bf-44da-917d-10627cacf8b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096703974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3096703974
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2397799593
Short name T444
Test name
Test status
Simulation time 17575010874 ps
CPU time 34.27 seconds
Started Jun 02 02:40:45 PM PDT 24
Finished Jun 02 02:41:20 PM PDT 24
Peak memory 217804 kb
Host smart-f4f2e7ec-03d9-47d1-800c-055b9024dfe9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397799593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2397799593
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2868703097
Short name T108
Test name
Test status
Simulation time 1129287415 ps
CPU time 153.93 seconds
Started Jun 02 02:40:47 PM PDT 24
Finished Jun 02 02:43:21 PM PDT 24
Peak memory 213952 kb
Host smart-e2783143-8e85-46c1-9303-4a95aea31362
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868703097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2868703097
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.750097774
Short name T425
Test name
Test status
Simulation time 2115242227 ps
CPU time 21.84 seconds
Started Jun 02 02:40:57 PM PDT 24
Finished Jun 02 02:41:20 PM PDT 24
Peak memory 216924 kb
Host smart-cc9761b1-b1ae-4f65-8825-344c6740b65c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750097774 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.750097774
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3912424168
Short name T430
Test name
Test status
Simulation time 4084099990 ps
CPU time 24.01 seconds
Started Jun 02 02:40:51 PM PDT 24
Finished Jun 02 02:41:15 PM PDT 24
Peak memory 211688 kb
Host smart-cb017c43-9f68-4f04-944c-68d8b736b1b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912424168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3912424168
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3562559691
Short name T103
Test name
Test status
Simulation time 50146771897 ps
CPU time 193.11 seconds
Started Jun 02 02:40:54 PM PDT 24
Finished Jun 02 02:44:08 PM PDT 24
Peak memory 215228 kb
Host smart-0d15269b-1cca-4cc0-b2cc-0a9daf7a14ea
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562559691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3562559691
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.220928066
Short name T69
Test name
Test status
Simulation time 949899376 ps
CPU time 13.95 seconds
Started Jun 02 02:40:53 PM PDT 24
Finished Jun 02 02:41:07 PM PDT 24
Peak memory 211172 kb
Host smart-a45ea247-0684-4559-979b-bbc1d7d39ba8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220928066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.220928066
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2493479034
Short name T415
Test name
Test status
Simulation time 1237679029 ps
CPU time 22.23 seconds
Started Jun 02 02:40:52 PM PDT 24
Finished Jun 02 02:41:15 PM PDT 24
Peak memory 218764 kb
Host smart-9880473a-69cf-4f78-bca3-7bf3ef62fdae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493479034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2493479034
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2693241124
Short name T116
Test name
Test status
Simulation time 3229949924 ps
CPU time 171.79 seconds
Started Jun 02 02:40:52 PM PDT 24
Finished Jun 02 02:43:45 PM PDT 24
Peak memory 214120 kb
Host smart-64e1bf4a-42ce-45d4-bfc6-5f10d3e26773
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693241124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2693241124
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2020067303
Short name T370
Test name
Test status
Simulation time 15180676707 ps
CPU time 30.93 seconds
Started Jun 02 02:40:53 PM PDT 24
Finished Jun 02 02:41:25 PM PDT 24
Peak memory 219808 kb
Host smart-eb4ef6d8-0a6f-45d2-902e-b30f29a4db8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020067303 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2020067303
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2210484921
Short name T399
Test name
Test status
Simulation time 3908098321 ps
CPU time 20.39 seconds
Started Jun 02 02:40:54 PM PDT 24
Finished Jun 02 02:41:15 PM PDT 24
Peak memory 211876 kb
Host smart-a20bf546-c03e-4158-bf12-c495bef0ee99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210484921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2210484921
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3689516071
Short name T373
Test name
Test status
Simulation time 22608488473 ps
CPU time 118.56 seconds
Started Jun 02 02:40:55 PM PDT 24
Finished Jun 02 02:42:55 PM PDT 24
Peak memory 213384 kb
Host smart-9b9bd471-15fb-42e1-8ce9-4aec6cb56ce6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689516071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3689516071
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2205888174
Short name T404
Test name
Test status
Simulation time 5217543547 ps
CPU time 17.75 seconds
Started Jun 02 02:40:53 PM PDT 24
Finished Jun 02 02:41:12 PM PDT 24
Peak memory 212504 kb
Host smart-663862fb-b87b-49df-9951-9c11b6729354
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205888174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2205888174
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3371189239
Short name T414
Test name
Test status
Simulation time 3340565675 ps
CPU time 21.26 seconds
Started Jun 02 02:40:51 PM PDT 24
Finished Jun 02 02:41:13 PM PDT 24
Peak memory 216168 kb
Host smart-ea1eb8fc-b962-4477-8e22-3db22962062d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371189239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3371189239
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3891513124
Short name T105
Test name
Test status
Simulation time 520379122 ps
CPU time 80.23 seconds
Started Jun 02 02:40:51 PM PDT 24
Finished Jun 02 02:42:12 PM PDT 24
Peak memory 213460 kb
Host smart-03f3e99f-e314-4a9c-9e50-66edefb63d8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891513124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3891513124
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1124680022
Short name T52
Test name
Test status
Simulation time 6256616626 ps
CPU time 12.26 seconds
Started Jun 02 02:40:57 PM PDT 24
Finished Jun 02 02:41:10 PM PDT 24
Peak memory 216044 kb
Host smart-1c042077-07e2-41ea-a58a-18b7e13c8be6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124680022 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1124680022
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1025033769
Short name T71
Test name
Test status
Simulation time 345623665 ps
CPU time 8.34 seconds
Started Jun 02 02:40:52 PM PDT 24
Finished Jun 02 02:41:01 PM PDT 24
Peak memory 211240 kb
Host smart-432820c7-eb50-4b0e-bfee-100064992cf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025033769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1025033769
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1666773433
Short name T86
Test name
Test status
Simulation time 13175229705 ps
CPU time 114.33 seconds
Started Jun 02 02:40:59 PM PDT 24
Finished Jun 02 02:42:54 PM PDT 24
Peak memory 214444 kb
Host smart-2dde2305-eac6-4e77-9ee7-439532a564b6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666773433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1666773433
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2108331457
Short name T95
Test name
Test status
Simulation time 721518102 ps
CPU time 12.16 seconds
Started Jun 02 02:41:00 PM PDT 24
Finished Jun 02 02:41:12 PM PDT 24
Peak memory 212252 kb
Host smart-1650b4de-7f65-4010-86ab-e4594f81d990
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108331457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2108331457
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2666895573
Short name T377
Test name
Test status
Simulation time 533298411 ps
CPU time 11.39 seconds
Started Jun 02 02:40:56 PM PDT 24
Finished Jun 02 02:41:08 PM PDT 24
Peak memory 217304 kb
Host smart-78866816-ac16-4164-b804-3aa10581e353
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666895573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2666895573
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1326973752
Short name T55
Test name
Test status
Simulation time 38182568572 ps
CPU time 102.46 seconds
Started Jun 02 02:40:56 PM PDT 24
Finished Jun 02 02:42:39 PM PDT 24
Peak memory 214552 kb
Host smart-f09b71fe-1703-4ccb-a260-a4e704e5936b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326973752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1326973752
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2668608230
Short name T397
Test name
Test status
Simulation time 4856275715 ps
CPU time 17.34 seconds
Started Jun 02 02:40:56 PM PDT 24
Finished Jun 02 02:41:14 PM PDT 24
Peak memory 214164 kb
Host smart-79d9fd99-0197-42d7-9822-ea52f674008e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668608230 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2668608230
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2979614063
Short name T434
Test name
Test status
Simulation time 971173226 ps
CPU time 8.31 seconds
Started Jun 02 02:41:00 PM PDT 24
Finished Jun 02 02:41:09 PM PDT 24
Peak memory 211256 kb
Host smart-71848467-f1d8-4b80-85fa-e691f1011e16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979614063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2979614063
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.921901735
Short name T104
Test name
Test status
Simulation time 22919527996 ps
CPU time 70.56 seconds
Started Jun 02 02:41:00 PM PDT 24
Finished Jun 02 02:42:11 PM PDT 24
Peak memory 213408 kb
Host smart-9bc42ae0-e3f3-46fb-a7db-d40a23de9593
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921901735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.921901735
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.592286208
Short name T408
Test name
Test status
Simulation time 3235272874 ps
CPU time 26.53 seconds
Started Jun 02 02:40:53 PM PDT 24
Finished Jun 02 02:41:20 PM PDT 24
Peak memory 212496 kb
Host smart-bdcf2e0b-0cca-45d1-8c30-7164bee78a95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592286208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.592286208
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2694255786
Short name T447
Test name
Test status
Simulation time 6909055213 ps
CPU time 30.88 seconds
Started Jun 02 02:40:56 PM PDT 24
Finished Jun 02 02:41:28 PM PDT 24
Peak memory 217784 kb
Host smart-b64f6e54-b1b9-44c2-9063-c9bf68f09db6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694255786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2694255786
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2215484433
Short name T422
Test name
Test status
Simulation time 8429491975 ps
CPU time 89.88 seconds
Started Jun 02 02:40:50 PM PDT 24
Finished Jun 02 02:42:21 PM PDT 24
Peak memory 213692 kb
Host smart-5c30a675-3468-4df9-817f-aa48dadfa3b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215484433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2215484433
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3449059915
Short name T135
Test name
Test status
Simulation time 513606750 ps
CPU time 11.72 seconds
Started Jun 02 02:41:18 PM PDT 24
Finished Jun 02 02:41:31 PM PDT 24
Peak memory 211208 kb
Host smart-3119ae7e-8148-4c7f-b643-678a88960604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449059915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3449059915
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2078418976
Short name T196
Test name
Test status
Simulation time 40041601958 ps
CPU time 553.86 seconds
Started Jun 02 02:41:03 PM PDT 24
Finished Jun 02 02:50:17 PM PDT 24
Peak memory 229000 kb
Host smart-041ea4a1-b659-42cb-95dc-b9bf61d15ff1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078418976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2078418976
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3977112603
Short name T360
Test name
Test status
Simulation time 1377363460 ps
CPU time 19.84 seconds
Started Jun 02 02:41:05 PM PDT 24
Finished Jun 02 02:41:25 PM PDT 24
Peak memory 214608 kb
Host smart-33449334-5a1c-4ee4-b22b-a72d110c7eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977112603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3977112603
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.4022053302
Short name T100
Test name
Test status
Simulation time 5650527244 ps
CPU time 26.01 seconds
Started Jun 02 02:41:07 PM PDT 24
Finished Jun 02 02:41:33 PM PDT 24
Peak memory 212856 kb
Host smart-a0a44b50-9211-471b-91a6-3883f1ff6c34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4022053302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.4022053302
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2190831650
Short name T31
Test name
Test status
Simulation time 7948948864 ps
CPU time 242.1 seconds
Started Jun 02 02:41:05 PM PDT 24
Finished Jun 02 02:45:08 PM PDT 24
Peak memory 238468 kb
Host smart-9bf27a32-da17-4b3d-9064-d1c9730746d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190831650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2190831650
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2044120177
Short name T314
Test name
Test status
Simulation time 2594036349 ps
CPU time 35.66 seconds
Started Jun 02 02:41:07 PM PDT 24
Finished Jun 02 02:41:43 PM PDT 24
Peak memory 215772 kb
Host smart-9345a81c-180d-41d3-8d38-cdf5a8ab4055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044120177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2044120177
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1744229014
Short name T53
Test name
Test status
Simulation time 10797331477 ps
CPU time 94.62 seconds
Started Jun 02 02:41:04 PM PDT 24
Finished Jun 02 02:42:39 PM PDT 24
Peak memory 219380 kb
Host smart-7d2d5619-1b65-447e-b985-a1fd84def321
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744229014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1744229014
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1498328123
Short name T44
Test name
Test status
Simulation time 634764375927 ps
CPU time 735.22 seconds
Started Jun 02 02:41:03 PM PDT 24
Finished Jun 02 02:53:18 PM PDT 24
Peak memory 237292 kb
Host smart-ae4cadf4-adb7-4e20-907c-805c0a67e060
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498328123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1498328123
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.960046365
Short name T348
Test name
Test status
Simulation time 25897276009 ps
CPU time 59.25 seconds
Started Jun 02 02:41:05 PM PDT 24
Finished Jun 02 02:42:05 PM PDT 24
Peak memory 215040 kb
Host smart-d1d8eb25-11f0-48e1-892e-ceb2b213cdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960046365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.960046365
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.795158778
Short name T219
Test name
Test status
Simulation time 183979899 ps
CPU time 10.42 seconds
Started Jun 02 02:41:05 PM PDT 24
Finished Jun 02 02:41:16 PM PDT 24
Peak memory 212332 kb
Host smart-32d4dd44-71e1-4d0f-a044-951a3d7db513
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=795158778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.795158778
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1695174817
Short name T33
Test name
Test status
Simulation time 3567803568 ps
CPU time 252.87 seconds
Started Jun 02 02:41:09 PM PDT 24
Finished Jun 02 02:45:22 PM PDT 24
Peak memory 236828 kb
Host smart-c6666550-09f1-45e8-b71b-c493046f549d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695174817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1695174817
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.433668770
Short name T258
Test name
Test status
Simulation time 6144815207 ps
CPU time 40.7 seconds
Started Jun 02 02:41:04 PM PDT 24
Finished Jun 02 02:41:45 PM PDT 24
Peak memory 217400 kb
Host smart-36ad2290-4972-4c16-9a92-27ea919ad09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433668770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.433668770
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1581075888
Short name T74
Test name
Test status
Simulation time 1424795963 ps
CPU time 45.46 seconds
Started Jun 02 02:41:12 PM PDT 24
Finished Jun 02 02:41:58 PM PDT 24
Peak memory 219280 kb
Host smart-508a9913-3772-4379-9f7e-8107fc1df5ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581075888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1581075888
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1046006908
Short name T335
Test name
Test status
Simulation time 174442775 ps
CPU time 8.33 seconds
Started Jun 02 02:41:25 PM PDT 24
Finished Jun 02 02:41:34 PM PDT 24
Peak memory 211260 kb
Host smart-85d6f536-50e6-40cb-95a3-a6ff885e53f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046006908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1046006908
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.187495378
Short name T280
Test name
Test status
Simulation time 61664602498 ps
CPU time 483.44 seconds
Started Jun 02 02:41:19 PM PDT 24
Finished Jun 02 02:49:24 PM PDT 24
Peak memory 230556 kb
Host smart-8ce7c4ad-dce9-4fab-a14c-61e914090771
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187495378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.187495378
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.4012802812
Short name T180
Test name
Test status
Simulation time 3973947530 ps
CPU time 22.66 seconds
Started Jun 02 02:41:19 PM PDT 24
Finished Jun 02 02:41:43 PM PDT 24
Peak memory 211348 kb
Host smart-7595fb3a-38bf-4fda-9013-986ef665f5cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4012802812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.4012802812
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.62852144
Short name T333
Test name
Test status
Simulation time 3695751276 ps
CPU time 41.86 seconds
Started Jun 02 02:41:18 PM PDT 24
Finished Jun 02 02:42:01 PM PDT 24
Peak memory 217472 kb
Host smart-716e3067-1fbd-456e-86fa-8108e3dce48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62852144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.62852144
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1121218396
Short name T125
Test name
Test status
Simulation time 6361579473 ps
CPU time 63.67 seconds
Started Jun 02 02:41:18 PM PDT 24
Finished Jun 02 02:42:23 PM PDT 24
Peak memory 218228 kb
Host smart-566d1293-ea36-4bb3-b755-ad7155383bb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121218396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1121218396
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2817700551
Short name T149
Test name
Test status
Simulation time 750634175 ps
CPU time 8.38 seconds
Started Jun 02 02:41:23 PM PDT 24
Finished Jun 02 02:41:32 PM PDT 24
Peak memory 211308 kb
Host smart-d7a04f78-8b80-4b2d-bebd-bad1a95183c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817700551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2817700551
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.266717011
Short name T120
Test name
Test status
Simulation time 18265324911 ps
CPU time 200.11 seconds
Started Jun 02 02:41:30 PM PDT 24
Finished Jun 02 02:44:51 PM PDT 24
Peak memory 238092 kb
Host smart-e0d0852e-3a30-4275-aa06-772e8418dee5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266717011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.266717011
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3025113714
Short name T358
Test name
Test status
Simulation time 4806070109 ps
CPU time 28.4 seconds
Started Jun 02 02:41:26 PM PDT 24
Finished Jun 02 02:41:55 PM PDT 24
Peak memory 211708 kb
Host smart-8cb86920-d0fa-4c0e-930e-9747265ca9db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3025113714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3025113714
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2771286031
Short name T233
Test name
Test status
Simulation time 1456970689 ps
CPU time 20.51 seconds
Started Jun 02 02:41:23 PM PDT 24
Finished Jun 02 02:41:44 PM PDT 24
Peak memory 217324 kb
Host smart-18dda75f-e93f-43f9-9233-1a20a9f59323
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771286031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2771286031
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3195785439
Short name T162
Test name
Test status
Simulation time 3269852253 ps
CPU time 28.33 seconds
Started Jun 02 02:41:30 PM PDT 24
Finished Jun 02 02:41:59 PM PDT 24
Peak memory 211852 kb
Host smart-d7cd7427-40b1-4c0c-818d-360406fd73e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195785439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3195785439
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2034438979
Short name T320
Test name
Test status
Simulation time 43560389071 ps
CPU time 551.19 seconds
Started Jun 02 02:41:25 PM PDT 24
Finished Jun 02 02:50:37 PM PDT 24
Peak memory 230640 kb
Host smart-18a87799-203f-47ca-ab13-e117461b56ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034438979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2034438979
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.4264312031
Short name T292
Test name
Test status
Simulation time 21672376496 ps
CPU time 68.34 seconds
Started Jun 02 02:41:24 PM PDT 24
Finished Jun 02 02:42:33 PM PDT 24
Peak memory 214124 kb
Host smart-d8dc9878-d725-448e-82b1-0aa9efe5f5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264312031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.4264312031
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3628789263
Short name T145
Test name
Test status
Simulation time 36635489648 ps
CPU time 29.26 seconds
Started Jun 02 02:41:34 PM PDT 24
Finished Jun 02 02:42:05 PM PDT 24
Peak memory 211788 kb
Host smart-4ad779c4-a825-4e05-a17e-138b188e87f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3628789263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3628789263
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1915206446
Short name T75
Test name
Test status
Simulation time 15520843143 ps
CPU time 41.15 seconds
Started Jun 02 02:41:24 PM PDT 24
Finished Jun 02 02:42:06 PM PDT 24
Peak memory 217612 kb
Host smart-7f5a1501-f5e1-4fe0-b1f1-613e0912d258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915206446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1915206446
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.4225930120
Short name T131
Test name
Test status
Simulation time 10777992401 ps
CPU time 117.46 seconds
Started Jun 02 02:41:24 PM PDT 24
Finished Jun 02 02:43:22 PM PDT 24
Peak memory 221084 kb
Host smart-7eb36838-ff4d-4713-88d3-66e24394e88b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225930120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.4225930120
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3611820213
Short name T54
Test name
Test status
Simulation time 3424698384 ps
CPU time 29.12 seconds
Started Jun 02 02:41:25 PM PDT 24
Finished Jun 02 02:41:55 PM PDT 24
Peak memory 211832 kb
Host smart-2ef6b2ba-2f7e-48cb-bd78-eeef86deee12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611820213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3611820213
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.4000097630
Short name T260
Test name
Test status
Simulation time 8057716445 ps
CPU time 67 seconds
Started Jun 02 02:41:25 PM PDT 24
Finished Jun 02 02:42:33 PM PDT 24
Peak memory 215264 kb
Host smart-35596dc6-c389-4597-bc42-a07e832a8afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000097630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.4000097630
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2794392580
Short name T277
Test name
Test status
Simulation time 5857007689 ps
CPU time 19.19 seconds
Started Jun 02 02:41:30 PM PDT 24
Finished Jun 02 02:41:50 PM PDT 24
Peak memory 211860 kb
Host smart-9778e20e-db79-4ac7-8941-ef7af0fc512d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2794392580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2794392580
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3829346665
Short name T293
Test name
Test status
Simulation time 9194045834 ps
CPU time 35.63 seconds
Started Jun 02 02:41:23 PM PDT 24
Finished Jun 02 02:41:59 PM PDT 24
Peak memory 217492 kb
Host smart-cd9c397a-b235-4fc3-9ac1-def1f2ece66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829346665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3829346665
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1534374457
Short name T183
Test name
Test status
Simulation time 8284569302 ps
CPU time 61.46 seconds
Started Jun 02 02:41:24 PM PDT 24
Finished Jun 02 02:42:26 PM PDT 24
Peak memory 219048 kb
Host smart-b63ab734-18ab-433f-91ff-7e656b26cef6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534374457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1534374457
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3888222787
Short name T59
Test name
Test status
Simulation time 1032299978 ps
CPU time 8.41 seconds
Started Jun 02 02:41:35 PM PDT 24
Finished Jun 02 02:41:44 PM PDT 24
Peak memory 211320 kb
Host smart-d1624546-b7d2-4cb6-9238-a453291aeffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888222787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3888222787
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3022830195
Short name T278
Test name
Test status
Simulation time 37028829727 ps
CPU time 396.08 seconds
Started Jun 02 02:41:25 PM PDT 24
Finished Jun 02 02:48:02 PM PDT 24
Peak memory 236684 kb
Host smart-2bae1203-6cd7-4738-8ba4-4f2b6534c483
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022830195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3022830195
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1144290852
Short name T259
Test name
Test status
Simulation time 3089580356 ps
CPU time 30.66 seconds
Started Jun 02 02:41:24 PM PDT 24
Finished Jun 02 02:41:55 PM PDT 24
Peak memory 214832 kb
Host smart-3e5dfe6e-eef7-42da-8712-84babc130601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144290852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1144290852
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2758061586
Short name T323
Test name
Test status
Simulation time 4072074035 ps
CPU time 33.27 seconds
Started Jun 02 02:41:23 PM PDT 24
Finished Jun 02 02:41:57 PM PDT 24
Peak memory 212300 kb
Host smart-c4601900-b09c-4f2d-992c-300b8b83ce89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2758061586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2758061586
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2366022237
Short name T246
Test name
Test status
Simulation time 1538211471 ps
CPU time 20.92 seconds
Started Jun 02 02:41:23 PM PDT 24
Finished Jun 02 02:41:45 PM PDT 24
Peak memory 217836 kb
Host smart-7bf6fc56-6b8a-4a82-9a02-173e3b80e58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366022237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2366022237
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2333110181
Short name T349
Test name
Test status
Simulation time 2122357454 ps
CPU time 33.27 seconds
Started Jun 02 02:41:25 PM PDT 24
Finished Jun 02 02:42:00 PM PDT 24
Peak memory 219264 kb
Host smart-3105b7c1-85d8-4045-b373-eaa8ae92b412
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333110181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2333110181
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2444417700
Short name T7
Test name
Test status
Simulation time 171133085 ps
CPU time 8.41 seconds
Started Jun 02 02:41:34 PM PDT 24
Finished Jun 02 02:41:44 PM PDT 24
Peak memory 211304 kb
Host smart-7de61377-52da-40e4-8b61-16b6fd624b9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444417700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2444417700
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2266787126
Short name T221
Test name
Test status
Simulation time 107295507456 ps
CPU time 413.93 seconds
Started Jun 02 02:41:24 PM PDT 24
Finished Jun 02 02:48:19 PM PDT 24
Peak memory 239524 kb
Host smart-d9eee739-38b5-4c22-87a3-65addf1f6e1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266787126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2266787126
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3719204182
Short name T150
Test name
Test status
Simulation time 28337848088 ps
CPU time 64.68 seconds
Started Jun 02 02:41:30 PM PDT 24
Finished Jun 02 02:42:36 PM PDT 24
Peak memory 215032 kb
Host smart-48e40b16-4895-4b74-84fe-7be912855942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719204182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3719204182
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2968365805
Short name T203
Test name
Test status
Simulation time 2587810217 ps
CPU time 26.62 seconds
Started Jun 02 02:41:25 PM PDT 24
Finished Jun 02 02:41:52 PM PDT 24
Peak memory 212592 kb
Host smart-f458ef03-2008-4184-95a7-da63691eb53c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2968365805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2968365805
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.867812294
Short name T300
Test name
Test status
Simulation time 54689190012 ps
CPU time 51.03 seconds
Started Jun 02 02:41:25 PM PDT 24
Finished Jun 02 02:42:17 PM PDT 24
Peak memory 218308 kb
Host smart-ffa2f4be-f77f-47a0-8f1a-a4d1e19734a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867812294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.867812294
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3446507805
Short name T306
Test name
Test status
Simulation time 5990931177 ps
CPU time 68.03 seconds
Started Jun 02 02:41:34 PM PDT 24
Finished Jun 02 02:42:43 PM PDT 24
Peak memory 216904 kb
Host smart-72afb3ff-e54c-4cf9-ad32-cd27dfe789c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446507805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3446507805
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3341295926
Short name T198
Test name
Test status
Simulation time 7849683320 ps
CPU time 20.96 seconds
Started Jun 02 02:41:27 PM PDT 24
Finished Jun 02 02:41:49 PM PDT 24
Peak memory 212244 kb
Host smart-b5e5db07-e9e8-43ed-b516-28e6e26f135f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341295926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3341295926
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3578004989
Short name T340
Test name
Test status
Simulation time 31033729377 ps
CPU time 468.9 seconds
Started Jun 02 02:41:24 PM PDT 24
Finished Jun 02 02:49:13 PM PDT 24
Peak memory 238904 kb
Host smart-2a390a7a-e305-4e54-b0c5-df3ffd33d382
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578004989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3578004989
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1980753138
Short name T284
Test name
Test status
Simulation time 13607028154 ps
CPU time 30.76 seconds
Started Jun 02 02:41:25 PM PDT 24
Finished Jun 02 02:41:56 PM PDT 24
Peak memory 215112 kb
Host smart-021c468a-5cec-40a8-9244-0137b625d807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980753138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1980753138
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3233580439
Short name T364
Test name
Test status
Simulation time 351127846 ps
CPU time 10.08 seconds
Started Jun 02 02:41:24 PM PDT 24
Finished Jun 02 02:41:35 PM PDT 24
Peak memory 212628 kb
Host smart-b254551f-f741-4e57-95c8-d9bb08e1c2b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3233580439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3233580439
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1135144613
Short name T239
Test name
Test status
Simulation time 3957651360 ps
CPU time 33.58 seconds
Started Jun 02 02:41:25 PM PDT 24
Finished Jun 02 02:42:00 PM PDT 24
Peak memory 217484 kb
Host smart-e15cf47b-d20f-486e-825a-613d818441e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135144613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1135144613
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3490889172
Short name T22
Test name
Test status
Simulation time 5211664177 ps
CPU time 69.4 seconds
Started Jun 02 02:41:23 PM PDT 24
Finished Jun 02 02:42:33 PM PDT 24
Peak memory 218916 kb
Host smart-d8c2f18a-40ec-4a11-9861-981795438e9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490889172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3490889172
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1014407968
Short name T141
Test name
Test status
Simulation time 9109950957 ps
CPU time 22.1 seconds
Started Jun 02 02:41:25 PM PDT 24
Finished Jun 02 02:41:48 PM PDT 24
Peak memory 212336 kb
Host smart-467ee214-89ec-456d-b02e-6cd74b412052
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014407968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1014407968
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.872569460
Short name T29
Test name
Test status
Simulation time 58847534545 ps
CPU time 593.97 seconds
Started Jun 02 02:41:27 PM PDT 24
Finished Jun 02 02:51:22 PM PDT 24
Peak memory 240024 kb
Host smart-ca3acf63-75c0-466d-a8b8-ed780b8b1f49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872569460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.872569460
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.4025723162
Short name T321
Test name
Test status
Simulation time 15049358082 ps
CPU time 42.61 seconds
Started Jun 02 02:41:25 PM PDT 24
Finished Jun 02 02:42:08 PM PDT 24
Peak memory 215068 kb
Host smart-09434fa1-b022-4efa-846c-5fb862d3d303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025723162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.4025723162
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1487619765
Short name T123
Test name
Test status
Simulation time 11683100803 ps
CPU time 26.89 seconds
Started Jun 02 02:41:30 PM PDT 24
Finished Jun 02 02:41:58 PM PDT 24
Peak memory 211452 kb
Host smart-64ff79e6-a35e-4298-a9ed-0d333a9f2062
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1487619765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1487619765
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.13130037
Short name T77
Test name
Test status
Simulation time 587514391 ps
CPU time 20.71 seconds
Started Jun 02 02:41:25 PM PDT 24
Finished Jun 02 02:41:47 PM PDT 24
Peak memory 217468 kb
Host smart-81d138da-61e9-44a9-af50-7b5380d795ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13130037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.13130037
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1847162095
Short name T133
Test name
Test status
Simulation time 4977680991 ps
CPU time 57.66 seconds
Started Jun 02 02:41:25 PM PDT 24
Finished Jun 02 02:42:24 PM PDT 24
Peak memory 218132 kb
Host smart-dec7cd04-e8af-45dc-98ae-77e732041d47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847162095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1847162095
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1444350574
Short name T206
Test name
Test status
Simulation time 4841358921 ps
CPU time 23.71 seconds
Started Jun 02 02:41:30 PM PDT 24
Finished Jun 02 02:41:54 PM PDT 24
Peak memory 211364 kb
Host smart-68e9fca1-9959-49bf-9f2c-83cb5fc73226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444350574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1444350574
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.4157405125
Short name T207
Test name
Test status
Simulation time 10686406026 ps
CPU time 335.41 seconds
Started Jun 02 02:41:30 PM PDT 24
Finished Jun 02 02:47:06 PM PDT 24
Peak memory 240928 kb
Host smart-62645d49-ef2f-46c7-8358-3ff90ae61c14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157405125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.4157405125
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.4112442105
Short name T265
Test name
Test status
Simulation time 9023349619 ps
CPU time 47.78 seconds
Started Jun 02 02:41:24 PM PDT 24
Finished Jun 02 02:42:13 PM PDT 24
Peak memory 214996 kb
Host smart-e22e8100-e990-4bb7-9590-82c9f00bc9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112442105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.4112442105
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3523993855
Short name T344
Test name
Test status
Simulation time 1688933881 ps
CPU time 13.71 seconds
Started Jun 02 02:41:34 PM PDT 24
Finished Jun 02 02:41:49 PM PDT 24
Peak memory 211300 kb
Host smart-7bd669ae-8d28-4041-8813-39570a4fd38e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3523993855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3523993855
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.945231078
Short name T168
Test name
Test status
Simulation time 56002676536 ps
CPU time 38.28 seconds
Started Jun 02 02:41:23 PM PDT 24
Finished Jun 02 02:42:03 PM PDT 24
Peak memory 218624 kb
Host smart-3cc062be-fcce-4406-8dfc-c51e6335fccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945231078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.945231078
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.251881917
Short name T78
Test name
Test status
Simulation time 55007332019 ps
CPU time 110.57 seconds
Started Jun 02 02:41:26 PM PDT 24
Finished Jun 02 02:43:17 PM PDT 24
Peak memory 222192 kb
Host smart-9334f16c-3bc4-46dc-aa20-738822ced66e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251881917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.251881917
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1752846941
Short name T248
Test name
Test status
Simulation time 1032620401 ps
CPU time 12.09 seconds
Started Jun 02 02:41:35 PM PDT 24
Finished Jun 02 02:41:48 PM PDT 24
Peak memory 211320 kb
Host smart-ac91c9e2-b713-4599-981d-9bef86bca477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752846941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1752846941
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1370553964
Short name T197
Test name
Test status
Simulation time 39569315957 ps
CPU time 349 seconds
Started Jun 02 02:41:32 PM PDT 24
Finished Jun 02 02:47:22 PM PDT 24
Peak memory 237952 kb
Host smart-62c42bdb-7b3a-4b21-911e-b1b4abd19d69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370553964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1370553964
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2874340939
Short name T223
Test name
Test status
Simulation time 2062098351 ps
CPU time 22.07 seconds
Started Jun 02 02:41:30 PM PDT 24
Finished Jun 02 02:41:53 PM PDT 24
Peak memory 215024 kb
Host smart-f9295bf4-75b1-4b37-97e8-1c00c40a4c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874340939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2874340939
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.541894482
Short name T192
Test name
Test status
Simulation time 355210037 ps
CPU time 10.64 seconds
Started Jun 02 02:41:32 PM PDT 24
Finished Jun 02 02:41:44 PM PDT 24
Peak memory 212700 kb
Host smart-d8f14908-3a6f-46cc-9125-1f8baeb22249
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=541894482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.541894482
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2406461374
Short name T191
Test name
Test status
Simulation time 6443946338 ps
CPU time 32.82 seconds
Started Jun 02 02:41:31 PM PDT 24
Finished Jun 02 02:42:06 PM PDT 24
Peak memory 217980 kb
Host smart-6df87cb5-5eff-47ff-b4f1-cb937f99dcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406461374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2406461374
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.4246119524
Short name T36
Test name
Test status
Simulation time 2847418448 ps
CPU time 15.91 seconds
Started Jun 02 02:41:30 PM PDT 24
Finished Jun 02 02:41:47 PM PDT 24
Peak memory 212336 kb
Host smart-b216608b-e0ed-4f9f-b80a-92675bd068d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246119524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.4246119524
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.113459275
Short name T139
Test name
Test status
Simulation time 174289886 ps
CPU time 8.63 seconds
Started Jun 02 02:41:09 PM PDT 24
Finished Jun 02 02:41:18 PM PDT 24
Peak memory 211296 kb
Host smart-5f922cf8-6ec8-4d69-9bdc-c5c6b5959677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113459275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.113459275
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2416196316
Short name T153
Test name
Test status
Simulation time 26364807494 ps
CPU time 264.11 seconds
Started Jun 02 02:41:11 PM PDT 24
Finished Jun 02 02:45:36 PM PDT 24
Peak memory 238024 kb
Host smart-0314b28b-ecd7-4bbd-b1e5-8cf4752264c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416196316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2416196316
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1304647832
Short name T165
Test name
Test status
Simulation time 15048929287 ps
CPU time 42.55 seconds
Started Jun 02 02:41:11 PM PDT 24
Finished Jun 02 02:41:54 PM PDT 24
Peak memory 215272 kb
Host smart-bc765db9-8173-4aea-9c1b-5ca7c5c2ecdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304647832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1304647832
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3740681952
Short name T182
Test name
Test status
Simulation time 3325008181 ps
CPU time 16.8 seconds
Started Jun 02 02:41:12 PM PDT 24
Finished Jun 02 02:41:29 PM PDT 24
Peak memory 211520 kb
Host smart-ec99c810-54a9-4b45-aa01-4466cbaf2602
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3740681952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3740681952
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.120066304
Short name T34
Test name
Test status
Simulation time 7065982323 ps
CPU time 244.4 seconds
Started Jun 02 02:41:11 PM PDT 24
Finished Jun 02 02:45:16 PM PDT 24
Peak memory 236852 kb
Host smart-6bf434f4-2788-4657-911a-f3d6ea91a48d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120066304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.120066304
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.254202143
Short name T276
Test name
Test status
Simulation time 29517342068 ps
CPU time 65.14 seconds
Started Jun 02 02:41:07 PM PDT 24
Finished Jun 02 02:42:12 PM PDT 24
Peak memory 215352 kb
Host smart-c1df0f39-b297-4f37-a143-915f5f04d19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254202143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.254202143
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1531980961
Short name T151
Test name
Test status
Simulation time 4124480246 ps
CPU time 48.77 seconds
Started Jun 02 02:41:04 PM PDT 24
Finished Jun 02 02:41:54 PM PDT 24
Peak memory 217996 kb
Host smart-ddfec01d-812c-4aba-a2a0-f70d2c4f9c7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531980961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1531980961
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3558712996
Short name T140
Test name
Test status
Simulation time 6309822127 ps
CPU time 24.07 seconds
Started Jun 02 02:41:32 PM PDT 24
Finished Jun 02 02:41:57 PM PDT 24
Peak memory 212232 kb
Host smart-fa32b1fe-e023-47de-b1e6-d56e32901e31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558712996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3558712996
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.352864627
Short name T339
Test name
Test status
Simulation time 3405369091 ps
CPU time 282.91 seconds
Started Jun 02 02:41:31 PM PDT 24
Finished Jun 02 02:46:16 PM PDT 24
Peak memory 237924 kb
Host smart-8efd1eb1-9929-4ac5-9ccb-59556d11bd61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352864627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.352864627
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3992439557
Short name T205
Test name
Test status
Simulation time 848013271 ps
CPU time 19.5 seconds
Started Jun 02 02:41:32 PM PDT 24
Finished Jun 02 02:41:52 PM PDT 24
Peak memory 214588 kb
Host smart-3081996b-b251-4a6b-8c4a-d33a8ee4ce36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992439557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3992439557
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3920015224
Short name T273
Test name
Test status
Simulation time 671636081 ps
CPU time 10.49 seconds
Started Jun 02 02:41:34 PM PDT 24
Finished Jun 02 02:41:45 PM PDT 24
Peak memory 212776 kb
Host smart-52311bf4-3341-491a-bd59-54c083ba2d6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3920015224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3920015224
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3412333689
Short name T313
Test name
Test status
Simulation time 24463194030 ps
CPU time 56.09 seconds
Started Jun 02 02:41:30 PM PDT 24
Finished Jun 02 02:42:27 PM PDT 24
Peak memory 218520 kb
Host smart-bc1db8bc-cd31-4931-9460-1a15d67d65c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412333689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3412333689
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.281387607
Short name T222
Test name
Test status
Simulation time 32862130736 ps
CPU time 69.19 seconds
Started Jun 02 02:41:33 PM PDT 24
Finished Jun 02 02:42:43 PM PDT 24
Peak memory 218180 kb
Host smart-c7d0217b-528e-4f89-94e5-f171deb32ea0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281387607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.281387607
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.850550758
Short name T61
Test name
Test status
Simulation time 174309438 ps
CPU time 8.42 seconds
Started Jun 02 02:41:31 PM PDT 24
Finished Jun 02 02:41:41 PM PDT 24
Peak memory 211324 kb
Host smart-f06e5617-bdaa-4c6a-b292-b9600e4817d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850550758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.850550758
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2240223397
Short name T186
Test name
Test status
Simulation time 752326172 ps
CPU time 19.77 seconds
Started Jun 02 02:41:31 PM PDT 24
Finished Jun 02 02:41:52 PM PDT 24
Peak memory 214864 kb
Host smart-3a83e4da-fefb-49b6-9d47-d0dc20a05313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240223397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2240223397
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.159992678
Short name T283
Test name
Test status
Simulation time 361103148 ps
CPU time 10.11 seconds
Started Jun 02 02:41:32 PM PDT 24
Finished Jun 02 02:41:43 PM PDT 24
Peak memory 212592 kb
Host smart-e8e23b88-0bbf-4870-8bda-e4486dd74508
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=159992678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.159992678
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.601336267
Short name T138
Test name
Test status
Simulation time 4139477585 ps
CPU time 27.01 seconds
Started Jun 02 02:41:32 PM PDT 24
Finished Jun 02 02:42:00 PM PDT 24
Peak memory 217212 kb
Host smart-76361299-b2a7-4537-bb45-a49cde1ae246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601336267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.601336267
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.752835804
Short name T202
Test name
Test status
Simulation time 581401140 ps
CPU time 12.75 seconds
Started Jun 02 02:41:32 PM PDT 24
Finished Jun 02 02:41:46 PM PDT 24
Peak memory 211340 kb
Host smart-122a767f-e65d-42cc-a273-635b0fcf5cde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752835804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.752835804
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2341291951
Short name T338
Test name
Test status
Simulation time 67716395536 ps
CPU time 645.97 seconds
Started Jun 02 02:41:31 PM PDT 24
Finished Jun 02 02:52:18 PM PDT 24
Peak memory 237980 kb
Host smart-db64beb9-e8ca-4541-9f94-b4ed82a6b34f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341291951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2341291951
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1964603109
Short name T188
Test name
Test status
Simulation time 8510320441 ps
CPU time 69.68 seconds
Started Jun 02 02:41:32 PM PDT 24
Finished Jun 02 02:42:42 PM PDT 24
Peak memory 215112 kb
Host smart-88259fd2-110c-4c53-a4ab-2f2ef847891b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964603109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1964603109
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3985319069
Short name T249
Test name
Test status
Simulation time 15977785934 ps
CPU time 25.88 seconds
Started Jun 02 02:41:31 PM PDT 24
Finished Jun 02 02:41:59 PM PDT 24
Peak memory 211788 kb
Host smart-735ca80f-45b4-4092-a03e-ec24743d1c7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3985319069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3985319069
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.66162652
Short name T200
Test name
Test status
Simulation time 28955874794 ps
CPU time 138.13 seconds
Started Jun 02 02:41:32 PM PDT 24
Finished Jun 02 02:43:51 PM PDT 24
Peak memory 221736 kb
Host smart-28515f24-a7a2-4b64-b807-b4e065886872
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66162652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 22.rom_ctrl_stress_all.66162652
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3338130616
Short name T47
Test name
Test status
Simulation time 35151647578 ps
CPU time 2777.69 seconds
Started Jun 02 02:41:31 PM PDT 24
Finished Jun 02 03:27:50 PM PDT 24
Peak memory 235848 kb
Host smart-1cf2b554-bedc-4d5c-a702-bdfc4325ccbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338130616 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3338130616
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.628388932
Short name T226
Test name
Test status
Simulation time 688471222 ps
CPU time 8.54 seconds
Started Jun 02 02:41:31 PM PDT 24
Finished Jun 02 02:41:41 PM PDT 24
Peak memory 211240 kb
Host smart-ab3dd4b8-50d3-45c9-9e34-b4496043a650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628388932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.628388932
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3605125403
Short name T217
Test name
Test status
Simulation time 147931237412 ps
CPU time 563.68 seconds
Started Jun 02 02:41:37 PM PDT 24
Finished Jun 02 02:51:01 PM PDT 24
Peak memory 237876 kb
Host smart-2461a267-283a-4f39-a8aa-a45981091146
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605125403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3605125403
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3737634970
Short name T322
Test name
Test status
Simulation time 34010488528 ps
CPU time 71.18 seconds
Started Jun 02 02:41:32 PM PDT 24
Finished Jun 02 02:42:44 PM PDT 24
Peak memory 215120 kb
Host smart-79d020bc-96bd-4e7c-ab80-77562d5af980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737634970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3737634970
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.783948432
Short name T331
Test name
Test status
Simulation time 3931318200 ps
CPU time 33.81 seconds
Started Jun 02 02:41:30 PM PDT 24
Finished Jun 02 02:42:05 PM PDT 24
Peak memory 211336 kb
Host smart-bd401233-3cc0-433e-8d0b-b2b7a371b7a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=783948432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.783948432
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.800724974
Short name T6
Test name
Test status
Simulation time 360143572 ps
CPU time 20.66 seconds
Started Jun 02 02:41:31 PM PDT 24
Finished Jun 02 02:41:53 PM PDT 24
Peak memory 213708 kb
Host smart-1999b08b-8db7-4e16-8f23-e4fc86cc4056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800724974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.800724974
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2701789267
Short name T37
Test name
Test status
Simulation time 6710133335 ps
CPU time 61.93 seconds
Started Jun 02 02:41:31 PM PDT 24
Finished Jun 02 02:42:35 PM PDT 24
Peak memory 218312 kb
Host smart-3a8cbb96-411c-42e8-96dd-e7e00c747a27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701789267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2701789267
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3567077609
Short name T134
Test name
Test status
Simulation time 170816507 ps
CPU time 8.64 seconds
Started Jun 02 02:41:39 PM PDT 24
Finished Jun 02 02:41:49 PM PDT 24
Peak memory 211268 kb
Host smart-81b1f3bc-c3f0-4ae2-9fdc-4cadc05fb928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567077609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3567077609
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1565178667
Short name T317
Test name
Test status
Simulation time 10003159111 ps
CPU time 180.46 seconds
Started Jun 02 02:41:31 PM PDT 24
Finished Jun 02 02:44:33 PM PDT 24
Peak memory 228868 kb
Host smart-894455b3-8dd9-492d-880c-38d292959458
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565178667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1565178667
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.24129612
Short name T24
Test name
Test status
Simulation time 15728665753 ps
CPU time 44.6 seconds
Started Jun 02 02:41:39 PM PDT 24
Finished Jun 02 02:42:25 PM PDT 24
Peak memory 215152 kb
Host smart-90c4c8d3-1d90-40c8-90c8-c91be65911df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24129612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.24129612
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.4222467842
Short name T152
Test name
Test status
Simulation time 727453623 ps
CPU time 10.83 seconds
Started Jun 02 02:41:32 PM PDT 24
Finished Jun 02 02:41:44 PM PDT 24
Peak memory 212716 kb
Host smart-49dd5ee8-ac7a-498d-8e8e-d38066982352
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4222467842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.4222467842
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1811455458
Short name T211
Test name
Test status
Simulation time 1662179591 ps
CPU time 31.37 seconds
Started Jun 02 02:41:37 PM PDT 24
Finished Jun 02 02:42:09 PM PDT 24
Peak memory 217948 kb
Host smart-0bb1874a-71a9-4926-af7f-ccf95c068a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811455458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1811455458
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.701434354
Short name T262
Test name
Test status
Simulation time 5861120404 ps
CPU time 31.78 seconds
Started Jun 02 02:41:32 PM PDT 24
Finished Jun 02 02:42:05 PM PDT 24
Peak memory 211792 kb
Host smart-2aad8830-4c45-44c1-9c7f-59a5a4cf3ae2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701434354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.701434354
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.18422290
Short name T250
Test name
Test status
Simulation time 13682389879 ps
CPU time 27.54 seconds
Started Jun 02 02:41:40 PM PDT 24
Finished Jun 02 02:42:08 PM PDT 24
Peak memory 212288 kb
Host smart-b706cc9d-71c9-40fa-b200-7324198112aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18422290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.18422290
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3770069786
Short name T194
Test name
Test status
Simulation time 98881244699 ps
CPU time 400.49 seconds
Started Jun 02 02:41:38 PM PDT 24
Finished Jun 02 02:48:19 PM PDT 24
Peak memory 216824 kb
Host smart-f768d74b-eb1d-4321-9489-8737aebe29d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770069786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3770069786
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.129715846
Short name T301
Test name
Test status
Simulation time 353403227 ps
CPU time 19.51 seconds
Started Jun 02 02:41:39 PM PDT 24
Finished Jun 02 02:41:59 PM PDT 24
Peak memory 214692 kb
Host smart-c6317a99-fe9c-4d3c-a0b4-087d82b8442a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129715846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.129715846
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1992874190
Short name T4
Test name
Test status
Simulation time 3713484884 ps
CPU time 30.99 seconds
Started Jun 02 02:41:36 PM PDT 24
Finished Jun 02 02:42:08 PM PDT 24
Peak memory 211376 kb
Host smart-d40b833d-876e-449a-8cec-38a246488bc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1992874190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1992874190
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3891993779
Short name T361
Test name
Test status
Simulation time 49013980153 ps
CPU time 63.41 seconds
Started Jun 02 02:41:38 PM PDT 24
Finished Jun 02 02:42:42 PM PDT 24
Peak memory 218092 kb
Host smart-b975c883-a843-40df-968c-9594c2f0c34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891993779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3891993779
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.319506328
Short name T129
Test name
Test status
Simulation time 10196193014 ps
CPU time 110.05 seconds
Started Jun 02 02:41:39 PM PDT 24
Finished Jun 02 02:43:30 PM PDT 24
Peak memory 220536 kb
Host smart-b52be0de-8201-4a1d-b484-d7798dbf6079
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319506328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.319506328
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1530307581
Short name T176
Test name
Test status
Simulation time 6659310374 ps
CPU time 28.03 seconds
Started Jun 02 02:41:38 PM PDT 24
Finished Jun 02 02:42:07 PM PDT 24
Peak memory 212180 kb
Host smart-19903d8e-5428-44cf-bad4-87412e126e4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530307581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1530307581
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.392446192
Short name T332
Test name
Test status
Simulation time 327568547410 ps
CPU time 541.97 seconds
Started Jun 02 02:41:37 PM PDT 24
Finished Jun 02 02:50:40 PM PDT 24
Peak memory 240192 kb
Host smart-13282717-1d0a-40cf-8270-d3e50f71e9f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392446192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.392446192
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4287845797
Short name T156
Test name
Test status
Simulation time 3251032895 ps
CPU time 38.86 seconds
Started Jun 02 02:41:37 PM PDT 24
Finished Jun 02 02:42:17 PM PDT 24
Peak memory 215088 kb
Host smart-02010784-8251-4dea-862a-3a9365f7b756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287845797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4287845797
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.482138818
Short name T224
Test name
Test status
Simulation time 4990919365 ps
CPU time 14 seconds
Started Jun 02 02:41:37 PM PDT 24
Finished Jun 02 02:41:52 PM PDT 24
Peak memory 211936 kb
Host smart-a25c77e6-77c8-4f55-b4d6-e12242afc45d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=482138818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.482138818
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3104144394
Short name T316
Test name
Test status
Simulation time 46362175186 ps
CPU time 58.55 seconds
Started Jun 02 02:41:39 PM PDT 24
Finished Jun 02 02:42:38 PM PDT 24
Peak memory 218212 kb
Host smart-106087fa-a659-4009-b353-7c1810df8765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104144394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3104144394
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1139597034
Short name T157
Test name
Test status
Simulation time 12550356946 ps
CPU time 40.43 seconds
Started Jun 02 02:41:38 PM PDT 24
Finished Jun 02 02:42:19 PM PDT 24
Peak memory 218884 kb
Host smart-8a298476-cebb-4fc0-b93e-de3284b5c8cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139597034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1139597034
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1125299568
Short name T342
Test name
Test status
Simulation time 345752176 ps
CPU time 11 seconds
Started Jun 02 02:41:39 PM PDT 24
Finished Jun 02 02:41:51 PM PDT 24
Peak memory 211308 kb
Host smart-eed7cc9c-8055-46fd-b4c8-de85f60972a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125299568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1125299568
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2269377192
Short name T179
Test name
Test status
Simulation time 8005249601 ps
CPU time 274.86 seconds
Started Jun 02 02:41:39 PM PDT 24
Finished Jun 02 02:46:15 PM PDT 24
Peak memory 233976 kb
Host smart-a48e6607-1905-4ce2-9742-a6ac0c34db85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269377192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2269377192
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3119538527
Short name T225
Test name
Test status
Simulation time 2484191147 ps
CPU time 35.6 seconds
Started Jun 02 02:41:43 PM PDT 24
Finished Jun 02 02:42:19 PM PDT 24
Peak memory 215008 kb
Host smart-1a54eeaa-10fc-43ae-a322-498ac53c00b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119538527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3119538527
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3178375994
Short name T241
Test name
Test status
Simulation time 3177346949 ps
CPU time 28.47 seconds
Started Jun 02 02:41:43 PM PDT 24
Finished Jun 02 02:42:12 PM PDT 24
Peak memory 211376 kb
Host smart-0fc66602-bf00-44a2-af1a-acb77faae83f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3178375994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3178375994
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3009313264
Short name T199
Test name
Test status
Simulation time 3218422011 ps
CPU time 41.3 seconds
Started Jun 02 02:41:36 PM PDT 24
Finished Jun 02 02:42:18 PM PDT 24
Peak memory 218664 kb
Host smart-cd16d201-0dec-4075-93af-5e021295dc26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009313264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3009313264
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.593060492
Short name T351
Test name
Test status
Simulation time 5053127987 ps
CPU time 34.09 seconds
Started Jun 02 02:41:38 PM PDT 24
Finished Jun 02 02:42:13 PM PDT 24
Peak memory 211440 kb
Host smart-4853dfdb-97cf-47e9-97fb-d4271720a83f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593060492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.593060492
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.44517126
Short name T231
Test name
Test status
Simulation time 93324983608 ps
CPU time 991.65 seconds
Started Jun 02 02:41:39 PM PDT 24
Finished Jun 02 02:58:12 PM PDT 24
Peak memory 229216 kb
Host smart-26835f47-f6de-44e4-a07d-d310a026ad3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44517126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_co
rrupt_sig_fatal_chk.44517126
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.4036715914
Short name T285
Test name
Test status
Simulation time 38844680151 ps
CPU time 71.44 seconds
Started Jun 02 02:41:40 PM PDT 24
Finished Jun 02 02:42:52 PM PDT 24
Peak memory 215012 kb
Host smart-787fd5a3-cf22-4bac-826d-1ffa3a90e653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036715914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.4036715914
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.25721591
Short name T13
Test name
Test status
Simulation time 2072297973 ps
CPU time 17.22 seconds
Started Jun 02 02:41:37 PM PDT 24
Finished Jun 02 02:41:55 PM PDT 24
Peak memory 211392 kb
Host smart-570879c3-26e8-47c9-b3ae-c377c87af462
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=25721591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.25721591
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1492661635
Short name T144
Test name
Test status
Simulation time 9348307282 ps
CPU time 34.73 seconds
Started Jun 02 02:41:41 PM PDT 24
Finished Jun 02 02:42:16 PM PDT 24
Peak memory 218064 kb
Host smart-fc61dee0-ebb4-40e4-9eb5-08dac95fb905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492661635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1492661635
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1006961019
Short name T161
Test name
Test status
Simulation time 8051333997 ps
CPU time 104.55 seconds
Started Jun 02 02:41:39 PM PDT 24
Finished Jun 02 02:43:24 PM PDT 24
Peak memory 221644 kb
Host smart-c16e87a7-558d-4fbf-a30c-6bd53547701d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006961019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1006961019
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2220127662
Short name T40
Test name
Test status
Simulation time 4450519859 ps
CPU time 21.58 seconds
Started Jun 02 02:41:39 PM PDT 24
Finished Jun 02 02:42:02 PM PDT 24
Peak memory 212296 kb
Host smart-c7a621af-6349-4723-95b3-458ea52c20b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220127662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2220127662
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1679012802
Short name T190
Test name
Test status
Simulation time 65254545217 ps
CPU time 692.5 seconds
Started Jun 02 02:41:41 PM PDT 24
Finished Jun 02 02:53:14 PM PDT 24
Peak memory 238056 kb
Host smart-7ca0b5d4-231f-4252-87a3-a8970aa2b73f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679012802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1679012802
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.639974705
Short name T345
Test name
Test status
Simulation time 1737781180 ps
CPU time 19.6 seconds
Started Jun 02 02:41:38 PM PDT 24
Finished Jun 02 02:41:58 PM PDT 24
Peak memory 214924 kb
Host smart-d8e100ef-0f7b-4583-af58-e9e40cf357f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639974705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.639974705
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3370386544
Short name T12
Test name
Test status
Simulation time 603077779 ps
CPU time 10.81 seconds
Started Jun 02 02:41:38 PM PDT 24
Finished Jun 02 02:41:49 PM PDT 24
Peak memory 212764 kb
Host smart-6b7af283-33dc-4ad3-90c9-2e4223f2234f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3370386544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3370386544
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.4094633585
Short name T242
Test name
Test status
Simulation time 1046471831 ps
CPU time 23.23 seconds
Started Jun 02 02:41:43 PM PDT 24
Finished Jun 02 02:42:07 PM PDT 24
Peak memory 217964 kb
Host smart-e854cc62-4c3b-40f7-96e8-d69ce81234bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094633585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.4094633585
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3819963615
Short name T245
Test name
Test status
Simulation time 12521214561 ps
CPU time 47.96 seconds
Started Jun 02 02:41:43 PM PDT 24
Finished Jun 02 02:42:32 PM PDT 24
Peak memory 217728 kb
Host smart-19941697-1784-4f50-b624-552646d66ff5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819963615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3819963615
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2005485203
Short name T354
Test name
Test status
Simulation time 4961208723 ps
CPU time 23.28 seconds
Started Jun 02 02:41:13 PM PDT 24
Finished Jun 02 02:41:37 PM PDT 24
Peak memory 212360 kb
Host smart-34391336-17e0-4e20-8068-fd5c9b8ab80c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005485203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2005485203
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3699385842
Short name T238
Test name
Test status
Simulation time 18563456107 ps
CPU time 367.26 seconds
Started Jun 02 02:41:11 PM PDT 24
Finished Jun 02 02:47:19 PM PDT 24
Peak memory 240184 kb
Host smart-ba2e12d3-d764-47e7-83f9-d334d0f18ded
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699385842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3699385842
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2816437371
Short name T171
Test name
Test status
Simulation time 17988905870 ps
CPU time 64.95 seconds
Started Jun 02 02:41:11 PM PDT 24
Finished Jun 02 02:42:16 PM PDT 24
Peak memory 214160 kb
Host smart-29d40cdb-873f-4d65-8eab-24e42c1cbb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816437371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2816437371
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3393408074
Short name T189
Test name
Test status
Simulation time 1569851955 ps
CPU time 21.31 seconds
Started Jun 02 02:41:09 PM PDT 24
Finished Jun 02 02:41:31 PM PDT 24
Peak memory 212528 kb
Host smart-d7060276-0295-48ad-bc04-5dd5d14e7d48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3393408074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3393408074
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.274960256
Short name T337
Test name
Test status
Simulation time 7735265520 ps
CPU time 65.5 seconds
Started Jun 02 02:41:13 PM PDT 24
Finished Jun 02 02:42:19 PM PDT 24
Peak memory 215612 kb
Host smart-d0a413e5-3b28-4570-80c6-168c53b576fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274960256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.274960256
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2635543191
Short name T181
Test name
Test status
Simulation time 43644251582 ps
CPU time 120.84 seconds
Started Jun 02 02:41:11 PM PDT 24
Finished Jun 02 02:43:13 PM PDT 24
Peak memory 220284 kb
Host smart-b2c26c56-5644-4edb-88d2-e6689c0802ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635543191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2635543191
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.521687963
Short name T352
Test name
Test status
Simulation time 1109046877 ps
CPU time 15 seconds
Started Jun 02 02:41:45 PM PDT 24
Finished Jun 02 02:42:00 PM PDT 24
Peak memory 211364 kb
Host smart-528942f4-9623-47cb-8bbe-16f6c3512700
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521687963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.521687963
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.257838588
Short name T45
Test name
Test status
Simulation time 126325835098 ps
CPU time 737.21 seconds
Started Jun 02 02:41:45 PM PDT 24
Finished Jun 02 02:54:03 PM PDT 24
Peak memory 234368 kb
Host smart-4bcd8e96-9bc8-4cc8-9dd7-85adc6e20992
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257838588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.257838588
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4090420142
Short name T291
Test name
Test status
Simulation time 5631891927 ps
CPU time 42.27 seconds
Started Jun 02 02:41:49 PM PDT 24
Finished Jun 02 02:42:31 PM PDT 24
Peak memory 214036 kb
Host smart-7d852bb0-ebfa-4c20-8404-abd1dd67fc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090420142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.4090420142
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3693376348
Short name T208
Test name
Test status
Simulation time 4188166188 ps
CPU time 35.07 seconds
Started Jun 02 02:41:44 PM PDT 24
Finished Jun 02 02:42:20 PM PDT 24
Peak memory 211448 kb
Host smart-61c22468-67a6-422a-b890-c53c69efc01f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3693376348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3693376348
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1124172629
Short name T218
Test name
Test status
Simulation time 22018872540 ps
CPU time 56.62 seconds
Started Jun 02 02:41:43 PM PDT 24
Finished Jun 02 02:42:41 PM PDT 24
Peak memory 216632 kb
Host smart-8e71d61f-5622-4432-9d40-a662cb44af51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124172629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1124172629
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2555270053
Short name T204
Test name
Test status
Simulation time 39618708315 ps
CPU time 128.12 seconds
Started Jun 02 02:41:39 PM PDT 24
Finished Jun 02 02:43:48 PM PDT 24
Peak memory 220516 kb
Host smart-e6ef9d85-c8aa-4148-a2cf-93e6a65eea46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555270053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2555270053
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3809817464
Short name T5
Test name
Test status
Simulation time 11338230194 ps
CPU time 28.61 seconds
Started Jun 02 02:41:45 PM PDT 24
Finished Jun 02 02:42:14 PM PDT 24
Peak memory 212184 kb
Host smart-2c1311e3-9a9d-4ff5-9143-06b65aafb71c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809817464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3809817464
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.939330070
Short name T330
Test name
Test status
Simulation time 132945401507 ps
CPU time 282.3 seconds
Started Jun 02 02:41:45 PM PDT 24
Finished Jun 02 02:46:28 PM PDT 24
Peak memory 236172 kb
Host smart-19aaa6b9-6cdc-475b-bf66-48b5144e25d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939330070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.939330070
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3002824930
Short name T228
Test name
Test status
Simulation time 11886180270 ps
CPU time 35.58 seconds
Started Jun 02 02:41:44 PM PDT 24
Finished Jun 02 02:42:20 PM PDT 24
Peak memory 214128 kb
Host smart-42a860e0-d29c-44ce-bf9b-e5c36c7cffcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002824930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3002824930
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3761120950
Short name T343
Test name
Test status
Simulation time 3858211485 ps
CPU time 19.06 seconds
Started Jun 02 02:41:46 PM PDT 24
Finished Jun 02 02:42:05 PM PDT 24
Peak memory 212584 kb
Host smart-0947b191-e844-4fc9-ab68-f2df3034234a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3761120950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3761120950
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3884683133
Short name T1
Test name
Test status
Simulation time 20692757605 ps
CPU time 54 seconds
Started Jun 02 02:41:44 PM PDT 24
Finished Jun 02 02:42:38 PM PDT 24
Peak memory 215516 kb
Host smart-771bba2c-2d40-4f3e-ace7-83b09ae11035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884683133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3884683133
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2085516211
Short name T247
Test name
Test status
Simulation time 11507472081 ps
CPU time 98.58 seconds
Started Jun 02 02:41:44 PM PDT 24
Finished Jun 02 02:43:24 PM PDT 24
Peak memory 219704 kb
Host smart-5f6ba069-3a41-47e3-acb2-b7dba39569d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085516211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2085516211
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.935402755
Short name T136
Test name
Test status
Simulation time 17721187938 ps
CPU time 32.84 seconds
Started Jun 02 02:41:44 PM PDT 24
Finished Jun 02 02:42:18 PM PDT 24
Peak memory 211464 kb
Host smart-d85dc76e-8080-48b0-9f2f-c0a09361b8e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935402755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.935402755
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.372395784
Short name T282
Test name
Test status
Simulation time 11541669657 ps
CPU time 67.38 seconds
Started Jun 02 02:41:43 PM PDT 24
Finished Jun 02 02:42:51 PM PDT 24
Peak memory 215196 kb
Host smart-0911539e-4acf-4dfb-b628-5e6f5cfc899a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372395784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.372395784
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2425465233
Short name T39
Test name
Test status
Simulation time 351613183 ps
CPU time 10.91 seconds
Started Jun 02 02:41:43 PM PDT 24
Finished Jun 02 02:41:55 PM PDT 24
Peak memory 212356 kb
Host smart-8b308ec2-0291-445b-9284-43bed819faa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2425465233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2425465233
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3330448690
Short name T251
Test name
Test status
Simulation time 348867274 ps
CPU time 20.54 seconds
Started Jun 02 02:41:42 PM PDT 24
Finished Jun 02 02:42:04 PM PDT 24
Peak memory 216460 kb
Host smart-5b975678-adfb-4d07-b96c-e866867d0f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330448690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3330448690
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3623144756
Short name T237
Test name
Test status
Simulation time 15129050720 ps
CPU time 151.96 seconds
Started Jun 02 02:41:43 PM PDT 24
Finished Jun 02 02:44:16 PM PDT 24
Peak memory 220896 kb
Host smart-4947944c-9c3b-43a2-992a-e72afac071fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623144756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3623144756
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3808694301
Short name T175
Test name
Test status
Simulation time 2383907689 ps
CPU time 23.48 seconds
Started Jun 02 02:41:42 PM PDT 24
Finished Jun 02 02:42:06 PM PDT 24
Peak memory 211952 kb
Host smart-ab3e3837-bc4b-4e93-ad31-e5b89557089a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808694301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3808694301
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2988457174
Short name T27
Test name
Test status
Simulation time 11207430320 ps
CPU time 180.14 seconds
Started Jun 02 02:41:50 PM PDT 24
Finished Jun 02 02:44:50 PM PDT 24
Peak memory 219612 kb
Host smart-72b4cb4f-3587-419c-a259-be615d8f90a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988457174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2988457174
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1288582746
Short name T287
Test name
Test status
Simulation time 332526912 ps
CPU time 19.55 seconds
Started Jun 02 02:41:42 PM PDT 24
Finished Jun 02 02:42:02 PM PDT 24
Peak memory 214800 kb
Host smart-25524b66-2d7a-4731-a3c7-6d9441bfc36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288582746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1288582746
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3849159769
Short name T270
Test name
Test status
Simulation time 4436732744 ps
CPU time 23.73 seconds
Started Jun 02 02:41:47 PM PDT 24
Finished Jun 02 02:42:11 PM PDT 24
Peak memory 211436 kb
Host smart-9c2d6956-04bb-4d21-ada6-fbe7275acfd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3849159769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3849159769
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2980382138
Short name T302
Test name
Test status
Simulation time 4439705502 ps
CPU time 46.56 seconds
Started Jun 02 02:41:49 PM PDT 24
Finished Jun 02 02:42:36 PM PDT 24
Peak memory 215092 kb
Host smart-337533c1-d50b-4c5a-8b21-0f7e09320670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980382138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2980382138
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2133283354
Short name T341
Test name
Test status
Simulation time 14143595113 ps
CPU time 160.41 seconds
Started Jun 02 02:41:45 PM PDT 24
Finished Jun 02 02:44:26 PM PDT 24
Peak memory 230520 kb
Host smart-206519fa-2b6b-4b61-8ce3-f7df6429b4b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133283354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2133283354
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4127424257
Short name T297
Test name
Test status
Simulation time 10950556093 ps
CPU time 25.04 seconds
Started Jun 02 02:41:58 PM PDT 24
Finished Jun 02 02:42:25 PM PDT 24
Peak memory 212092 kb
Host smart-c95077dc-3aaf-4db6-8b6a-58d256e7af02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127424257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4127424257
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1680450092
Short name T46
Test name
Test status
Simulation time 448912274820 ps
CPU time 803.35 seconds
Started Jun 02 02:41:45 PM PDT 24
Finished Jun 02 02:55:09 PM PDT 24
Peak memory 240628 kb
Host smart-d9add129-fb8b-4dd1-9af0-5f62f73e5085
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680450092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1680450092
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2118626795
Short name T294
Test name
Test status
Simulation time 25638805018 ps
CPU time 65.73 seconds
Started Jun 02 02:41:45 PM PDT 24
Finished Jun 02 02:42:52 PM PDT 24
Peak memory 215076 kb
Host smart-e1905f65-7993-460b-9d29-9724f90dd949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118626795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2118626795
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.4014306825
Short name T269
Test name
Test status
Simulation time 39123067933 ps
CPU time 33.41 seconds
Started Jun 02 02:41:44 PM PDT 24
Finished Jun 02 02:42:18 PM PDT 24
Peak memory 211848 kb
Host smart-d49c0ca4-1e7f-44c3-9885-8d20e9b8e0a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4014306825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.4014306825
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1219683721
Short name T255
Test name
Test status
Simulation time 3596745195 ps
CPU time 42.75 seconds
Started Jun 02 02:41:51 PM PDT 24
Finished Jun 02 02:42:34 PM PDT 24
Peak memory 217700 kb
Host smart-d8161123-d292-4a43-812f-42d6addbb757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219683721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1219683721
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1664147673
Short name T122
Test name
Test status
Simulation time 718533756 ps
CPU time 18.34 seconds
Started Jun 02 02:41:42 PM PDT 24
Finished Jun 02 02:42:01 PM PDT 24
Peak memory 212404 kb
Host smart-eaeb5bf9-4a76-4ea9-88fb-7810a2ab6485
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664147673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1664147673
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2579215546
Short name T48
Test name
Test status
Simulation time 158937703773 ps
CPU time 8472.78 seconds
Started Jun 02 02:41:58 PM PDT 24
Finished Jun 02 05:03:13 PM PDT 24
Peak memory 235924 kb
Host smart-5d561262-e853-45a1-819f-93d387218298
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579215546 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2579215546
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3399104560
Short name T304
Test name
Test status
Simulation time 332209750 ps
CPU time 8.66 seconds
Started Jun 02 02:41:50 PM PDT 24
Finished Jun 02 02:41:59 PM PDT 24
Peak memory 211260 kb
Host smart-a22fb4b8-8d86-49cc-8b45-ed28ca0dbd83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399104560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3399104560
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2941200917
Short name T359
Test name
Test status
Simulation time 54712210681 ps
CPU time 615.29 seconds
Started Jun 02 02:42:01 PM PDT 24
Finished Jun 02 02:52:19 PM PDT 24
Peak memory 217804 kb
Host smart-42abcf62-ee00-468b-b17e-2067089a5c2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941200917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2941200917
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2622553338
Short name T220
Test name
Test status
Simulation time 661335382 ps
CPU time 24.19 seconds
Started Jun 02 02:41:49 PM PDT 24
Finished Jun 02 02:42:13 PM PDT 24
Peak memory 213720 kb
Host smart-6524d12b-98e9-4207-b936-d7fc1e53ca24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622553338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2622553338
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2052427789
Short name T158
Test name
Test status
Simulation time 5110787756 ps
CPU time 25.92 seconds
Started Jun 02 02:41:51 PM PDT 24
Finished Jun 02 02:42:17 PM PDT 24
Peak memory 212724 kb
Host smart-cc59f3ab-5098-4b9f-821f-82145cc3aaa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2052427789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2052427789
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.631018794
Short name T267
Test name
Test status
Simulation time 2377147969 ps
CPU time 29.55 seconds
Started Jun 02 02:41:51 PM PDT 24
Finished Jun 02 02:42:21 PM PDT 24
Peak memory 214756 kb
Host smart-84eb9071-5294-4c60-ac6d-79910c4f878e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631018794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.631018794
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1966446822
Short name T229
Test name
Test status
Simulation time 12396833000 ps
CPU time 73.64 seconds
Started Jun 02 02:41:59 PM PDT 24
Finished Jun 02 02:43:14 PM PDT 24
Peak memory 218680 kb
Host smart-3dac5279-fe66-4786-9666-6afb67edcc2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966446822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1966446822
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2591332045
Short name T243
Test name
Test status
Simulation time 4213429441 ps
CPU time 32.32 seconds
Started Jun 02 02:41:47 PM PDT 24
Finished Jun 02 02:42:20 PM PDT 24
Peak memory 211772 kb
Host smart-d10e7e58-0168-41ea-8b83-6d417ec971bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591332045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2591332045
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.9612128
Short name T318
Test name
Test status
Simulation time 145714265811 ps
CPU time 328.35 seconds
Started Jun 02 02:41:51 PM PDT 24
Finished Jun 02 02:47:20 PM PDT 24
Peak memory 227404 kb
Host smart-16064f63-8082-4fff-a630-7266c4337192
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9612128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_s
ig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_cor
rupt_sig_fatal_chk.9612128
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1562320707
Short name T252
Test name
Test status
Simulation time 15641612608 ps
CPU time 63.98 seconds
Started Jun 02 02:41:58 PM PDT 24
Finished Jun 02 02:43:03 PM PDT 24
Peak memory 213832 kb
Host smart-5d9417f4-7dbb-4e9b-b97c-92a780eb7865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562320707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1562320707
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.909111033
Short name T170
Test name
Test status
Simulation time 1494759855 ps
CPU time 19.68 seconds
Started Jun 02 02:41:49 PM PDT 24
Finished Jun 02 02:42:10 PM PDT 24
Peak memory 212172 kb
Host smart-9379375d-fbe1-4944-98ad-809b1c01e653
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=909111033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.909111033
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.359762321
Short name T279
Test name
Test status
Simulation time 4217020481 ps
CPU time 39.44 seconds
Started Jun 02 02:41:51 PM PDT 24
Finished Jun 02 02:42:31 PM PDT 24
Peak memory 217676 kb
Host smart-be21a004-269a-4008-8f15-2599923bf161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359762321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.359762321
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3791283312
Short name T298
Test name
Test status
Simulation time 12374003194 ps
CPU time 58.75 seconds
Started Jun 02 02:42:01 PM PDT 24
Finished Jun 02 02:43:02 PM PDT 24
Peak memory 219380 kb
Host smart-976433a1-4353-4308-9dfa-0a0e48e71d69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791283312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3791283312
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2846224987
Short name T60
Test name
Test status
Simulation time 688943821 ps
CPU time 8.49 seconds
Started Jun 02 02:41:53 PM PDT 24
Finished Jun 02 02:42:02 PM PDT 24
Peak memory 211320 kb
Host smart-f21653e1-b75a-461f-82fc-b1237609d353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846224987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2846224987
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.4199004660
Short name T357
Test name
Test status
Simulation time 19319203917 ps
CPU time 219.28 seconds
Started Jun 02 02:41:51 PM PDT 24
Finished Jun 02 02:45:31 PM PDT 24
Peak memory 240052 kb
Host smart-70eb0895-de71-4558-b19d-16847c914981
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199004660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.4199004660
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1034650046
Short name T23
Test name
Test status
Simulation time 34858576757 ps
CPU time 69.58 seconds
Started Jun 02 02:41:59 PM PDT 24
Finished Jun 02 02:43:11 PM PDT 24
Peak memory 215072 kb
Host smart-54be9c04-c9dc-4bad-af4e-498384c1785d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034650046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1034650046
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1530553366
Short name T264
Test name
Test status
Simulation time 9071887971 ps
CPU time 31.77 seconds
Started Jun 02 02:41:52 PM PDT 24
Finished Jun 02 02:42:24 PM PDT 24
Peak memory 211908 kb
Host smart-6f868819-2f66-4313-a13c-f9fdf14209b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1530553366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1530553366
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2299868484
Short name T236
Test name
Test status
Simulation time 17990674578 ps
CPU time 45.43 seconds
Started Jun 02 02:41:56 PM PDT 24
Finished Jun 02 02:42:42 PM PDT 24
Peak memory 217976 kb
Host smart-151a06b7-f92c-4cc5-b945-d4caef6cade3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299868484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2299868484
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1953332722
Short name T356
Test name
Test status
Simulation time 41786074907 ps
CPU time 145.34 seconds
Started Jun 02 02:42:01 PM PDT 24
Finished Jun 02 02:44:29 PM PDT 24
Peak memory 220752 kb
Host smart-0f629b3a-b4c0-43eb-b357-d2096217b138
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953332722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1953332722
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.4234565384
Short name T214
Test name
Test status
Simulation time 4299901688 ps
CPU time 30.19 seconds
Started Jun 02 02:41:57 PM PDT 24
Finished Jun 02 02:42:29 PM PDT 24
Peak memory 211572 kb
Host smart-4202d257-797d-432c-94f5-0d2bc18730a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234565384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.4234565384
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3239940049
Short name T299
Test name
Test status
Simulation time 8257162809 ps
CPU time 224.93 seconds
Started Jun 02 02:41:50 PM PDT 24
Finished Jun 02 02:45:36 PM PDT 24
Peak memory 240780 kb
Host smart-716d94e1-fdee-4431-a6d6-e1dfb0b042e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239940049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3239940049
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2848176197
Short name T19
Test name
Test status
Simulation time 336052162 ps
CPU time 19.82 seconds
Started Jun 02 02:41:53 PM PDT 24
Finished Jun 02 02:42:13 PM PDT 24
Peak memory 215048 kb
Host smart-d9adb53d-e036-4a4d-896a-2cd35f7ad3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848176197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2848176197
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1369308497
Short name T328
Test name
Test status
Simulation time 3825321250 ps
CPU time 31.74 seconds
Started Jun 02 02:41:56 PM PDT 24
Finished Jun 02 02:42:28 PM PDT 24
Peak memory 211256 kb
Host smart-8bf16019-5a38-477c-8a5a-1c5c16b748b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1369308497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1369308497
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3863009848
Short name T3
Test name
Test status
Simulation time 9162879057 ps
CPU time 48.02 seconds
Started Jun 02 02:42:01 PM PDT 24
Finished Jun 02 02:42:51 PM PDT 24
Peak memory 218100 kb
Host smart-7e3c2294-7fda-41e1-9ab1-76fd4fda969e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863009848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3863009848
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1268971307
Short name T132
Test name
Test status
Simulation time 7720364705 ps
CPU time 105.25 seconds
Started Jun 02 02:41:57 PM PDT 24
Finished Jun 02 02:43:43 PM PDT 24
Peak memory 219628 kb
Host smart-f0b4e57d-ee93-421c-99d6-aabdf927186d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268971307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1268971307
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2216025010
Short name T325
Test name
Test status
Simulation time 167501555 ps
CPU time 8.36 seconds
Started Jun 02 02:41:49 PM PDT 24
Finished Jun 02 02:41:58 PM PDT 24
Peak memory 211260 kb
Host smart-2572b7d2-9d68-4bcf-8c65-dc9f663047d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216025010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2216025010
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4219310963
Short name T215
Test name
Test status
Simulation time 3453323340 ps
CPU time 226.64 seconds
Started Jun 02 02:41:59 PM PDT 24
Finished Jun 02 02:45:48 PM PDT 24
Peak memory 237820 kb
Host smart-f87adb37-5d9b-4be6-89ae-f20458146320
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219310963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.4219310963
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3706115251
Short name T312
Test name
Test status
Simulation time 111359819168 ps
CPU time 53.59 seconds
Started Jun 02 02:42:02 PM PDT 24
Finished Jun 02 02:42:57 PM PDT 24
Peak memory 215128 kb
Host smart-6dc736fa-b5f6-4366-88e8-30cdf360a740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706115251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3706115251
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.4181483299
Short name T147
Test name
Test status
Simulation time 181459693 ps
CPU time 10.42 seconds
Started Jun 02 02:41:52 PM PDT 24
Finished Jun 02 02:42:03 PM PDT 24
Peak memory 212532 kb
Host smart-69cacb22-e2ee-4c69-a368-a8b34844d08b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4181483299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.4181483299
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.290376526
Short name T173
Test name
Test status
Simulation time 35027239920 ps
CPU time 77.56 seconds
Started Jun 02 02:41:51 PM PDT 24
Finished Jun 02 02:43:10 PM PDT 24
Peak memory 218168 kb
Host smart-6bb082ba-0ad8-46ef-93b8-0f9150d24f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290376526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.290376526
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1801376277
Short name T201
Test name
Test status
Simulation time 2406282150 ps
CPU time 74.08 seconds
Started Jun 02 02:42:01 PM PDT 24
Finished Jun 02 02:43:17 PM PDT 24
Peak memory 227524 kb
Host smart-d9adf1fc-e479-4dcd-a846-27b78df8a3d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801376277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1801376277
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3682486649
Short name T263
Test name
Test status
Simulation time 44877481071 ps
CPU time 32.63 seconds
Started Jun 02 02:41:10 PM PDT 24
Finished Jun 02 02:41:43 PM PDT 24
Peak memory 212248 kb
Host smart-de3cc252-a3b6-4bed-b202-e26a5438fd58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682486649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3682486649
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.790954068
Short name T193
Test name
Test status
Simulation time 157915421116 ps
CPU time 421.09 seconds
Started Jun 02 02:41:13 PM PDT 24
Finished Jun 02 02:48:14 PM PDT 24
Peak memory 228912 kb
Host smart-e470c234-d349-4dad-80d0-f66fb1e67a1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790954068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.790954068
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1782967470
Short name T253
Test name
Test status
Simulation time 7010603777 ps
CPU time 42.38 seconds
Started Jun 02 02:41:11 PM PDT 24
Finished Jun 02 02:41:55 PM PDT 24
Peak memory 215168 kb
Host smart-8d4c3429-6588-457f-a019-82509f610097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782967470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1782967470
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.4013669716
Short name T271
Test name
Test status
Simulation time 10155758058 ps
CPU time 26.29 seconds
Started Jun 02 02:41:10 PM PDT 24
Finished Jun 02 02:41:37 PM PDT 24
Peak memory 211984 kb
Host smart-5f78b8c5-2566-4eea-943d-ab21610baaf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4013669716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.4013669716
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3158888492
Short name T30
Test name
Test status
Simulation time 521208704 ps
CPU time 232.37 seconds
Started Jun 02 02:41:10 PM PDT 24
Finished Jun 02 02:45:03 PM PDT 24
Peak memory 238076 kb
Host smart-ef6c232a-8368-4a7c-9f16-3eab9cd4cbf4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158888492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3158888492
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.4108256293
Short name T254
Test name
Test status
Simulation time 25540571433 ps
CPU time 59.18 seconds
Started Jun 02 02:41:13 PM PDT 24
Finished Jun 02 02:42:13 PM PDT 24
Peak memory 217668 kb
Host smart-e914f40e-b711-4f5c-bd3d-faa70b8be63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108256293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.4108256293
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1559094864
Short name T57
Test name
Test status
Simulation time 2414189792 ps
CPU time 31.57 seconds
Started Jun 02 02:41:12 PM PDT 24
Finished Jun 02 02:41:44 PM PDT 24
Peak memory 219344 kb
Host smart-1fcee505-1a92-4cb2-ac2d-822e943574ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559094864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1559094864
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1886529480
Short name T137
Test name
Test status
Simulation time 2492298307 ps
CPU time 24.22 seconds
Started Jun 02 02:42:00 PM PDT 24
Finished Jun 02 02:42:26 PM PDT 24
Peak memory 211788 kb
Host smart-c4a3cbc7-cdfb-4fde-8254-e2d0f21570b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886529480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1886529480
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3078404513
Short name T240
Test name
Test status
Simulation time 68533955829 ps
CPU time 316.41 seconds
Started Jun 02 02:41:51 PM PDT 24
Finished Jun 02 02:47:08 PM PDT 24
Peak memory 239116 kb
Host smart-c4e911ce-d6ff-445f-b9b8-dd8d156ce5af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078404513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3078404513
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1360380048
Short name T10
Test name
Test status
Simulation time 8798914475 ps
CPU time 56.14 seconds
Started Jun 02 02:41:51 PM PDT 24
Finished Jun 02 02:42:48 PM PDT 24
Peak memory 215188 kb
Host smart-aef2fde2-f51c-472b-a797-3d8ff2fdc222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360380048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1360380048
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3022815412
Short name T142
Test name
Test status
Simulation time 8322538163 ps
CPU time 34.36 seconds
Started Jun 02 02:41:56 PM PDT 24
Finished Jun 02 02:42:32 PM PDT 24
Peak memory 211428 kb
Host smart-8e07945c-783a-4613-b267-ca6b4a60c940
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3022815412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3022815412
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2550326018
Short name T334
Test name
Test status
Simulation time 28091589720 ps
CPU time 76.97 seconds
Started Jun 02 02:41:56 PM PDT 24
Finished Jun 02 02:43:14 PM PDT 24
Peak memory 216808 kb
Host smart-3dfe3b30-c3c5-47d2-9438-9bece00a5856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550326018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2550326018
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2692519081
Short name T174
Test name
Test status
Simulation time 24699312460 ps
CPU time 77.03 seconds
Started Jun 02 02:41:58 PM PDT 24
Finished Jun 02 02:43:17 PM PDT 24
Peak memory 219396 kb
Host smart-fc55bc67-2970-4e61-84b8-82dbf03de113
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692519081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2692519081
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.121170992
Short name T15
Test name
Test status
Simulation time 213100485588 ps
CPU time 2088.67 seconds
Started Jun 02 02:41:58 PM PDT 24
Finished Jun 02 03:16:48 PM PDT 24
Peak memory 244096 kb
Host smart-5df16732-8b02-4f3f-a945-d7aa8a6349f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121170992 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.121170992
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1612390247
Short name T234
Test name
Test status
Simulation time 1059475098 ps
CPU time 15.68 seconds
Started Jun 02 02:42:01 PM PDT 24
Finished Jun 02 02:42:18 PM PDT 24
Peak memory 211244 kb
Host smart-7f433821-b866-4a61-936f-41e49d948446
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612390247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1612390247
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1285906402
Short name T184
Test name
Test status
Simulation time 99283238307 ps
CPU time 706.32 seconds
Started Jun 02 02:41:58 PM PDT 24
Finished Jun 02 02:53:46 PM PDT 24
Peak memory 240412 kb
Host smart-1ed77e15-c5f0-4492-abe3-c14d1ef6b8ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285906402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1285906402
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2857963086
Short name T329
Test name
Test status
Simulation time 7071011964 ps
CPU time 61.17 seconds
Started Jun 02 02:42:03 PM PDT 24
Finished Jun 02 02:43:06 PM PDT 24
Peak memory 215052 kb
Host smart-7417bab4-159c-40f7-ad29-1f0b5824445f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857963086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2857963086
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3867938089
Short name T266
Test name
Test status
Simulation time 1384351153 ps
CPU time 14.62 seconds
Started Jun 02 02:42:02 PM PDT 24
Finished Jun 02 02:42:18 PM PDT 24
Peak memory 211332 kb
Host smart-a30f42fc-8654-464c-87eb-d14dafab1e4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3867938089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3867938089
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1067346267
Short name T295
Test name
Test status
Simulation time 29229982344 ps
CPU time 66.13 seconds
Started Jun 02 02:41:59 PM PDT 24
Finished Jun 02 02:43:07 PM PDT 24
Peak memory 217700 kb
Host smart-b18cc014-e5b0-4e77-8e69-d1ed6df49117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067346267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1067346267
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.4243154969
Short name T288
Test name
Test status
Simulation time 12183853603 ps
CPU time 37.09 seconds
Started Jun 02 02:41:57 PM PDT 24
Finished Jun 02 02:42:36 PM PDT 24
Peak memory 218856 kb
Host smart-7ccbc0e9-3f56-4e6f-a955-192d6356b9dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243154969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.4243154969
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1079499471
Short name T350
Test name
Test status
Simulation time 3575590892 ps
CPU time 29.62 seconds
Started Jun 02 02:41:57 PM PDT 24
Finished Jun 02 02:42:29 PM PDT 24
Peak memory 211868 kb
Host smart-bcff7084-436b-44d7-b88d-36f6a33ddf11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079499471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1079499471
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.307195283
Short name T366
Test name
Test status
Simulation time 66046115480 ps
CPU time 376.34 seconds
Started Jun 02 02:42:00 PM PDT 24
Finished Jun 02 02:48:18 PM PDT 24
Peak memory 230136 kb
Host smart-8628a29c-bd75-477d-9f09-50fee16c7b87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307195283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.307195283
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2020387308
Short name T305
Test name
Test status
Simulation time 18434804002 ps
CPU time 46.6 seconds
Started Jun 02 02:41:57 PM PDT 24
Finished Jun 02 02:42:45 PM PDT 24
Peak memory 215144 kb
Host smart-ae1aac95-e645-419f-b6c9-0de2d8af6609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020387308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2020387308
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1075435407
Short name T42
Test name
Test status
Simulation time 11780070619 ps
CPU time 21.36 seconds
Started Jun 02 02:42:00 PM PDT 24
Finished Jun 02 02:42:23 PM PDT 24
Peak memory 211388 kb
Host smart-42153e5b-20e7-4d6c-b2e2-b766e6e67d3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1075435407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1075435407
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.4271037535
Short name T130
Test name
Test status
Simulation time 354206196 ps
CPU time 19.94 seconds
Started Jun 02 02:41:59 PM PDT 24
Finished Jun 02 02:42:21 PM PDT 24
Peak memory 215124 kb
Host smart-3f5266ce-a7ce-42af-9683-042fe2b9aec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271037535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.4271037535
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2472284626
Short name T347
Test name
Test status
Simulation time 26934194705 ps
CPU time 64.27 seconds
Started Jun 02 02:42:00 PM PDT 24
Finished Jun 02 02:43:06 PM PDT 24
Peak memory 219296 kb
Host smart-d2253fd3-d6ca-493f-b155-342f1401112a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472284626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2472284626
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.4264666113
Short name T213
Test name
Test status
Simulation time 15776322416 ps
CPU time 33.38 seconds
Started Jun 02 02:42:01 PM PDT 24
Finished Jun 02 02:42:36 PM PDT 24
Peak memory 212364 kb
Host smart-2bb0c6ee-b60e-4250-a450-67e4ff8cb2bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264666113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.4264666113
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1314870456
Short name T172
Test name
Test status
Simulation time 57826213253 ps
CPU time 607.69 seconds
Started Jun 02 02:41:59 PM PDT 24
Finished Jun 02 02:52:08 PM PDT 24
Peak memory 233912 kb
Host smart-56a3e2ec-f57e-4e02-a0de-f5c3ebf16c26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314870456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1314870456
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3145293716
Short name T353
Test name
Test status
Simulation time 15577376304 ps
CPU time 38.82 seconds
Started Jun 02 02:41:59 PM PDT 24
Finished Jun 02 02:42:39 PM PDT 24
Peak memory 215096 kb
Host smart-24fd3d54-423c-4242-9410-d5f66807a698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145293716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3145293716
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.452149332
Short name T257
Test name
Test status
Simulation time 181492766 ps
CPU time 10.68 seconds
Started Jun 02 02:42:01 PM PDT 24
Finished Jun 02 02:42:13 PM PDT 24
Peak memory 212432 kb
Host smart-1a0b2781-7213-47a8-9422-8ffecd7f991e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=452149332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.452149332
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1559792737
Short name T155
Test name
Test status
Simulation time 7791575248 ps
CPU time 64.91 seconds
Started Jun 02 02:41:59 PM PDT 24
Finished Jun 02 02:43:06 PM PDT 24
Peak memory 218660 kb
Host smart-159fe263-88d1-4c85-9e99-521beb44a772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559792737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1559792737
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3226113866
Short name T309
Test name
Test status
Simulation time 4538239220 ps
CPU time 47.94 seconds
Started Jun 02 02:42:01 PM PDT 24
Finished Jun 02 02:42:52 PM PDT 24
Peak memory 217524 kb
Host smart-d7dcf210-881b-4489-986f-62cd0a2d9642
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226113866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3226113866
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3372246713
Short name T187
Test name
Test status
Simulation time 16711576841 ps
CPU time 33.71 seconds
Started Jun 02 02:41:57 PM PDT 24
Finished Jun 02 02:42:33 PM PDT 24
Peak memory 212140 kb
Host smart-3083981f-cce6-4837-a177-aaabf4d724a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372246713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3372246713
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2724435140
Short name T327
Test name
Test status
Simulation time 179955477796 ps
CPU time 898.81 seconds
Started Jun 02 02:42:00 PM PDT 24
Finished Jun 02 02:57:01 PM PDT 24
Peak memory 240536 kb
Host smart-a5a1a86b-965c-48b9-b14b-6dcfc2e6a6da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724435140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2724435140
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2920512564
Short name T275
Test name
Test status
Simulation time 72107563493 ps
CPU time 45.36 seconds
Started Jun 02 02:41:58 PM PDT 24
Finished Jun 02 02:42:45 PM PDT 24
Peak memory 215076 kb
Host smart-0898f9c6-ab09-413b-9f80-84ab9eda22fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920512564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2920512564
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1682780234
Short name T216
Test name
Test status
Simulation time 515332758 ps
CPU time 12 seconds
Started Jun 02 02:41:58 PM PDT 24
Finished Jun 02 02:42:12 PM PDT 24
Peak memory 212312 kb
Host smart-f5476caf-8408-4a0d-aed9-b31796e36531
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1682780234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1682780234
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3789647059
Short name T121
Test name
Test status
Simulation time 16076857235 ps
CPU time 71.16 seconds
Started Jun 02 02:41:59 PM PDT 24
Finished Jun 02 02:43:13 PM PDT 24
Peak memory 217756 kb
Host smart-451c3acc-229b-4e99-b2f1-72088f29167d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789647059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3789647059
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3431538618
Short name T274
Test name
Test status
Simulation time 1101312799 ps
CPU time 30.74 seconds
Started Jun 02 02:42:01 PM PDT 24
Finished Jun 02 02:42:34 PM PDT 24
Peak memory 219200 kb
Host smart-99acce22-5549-439a-ac62-f628c61f9bd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431538618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3431538618
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.453017671
Short name T261
Test name
Test status
Simulation time 8885244746 ps
CPU time 22.62 seconds
Started Jun 02 02:42:04 PM PDT 24
Finished Jun 02 02:42:27 PM PDT 24
Peak memory 212360 kb
Host smart-9fb42eb2-b875-45aa-99b3-284077a2fae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453017671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.453017671
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3679052869
Short name T25
Test name
Test status
Simulation time 12865387667 ps
CPU time 193.69 seconds
Started Jun 02 02:41:57 PM PDT 24
Finished Jun 02 02:45:13 PM PDT 24
Peak memory 228940 kb
Host smart-0b67b4ac-f242-4813-92f6-124b41709fb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679052869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3679052869
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3749038635
Short name T286
Test name
Test status
Simulation time 3973395317 ps
CPU time 44.34 seconds
Started Jun 02 02:42:00 PM PDT 24
Finished Jun 02 02:42:46 PM PDT 24
Peak memory 214928 kb
Host smart-ba28cb15-f52d-4a7a-bc91-c8a466ad4d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749038635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3749038635
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.654140428
Short name T210
Test name
Test status
Simulation time 3008554123 ps
CPU time 27.06 seconds
Started Jun 02 02:42:00 PM PDT 24
Finished Jun 02 02:42:29 PM PDT 24
Peak memory 211320 kb
Host smart-f8ac5e9b-108c-48ca-8cd1-91fd1654bbe7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=654140428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.654140428
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.342728027
Short name T35
Test name
Test status
Simulation time 19740041859 ps
CPU time 56.78 seconds
Started Jun 02 02:41:59 PM PDT 24
Finished Jun 02 02:42:58 PM PDT 24
Peak memory 218212 kb
Host smart-35d79145-dd2b-436c-9674-5a6fa1039b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342728027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.342728027
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2961067756
Short name T272
Test name
Test status
Simulation time 5267388163 ps
CPU time 36.2 seconds
Started Jun 02 02:42:00 PM PDT 24
Finished Jun 02 02:42:38 PM PDT 24
Peak memory 218928 kb
Host smart-cee7d241-4024-49c2-a20f-7dc8c2033c35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961067756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2961067756
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1364371803
Short name T235
Test name
Test status
Simulation time 7969646224 ps
CPU time 32.56 seconds
Started Jun 02 02:42:03 PM PDT 24
Finished Jun 02 02:42:37 PM PDT 24
Peak memory 212052 kb
Host smart-82e59cd3-9492-42ff-879a-a1991c79362c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364371803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1364371803
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1092442732
Short name T336
Test name
Test status
Simulation time 35531105978 ps
CPU time 257.74 seconds
Started Jun 02 02:41:58 PM PDT 24
Finished Jun 02 02:46:17 PM PDT 24
Peak memory 240236 kb
Host smart-1b287512-0fe3-480f-a05a-28d57d3eea68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092442732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1092442732
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2828327377
Short name T178
Test name
Test status
Simulation time 7498640520 ps
CPU time 31.69 seconds
Started Jun 02 02:41:58 PM PDT 24
Finished Jun 02 02:42:31 PM PDT 24
Peak memory 215240 kb
Host smart-16ac2136-bb74-409b-a0cd-eb4c90227a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828327377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2828327377
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1810072950
Short name T209
Test name
Test status
Simulation time 761994127 ps
CPU time 10.5 seconds
Started Jun 02 02:41:59 PM PDT 24
Finished Jun 02 02:42:11 PM PDT 24
Peak memory 212612 kb
Host smart-cdbf8284-2c12-4a59-84e8-6b7ef789a2e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1810072950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1810072950
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1334515518
Short name T160
Test name
Test status
Simulation time 2088433078 ps
CPU time 26.54 seconds
Started Jun 02 02:42:01 PM PDT 24
Finished Jun 02 02:42:29 PM PDT 24
Peak memory 216760 kb
Host smart-4d8d3efe-049f-4b3f-87dd-798dd0f7db61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334515518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1334515518
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.582901118
Short name T365
Test name
Test status
Simulation time 42852929451 ps
CPU time 100.96 seconds
Started Jun 02 02:41:58 PM PDT 24
Finished Jun 02 02:43:41 PM PDT 24
Peak memory 219420 kb
Host smart-51602783-0cf1-486d-9c07-d4e0d821534a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582901118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.582901118
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3838653092
Short name T126
Test name
Test status
Simulation time 70258327950 ps
CPU time 30.78 seconds
Started Jun 02 02:41:58 PM PDT 24
Finished Jun 02 02:42:31 PM PDT 24
Peak memory 212196 kb
Host smart-ac23bcc9-a463-4792-ae43-53af97149d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838653092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3838653092
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.850305320
Short name T21
Test name
Test status
Simulation time 227837519548 ps
CPU time 232.14 seconds
Started Jun 02 02:41:59 PM PDT 24
Finished Jun 02 02:45:53 PM PDT 24
Peak memory 217472 kb
Host smart-f9aa9227-0f30-4540-ab2a-44bc31402175
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850305320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.850305320
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.4180980678
Short name T146
Test name
Test status
Simulation time 7007043354 ps
CPU time 59.37 seconds
Started Jun 02 02:42:02 PM PDT 24
Finished Jun 02 02:43:03 PM PDT 24
Peak memory 214656 kb
Host smart-c9e9f01b-919b-4df4-b848-f8c63aa4f71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180980678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.4180980678
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1987249052
Short name T307
Test name
Test status
Simulation time 18134933283 ps
CPU time 27.12 seconds
Started Jun 02 02:41:59 PM PDT 24
Finished Jun 02 02:42:28 PM PDT 24
Peak memory 211784 kb
Host smart-5d688795-f55e-4b63-9ec2-050c1cca1a87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1987249052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1987249052
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3117942594
Short name T296
Test name
Test status
Simulation time 12739187968 ps
CPU time 60.12 seconds
Started Jun 02 02:41:58 PM PDT 24
Finished Jun 02 02:43:00 PM PDT 24
Peak memory 217648 kb
Host smart-33ac52b8-3de7-40e4-8a15-d8c64cd0f922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117942594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3117942594
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3319876555
Short name T227
Test name
Test status
Simulation time 11223594401 ps
CPU time 65.86 seconds
Started Jun 02 02:42:01 PM PDT 24
Finished Jun 02 02:43:09 PM PDT 24
Peak memory 219320 kb
Host smart-14f247cf-7233-4f2e-97f4-0b23923871c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319876555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3319876555
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1283722761
Short name T362
Test name
Test status
Simulation time 4360797927 ps
CPU time 34.27 seconds
Started Jun 02 02:42:02 PM PDT 24
Finished Jun 02 02:42:38 PM PDT 24
Peak memory 212284 kb
Host smart-3282f6c3-2a4c-4e15-9765-9a99b2e7f3b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283722761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1283722761
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1643041274
Short name T43
Test name
Test status
Simulation time 274011909986 ps
CPU time 380.91 seconds
Started Jun 02 02:42:01 PM PDT 24
Finished Jun 02 02:48:24 PM PDT 24
Peak memory 216736 kb
Host smart-15e0595b-74f8-4321-a21d-57ef9dec8ddd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643041274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1643041274
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3473256377
Short name T154
Test name
Test status
Simulation time 339482106 ps
CPU time 18.96 seconds
Started Jun 02 02:42:06 PM PDT 24
Finished Jun 02 02:42:25 PM PDT 24
Peak memory 214716 kb
Host smart-a5693adf-ee72-4893-8904-0b24e58c4699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473256377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3473256377
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.938291378
Short name T244
Test name
Test status
Simulation time 183045454 ps
CPU time 10.37 seconds
Started Jun 02 02:42:06 PM PDT 24
Finished Jun 02 02:42:17 PM PDT 24
Peak memory 212272 kb
Host smart-2f992071-2516-4c4f-8d03-3f4122d6f161
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=938291378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.938291378
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.324905642
Short name T289
Test name
Test status
Simulation time 27581423707 ps
CPU time 57.16 seconds
Started Jun 02 02:41:59 PM PDT 24
Finished Jun 02 02:42:58 PM PDT 24
Peak memory 217828 kb
Host smart-a388b11b-7c87-443e-9b60-44f2bed9ae99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324905642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.324905642
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.4128680325
Short name T195
Test name
Test status
Simulation time 26842731997 ps
CPU time 86.14 seconds
Started Jun 02 02:42:01 PM PDT 24
Finished Jun 02 02:43:29 PM PDT 24
Peak memory 221116 kb
Host smart-a84129e6-7840-4d61-b273-0c95d7f78586
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128680325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.4128680325
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2675214167
Short name T290
Test name
Test status
Simulation time 13567793557 ps
CPU time 28.72 seconds
Started Jun 02 02:42:02 PM PDT 24
Finished Jun 02 02:42:32 PM PDT 24
Peak memory 212248 kb
Host smart-b58ad74a-84ba-47de-bee5-877af085cd6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675214167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2675214167
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3473955809
Short name T256
Test name
Test status
Simulation time 36452991120 ps
CPU time 629.21 seconds
Started Jun 02 02:42:05 PM PDT 24
Finished Jun 02 02:52:35 PM PDT 24
Peak memory 219656 kb
Host smart-5ecde4bb-8a95-4f00-9db2-a04630f6620b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473955809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3473955809
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.553738725
Short name T18
Test name
Test status
Simulation time 1435221245 ps
CPU time 19.5 seconds
Started Jun 02 02:42:06 PM PDT 24
Finished Jun 02 02:42:26 PM PDT 24
Peak memory 214864 kb
Host smart-460a18e2-5c1e-4421-a661-a5fc715a1e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553738725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.553738725
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2650296522
Short name T124
Test name
Test status
Simulation time 2079836759 ps
CPU time 23.13 seconds
Started Jun 02 02:42:06 PM PDT 24
Finished Jun 02 02:42:30 PM PDT 24
Peak memory 212380 kb
Host smart-ee9c6551-f15a-4dac-b968-9770265420ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2650296522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2650296522
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3317110126
Short name T76
Test name
Test status
Simulation time 841746102 ps
CPU time 26.7 seconds
Started Jun 02 02:42:02 PM PDT 24
Finished Jun 02 02:42:30 PM PDT 24
Peak memory 217088 kb
Host smart-af6d0cc8-7870-4ab4-aadc-b7f30fdbae28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317110126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3317110126
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2272199113
Short name T167
Test name
Test status
Simulation time 34306346333 ps
CPU time 100.33 seconds
Started Jun 02 02:42:01 PM PDT 24
Finished Jun 02 02:43:43 PM PDT 24
Peak memory 219452 kb
Host smart-d11abb71-bac9-43af-8f4d-62f4653f79c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272199113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2272199113
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.458089200
Short name T310
Test name
Test status
Simulation time 4190779454 ps
CPU time 22.18 seconds
Started Jun 02 02:41:24 PM PDT 24
Finished Jun 02 02:41:47 PM PDT 24
Peak memory 211656 kb
Host smart-4a03a52c-4125-40f9-8388-7d2aa0d8bdbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458089200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.458089200
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1334471577
Short name T212
Test name
Test status
Simulation time 33779508542 ps
CPU time 386.24 seconds
Started Jun 02 02:41:17 PM PDT 24
Finished Jun 02 02:47:44 PM PDT 24
Peak memory 236920 kb
Host smart-6aeb9667-cc8e-4eee-9bc8-675f074483e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334471577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1334471577
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3025548320
Short name T143
Test name
Test status
Simulation time 55512493787 ps
CPU time 65.62 seconds
Started Jun 02 02:41:19 PM PDT 24
Finished Jun 02 02:42:26 PM PDT 24
Peak memory 215120 kb
Host smart-23c098af-0150-4f7b-b0cd-bb05a25843f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025548320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3025548320
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.250589011
Short name T363
Test name
Test status
Simulation time 755684028 ps
CPU time 15.84 seconds
Started Jun 02 02:41:20 PM PDT 24
Finished Jun 02 02:41:37 PM PDT 24
Peak memory 212292 kb
Host smart-cae63db1-06fa-400e-97fc-3015de3df6e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=250589011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.250589011
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3433141338
Short name T311
Test name
Test status
Simulation time 22476653168 ps
CPU time 78.15 seconds
Started Jun 02 02:41:10 PM PDT 24
Finished Jun 02 02:42:29 PM PDT 24
Peak memory 217200 kb
Host smart-f13bcd09-d701-4744-9be1-2dcca8c139d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433141338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3433141338
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2690191445
Short name T164
Test name
Test status
Simulation time 16463821633 ps
CPU time 43.15 seconds
Started Jun 02 02:41:11 PM PDT 24
Finished Jun 02 02:41:55 PM PDT 24
Peak memory 218436 kb
Host smart-f29f3ea3-a61b-49a0-aa3b-b74141a98f24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690191445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2690191445
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1602834217
Short name T41
Test name
Test status
Simulation time 19843836360 ps
CPU time 31.03 seconds
Started Jun 02 02:41:21 PM PDT 24
Finished Jun 02 02:41:52 PM PDT 24
Peak memory 212248 kb
Host smart-313c831a-be89-4c40-b1c3-4f29d765b5f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602834217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1602834217
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1705399528
Short name T232
Test name
Test status
Simulation time 15339966883 ps
CPU time 302.65 seconds
Started Jun 02 02:41:18 PM PDT 24
Finished Jun 02 02:46:21 PM PDT 24
Peak memory 239924 kb
Host smart-64b3dd0e-a3d4-4c01-8ce0-fd2982756e15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705399528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1705399528
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1738901323
Short name T17
Test name
Test status
Simulation time 2067409135 ps
CPU time 19.48 seconds
Started Jun 02 02:41:18 PM PDT 24
Finished Jun 02 02:41:38 PM PDT 24
Peak memory 215264 kb
Host smart-9190394c-3cfb-4ccd-8e70-2cb23e415159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738901323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1738901323
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2317629146
Short name T38
Test name
Test status
Simulation time 6103327310 ps
CPU time 34.2 seconds
Started Jun 02 02:41:21 PM PDT 24
Finished Jun 02 02:41:56 PM PDT 24
Peak memory 212600 kb
Host smart-205e826a-396e-4427-8db2-138a31369ace
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2317629146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2317629146
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.387402855
Short name T326
Test name
Test status
Simulation time 51103856863 ps
CPU time 54.56 seconds
Started Jun 02 02:41:23 PM PDT 24
Finished Jun 02 02:42:18 PM PDT 24
Peak memory 218128 kb
Host smart-03820765-cf82-4e81-a026-611d3170a8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387402855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.387402855
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2259242536
Short name T128
Test name
Test status
Simulation time 25113197371 ps
CPU time 112.1 seconds
Started Jun 02 02:41:17 PM PDT 24
Finished Jun 02 02:43:10 PM PDT 24
Peak memory 216120 kb
Host smart-2b47c33a-bf2b-4e6c-b627-884438abeca8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259242536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2259242536
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3764734555
Short name T346
Test name
Test status
Simulation time 3754557256 ps
CPU time 21.18 seconds
Started Jun 02 02:41:18 PM PDT 24
Finished Jun 02 02:41:41 PM PDT 24
Peak memory 211400 kb
Host smart-f69768c7-94d0-409d-a53a-5da24b1f7ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764734555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3764734555
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3464347397
Short name T159
Test name
Test status
Simulation time 169124934267 ps
CPU time 202.86 seconds
Started Jun 02 02:41:17 PM PDT 24
Finished Jun 02 02:44:40 PM PDT 24
Peak memory 239996 kb
Host smart-1f7724c4-a18f-4cd9-a097-36a068f90b92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464347397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3464347397
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.4085517032
Short name T281
Test name
Test status
Simulation time 662315194 ps
CPU time 19.25 seconds
Started Jun 02 02:41:18 PM PDT 24
Finished Jun 02 02:41:39 PM PDT 24
Peak memory 214840 kb
Host smart-b474afc2-02ee-43d9-8cef-3414b92559fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085517032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.4085517032
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2007995617
Short name T101
Test name
Test status
Simulation time 975051918 ps
CPU time 10.55 seconds
Started Jun 02 02:41:18 PM PDT 24
Finished Jun 02 02:41:30 PM PDT 24
Peak memory 212240 kb
Host smart-6d3d036f-7492-4df3-ba09-30c935ab21b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2007995617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2007995617
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1990700164
Short name T166
Test name
Test status
Simulation time 8268225107 ps
CPU time 48.72 seconds
Started Jun 02 02:41:18 PM PDT 24
Finished Jun 02 02:42:07 PM PDT 24
Peak memory 217164 kb
Host smart-c65aa39e-ae76-472f-9232-be4a2001a776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990700164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1990700164
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.941251515
Short name T324
Test name
Test status
Simulation time 2066836917 ps
CPU time 28.72 seconds
Started Jun 02 02:41:18 PM PDT 24
Finished Jun 02 02:41:47 PM PDT 24
Peak memory 214032 kb
Host smart-7adce23d-9ced-4ed8-a7fa-ada667a46461
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941251515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.941251515
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3867479990
Short name T308
Test name
Test status
Simulation time 174476711 ps
CPU time 8.02 seconds
Started Jun 02 02:41:21 PM PDT 24
Finished Jun 02 02:41:29 PM PDT 24
Peak memory 211312 kb
Host smart-061d805d-d2d7-4325-9cb5-b08e578d9dff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867479990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3867479990
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.105445552
Short name T303
Test name
Test status
Simulation time 6658312280 ps
CPU time 233.63 seconds
Started Jun 02 02:41:19 PM PDT 24
Finished Jun 02 02:45:14 PM PDT 24
Peak memory 240280 kb
Host smart-8c998d0a-7d0b-4d82-b691-4146c1dc3237
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105445552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.105445552
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1815840016
Short name T177
Test name
Test status
Simulation time 15757890207 ps
CPU time 46.57 seconds
Started Jun 02 02:41:29 PM PDT 24
Finished Jun 02 02:42:17 PM PDT 24
Peak memory 215744 kb
Host smart-1749bcdb-7500-4fbf-ab93-98fd3dbedb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815840016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1815840016
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1720990650
Short name T355
Test name
Test status
Simulation time 749161334 ps
CPU time 15.59 seconds
Started Jun 02 02:41:19 PM PDT 24
Finished Jun 02 02:41:36 PM PDT 24
Peak memory 212304 kb
Host smart-786542da-7852-467c-ad35-238ab94bafca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1720990650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1720990650
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2947991720
Short name T319
Test name
Test status
Simulation time 1363476639 ps
CPU time 20.77 seconds
Started Jun 02 02:41:17 PM PDT 24
Finished Jun 02 02:41:38 PM PDT 24
Peak memory 215784 kb
Host smart-f871d9be-6f14-4d76-b591-1df1a2a88bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947991720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2947991720
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1581608565
Short name T169
Test name
Test status
Simulation time 48185439025 ps
CPU time 162.26 seconds
Started Jun 02 02:41:17 PM PDT 24
Finished Jun 02 02:44:00 PM PDT 24
Peak memory 220304 kb
Host smart-0ca983fe-a553-471c-ad24-d396e4b385c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581608565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1581608565
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1061695851
Short name T315
Test name
Test status
Simulation time 10406448257 ps
CPU time 21.4 seconds
Started Jun 02 02:41:18 PM PDT 24
Finished Jun 02 02:41:41 PM PDT 24
Peak memory 211324 kb
Host smart-eb1c7655-f654-4e5e-88d7-8f3292f311e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061695851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1061695851
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.862951670
Short name T268
Test name
Test status
Simulation time 36064914845 ps
CPU time 255.89 seconds
Started Jun 02 02:41:19 PM PDT 24
Finished Jun 02 02:45:36 PM PDT 24
Peak memory 215768 kb
Host smart-72f2129e-982c-435d-b0e1-b99810cf44d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862951670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.862951670
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4157766128
Short name T185
Test name
Test status
Simulation time 844489446 ps
CPU time 25.66 seconds
Started Jun 02 02:41:24 PM PDT 24
Finished Jun 02 02:41:51 PM PDT 24
Peak memory 214768 kb
Host smart-2029c80d-bfef-4622-8ad4-b8cac96d4673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157766128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.4157766128
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1012945896
Short name T8
Test name
Test status
Simulation time 8224997429 ps
CPU time 22.68 seconds
Started Jun 02 02:41:19 PM PDT 24
Finished Jun 02 02:41:43 PM PDT 24
Peak memory 212628 kb
Host smart-6f52de5c-d8a5-42c5-ab2b-983537e3a05d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1012945896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1012945896
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3553826183
Short name T230
Test name
Test status
Simulation time 734895361 ps
CPU time 19.93 seconds
Started Jun 02 02:41:21 PM PDT 24
Finished Jun 02 02:41:41 PM PDT 24
Peak memory 216504 kb
Host smart-84bd7e87-9c9b-401c-940d-7f5193dfcc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553826183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3553826183
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.758520314
Short name T127
Test name
Test status
Simulation time 29338166519 ps
CPU time 95.16 seconds
Started Jun 02 02:41:19 PM PDT 24
Finished Jun 02 02:42:56 PM PDT 24
Peak memory 220028 kb
Host smart-c7d55956-54ba-43d6-9f94-4defa45f265e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758520314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.758520314
Directory /workspace/9.rom_ctrl_stress_all/latest
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