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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.50 96.97 93.02 97.88 100.00 98.37 97.89 98.37


Total test records in report: 462
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T300 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3793448510 Jun 04 01:41:01 PM PDT 24 Jun 04 01:41:19 PM PDT 24 8268259379 ps
T301 /workspace/coverage/default/42.rom_ctrl_alert_test.1544617420 Jun 04 01:41:01 PM PDT 24 Jun 04 01:41:36 PM PDT 24 16707088581 ps
T302 /workspace/coverage/default/45.rom_ctrl_alert_test.1739106043 Jun 04 01:41:11 PM PDT 24 Jun 04 01:41:20 PM PDT 24 176443623 ps
T303 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3621041987 Jun 04 01:40:08 PM PDT 24 Jun 04 01:42:17 PM PDT 24 3445430585 ps
T304 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1177235134 Jun 04 01:40:54 PM PDT 24 Jun 04 01:41:29 PM PDT 24 16953503795 ps
T305 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.847119141 Jun 04 01:40:28 PM PDT 24 Jun 04 01:41:22 PM PDT 24 10818420236 ps
T306 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2806451506 Jun 04 01:39:57 PM PDT 24 Jun 04 01:52:05 PM PDT 24 266066752466 ps
T307 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4039746006 Jun 04 01:39:57 PM PDT 24 Jun 04 01:40:18 PM PDT 24 2389438498 ps
T308 /workspace/coverage/default/26.rom_ctrl_stress_all.3228076915 Jun 04 01:40:25 PM PDT 24 Jun 04 01:42:00 PM PDT 24 33003110253 ps
T309 /workspace/coverage/default/43.rom_ctrl_stress_all.1666246605 Jun 04 01:41:11 PM PDT 24 Jun 04 01:41:57 PM PDT 24 10042532124 ps
T310 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.530354857 Jun 04 01:40:13 PM PDT 24 Jun 04 01:40:39 PM PDT 24 2532363657 ps
T311 /workspace/coverage/default/28.rom_ctrl_alert_test.3406183290 Jun 04 01:40:34 PM PDT 24 Jun 04 01:40:44 PM PDT 24 175998805 ps
T312 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.696093803 Jun 04 01:40:31 PM PDT 24 Jun 04 01:56:24 PM PDT 24 95432587337 ps
T313 /workspace/coverage/default/20.rom_ctrl_alert_test.3953406723 Jun 04 01:40:27 PM PDT 24 Jun 04 01:40:59 PM PDT 24 7809782058 ps
T314 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1641742624 Jun 04 01:40:43 PM PDT 24 Jun 04 01:41:42 PM PDT 24 6662240019 ps
T315 /workspace/coverage/default/31.rom_ctrl_smoke.1432291331 Jun 04 01:40:36 PM PDT 24 Jun 04 01:41:26 PM PDT 24 5249372734 ps
T316 /workspace/coverage/default/47.rom_ctrl_smoke.1935929146 Jun 04 01:41:12 PM PDT 24 Jun 04 01:42:00 PM PDT 24 8611292430 ps
T317 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4039344305 Jun 04 01:40:13 PM PDT 24 Jun 04 01:45:14 PM PDT 24 78898647928 ps
T318 /workspace/coverage/default/32.rom_ctrl_smoke.2190083186 Jun 04 01:40:37 PM PDT 24 Jun 04 01:41:31 PM PDT 24 4112198303 ps
T33 /workspace/coverage/default/1.rom_ctrl_sec_cm.715871669 Jun 04 01:39:46 PM PDT 24 Jun 04 01:42:07 PM PDT 24 17545298794 ps
T319 /workspace/coverage/default/19.rom_ctrl_stress_all.249933867 Jun 04 01:40:14 PM PDT 24 Jun 04 01:41:22 PM PDT 24 4289896052 ps
T320 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1173161045 Jun 04 01:40:13 PM PDT 24 Jun 04 01:40:34 PM PDT 24 6936386330 ps
T321 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2464996811 Jun 04 01:40:13 PM PDT 24 Jun 04 01:40:44 PM PDT 24 3110754322 ps
T322 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2588894033 Jun 04 01:40:10 PM PDT 24 Jun 04 01:40:23 PM PDT 24 689245591 ps
T323 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1914468427 Jun 04 01:39:52 PM PDT 24 Jun 04 01:46:36 PM PDT 24 125455699719 ps
T324 /workspace/coverage/default/18.rom_ctrl_alert_test.1404001416 Jun 04 01:40:17 PM PDT 24 Jun 04 01:40:50 PM PDT 24 26710698754 ps
T325 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1289910163 Jun 04 01:40:33 PM PDT 24 Jun 04 01:40:50 PM PDT 24 3318449251 ps
T326 /workspace/coverage/default/11.rom_ctrl_alert_test.3784162057 Jun 04 01:40:07 PM PDT 24 Jun 04 01:40:41 PM PDT 24 4464982388 ps
T327 /workspace/coverage/default/31.rom_ctrl_stress_all.3635430344 Jun 04 01:40:37 PM PDT 24 Jun 04 01:41:13 PM PDT 24 8501957847 ps
T328 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4122593640 Jun 04 01:40:16 PM PDT 24 Jun 04 01:49:20 PM PDT 24 413131101111 ps
T329 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1125492110 Jun 04 01:39:46 PM PDT 24 Jun 04 01:40:07 PM PDT 24 1439401659 ps
T330 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2463055230 Jun 04 01:39:55 PM PDT 24 Jun 04 01:40:07 PM PDT 24 182676497 ps
T331 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3887155796 Jun 04 01:39:57 PM PDT 24 Jun 04 01:40:29 PM PDT 24 8008433168 ps
T332 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3115796086 Jun 04 01:40:40 PM PDT 24 Jun 04 01:55:53 PM PDT 24 77681926125 ps
T333 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.689560861 Jun 04 01:40:33 PM PDT 24 Jun 04 01:51:26 PM PDT 24 69875146761 ps
T334 /workspace/coverage/default/23.rom_ctrl_alert_test.2594345286 Jun 04 01:40:25 PM PDT 24 Jun 04 01:40:58 PM PDT 24 14596853726 ps
T335 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1386934347 Jun 04 01:40:25 PM PDT 24 Jun 04 01:41:22 PM PDT 24 31846269150 ps
T336 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2812711738 Jun 04 01:41:00 PM PDT 24 Jun 04 01:47:21 PM PDT 24 45294103062 ps
T337 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3664773041 Jun 04 01:40:42 PM PDT 24 Jun 04 01:41:06 PM PDT 24 502111526 ps
T338 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1636111184 Jun 04 01:39:47 PM PDT 24 Jun 04 01:40:08 PM PDT 24 944761335 ps
T339 /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1906187252 Jun 04 01:39:45 PM PDT 24 Jun 04 02:25:18 PM PDT 24 518590521574 ps
T340 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2239104290 Jun 04 01:39:54 PM PDT 24 Jun 04 01:43:54 PM PDT 24 13151961671 ps
T341 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.4009618017 Jun 04 01:40:05 PM PDT 24 Jun 04 01:40:26 PM PDT 24 1319148528 ps
T342 /workspace/coverage/default/0.rom_ctrl_smoke.2345066628 Jun 04 01:39:53 PM PDT 24 Jun 04 01:40:56 PM PDT 24 6210634791 ps
T343 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3042034782 Jun 04 01:41:02 PM PDT 24 Jun 04 01:41:52 PM PDT 24 4934664615 ps
T344 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3586165355 Jun 04 01:40:14 PM PDT 24 Jun 04 01:41:13 PM PDT 24 38500162521 ps
T345 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.764905196 Jun 04 01:40:09 PM PDT 24 Jun 04 01:49:06 PM PDT 24 33707008864 ps
T346 /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.523789172 Jun 04 01:40:35 PM PDT 24 Jun 04 01:58:01 PM PDT 24 109235522493 ps
T347 /workspace/coverage/default/30.rom_ctrl_smoke.3972143307 Jun 04 01:40:40 PM PDT 24 Jun 04 01:41:01 PM PDT 24 355205678 ps
T34 /workspace/coverage/default/4.rom_ctrl_sec_cm.2278547859 Jun 04 01:39:56 PM PDT 24 Jun 04 01:44:04 PM PDT 24 5485293539 ps
T348 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3281237671 Jun 04 01:40:35 PM PDT 24 Jun 04 01:41:06 PM PDT 24 1531736569 ps
T349 /workspace/coverage/default/27.rom_ctrl_alert_test.3516331977 Jun 04 01:40:28 PM PDT 24 Jun 04 01:40:49 PM PDT 24 14260571127 ps
T350 /workspace/coverage/default/20.rom_ctrl_smoke.4151775042 Jun 04 01:40:26 PM PDT 24 Jun 04 01:41:16 PM PDT 24 11643587798 ps
T351 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2105976273 Jun 04 01:40:17 PM PDT 24 Jun 04 01:49:30 PM PDT 24 87492267538 ps
T352 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.907009669 Jun 04 01:40:24 PM PDT 24 Jun 04 01:49:27 PM PDT 24 137152231944 ps
T353 /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1014771391 Jun 04 01:41:12 PM PDT 24 Jun 04 01:56:49 PM PDT 24 93856826616 ps
T354 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1786471123 Jun 04 01:41:19 PM PDT 24 Jun 04 01:41:51 PM PDT 24 3721670450 ps
T355 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1669220011 Jun 04 01:40:45 PM PDT 24 Jun 04 01:41:46 PM PDT 24 14061021275 ps
T356 /workspace/coverage/default/28.rom_ctrl_smoke.1420711471 Jun 04 01:40:35 PM PDT 24 Jun 04 01:41:38 PM PDT 24 76476140834 ps
T357 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3268051052 Jun 04 01:40:08 PM PDT 24 Jun 04 01:40:42 PM PDT 24 3854536891 ps
T358 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1439852186 Jun 04 01:41:11 PM PDT 24 Jun 04 01:41:43 PM PDT 24 3749346427 ps
T359 /workspace/coverage/default/19.rom_ctrl_smoke.3142462829 Jun 04 01:40:17 PM PDT 24 Jun 04 01:41:40 PM PDT 24 8046676208 ps
T360 /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3030778048 Jun 04 01:39:56 PM PDT 24 Jun 04 02:46:12 PM PDT 24 374887460277 ps
T361 /workspace/coverage/default/45.rom_ctrl_stress_all.2069303536 Jun 04 01:41:09 PM PDT 24 Jun 04 01:42:20 PM PDT 24 4222678071 ps
T362 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.792094834 Jun 04 01:40:08 PM PDT 24 Jun 04 01:40:20 PM PDT 24 734504697 ps
T363 /workspace/coverage/default/1.rom_ctrl_alert_test.1517137075 Jun 04 01:39:46 PM PDT 24 Jun 04 01:40:04 PM PDT 24 4591795926 ps
T364 /workspace/coverage/default/5.rom_ctrl_smoke.2457297528 Jun 04 01:39:56 PM PDT 24 Jun 04 01:40:59 PM PDT 24 40956268964 ps
T57 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2087021482 Jun 04 12:52:27 PM PDT 24 Jun 04 12:52:44 PM PDT 24 1124457796 ps
T58 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.474800619 Jun 04 12:52:31 PM PDT 24 Jun 04 12:54:19 PM PDT 24 47975916001 ps
T59 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2044902736 Jun 04 12:52:36 PM PDT 24 Jun 04 12:52:47 PM PDT 24 257130138 ps
T95 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1228636241 Jun 04 12:52:32 PM PDT 24 Jun 04 12:53:14 PM PDT 24 40821223207 ps
T365 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1256767120 Jun 04 12:52:42 PM PDT 24 Jun 04 12:52:52 PM PDT 24 413543491 ps
T96 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.644892415 Jun 04 12:52:43 PM PDT 24 Jun 04 12:53:05 PM PDT 24 8197217702 ps
T54 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2242090852 Jun 04 12:52:37 PM PDT 24 Jun 04 12:53:58 PM PDT 24 1053130800 ps
T366 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3345887672 Jun 04 12:52:40 PM PDT 24 Jun 04 12:52:53 PM PDT 24 612057321 ps
T63 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2386162872 Jun 04 12:52:31 PM PDT 24 Jun 04 12:53:02 PM PDT 24 2484887454 ps
T55 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3492294731 Jun 04 12:52:24 PM PDT 24 Jun 04 12:54:06 PM PDT 24 13727983450 ps
T97 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.919137792 Jun 04 12:52:25 PM PDT 24 Jun 04 12:54:33 PM PDT 24 24606473462 ps
T98 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.4222253035 Jun 04 12:52:29 PM PDT 24 Jun 04 12:54:33 PM PDT 24 15445325838 ps
T367 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.504325746 Jun 04 12:52:30 PM PDT 24 Jun 04 12:52:58 PM PDT 24 3293835105 ps
T368 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3103766959 Jun 04 12:52:31 PM PDT 24 Jun 04 12:53:11 PM PDT 24 4180405830 ps
T369 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.593807426 Jun 04 12:52:34 PM PDT 24 Jun 04 12:52:46 PM PDT 24 241481677 ps
T56 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2916933762 Jun 04 12:52:37 PM PDT 24 Jun 04 12:53:57 PM PDT 24 491873497 ps
T370 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2633828020 Jun 04 12:52:30 PM PDT 24 Jun 04 12:52:43 PM PDT 24 611884592 ps
T64 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2245292187 Jun 04 12:52:25 PM PDT 24 Jun 04 12:52:53 PM PDT 24 14045036338 ps
T89 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2622867608 Jun 04 12:52:25 PM PDT 24 Jun 04 12:52:35 PM PDT 24 174564833 ps
T371 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2619625957 Jun 04 12:52:24 PM PDT 24 Jun 04 12:52:41 PM PDT 24 5005649859 ps
T65 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.23770455 Jun 04 12:52:41 PM PDT 24 Jun 04 12:53:20 PM PDT 24 693798574 ps
T372 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.195609167 Jun 04 12:52:30 PM PDT 24 Jun 04 12:52:43 PM PDT 24 502051128 ps
T373 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.410841501 Jun 04 12:52:52 PM PDT 24 Jun 04 12:53:23 PM PDT 24 13380157936 ps
T107 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2054854040 Jun 04 12:52:28 PM PDT 24 Jun 04 12:55:16 PM PDT 24 24621823898 ps
T66 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.4199617160 Jun 04 12:52:24 PM PDT 24 Jun 04 12:52:53 PM PDT 24 6720437918 ps
T374 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2504760157 Jun 04 12:52:33 PM PDT 24 Jun 04 12:52:47 PM PDT 24 760665269 ps
T375 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1207051651 Jun 04 12:52:32 PM PDT 24 Jun 04 12:52:42 PM PDT 24 187571957 ps
T376 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2495231533 Jun 04 12:52:26 PM PDT 24 Jun 04 12:52:56 PM PDT 24 7372759871 ps
T377 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3208397706 Jun 04 12:52:37 PM PDT 24 Jun 04 12:52:46 PM PDT 24 787387302 ps
T378 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.463254608 Jun 04 12:52:27 PM PDT 24 Jun 04 12:52:59 PM PDT 24 16417322932 ps
T379 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3960801739 Jun 04 12:52:23 PM PDT 24 Jun 04 12:52:43 PM PDT 24 6883689533 ps
T67 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.463988080 Jun 04 12:52:32 PM PDT 24 Jun 04 12:53:05 PM PDT 24 73978967169 ps
T380 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1886808831 Jun 04 12:52:32 PM PDT 24 Jun 04 12:53:01 PM PDT 24 2832903776 ps
T111 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.320016919 Jun 04 12:52:27 PM PDT 24 Jun 04 12:55:20 PM PDT 24 3525549596 ps
T381 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3572870310 Jun 04 12:52:27 PM PDT 24 Jun 04 12:52:47 PM PDT 24 1577475117 ps
T382 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4126944116 Jun 04 12:52:28 PM PDT 24 Jun 04 12:52:48 PM PDT 24 2889509188 ps
T68 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.201654211 Jun 04 12:52:32 PM PDT 24 Jun 04 12:55:14 PM PDT 24 152199454892 ps
T69 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3300099983 Jun 04 12:52:33 PM PDT 24 Jun 04 12:53:04 PM PDT 24 2977216574 ps
T383 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1562708875 Jun 04 12:52:29 PM PDT 24 Jun 04 12:52:46 PM PDT 24 2219876509 ps
T70 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2315045154 Jun 04 12:52:35 PM PDT 24 Jun 04 12:53:14 PM PDT 24 733590347 ps
T71 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2103870102 Jun 04 12:52:32 PM PDT 24 Jun 04 12:55:10 PM PDT 24 69718567960 ps
T384 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1803812241 Jun 04 12:52:33 PM PDT 24 Jun 04 12:52:56 PM PDT 24 1956727253 ps
T112 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1554077068 Jun 04 12:52:38 PM PDT 24 Jun 04 12:54:12 PM PDT 24 8140821757 ps
T104 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3246426378 Jun 04 12:52:25 PM PDT 24 Jun 04 12:54:02 PM PDT 24 3366590660 ps
T385 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2361242934 Jun 04 12:52:30 PM PDT 24 Jun 04 12:52:51 PM PDT 24 5607142711 ps
T386 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4159118216 Jun 04 12:52:35 PM PDT 24 Jun 04 12:53:06 PM PDT 24 26352084467 ps
T108 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.588890477 Jun 04 12:52:31 PM PDT 24 Jun 04 12:53:55 PM PDT 24 495401660 ps
T78 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2037625819 Jun 04 12:52:32 PM PDT 24 Jun 04 12:54:10 PM PDT 24 21435150947 ps
T387 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1537305490 Jun 04 12:52:33 PM PDT 24 Jun 04 12:54:19 PM PDT 24 8528623600 ps
T388 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2995671938 Jun 04 12:52:29 PM PDT 24 Jun 04 12:53:56 PM PDT 24 7977550005 ps
T79 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1445828853 Jun 04 12:52:27 PM PDT 24 Jun 04 12:52:37 PM PDT 24 176261969 ps
T389 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1812397757 Jun 04 12:52:49 PM PDT 24 Jun 04 12:53:16 PM PDT 24 2996483627 ps
T390 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3511923420 Jun 04 12:52:26 PM PDT 24 Jun 04 12:53:03 PM PDT 24 19307775217 ps
T391 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4202106762 Jun 04 12:52:36 PM PDT 24 Jun 04 12:52:48 PM PDT 24 1100923854 ps
T392 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.772248772 Jun 04 12:52:30 PM PDT 24 Jun 04 12:53:04 PM PDT 24 14287189017 ps
T90 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4044978003 Jun 04 12:52:24 PM PDT 24 Jun 04 12:52:33 PM PDT 24 346335398 ps
T393 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1571151750 Jun 04 12:52:34 PM PDT 24 Jun 04 12:54:13 PM PDT 24 39504772406 ps
T394 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4186789974 Jun 04 12:52:36 PM PDT 24 Jun 04 12:53:07 PM PDT 24 11157608685 ps
T105 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1120090077 Jun 04 12:52:30 PM PDT 24 Jun 04 12:55:24 PM PDT 24 3733279181 ps
T106 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.282506272 Jun 04 12:52:24 PM PDT 24 Jun 04 12:53:54 PM PDT 24 1591637706 ps
T395 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.998182571 Jun 04 12:52:32 PM PDT 24 Jun 04 12:52:53 PM PDT 24 20039011026 ps
T396 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2783887329 Jun 04 12:52:24 PM PDT 24 Jun 04 12:52:56 PM PDT 24 3829963207 ps
T397 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.378412275 Jun 04 12:52:27 PM PDT 24 Jun 04 12:55:41 PM PDT 24 102950424810 ps
T398 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4285191293 Jun 04 12:52:27 PM PDT 24 Jun 04 12:52:37 PM PDT 24 353121738 ps
T399 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3553727717 Jun 04 12:52:31 PM PDT 24 Jun 04 12:52:48 PM PDT 24 257717016 ps
T80 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.617121335 Jun 04 12:52:35 PM PDT 24 Jun 04 12:53:06 PM PDT 24 3528961353 ps
T400 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1591565089 Jun 04 12:52:33 PM PDT 24 Jun 04 12:52:42 PM PDT 24 339202618 ps
T81 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2137420923 Jun 04 12:52:24 PM PDT 24 Jun 04 12:52:44 PM PDT 24 3484230974 ps
T91 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3952123133 Jun 04 12:52:26 PM PDT 24 Jun 04 12:52:40 PM PDT 24 730108406 ps
T92 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1454088788 Jun 04 12:52:40 PM PDT 24 Jun 04 12:53:04 PM PDT 24 5203761908 ps
T93 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.987523376 Jun 04 12:52:34 PM PDT 24 Jun 04 12:52:53 PM PDT 24 1640789936 ps
T401 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1482520116 Jun 04 12:52:36 PM PDT 24 Jun 04 12:52:53 PM PDT 24 2867321041 ps
T402 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1981492619 Jun 04 12:52:54 PM PDT 24 Jun 04 12:53:27 PM PDT 24 6954570248 ps
T94 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.884827521 Jun 04 12:52:31 PM PDT 24 Jun 04 12:52:58 PM PDT 24 6012421309 ps
T403 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3267060878 Jun 04 12:52:46 PM PDT 24 Jun 04 12:52:56 PM PDT 24 367090228 ps
T404 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.852397596 Jun 04 12:52:25 PM PDT 24 Jun 04 12:52:38 PM PDT 24 6862402759 ps
T87 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2830456752 Jun 04 12:52:27 PM PDT 24 Jun 04 12:53:06 PM PDT 24 2866304000 ps
T405 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.224037214 Jun 04 12:52:26 PM PDT 24 Jun 04 12:52:36 PM PDT 24 917662059 ps
T406 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3180312266 Jun 04 12:52:29 PM PDT 24 Jun 04 12:52:39 PM PDT 24 176400459 ps
T407 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1130291455 Jun 04 12:52:29 PM PDT 24 Jun 04 12:52:55 PM PDT 24 9963659909 ps
T408 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1831096196 Jun 04 12:52:31 PM PDT 24 Jun 04 12:54:33 PM PDT 24 65856418297 ps
T409 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1899890703 Jun 04 12:52:38 PM PDT 24 Jun 04 12:53:10 PM PDT 24 7846236431 ps
T410 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.777815137 Jun 04 12:52:26 PM PDT 24 Jun 04 12:53:01 PM PDT 24 4388543402 ps
T109 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3634570898 Jun 04 12:52:31 PM PDT 24 Jun 04 12:55:12 PM PDT 24 1195556384 ps
T86 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.460886941 Jun 04 12:52:27 PM PDT 24 Jun 04 12:53:07 PM PDT 24 1448330253 ps
T411 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4073140986 Jun 04 12:52:26 PM PDT 24 Jun 04 12:52:36 PM PDT 24 170710488 ps
T412 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2493216339 Jun 04 12:52:29 PM PDT 24 Jun 04 12:52:53 PM PDT 24 10653496646 ps
T113 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1442973789 Jun 04 12:52:27 PM PDT 24 Jun 04 12:55:13 PM PDT 24 12117098392 ps
T413 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3239861233 Jun 04 12:52:33 PM PDT 24 Jun 04 12:53:05 PM PDT 24 15714133730 ps
T414 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.91870199 Jun 04 12:52:29 PM PDT 24 Jun 04 12:52:52 PM PDT 24 6204762651 ps
T415 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4086925373 Jun 04 12:52:26 PM PDT 24 Jun 04 12:52:58 PM PDT 24 3702967142 ps
T416 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2835469044 Jun 04 12:52:25 PM PDT 24 Jun 04 12:52:55 PM PDT 24 3531584876 ps
T417 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3402518422 Jun 04 12:52:32 PM PDT 24 Jun 04 12:53:01 PM PDT 24 3200912221 ps
T418 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2140714490 Jun 04 12:52:30 PM PDT 24 Jun 04 12:52:44 PM PDT 24 3071235255 ps
T419 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.688080754 Jun 04 12:52:35 PM PDT 24 Jun 04 12:52:49 PM PDT 24 1719943059 ps
T420 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3188479873 Jun 04 12:52:30 PM PDT 24 Jun 04 12:52:53 PM PDT 24 2188205157 ps
T421 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3407164700 Jun 04 12:52:37 PM PDT 24 Jun 04 12:52:50 PM PDT 24 608241083 ps
T82 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1997706091 Jun 04 12:52:29 PM PDT 24 Jun 04 12:52:46 PM PDT 24 1166157279 ps
T422 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2309343633 Jun 04 12:52:28 PM PDT 24 Jun 04 12:52:51 PM PDT 24 1481374722 ps
T423 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.134713708 Jun 04 12:52:31 PM PDT 24 Jun 04 12:52:41 PM PDT 24 591123671 ps
T424 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.15847689 Jun 04 12:52:34 PM PDT 24 Jun 04 12:52:43 PM PDT 24 613340203 ps
T425 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2300506657 Jun 04 12:52:31 PM PDT 24 Jun 04 12:53:06 PM PDT 24 57109856522 ps
T426 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2061966625 Jun 04 12:52:39 PM PDT 24 Jun 04 12:54:02 PM PDT 24 548524593 ps
T427 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1167150776 Jun 04 12:52:25 PM PDT 24 Jun 04 12:53:03 PM PDT 24 16695347233 ps
T428 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2470253243 Jun 04 12:52:25 PM PDT 24 Jun 04 12:52:41 PM PDT 24 1717299148 ps
T429 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1702942235 Jun 04 12:52:22 PM PDT 24 Jun 04 12:52:51 PM PDT 24 3433247301 ps
T430 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.268636144 Jun 04 12:52:36 PM PDT 24 Jun 04 12:53:01 PM PDT 24 4994667513 ps
T110 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1560141255 Jun 04 12:52:48 PM PDT 24 Jun 04 12:54:21 PM PDT 24 2349272962 ps
T431 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1966234725 Jun 04 12:52:34 PM PDT 24 Jun 04 12:53:03 PM PDT 24 5678658198 ps
T432 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3390276811 Jun 04 12:52:34 PM PDT 24 Jun 04 12:53:35 PM PDT 24 14512106959 ps
T433 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1435722291 Jun 04 12:52:26 PM PDT 24 Jun 04 12:54:39 PM PDT 24 51489912724 ps
T434 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.813293164 Jun 04 12:52:32 PM PDT 24 Jun 04 12:53:00 PM PDT 24 3430836541 ps
T435 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.782868157 Jun 04 12:52:26 PM PDT 24 Jun 04 12:54:05 PM PDT 24 4316514508 ps
T88 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2203496031 Jun 04 12:52:32 PM PDT 24 Jun 04 12:52:41 PM PDT 24 167603537 ps
T436 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1485647002 Jun 04 12:52:36 PM PDT 24 Jun 04 12:53:00 PM PDT 24 3773409577 ps
T437 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1388505886 Jun 04 12:52:30 PM PDT 24 Jun 04 12:52:41 PM PDT 24 190690132 ps
T114 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2878459738 Jun 04 12:52:23 PM PDT 24 Jun 04 12:55:10 PM PDT 24 16633568124 ps
T438 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2977542278 Jun 04 12:52:33 PM PDT 24 Jun 04 12:52:50 PM PDT 24 1816284217 ps
T439 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.471276242 Jun 04 12:52:35 PM PDT 24 Jun 04 12:55:20 PM PDT 24 5407543567 ps
T440 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.659852247 Jun 04 12:52:26 PM PDT 24 Jun 04 12:52:54 PM PDT 24 12219945330 ps
T441 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4036648168 Jun 04 12:52:25 PM PDT 24 Jun 04 12:52:38 PM PDT 24 1103297956 ps
T442 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.529649912 Jun 04 12:52:36 PM PDT 24 Jun 04 12:55:23 PM PDT 24 18477030962 ps
T443 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2041678228 Jun 04 12:52:41 PM PDT 24 Jun 04 12:53:09 PM PDT 24 19836837654 ps
T444 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.911133255 Jun 04 12:52:35 PM PDT 24 Jun 04 12:54:12 PM PDT 24 11466932410 ps
T445 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1442900298 Jun 04 12:52:27 PM PDT 24 Jun 04 12:53:00 PM PDT 24 3498217477 ps
T446 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1677375003 Jun 04 12:52:36 PM PDT 24 Jun 04 12:53:34 PM PDT 24 2110210010 ps
T83 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2491858288 Jun 04 12:52:29 PM PDT 24 Jun 04 12:54:10 PM PDT 24 7755236218 ps
T447 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2731844496 Jun 04 12:52:29 PM PDT 24 Jun 04 12:52:54 PM PDT 24 11097468953 ps
T448 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3544505692 Jun 04 12:52:26 PM PDT 24 Jun 04 12:53:00 PM PDT 24 4340192612 ps
T84 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1102059393 Jun 04 12:52:26 PM PDT 24 Jun 04 12:52:55 PM PDT 24 10268445728 ps
T449 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3415898100 Jun 04 12:52:24 PM PDT 24 Jun 04 12:52:53 PM PDT 24 3204687404 ps
T450 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3802791775 Jun 04 12:52:35 PM PDT 24 Jun 04 12:53:05 PM PDT 24 3663572788 ps
T451 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4081638859 Jun 04 12:52:31 PM PDT 24 Jun 04 12:52:48 PM PDT 24 6725564848 ps
T452 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1644402095 Jun 04 12:52:35 PM PDT 24 Jun 04 12:53:07 PM PDT 24 17419549162 ps
T85 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1885230480 Jun 04 12:52:31 PM PDT 24 Jun 04 12:54:34 PM PDT 24 131734382454 ps
T453 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.916153675 Jun 04 12:52:31 PM PDT 24 Jun 04 12:53:05 PM PDT 24 4158365070 ps
T454 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2542945064 Jun 04 12:52:37 PM PDT 24 Jun 04 12:52:54 PM PDT 24 2064670459 ps
T455 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4126115505 Jun 04 12:52:23 PM PDT 24 Jun 04 12:52:32 PM PDT 24 752492100 ps
T456 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4268170470 Jun 04 12:52:30 PM PDT 24 Jun 04 12:52:39 PM PDT 24 296626287 ps
T457 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4270691347 Jun 04 12:52:23 PM PDT 24 Jun 04 12:52:36 PM PDT 24 178215716 ps
T458 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.295448037 Jun 04 12:52:37 PM PDT 24 Jun 04 12:53:00 PM PDT 24 41285530604 ps
T459 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.590378879 Jun 04 12:52:35 PM PDT 24 Jun 04 12:52:45 PM PDT 24 332039950 ps
T460 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3605356472 Jun 04 12:52:35 PM PDT 24 Jun 04 12:54:11 PM PDT 24 11717556544 ps
T461 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2889612301 Jun 04 12:52:31 PM PDT 24 Jun 04 12:52:44 PM PDT 24 183779210 ps
T462 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2479233106 Jun 04 12:52:33 PM PDT 24 Jun 04 12:52:42 PM PDT 24 551093217 ps

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3472138910
Short name T6
Test name
Test status
Simulation time 84386152430 ps
CPU time 359.97 seconds
Started Jun 04 01:40:34 PM PDT 24
Finished Jun 04 01:46:36 PM PDT 24
Peak memory 240964 kb
Host smart-21882c28-51c7-48b1-ad45-c088bb1c4e30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472138910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3472138910
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1720914193
Short name T13
Test name
Test status
Simulation time 140203615631 ps
CPU time 1293.58 seconds
Started Jun 04 01:39:56 PM PDT 24
Finished Jun 04 02:01:32 PM PDT 24
Peak memory 237496 kb
Host smart-04db72a4-37dc-4b59-8747-74ce12610519
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720914193 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1720914193
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3874005897
Short name T3
Test name
Test status
Simulation time 19858055068 ps
CPU time 185.9 seconds
Started Jun 04 01:40:44 PM PDT 24
Finished Jun 04 01:43:51 PM PDT 24
Peak memory 230036 kb
Host smart-1646b8bb-8250-4830-9c6d-12065d63d528
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874005897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3874005897
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2054854040
Short name T107
Test name
Test status
Simulation time 24621823898 ps
CPU time 166.56 seconds
Started Jun 04 12:52:28 PM PDT 24
Finished Jun 04 12:55:16 PM PDT 24
Peak memory 219524 kb
Host smart-54d4f778-d743-49f1-8e25-21e0878344de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054854040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2054854040
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2574108103
Short name T22
Test name
Test status
Simulation time 51422015270 ps
CPU time 483.56 seconds
Started Jun 04 01:39:59 PM PDT 24
Finished Jun 04 01:48:04 PM PDT 24
Peak memory 228184 kb
Host smart-a9dd0cfa-9b57-43c8-8366-15014b39bc1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574108103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2574108103
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3004968134
Short name T27
Test name
Test status
Simulation time 47642559373 ps
CPU time 138.34 seconds
Started Jun 04 01:39:45 PM PDT 24
Finished Jun 04 01:42:05 PM PDT 24
Peak memory 236864 kb
Host smart-dfa02b1a-96b8-4c5e-a691-04325c764d2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004968134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3004968134
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.23770455
Short name T65
Test name
Test status
Simulation time 693798574 ps
CPU time 37.63 seconds
Started Jun 04 12:52:41 PM PDT 24
Finished Jun 04 12:53:20 PM PDT 24
Peak memory 213248 kb
Host smart-9a0ee236-d4c9-40db-981b-fdb57ba67815
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23770455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pas
sthru_mem_tl_intg_err.23770455
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3634570898
Short name T109
Test name
Test status
Simulation time 1195556384 ps
CPU time 159.35 seconds
Started Jun 04 12:52:31 PM PDT 24
Finished Jun 04 12:55:12 PM PDT 24
Peak memory 213760 kb
Host smart-23ed6a7a-a169-494b-ab26-1cf4fcccd687
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634570898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3634570898
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2157843948
Short name T14
Test name
Test status
Simulation time 66246825208 ps
CPU time 1249.92 seconds
Started Jun 04 01:40:29 PM PDT 24
Finished Jun 04 02:01:21 PM PDT 24
Peak memory 235960 kb
Host smart-6d159403-ef54-4b1d-9157-a5759abdf0e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157843948 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.2157843948
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.682464751
Short name T32
Test name
Test status
Simulation time 7549654845 ps
CPU time 21.4 seconds
Started Jun 04 01:40:05 PM PDT 24
Finished Jun 04 01:40:27 PM PDT 24
Peak memory 211428 kb
Host smart-ce3d46b7-e0e0-47c4-bc8f-e2fc1ef6783b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682464751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.682464751
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1159404364
Short name T19
Test name
Test status
Simulation time 1374546282 ps
CPU time 19.43 seconds
Started Jun 04 01:40:05 PM PDT 24
Finished Jun 04 01:40:25 PM PDT 24
Peak memory 214808 kb
Host smart-0d54eab6-6b43-4bc9-a74a-68517e577c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159404364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1159404364
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3590865254
Short name T133
Test name
Test status
Simulation time 3438859026 ps
CPU time 41.07 seconds
Started Jun 04 01:40:16 PM PDT 24
Finished Jun 04 01:40:58 PM PDT 24
Peak memory 214716 kb
Host smart-59575fd4-23c3-4cda-a9d5-8181ee704e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590865254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3590865254
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2103870102
Short name T71
Test name
Test status
Simulation time 69718567960 ps
CPU time 156.28 seconds
Started Jun 04 12:52:32 PM PDT 24
Finished Jun 04 12:55:10 PM PDT 24
Peak memory 215356 kb
Host smart-4464f2ac-2ab7-4970-9aec-beb869af646b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103870102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2103870102
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1120090077
Short name T105
Test name
Test status
Simulation time 3733279181 ps
CPU time 172.79 seconds
Started Jun 04 12:52:30 PM PDT 24
Finished Jun 04 12:55:24 PM PDT 24
Peak memory 215052 kb
Host smart-d796902c-a5ce-4b71-8303-19a67984722a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120090077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1120090077
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.166513254
Short name T26
Test name
Test status
Simulation time 4979737490 ps
CPU time 318.33 seconds
Started Jun 04 01:41:11 PM PDT 24
Finished Jun 04 01:46:31 PM PDT 24
Peak memory 217588 kb
Host smart-595383bb-7c97-45d2-8fe9-e79b47ce00f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166513254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.166513254
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.474800619
Short name T58
Test name
Test status
Simulation time 47975916001 ps
CPU time 106.47 seconds
Started Jun 04 12:52:31 PM PDT 24
Finished Jun 04 12:54:19 PM PDT 24
Peak memory 214280 kb
Host smart-51f436bc-a61c-4511-ab64-c2efe87d90fb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474800619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.474800619
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.320016919
Short name T111
Test name
Test status
Simulation time 3525549596 ps
CPU time 171.57 seconds
Started Jun 04 12:52:27 PM PDT 24
Finished Jun 04 12:55:20 PM PDT 24
Peak memory 214044 kb
Host smart-098408d2-96ca-4f14-b9af-9dcb0f1f3781
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320016919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.320016919
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1128620361
Short name T76
Test name
Test status
Simulation time 11584783605 ps
CPU time 114.59 seconds
Started Jun 04 01:39:47 PM PDT 24
Finished Jun 04 01:41:44 PM PDT 24
Peak memory 219492 kb
Host smart-97ea6421-fd3a-49f6-95ff-e9c76de92698
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128620361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1128620361
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1997706091
Short name T82
Test name
Test status
Simulation time 1166157279 ps
CPU time 15.26 seconds
Started Jun 04 12:52:29 PM PDT 24
Finished Jun 04 12:52:46 PM PDT 24
Peak memory 211084 kb
Host smart-87fa7409-5391-451d-af47-6d11915d3929
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997706091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1997706091
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2731844496
Short name T447
Test name
Test status
Simulation time 11097468953 ps
CPU time 24.39 seconds
Started Jun 04 12:52:29 PM PDT 24
Finished Jun 04 12:52:54 PM PDT 24
Peak memory 212412 kb
Host smart-199dd481-8312-4b1a-ae54-fac01eeec475
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731844496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2731844496
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1228636241
Short name T95
Test name
Test status
Simulation time 40821223207 ps
CPU time 40.7 seconds
Started Jun 04 12:52:32 PM PDT 24
Finished Jun 04 12:53:14 PM PDT 24
Peak memory 212304 kb
Host smart-608c7295-e443-44d5-ab7e-f35f23c776b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228636241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1228636241
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4126115505
Short name T455
Test name
Test status
Simulation time 752492100 ps
CPU time 8.93 seconds
Started Jun 04 12:52:23 PM PDT 24
Finished Jun 04 12:52:32 PM PDT 24
Peak memory 216700 kb
Host smart-194f2efc-a385-4fa7-8670-e8adb752fa3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126115505 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.4126115505
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.4199617160
Short name T66
Test name
Test status
Simulation time 6720437918 ps
CPU time 28.28 seconds
Started Jun 04 12:52:24 PM PDT 24
Finished Jun 04 12:52:53 PM PDT 24
Peak memory 211600 kb
Host smart-de5b4ae2-f22a-4640-a19b-b0f00a8eca8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199617160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.4199617160
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.813293164
Short name T434
Test name
Test status
Simulation time 3430836541 ps
CPU time 26.4 seconds
Started Jun 04 12:52:32 PM PDT 24
Finished Jun 04 12:53:00 PM PDT 24
Peak memory 211048 kb
Host smart-f46bd88c-aa7d-4c7f-af2f-8bbb718fada0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813293164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.813293164
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2619625957
Short name T371
Test name
Test status
Simulation time 5005649859 ps
CPU time 15.66 seconds
Started Jun 04 12:52:24 PM PDT 24
Finished Jun 04 12:52:41 PM PDT 24
Peak memory 211156 kb
Host smart-3acdd994-c88e-4078-9032-702cf8abf9fa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619625957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2619625957
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2491858288
Short name T83
Test name
Test status
Simulation time 7755236218 ps
CPU time 100.3 seconds
Started Jun 04 12:52:29 PM PDT 24
Finished Jun 04 12:54:10 PM PDT 24
Peak memory 215424 kb
Host smart-650727b4-97c9-451d-9594-75018d289b94
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491858288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2491858288
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.224037214
Short name T405
Test name
Test status
Simulation time 917662059 ps
CPU time 8.16 seconds
Started Jun 04 12:52:26 PM PDT 24
Finished Jun 04 12:52:36 PM PDT 24
Peak memory 211284 kb
Host smart-872cd433-fb7c-41e1-a703-1461f78c772e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224037214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.224037214
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1981492619
Short name T402
Test name
Test status
Simulation time 6954570248 ps
CPU time 32.24 seconds
Started Jun 04 12:52:54 PM PDT 24
Finished Jun 04 12:53:27 PM PDT 24
Peak memory 219052 kb
Host smart-6418af69-240c-4f26-b53d-78bbab63d28f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981492619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1981492619
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.282506272
Short name T106
Test name
Test status
Simulation time 1591637706 ps
CPU time 89 seconds
Started Jun 04 12:52:24 PM PDT 24
Finished Jun 04 12:53:54 PM PDT 24
Peak memory 212580 kb
Host smart-ba89f388-c359-44ad-9bcc-2e5ca59bbd90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282506272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.282506272
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1445828853
Short name T79
Test name
Test status
Simulation time 176261969 ps
CPU time 8.27 seconds
Started Jun 04 12:52:27 PM PDT 24
Finished Jun 04 12:52:37 PM PDT 24
Peak memory 211180 kb
Host smart-48fdc7a2-0e83-48f6-8eb8-be7038194816
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445828853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1445828853
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1702942235
Short name T429
Test name
Test status
Simulation time 3433247301 ps
CPU time 28.48 seconds
Started Jun 04 12:52:22 PM PDT 24
Finished Jun 04 12:52:51 PM PDT 24
Peak memory 211316 kb
Host smart-9bbff760-96d6-40d8-a0bb-1cceb13d8ce6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702942235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1702942235
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4086925373
Short name T415
Test name
Test status
Simulation time 3702967142 ps
CPU time 31.59 seconds
Started Jun 04 12:52:26 PM PDT 24
Finished Jun 04 12:52:58 PM PDT 24
Peak memory 211960 kb
Host smart-a4c5df7b-fcaf-4192-96ce-1f93f5f3b2b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086925373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.4086925373
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2087021482
Short name T57
Test name
Test status
Simulation time 1124457796 ps
CPU time 15.34 seconds
Started Jun 04 12:52:27 PM PDT 24
Finished Jun 04 12:52:44 PM PDT 24
Peak memory 215852 kb
Host smart-9a60c0a2-8356-4810-b420-307964deb20e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087021482 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2087021482
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4081638859
Short name T451
Test name
Test status
Simulation time 6725564848 ps
CPU time 15.07 seconds
Started Jun 04 12:52:31 PM PDT 24
Finished Jun 04 12:52:48 PM PDT 24
Peak memory 211304 kb
Host smart-8d1036a5-26b3-4a01-aae5-765dcbb9ce1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081638859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4081638859
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2495231533
Short name T376
Test name
Test status
Simulation time 7372759871 ps
CPU time 28.64 seconds
Started Jun 04 12:52:26 PM PDT 24
Finished Jun 04 12:52:56 PM PDT 24
Peak memory 211176 kb
Host smart-a607fb4e-d050-4a66-bd06-05775445b36a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495231533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2495231533
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3208397706
Short name T377
Test name
Test status
Simulation time 787387302 ps
CPU time 7.86 seconds
Started Jun 04 12:52:37 PM PDT 24
Finished Jun 04 12:52:46 PM PDT 24
Peak memory 211188 kb
Host smart-12e4c370-6c29-4f72-8443-3c4f266bf132
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208397706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3208397706
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4044978003
Short name T90
Test name
Test status
Simulation time 346335398 ps
CPU time 8.19 seconds
Started Jun 04 12:52:24 PM PDT 24
Finished Jun 04 12:52:33 PM PDT 24
Peak memory 211328 kb
Host smart-7dcff879-7194-43f2-a70a-cee6f5724fda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044978003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.4044978003
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2889612301
Short name T461
Test name
Test status
Simulation time 183779210 ps
CPU time 11.28 seconds
Started Jun 04 12:52:31 PM PDT 24
Finished Jun 04 12:52:44 PM PDT 24
Peak memory 216104 kb
Host smart-846c9f6d-c103-4896-af16-850743c00ae0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889612301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2889612301
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1482520116
Short name T401
Test name
Test status
Simulation time 2867321041 ps
CPU time 16.63 seconds
Started Jun 04 12:52:36 PM PDT 24
Finished Jun 04 12:52:53 PM PDT 24
Peak memory 215016 kb
Host smart-b0f269ef-caf9-4ef9-881a-77f7e7b00850
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482520116 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1482520116
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3407164700
Short name T421
Test name
Test status
Simulation time 608241083 ps
CPU time 12.09 seconds
Started Jun 04 12:52:37 PM PDT 24
Finished Jun 04 12:52:50 PM PDT 24
Peak memory 211132 kb
Host smart-dd45a7c9-1fa1-4c6c-af13-482416f99beb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407164700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3407164700
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.201654211
Short name T68
Test name
Test status
Simulation time 152199454892 ps
CPU time 160.3 seconds
Started Jun 04 12:52:32 PM PDT 24
Finished Jun 04 12:55:14 PM PDT 24
Peak memory 215436 kb
Host smart-b6c129c0-c300-4b4b-8060-8bc4aaf1baed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201654211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.201654211
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3402518422
Short name T417
Test name
Test status
Simulation time 3200912221 ps
CPU time 27.49 seconds
Started Jun 04 12:52:32 PM PDT 24
Finished Jun 04 12:53:01 PM PDT 24
Peak memory 212568 kb
Host smart-96245771-6705-4b04-ad11-75bbb5a52c2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402518422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3402518422
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2361242934
Short name T385
Test name
Test status
Simulation time 5607142711 ps
CPU time 19.59 seconds
Started Jun 04 12:52:30 PM PDT 24
Finished Jun 04 12:52:51 PM PDT 24
Peak memory 218640 kb
Host smart-777bf7f0-1e39-429e-b473-1b17bd06d7bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361242934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2361242934
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.588890477
Short name T108
Test name
Test status
Simulation time 495401660 ps
CPU time 82.64 seconds
Started Jun 04 12:52:31 PM PDT 24
Finished Jun 04 12:53:55 PM PDT 24
Peak memory 213696 kb
Host smart-c53fa1d7-a010-4a51-8d66-74c3319abcb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588890477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.588890477
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.91870199
Short name T414
Test name
Test status
Simulation time 6204762651 ps
CPU time 21.25 seconds
Started Jun 04 12:52:29 PM PDT 24
Finished Jun 04 12:52:52 PM PDT 24
Peak memory 219036 kb
Host smart-840309c3-fc8d-46eb-945a-99f2fb287ed1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91870199 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.91870199
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1644402095
Short name T452
Test name
Test status
Simulation time 17419549162 ps
CPU time 31.47 seconds
Started Jun 04 12:52:35 PM PDT 24
Finished Jun 04 12:53:07 PM PDT 24
Peak memory 212192 kb
Host smart-9eb91df8-2a87-4ef7-bcf7-cba96f2f1b36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644402095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1644402095
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1571151750
Short name T393
Test name
Test status
Simulation time 39504772406 ps
CPU time 98.12 seconds
Started Jun 04 12:52:34 PM PDT 24
Finished Jun 04 12:54:13 PM PDT 24
Peak memory 214364 kb
Host smart-18a2ecd0-3643-4fe4-9e4b-d443a7932f7e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571151750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1571151750
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2479233106
Short name T462
Test name
Test status
Simulation time 551093217 ps
CPU time 7.92 seconds
Started Jun 04 12:52:33 PM PDT 24
Finished Jun 04 12:52:42 PM PDT 24
Peak memory 211164 kb
Host smart-464627dd-8bdd-412c-8315-95d60e2695f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479233106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2479233106
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.195609167
Short name T372
Test name
Test status
Simulation time 502051128 ps
CPU time 11.77 seconds
Started Jun 04 12:52:30 PM PDT 24
Finished Jun 04 12:52:43 PM PDT 24
Peak memory 217236 kb
Host smart-5373160e-8a7b-45c5-8c80-f2b4c2d26b87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195609167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.195609167
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2242090852
Short name T54
Test name
Test status
Simulation time 1053130800 ps
CPU time 79.07 seconds
Started Jun 04 12:52:37 PM PDT 24
Finished Jun 04 12:53:58 PM PDT 24
Peak memory 219452 kb
Host smart-9ca05922-e265-48e5-86f4-73bd91c44a42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242090852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2242090852
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1207051651
Short name T375
Test name
Test status
Simulation time 187571957 ps
CPU time 8.71 seconds
Started Jun 04 12:52:32 PM PDT 24
Finished Jun 04 12:52:42 PM PDT 24
Peak memory 216388 kb
Host smart-7123f96d-2565-4120-ac58-529b35985982
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207051651 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1207051651
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.644892415
Short name T96
Test name
Test status
Simulation time 8197217702 ps
CPU time 20.89 seconds
Started Jun 04 12:52:43 PM PDT 24
Finished Jun 04 12:53:05 PM PDT 24
Peak memory 212436 kb
Host smart-516a30b0-5e5b-4c21-8161-9680c0958c92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644892415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.644892415
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2037625819
Short name T78
Test name
Test status
Simulation time 21435150947 ps
CPU time 96.55 seconds
Started Jun 04 12:52:32 PM PDT 24
Finished Jun 04 12:54:10 PM PDT 24
Peak memory 213800 kb
Host smart-6a502c00-f103-42dd-b1a8-74e59de36533
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037625819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2037625819
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.884827521
Short name T94
Test name
Test status
Simulation time 6012421309 ps
CPU time 25.21 seconds
Started Jun 04 12:52:31 PM PDT 24
Finished Jun 04 12:52:58 PM PDT 24
Peak memory 212948 kb
Host smart-15b3b5aa-d248-42e7-9cb5-c07493bcb97a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884827521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.884827521
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1803812241
Short name T384
Test name
Test status
Simulation time 1956727253 ps
CPU time 21.76 seconds
Started Jun 04 12:52:33 PM PDT 24
Finished Jun 04 12:52:56 PM PDT 24
Peak memory 218180 kb
Host smart-756ef673-acdd-441e-8620-27036f19c4c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803812241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1803812241
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1560141255
Short name T110
Test name
Test status
Simulation time 2349272962 ps
CPU time 90.99 seconds
Started Jun 04 12:52:48 PM PDT 24
Finished Jun 04 12:54:21 PM PDT 24
Peak memory 219520 kb
Host smart-0b34cb5b-60b9-4918-b8c7-f93b62200046
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560141255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1560141255
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.916153675
Short name T453
Test name
Test status
Simulation time 4158365070 ps
CPU time 32.16 seconds
Started Jun 04 12:52:31 PM PDT 24
Finished Jun 04 12:53:05 PM PDT 24
Peak memory 217756 kb
Host smart-33b5c0d0-f77f-44d8-b5f8-119b8b3fc67f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916153675 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.916153675
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2504760157
Short name T374
Test name
Test status
Simulation time 760665269 ps
CPU time 13.62 seconds
Started Jun 04 12:52:33 PM PDT 24
Finished Jun 04 12:52:47 PM PDT 24
Peak memory 211132 kb
Host smart-6d4ba4aa-e3ab-4b7c-be61-6b4e20343f8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504760157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2504760157
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3300099983
Short name T69
Test name
Test status
Simulation time 2977216574 ps
CPU time 29.5 seconds
Started Jun 04 12:52:33 PM PDT 24
Finished Jun 04 12:53:04 PM PDT 24
Peak memory 212508 kb
Host smart-eab21758-0afd-47a2-a533-15721742b1ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300099983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3300099983
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2041678228
Short name T443
Test name
Test status
Simulation time 19836837654 ps
CPU time 26.7 seconds
Started Jun 04 12:52:41 PM PDT 24
Finished Jun 04 12:53:09 PM PDT 24
Peak memory 219148 kb
Host smart-6de30131-57e0-47c2-a8d5-973b83ad18ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041678228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2041678228
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2916933762
Short name T56
Test name
Test status
Simulation time 491873497 ps
CPU time 79.32 seconds
Started Jun 04 12:52:37 PM PDT 24
Finished Jun 04 12:53:57 PM PDT 24
Peak memory 213344 kb
Host smart-d9846038-3ce3-4099-b528-1e700b10c4fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916933762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2916933762
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.295448037
Short name T458
Test name
Test status
Simulation time 41285530604 ps
CPU time 21.4 seconds
Started Jun 04 12:52:37 PM PDT 24
Finished Jun 04 12:53:00 PM PDT 24
Peak memory 217336 kb
Host smart-813c2f26-8efd-4f4f-89b4-50f03b5c7c1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295448037 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.295448037
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2203496031
Short name T88
Test name
Test status
Simulation time 167603537 ps
CPU time 8.01 seconds
Started Jun 04 12:52:32 PM PDT 24
Finished Jun 04 12:52:41 PM PDT 24
Peak memory 211152 kb
Host smart-8f40206a-5a24-4db5-8aaf-3756d04c75a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203496031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2203496031
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3390276811
Short name T432
Test name
Test status
Simulation time 14512106959 ps
CPU time 60.31 seconds
Started Jun 04 12:52:34 PM PDT 24
Finished Jun 04 12:53:35 PM PDT 24
Peak memory 214620 kb
Host smart-4c7186dd-ceb8-4026-9e78-aa43b5d004de
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390276811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3390276811
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.268636144
Short name T430
Test name
Test status
Simulation time 4994667513 ps
CPU time 23.31 seconds
Started Jun 04 12:52:36 PM PDT 24
Finished Jun 04 12:53:01 PM PDT 24
Peak memory 212520 kb
Host smart-c26f640b-c245-4d52-8ae8-5d303e81a6e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268636144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.268636144
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1886808831
Short name T380
Test name
Test status
Simulation time 2832903776 ps
CPU time 27.34 seconds
Started Jun 04 12:52:32 PM PDT 24
Finished Jun 04 12:53:01 PM PDT 24
Peak memory 217496 kb
Host smart-e024ceb0-45d8-40dd-a94b-325e096f767a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886808831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1886808831
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1554077068
Short name T112
Test name
Test status
Simulation time 8140821757 ps
CPU time 92.3 seconds
Started Jun 04 12:52:38 PM PDT 24
Finished Jun 04 12:54:12 PM PDT 24
Peak memory 213720 kb
Host smart-e0ab544f-7313-49bd-bea5-b0410995429e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554077068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1554077068
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.4159118216
Short name T386
Test name
Test status
Simulation time 26352084467 ps
CPU time 30.53 seconds
Started Jun 04 12:52:35 PM PDT 24
Finished Jun 04 12:53:06 PM PDT 24
Peak memory 214760 kb
Host smart-a8ec6694-24d7-4625-bf18-d6950f153e8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159118216 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.4159118216
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2300506657
Short name T425
Test name
Test status
Simulation time 57109856522 ps
CPU time 32.89 seconds
Started Jun 04 12:52:31 PM PDT 24
Finished Jun 04 12:53:06 PM PDT 24
Peak memory 212204 kb
Host smart-4924ee3d-0972-47ee-80bc-8b19f5d09a3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300506657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2300506657
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.529649912
Short name T442
Test name
Test status
Simulation time 18477030962 ps
CPU time 165.95 seconds
Started Jun 04 12:52:36 PM PDT 24
Finished Jun 04 12:55:23 PM PDT 24
Peak memory 216628 kb
Host smart-6b4df606-c56c-407c-8837-2657b0f7bd2e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529649912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.529649912
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.688080754
Short name T419
Test name
Test status
Simulation time 1719943059 ps
CPU time 13.39 seconds
Started Jun 04 12:52:35 PM PDT 24
Finished Jun 04 12:52:49 PM PDT 24
Peak memory 211292 kb
Host smart-480e1dd6-8ee5-41b1-b0c5-1e787e4250bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688080754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.688080754
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1966234725
Short name T431
Test name
Test status
Simulation time 5678658198 ps
CPU time 28.49 seconds
Started Jun 04 12:52:34 PM PDT 24
Finished Jun 04 12:53:03 PM PDT 24
Peak memory 218864 kb
Host smart-9eac7a4a-d395-475a-8771-7f73e876f670
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966234725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1966234725
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4186789974
Short name T394
Test name
Test status
Simulation time 11157608685 ps
CPU time 24.89 seconds
Started Jun 04 12:52:36 PM PDT 24
Finished Jun 04 12:53:07 PM PDT 24
Peak memory 218080 kb
Host smart-096579da-4cbf-418e-a898-a7012a64af2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186789974 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.4186789974
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4268170470
Short name T456
Test name
Test status
Simulation time 296626287 ps
CPU time 7.98 seconds
Started Jun 04 12:52:30 PM PDT 24
Finished Jun 04 12:52:39 PM PDT 24
Peak memory 211256 kb
Host smart-92127a94-91f6-47e8-bc49-64500326f431
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268170470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.4268170470
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2995671938
Short name T388
Test name
Test status
Simulation time 7977550005 ps
CPU time 85.04 seconds
Started Jun 04 12:52:29 PM PDT 24
Finished Jun 04 12:53:56 PM PDT 24
Peak memory 214424 kb
Host smart-4dba2338-b158-4d54-8126-56e71e4bac9d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995671938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2995671938
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1899890703
Short name T409
Test name
Test status
Simulation time 7846236431 ps
CPU time 31.61 seconds
Started Jun 04 12:52:38 PM PDT 24
Finished Jun 04 12:53:10 PM PDT 24
Peak memory 212660 kb
Host smart-564663aa-16fd-4091-9722-77502d3c9cee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899890703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1899890703
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.410841501
Short name T373
Test name
Test status
Simulation time 13380157936 ps
CPU time 29.54 seconds
Started Jun 04 12:52:52 PM PDT 24
Finished Jun 04 12:53:23 PM PDT 24
Peak memory 219596 kb
Host smart-950c880b-b810-49d8-8d77-212971a16f82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410841501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.410841501
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2061966625
Short name T426
Test name
Test status
Simulation time 548524593 ps
CPU time 82.15 seconds
Started Jun 04 12:52:39 PM PDT 24
Finished Jun 04 12:54:02 PM PDT 24
Peak memory 213256 kb
Host smart-aeb7881d-3522-4e6f-b70c-6c432b500a91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061966625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2061966625
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3267060878
Short name T403
Test name
Test status
Simulation time 367090228 ps
CPU time 8.9 seconds
Started Jun 04 12:52:46 PM PDT 24
Finished Jun 04 12:52:56 PM PDT 24
Peak memory 216416 kb
Host smart-72c3df3f-9029-4167-9920-9144da8ef8c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267060878 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3267060878
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.617121335
Short name T80
Test name
Test status
Simulation time 3528961353 ps
CPU time 29.17 seconds
Started Jun 04 12:52:35 PM PDT 24
Finished Jun 04 12:53:06 PM PDT 24
Peak memory 211688 kb
Host smart-9047902d-507b-46c1-9064-3c7a9dac3abf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617121335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.617121335
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1831096196
Short name T408
Test name
Test status
Simulation time 65856418297 ps
CPU time 120.45 seconds
Started Jun 04 12:52:31 PM PDT 24
Finished Jun 04 12:54:33 PM PDT 24
Peak memory 214516 kb
Host smart-ff94319b-8baa-4156-bb83-1fda681c8b38
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831096196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1831096196
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3188479873
Short name T420
Test name
Test status
Simulation time 2188205157 ps
CPU time 21.54 seconds
Started Jun 04 12:52:30 PM PDT 24
Finished Jun 04 12:52:53 PM PDT 24
Peak memory 212168 kb
Host smart-af931751-ac81-4f56-9e3d-a55ebcc2ef3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188479873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3188479873
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2542945064
Short name T454
Test name
Test status
Simulation time 2064670459 ps
CPU time 15.27 seconds
Started Jun 04 12:52:37 PM PDT 24
Finished Jun 04 12:52:54 PM PDT 24
Peak memory 217268 kb
Host smart-583c155f-d08b-486c-9bf0-cc613a6df707
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542945064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2542945064
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3605356472
Short name T460
Test name
Test status
Simulation time 11717556544 ps
CPU time 95.15 seconds
Started Jun 04 12:52:35 PM PDT 24
Finished Jun 04 12:54:11 PM PDT 24
Peak memory 213944 kb
Host smart-7bc95c96-04ac-4705-985d-9b545821e9e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605356472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3605356472
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1256767120
Short name T365
Test name
Test status
Simulation time 413543491 ps
CPU time 8.85 seconds
Started Jun 04 12:52:42 PM PDT 24
Finished Jun 04 12:52:52 PM PDT 24
Peak memory 219476 kb
Host smart-a8862a04-f9ad-4437-ae6e-877bee4e2e82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256767120 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1256767120
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3802791775
Short name T450
Test name
Test status
Simulation time 3663572788 ps
CPU time 29 seconds
Started Jun 04 12:52:35 PM PDT 24
Finished Jun 04 12:53:05 PM PDT 24
Peak memory 211788 kb
Host smart-12ff89b5-4e72-4ead-9d50-1cac96a05129
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802791775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3802791775
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1677375003
Short name T446
Test name
Test status
Simulation time 2110210010 ps
CPU time 56.52 seconds
Started Jun 04 12:52:36 PM PDT 24
Finished Jun 04 12:53:34 PM PDT 24
Peak memory 213468 kb
Host smart-78b60c1c-5a2c-42a8-abbf-ee488bdfd6d1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677375003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1677375003
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.590378879
Short name T459
Test name
Test status
Simulation time 332039950 ps
CPU time 8.29 seconds
Started Jun 04 12:52:35 PM PDT 24
Finished Jun 04 12:52:45 PM PDT 24
Peak memory 211180 kb
Host smart-b35afaf5-bd76-453f-8974-da493f21ac1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590378879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.590378879
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1485647002
Short name T436
Test name
Test status
Simulation time 3773409577 ps
CPU time 22.65 seconds
Started Jun 04 12:52:36 PM PDT 24
Finished Jun 04 12:53:00 PM PDT 24
Peak memory 217340 kb
Host smart-4c0a0ab1-be5e-4a10-a3ac-d8719c9661ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485647002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1485647002
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.471276242
Short name T439
Test name
Test status
Simulation time 5407543567 ps
CPU time 163.75 seconds
Started Jun 04 12:52:35 PM PDT 24
Finished Jun 04 12:55:20 PM PDT 24
Peak memory 214064 kb
Host smart-d633fda4-5d2f-4bd4-aa44-bec16609810d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471276242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.471276242
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3345887672
Short name T366
Test name
Test status
Simulation time 612057321 ps
CPU time 12.97 seconds
Started Jun 04 12:52:40 PM PDT 24
Finished Jun 04 12:52:53 PM PDT 24
Peak memory 216056 kb
Host smart-e98b1735-1481-498e-a837-ffb71ff57f57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345887672 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3345887672
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1812397757
Short name T389
Test name
Test status
Simulation time 2996483627 ps
CPU time 24.91 seconds
Started Jun 04 12:52:49 PM PDT 24
Finished Jun 04 12:53:16 PM PDT 24
Peak memory 211316 kb
Host smart-6eca3519-d895-4f34-913d-a7de577c2f70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812397757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1812397757
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2315045154
Short name T70
Test name
Test status
Simulation time 733590347 ps
CPU time 37.79 seconds
Started Jun 04 12:52:35 PM PDT 24
Finished Jun 04 12:53:14 PM PDT 24
Peak memory 213344 kb
Host smart-eff0bebb-425c-4848-99e4-e82885944ea1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315045154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2315045154
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1454088788
Short name T92
Test name
Test status
Simulation time 5203761908 ps
CPU time 23.15 seconds
Started Jun 04 12:52:40 PM PDT 24
Finished Jun 04 12:53:04 PM PDT 24
Peak memory 212508 kb
Host smart-31d5a55c-d7bd-4cdb-8ff8-de945eeafb64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454088788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1454088788
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4202106762
Short name T391
Test name
Test status
Simulation time 1100923854 ps
CPU time 10.88 seconds
Started Jun 04 12:52:36 PM PDT 24
Finished Jun 04 12:52:48 PM PDT 24
Peak memory 216940 kb
Host smart-3b8f4342-8fe4-48df-b0b2-e3c8c08d4450
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202106762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.4202106762
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.911133255
Short name T444
Test name
Test status
Simulation time 11466932410 ps
CPU time 95.74 seconds
Started Jun 04 12:52:35 PM PDT 24
Finished Jun 04 12:54:12 PM PDT 24
Peak memory 214108 kb
Host smart-0dab8324-c0bc-4de5-a0f3-61375c601a43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911133255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.911133255
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3960801739
Short name T379
Test name
Test status
Simulation time 6883689533 ps
CPU time 19.15 seconds
Started Jun 04 12:52:23 PM PDT 24
Finished Jun 04 12:52:43 PM PDT 24
Peak memory 212128 kb
Host smart-98ccae27-1bca-41ac-bd8d-8f065e4c63f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960801739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3960801739
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2140714490
Short name T418
Test name
Test status
Simulation time 3071235255 ps
CPU time 13.25 seconds
Started Jun 04 12:52:30 PM PDT 24
Finished Jun 04 12:52:44 PM PDT 24
Peak memory 211344 kb
Host smart-f1bf68af-a252-4fd4-a50f-401e345e16a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140714490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2140714490
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4270691347
Short name T457
Test name
Test status
Simulation time 178215716 ps
CPU time 11.66 seconds
Started Jun 04 12:52:23 PM PDT 24
Finished Jun 04 12:52:36 PM PDT 24
Peak memory 211256 kb
Host smart-84cafd44-e184-4ae4-9c25-176a86188fdc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270691347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.4270691347
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.777815137
Short name T410
Test name
Test status
Simulation time 4388543402 ps
CPU time 33.19 seconds
Started Jun 04 12:52:26 PM PDT 24
Finished Jun 04 12:53:01 PM PDT 24
Peak memory 216440 kb
Host smart-545c766d-cfa8-4396-b7c0-2bb44886e197
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777815137 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.777815137
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2137420923
Short name T81
Test name
Test status
Simulation time 3484230974 ps
CPU time 18.94 seconds
Started Jun 04 12:52:24 PM PDT 24
Finished Jun 04 12:52:44 PM PDT 24
Peak memory 211900 kb
Host smart-13bb64b0-9f36-4fe1-84c7-44d70ad50760
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137420923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2137420923
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3239861233
Short name T413
Test name
Test status
Simulation time 15714133730 ps
CPU time 30.44 seconds
Started Jun 04 12:52:33 PM PDT 24
Finished Jun 04 12:53:05 PM PDT 24
Peak memory 211064 kb
Host smart-634fad43-3137-4ce8-b065-44b450c13466
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239861233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3239861233
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3180312266
Short name T406
Test name
Test status
Simulation time 176400459 ps
CPU time 7.97 seconds
Started Jun 04 12:52:29 PM PDT 24
Finished Jun 04 12:52:39 PM PDT 24
Peak memory 211036 kb
Host smart-792e6834-2521-4a7e-8f60-08afc17921cd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180312266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3180312266
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2830456752
Short name T87
Test name
Test status
Simulation time 2866304000 ps
CPU time 37.25 seconds
Started Jun 04 12:52:27 PM PDT 24
Finished Jun 04 12:53:06 PM PDT 24
Peak memory 213184 kb
Host smart-35ca74a2-57c5-497c-918d-6ef6d32ebb5b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830456752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2830456752
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1167150776
Short name T427
Test name
Test status
Simulation time 16695347233 ps
CPU time 37.06 seconds
Started Jun 04 12:52:25 PM PDT 24
Finished Jun 04 12:53:03 PM PDT 24
Peak memory 212780 kb
Host smart-0c021ae8-cd0b-4503-bc5b-f518d6035d97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167150776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1167150776
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3103766959
Short name T368
Test name
Test status
Simulation time 4180405830 ps
CPU time 38.07 seconds
Started Jun 04 12:52:31 PM PDT 24
Finished Jun 04 12:53:11 PM PDT 24
Peak memory 218684 kb
Host smart-0db33e17-5544-4cec-b3b7-02984f88f174
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103766959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3103766959
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3492294731
Short name T55
Test name
Test status
Simulation time 13727983450 ps
CPU time 100.37 seconds
Started Jun 04 12:52:24 PM PDT 24
Finished Jun 04 12:54:06 PM PDT 24
Peak memory 213996 kb
Host smart-f07aad4d-f67f-40bc-9d56-3508c947adad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492294731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3492294731
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2245292187
Short name T64
Test name
Test status
Simulation time 14045036338 ps
CPU time 27.6 seconds
Started Jun 04 12:52:25 PM PDT 24
Finished Jun 04 12:52:53 PM PDT 24
Peak memory 212284 kb
Host smart-90061ed6-d384-4c4e-bcf3-49ddf43838f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245292187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2245292187
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2493216339
Short name T412
Test name
Test status
Simulation time 10653496646 ps
CPU time 22.58 seconds
Started Jun 04 12:52:29 PM PDT 24
Finished Jun 04 12:52:53 PM PDT 24
Peak memory 211596 kb
Host smart-823e63c0-325c-4ff4-a8a6-0a514088767f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493216339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2493216339
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2386162872
Short name T63
Test name
Test status
Simulation time 2484887454 ps
CPU time 29.24 seconds
Started Jun 04 12:52:31 PM PDT 24
Finished Jun 04 12:53:02 PM PDT 24
Peak memory 212016 kb
Host smart-42eb61f4-bf81-4548-bd61-c41dd2fb0254
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386162872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2386162872
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.998182571
Short name T395
Test name
Test status
Simulation time 20039011026 ps
CPU time 19.82 seconds
Started Jun 04 12:52:32 PM PDT 24
Finished Jun 04 12:52:53 PM PDT 24
Peak memory 216568 kb
Host smart-db80b266-aff8-46d1-b056-9daf587ae35d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998182571 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.998182571
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.659852247
Short name T440
Test name
Test status
Simulation time 12219945330 ps
CPU time 26.06 seconds
Started Jun 04 12:52:26 PM PDT 24
Finished Jun 04 12:52:54 PM PDT 24
Peak memory 211960 kb
Host smart-590cbc7e-8057-4ba3-afed-9e97dc324dc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659852247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.659852247
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3544505692
Short name T448
Test name
Test status
Simulation time 4340192612 ps
CPU time 31.85 seconds
Started Jun 04 12:52:26 PM PDT 24
Finished Jun 04 12:53:00 PM PDT 24
Peak memory 211188 kb
Host smart-2dd543f1-fa72-4dc8-88da-d2bce3085799
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544505692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3544505692
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.504325746
Short name T367
Test name
Test status
Simulation time 3293835105 ps
CPU time 26.84 seconds
Started Jun 04 12:52:30 PM PDT 24
Finished Jun 04 12:52:58 PM PDT 24
Peak memory 211236 kb
Host smart-180c29e6-fabf-4d0e-b5fb-34771a96bb8f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504325746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
504325746
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.378412275
Short name T397
Test name
Test status
Simulation time 102950424810 ps
CPU time 192.19 seconds
Started Jun 04 12:52:27 PM PDT 24
Finished Jun 04 12:55:41 PM PDT 24
Peak memory 215620 kb
Host smart-75024859-c9b2-41e2-baa5-6f33cf677d9a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378412275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.378412275
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.852397596
Short name T404
Test name
Test status
Simulation time 6862402759 ps
CPU time 11.5 seconds
Started Jun 04 12:52:25 PM PDT 24
Finished Jun 04 12:52:38 PM PDT 24
Peak memory 211380 kb
Host smart-559f115f-733e-49d3-82df-32e9c1a23c38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852397596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.852397596
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3511923420
Short name T390
Test name
Test status
Simulation time 19307775217 ps
CPU time 35.48 seconds
Started Jun 04 12:52:26 PM PDT 24
Finished Jun 04 12:53:03 PM PDT 24
Peak memory 218800 kb
Host smart-a5e7b877-3e5a-4298-9798-8f860a43aaf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511923420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3511923420
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3246426378
Short name T104
Test name
Test status
Simulation time 3366590660 ps
CPU time 95.19 seconds
Started Jun 04 12:52:25 PM PDT 24
Finished Jun 04 12:54:02 PM PDT 24
Peak memory 212272 kb
Host smart-17713e88-9f41-4190-8396-f7e864f0fc17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246426378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3246426378
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1102059393
Short name T84
Test name
Test status
Simulation time 10268445728 ps
CPU time 27.78 seconds
Started Jun 04 12:52:26 PM PDT 24
Finished Jun 04 12:52:55 PM PDT 24
Peak memory 211976 kb
Host smart-95319d68-4a81-4ad4-8a58-d26033f885e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102059393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1102059393
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4073140986
Short name T411
Test name
Test status
Simulation time 170710488 ps
CPU time 8.4 seconds
Started Jun 04 12:52:26 PM PDT 24
Finished Jun 04 12:52:36 PM PDT 24
Peak memory 211288 kb
Host smart-cfc0f75e-e772-49c6-8558-f5270609f7a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073140986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.4073140986
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2470253243
Short name T428
Test name
Test status
Simulation time 1717299148 ps
CPU time 14.81 seconds
Started Jun 04 12:52:25 PM PDT 24
Finished Jun 04 12:52:41 PM PDT 24
Peak memory 212028 kb
Host smart-2992c078-e302-45a0-a892-0957e763afb1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470253243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2470253243
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2835469044
Short name T416
Test name
Test status
Simulation time 3531584876 ps
CPU time 28.96 seconds
Started Jun 04 12:52:25 PM PDT 24
Finished Jun 04 12:52:55 PM PDT 24
Peak memory 218392 kb
Host smart-f3684498-c073-4632-9cd2-5c9938c59c17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835469044 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2835469044
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.463254608
Short name T378
Test name
Test status
Simulation time 16417322932 ps
CPU time 30.35 seconds
Started Jun 04 12:52:27 PM PDT 24
Finished Jun 04 12:52:59 PM PDT 24
Peak memory 212368 kb
Host smart-e24bb84a-615b-412c-9f46-1e45ce7e5356
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463254608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.463254608
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4126944116
Short name T382
Test name
Test status
Simulation time 2889509188 ps
CPU time 19.28 seconds
Started Jun 04 12:52:28 PM PDT 24
Finished Jun 04 12:52:48 PM PDT 24
Peak memory 210928 kb
Host smart-4422e16f-ce4a-4fb2-97d4-1d6ad3f57d84
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126944116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.4126944116
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.134713708
Short name T423
Test name
Test status
Simulation time 591123671 ps
CPU time 8.19 seconds
Started Jun 04 12:52:31 PM PDT 24
Finished Jun 04 12:52:41 PM PDT 24
Peak memory 211184 kb
Host smart-55133a66-59e2-4862-8072-480547806783
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134713708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
134713708
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2622867608
Short name T89
Test name
Test status
Simulation time 174564833 ps
CPU time 8.41 seconds
Started Jun 04 12:52:25 PM PDT 24
Finished Jun 04 12:52:35 PM PDT 24
Peak memory 211188 kb
Host smart-3085d607-fe48-4bfd-b13a-45a671f48a9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622867608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2622867608
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1442900298
Short name T445
Test name
Test status
Simulation time 3498217477 ps
CPU time 31.11 seconds
Started Jun 04 12:52:27 PM PDT 24
Finished Jun 04 12:53:00 PM PDT 24
Peak memory 217092 kb
Host smart-6d031c44-36e2-4b23-b97e-8a08323ee1d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442900298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1442900298
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2878459738
Short name T114
Test name
Test status
Simulation time 16633568124 ps
CPU time 166.26 seconds
Started Jun 04 12:52:23 PM PDT 24
Finished Jun 04 12:55:10 PM PDT 24
Peak memory 219356 kb
Host smart-ecb4669e-1a67-46e5-9e58-0fc70c54a231
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878459738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2878459738
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3572870310
Short name T381
Test name
Test status
Simulation time 1577475117 ps
CPU time 18.16 seconds
Started Jun 04 12:52:27 PM PDT 24
Finished Jun 04 12:52:47 PM PDT 24
Peak memory 214860 kb
Host smart-e7f94500-0765-48b6-9c16-acf435a28744
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572870310 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3572870310
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1591565089
Short name T400
Test name
Test status
Simulation time 339202618 ps
CPU time 8.3 seconds
Started Jun 04 12:52:33 PM PDT 24
Finished Jun 04 12:52:42 PM PDT 24
Peak memory 211284 kb
Host smart-f4c0985c-392f-4584-9a6c-eb39872f1c18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591565089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1591565089
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.919137792
Short name T97
Test name
Test status
Simulation time 24606473462 ps
CPU time 127.63 seconds
Started Jun 04 12:52:25 PM PDT 24
Finished Jun 04 12:54:33 PM PDT 24
Peak memory 215436 kb
Host smart-daa388bd-a8e0-4278-8464-b35e4d186295
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919137792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.919137792
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3415898100
Short name T449
Test name
Test status
Simulation time 3204687404 ps
CPU time 27.7 seconds
Started Jun 04 12:52:24 PM PDT 24
Finished Jun 04 12:52:53 PM PDT 24
Peak memory 212424 kb
Host smart-a0fb789b-2a26-40b2-8d6e-a071204cc8da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415898100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3415898100
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2633828020
Short name T370
Test name
Test status
Simulation time 611884592 ps
CPU time 10.98 seconds
Started Jun 04 12:52:30 PM PDT 24
Finished Jun 04 12:52:43 PM PDT 24
Peak memory 217120 kb
Host smart-4f29da94-7b11-4a82-a6ab-8340831dc6df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633828020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2633828020
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1537305490
Short name T387
Test name
Test status
Simulation time 8528623600 ps
CPU time 104.92 seconds
Started Jun 04 12:52:33 PM PDT 24
Finished Jun 04 12:54:19 PM PDT 24
Peak memory 213808 kb
Host smart-6ce0c24e-dde1-4f01-9eec-370dff3e0d7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537305490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1537305490
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1388505886
Short name T437
Test name
Test status
Simulation time 190690132 ps
CPU time 9.01 seconds
Started Jun 04 12:52:30 PM PDT 24
Finished Jun 04 12:52:41 PM PDT 24
Peak memory 216652 kb
Host smart-a67c2059-21f2-4b9f-9e49-8696d807dc2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388505886 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1388505886
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2783887329
Short name T396
Test name
Test status
Simulation time 3829963207 ps
CPU time 31.27 seconds
Started Jun 04 12:52:24 PM PDT 24
Finished Jun 04 12:52:56 PM PDT 24
Peak memory 211516 kb
Host smart-bb49eda3-e8ac-4957-a5ee-4b0e75411130
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783887329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2783887329
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.460886941
Short name T86
Test name
Test status
Simulation time 1448330253 ps
CPU time 37.9 seconds
Started Jun 04 12:52:27 PM PDT 24
Finished Jun 04 12:53:07 PM PDT 24
Peak memory 213668 kb
Host smart-46519e94-899f-4f98-aed1-834d9a660d3d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460886941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.460886941
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.15847689
Short name T424
Test name
Test status
Simulation time 613340203 ps
CPU time 8.37 seconds
Started Jun 04 12:52:34 PM PDT 24
Finished Jun 04 12:52:43 PM PDT 24
Peak memory 211260 kb
Host smart-bdcca9ee-e727-4b17-b902-dc390360d3e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15847689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctr
l_same_csr_outstanding.15847689
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3553727717
Short name T399
Test name
Test status
Simulation time 257717016 ps
CPU time 14.56 seconds
Started Jun 04 12:52:31 PM PDT 24
Finished Jun 04 12:52:48 PM PDT 24
Peak memory 218396 kb
Host smart-56908f71-4a73-44c1-98de-d8aa7d51441e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553727717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3553727717
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.782868157
Short name T435
Test name
Test status
Simulation time 4316514508 ps
CPU time 97.63 seconds
Started Jun 04 12:52:26 PM PDT 24
Finished Jun 04 12:54:05 PM PDT 24
Peak memory 213940 kb
Host smart-0d5c3094-e0fd-4d18-8141-499315b89b5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782868157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.782868157
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2044902736
Short name T59
Test name
Test status
Simulation time 257130138 ps
CPU time 10 seconds
Started Jun 04 12:52:36 PM PDT 24
Finished Jun 04 12:52:47 PM PDT 24
Peak memory 214164 kb
Host smart-bee0ac92-c5d0-4f36-9bf0-5c36c9eefb0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044902736 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2044902736
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2977542278
Short name T438
Test name
Test status
Simulation time 1816284217 ps
CPU time 16.65 seconds
Started Jun 04 12:52:33 PM PDT 24
Finished Jun 04 12:52:50 PM PDT 24
Peak memory 211980 kb
Host smart-bde4cacc-80c0-4d08-bad3-4f1c64b74851
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977542278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2977542278
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1435722291
Short name T433
Test name
Test status
Simulation time 51489912724 ps
CPU time 132.56 seconds
Started Jun 04 12:52:26 PM PDT 24
Finished Jun 04 12:54:39 PM PDT 24
Peak memory 215520 kb
Host smart-a5c04c04-dd55-4559-92bd-7fef884e5e1e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435722291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1435722291
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3952123133
Short name T91
Test name
Test status
Simulation time 730108406 ps
CPU time 12.02 seconds
Started Jun 04 12:52:26 PM PDT 24
Finished Jun 04 12:52:40 PM PDT 24
Peak memory 212416 kb
Host smart-6051dcd8-cf5f-4404-9dbb-eac5005e8316
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952123133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3952123133
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.593807426
Short name T369
Test name
Test status
Simulation time 241481677 ps
CPU time 11.89 seconds
Started Jun 04 12:52:34 PM PDT 24
Finished Jun 04 12:52:46 PM PDT 24
Peak memory 216252 kb
Host smart-093c4032-4ef7-4356-b733-a6c0dc79eda6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593807426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.593807426
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1562708875
Short name T383
Test name
Test status
Simulation time 2219876509 ps
CPU time 15.92 seconds
Started Jun 04 12:52:29 PM PDT 24
Finished Jun 04 12:52:46 PM PDT 24
Peak memory 219584 kb
Host smart-cc795f9a-9deb-45d0-88be-7328d9b77ac2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562708875 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1562708875
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4285191293
Short name T398
Test name
Test status
Simulation time 353121738 ps
CPU time 8.08 seconds
Started Jun 04 12:52:27 PM PDT 24
Finished Jun 04 12:52:37 PM PDT 24
Peak memory 211216 kb
Host smart-13db0816-968f-43d3-83ac-d2b4b1be3229
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285191293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.4285191293
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1885230480
Short name T85
Test name
Test status
Simulation time 131734382454 ps
CPU time 121.82 seconds
Started Jun 04 12:52:31 PM PDT 24
Finished Jun 04 12:54:34 PM PDT 24
Peak memory 213400 kb
Host smart-002fcdcb-4268-43a9-95d5-f2db34aa0601
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885230480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1885230480
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2309343633
Short name T422
Test name
Test status
Simulation time 1481374722 ps
CPU time 21.5 seconds
Started Jun 04 12:52:28 PM PDT 24
Finished Jun 04 12:52:51 PM PDT 24
Peak memory 212676 kb
Host smart-69332b18-3e13-42c8-8003-b19ba76dd485
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309343633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2309343633
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1130291455
Short name T407
Test name
Test status
Simulation time 9963659909 ps
CPU time 24.85 seconds
Started Jun 04 12:52:29 PM PDT 24
Finished Jun 04 12:52:55 PM PDT 24
Peak memory 219576 kb
Host smart-ba73c0d2-cda2-4e1e-8abd-9ec72d61ca8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130291455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1130291455
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4036648168
Short name T441
Test name
Test status
Simulation time 1103297956 ps
CPU time 11.69 seconds
Started Jun 04 12:52:25 PM PDT 24
Finished Jun 04 12:52:38 PM PDT 24
Peak memory 217672 kb
Host smart-a0f9c7d3-6d25-4700-8111-fe3cf194f1e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036648168 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.4036648168
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.463988080
Short name T67
Test name
Test status
Simulation time 73978967169 ps
CPU time 31.02 seconds
Started Jun 04 12:52:32 PM PDT 24
Finished Jun 04 12:53:05 PM PDT 24
Peak memory 212424 kb
Host smart-96293b18-77e9-4562-bfa8-5aa4802fb37a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463988080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.463988080
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.4222253035
Short name T98
Test name
Test status
Simulation time 15445325838 ps
CPU time 123.46 seconds
Started Jun 04 12:52:29 PM PDT 24
Finished Jun 04 12:54:33 PM PDT 24
Peak memory 214392 kb
Host smart-6fe2e4fd-1f98-45cc-b75b-ecb00ddfb140
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222253035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.4222253035
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.987523376
Short name T93
Test name
Test status
Simulation time 1640789936 ps
CPU time 18.25 seconds
Started Jun 04 12:52:34 PM PDT 24
Finished Jun 04 12:52:53 PM PDT 24
Peak memory 212436 kb
Host smart-b9d420d4-89ca-48e8-a304-4934ac32e2d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987523376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.987523376
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.772248772
Short name T392
Test name
Test status
Simulation time 14287189017 ps
CPU time 32.62 seconds
Started Jun 04 12:52:30 PM PDT 24
Finished Jun 04 12:53:04 PM PDT 24
Peak memory 219504 kb
Host smart-2f6bc994-9f93-47d0-a6ad-dea58688213c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772248772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.772248772
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1442973789
Short name T113
Test name
Test status
Simulation time 12117098392 ps
CPU time 163.72 seconds
Started Jun 04 12:52:27 PM PDT 24
Finished Jun 04 12:55:13 PM PDT 24
Peak memory 214212 kb
Host smart-0021d277-6fdc-4303-9aa2-b895ae9a778a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442973789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1442973789
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2625399934
Short name T61
Test name
Test status
Simulation time 4259643875 ps
CPU time 34.43 seconds
Started Jun 04 01:39:47 PM PDT 24
Finished Jun 04 01:40:24 PM PDT 24
Peak memory 211396 kb
Host smart-16e00c3f-6ac9-4db1-952f-29d9bff9ce20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625399934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2625399934
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1914468427
Short name T323
Test name
Test status
Simulation time 125455699719 ps
CPU time 402.33 seconds
Started Jun 04 01:39:52 PM PDT 24
Finished Jun 04 01:46:36 PM PDT 24
Peak memory 240520 kb
Host smart-79e9a068-8653-4b65-a36f-8c28fff444e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914468427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1914468427
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3996622130
Short name T182
Test name
Test status
Simulation time 31987675643 ps
CPU time 69.06 seconds
Started Jun 04 01:39:46 PM PDT 24
Finished Jun 04 01:40:57 PM PDT 24
Peak memory 215092 kb
Host smart-869e8475-e54c-4ce2-9c8f-e0987f8eec21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996622130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3996622130
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2071670373
Short name T217
Test name
Test status
Simulation time 3630979214 ps
CPU time 32.26 seconds
Started Jun 04 01:39:47 PM PDT 24
Finished Jun 04 01:40:21 PM PDT 24
Peak memory 211588 kb
Host smart-74c93897-22a4-4bc8-b8d3-574a74f03b0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2071670373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2071670373
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1028625507
Short name T29
Test name
Test status
Simulation time 5346854509 ps
CPU time 134.94 seconds
Started Jun 04 01:39:44 PM PDT 24
Finished Jun 04 01:42:01 PM PDT 24
Peak memory 239104 kb
Host smart-d071bdac-913b-4aa5-a8dc-6f344b954fa8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028625507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1028625507
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2345066628
Short name T342
Test name
Test status
Simulation time 6210634791 ps
CPU time 61.61 seconds
Started Jun 04 01:39:53 PM PDT 24
Finished Jun 04 01:40:56 PM PDT 24
Peak memory 217536 kb
Host smart-70ab8d68-7bcb-496b-968f-d9136dd3a12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345066628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2345066628
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1754127522
Short name T119
Test name
Test status
Simulation time 7241955077 ps
CPU time 42.53 seconds
Started Jun 04 01:39:47 PM PDT 24
Finished Jun 04 01:40:31 PM PDT 24
Peak memory 219220 kb
Host smart-5f1f7698-ba99-4bc2-9f88-7194f7399c5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754127522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1754127522
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1517137075
Short name T363
Test name
Test status
Simulation time 4591795926 ps
CPU time 16.2 seconds
Started Jun 04 01:39:46 PM PDT 24
Finished Jun 04 01:40:04 PM PDT 24
Peak memory 211436 kb
Host smart-0ffd4204-682f-4351-8896-dceebf14a2c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517137075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1517137075
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1559232331
Short name T156
Test name
Test status
Simulation time 5128569819 ps
CPU time 212.93 seconds
Started Jun 04 01:39:45 PM PDT 24
Finished Jun 04 01:43:20 PM PDT 24
Peak memory 238120 kb
Host smart-bdbb9e11-dd7f-40a9-b8b3-a66fb7b3dd72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559232331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1559232331
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1125492110
Short name T329
Test name
Test status
Simulation time 1439401659 ps
CPU time 19.4 seconds
Started Jun 04 01:39:46 PM PDT 24
Finished Jun 04 01:40:07 PM PDT 24
Peak memory 216372 kb
Host smart-9e3f0f98-e52a-47fe-808b-d742de220aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125492110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1125492110
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2546272641
Short name T179
Test name
Test status
Simulation time 13139178898 ps
CPU time 29.51 seconds
Started Jun 04 01:39:46 PM PDT 24
Finished Jun 04 01:40:18 PM PDT 24
Peak memory 211640 kb
Host smart-7b79d48f-c584-4137-a624-2c1c982c1e45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2546272641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2546272641
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.715871669
Short name T33
Test name
Test status
Simulation time 17545298794 ps
CPU time 139.91 seconds
Started Jun 04 01:39:46 PM PDT 24
Finished Jun 04 01:42:07 PM PDT 24
Peak memory 237900 kb
Host smart-f030740f-e38d-4673-ad98-0f5de11250ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715871669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.715871669
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2644538940
Short name T140
Test name
Test status
Simulation time 36915882917 ps
CPU time 48.38 seconds
Started Jun 04 01:39:45 PM PDT 24
Finished Jun 04 01:40:35 PM PDT 24
Peak memory 218040 kb
Host smart-0f8723cd-cbc6-4676-828f-f1c3fc18192a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644538940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2644538940
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1906187252
Short name T339
Test name
Test status
Simulation time 518590521574 ps
CPU time 2730.84 seconds
Started Jun 04 01:39:45 PM PDT 24
Finished Jun 04 02:25:18 PM PDT 24
Peak memory 244048 kb
Host smart-aac62154-6b41-4ccb-a62d-b099ca5cda99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906187252 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.1906187252
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2840781379
Short name T191
Test name
Test status
Simulation time 114276402196 ps
CPU time 321.8 seconds
Started Jun 04 01:40:07 PM PDT 24
Finished Jun 04 01:45:30 PM PDT 24
Peak memory 240316 kb
Host smart-3e222a37-eba8-4b2f-97e0-f5ddb32bef6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840781379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2840781379
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.4009618017
Short name T341
Test name
Test status
Simulation time 1319148528 ps
CPU time 19.26 seconds
Started Jun 04 01:40:05 PM PDT 24
Finished Jun 04 01:40:26 PM PDT 24
Peak memory 214800 kb
Host smart-54cf5527-9bce-4609-9d27-96d6f1d1930b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009618017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.4009618017
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.792094834
Short name T362
Test name
Test status
Simulation time 734504697 ps
CPU time 10.58 seconds
Started Jun 04 01:40:08 PM PDT 24
Finished Jun 04 01:40:20 PM PDT 24
Peak memory 211624 kb
Host smart-b2fe0910-d8da-4b14-bfe7-6b15456fff80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=792094834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.792094834
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2125668222
Short name T245
Test name
Test status
Simulation time 17770446771 ps
CPU time 51 seconds
Started Jun 04 01:40:07 PM PDT 24
Finished Jun 04 01:40:59 PM PDT 24
Peak memory 218104 kb
Host smart-86a0dced-8740-46b6-a879-3422ce683036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125668222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2125668222
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1222363005
Short name T256
Test name
Test status
Simulation time 9286694296 ps
CPU time 85.81 seconds
Started Jun 04 01:40:08 PM PDT 24
Finished Jun 04 01:41:35 PM PDT 24
Peak memory 219592 kb
Host smart-a4be4525-785e-4bf9-ac72-f54ca43e5f53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222363005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1222363005
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3784162057
Short name T326
Test name
Test status
Simulation time 4464982388 ps
CPU time 32.57 seconds
Started Jun 04 01:40:07 PM PDT 24
Finished Jun 04 01:40:41 PM PDT 24
Peak memory 212300 kb
Host smart-05fb44e2-227b-4e2f-a38c-120838496655
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784162057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3784162057
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2577690080
Short name T41
Test name
Test status
Simulation time 2107634704 ps
CPU time 151.49 seconds
Started Jun 04 01:40:04 PM PDT 24
Finished Jun 04 01:42:36 PM PDT 24
Peak memory 239620 kb
Host smart-a2b53f6c-9bde-4e5a-be10-9b7ebb04818d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577690080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2577690080
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3268051052
Short name T357
Test name
Test status
Simulation time 3854536891 ps
CPU time 32.74 seconds
Started Jun 04 01:40:08 PM PDT 24
Finished Jun 04 01:40:42 PM PDT 24
Peak memory 211408 kb
Host smart-3fe5b465-2375-4e15-92e7-d096ddd70ada
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3268051052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3268051052
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.402241394
Short name T101
Test name
Test status
Simulation time 5878736097 ps
CPU time 53.25 seconds
Started Jun 04 01:40:06 PM PDT 24
Finished Jun 04 01:41:00 PM PDT 24
Peak memory 215500 kb
Host smart-dd491d00-58e3-43a3-89f3-1bd49944ec13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402241394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.402241394
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3831811871
Short name T197
Test name
Test status
Simulation time 4584756564 ps
CPU time 49.94 seconds
Started Jun 04 01:40:08 PM PDT 24
Finished Jun 04 01:41:00 PM PDT 24
Peak memory 218084 kb
Host smart-c0460086-4f3d-43b2-8730-33d7fe2db4ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831811871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3831811871
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3828502697
Short name T31
Test name
Test status
Simulation time 3403824604 ps
CPU time 28.41 seconds
Started Jun 04 01:40:07 PM PDT 24
Finished Jun 04 01:40:37 PM PDT 24
Peak memory 211944 kb
Host smart-6ef79565-2d0a-4718-9df1-4e76dd6113ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828502697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3828502697
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3621041987
Short name T303
Test name
Test status
Simulation time 3445430585 ps
CPU time 127.25 seconds
Started Jun 04 01:40:08 PM PDT 24
Finished Jun 04 01:42:17 PM PDT 24
Peak memory 225800 kb
Host smart-ca26d9a1-2cdb-473c-9bd7-38e71f3d656b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621041987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3621041987
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3430468699
Short name T264
Test name
Test status
Simulation time 7104091688 ps
CPU time 63.39 seconds
Started Jun 04 01:40:11 PM PDT 24
Finished Jun 04 01:41:15 PM PDT 24
Peak memory 215136 kb
Host smart-a2099110-3fbf-4a2f-b5c6-fdb0088ad76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430468699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3430468699
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2588894033
Short name T322
Test name
Test status
Simulation time 689245591 ps
CPU time 12.81 seconds
Started Jun 04 01:40:10 PM PDT 24
Finished Jun 04 01:40:23 PM PDT 24
Peak memory 211340 kb
Host smart-dae2e757-4a7d-4bf3-90b1-92107b2afc4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2588894033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2588894033
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2652556457
Short name T187
Test name
Test status
Simulation time 716597751 ps
CPU time 20.56 seconds
Started Jun 04 01:40:08 PM PDT 24
Finished Jun 04 01:40:30 PM PDT 24
Peak memory 217676 kb
Host smart-0dbea353-4c15-4471-9389-6970172699a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652556457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2652556457
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.174510427
Short name T193
Test name
Test status
Simulation time 17296819247 ps
CPU time 26.39 seconds
Started Jun 04 01:40:07 PM PDT 24
Finished Jun 04 01:40:35 PM PDT 24
Peak memory 214180 kb
Host smart-0ba0f77d-7700-41a1-8601-f2a1788e70a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174510427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.174510427
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1996204895
Short name T216
Test name
Test status
Simulation time 5536559256 ps
CPU time 24.77 seconds
Started Jun 04 01:40:09 PM PDT 24
Finished Jun 04 01:40:35 PM PDT 24
Peak memory 211476 kb
Host smart-dff64b7d-857c-498b-91b5-5caaa7816878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996204895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1996204895
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.764905196
Short name T345
Test name
Test status
Simulation time 33707008864 ps
CPU time 535.46 seconds
Started Jun 04 01:40:09 PM PDT 24
Finished Jun 04 01:49:06 PM PDT 24
Peak memory 241004 kb
Host smart-7bb532f1-76f0-46b0-a027-cf32b4f93c90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764905196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.764905196
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2095769850
Short name T265
Test name
Test status
Simulation time 48350854529 ps
CPU time 66.1 seconds
Started Jun 04 01:40:09 PM PDT 24
Finished Jun 04 01:41:16 PM PDT 24
Peak memory 215244 kb
Host smart-e9baf3e5-7dda-4ca5-b8bf-0c7bd0735ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095769850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2095769850
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3796271478
Short name T52
Test name
Test status
Simulation time 467896384 ps
CPU time 12.22 seconds
Started Jun 04 01:40:08 PM PDT 24
Finished Jun 04 01:40:21 PM PDT 24
Peak memory 211680 kb
Host smart-636714b5-df75-4a37-8b82-671ae1bf2c4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3796271478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3796271478
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2035415820
Short name T118
Test name
Test status
Simulation time 17806687658 ps
CPU time 45.68 seconds
Started Jun 04 01:40:12 PM PDT 24
Finished Jun 04 01:40:58 PM PDT 24
Peak memory 217560 kb
Host smart-b7c030ff-3f39-4863-9daa-ee083c04186f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035415820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2035415820
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3714891581
Short name T268
Test name
Test status
Simulation time 1972202367 ps
CPU time 51.22 seconds
Started Jun 04 01:40:08 PM PDT 24
Finished Jun 04 01:41:00 PM PDT 24
Peak memory 219252 kb
Host smart-154731c7-a956-4671-bab9-c28ef132b88e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714891581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3714891581
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1025979029
Short name T247
Test name
Test status
Simulation time 342404170 ps
CPU time 10.74 seconds
Started Jun 04 01:40:15 PM PDT 24
Finished Jun 04 01:40:27 PM PDT 24
Peak memory 211372 kb
Host smart-3ea58207-f8a7-4449-ad29-e940d9f7d419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025979029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1025979029
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2105976273
Short name T351
Test name
Test status
Simulation time 87492267538 ps
CPU time 551.79 seconds
Started Jun 04 01:40:17 PM PDT 24
Finished Jun 04 01:49:30 PM PDT 24
Peak memory 240552 kb
Host smart-abb747a3-bce6-4060-a917-a82ef607638b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105976273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2105976273
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2464996811
Short name T321
Test name
Test status
Simulation time 3110754322 ps
CPU time 29.21 seconds
Started Jun 04 01:40:13 PM PDT 24
Finished Jun 04 01:40:44 PM PDT 24
Peak memory 211456 kb
Host smart-f98f8474-9ee5-4582-b262-8994cf2b51cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2464996811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2464996811
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3626893093
Short name T186
Test name
Test status
Simulation time 44400132173 ps
CPU time 50.57 seconds
Started Jun 04 01:40:10 PM PDT 24
Finished Jun 04 01:41:01 PM PDT 24
Peak memory 217984 kb
Host smart-44ba9494-534b-4703-a262-7bab05aa3a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626893093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3626893093
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2494683596
Short name T150
Test name
Test status
Simulation time 10511887579 ps
CPU time 84.15 seconds
Started Jun 04 01:40:08 PM PDT 24
Finished Jun 04 01:41:34 PM PDT 24
Peak memory 219424 kb
Host smart-572431ae-5c9f-4d69-89ff-3ba214ffe380
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494683596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2494683596
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3583914918
Short name T278
Test name
Test status
Simulation time 16013131284 ps
CPU time 30.49 seconds
Started Jun 04 01:40:17 PM PDT 24
Finished Jun 04 01:40:49 PM PDT 24
Peak memory 212132 kb
Host smart-69e43bdf-2e01-4bc0-8424-26c3844fafc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583914918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3583914918
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2258591594
Short name T35
Test name
Test status
Simulation time 6363038101 ps
CPU time 242.75 seconds
Started Jun 04 01:40:18 PM PDT 24
Finished Jun 04 01:44:22 PM PDT 24
Peak memory 239580 kb
Host smart-359f3924-b671-4e12-b21f-8e6311afacd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258591594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2258591594
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3586165355
Short name T344
Test name
Test status
Simulation time 38500162521 ps
CPU time 57.44 seconds
Started Jun 04 01:40:14 PM PDT 24
Finished Jun 04 01:41:13 PM PDT 24
Peak memory 215656 kb
Host smart-eed21c76-b571-4e0a-9310-73f76d5bf1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586165355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3586165355
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.287096186
Short name T291
Test name
Test status
Simulation time 1752479164 ps
CPU time 20.48 seconds
Started Jun 04 01:40:15 PM PDT 24
Finished Jun 04 01:40:37 PM PDT 24
Peak memory 211548 kb
Host smart-b6d43448-6724-478a-aa7a-fae3cfdac179
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=287096186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.287096186
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3610983899
Short name T37
Test name
Test status
Simulation time 1554506851 ps
CPU time 19.51 seconds
Started Jun 04 01:40:16 PM PDT 24
Finished Jun 04 01:40:37 PM PDT 24
Peak memory 216808 kb
Host smart-c29acf9f-0254-46f5-8c11-682eb8b7110e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610983899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3610983899
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.890674288
Short name T190
Test name
Test status
Simulation time 26618452866 ps
CPU time 111.74 seconds
Started Jun 04 01:40:16 PM PDT 24
Finished Jun 04 01:42:09 PM PDT 24
Peak memory 220616 kb
Host smart-c036f3d2-67bd-46a9-8282-2ad96f10539e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890674288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.890674288
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.400119922
Short name T232
Test name
Test status
Simulation time 338891999 ps
CPU time 8.04 seconds
Started Jun 04 01:40:17 PM PDT 24
Finished Jun 04 01:40:26 PM PDT 24
Peak memory 211260 kb
Host smart-9e5e4b96-9222-4eda-8f3b-c1c183e0eea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400119922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.400119922
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.4031636760
Short name T234
Test name
Test status
Simulation time 58393813997 ps
CPU time 657.78 seconds
Started Jun 04 01:40:15 PM PDT 24
Finished Jun 04 01:51:14 PM PDT 24
Peak memory 234936 kb
Host smart-df2347fc-fa4c-467b-ab51-69de28355935
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031636760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.4031636760
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1181419890
Short name T299
Test name
Test status
Simulation time 35550262040 ps
CPU time 57.56 seconds
Started Jun 04 01:40:14 PM PDT 24
Finished Jun 04 01:41:13 PM PDT 24
Peak memory 215200 kb
Host smart-7a069cb2-a58d-47cd-9e57-f02deeb7675c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181419890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1181419890
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1173161045
Short name T320
Test name
Test status
Simulation time 6936386330 ps
CPU time 20.12 seconds
Started Jun 04 01:40:13 PM PDT 24
Finished Jun 04 01:40:34 PM PDT 24
Peak memory 212660 kb
Host smart-bd388cdf-a6f2-4871-8ea8-b1d09ec9e278
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1173161045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1173161045
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1489719246
Short name T221
Test name
Test status
Simulation time 30658775876 ps
CPU time 57.74 seconds
Started Jun 04 01:40:18 PM PDT 24
Finished Jun 04 01:41:17 PM PDT 24
Peak memory 217952 kb
Host smart-de24a3c1-21c5-4545-a1b2-d36d03950f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489719246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1489719246
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1436548145
Short name T273
Test name
Test status
Simulation time 10615506774 ps
CPU time 127.03 seconds
Started Jun 04 01:40:14 PM PDT 24
Finished Jun 04 01:42:23 PM PDT 24
Peak memory 219884 kb
Host smart-2c8a1254-c995-4033-9fc0-35a3429c62f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436548145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1436548145
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1965544197
Short name T201
Test name
Test status
Simulation time 4340344902 ps
CPU time 32.47 seconds
Started Jun 04 01:40:16 PM PDT 24
Finished Jun 04 01:40:50 PM PDT 24
Peak memory 212300 kb
Host smart-4c223c84-6be0-48e7-bd49-c39552a42e4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965544197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1965544197
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.4122593640
Short name T328
Test name
Test status
Simulation time 413131101111 ps
CPU time 542.57 seconds
Started Jun 04 01:40:16 PM PDT 24
Finished Jun 04 01:49:20 PM PDT 24
Peak memory 228860 kb
Host smart-9df3631d-c23b-4fcb-97e0-3d83f6f3eb79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122593640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.4122593640
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2568849811
Short name T178
Test name
Test status
Simulation time 6267651408 ps
CPU time 30.61 seconds
Started Jun 04 01:40:15 PM PDT 24
Finished Jun 04 01:40:47 PM PDT 24
Peak memory 215452 kb
Host smart-10bdb6a3-b47d-42be-9eef-95647094ef71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568849811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2568849811
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.530354857
Short name T310
Test name
Test status
Simulation time 2532363657 ps
CPU time 25.38 seconds
Started Jun 04 01:40:13 PM PDT 24
Finished Jun 04 01:40:39 PM PDT 24
Peak memory 211792 kb
Host smart-5381c017-26f0-4c13-860d-907964bf3ed2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=530354857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.530354857
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.628613258
Short name T74
Test name
Test status
Simulation time 4236331374 ps
CPU time 24.01 seconds
Started Jun 04 01:40:16 PM PDT 24
Finished Jun 04 01:40:41 PM PDT 24
Peak memory 217788 kb
Host smart-a202fcbb-7a41-4d49-8a02-cfb4ad158bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628613258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.628613258
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1552161898
Short name T262
Test name
Test status
Simulation time 17158228868 ps
CPU time 50.87 seconds
Started Jun 04 01:40:16 PM PDT 24
Finished Jun 04 01:41:08 PM PDT 24
Peak memory 218536 kb
Host smart-a1fb002e-def8-46c7-90b9-8ad25ae2f285
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552161898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1552161898
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1404001416
Short name T324
Test name
Test status
Simulation time 26710698754 ps
CPU time 31.73 seconds
Started Jun 04 01:40:17 PM PDT 24
Finished Jun 04 01:40:50 PM PDT 24
Peak memory 212296 kb
Host smart-a8fad5fd-5461-42e3-aeb8-f7bde2a7eaf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404001416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1404001416
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3191048717
Short name T169
Test name
Test status
Simulation time 204249186755 ps
CPU time 316.38 seconds
Started Jun 04 01:40:13 PM PDT 24
Finished Jun 04 01:45:31 PM PDT 24
Peak memory 218076 kb
Host smart-d45b49cc-42b2-4ca7-99ab-32d91f261251
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191048717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3191048717
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1231501030
Short name T18
Test name
Test status
Simulation time 1367332432 ps
CPU time 29 seconds
Started Jun 04 01:40:17 PM PDT 24
Finished Jun 04 01:40:47 PM PDT 24
Peak memory 214800 kb
Host smart-a170bfca-5241-4e81-b7aa-1e207c41f2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231501030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1231501030
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.894519846
Short name T121
Test name
Test status
Simulation time 11376520392 ps
CPU time 16.24 seconds
Started Jun 04 01:40:15 PM PDT 24
Finished Jun 04 01:40:32 PM PDT 24
Peak memory 212968 kb
Host smart-5112efd3-8701-4bb5-b9af-4d52659f7114
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=894519846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.894519846
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3440758983
Short name T134
Test name
Test status
Simulation time 725202101 ps
CPU time 19.75 seconds
Started Jun 04 01:40:16 PM PDT 24
Finished Jun 04 01:40:37 PM PDT 24
Peak memory 215780 kb
Host smart-1f976e67-e65b-49a9-91cc-e17491c3d9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440758983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3440758983
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.21893993
Short name T177
Test name
Test status
Simulation time 69421107760 ps
CPU time 147.44 seconds
Started Jun 04 01:40:17 PM PDT 24
Finished Jun 04 01:42:45 PM PDT 24
Peak memory 221060 kb
Host smart-d88dd9a8-734a-4b2e-9d23-7c9a14cb62d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21893993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 18.rom_ctrl_stress_all.21893993
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1564112689
Short name T252
Test name
Test status
Simulation time 244846176 ps
CPU time 8.43 seconds
Started Jun 04 01:40:24 PM PDT 24
Finished Jun 04 01:40:34 PM PDT 24
Peak memory 211340 kb
Host smart-e2bb050e-6542-4edf-81e0-4e5c92678aa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564112689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1564112689
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4039344305
Short name T317
Test name
Test status
Simulation time 78898647928 ps
CPU time 299.44 seconds
Started Jun 04 01:40:13 PM PDT 24
Finished Jun 04 01:45:14 PM PDT 24
Peak memory 225816 kb
Host smart-984b7d4b-eff4-4cab-a689-aa30a5fce04a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039344305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.4039344305
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.847119141
Short name T305
Test name
Test status
Simulation time 10818420236 ps
CPU time 52.12 seconds
Started Jun 04 01:40:28 PM PDT 24
Finished Jun 04 01:41:22 PM PDT 24
Peak memory 215124 kb
Host smart-a81cae22-c376-47d9-ab36-d23a6b5d4438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847119141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.847119141
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2807100153
Short name T1
Test name
Test status
Simulation time 3776230457 ps
CPU time 30.91 seconds
Started Jun 04 01:40:18 PM PDT 24
Finished Jun 04 01:40:50 PM PDT 24
Peak memory 211584 kb
Host smart-8b239b75-c3e3-41e3-944c-e82443c1728f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2807100153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2807100153
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3142462829
Short name T359
Test name
Test status
Simulation time 8046676208 ps
CPU time 82.33 seconds
Started Jun 04 01:40:17 PM PDT 24
Finished Jun 04 01:41:40 PM PDT 24
Peak memory 218060 kb
Host smart-d8fc8122-f92e-43d4-9652-ef00ef518a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142462829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3142462829
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.249933867
Short name T319
Test name
Test status
Simulation time 4289896052 ps
CPU time 67.05 seconds
Started Jun 04 01:40:14 PM PDT 24
Finished Jun 04 01:41:22 PM PDT 24
Peak memory 221728 kb
Host smart-92eea4bd-9fd6-4877-b17c-d91b46f36c87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249933867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.249933867
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3013117072
Short name T212
Test name
Test status
Simulation time 1177515543 ps
CPU time 8.66 seconds
Started Jun 04 01:39:53 PM PDT 24
Finished Jun 04 01:40:03 PM PDT 24
Peak memory 211344 kb
Host smart-4b017bb2-455f-45c7-a135-7b5b3657a50f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013117072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3013117072
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.112517830
Short name T259
Test name
Test status
Simulation time 5080419085 ps
CPU time 147.21 seconds
Started Jun 04 01:39:46 PM PDT 24
Finished Jun 04 01:42:15 PM PDT 24
Peak memory 217940 kb
Host smart-676f71dd-1563-4e03-b7b8-4707f45f2f05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112517830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.112517830
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1636111184
Short name T338
Test name
Test status
Simulation time 944761335 ps
CPU time 19.08 seconds
Started Jun 04 01:39:47 PM PDT 24
Finished Jun 04 01:40:08 PM PDT 24
Peak memory 214700 kb
Host smart-30df6938-cada-4d0f-8758-ae0c87240494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636111184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1636111184
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3431038060
Short name T160
Test name
Test status
Simulation time 719903515 ps
CPU time 10.28 seconds
Started Jun 04 01:39:46 PM PDT 24
Finished Jun 04 01:39:58 PM PDT 24
Peak memory 212608 kb
Host smart-04de74f3-475b-4838-9f8b-5ebf70095a72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3431038060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3431038060
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.478907743
Short name T139
Test name
Test status
Simulation time 7737066443 ps
CPU time 47.04 seconds
Started Jun 04 01:39:45 PM PDT 24
Finished Jun 04 01:40:34 PM PDT 24
Peak memory 219344 kb
Host smart-5fad79af-b72e-44e3-a717-e1e82e4bd4ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478907743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.478907743
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3953406723
Short name T313
Test name
Test status
Simulation time 7809782058 ps
CPU time 30.14 seconds
Started Jun 04 01:40:27 PM PDT 24
Finished Jun 04 01:40:59 PM PDT 24
Peak memory 212292 kb
Host smart-64877d07-a072-4234-a2c8-ced92e292b20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953406723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3953406723
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2116041913
Short name T198
Test name
Test status
Simulation time 60531637743 ps
CPU time 504.58 seconds
Started Jun 04 01:40:25 PM PDT 24
Finished Jun 04 01:48:52 PM PDT 24
Peak memory 229696 kb
Host smart-8406eee3-21bc-4b4e-bc00-fd963869a9c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116041913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2116041913
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3613316583
Short name T236
Test name
Test status
Simulation time 4471746688 ps
CPU time 46.53 seconds
Started Jun 04 01:40:29 PM PDT 24
Finished Jun 04 01:41:18 PM PDT 24
Peak memory 215112 kb
Host smart-61117a8d-3aef-46ea-8a5b-0f4088b58f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613316583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3613316583
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1594286534
Short name T142
Test name
Test status
Simulation time 1240943190 ps
CPU time 12.77 seconds
Started Jun 04 01:40:26 PM PDT 24
Finished Jun 04 01:40:41 PM PDT 24
Peak memory 211364 kb
Host smart-33218085-3c15-4132-87c2-b53bbd1e8b6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1594286534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1594286534
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.4151775042
Short name T350
Test name
Test status
Simulation time 11643587798 ps
CPU time 46.92 seconds
Started Jun 04 01:40:26 PM PDT 24
Finished Jun 04 01:41:16 PM PDT 24
Peak memory 215260 kb
Host smart-e805936b-7b03-455b-9de0-59993dbdfd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151775042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.4151775042
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.802239492
Short name T75
Test name
Test status
Simulation time 24724564953 ps
CPU time 141.58 seconds
Started Jun 04 01:40:26 PM PDT 24
Finished Jun 04 01:42:50 PM PDT 24
Peak memory 220920 kb
Host smart-e804b56b-1f95-4529-8672-81bd9dbbdbf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802239492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.802239492
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1880729141
Short name T60
Test name
Test status
Simulation time 1310519770 ps
CPU time 13.51 seconds
Started Jun 04 01:40:26 PM PDT 24
Finished Jun 04 01:40:42 PM PDT 24
Peak memory 211348 kb
Host smart-b03b9886-0e6a-460a-8d3b-e30ed65def46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880729141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1880729141
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.739679098
Short name T260
Test name
Test status
Simulation time 94126273105 ps
CPU time 248.28 seconds
Started Jun 04 01:40:26 PM PDT 24
Finished Jun 04 01:44:37 PM PDT 24
Peak memory 236744 kb
Host smart-7fd8e353-9c0d-4930-b24d-694c6dde7d7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739679098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.739679098
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4056158363
Short name T173
Test name
Test status
Simulation time 20421436837 ps
CPU time 48.94 seconds
Started Jun 04 01:40:28 PM PDT 24
Finished Jun 04 01:41:19 PM PDT 24
Peak memory 217692 kb
Host smart-f71af49f-3d15-4f84-8e9a-e65d82bd7d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056158363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4056158363
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1132388458
Short name T175
Test name
Test status
Simulation time 19742707085 ps
CPU time 22.63 seconds
Started Jun 04 01:40:30 PM PDT 24
Finished Jun 04 01:40:55 PM PDT 24
Peak memory 211640 kb
Host smart-559c8f77-52fe-4f9e-82a5-58711b1371bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1132388458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1132388458
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3377445730
Short name T257
Test name
Test status
Simulation time 9597704397 ps
CPU time 34.36 seconds
Started Jun 04 01:40:25 PM PDT 24
Finished Jun 04 01:41:01 PM PDT 24
Peak memory 217232 kb
Host smart-f1730b90-89d3-4e38-bee6-25c54e4da437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377445730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3377445730
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2701079590
Short name T159
Test name
Test status
Simulation time 47758256725 ps
CPU time 113.95 seconds
Started Jun 04 01:40:29 PM PDT 24
Finished Jun 04 01:42:26 PM PDT 24
Peak memory 220464 kb
Host smart-8f9ec97d-2ff2-4bf0-b2e4-680857b7c402
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701079590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2701079590
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1307001790
Short name T203
Test name
Test status
Simulation time 3367059105 ps
CPU time 20.02 seconds
Started Jun 04 01:40:30 PM PDT 24
Finished Jun 04 01:40:53 PM PDT 24
Peak memory 211372 kb
Host smart-3c617bd8-d95b-454c-a339-a57ba9b765e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307001790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1307001790
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3559745193
Short name T20
Test name
Test status
Simulation time 181112632810 ps
CPU time 519.84 seconds
Started Jun 04 01:40:25 PM PDT 24
Finished Jun 04 01:49:06 PM PDT 24
Peak memory 241028 kb
Host smart-f2222f04-3186-4678-9bb5-40645b52e720
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559745193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3559745193
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2884015744
Short name T276
Test name
Test status
Simulation time 2065101909 ps
CPU time 22.46 seconds
Started Jun 04 01:40:28 PM PDT 24
Finished Jun 04 01:40:53 PM PDT 24
Peak memory 212828 kb
Host smart-e6ef613d-4cd2-4c6a-95d0-77bdc4633d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884015744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2884015744
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2518573843
Short name T124
Test name
Test status
Simulation time 187071023 ps
CPU time 10.76 seconds
Started Jun 04 01:40:28 PM PDT 24
Finished Jun 04 01:40:41 PM PDT 24
Peak memory 212644 kb
Host smart-cc64d293-7e8a-4bee-91cb-d7c10dd5142e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2518573843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2518573843
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.4060484837
Short name T38
Test name
Test status
Simulation time 1647420347 ps
CPU time 19.41 seconds
Started Jun 04 01:40:30 PM PDT 24
Finished Jun 04 01:40:51 PM PDT 24
Peak memory 217336 kb
Host smart-433cadd4-acbc-4aa4-b4b6-ca74b2e6fbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060484837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.4060484837
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2926244838
Short name T149
Test name
Test status
Simulation time 12074085818 ps
CPU time 63.7 seconds
Started Jun 04 01:40:30 PM PDT 24
Finished Jun 04 01:41:36 PM PDT 24
Peak memory 219860 kb
Host smart-57979691-fda9-4def-9a73-b2f44a3b5fcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926244838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2926244838
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2594345286
Short name T334
Test name
Test status
Simulation time 14596853726 ps
CPU time 30.07 seconds
Started Jun 04 01:40:25 PM PDT 24
Finished Jun 04 01:40:58 PM PDT 24
Peak memory 212240 kb
Host smart-a38c36f0-f0f6-4652-8fdb-0a4be26246a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594345286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2594345286
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2132626871
Short name T154
Test name
Test status
Simulation time 1287224284 ps
CPU time 122.84 seconds
Started Jun 04 01:40:25 PM PDT 24
Finished Jun 04 01:42:29 PM PDT 24
Peak memory 239928 kb
Host smart-6cff8ca8-7fb4-43b3-a48c-720d620be2c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132626871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2132626871
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1630449646
Short name T261
Test name
Test status
Simulation time 10741823527 ps
CPU time 52.11 seconds
Started Jun 04 01:40:25 PM PDT 24
Finished Jun 04 01:41:20 PM PDT 24
Peak memory 215196 kb
Host smart-d11704e7-2c6d-4af1-82e4-6db6cdc70106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630449646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1630449646
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.570206279
Short name T270
Test name
Test status
Simulation time 3364551671 ps
CPU time 30.99 seconds
Started Jun 04 01:40:25 PM PDT 24
Finished Jun 04 01:40:59 PM PDT 24
Peak memory 211336 kb
Host smart-d6070d0a-f8f4-4fcf-bbd5-8e88d7fb61cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=570206279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.570206279
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.801438684
Short name T170
Test name
Test status
Simulation time 5042262221 ps
CPU time 48.72 seconds
Started Jun 04 01:40:24 PM PDT 24
Finished Jun 04 01:41:15 PM PDT 24
Peak memory 215108 kb
Host smart-34ef2910-6e18-4938-bc3b-e6e8feb785fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801438684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.801438684
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2603471350
Short name T72
Test name
Test status
Simulation time 37785431410 ps
CPU time 122.63 seconds
Started Jun 04 01:40:29 PM PDT 24
Finished Jun 04 01:42:34 PM PDT 24
Peak memory 219400 kb
Host smart-191c949c-8d19-494b-a702-b52585c57d08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603471350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2603471350
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2556931569
Short name T16
Test name
Test status
Simulation time 27077349621 ps
CPU time 8147.71 seconds
Started Jun 04 01:40:26 PM PDT 24
Finished Jun 04 03:56:17 PM PDT 24
Peak memory 235928 kb
Host smart-8a196795-b6e1-463d-9e4f-b74b400a51bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556931569 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.2556931569
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1418542159
Short name T296
Test name
Test status
Simulation time 9554109253 ps
CPU time 23.49 seconds
Started Jun 04 01:40:28 PM PDT 24
Finished Jun 04 01:40:53 PM PDT 24
Peak memory 211484 kb
Host smart-edfc432f-a887-4a7a-a20d-871d73a8f7b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418542159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1418542159
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.907009669
Short name T352
Test name
Test status
Simulation time 137152231944 ps
CPU time 540.94 seconds
Started Jun 04 01:40:24 PM PDT 24
Finished Jun 04 01:49:27 PM PDT 24
Peak memory 229484 kb
Host smart-5ad4e32e-8a92-403b-93ef-f7e7e02cfd35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907009669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.907009669
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1093048095
Short name T155
Test name
Test status
Simulation time 28470437821 ps
CPU time 60.6 seconds
Started Jun 04 01:40:27 PM PDT 24
Finished Jun 04 01:41:30 PM PDT 24
Peak memory 215104 kb
Host smart-05ac760f-3d52-44e3-96c4-b8909fedbc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093048095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1093048095
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3862183069
Short name T189
Test name
Test status
Simulation time 181043426 ps
CPU time 10.28 seconds
Started Jun 04 01:40:29 PM PDT 24
Finished Jun 04 01:40:41 PM PDT 24
Peak memory 212268 kb
Host smart-cb2b5fce-a7ca-483b-849f-313d22e2a19a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3862183069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3862183069
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2651620854
Short name T202
Test name
Test status
Simulation time 345711442 ps
CPU time 20.24 seconds
Started Jun 04 01:40:33 PM PDT 24
Finished Jun 04 01:40:54 PM PDT 24
Peak memory 216896 kb
Host smart-7ad27883-d0a2-4340-b262-79ade2037d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651620854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2651620854
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3500297596
Short name T281
Test name
Test status
Simulation time 2785706691 ps
CPU time 68.51 seconds
Started Jun 04 01:40:24 PM PDT 24
Finished Jun 04 01:41:33 PM PDT 24
Peak memory 219272 kb
Host smart-d7ec48fb-d6ea-4fb7-aa07-5a760c4e7f87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500297596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3500297596
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2981928694
Short name T44
Test name
Test status
Simulation time 781024717603 ps
CPU time 2464.79 seconds
Started Jun 04 01:40:27 PM PDT 24
Finished Jun 04 02:21:34 PM PDT 24
Peak memory 249648 kb
Host smart-8f540faa-6494-43ae-9898-cc9d4241d8ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981928694 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.2981928694
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3957591770
Short name T235
Test name
Test status
Simulation time 660396299 ps
CPU time 8.63 seconds
Started Jun 04 01:40:26 PM PDT 24
Finished Jun 04 01:40:37 PM PDT 24
Peak memory 211360 kb
Host smart-2e24f3c4-94b3-41b7-80cd-fa8898e82411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957591770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3957591770
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.4266848035
Short name T293
Test name
Test status
Simulation time 47762030586 ps
CPU time 776.61 seconds
Started Jun 04 01:40:27 PM PDT 24
Finished Jun 04 01:53:25 PM PDT 24
Peak memory 235036 kb
Host smart-848420e5-ec9c-4da8-839b-c89c58948c34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266848035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.4266848035
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1386934347
Short name T335
Test name
Test status
Simulation time 31846269150 ps
CPU time 55.1 seconds
Started Jun 04 01:40:25 PM PDT 24
Finished Jun 04 01:41:22 PM PDT 24
Peak memory 215128 kb
Host smart-5e8ddbb2-1a9b-46df-9a9a-1dd08bee1b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386934347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1386934347
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.282112556
Short name T122
Test name
Test status
Simulation time 2163372629 ps
CPU time 22.25 seconds
Started Jun 04 01:40:31 PM PDT 24
Finished Jun 04 01:40:55 PM PDT 24
Peak memory 212540 kb
Host smart-c0a95cd5-74f1-425a-ba65-57b179420f72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=282112556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.282112556
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2569746086
Short name T51
Test name
Test status
Simulation time 6887493915 ps
CPU time 40.78 seconds
Started Jun 04 01:40:25 PM PDT 24
Finished Jun 04 01:41:08 PM PDT 24
Peak memory 217200 kb
Host smart-864c56ab-5190-4036-a58a-2bab9cdf6b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569746086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2569746086
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2882219805
Short name T218
Test name
Test status
Simulation time 11072130503 ps
CPU time 28.23 seconds
Started Jun 04 01:40:28 PM PDT 24
Finished Jun 04 01:40:59 PM PDT 24
Peak memory 214172 kb
Host smart-30732d08-ab81-4f1b-a23d-d3fed30d3196
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882219805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2882219805
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1431487698
Short name T172
Test name
Test status
Simulation time 14969080222 ps
CPU time 24.9 seconds
Started Jun 04 01:40:30 PM PDT 24
Finished Jun 04 01:40:58 PM PDT 24
Peak memory 211472 kb
Host smart-6d403c30-6b1e-42a3-af62-6d06e09ba221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431487698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1431487698
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.696093803
Short name T312
Test name
Test status
Simulation time 95432587337 ps
CPU time 950.71 seconds
Started Jun 04 01:40:31 PM PDT 24
Finished Jun 04 01:56:24 PM PDT 24
Peak memory 229140 kb
Host smart-7944bdcb-9c2c-4a72-a68a-ba8150a31ff8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696093803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.696093803
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2551431843
Short name T227
Test name
Test status
Simulation time 1151260477 ps
CPU time 27.38 seconds
Started Jun 04 01:40:30 PM PDT 24
Finished Jun 04 01:40:59 PM PDT 24
Peak memory 214952 kb
Host smart-f0a6ee0a-ea6d-4dc3-8570-8ab661e179ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551431843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2551431843
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.429701545
Short name T238
Test name
Test status
Simulation time 65537489992 ps
CPU time 29.75 seconds
Started Jun 04 01:40:28 PM PDT 24
Finished Jun 04 01:41:01 PM PDT 24
Peak memory 212924 kb
Host smart-4a16a357-67b9-4a3e-9119-368cec0163a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=429701545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.429701545
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3800761667
Short name T184
Test name
Test status
Simulation time 30776579641 ps
CPU time 64.69 seconds
Started Jun 04 01:40:25 PM PDT 24
Finished Jun 04 01:41:32 PM PDT 24
Peak memory 217112 kb
Host smart-3cfc21ed-da44-4592-98e8-cb4eddadc99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800761667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3800761667
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3228076915
Short name T308
Test name
Test status
Simulation time 33003110253 ps
CPU time 92.31 seconds
Started Jun 04 01:40:25 PM PDT 24
Finished Jun 04 01:42:00 PM PDT 24
Peak memory 219428 kb
Host smart-5ffb4d1e-5d89-4149-b102-461cab1eb2fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228076915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3228076915
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3516331977
Short name T349
Test name
Test status
Simulation time 14260571127 ps
CPU time 19.04 seconds
Started Jun 04 01:40:28 PM PDT 24
Finished Jun 04 01:40:49 PM PDT 24
Peak memory 211468 kb
Host smart-637915f1-6c10-46fe-9ffc-b5626c3d6bf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516331977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3516331977
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.285033261
Short name T242
Test name
Test status
Simulation time 130560290154 ps
CPU time 346.81 seconds
Started Jun 04 01:40:28 PM PDT 24
Finished Jun 04 01:46:17 PM PDT 24
Peak memory 237808 kb
Host smart-978cc709-9e42-44ed-9465-26c2bf9820fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285033261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.285033261
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.379345838
Short name T219
Test name
Test status
Simulation time 5217737568 ps
CPU time 52.67 seconds
Started Jun 04 01:40:27 PM PDT 24
Finished Jun 04 01:41:22 PM PDT 24
Peak memory 215092 kb
Host smart-6cb6d7a2-4faf-49eb-a2e2-df72fe7c4877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379345838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.379345838
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3971881006
Short name T251
Test name
Test status
Simulation time 3711475794 ps
CPU time 21.2 seconds
Started Jun 04 01:40:28 PM PDT 24
Finished Jun 04 01:40:51 PM PDT 24
Peak memory 212440 kb
Host smart-5428d8ea-1e1c-4d91-a276-9ee89e129f49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3971881006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3971881006
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.928046439
Short name T195
Test name
Test status
Simulation time 16017493106 ps
CPU time 49.45 seconds
Started Jun 04 01:40:26 PM PDT 24
Finished Jun 04 01:41:18 PM PDT 24
Peak memory 218268 kb
Host smart-28accbfc-bf74-44ad-9531-cb806ca8eb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928046439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.928046439
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.966005561
Short name T192
Test name
Test status
Simulation time 1269720669 ps
CPU time 19.8 seconds
Started Jun 04 01:40:33 PM PDT 24
Finished Jun 04 01:40:54 PM PDT 24
Peak memory 213508 kb
Host smart-2e11144c-5fd4-409d-bc7c-55fb119551b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966005561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.966005561
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3406183290
Short name T311
Test name
Test status
Simulation time 175998805 ps
CPU time 8.05 seconds
Started Jun 04 01:40:34 PM PDT 24
Finished Jun 04 01:40:44 PM PDT 24
Peak memory 211360 kb
Host smart-d5e72f60-fe02-4814-98e9-21271c3e6776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406183290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3406183290
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.4220361794
Short name T17
Test name
Test status
Simulation time 1572098699 ps
CPU time 19.49 seconds
Started Jun 04 01:40:33 PM PDT 24
Finished Jun 04 01:40:54 PM PDT 24
Peak memory 214932 kb
Host smart-f6aacd9f-8b38-4757-856c-ad8b5d021158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220361794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.4220361794
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1423042321
Short name T129
Test name
Test status
Simulation time 6537456141 ps
CPU time 28.69 seconds
Started Jun 04 01:40:44 PM PDT 24
Finished Jun 04 01:41:14 PM PDT 24
Peak memory 212640 kb
Host smart-7442ff99-0510-460b-b59a-cad7fcda008f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1423042321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1423042321
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1420711471
Short name T356
Test name
Test status
Simulation time 76476140834 ps
CPU time 61.57 seconds
Started Jun 04 01:40:35 PM PDT 24
Finished Jun 04 01:41:38 PM PDT 24
Peak memory 217480 kb
Host smart-28986536-f7a8-4811-a92d-8e057e4e95e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420711471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1420711471
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1961591887
Short name T128
Test name
Test status
Simulation time 63284494025 ps
CPU time 139 seconds
Started Jun 04 01:40:35 PM PDT 24
Finished Jun 04 01:42:56 PM PDT 24
Peak memory 227588 kb
Host smart-70036aae-1a2a-4fa9-b9aa-dc4155f9e98d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961591887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1961591887
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1499865869
Short name T62
Test name
Test status
Simulation time 1782753074 ps
CPU time 19.41 seconds
Started Jun 04 01:40:33 PM PDT 24
Finished Jun 04 01:40:53 PM PDT 24
Peak memory 211312 kb
Host smart-a2f1fa1b-17b8-4b20-a28f-91d6f735da51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499865869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1499865869
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1871590669
Short name T258
Test name
Test status
Simulation time 40035190260 ps
CPU time 227.68 seconds
Started Jun 04 01:40:34 PM PDT 24
Finished Jun 04 01:44:23 PM PDT 24
Peak memory 227728 kb
Host smart-a2e4d5f6-936b-4f12-9e86-64eec4d1cffd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871590669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1871590669
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1627291553
Short name T23
Test name
Test status
Simulation time 14040326521 ps
CPU time 45.82 seconds
Started Jun 04 01:40:35 PM PDT 24
Finished Jun 04 01:41:22 PM PDT 24
Peak memory 215096 kb
Host smart-b35f86cc-9bce-4611-9a53-fb1a8f4cb46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627291553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1627291553
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3918700752
Short name T185
Test name
Test status
Simulation time 697078810 ps
CPU time 10.58 seconds
Started Jun 04 01:40:34 PM PDT 24
Finished Jun 04 01:40:46 PM PDT 24
Peak memory 212616 kb
Host smart-11fafb14-ccad-4f56-a9ac-15f0cf9e100b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3918700752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3918700752
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3610524091
Short name T210
Test name
Test status
Simulation time 1556518783 ps
CPU time 20.06 seconds
Started Jun 04 01:40:38 PM PDT 24
Finished Jun 04 01:40:58 PM PDT 24
Peak memory 216212 kb
Host smart-505d0dc5-8c64-450f-b050-3d43eae8f14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610524091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3610524091
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.705937732
Short name T77
Test name
Test status
Simulation time 1423363267 ps
CPU time 13.94 seconds
Started Jun 04 01:40:33 PM PDT 24
Finished Jun 04 01:40:48 PM PDT 24
Peak memory 213772 kb
Host smart-35adc202-8be6-4441-978b-42793407d8bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705937732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.705937732
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3275615120
Short name T148
Test name
Test status
Simulation time 21193603316 ps
CPU time 30.47 seconds
Started Jun 04 01:39:59 PM PDT 24
Finished Jun 04 01:40:31 PM PDT 24
Peak memory 212148 kb
Host smart-7c0ac57b-2ee0-46ec-ac1f-55772c00101e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275615120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3275615120
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2239104290
Short name T340
Test name
Test status
Simulation time 13151961671 ps
CPU time 239.06 seconds
Started Jun 04 01:39:54 PM PDT 24
Finished Jun 04 01:43:54 PM PDT 24
Peak memory 216020 kb
Host smart-bba1a67c-d66d-4d40-a2d2-938d2bd680fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239104290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2239104290
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2093816419
Short name T249
Test name
Test status
Simulation time 13717882043 ps
CPU time 54.37 seconds
Started Jun 04 01:39:54 PM PDT 24
Finished Jun 04 01:40:50 PM PDT 24
Peak memory 215524 kb
Host smart-e806def3-b016-4fd1-b399-6992412c40aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093816419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2093816419
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4039746006
Short name T307
Test name
Test status
Simulation time 2389438498 ps
CPU time 19.26 seconds
Started Jun 04 01:39:57 PM PDT 24
Finished Jun 04 01:40:18 PM PDT 24
Peak memory 212772 kb
Host smart-e7fea53b-b489-40bd-8dfd-d326c6302de0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4039746006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.4039746006
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2573013698
Short name T28
Test name
Test status
Simulation time 2042395812 ps
CPU time 227.46 seconds
Started Jun 04 01:39:56 PM PDT 24
Finished Jun 04 01:43:46 PM PDT 24
Peak memory 238024 kb
Host smart-ebc46497-e1ff-4453-9b5a-93afab851eb9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573013698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2573013698
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.563335678
Short name T275
Test name
Test status
Simulation time 728327925 ps
CPU time 20.02 seconds
Started Jun 04 01:39:57 PM PDT 24
Finished Jun 04 01:40:19 PM PDT 24
Peak memory 215848 kb
Host smart-9f68d1d7-96b8-4efc-9b31-5eb19df7dd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563335678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.563335678
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.501264721
Short name T206
Test name
Test status
Simulation time 53354915190 ps
CPU time 139.53 seconds
Started Jun 04 01:39:56 PM PDT 24
Finished Jun 04 01:42:17 PM PDT 24
Peak memory 227912 kb
Host smart-56ec9ab1-4014-4de8-900d-90c06089ff5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501264721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.501264721
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2193607214
Short name T146
Test name
Test status
Simulation time 3281025806 ps
CPU time 13.47 seconds
Started Jun 04 01:40:40 PM PDT 24
Finished Jun 04 01:40:55 PM PDT 24
Peak memory 211396 kb
Host smart-dfeb1f73-8abf-415b-af5c-b9d8c3e0c84b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193607214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2193607214
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.689560861
Short name T333
Test name
Test status
Simulation time 69875146761 ps
CPU time 651.35 seconds
Started Jun 04 01:40:33 PM PDT 24
Finished Jun 04 01:51:26 PM PDT 24
Peak memory 228648 kb
Host smart-491fd2bf-b0b4-49d4-8c12-80d0cf260aef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689560861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.689560861
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1035482655
Short name T162
Test name
Test status
Simulation time 4594467500 ps
CPU time 48.13 seconds
Started Jun 04 01:40:37 PM PDT 24
Finished Jun 04 01:41:26 PM PDT 24
Peak memory 215204 kb
Host smart-286a751b-0253-4816-b2af-dc4fdde42c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035482655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1035482655
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1289910163
Short name T325
Test name
Test status
Simulation time 3318449251 ps
CPU time 16.27 seconds
Started Jun 04 01:40:33 PM PDT 24
Finished Jun 04 01:40:50 PM PDT 24
Peak memory 211612 kb
Host smart-d2f80fc3-6a2e-4d3e-ae41-124e208a9fcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1289910163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1289910163
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3972143307
Short name T347
Test name
Test status
Simulation time 355205678 ps
CPU time 20.09 seconds
Started Jun 04 01:40:40 PM PDT 24
Finished Jun 04 01:41:01 PM PDT 24
Peak memory 217600 kb
Host smart-7aa5b76b-4634-4d5f-8a8c-be7de009ec53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972143307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3972143307
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2833674440
Short name T73
Test name
Test status
Simulation time 49413664054 ps
CPU time 62.72 seconds
Started Jun 04 01:40:45 PM PDT 24
Finished Jun 04 01:41:49 PM PDT 24
Peak memory 218640 kb
Host smart-e5ab41c0-9bd0-4304-98ef-0389d25bdee1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833674440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2833674440
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1426968366
Short name T285
Test name
Test status
Simulation time 16471925856 ps
CPU time 33.22 seconds
Started Jun 04 01:40:33 PM PDT 24
Finished Jun 04 01:41:07 PM PDT 24
Peak memory 212168 kb
Host smart-db6a436b-54b9-4d6d-805e-430807bd85e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426968366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1426968366
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2378052400
Short name T125
Test name
Test status
Simulation time 25675490783 ps
CPU time 325.12 seconds
Started Jun 04 01:40:35 PM PDT 24
Finished Jun 04 01:46:02 PM PDT 24
Peak memory 216836 kb
Host smart-4e9d3c11-c4bc-4c9b-a9fa-dced46c8f620
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378052400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2378052400
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3230044824
Short name T233
Test name
Test status
Simulation time 4093563914 ps
CPU time 33.01 seconds
Started Jun 04 01:40:33 PM PDT 24
Finished Jun 04 01:41:08 PM PDT 24
Peak memory 214772 kb
Host smart-d1144da6-4751-4e8d-826d-3a491f3866e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230044824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3230044824
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1907558251
Short name T102
Test name
Test status
Simulation time 9232990958 ps
CPU time 23.36 seconds
Started Jun 04 01:40:38 PM PDT 24
Finished Jun 04 01:41:02 PM PDT 24
Peak memory 211448 kb
Host smart-796d42b8-c670-45e8-9666-05ae81b17dca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1907558251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1907558251
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1432291331
Short name T315
Test name
Test status
Simulation time 5249372734 ps
CPU time 48.83 seconds
Started Jun 04 01:40:36 PM PDT 24
Finished Jun 04 01:41:26 PM PDT 24
Peak memory 215196 kb
Host smart-960e3ab2-ec6a-4651-89a2-10079cec8f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432291331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1432291331
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3635430344
Short name T327
Test name
Test status
Simulation time 8501957847 ps
CPU time 34.48 seconds
Started Jun 04 01:40:37 PM PDT 24
Finished Jun 04 01:41:13 PM PDT 24
Peak memory 213108 kb
Host smart-5eab29f1-a59f-4bec-935b-2d4f8066c0f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635430344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3635430344
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.791408230
Short name T48
Test name
Test status
Simulation time 100842570147 ps
CPU time 1742.56 seconds
Started Jun 04 01:40:34 PM PDT 24
Finished Jun 04 02:09:39 PM PDT 24
Peak memory 244660 kb
Host smart-f249d415-2f5f-4d76-9e49-f5eab1dd920e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791408230 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.791408230
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.896369353
Short name T164
Test name
Test status
Simulation time 167505586 ps
CPU time 8.21 seconds
Started Jun 04 01:40:44 PM PDT 24
Finished Jun 04 01:40:53 PM PDT 24
Peak memory 211316 kb
Host smart-96d4b5be-e74e-48a6-a354-37ddc7bc48e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896369353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.896369353
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2097633629
Short name T205
Test name
Test status
Simulation time 8040930406 ps
CPU time 224.96 seconds
Started Jun 04 01:40:34 PM PDT 24
Finished Jun 04 01:44:20 PM PDT 24
Peak memory 225804 kb
Host smart-0697e1b6-84e6-4d92-84eb-507ae1aeb9a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097633629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2097633629
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3281237671
Short name T348
Test name
Test status
Simulation time 1531736569 ps
CPU time 29.62 seconds
Started Jun 04 01:40:35 PM PDT 24
Finished Jun 04 01:41:06 PM PDT 24
Peak memory 214788 kb
Host smart-f6321031-8814-4389-b9d5-02b209026cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281237671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3281237671
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3661872973
Short name T50
Test name
Test status
Simulation time 611021400 ps
CPU time 14.46 seconds
Started Jun 04 01:40:37 PM PDT 24
Finished Jun 04 01:40:52 PM PDT 24
Peak memory 212588 kb
Host smart-451d7fad-66b1-4227-b6c6-9afac206053c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3661872973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3661872973
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2190083186
Short name T318
Test name
Test status
Simulation time 4112198303 ps
CPU time 53.56 seconds
Started Jun 04 01:40:37 PM PDT 24
Finished Jun 04 01:41:31 PM PDT 24
Peak memory 217604 kb
Host smart-601171e5-6d07-4c05-b502-f760a9fa130a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190083186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2190083186
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2640835586
Short name T11
Test name
Test status
Simulation time 338567869 ps
CPU time 14.93 seconds
Started Jun 04 01:40:34 PM PDT 24
Finished Jun 04 01:40:51 PM PDT 24
Peak memory 213384 kb
Host smart-585be704-33d7-4095-85a2-501efd645951
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640835586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2640835586
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.523789172
Short name T346
Test name
Test status
Simulation time 109235522493 ps
CPU time 1044.68 seconds
Started Jun 04 01:40:35 PM PDT 24
Finished Jun 04 01:58:01 PM PDT 24
Peak memory 237032 kb
Host smart-7fb77236-f6b8-45a3-a4d0-517c38bf2d2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523789172 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.523789172
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2933575990
Short name T253
Test name
Test status
Simulation time 5628889396 ps
CPU time 25.41 seconds
Started Jun 04 01:40:34 PM PDT 24
Finished Jun 04 01:41:01 PM PDT 24
Peak memory 212288 kb
Host smart-823e8a18-1290-4ee9-9205-4e9dedec931b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933575990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2933575990
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3115796086
Short name T332
Test name
Test status
Simulation time 77681926125 ps
CPU time 912.08 seconds
Started Jun 04 01:40:40 PM PDT 24
Finished Jun 04 01:55:53 PM PDT 24
Peak memory 229972 kb
Host smart-1d4c8084-60fb-4b17-af17-cc4e472de3dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115796086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3115796086
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.644454931
Short name T283
Test name
Test status
Simulation time 26702652341 ps
CPU time 61.62 seconds
Started Jun 04 01:40:44 PM PDT 24
Finished Jun 04 01:41:47 PM PDT 24
Peak memory 215184 kb
Host smart-a87c3513-a9fe-4bb1-a805-2c5f798fc4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644454931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.644454931
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2454011966
Short name T116
Test name
Test status
Simulation time 2895147767 ps
CPU time 27.52 seconds
Started Jun 04 01:40:36 PM PDT 24
Finished Jun 04 01:41:05 PM PDT 24
Peak memory 211388 kb
Host smart-dc54b305-517b-48dc-9e13-eadaf5b79544
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2454011966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2454011966
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3581399481
Short name T152
Test name
Test status
Simulation time 14477278100 ps
CPU time 58.92 seconds
Started Jun 04 01:40:35 PM PDT 24
Finished Jun 04 01:41:35 PM PDT 24
Peak memory 218088 kb
Host smart-434f14f8-29aa-4c70-b47f-56326620e53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581399481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3581399481
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.4256483452
Short name T130
Test name
Test status
Simulation time 6786905415 ps
CPU time 37.71 seconds
Started Jun 04 01:40:34 PM PDT 24
Finished Jun 04 01:41:13 PM PDT 24
Peak memory 219324 kb
Host smart-6f0cb3c7-f23d-4110-aee1-262228c3f0a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256483452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.4256483452
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3123032790
Short name T228
Test name
Test status
Simulation time 345979797 ps
CPU time 8.39 seconds
Started Jun 04 01:40:50 PM PDT 24
Finished Jun 04 01:40:59 PM PDT 24
Peak memory 211276 kb
Host smart-d06ed0d2-fb0d-4af9-838a-321390acb743
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123032790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3123032790
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3396540177
Short name T141
Test name
Test status
Simulation time 18203046834 ps
CPU time 270.67 seconds
Started Jun 04 01:40:43 PM PDT 24
Finished Jun 04 01:45:16 PM PDT 24
Peak memory 237040 kb
Host smart-a3f12d66-400a-46ee-b669-350c8c8feb71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396540177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3396540177
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3664773041
Short name T337
Test name
Test status
Simulation time 502111526 ps
CPU time 22.3 seconds
Started Jun 04 01:40:42 PM PDT 24
Finished Jun 04 01:41:06 PM PDT 24
Peak memory 212812 kb
Host smart-ec9824a4-7553-42f6-858b-90279edebf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664773041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3664773041
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1446428423
Short name T158
Test name
Test status
Simulation time 11564280275 ps
CPU time 26.64 seconds
Started Jun 04 01:40:42 PM PDT 24
Finished Jun 04 01:41:09 PM PDT 24
Peak memory 211864 kb
Host smart-1eda13e1-d3e6-4b8d-a595-6c0b1aa3d175
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1446428423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1446428423
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.4262001963
Short name T243
Test name
Test status
Simulation time 5473100196 ps
CPU time 36.5 seconds
Started Jun 04 01:40:46 PM PDT 24
Finished Jun 04 01:41:23 PM PDT 24
Peak memory 217468 kb
Host smart-b7e5dc87-3622-4073-8d6a-359e210052a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262001963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.4262001963
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1439919204
Short name T46
Test name
Test status
Simulation time 62027964053 ps
CPU time 2301.6 seconds
Started Jun 04 01:40:43 PM PDT 24
Finished Jun 04 02:19:06 PM PDT 24
Peak memory 240572 kb
Host smart-777fd3ac-34c4-4405-9eb7-2cabfc0d06cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439919204 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.1439919204
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.730915557
Short name T30
Test name
Test status
Simulation time 613131254 ps
CPU time 8.24 seconds
Started Jun 04 01:40:43 PM PDT 24
Finished Jun 04 01:40:52 PM PDT 24
Peak memory 211364 kb
Host smart-53db9e89-8601-4561-9ee6-41af9592862b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730915557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.730915557
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.269293418
Short name T127
Test name
Test status
Simulation time 74755319458 ps
CPU time 645.48 seconds
Started Jun 04 01:40:44 PM PDT 24
Finished Jun 04 01:51:31 PM PDT 24
Peak memory 217200 kb
Host smart-791618cb-2fe3-474c-a80d-74d03db0621d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269293418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.269293418
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1669220011
Short name T355
Test name
Test status
Simulation time 14061021275 ps
CPU time 60.12 seconds
Started Jun 04 01:40:45 PM PDT 24
Finished Jun 04 01:41:46 PM PDT 24
Peak memory 215216 kb
Host smart-96aad912-6eb0-4069-bc43-00c1d57cd567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669220011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1669220011
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3982006165
Short name T254
Test name
Test status
Simulation time 16213335926 ps
CPU time 35.82 seconds
Started Jun 04 01:40:44 PM PDT 24
Finished Jun 04 01:41:21 PM PDT 24
Peak memory 211796 kb
Host smart-c480d6ba-6743-44f6-9db8-f880a2dafb3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3982006165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3982006165
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3177206016
Short name T145
Test name
Test status
Simulation time 3333072259 ps
CPU time 25.97 seconds
Started Jun 04 01:40:42 PM PDT 24
Finished Jun 04 01:41:09 PM PDT 24
Peak memory 217220 kb
Host smart-cb264b0f-84fc-4670-8961-b6a1521587bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177206016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3177206016
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2408549876
Short name T204
Test name
Test status
Simulation time 867821085 ps
CPU time 8.27 seconds
Started Jun 04 01:40:43 PM PDT 24
Finished Jun 04 01:40:52 PM PDT 24
Peak memory 211332 kb
Host smart-7c78ea25-b72e-4e29-bf55-aa1226a5a09e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408549876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2408549876
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.599308099
Short name T277
Test name
Test status
Simulation time 122673640065 ps
CPU time 673.69 seconds
Started Jun 04 01:40:43 PM PDT 24
Finished Jun 04 01:51:58 PM PDT 24
Peak memory 236536 kb
Host smart-e87a5516-352f-4aac-88ea-b80e1295a421
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599308099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.599308099
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1641742624
Short name T314
Test name
Test status
Simulation time 6662240019 ps
CPU time 57.36 seconds
Started Jun 04 01:40:43 PM PDT 24
Finished Jun 04 01:41:42 PM PDT 24
Peak memory 215176 kb
Host smart-fc925db0-497d-49f5-be6a-d548abbb3d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641742624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1641742624
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3102655436
Short name T136
Test name
Test status
Simulation time 2842323089 ps
CPU time 24.07 seconds
Started Jun 04 01:40:43 PM PDT 24
Finished Jun 04 01:41:09 PM PDT 24
Peak memory 211380 kb
Host smart-9c000485-5e83-4fde-a087-b321ca954651
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3102655436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3102655436
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2532567259
Short name T143
Test name
Test status
Simulation time 1938036136 ps
CPU time 32.61 seconds
Started Jun 04 01:40:45 PM PDT 24
Finished Jun 04 01:41:18 PM PDT 24
Peak memory 216652 kb
Host smart-f6a3cd3f-c715-4b03-b878-07e72c2a5ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532567259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2532567259
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1104092240
Short name T274
Test name
Test status
Simulation time 38132184796 ps
CPU time 96.29 seconds
Started Jun 04 01:40:44 PM PDT 24
Finished Jun 04 01:42:22 PM PDT 24
Peak memory 218396 kb
Host smart-915618c3-bc3b-4b33-a566-274151250c3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104092240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1104092240
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2192444542
Short name T295
Test name
Test status
Simulation time 4114254509 ps
CPU time 20.97 seconds
Started Jun 04 01:40:55 PM PDT 24
Finished Jun 04 01:41:16 PM PDT 24
Peak memory 211416 kb
Host smart-78b5e630-cf0c-4593-b51e-6eb5b5046270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192444542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2192444542
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.538007981
Short name T12
Test name
Test status
Simulation time 2469177005 ps
CPU time 180.36 seconds
Started Jun 04 01:40:53 PM PDT 24
Finished Jun 04 01:43:54 PM PDT 24
Peak memory 240180 kb
Host smart-73759223-18c9-4dfa-9243-22e5106690ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538007981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.538007981
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.4210412335
Short name T168
Test name
Test status
Simulation time 6838129097 ps
CPU time 60.83 seconds
Started Jun 04 01:40:57 PM PDT 24
Finished Jun 04 01:41:59 PM PDT 24
Peak memory 214008 kb
Host smart-65c4998b-574e-4512-ba3c-08fc38d6bdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210412335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.4210412335
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1177235134
Short name T304
Test name
Test status
Simulation time 16953503795 ps
CPU time 34.73 seconds
Started Jun 04 01:40:54 PM PDT 24
Finished Jun 04 01:41:29 PM PDT 24
Peak memory 211400 kb
Host smart-b171be41-3328-488e-916e-9f6905f0c1fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1177235134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1177235134
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2480446063
Short name T166
Test name
Test status
Simulation time 8300391667 ps
CPU time 62.14 seconds
Started Jun 04 01:40:51 PM PDT 24
Finished Jun 04 01:41:54 PM PDT 24
Peak memory 217644 kb
Host smart-05024481-6d33-439c-8380-f2d381ed5191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480446063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2480446063
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3179811192
Short name T200
Test name
Test status
Simulation time 7218917384 ps
CPU time 65.89 seconds
Started Jun 04 01:40:51 PM PDT 24
Finished Jun 04 01:41:57 PM PDT 24
Peak memory 218620 kb
Host smart-ab73b1fe-28ad-4c15-8adc-668aa072acb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179811192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3179811192
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2614895179
Short name T15
Test name
Test status
Simulation time 120628784548 ps
CPU time 1183.02 seconds
Started Jun 04 01:40:51 PM PDT 24
Finished Jun 04 02:00:35 PM PDT 24
Peak memory 235956 kb
Host smart-e983d300-1d51-4533-be76-b6ff5b1fff80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614895179 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.2614895179
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.4063867837
Short name T147
Test name
Test status
Simulation time 11620063653 ps
CPU time 25.53 seconds
Started Jun 04 01:40:53 PM PDT 24
Finished Jun 04 01:41:20 PM PDT 24
Peak memory 211424 kb
Host smart-4579859f-4b53-48f2-aa9d-11f7271b40e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063867837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.4063867837
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2660356570
Short name T240
Test name
Test status
Simulation time 352155287218 ps
CPU time 784.29 seconds
Started Jun 04 01:40:56 PM PDT 24
Finished Jun 04 01:54:01 PM PDT 24
Peak memory 237932 kb
Host smart-5c4a9e3a-46f3-4387-8026-1f445aeb4290
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660356570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2660356570
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3964909073
Short name T24
Test name
Test status
Simulation time 9854480477 ps
CPU time 36.56 seconds
Started Jun 04 01:40:53 PM PDT 24
Finished Jun 04 01:41:30 PM PDT 24
Peak memory 215120 kb
Host smart-86e40359-6c2d-4b7b-b221-0dcee64329d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964909073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3964909073
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3524976937
Short name T120
Test name
Test status
Simulation time 3703590495 ps
CPU time 31.29 seconds
Started Jun 04 01:40:52 PM PDT 24
Finished Jun 04 01:41:24 PM PDT 24
Peak memory 211520 kb
Host smart-e8fa273f-8ac1-41df-989c-04fa89381189
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3524976937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3524976937
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.65306096
Short name T289
Test name
Test status
Simulation time 1487395538 ps
CPU time 20.04 seconds
Started Jun 04 01:40:53 PM PDT 24
Finished Jun 04 01:41:14 PM PDT 24
Peak memory 216528 kb
Host smart-ad21d7a3-14de-4318-83bd-5dba9a5ddbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65306096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.65306096
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2415703080
Short name T220
Test name
Test status
Simulation time 4622990872 ps
CPU time 51.64 seconds
Started Jun 04 01:40:50 PM PDT 24
Finished Jun 04 01:41:42 PM PDT 24
Peak memory 215272 kb
Host smart-ccfdbb67-5737-4151-be49-6504c2095b6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415703080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2415703080
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.4146803892
Short name T279
Test name
Test status
Simulation time 8536270379 ps
CPU time 32.85 seconds
Started Jun 04 01:40:52 PM PDT 24
Finished Jun 04 01:41:26 PM PDT 24
Peak memory 211440 kb
Host smart-81d1f414-fdbc-4da7-b6ba-79fcdd91f36f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146803892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.4146803892
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.92426579
Short name T36
Test name
Test status
Simulation time 62900604675 ps
CPU time 295.53 seconds
Started Jun 04 01:40:50 PM PDT 24
Finished Jun 04 01:45:46 PM PDT 24
Peak memory 218912 kb
Host smart-2ccf139e-be5c-481c-bbd4-a53ead502c7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92426579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_co
rrupt_sig_fatal_chk.92426579
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.928997443
Short name T180
Test name
Test status
Simulation time 5130809055 ps
CPU time 35.03 seconds
Started Jun 04 01:40:56 PM PDT 24
Finished Jun 04 01:41:32 PM PDT 24
Peak memory 215132 kb
Host smart-b425be32-dd09-42df-b5da-f5841533e9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928997443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.928997443
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3254897490
Short name T100
Test name
Test status
Simulation time 11890260945 ps
CPU time 28.12 seconds
Started Jun 04 01:40:52 PM PDT 24
Finished Jun 04 01:41:21 PM PDT 24
Peak memory 211872 kb
Host smart-3e36fec4-f98c-4d85-bb97-724d2158c3a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3254897490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3254897490
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.820692251
Short name T208
Test name
Test status
Simulation time 16378655000 ps
CPU time 47.16 seconds
Started Jun 04 01:40:52 PM PDT 24
Finished Jun 04 01:41:40 PM PDT 24
Peak memory 218188 kb
Host smart-51379e66-6683-4da7-91f2-d6226c7a8b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820692251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.820692251
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.588390725
Short name T151
Test name
Test status
Simulation time 75873191501 ps
CPU time 43.97 seconds
Started Jun 04 01:40:51 PM PDT 24
Finished Jun 04 01:41:36 PM PDT 24
Peak memory 218324 kb
Host smart-8ecae8d9-f891-43ea-b01f-092d1298dded
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588390725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.588390725
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2517672925
Short name T196
Test name
Test status
Simulation time 12580611216 ps
CPU time 26.8 seconds
Started Jun 04 01:39:54 PM PDT 24
Finished Jun 04 01:40:23 PM PDT 24
Peak memory 211436 kb
Host smart-b77211ba-e2ad-4c07-aa27-7d7bc327c885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517672925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2517672925
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1406836010
Short name T188
Test name
Test status
Simulation time 42822436938 ps
CPU time 520.25 seconds
Started Jun 04 01:39:58 PM PDT 24
Finished Jun 04 01:48:40 PM PDT 24
Peak memory 240064 kb
Host smart-5c096664-abb4-43d1-932d-04c43383848a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406836010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1406836010
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.534492449
Short name T207
Test name
Test status
Simulation time 8545501496 ps
CPU time 65.94 seconds
Started Jun 04 01:39:56 PM PDT 24
Finished Jun 04 01:41:03 PM PDT 24
Peak memory 215756 kb
Host smart-267e7424-8d30-4d6d-bdd1-41642ccc5d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534492449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.534492449
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2808814224
Short name T167
Test name
Test status
Simulation time 15337013545 ps
CPU time 33.99 seconds
Started Jun 04 01:39:55 PM PDT 24
Finished Jun 04 01:40:30 PM PDT 24
Peak memory 213028 kb
Host smart-be57f734-fdb2-4b31-8bf5-a3a5e262ebea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2808814224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2808814224
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2278547859
Short name T34
Test name
Test status
Simulation time 5485293539 ps
CPU time 247.11 seconds
Started Jun 04 01:39:56 PM PDT 24
Finished Jun 04 01:44:04 PM PDT 24
Peak memory 239188 kb
Host smart-ec1659e2-8a9f-46ee-9486-2bb4dfea97a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278547859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2278547859
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2648846472
Short name T153
Test name
Test status
Simulation time 14425366103 ps
CPU time 66.8 seconds
Started Jun 04 01:39:56 PM PDT 24
Finished Jun 04 01:41:05 PM PDT 24
Peak memory 217680 kb
Host smart-a29b44b8-17d3-406f-bdce-7a40c86fdfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648846472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2648846472
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1724316258
Short name T144
Test name
Test status
Simulation time 12054351753 ps
CPU time 114.39 seconds
Started Jun 04 01:39:58 PM PDT 24
Finished Jun 04 01:41:54 PM PDT 24
Peak memory 219328 kb
Host smart-5d41e63a-9561-4368-9601-9b84bc014e8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724316258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1724316258
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3316358245
Short name T292
Test name
Test status
Simulation time 2789967575 ps
CPU time 24.26 seconds
Started Jun 04 01:41:01 PM PDT 24
Finished Jun 04 01:41:27 PM PDT 24
Peak memory 211952 kb
Host smart-fd974cb4-358d-4dbd-9e2d-8ecda9feafd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316358245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3316358245
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2812711738
Short name T336
Test name
Test status
Simulation time 45294103062 ps
CPU time 380.43 seconds
Started Jun 04 01:41:00 PM PDT 24
Finished Jun 04 01:47:21 PM PDT 24
Peak memory 234476 kb
Host smart-95e1126f-5830-4ded-abd1-54a9712b19b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812711738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2812711738
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3816790793
Short name T222
Test name
Test status
Simulation time 4548014987 ps
CPU time 45.89 seconds
Started Jun 04 01:41:02 PM PDT 24
Finished Jun 04 01:41:49 PM PDT 24
Peak memory 215292 kb
Host smart-c1562e92-320f-4e9f-8572-993303392f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816790793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3816790793
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.446787800
Short name T290
Test name
Test status
Simulation time 10619918207 ps
CPU time 25.67 seconds
Started Jun 04 01:41:05 PM PDT 24
Finished Jun 04 01:41:31 PM PDT 24
Peak memory 211456 kb
Host smart-313a4fa8-d571-4683-8941-b3ece7c63120
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=446787800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.446787800
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.4254526383
Short name T298
Test name
Test status
Simulation time 22293502833 ps
CPU time 50.76 seconds
Started Jun 04 01:40:51 PM PDT 24
Finished Jun 04 01:41:42 PM PDT 24
Peak memory 217732 kb
Host smart-b97d2c4c-1c55-4e62-9f56-68bb27025736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254526383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.4254526383
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.4160845621
Short name T5
Test name
Test status
Simulation time 393946035 ps
CPU time 24.27 seconds
Started Jun 04 01:40:59 PM PDT 24
Finished Jun 04 01:41:24 PM PDT 24
Peak memory 218408 kb
Host smart-d3675366-0096-4694-9a22-ecd0f202bd5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160845621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.4160845621
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3926053691
Short name T45
Test name
Test status
Simulation time 62457433487 ps
CPU time 9772.78 seconds
Started Jun 04 01:41:01 PM PDT 24
Finished Jun 04 04:23:56 PM PDT 24
Peak memory 236816 kb
Host smart-ca9dfe81-74e5-49f8-87c8-fd95ed27d109
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926053691 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.3926053691
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2848297537
Short name T282
Test name
Test status
Simulation time 13950362991 ps
CPU time 28.53 seconds
Started Jun 04 01:41:01 PM PDT 24
Finished Jun 04 01:41:30 PM PDT 24
Peak memory 212204 kb
Host smart-4b9bc8ca-8d6e-4f96-8bf6-741c94285df9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848297537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2848297537
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.524020313
Short name T132
Test name
Test status
Simulation time 43552460606 ps
CPU time 473.19 seconds
Started Jun 04 01:41:05 PM PDT 24
Finished Jun 04 01:48:59 PM PDT 24
Peak memory 237944 kb
Host smart-a9dee6cf-776d-4516-bae6-3129c508c56e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524020313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.524020313
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3203029243
Short name T126
Test name
Test status
Simulation time 8768480453 ps
CPU time 46.28 seconds
Started Jun 04 01:41:05 PM PDT 24
Finished Jun 04 01:41:52 PM PDT 24
Peak memory 215132 kb
Host smart-4f7f315f-9f66-40e9-8e84-30bcf160b0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203029243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3203029243
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3793448510
Short name T300
Test name
Test status
Simulation time 8268259379 ps
CPU time 16.48 seconds
Started Jun 04 01:41:01 PM PDT 24
Finished Jun 04 01:41:19 PM PDT 24
Peak memory 211628 kb
Host smart-22bf7735-2bd6-469c-9399-4d8a7ba9e2ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3793448510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3793448510
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.263440615
Short name T49
Test name
Test status
Simulation time 12328508414 ps
CPU time 75.46 seconds
Started Jun 04 01:41:02 PM PDT 24
Finished Jun 04 01:42:18 PM PDT 24
Peak memory 217828 kb
Host smart-cb6112e6-5ace-4528-b5b2-5fabbd75b880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263440615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.263440615
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1819339028
Short name T194
Test name
Test status
Simulation time 65932712810 ps
CPU time 168.4 seconds
Started Jun 04 01:41:00 PM PDT 24
Finished Jun 04 01:43:49 PM PDT 24
Peak memory 227804 kb
Host smart-f5be0ab6-a4ff-45b8-8d29-0b8b2bc8e2be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819339028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1819339028
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1544617420
Short name T301
Test name
Test status
Simulation time 16707088581 ps
CPU time 33.97 seconds
Started Jun 04 01:41:01 PM PDT 24
Finished Jun 04 01:41:36 PM PDT 24
Peak memory 211484 kb
Host smart-25c5b508-056f-4496-8dd1-49ecb4b2e4e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544617420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1544617420
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2371756839
Short name T21
Test name
Test status
Simulation time 329508660548 ps
CPU time 501.73 seconds
Started Jun 04 01:41:04 PM PDT 24
Finished Jun 04 01:49:26 PM PDT 24
Peak memory 239720 kb
Host smart-380c197e-4e7f-4ce8-902e-e0f85a9a186c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371756839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2371756839
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3042034782
Short name T343
Test name
Test status
Simulation time 4934664615 ps
CPU time 49.28 seconds
Started Jun 04 01:41:02 PM PDT 24
Finished Jun 04 01:41:52 PM PDT 24
Peak memory 215112 kb
Host smart-66f5936a-5be1-4012-8b24-10d18e2d01b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042034782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3042034782
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1079056957
Short name T99
Test name
Test status
Simulation time 1061866816 ps
CPU time 11.89 seconds
Started Jun 04 01:41:00 PM PDT 24
Finished Jun 04 01:41:13 PM PDT 24
Peak memory 211556 kb
Host smart-2fac4bd2-9a08-488e-8e0a-ddbd9706e864
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1079056957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1079056957
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1489529643
Short name T288
Test name
Test status
Simulation time 6336228007 ps
CPU time 63.12 seconds
Started Jun 04 01:41:01 PM PDT 24
Finished Jun 04 01:42:05 PM PDT 24
Peak memory 217036 kb
Host smart-ec596c1f-d6dd-4a41-812f-15ec1a8663ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489529643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1489529643
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2829723569
Short name T165
Test name
Test status
Simulation time 5012126860 ps
CPU time 45.91 seconds
Started Jun 04 01:41:02 PM PDT 24
Finished Jun 04 01:41:49 PM PDT 24
Peak memory 221216 kb
Host smart-9416e2d2-6cf2-4f26-8e6e-ce32c7386c3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829723569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2829723569
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3383510029
Short name T214
Test name
Test status
Simulation time 3021351441 ps
CPU time 26.79 seconds
Started Jun 04 01:41:10 PM PDT 24
Finished Jun 04 01:41:38 PM PDT 24
Peak memory 211380 kb
Host smart-e97f56ff-0dea-4a47-b3bf-dbe834fda25f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383510029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3383510029
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3166682228
Short name T42
Test name
Test status
Simulation time 126083885289 ps
CPU time 569.54 seconds
Started Jun 04 01:41:12 PM PDT 24
Finished Jun 04 01:50:42 PM PDT 24
Peak memory 237456 kb
Host smart-30e6f947-f39a-4444-8c59-1c4a9050bfe3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166682228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3166682228
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3660362897
Short name T25
Test name
Test status
Simulation time 8542079776 ps
CPU time 69.06 seconds
Started Jun 04 01:41:10 PM PDT 24
Finished Jun 04 01:42:20 PM PDT 24
Peak memory 213036 kb
Host smart-d78d6b64-e983-4edf-bd92-9867133dd2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660362897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3660362897
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3105796012
Short name T10
Test name
Test status
Simulation time 17839765519 ps
CPU time 34.49 seconds
Started Jun 04 01:41:09 PM PDT 24
Finished Jun 04 01:41:44 PM PDT 24
Peak memory 211796 kb
Host smart-ebc5f9a1-b0cb-42dc-bf04-d1791e65a8cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3105796012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3105796012
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.4216382629
Short name T209
Test name
Test status
Simulation time 13857902449 ps
CPU time 65.59 seconds
Started Jun 04 01:40:59 PM PDT 24
Finished Jun 04 01:42:05 PM PDT 24
Peak memory 217492 kb
Host smart-96fb174d-fa03-4e62-9b98-be673a8a773e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216382629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.4216382629
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1666246605
Short name T309
Test name
Test status
Simulation time 10042532124 ps
CPU time 44.35 seconds
Started Jun 04 01:41:11 PM PDT 24
Finished Jun 04 01:41:57 PM PDT 24
Peak memory 219420 kb
Host smart-f2478f6c-a4e3-479d-b01e-683b5eb5ad81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666246605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1666246605
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.158069393
Short name T157
Test name
Test status
Simulation time 11204658452 ps
CPU time 25.74 seconds
Started Jun 04 01:41:12 PM PDT 24
Finished Jun 04 01:41:39 PM PDT 24
Peak memory 212292 kb
Host smart-f6fa1740-2fd7-4393-9f7c-fdf54080f143
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158069393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.158069393
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1250208707
Short name T255
Test name
Test status
Simulation time 174052801044 ps
CPU time 579.82 seconds
Started Jun 04 01:41:10 PM PDT 24
Finished Jun 04 01:50:51 PM PDT 24
Peak memory 217168 kb
Host smart-247a4354-20a9-4a66-89c1-46f38e863195
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250208707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1250208707
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.722113737
Short name T161
Test name
Test status
Simulation time 18819621611 ps
CPU time 48.04 seconds
Started Jun 04 01:41:11 PM PDT 24
Finished Jun 04 01:42:00 PM PDT 24
Peak memory 215452 kb
Host smart-56536f8a-6f9f-44f3-9703-1a1af1fb1a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722113737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.722113737
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3964211042
Short name T40
Test name
Test status
Simulation time 356061641 ps
CPU time 10.93 seconds
Started Jun 04 01:41:11 PM PDT 24
Finished Jun 04 01:41:23 PM PDT 24
Peak memory 212376 kb
Host smart-182d8550-2d09-4949-8eac-d9e91e0280f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3964211042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3964211042
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1878456949
Short name T53
Test name
Test status
Simulation time 12385295518 ps
CPU time 39.65 seconds
Started Jun 04 01:41:11 PM PDT 24
Finished Jun 04 01:41:52 PM PDT 24
Peak memory 217932 kb
Host smart-6f0da2e2-9c08-4618-958c-951f99017af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878456949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1878456949
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.814213345
Short name T287
Test name
Test status
Simulation time 3772037453 ps
CPU time 17.24 seconds
Started Jun 04 01:41:11 PM PDT 24
Finished Jun 04 01:41:30 PM PDT 24
Peak memory 213888 kb
Host smart-5d816127-c178-42d2-93c8-94421d994765
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814213345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.814213345
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1739106043
Short name T302
Test name
Test status
Simulation time 176443623 ps
CPU time 8.38 seconds
Started Jun 04 01:41:11 PM PDT 24
Finished Jun 04 01:41:20 PM PDT 24
Peak memory 211304 kb
Host smart-56046a7b-ff49-4a65-a64c-0d7db3cb0ad4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739106043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1739106043
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.190571301
Short name T239
Test name
Test status
Simulation time 10907635209 ps
CPU time 38.85 seconds
Started Jun 04 01:41:11 PM PDT 24
Finished Jun 04 01:41:51 PM PDT 24
Peak memory 215224 kb
Host smart-9dce401f-d259-440e-bb3b-47348f5e61c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190571301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.190571301
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2565132935
Short name T39
Test name
Test status
Simulation time 11859616042 ps
CPU time 22.21 seconds
Started Jun 04 01:41:11 PM PDT 24
Finished Jun 04 01:41:34 PM PDT 24
Peak memory 212932 kb
Host smart-6a41b20e-40cd-4c7b-9339-01562d2223e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2565132935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2565132935
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2005729154
Short name T181
Test name
Test status
Simulation time 10867301904 ps
CPU time 56.39 seconds
Started Jun 04 01:41:11 PM PDT 24
Finished Jun 04 01:42:09 PM PDT 24
Peak memory 217160 kb
Host smart-b95e418a-c110-4f3f-854d-2dcac2dc2d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005729154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2005729154
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2069303536
Short name T361
Test name
Test status
Simulation time 4222678071 ps
CPU time 69.89 seconds
Started Jun 04 01:41:09 PM PDT 24
Finished Jun 04 01:42:20 PM PDT 24
Peak memory 221668 kb
Host smart-c5121562-d400-408f-b8d3-1726e9aaba29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069303536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2069303536
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2206539308
Short name T272
Test name
Test status
Simulation time 660374020 ps
CPU time 8.33 seconds
Started Jun 04 01:41:11 PM PDT 24
Finished Jun 04 01:41:20 PM PDT 24
Peak memory 211316 kb
Host smart-eabdff8f-34c5-40f3-9ed1-d43a663d1d45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206539308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2206539308
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1895854105
Short name T115
Test name
Test status
Simulation time 69990289976 ps
CPU time 831.66 seconds
Started Jun 04 01:41:09 PM PDT 24
Finished Jun 04 01:55:02 PM PDT 24
Peak memory 217924 kb
Host smart-f84237ec-7bfd-4370-8805-f15cc511efc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895854105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1895854105
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.991200678
Short name T267
Test name
Test status
Simulation time 399845780 ps
CPU time 20.06 seconds
Started Jun 04 01:41:12 PM PDT 24
Finished Jun 04 01:41:33 PM PDT 24
Peak memory 214856 kb
Host smart-b54ff231-1428-493a-b89f-4d76c558abb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991200678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.991200678
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2761279384
Short name T138
Test name
Test status
Simulation time 23904678492 ps
CPU time 27.18 seconds
Started Jun 04 01:41:09 PM PDT 24
Finished Jun 04 01:41:37 PM PDT 24
Peak memory 211888 kb
Host smart-231ef79e-dac6-4515-8133-7a1a29340368
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2761279384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2761279384
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3505085256
Short name T230
Test name
Test status
Simulation time 8506572807 ps
CPU time 38.63 seconds
Started Jun 04 01:41:09 PM PDT 24
Finished Jun 04 01:41:48 PM PDT 24
Peak memory 218012 kb
Host smart-5f1ed841-aab3-4643-88e9-8c311520d023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505085256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3505085256
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3776570194
Short name T286
Test name
Test status
Simulation time 22983624940 ps
CPU time 256.98 seconds
Started Jun 04 01:41:11 PM PDT 24
Finished Jun 04 01:45:30 PM PDT 24
Peak memory 230908 kb
Host smart-a62f7dfe-a175-4b2d-bf21-a2560245d674
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776570194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3776570194
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1014771391
Short name T353
Test name
Test status
Simulation time 93856826616 ps
CPU time 936.07 seconds
Started Jun 04 01:41:12 PM PDT 24
Finished Jun 04 01:56:49 PM PDT 24
Peak memory 235924 kb
Host smart-a247eb42-685f-4683-9533-7549094af371
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014771391 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1014771391
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.4155468442
Short name T263
Test name
Test status
Simulation time 20820363177 ps
CPU time 29.74 seconds
Started Jun 04 01:41:10 PM PDT 24
Finished Jun 04 01:41:40 PM PDT 24
Peak memory 211456 kb
Host smart-83e744b3-e381-4c39-9fb3-769445f8f205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155468442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.4155468442
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2991433297
Short name T250
Test name
Test status
Simulation time 24204946719 ps
CPU time 241.89 seconds
Started Jun 04 01:41:13 PM PDT 24
Finished Jun 04 01:45:15 PM PDT 24
Peak memory 215768 kb
Host smart-4c6d0ce7-90de-4373-885e-fc345f75b4ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991433297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2991433297
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.55683938
Short name T137
Test name
Test status
Simulation time 2410550691 ps
CPU time 27.84 seconds
Started Jun 04 01:41:11 PM PDT 24
Finished Jun 04 01:41:40 PM PDT 24
Peak memory 214776 kb
Host smart-3e6ada87-c389-4836-968b-ae08868b51f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55683938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.55683938
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1439852186
Short name T358
Test name
Test status
Simulation time 3749346427 ps
CPU time 31.12 seconds
Started Jun 04 01:41:11 PM PDT 24
Finished Jun 04 01:41:43 PM PDT 24
Peak memory 212328 kb
Host smart-cddda70b-7d22-4381-b9e5-08692f715757
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1439852186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1439852186
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1935929146
Short name T316
Test name
Test status
Simulation time 8611292430 ps
CPU time 46.83 seconds
Started Jun 04 01:41:12 PM PDT 24
Finished Jun 04 01:42:00 PM PDT 24
Peak memory 216480 kb
Host smart-86e8c96c-2df0-4b37-987c-11395b17b009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935929146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1935929146
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3191011771
Short name T231
Test name
Test status
Simulation time 61425926402 ps
CPU time 65.33 seconds
Started Jun 04 01:41:13 PM PDT 24
Finished Jun 04 01:42:19 PM PDT 24
Peak memory 218316 kb
Host smart-11e4c1a3-71f0-423e-864e-3f96b30c9b7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191011771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3191011771
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2758278341
Short name T43
Test name
Test status
Simulation time 157075831788 ps
CPU time 1615.2 seconds
Started Jun 04 01:41:11 PM PDT 24
Finished Jun 04 02:08:07 PM PDT 24
Peak memory 236908 kb
Host smart-e960b3fe-ba1e-4c99-a30d-b340cd1c0b34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758278341 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2758278341
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.468390789
Short name T171
Test name
Test status
Simulation time 174354492 ps
CPU time 8.47 seconds
Started Jun 04 01:41:19 PM PDT 24
Finished Jun 04 01:41:29 PM PDT 24
Peak memory 211296 kb
Host smart-52359c1e-cb64-4fff-bdc0-377bfdd193c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468390789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.468390789
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3268068867
Short name T294
Test name
Test status
Simulation time 10862664348 ps
CPU time 189.66 seconds
Started Jun 04 01:41:21 PM PDT 24
Finished Jun 04 01:44:32 PM PDT 24
Peak memory 228784 kb
Host smart-78ddae01-6b8c-42e0-a0db-19141b0f0976
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268068867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3268068867
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.119836189
Short name T199
Test name
Test status
Simulation time 7346858318 ps
CPU time 42.78 seconds
Started Jun 04 01:41:21 PM PDT 24
Finished Jun 04 01:42:05 PM PDT 24
Peak memory 215332 kb
Host smart-46330b71-18f9-4317-a1c9-a8d8014b4317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119836189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.119836189
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1337375989
Short name T103
Test name
Test status
Simulation time 1111749027 ps
CPU time 17.59 seconds
Started Jun 04 01:41:26 PM PDT 24
Finished Jun 04 01:41:44 PM PDT 24
Peak memory 212584 kb
Host smart-0af933e3-e941-4e7d-887a-3557682b611b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1337375989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1337375989
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2132071505
Short name T7
Test name
Test status
Simulation time 15311839001 ps
CPU time 52.13 seconds
Started Jun 04 01:41:10 PM PDT 24
Finished Jun 04 01:42:03 PM PDT 24
Peak memory 218124 kb
Host smart-a10c8bdb-1555-4b16-8d95-adc315603b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132071505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2132071505
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.559845137
Short name T271
Test name
Test status
Simulation time 31622627848 ps
CPU time 91.5 seconds
Started Jun 04 01:41:11 PM PDT 24
Finished Jun 04 01:42:44 PM PDT 24
Peak memory 219432 kb
Host smart-e7de7a26-8b0d-4cac-9f9e-fc20830da3b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559845137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.559845137
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1629340419
Short name T183
Test name
Test status
Simulation time 1062554460 ps
CPU time 15.57 seconds
Started Jun 04 01:41:19 PM PDT 24
Finished Jun 04 01:41:35 PM PDT 24
Peak memory 211372 kb
Host smart-ed3e4771-2cea-47c1-b2e9-d07abde4851d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629340419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1629340419
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3514394495
Short name T2
Test name
Test status
Simulation time 135751046702 ps
CPU time 426.65 seconds
Started Jun 04 01:41:20 PM PDT 24
Finished Jun 04 01:48:28 PM PDT 24
Peak memory 217204 kb
Host smart-750c0c1a-4eac-4c48-93b6-4231ef08c90c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514394495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3514394495
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1714499943
Short name T269
Test name
Test status
Simulation time 18116259620 ps
CPU time 50.25 seconds
Started Jun 04 01:41:20 PM PDT 24
Finished Jun 04 01:42:12 PM PDT 24
Peak memory 214408 kb
Host smart-fd4bb6d6-b80f-421a-9f2a-3764a080cef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714499943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1714499943
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1786471123
Short name T354
Test name
Test status
Simulation time 3721670450 ps
CPU time 30.97 seconds
Started Jun 04 01:41:19 PM PDT 24
Finished Jun 04 01:41:51 PM PDT 24
Peak memory 211408 kb
Host smart-d81e6222-7dfc-4d7a-ac6a-f4a673e99af6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1786471123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1786471123
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3332554093
Short name T266
Test name
Test status
Simulation time 25318246383 ps
CPU time 58.95 seconds
Started Jun 04 01:41:20 PM PDT 24
Finished Jun 04 01:42:20 PM PDT 24
Peak memory 217960 kb
Host smart-2c3bb6d3-747a-47ee-8fc5-93c6d4161b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332554093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3332554093
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3372370735
Short name T297
Test name
Test status
Simulation time 6453346560 ps
CPU time 70.92 seconds
Started Jun 04 01:41:18 PM PDT 24
Finished Jun 04 01:42:30 PM PDT 24
Peak memory 219336 kb
Host smart-e23c5985-ad7e-4ad3-994c-732c80bc11d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372370735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3372370735
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1130356994
Short name T176
Test name
Test status
Simulation time 8155057972 ps
CPU time 19.15 seconds
Started Jun 04 01:39:55 PM PDT 24
Finished Jun 04 01:40:15 PM PDT 24
Peak memory 211472 kb
Host smart-87d67252-adbf-4886-ab70-7e5aacfab08e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130356994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1130356994
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1744895885
Short name T248
Test name
Test status
Simulation time 317530309855 ps
CPU time 376 seconds
Started Jun 04 01:39:56 PM PDT 24
Finished Jun 04 01:46:15 PM PDT 24
Peak memory 224768 kb
Host smart-8334ef91-9df6-4724-8667-52b8f2221d51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744895885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1744895885
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3452306595
Short name T284
Test name
Test status
Simulation time 6421026643 ps
CPU time 31.04 seconds
Started Jun 04 01:39:55 PM PDT 24
Finished Jun 04 01:40:28 PM PDT 24
Peak memory 216700 kb
Host smart-9d42be9c-23ca-441a-9585-c36c9bab1e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452306595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3452306595
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2463055230
Short name T330
Test name
Test status
Simulation time 182676497 ps
CPU time 10.58 seconds
Started Jun 04 01:39:55 PM PDT 24
Finished Jun 04 01:40:07 PM PDT 24
Peak memory 212312 kb
Host smart-8c7458cd-a89f-40f5-9f5c-c8870cd8f7ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2463055230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2463055230
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2457297528
Short name T364
Test name
Test status
Simulation time 40956268964 ps
CPU time 61.5 seconds
Started Jun 04 01:39:56 PM PDT 24
Finished Jun 04 01:40:59 PM PDT 24
Peak memory 217436 kb
Host smart-d98a3f7f-6445-42b1-b8e8-a24eb8eb577e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457297528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2457297528
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1881908299
Short name T237
Test name
Test status
Simulation time 38112785756 ps
CPU time 83.6 seconds
Started Jun 04 01:39:56 PM PDT 24
Finished Jun 04 01:41:22 PM PDT 24
Peak memory 219308 kb
Host smart-f7b93e24-456f-45be-ad78-92ba433a743e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881908299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1881908299
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2459126758
Short name T215
Test name
Test status
Simulation time 174353395 ps
CPU time 8.37 seconds
Started Jun 04 01:39:58 PM PDT 24
Finished Jun 04 01:40:08 PM PDT 24
Peak memory 211372 kb
Host smart-834efbd3-c10f-446e-85aa-34d6f2b97e25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459126758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2459126758
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1457441434
Short name T123
Test name
Test status
Simulation time 6811959794 ps
CPU time 60.46 seconds
Started Jun 04 01:39:57 PM PDT 24
Finished Jun 04 01:40:59 PM PDT 24
Peak memory 215328 kb
Host smart-ee5a8508-142c-4f7d-9e72-6d5f6c3efcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457441434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1457441434
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3887155796
Short name T331
Test name
Test status
Simulation time 8008433168 ps
CPU time 30.03 seconds
Started Jun 04 01:39:57 PM PDT 24
Finished Jun 04 01:40:29 PM PDT 24
Peak memory 212656 kb
Host smart-1954af66-a980-48d3-b422-c742aed749ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3887155796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3887155796
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2124498113
Short name T131
Test name
Test status
Simulation time 4537704109 ps
CPU time 48.54 seconds
Started Jun 04 01:39:56 PM PDT 24
Finished Jun 04 01:40:46 PM PDT 24
Peak memory 216692 kb
Host smart-154431f8-31de-4511-a451-90aacbf5529e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124498113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2124498113
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2110348500
Short name T229
Test name
Test status
Simulation time 19488993464 ps
CPU time 111.63 seconds
Started Jun 04 01:39:59 PM PDT 24
Finished Jun 04 01:41:52 PM PDT 24
Peak memory 218400 kb
Host smart-6cb9cb33-ca47-4b9b-9966-932ae5a8e9f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110348500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2110348500
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3030778048
Short name T360
Test name
Test status
Simulation time 374887460277 ps
CPU time 3973.28 seconds
Started Jun 04 01:39:56 PM PDT 24
Finished Jun 04 02:46:12 PM PDT 24
Peak memory 257180 kb
Host smart-611e251a-b340-4b86-a5d4-2d9132ce0135
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030778048 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.3030778048
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3808801717
Short name T135
Test name
Test status
Simulation time 12678110554 ps
CPU time 17.72 seconds
Started Jun 04 01:39:54 PM PDT 24
Finished Jun 04 01:40:13 PM PDT 24
Peak memory 211480 kb
Host smart-fc5fd994-89a2-410d-ba48-b2ce9270819e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808801717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3808801717
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1806929871
Short name T241
Test name
Test status
Simulation time 3196161782 ps
CPU time 269.14 seconds
Started Jun 04 01:39:56 PM PDT 24
Finished Jun 04 01:44:26 PM PDT 24
Peak memory 240496 kb
Host smart-72c1fb08-ce89-462d-b232-a29f53a299d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806929871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1806929871
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2422253864
Short name T213
Test name
Test status
Simulation time 1454715378 ps
CPU time 22.33 seconds
Started Jun 04 01:39:56 PM PDT 24
Finished Jun 04 01:40:21 PM PDT 24
Peak memory 214720 kb
Host smart-cff9c289-865e-4714-9951-54bd198f6f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422253864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2422253864
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3097771621
Short name T174
Test name
Test status
Simulation time 19155562268 ps
CPU time 31.51 seconds
Started Jun 04 01:39:57 PM PDT 24
Finished Jun 04 01:40:30 PM PDT 24
Peak memory 212892 kb
Host smart-8f47b7c5-428a-4705-9bb2-69567081415c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3097771621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3097771621
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3696768718
Short name T223
Test name
Test status
Simulation time 1054598782 ps
CPU time 29.1 seconds
Started Jun 04 01:39:57 PM PDT 24
Finished Jun 04 01:40:28 PM PDT 24
Peak memory 216608 kb
Host smart-1593d217-694a-410d-b655-42537f376623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696768718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3696768718
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1845826826
Short name T211
Test name
Test status
Simulation time 11825909274 ps
CPU time 129.51 seconds
Started Jun 04 01:39:54 PM PDT 24
Finished Jun 04 01:42:05 PM PDT 24
Peak memory 219420 kb
Host smart-8522fc5c-723a-4513-bc36-03bc0b84ce81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845826826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1845826826
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1895148899
Short name T244
Test name
Test status
Simulation time 4119301868 ps
CPU time 21.34 seconds
Started Jun 04 01:40:05 PM PDT 24
Finished Jun 04 01:40:27 PM PDT 24
Peak memory 211848 kb
Host smart-290e35b7-c8ee-44ac-9c5a-a5aacb1b35b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895148899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1895148899
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2806451506
Short name T306
Test name
Test status
Simulation time 266066752466 ps
CPU time 725.73 seconds
Started Jun 04 01:39:57 PM PDT 24
Finished Jun 04 01:52:05 PM PDT 24
Peak memory 240184 kb
Host smart-90734bc8-58f0-41d6-95d9-48003b6beb1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806451506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2806451506
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1171276988
Short name T280
Test name
Test status
Simulation time 2537466094 ps
CPU time 19.5 seconds
Started Jun 04 01:39:58 PM PDT 24
Finished Jun 04 01:40:19 PM PDT 24
Peak memory 214704 kb
Host smart-4fdfe07c-0d33-40bc-a987-1cc70de4bd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171276988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1171276988
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.879460616
Short name T225
Test name
Test status
Simulation time 2691101575 ps
CPU time 25.98 seconds
Started Jun 04 01:40:00 PM PDT 24
Finished Jun 04 01:40:27 PM PDT 24
Peak memory 211392 kb
Host smart-ae1d8a97-07eb-497f-8afa-14ae3f3275be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=879460616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.879460616
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2708768044
Short name T4
Test name
Test status
Simulation time 687051475 ps
CPU time 20.05 seconds
Started Jun 04 01:39:56 PM PDT 24
Finished Jun 04 01:40:17 PM PDT 24
Peak memory 217872 kb
Host smart-d35500ed-7502-4677-82bc-f225610ca619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708768044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2708768044
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1985617432
Short name T163
Test name
Test status
Simulation time 521838584 ps
CPU time 37.21 seconds
Started Jun 04 01:39:56 PM PDT 24
Finished Jun 04 01:40:34 PM PDT 24
Peak memory 218556 kb
Host smart-28490704-05cf-44c3-ab1e-f269f171ead4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985617432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1985617432
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2763666981
Short name T47
Test name
Test status
Simulation time 157002362691 ps
CPU time 1546.34 seconds
Started Jun 04 01:40:05 PM PDT 24
Finished Jun 04 02:05:53 PM PDT 24
Peak memory 239096 kb
Host smart-9b337f29-7b7a-4994-a552-c341da57ce1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763666981 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.2763666981
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1554713396
Short name T224
Test name
Test status
Simulation time 11129317901 ps
CPU time 23.56 seconds
Started Jun 04 01:40:07 PM PDT 24
Finished Jun 04 01:40:32 PM PDT 24
Peak memory 211416 kb
Host smart-74279b50-6fa3-464d-9553-7b62f1371497
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554713396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1554713396
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3883382674
Short name T9
Test name
Test status
Simulation time 22889220691 ps
CPU time 249.25 seconds
Started Jun 04 01:40:06 PM PDT 24
Finished Jun 04 01:44:17 PM PDT 24
Peak memory 228048 kb
Host smart-ffcf861c-9419-4f08-a473-d42317d48805
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883382674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3883382674
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.50468420
Short name T246
Test name
Test status
Simulation time 47696523915 ps
CPU time 57.08 seconds
Started Jun 04 01:40:06 PM PDT 24
Finished Jun 04 01:41:05 PM PDT 24
Peak memory 215148 kb
Host smart-f504b2f4-26d4-49be-8c69-dd64949d1e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50468420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.50468420
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1038741242
Short name T8
Test name
Test status
Simulation time 13837048415 ps
CPU time 28.24 seconds
Started Jun 04 01:40:05 PM PDT 24
Finished Jun 04 01:40:34 PM PDT 24
Peak memory 211372 kb
Host smart-b7952710-6a41-4437-b503-905f9bfd5233
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1038741242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1038741242
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2097479352
Short name T117
Test name
Test status
Simulation time 350978757 ps
CPU time 19.91 seconds
Started Jun 04 01:40:06 PM PDT 24
Finished Jun 04 01:40:27 PM PDT 24
Peak memory 216848 kb
Host smart-b2b74dd8-929a-4ef5-8bab-b4688bcf236b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097479352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2097479352
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2329881630
Short name T226
Test name
Test status
Simulation time 48366168461 ps
CPU time 104.36 seconds
Started Jun 04 01:40:04 PM PDT 24
Finished Jun 04 01:41:49 PM PDT 24
Peak memory 220128 kb
Host smart-e05e0025-0bf3-4d03-9ea5-20575edd9af3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329881630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2329881630
Directory /workspace/9.rom_ctrl_stress_all/latest
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