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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.48 96.97 92.88 97.88 100.00 98.37 97.89 98.37


Total test records in report: 455
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T303 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2796652111 Jun 05 05:16:14 PM PDT 24 Jun 05 05:16:47 PM PDT 24 15391062020 ps
T304 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1461387865 Jun 05 05:16:44 PM PDT 24 Jun 05 05:17:36 PM PDT 24 5581251385 ps
T305 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1047519105 Jun 05 05:17:52 PM PDT 24 Jun 05 05:27:37 PM PDT 24 29645776526 ps
T306 /workspace/coverage/default/0.rom_ctrl_alert_test.1986559176 Jun 05 05:15:27 PM PDT 24 Jun 05 05:15:57 PM PDT 24 5392769137 ps
T307 /workspace/coverage/default/33.rom_ctrl_stress_all.656897538 Jun 05 05:17:32 PM PDT 24 Jun 05 05:19:22 PM PDT 24 12334653629 ps
T308 /workspace/coverage/default/39.rom_ctrl_alert_test.527986912 Jun 05 05:17:59 PM PDT 24 Jun 05 05:18:09 PM PDT 24 167386895 ps
T309 /workspace/coverage/default/3.rom_ctrl_stress_all.620547970 Jun 05 05:15:26 PM PDT 24 Jun 05 05:15:55 PM PDT 24 450996204 ps
T310 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.704507221 Jun 05 05:16:21 PM PDT 24 Jun 05 05:17:21 PM PDT 24 16426282614 ps
T311 /workspace/coverage/default/49.rom_ctrl_stress_all.4197635732 Jun 05 05:18:20 PM PDT 24 Jun 05 05:18:45 PM PDT 24 930711533 ps
T312 /workspace/coverage/default/41.rom_ctrl_stress_all.3243230034 Jun 05 05:18:03 PM PDT 24 Jun 05 05:19:44 PM PDT 24 63901117043 ps
T313 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.273834549 Jun 05 05:17:55 PM PDT 24 Jun 05 05:18:42 PM PDT 24 10112247088 ps
T314 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1532452856 Jun 05 05:18:13 PM PDT 24 Jun 05 05:18:25 PM PDT 24 355228741 ps
T315 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.4066420379 Jun 05 05:16:54 PM PDT 24 Jun 05 05:24:22 PM PDT 24 6633075151 ps
T316 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.273959015 Jun 05 05:17:44 PM PDT 24 Jun 05 05:18:49 PM PDT 24 28269246302 ps
T317 /workspace/coverage/default/31.rom_ctrl_alert_test.4194003974 Jun 05 05:17:20 PM PDT 24 Jun 05 05:17:42 PM PDT 24 4117824331 ps
T318 /workspace/coverage/default/28.rom_ctrl_alert_test.170253855 Jun 05 05:17:05 PM PDT 24 Jun 05 05:17:24 PM PDT 24 2361212223 ps
T319 /workspace/coverage/default/19.rom_ctrl_stress_all.99597589 Jun 05 05:16:33 PM PDT 24 Jun 05 05:17:29 PM PDT 24 12382598097 ps
T320 /workspace/coverage/default/17.rom_ctrl_stress_all.623576166 Jun 05 05:16:21 PM PDT 24 Jun 05 05:17:22 PM PDT 24 12036725703 ps
T321 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1720208998 Jun 05 05:17:48 PM PDT 24 Jun 05 05:18:28 PM PDT 24 3115049430 ps
T322 /workspace/coverage/default/37.rom_ctrl_alert_test.2361547541 Jun 05 05:17:53 PM PDT 24 Jun 05 05:18:01 PM PDT 24 689572977 ps
T323 /workspace/coverage/default/18.rom_ctrl_smoke.2865132285 Jun 05 05:16:22 PM PDT 24 Jun 05 05:16:51 PM PDT 24 6263358793 ps
T324 /workspace/coverage/default/18.rom_ctrl_alert_test.855245948 Jun 05 05:16:32 PM PDT 24 Jun 05 05:17:04 PM PDT 24 29369658728 ps
T325 /workspace/coverage/default/19.rom_ctrl_smoke.714977770 Jun 05 05:16:34 PM PDT 24 Jun 05 05:18:05 PM PDT 24 8537132197 ps
T326 /workspace/coverage/default/32.rom_ctrl_stress_all.3507498544 Jun 05 05:17:21 PM PDT 24 Jun 05 05:18:27 PM PDT 24 6062581620 ps
T327 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4248553769 Jun 05 05:17:31 PM PDT 24 Jun 05 05:17:57 PM PDT 24 1127388989 ps
T328 /workspace/coverage/default/24.rom_ctrl_smoke.3450080723 Jun 05 05:16:50 PM PDT 24 Jun 05 05:17:11 PM PDT 24 4282741968 ps
T329 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.166200512 Jun 05 05:18:13 PM PDT 24 Jun 05 05:18:34 PM PDT 24 14220823456 ps
T330 /workspace/coverage/default/17.rom_ctrl_alert_test.1059280299 Jun 05 05:16:23 PM PDT 24 Jun 05 05:16:52 PM PDT 24 3420939771 ps
T331 /workspace/coverage/default/44.rom_ctrl_stress_all.303336647 Jun 05 05:18:11 PM PDT 24 Jun 05 05:19:59 PM PDT 24 14424548694 ps
T332 /workspace/coverage/default/8.rom_ctrl_smoke.2545132336 Jun 05 05:15:42 PM PDT 24 Jun 05 05:16:24 PM PDT 24 2766818953 ps
T333 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3227159901 Jun 05 05:18:00 PM PDT 24 Jun 05 05:18:26 PM PDT 24 5615417750 ps
T334 /workspace/coverage/default/9.rom_ctrl_smoke.648333655 Jun 05 05:15:46 PM PDT 24 Jun 05 05:17:09 PM PDT 24 7704097913 ps
T38 /workspace/coverage/default/1.rom_ctrl_sec_cm.1988550170 Jun 05 05:15:29 PM PDT 24 Jun 05 05:17:59 PM PDT 24 9076556615 ps
T335 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1577906822 Jun 05 05:15:36 PM PDT 24 Jun 05 05:16:04 PM PDT 24 10173731993 ps
T336 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1602761275 Jun 05 05:17:39 PM PDT 24 Jun 05 05:23:02 PM PDT 24 417516255285 ps
T337 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.123090368 Jun 05 05:17:52 PM PDT 24 Jun 05 05:18:21 PM PDT 24 5692012921 ps
T338 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3487928725 Jun 05 05:17:16 PM PDT 24 Jun 05 05:21:17 PM PDT 24 106495410933 ps
T339 /workspace/coverage/default/26.rom_ctrl_alert_test.2457357880 Jun 05 05:16:59 PM PDT 24 Jun 05 05:17:09 PM PDT 24 331858079 ps
T340 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1829231704 Jun 05 05:15:59 PM PDT 24 Jun 05 05:26:12 PM PDT 24 268401203551 ps
T341 /workspace/coverage/default/12.rom_ctrl_stress_all.3668634101 Jun 05 05:15:57 PM PDT 24 Jun 05 05:17:39 PM PDT 24 20899684868 ps
T342 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.371807708 Jun 05 05:16:51 PM PDT 24 Jun 05 05:17:58 PM PDT 24 16323012646 ps
T343 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1364689251 Jun 05 05:15:43 PM PDT 24 Jun 05 05:19:19 PM PDT 24 6777392033 ps
T344 /workspace/coverage/default/32.rom_ctrl_alert_test.739348698 Jun 05 05:17:32 PM PDT 24 Jun 05 05:17:41 PM PDT 24 169104051 ps
T345 /workspace/coverage/default/27.rom_ctrl_alert_test.1090732835 Jun 05 05:17:07 PM PDT 24 Jun 05 05:17:32 PM PDT 24 7942715281 ps
T346 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.729505856 Jun 05 05:17:37 PM PDT 24 Jun 05 05:21:49 PM PDT 24 3822542984 ps
T53 /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3539306705 Jun 05 05:15:43 PM PDT 24 Jun 05 05:53:03 PM PDT 24 238487124632 ps
T347 /workspace/coverage/default/47.rom_ctrl_alert_test.3962651263 Jun 05 05:18:20 PM PDT 24 Jun 05 05:18:51 PM PDT 24 3671330411 ps
T348 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3403689399 Jun 05 05:15:42 PM PDT 24 Jun 05 05:15:54 PM PDT 24 2471042952 ps
T54 /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2677435998 Jun 05 05:17:44 PM PDT 24 Jun 05 05:35:42 PM PDT 24 27068852478 ps
T349 /workspace/coverage/default/26.rom_ctrl_smoke.1190329112 Jun 05 05:17:00 PM PDT 24 Jun 05 05:17:44 PM PDT 24 3947245174 ps
T350 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3680123349 Jun 05 05:15:35 PM PDT 24 Jun 05 05:25:31 PM PDT 24 125936637112 ps
T351 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.944595162 Jun 05 05:16:33 PM PDT 24 Jun 05 05:16:50 PM PDT 24 1052710136 ps
T352 /workspace/coverage/default/40.rom_ctrl_stress_all.465613072 Jun 05 05:18:00 PM PDT 24 Jun 05 05:18:25 PM PDT 24 1735242132 ps
T353 /workspace/coverage/default/13.rom_ctrl_alert_test.622781050 Jun 05 05:16:09 PM PDT 24 Jun 05 05:16:40 PM PDT 24 3613610120 ps
T354 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1230435578 Jun 05 05:18:13 PM PDT 24 Jun 05 05:19:04 PM PDT 24 21768733424 ps
T55 /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1511550404 Jun 05 05:18:12 PM PDT 24 Jun 05 05:32:24 PM PDT 24 21743714331 ps
T355 /workspace/coverage/default/10.rom_ctrl_smoke.1282420715 Jun 05 05:15:52 PM PDT 24 Jun 05 05:16:14 PM PDT 24 352405763 ps
T356 /workspace/coverage/default/43.rom_ctrl_smoke.1090218903 Jun 05 05:18:12 PM PDT 24 Jun 05 05:18:34 PM PDT 24 439730893 ps
T357 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1833384839 Jun 05 05:16:34 PM PDT 24 Jun 05 05:17:14 PM PDT 24 3257675227 ps
T358 /workspace/coverage/default/12.rom_ctrl_smoke.3060899174 Jun 05 05:16:02 PM PDT 24 Jun 05 05:16:37 PM PDT 24 12226924859 ps
T67 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1023138487 Jun 05 05:33:09 PM PDT 24 Jun 05 05:33:34 PM PDT 24 8899613303 ps
T56 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1976003596 Jun 05 05:33:40 PM PDT 24 Jun 05 05:34:05 PM PDT 24 4618830048 ps
T68 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.937193797 Jun 05 05:33:45 PM PDT 24 Jun 05 05:34:04 PM PDT 24 12653577579 ps
T69 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.420736715 Jun 05 05:33:46 PM PDT 24 Jun 05 05:34:16 PM PDT 24 4352525957 ps
T108 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.15670603 Jun 05 05:33:26 PM PDT 24 Jun 05 05:33:50 PM PDT 24 13397501697 ps
T57 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3178461057 Jun 05 05:34:24 PM PDT 24 Jun 05 05:34:49 PM PDT 24 2241822318 ps
T76 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4286163647 Jun 05 05:34:21 PM PDT 24 Jun 05 05:34:59 PM PDT 24 3439768498 ps
T359 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3961778472 Jun 05 05:33:24 PM PDT 24 Jun 05 05:33:50 PM PDT 24 2424879724 ps
T63 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.223636804 Jun 05 05:33:08 PM PDT 24 Jun 05 05:35:41 PM PDT 24 603562869 ps
T360 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2546272270 Jun 05 05:34:31 PM PDT 24 Jun 05 05:34:43 PM PDT 24 1426822717 ps
T361 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3301385639 Jun 05 05:33:17 PM PDT 24 Jun 05 05:33:43 PM PDT 24 3041123897 ps
T362 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.650977116 Jun 05 05:34:15 PM PDT 24 Jun 05 05:34:44 PM PDT 24 38069342341 ps
T363 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1376967083 Jun 05 05:34:15 PM PDT 24 Jun 05 05:34:35 PM PDT 24 1708466205 ps
T109 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.302390102 Jun 05 05:33:30 PM PDT 24 Jun 05 05:34:02 PM PDT 24 14038137023 ps
T364 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3655134007 Jun 05 05:33:59 PM PDT 24 Jun 05 05:34:29 PM PDT 24 11084459090 ps
T365 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2336579414 Jun 05 05:33:17 PM PDT 24 Jun 05 05:33:36 PM PDT 24 6882037869 ps
T77 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1963589342 Jun 05 05:34:08 PM PDT 24 Jun 05 05:35:29 PM PDT 24 3598014786 ps
T366 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4080823091 Jun 05 05:34:00 PM PDT 24 Jun 05 05:34:29 PM PDT 24 13804309044 ps
T78 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3284072154 Jun 05 05:34:15 PM PDT 24 Jun 05 05:34:24 PM PDT 24 1270121493 ps
T367 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.925580340 Jun 05 05:33:38 PM PDT 24 Jun 05 05:33:47 PM PDT 24 687818425 ps
T368 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1271803332 Jun 05 05:34:23 PM PDT 24 Jun 05 05:34:59 PM PDT 24 3926571097 ps
T369 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3379143596 Jun 05 05:34:22 PM PDT 24 Jun 05 05:34:56 PM PDT 24 3602628262 ps
T370 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.831445059 Jun 05 05:33:07 PM PDT 24 Jun 05 05:33:32 PM PDT 24 2746888419 ps
T110 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1027359594 Jun 05 05:32:59 PM PDT 24 Jun 05 05:33:31 PM PDT 24 16396968422 ps
T79 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3319135767 Jun 05 05:34:07 PM PDT 24 Jun 05 05:34:30 PM PDT 24 33040285599 ps
T105 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4022502367 Jun 05 05:34:01 PM PDT 24 Jun 05 05:34:13 PM PDT 24 801965662 ps
T80 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.157727221 Jun 05 05:33:47 PM PDT 24 Jun 05 05:35:52 PM PDT 24 15913943585 ps
T106 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2432506888 Jun 05 05:34:07 PM PDT 24 Jun 05 05:34:16 PM PDT 24 662071980 ps
T81 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1531811484 Jun 05 05:33:38 PM PDT 24 Jun 05 05:33:51 PM PDT 24 184307690 ps
T82 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3013696767 Jun 05 05:34:15 PM PDT 24 Jun 05 05:34:46 PM PDT 24 7860039031 ps
T371 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3538043705 Jun 05 05:33:02 PM PDT 24 Jun 05 05:33:32 PM PDT 24 9377788206 ps
T372 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3845909162 Jun 05 05:34:29 PM PDT 24 Jun 05 05:34:58 PM PDT 24 14172729690 ps
T373 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1558681239 Jun 05 05:34:14 PM PDT 24 Jun 05 05:34:37 PM PDT 24 10472796800 ps
T374 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.884983984 Jun 05 05:33:33 PM PDT 24 Jun 05 05:33:49 PM PDT 24 1941674536 ps
T107 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2732435594 Jun 05 05:34:24 PM PDT 24 Jun 05 05:34:42 PM PDT 24 2864004408 ps
T83 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3245269359 Jun 05 05:33:24 PM PDT 24 Jun 05 05:33:33 PM PDT 24 176423546 ps
T375 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2536645965 Jun 05 05:32:55 PM PDT 24 Jun 05 05:33:19 PM PDT 24 7918633721 ps
T376 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.367733565 Jun 05 05:33:31 PM PDT 24 Jun 05 05:33:40 PM PDT 24 3294724423 ps
T377 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1755338553 Jun 05 05:34:06 PM PDT 24 Jun 05 05:34:40 PM PDT 24 22268778713 ps
T378 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.37426333 Jun 05 05:33:24 PM PDT 24 Jun 05 05:33:33 PM PDT 24 2747569683 ps
T64 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3144196097 Jun 05 05:33:32 PM PDT 24 Jun 05 05:35:12 PM PDT 24 15195496887 ps
T65 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3876941975 Jun 05 05:34:22 PM PDT 24 Jun 05 05:36:55 PM PDT 24 1911912890 ps
T84 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2641374137 Jun 05 05:34:24 PM PDT 24 Jun 05 05:35:36 PM PDT 24 10414285447 ps
T92 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3217248326 Jun 05 05:34:15 PM PDT 24 Jun 05 05:35:12 PM PDT 24 2136187564 ps
T114 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1252070011 Jun 05 05:33:17 PM PDT 24 Jun 05 05:36:04 PM PDT 24 11982536342 ps
T379 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.556428480 Jun 05 05:34:13 PM PDT 24 Jun 05 05:34:35 PM PDT 24 2438782322 ps
T380 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3918784315 Jun 05 05:33:45 PM PDT 24 Jun 05 05:34:19 PM PDT 24 25122024749 ps
T124 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3460960616 Jun 05 05:34:16 PM PDT 24 Jun 05 05:35:37 PM PDT 24 791030091 ps
T93 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.319186356 Jun 05 05:34:01 PM PDT 24 Jun 05 05:34:59 PM PDT 24 3022785600 ps
T94 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.503729774 Jun 05 05:33:31 PM PDT 24 Jun 05 05:35:15 PM PDT 24 67580743302 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2146925510 Jun 05 05:33:08 PM PDT 24 Jun 05 05:33:24 PM PDT 24 847159152 ps
T117 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2023024453 Jun 05 05:34:22 PM PDT 24 Jun 05 05:37:13 PM PDT 24 15159313255 ps
T382 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3827223257 Jun 05 05:33:07 PM PDT 24 Jun 05 05:33:39 PM PDT 24 8743946416 ps
T383 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2879646224 Jun 05 05:33:31 PM PDT 24 Jun 05 05:33:45 PM PDT 24 1378607938 ps
T95 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3722056868 Jun 05 05:34:00 PM PDT 24 Jun 05 05:34:22 PM PDT 24 2299983828 ps
T384 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3775226111 Jun 05 05:34:00 PM PDT 24 Jun 05 05:34:33 PM PDT 24 10039471828 ps
T385 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4104325184 Jun 05 05:33:53 PM PDT 24 Jun 05 05:34:05 PM PDT 24 1828877079 ps
T386 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1355125726 Jun 05 05:33:32 PM PDT 24 Jun 05 05:33:52 PM PDT 24 1849012960 ps
T387 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1439447721 Jun 05 05:33:45 PM PDT 24 Jun 05 05:34:14 PM PDT 24 35504480802 ps
T388 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.332194557 Jun 05 05:33:53 PM PDT 24 Jun 05 05:35:03 PM PDT 24 19713585448 ps
T389 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1069083728 Jun 05 05:34:00 PM PDT 24 Jun 05 05:34:13 PM PDT 24 521579643 ps
T96 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1605342223 Jun 05 05:33:09 PM PDT 24 Jun 05 05:33:46 PM PDT 24 2842250835 ps
T97 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.817414104 Jun 05 05:33:30 PM PDT 24 Jun 05 05:33:39 PM PDT 24 687878633 ps
T390 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1905711816 Jun 05 05:33:26 PM PDT 24 Jun 05 05:33:44 PM PDT 24 5604877162 ps
T98 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2865145280 Jun 05 05:32:53 PM PDT 24 Jun 05 05:33:51 PM PDT 24 11947476491 ps
T391 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.52020680 Jun 05 05:34:25 PM PDT 24 Jun 05 05:34:43 PM PDT 24 1611785233 ps
T102 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3095895661 Jun 05 05:33:03 PM PDT 24 Jun 05 05:34:25 PM PDT 24 32991968682 ps
T392 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1728721497 Jun 05 05:34:25 PM PDT 24 Jun 05 05:34:53 PM PDT 24 3559774100 ps
T393 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.767632575 Jun 05 05:34:23 PM PDT 24 Jun 05 05:34:54 PM PDT 24 4275264695 ps
T394 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.669177336 Jun 05 05:33:52 PM PDT 24 Jun 05 05:34:02 PM PDT 24 372906308 ps
T395 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1476198615 Jun 05 05:33:46 PM PDT 24 Jun 05 05:35:41 PM PDT 24 10110221656 ps
T396 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1145067162 Jun 05 05:34:16 PM PDT 24 Jun 05 05:34:31 PM PDT 24 985733304 ps
T115 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2037084222 Jun 05 05:32:55 PM PDT 24 Jun 05 05:34:27 PM PDT 24 2210157693 ps
T397 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1717886951 Jun 05 05:33:09 PM PDT 24 Jun 05 05:33:37 PM PDT 24 27445318210 ps
T398 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.143874425 Jun 05 05:33:40 PM PDT 24 Jun 05 05:34:03 PM PDT 24 6284260899 ps
T399 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1368903265 Jun 05 05:33:08 PM PDT 24 Jun 05 05:33:22 PM PDT 24 177816442 ps
T119 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2591477379 Jun 05 05:34:24 PM PDT 24 Jun 05 05:35:46 PM PDT 24 1177970107 ps
T400 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1605498788 Jun 05 05:34:01 PM PDT 24 Jun 05 05:34:23 PM PDT 24 5272534471 ps
T401 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.56628185 Jun 05 05:33:59 PM PDT 24 Jun 05 05:36:51 PM PDT 24 158616810718 ps
T402 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2097899534 Jun 05 05:34:23 PM PDT 24 Jun 05 05:34:45 PM PDT 24 2125313873 ps
T103 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3994404705 Jun 05 05:33:26 PM PDT 24 Jun 05 05:33:40 PM PDT 24 3162539125 ps
T403 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1065551508 Jun 05 05:33:24 PM PDT 24 Jun 05 05:33:43 PM PDT 24 1835647004 ps
T404 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1967472961 Jun 05 05:33:38 PM PDT 24 Jun 05 05:34:03 PM PDT 24 33910990981 ps
T116 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4244372998 Jun 05 05:33:37 PM PDT 24 Jun 05 05:36:24 PM PDT 24 11912859417 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3947573123 Jun 05 05:33:18 PM PDT 24 Jun 05 05:35:05 PM PDT 24 17091843728 ps
T406 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1983302478 Jun 05 05:33:01 PM PDT 24 Jun 05 05:33:22 PM PDT 24 2001984565 ps
T407 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3884850883 Jun 05 05:34:01 PM PDT 24 Jun 05 05:34:34 PM PDT 24 17267303620 ps
T408 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3758884095 Jun 05 05:33:31 PM PDT 24 Jun 05 05:33:48 PM PDT 24 2566171144 ps
T409 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.483276470 Jun 05 05:33:09 PM PDT 24 Jun 05 05:33:43 PM PDT 24 53372477686 ps
T99 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3117883172 Jun 05 05:33:07 PM PDT 24 Jun 05 05:33:39 PM PDT 24 12962057454 ps
T410 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.347420823 Jun 05 05:34:06 PM PDT 24 Jun 05 05:35:46 PM PDT 24 10518449360 ps
T411 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3977968291 Jun 05 05:33:03 PM PDT 24 Jun 05 05:33:24 PM PDT 24 4240913199 ps
T101 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1889008215 Jun 05 05:33:08 PM PDT 24 Jun 05 05:33:30 PM PDT 24 2983959728 ps
T122 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.697727729 Jun 05 05:34:00 PM PDT 24 Jun 05 05:36:41 PM PDT 24 11129272419 ps
T412 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.96338446 Jun 05 05:32:54 PM PDT 24 Jun 05 05:33:04 PM PDT 24 1451169877 ps
T413 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1431291995 Jun 05 05:34:07 PM PDT 24 Jun 05 05:37:02 PM PDT 24 62715905810 ps
T113 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.104035852 Jun 05 05:33:37 PM PDT 24 Jun 05 05:34:56 PM PDT 24 26406994812 ps
T414 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1185231686 Jun 05 05:34:21 PM PDT 24 Jun 05 05:34:50 PM PDT 24 6996006020 ps
T415 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1199730943 Jun 05 05:34:07 PM PDT 24 Jun 05 05:34:28 PM PDT 24 2056510517 ps
T118 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2819422966 Jun 05 05:33:52 PM PDT 24 Jun 05 05:35:33 PM PDT 24 17125534267 ps
T416 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2199415951 Jun 05 05:34:26 PM PDT 24 Jun 05 05:34:39 PM PDT 24 2014465397 ps
T417 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3260568357 Jun 05 05:33:28 PM PDT 24 Jun 05 05:34:42 PM PDT 24 23316917924 ps
T418 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2097004460 Jun 05 05:32:54 PM PDT 24 Jun 05 05:33:15 PM PDT 24 8837219126 ps
T419 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2988100948 Jun 05 05:34:22 PM PDT 24 Jun 05 05:36:26 PM PDT 24 61772364176 ps
T420 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1845910115 Jun 05 05:34:16 PM PDT 24 Jun 05 05:37:08 PM PDT 24 13628848847 ps
T421 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1445108829 Jun 05 05:34:30 PM PDT 24 Jun 05 05:34:49 PM PDT 24 994313182 ps
T422 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2374986113 Jun 05 05:34:15 PM PDT 24 Jun 05 05:35:30 PM PDT 24 47938288766 ps
T423 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1932139527 Jun 05 05:34:24 PM PDT 24 Jun 05 05:34:38 PM PDT 24 9562016614 ps
T424 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1388012968 Jun 05 05:34:15 PM PDT 24 Jun 05 05:34:53 PM PDT 24 2741382678 ps
T425 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3237593604 Jun 05 05:34:16 PM PDT 24 Jun 05 05:34:39 PM PDT 24 2631371123 ps
T426 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2102585662 Jun 05 05:34:06 PM PDT 24 Jun 05 05:34:18 PM PDT 24 1179499621 ps
T427 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2775974685 Jun 05 05:33:08 PM PDT 24 Jun 05 05:33:21 PM PDT 24 2397036069 ps
T428 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2224614593 Jun 05 05:33:47 PM PDT 24 Jun 05 05:34:14 PM PDT 24 6430783016 ps
T429 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3927885063 Jun 05 05:33:08 PM PDT 24 Jun 05 05:33:34 PM PDT 24 2988927666 ps
T430 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2124795516 Jun 05 05:33:55 PM PDT 24 Jun 05 05:34:29 PM PDT 24 3854708242 ps
T431 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.584390778 Jun 05 05:33:44 PM PDT 24 Jun 05 05:34:09 PM PDT 24 8475337478 ps
T123 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.373247391 Jun 05 05:34:02 PM PDT 24 Jun 05 05:35:39 PM PDT 24 3358481609 ps
T432 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3693019788 Jun 05 05:33:52 PM PDT 24 Jun 05 05:34:00 PM PDT 24 346279400 ps
T433 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3634556585 Jun 05 05:33:01 PM PDT 24 Jun 05 05:33:29 PM PDT 24 6739020805 ps
T104 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1031078226 Jun 05 05:34:16 PM PDT 24 Jun 05 05:34:39 PM PDT 24 2664230575 ps
T434 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.511842688 Jun 05 05:34:07 PM PDT 24 Jun 05 05:34:18 PM PDT 24 537883583 ps
T435 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2569128018 Jun 05 05:33:06 PM PDT 24 Jun 05 05:33:23 PM PDT 24 1275784874 ps
T436 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3952453415 Jun 05 05:32:55 PM PDT 24 Jun 05 05:33:29 PM PDT 24 16364722829 ps
T437 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.225651963 Jun 05 05:33:01 PM PDT 24 Jun 05 05:33:35 PM PDT 24 10585435617 ps
T100 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2961672249 Jun 05 05:33:07 PM PDT 24 Jun 05 05:33:37 PM PDT 24 3748763642 ps
T438 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2893744636 Jun 05 05:33:01 PM PDT 24 Jun 05 05:33:13 PM PDT 24 692807608 ps
T439 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.652787270 Jun 05 05:34:23 PM PDT 24 Jun 05 05:34:53 PM PDT 24 3825587473 ps
T440 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3753986630 Jun 05 05:34:17 PM PDT 24 Jun 05 05:34:43 PM PDT 24 8936086628 ps
T441 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.396214571 Jun 05 05:33:01 PM PDT 24 Jun 05 05:33:25 PM PDT 24 18996757880 ps
T120 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1007717760 Jun 05 05:34:21 PM PDT 24 Jun 05 05:37:17 PM PDT 24 4056274352 ps
T442 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4040641424 Jun 05 05:33:24 PM PDT 24 Jun 05 05:33:43 PM PDT 24 676799522 ps
T443 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2473952728 Jun 05 05:34:07 PM PDT 24 Jun 05 05:36:41 PM PDT 24 1959940616 ps
T444 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1164784246 Jun 05 05:33:31 PM PDT 24 Jun 05 05:33:54 PM PDT 24 9192392314 ps
T445 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.46492726 Jun 05 05:33:00 PM PDT 24 Jun 05 05:33:31 PM PDT 24 52919037925 ps
T446 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3448839296 Jun 05 05:34:25 PM PDT 24 Jun 05 05:34:54 PM PDT 24 3089271412 ps
T447 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.228717744 Jun 05 05:33:32 PM PDT 24 Jun 05 05:34:07 PM PDT 24 15413248848 ps
T448 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2289697365 Jun 05 05:34:08 PM PDT 24 Jun 05 05:34:20 PM PDT 24 332085591 ps
T449 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3247430023 Jun 05 05:33:45 PM PDT 24 Jun 05 05:35:27 PM PDT 24 8278248437 ps
T450 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2568468879 Jun 05 05:33:52 PM PDT 24 Jun 05 05:34:20 PM PDT 24 17402800567 ps
T451 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1942811776 Jun 05 05:33:18 PM PDT 24 Jun 05 05:33:30 PM PDT 24 636355822 ps
T452 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2507321649 Jun 05 05:34:00 PM PDT 24 Jun 05 05:34:09 PM PDT 24 174337127 ps
T453 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2229041863 Jun 05 05:34:06 PM PDT 24 Jun 05 05:34:29 PM PDT 24 2368501504 ps
T121 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2213935582 Jun 05 05:33:53 PM PDT 24 Jun 05 05:35:32 PM PDT 24 3135322196 ps
T454 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1364160393 Jun 05 05:33:26 PM PDT 24 Jun 05 05:34:46 PM PDT 24 507452991 ps
T455 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3184745585 Jun 05 05:33:03 PM PDT 24 Jun 05 05:34:37 PM PDT 24 5171778736 ps

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.821993405
Short name T3
Test name
Test status
Simulation time 178695340279 ps
CPU time 914.96 seconds
Started Jun 05 05:16:38 PM PDT 24
Finished Jun 05 05:31:54 PM PDT 24
Peak memory 240664 kb
Host smart-3e871dfb-5d88-4fb0-bf73-d0b01a185ade
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821993405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.821993405
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1835684697
Short name T21
Test name
Test status
Simulation time 217002956259 ps
CPU time 2056.98 seconds
Started Jun 05 05:16:40 PM PDT 24
Finished Jun 05 05:50:57 PM PDT 24
Peak memory 240208 kb
Host smart-e1cb22ce-e4c1-4ec7-a3f7-fd6651be4b15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835684697 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1835684697
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3997722415
Short name T6
Test name
Test status
Simulation time 2788952538 ps
CPU time 25.63 seconds
Started Jun 05 05:16:01 PM PDT 24
Finished Jun 05 05:16:27 PM PDT 24
Peak memory 211320 kb
Host smart-55c203ca-a67d-488b-a302-8e68f98b4136
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3997722415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3997722415
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3612412626
Short name T18
Test name
Test status
Simulation time 24941570602 ps
CPU time 54.5 seconds
Started Jun 05 05:16:26 PM PDT 24
Finished Jun 05 05:17:22 PM PDT 24
Peak memory 217288 kb
Host smart-b4d40c19-8ee1-4cbd-a38d-8ba14a910662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612412626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3612412626
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1219455992
Short name T28
Test name
Test status
Simulation time 8593333827 ps
CPU time 21.27 seconds
Started Jun 05 05:18:13 PM PDT 24
Finished Jun 05 05:18:35 PM PDT 24
Peak memory 211396 kb
Host smart-e68fdc26-ed70-4b04-8803-9ffcc17cd195
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219455992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1219455992
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3876941975
Short name T65
Test name
Test status
Simulation time 1911912890 ps
CPU time 153.31 seconds
Started Jun 05 05:34:22 PM PDT 24
Finished Jun 05 05:36:55 PM PDT 24
Peak memory 215096 kb
Host smart-4e6b2bce-4d82-4c8a-ba62-f0a16781231d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876941975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3876941975
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3270360286
Short name T15
Test name
Test status
Simulation time 4059663231 ps
CPU time 304.02 seconds
Started Jun 05 05:16:06 PM PDT 24
Finished Jun 05 05:21:10 PM PDT 24
Peak memory 225360 kb
Host smart-9e8da47a-725a-4dcf-8f98-8137e59068f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270360286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3270360286
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.584963615
Short name T87
Test name
Test status
Simulation time 23427855070 ps
CPU time 142.15 seconds
Started Jun 05 05:15:29 PM PDT 24
Finished Jun 05 05:17:52 PM PDT 24
Peak memory 220320 kb
Host smart-8fb72632-397d-4680-bda8-512114a460e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584963615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.584963615
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1963954346
Short name T66
Test name
Test status
Simulation time 8849052150 ps
CPU time 29.4 seconds
Started Jun 05 05:16:34 PM PDT 24
Finished Jun 05 05:17:04 PM PDT 24
Peak memory 212976 kb
Host smart-e89be9bf-9ef0-473e-abda-c43c3fcb8f8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963954346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1963954346
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1417406024
Short name T34
Test name
Test status
Simulation time 3687951763 ps
CPU time 247.55 seconds
Started Jun 05 05:15:28 PM PDT 24
Finished Jun 05 05:19:36 PM PDT 24
Peak memory 236608 kb
Host smart-44ad9c1f-6363-4242-a6f5-e6a32ec4cc22
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417406024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1417406024
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4244372998
Short name T116
Test name
Test status
Simulation time 11912859417 ps
CPU time 165.78 seconds
Started Jun 05 05:33:37 PM PDT 24
Finished Jun 05 05:36:24 PM PDT 24
Peak memory 214132 kb
Host smart-85ad85d0-9edb-4cf8-ad28-80c50d270d47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244372998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.4244372998
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1963589342
Short name T77
Test name
Test status
Simulation time 3598014786 ps
CPU time 79.82 seconds
Started Jun 05 05:34:08 PM PDT 24
Finished Jun 05 05:35:29 PM PDT 24
Peak memory 215660 kb
Host smart-ee6e2b1f-25bc-48c7-a1df-1a08c30f11e2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963589342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1963589342
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.22580137
Short name T10
Test name
Test status
Simulation time 3676687673 ps
CPU time 30.93 seconds
Started Jun 05 05:15:29 PM PDT 24
Finished Jun 05 05:16:01 PM PDT 24
Peak memory 215052 kb
Host smart-5c89cd0e-790f-4a80-8c7c-d238b3ca15eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22580137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.22580137
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3330607631
Short name T268
Test name
Test status
Simulation time 332413490 ps
CPU time 19.35 seconds
Started Jun 05 05:15:57 PM PDT 24
Finished Jun 05 05:16:17 PM PDT 24
Peak memory 214532 kb
Host smart-2ed603e5-4c15-4233-bf23-9e74deb49542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330607631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3330607631
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.223636804
Short name T63
Test name
Test status
Simulation time 603562869 ps
CPU time 152.83 seconds
Started Jun 05 05:33:08 PM PDT 24
Finished Jun 05 05:35:41 PM PDT 24
Peak memory 214076 kb
Host smart-790407d4-445f-43f3-9562-b288ceaa817c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223636804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.223636804
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3683848947
Short name T88
Test name
Test status
Simulation time 2756517633 ps
CPU time 44.03 seconds
Started Jun 05 05:16:09 PM PDT 24
Finished Jun 05 05:16:54 PM PDT 24
Peak memory 219288 kb
Host smart-abb28c0f-1d01-4419-9b66-8a3321e6995e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683848947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3683848947
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2961672249
Short name T100
Test name
Test status
Simulation time 3748763642 ps
CPU time 29.94 seconds
Started Jun 05 05:33:07 PM PDT 24
Finished Jun 05 05:33:37 PM PDT 24
Peak memory 211512 kb
Host smart-c9c428ce-a4b2-4725-b7eb-cac103e598bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961672249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2961672249
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2037084222
Short name T115
Test name
Test status
Simulation time 2210157693 ps
CPU time 91.65 seconds
Started Jun 05 05:32:55 PM PDT 24
Finished Jun 05 05:34:27 PM PDT 24
Peak memory 213800 kb
Host smart-0bdebad0-88f3-4eaa-9534-764f6f341946
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037084222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2037084222
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3095895661
Short name T102
Test name
Test status
Simulation time 32991968682 ps
CPU time 81.56 seconds
Started Jun 05 05:33:03 PM PDT 24
Finished Jun 05 05:34:25 PM PDT 24
Peak memory 213812 kb
Host smart-cbac1b22-c389-4d91-b3a7-afbc86fb50a7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095895661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3095895661
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3634556585
Short name T433
Test name
Test status
Simulation time 6739020805 ps
CPU time 27.79 seconds
Started Jun 05 05:33:01 PM PDT 24
Finished Jun 05 05:33:29 PM PDT 24
Peak memory 211832 kb
Host smart-07757f5f-5560-47d0-ba8e-148e2b1aa9d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634556585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3634556585
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1027359594
Short name T110
Test name
Test status
Simulation time 16396968422 ps
CPU time 31.55 seconds
Started Jun 05 05:32:59 PM PDT 24
Finished Jun 05 05:33:31 PM PDT 24
Peak memory 219556 kb
Host smart-40f0a526-6821-4ba9-9748-da806de451ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027359594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1027359594
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2536645965
Short name T375
Test name
Test status
Simulation time 7918633721 ps
CPU time 23.8 seconds
Started Jun 05 05:32:55 PM PDT 24
Finished Jun 05 05:33:19 PM PDT 24
Peak memory 212448 kb
Host smart-949c4e53-5a3c-40c1-ada0-3e17cad743d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536645965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2536645965
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1983302478
Short name T406
Test name
Test status
Simulation time 2001984565 ps
CPU time 20.05 seconds
Started Jun 05 05:33:01 PM PDT 24
Finished Jun 05 05:33:22 PM PDT 24
Peak memory 217200 kb
Host smart-20eed6fa-9a7b-4fca-b364-8b59040a91dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983302478 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1983302478
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.396214571
Short name T441
Test name
Test status
Simulation time 18996757880 ps
CPU time 23.18 seconds
Started Jun 05 05:33:01 PM PDT 24
Finished Jun 05 05:33:25 PM PDT 24
Peak memory 212532 kb
Host smart-c8b801a4-a2fe-4d13-9e81-32ce3eff621a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396214571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.396214571
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2097004460
Short name T418
Test name
Test status
Simulation time 8837219126 ps
CPU time 20.67 seconds
Started Jun 05 05:32:54 PM PDT 24
Finished Jun 05 05:33:15 PM PDT 24
Peak memory 211264 kb
Host smart-a462290b-7f1c-41ba-b21a-086d435e3d79
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097004460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2097004460
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.96338446
Short name T412
Test name
Test status
Simulation time 1451169877 ps
CPU time 9.56 seconds
Started Jun 05 05:32:54 PM PDT 24
Finished Jun 05 05:33:04 PM PDT 24
Peak memory 211272 kb
Host smart-0ef4611b-db29-4e6b-a4a1-996bb81ea62f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96338446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.96338446
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2865145280
Short name T98
Test name
Test status
Simulation time 11947476491 ps
CPU time 57.22 seconds
Started Jun 05 05:32:53 PM PDT 24
Finished Jun 05 05:33:51 PM PDT 24
Peak memory 214408 kb
Host smart-81629d70-5000-4253-928a-5ad481ebfe71
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865145280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2865145280
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.225651963
Short name T437
Test name
Test status
Simulation time 10585435617 ps
CPU time 33.73 seconds
Started Jun 05 05:33:01 PM PDT 24
Finished Jun 05 05:33:35 PM PDT 24
Peak memory 212884 kb
Host smart-b1ea7344-2b89-499c-bff4-99098137556d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225651963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.225651963
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3952453415
Short name T436
Test name
Test status
Simulation time 16364722829 ps
CPU time 33.63 seconds
Started Jun 05 05:32:55 PM PDT 24
Finished Jun 05 05:33:29 PM PDT 24
Peak memory 218832 kb
Host smart-e64e1360-55c8-41ba-914b-dcf0e8c2a83d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952453415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3952453415
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3117883172
Short name T99
Test name
Test status
Simulation time 12962057454 ps
CPU time 30.65 seconds
Started Jun 05 05:33:07 PM PDT 24
Finished Jun 05 05:33:39 PM PDT 24
Peak memory 212320 kb
Host smart-9009ad74-7984-4ab0-801d-ac5568149a10
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117883172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3117883172
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3927885063
Short name T429
Test name
Test status
Simulation time 2988927666 ps
CPU time 25.5 seconds
Started Jun 05 05:33:08 PM PDT 24
Finished Jun 05 05:33:34 PM PDT 24
Peak memory 219560 kb
Host smart-34bd6f99-0099-4c09-a819-2e20eaedb32a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927885063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3927885063
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2893744636
Short name T438
Test name
Test status
Simulation time 692807608 ps
CPU time 11.68 seconds
Started Jun 05 05:33:01 PM PDT 24
Finished Jun 05 05:33:13 PM PDT 24
Peak memory 211292 kb
Host smart-8446c432-b824-4e09-a44c-08684843abbc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893744636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2893744636
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.831445059
Short name T370
Test name
Test status
Simulation time 2746888419 ps
CPU time 24.56 seconds
Started Jun 05 05:33:07 PM PDT 24
Finished Jun 05 05:33:32 PM PDT 24
Peak memory 216736 kb
Host smart-5b3ca05f-460b-4d86-9266-6a472fbc60a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831445059 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.831445059
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3538043705
Short name T371
Test name
Test status
Simulation time 9377788206 ps
CPU time 29.76 seconds
Started Jun 05 05:33:02 PM PDT 24
Finished Jun 05 05:33:32 PM PDT 24
Peak memory 211232 kb
Host smart-46cbb5aa-e450-41a7-8775-8d2ad883f71f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538043705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3538043705
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3977968291
Short name T411
Test name
Test status
Simulation time 4240913199 ps
CPU time 20.26 seconds
Started Jun 05 05:33:03 PM PDT 24
Finished Jun 05 05:33:24 PM PDT 24
Peak memory 211324 kb
Host smart-62d424b5-60bd-4529-a1d9-26330c35ebb6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977968291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3977968291
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1023138487
Short name T67
Test name
Test status
Simulation time 8899613303 ps
CPU time 24.54 seconds
Started Jun 05 05:33:09 PM PDT 24
Finished Jun 05 05:33:34 PM PDT 24
Peak memory 212800 kb
Host smart-7350419c-adb4-4c24-9ff6-ed984e3e26d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023138487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1023138487
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.46492726
Short name T445
Test name
Test status
Simulation time 52919037925 ps
CPU time 30.52 seconds
Started Jun 05 05:33:00 PM PDT 24
Finished Jun 05 05:33:31 PM PDT 24
Peak memory 218924 kb
Host smart-2f13595b-697f-4a18-8b27-128d96c9530f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46492726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.46492726
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3184745585
Short name T455
Test name
Test status
Simulation time 5171778736 ps
CPU time 93.62 seconds
Started Jun 05 05:33:03 PM PDT 24
Finished Jun 05 05:34:37 PM PDT 24
Peak memory 213840 kb
Host smart-f1e43890-126d-4d12-9625-f2d0e3d66c45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184745585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3184745585
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3884850883
Short name T407
Test name
Test status
Simulation time 17267303620 ps
CPU time 32.82 seconds
Started Jun 05 05:34:01 PM PDT 24
Finished Jun 05 05:34:34 PM PDT 24
Peak memory 217124 kb
Host smart-4b9d48ec-df96-4724-8e80-4bc2169cfa6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884850883 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3884850883
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2507321649
Short name T452
Test name
Test status
Simulation time 174337127 ps
CPU time 8.04 seconds
Started Jun 05 05:34:00 PM PDT 24
Finished Jun 05 05:34:09 PM PDT 24
Peak memory 211288 kb
Host smart-c0a3e170-3fbd-41fd-89db-d29fe4998b63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507321649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2507321649
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.56628185
Short name T401
Test name
Test status
Simulation time 158616810718 ps
CPU time 171.41 seconds
Started Jun 05 05:33:59 PM PDT 24
Finished Jun 05 05:36:51 PM PDT 24
Peak memory 215284 kb
Host smart-32ac2d2d-0f6b-4f71-9b5e-3c7d3b01b0f0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56628185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pas
sthru_mem_tl_intg_err.56628185
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1069083728
Short name T389
Test name
Test status
Simulation time 521579643 ps
CPU time 12 seconds
Started Jun 05 05:34:00 PM PDT 24
Finished Jun 05 05:34:13 PM PDT 24
Peak memory 211388 kb
Host smart-c4e27e9b-8724-4eeb-ad28-0120c360f829
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069083728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1069083728
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4080823091
Short name T366
Test name
Test status
Simulation time 13804309044 ps
CPU time 29.5 seconds
Started Jun 05 05:34:00 PM PDT 24
Finished Jun 05 05:34:29 PM PDT 24
Peak memory 219636 kb
Host smart-d4794fc6-ddab-4ede-b7ff-199217fca988
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080823091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.4080823091
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.697727729
Short name T122
Test name
Test status
Simulation time 11129272419 ps
CPU time 160.82 seconds
Started Jun 05 05:34:00 PM PDT 24
Finished Jun 05 05:36:41 PM PDT 24
Peak memory 214140 kb
Host smart-045e74a3-751f-4b31-abb7-25c7f71c540b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697727729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.697727729
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.511842688
Short name T434
Test name
Test status
Simulation time 537883583 ps
CPU time 10.2 seconds
Started Jun 05 05:34:07 PM PDT 24
Finished Jun 05 05:34:18 PM PDT 24
Peak memory 216380 kb
Host smart-8d94b966-dce5-4dee-acd8-49fd668ff75d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511842688 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.511842688
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3722056868
Short name T95
Test name
Test status
Simulation time 2299983828 ps
CPU time 21.59 seconds
Started Jun 05 05:34:00 PM PDT 24
Finished Jun 05 05:34:22 PM PDT 24
Peak memory 211440 kb
Host smart-0e985443-136f-4f05-aad6-cda1fcfc54be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722056868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3722056868
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.319186356
Short name T93
Test name
Test status
Simulation time 3022785600 ps
CPU time 56.84 seconds
Started Jun 05 05:34:01 PM PDT 24
Finished Jun 05 05:34:59 PM PDT 24
Peak memory 214764 kb
Host smart-e87cd19e-dd53-447b-935f-ce9fac2d838b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319186356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.319186356
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3319135767
Short name T79
Test name
Test status
Simulation time 33040285599 ps
CPU time 22.72 seconds
Started Jun 05 05:34:07 PM PDT 24
Finished Jun 05 05:34:30 PM PDT 24
Peak memory 212804 kb
Host smart-ae18b9d8-9cac-4db1-8b88-371d81091947
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319135767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3319135767
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3655134007
Short name T364
Test name
Test status
Simulation time 11084459090 ps
CPU time 29.27 seconds
Started Jun 05 05:33:59 PM PDT 24
Finished Jun 05 05:34:29 PM PDT 24
Peak memory 216848 kb
Host smart-13102437-00d6-4014-aa6b-f106fa33e028
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655134007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3655134007
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.373247391
Short name T123
Test name
Test status
Simulation time 3358481609 ps
CPU time 97.23 seconds
Started Jun 05 05:34:02 PM PDT 24
Finished Jun 05 05:35:39 PM PDT 24
Peak memory 213400 kb
Host smart-278bca3b-5e14-4710-a966-ebfae646b731
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373247391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.373247391
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2229041863
Short name T453
Test name
Test status
Simulation time 2368501504 ps
CPU time 22.55 seconds
Started Jun 05 05:34:06 PM PDT 24
Finished Jun 05 05:34:29 PM PDT 24
Peak memory 215160 kb
Host smart-df50a3ce-37b1-43b6-81ac-d400c3e92606
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229041863 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2229041863
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1199730943
Short name T415
Test name
Test status
Simulation time 2056510517 ps
CPU time 20.52 seconds
Started Jun 05 05:34:07 PM PDT 24
Finished Jun 05 05:34:28 PM PDT 24
Peak memory 211992 kb
Host smart-224de78f-4231-44bf-ac63-a098e1e5c8f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199730943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1199730943
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2432506888
Short name T106
Test name
Test status
Simulation time 662071980 ps
CPU time 8.37 seconds
Started Jun 05 05:34:07 PM PDT 24
Finished Jun 05 05:34:16 PM PDT 24
Peak memory 211652 kb
Host smart-25296add-2769-4ec6-b2b5-2a144998e608
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432506888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2432506888
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2102585662
Short name T426
Test name
Test status
Simulation time 1179499621 ps
CPU time 10.98 seconds
Started Jun 05 05:34:06 PM PDT 24
Finished Jun 05 05:34:18 PM PDT 24
Peak memory 217060 kb
Host smart-ed77241d-4446-49f6-b372-36e3c8450377
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102585662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2102585662
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1431291995
Short name T413
Test name
Test status
Simulation time 62715905810 ps
CPU time 174.35 seconds
Started Jun 05 05:34:07 PM PDT 24
Finished Jun 05 05:37:02 PM PDT 24
Peak memory 214424 kb
Host smart-1ce0372e-8aaa-4244-8dce-ae971e6d66cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431291995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1431291995
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.556428480
Short name T379
Test name
Test status
Simulation time 2438782322 ps
CPU time 22.39 seconds
Started Jun 05 05:34:13 PM PDT 24
Finished Jun 05 05:34:35 PM PDT 24
Peak memory 218468 kb
Host smart-de0faeae-abb9-4870-ac71-875e1bf46c35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556428480 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.556428480
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1755338553
Short name T377
Test name
Test status
Simulation time 22268778713 ps
CPU time 32.83 seconds
Started Jun 05 05:34:06 PM PDT 24
Finished Jun 05 05:34:40 PM PDT 24
Peak memory 212380 kb
Host smart-988d7448-24ba-47ee-83de-0f995b0f55e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755338553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1755338553
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.347420823
Short name T410
Test name
Test status
Simulation time 10518449360 ps
CPU time 98.77 seconds
Started Jun 05 05:34:06 PM PDT 24
Finished Jun 05 05:35:46 PM PDT 24
Peak memory 214476 kb
Host smart-abc4dbc1-30e7-487f-9264-97a6bcee1ec7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347420823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.347420823
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3013696767
Short name T82
Test name
Test status
Simulation time 7860039031 ps
CPU time 31.06 seconds
Started Jun 05 05:34:15 PM PDT 24
Finished Jun 05 05:34:46 PM PDT 24
Peak memory 212556 kb
Host smart-1853517a-eaa1-4146-95de-689b79eacdb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013696767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3013696767
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2289697365
Short name T448
Test name
Test status
Simulation time 332085591 ps
CPU time 11.63 seconds
Started Jun 05 05:34:08 PM PDT 24
Finished Jun 05 05:34:20 PM PDT 24
Peak memory 217532 kb
Host smart-5e46373b-b845-4241-8cb6-e3ae9ae717ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289697365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2289697365
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2473952728
Short name T443
Test name
Test status
Simulation time 1959940616 ps
CPU time 153.73 seconds
Started Jun 05 05:34:07 PM PDT 24
Finished Jun 05 05:36:41 PM PDT 24
Peak memory 214092 kb
Host smart-de89c219-a3bc-4e0d-b333-84c796158efd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473952728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2473952728
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.650977116
Short name T362
Test name
Test status
Simulation time 38069342341 ps
CPU time 28.22 seconds
Started Jun 05 05:34:15 PM PDT 24
Finished Jun 05 05:34:44 PM PDT 24
Peak memory 215044 kb
Host smart-b3d3fe6f-e896-4e40-a634-13019a584dc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650977116 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.650977116
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1031078226
Short name T104
Test name
Test status
Simulation time 2664230575 ps
CPU time 23.19 seconds
Started Jun 05 05:34:16 PM PDT 24
Finished Jun 05 05:34:39 PM PDT 24
Peak memory 211664 kb
Host smart-5e780746-1a29-4394-b273-5fae73c1a17e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031078226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1031078226
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1388012968
Short name T424
Test name
Test status
Simulation time 2741382678 ps
CPU time 37.32 seconds
Started Jun 05 05:34:15 PM PDT 24
Finished Jun 05 05:34:53 PM PDT 24
Peak memory 213432 kb
Host smart-f0c08eb8-c959-4a6e-a24e-14be84ab1f31
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388012968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1388012968
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3284072154
Short name T78
Test name
Test status
Simulation time 1270121493 ps
CPU time 8.25 seconds
Started Jun 05 05:34:15 PM PDT 24
Finished Jun 05 05:34:24 PM PDT 24
Peak memory 211276 kb
Host smart-ec401557-5109-46d8-8a32-9c38c37eacc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284072154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3284072154
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1558681239
Short name T373
Test name
Test status
Simulation time 10472796800 ps
CPU time 22.67 seconds
Started Jun 05 05:34:14 PM PDT 24
Finished Jun 05 05:34:37 PM PDT 24
Peak memory 217668 kb
Host smart-0b47d17e-3099-4019-ac69-12a8a23689b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558681239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1558681239
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1845910115
Short name T420
Test name
Test status
Simulation time 13628848847 ps
CPU time 171.67 seconds
Started Jun 05 05:34:16 PM PDT 24
Finished Jun 05 05:37:08 PM PDT 24
Peak memory 214248 kb
Host smart-c02adcb4-47a2-44df-bee9-ca6407a38a61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845910115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1845910115
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1376967083
Short name T363
Test name
Test status
Simulation time 1708466205 ps
CPU time 19.16 seconds
Started Jun 05 05:34:15 PM PDT 24
Finished Jun 05 05:34:35 PM PDT 24
Peak memory 217844 kb
Host smart-9ee85c6c-56c8-4ac9-9f7a-020185f9a774
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376967083 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1376967083
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3237593604
Short name T425
Test name
Test status
Simulation time 2631371123 ps
CPU time 22.48 seconds
Started Jun 05 05:34:16 PM PDT 24
Finished Jun 05 05:34:39 PM PDT 24
Peak memory 211352 kb
Host smart-384a8b35-c2ab-46f4-a76c-545c6d637158
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237593604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3237593604
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2374986113
Short name T422
Test name
Test status
Simulation time 47938288766 ps
CPU time 74.87 seconds
Started Jun 05 05:34:15 PM PDT 24
Finished Jun 05 05:35:30 PM PDT 24
Peak memory 214460 kb
Host smart-4b54ca58-3963-453f-8ee6-a20438ad9d97
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374986113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2374986113
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1145067162
Short name T396
Test name
Test status
Simulation time 985733304 ps
CPU time 15.14 seconds
Started Jun 05 05:34:16 PM PDT 24
Finished Jun 05 05:34:31 PM PDT 24
Peak memory 211328 kb
Host smart-c7f70f58-cb30-418e-b664-ffc4f2225980
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145067162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1145067162
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3753986630
Short name T440
Test name
Test status
Simulation time 8936086628 ps
CPU time 25.69 seconds
Started Jun 05 05:34:17 PM PDT 24
Finished Jun 05 05:34:43 PM PDT 24
Peak memory 219628 kb
Host smart-e31d3055-2f44-40c2-89ae-c0a4831c940c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753986630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3753986630
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3460960616
Short name T124
Test name
Test status
Simulation time 791030091 ps
CPU time 79.79 seconds
Started Jun 05 05:34:16 PM PDT 24
Finished Jun 05 05:35:37 PM PDT 24
Peak memory 213720 kb
Host smart-5aa272a1-12e6-41d4-897a-fc28f7078298
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460960616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3460960616
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2199415951
Short name T416
Test name
Test status
Simulation time 2014465397 ps
CPU time 12.2 seconds
Started Jun 05 05:34:26 PM PDT 24
Finished Jun 05 05:34:39 PM PDT 24
Peak memory 217504 kb
Host smart-8de99865-8bc5-450f-8170-1b5afca37afe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199415951 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2199415951
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.52020680
Short name T391
Test name
Test status
Simulation time 1611785233 ps
CPU time 17.55 seconds
Started Jun 05 05:34:25 PM PDT 24
Finished Jun 05 05:34:43 PM PDT 24
Peak memory 212080 kb
Host smart-49119910-c185-4adc-9bef-3e35bd338c17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52020680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.52020680
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3217248326
Short name T92
Test name
Test status
Simulation time 2136187564 ps
CPU time 56.68 seconds
Started Jun 05 05:34:15 PM PDT 24
Finished Jun 05 05:35:12 PM PDT 24
Peak memory 215432 kb
Host smart-45561535-f4ac-4c65-af99-3fc85becfe7f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217248326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3217248326
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2732435594
Short name T107
Test name
Test status
Simulation time 2864004408 ps
CPU time 16.81 seconds
Started Jun 05 05:34:24 PM PDT 24
Finished Jun 05 05:34:42 PM PDT 24
Peak memory 211540 kb
Host smart-9b364194-747b-4706-b79d-2e09604951bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732435594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2732435594
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3448839296
Short name T446
Test name
Test status
Simulation time 3089271412 ps
CPU time 28.51 seconds
Started Jun 05 05:34:25 PM PDT 24
Finished Jun 05 05:34:54 PM PDT 24
Peak memory 218400 kb
Host smart-84b959a4-3783-4e98-aa5d-fa40a21febd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448839296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3448839296
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2023024453
Short name T117
Test name
Test status
Simulation time 15159313255 ps
CPU time 171.03 seconds
Started Jun 05 05:34:22 PM PDT 24
Finished Jun 05 05:37:13 PM PDT 24
Peak memory 219560 kb
Host smart-6ed0c1e8-2160-4ba4-a59f-b57a4477a81e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023024453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2023024453
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2097899534
Short name T402
Test name
Test status
Simulation time 2125313873 ps
CPU time 21.13 seconds
Started Jun 05 05:34:23 PM PDT 24
Finished Jun 05 05:34:45 PM PDT 24
Peak memory 219584 kb
Host smart-b6a60ca0-ccf3-4166-9733-4739babd3793
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097899534 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2097899534
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1728721497
Short name T392
Test name
Test status
Simulation time 3559774100 ps
CPU time 28 seconds
Started Jun 05 05:34:25 PM PDT 24
Finished Jun 05 05:34:53 PM PDT 24
Peak memory 211764 kb
Host smart-3b532c72-f7af-4739-85a2-b1c3c0d271a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728721497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1728721497
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2988100948
Short name T419
Test name
Test status
Simulation time 61772364176 ps
CPU time 122.67 seconds
Started Jun 05 05:34:22 PM PDT 24
Finished Jun 05 05:36:26 PM PDT 24
Peak memory 214412 kb
Host smart-3d607558-1340-4a37-bad3-7872f556d647
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988100948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2988100948
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.767632575
Short name T393
Test name
Test status
Simulation time 4275264695 ps
CPU time 30.73 seconds
Started Jun 05 05:34:23 PM PDT 24
Finished Jun 05 05:34:54 PM PDT 24
Peak memory 212052 kb
Host smart-e7b88b43-c6c7-4bf5-ba38-5bde9bc25c90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767632575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.767632575
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3178461057
Short name T57
Test name
Test status
Simulation time 2241822318 ps
CPU time 25.35 seconds
Started Jun 05 05:34:24 PM PDT 24
Finished Jun 05 05:34:49 PM PDT 24
Peak memory 219636 kb
Host smart-0623844a-b81e-4f6b-afa8-361791d73bcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178461057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3178461057
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1932139527
Short name T423
Test name
Test status
Simulation time 9562016614 ps
CPU time 13.41 seconds
Started Jun 05 05:34:24 PM PDT 24
Finished Jun 05 05:34:38 PM PDT 24
Peak memory 216628 kb
Host smart-a494d86e-f1a2-479c-92bb-e2cdbac989e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932139527 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1932139527
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1185231686
Short name T414
Test name
Test status
Simulation time 6996006020 ps
CPU time 28.02 seconds
Started Jun 05 05:34:21 PM PDT 24
Finished Jun 05 05:34:50 PM PDT 24
Peak memory 212420 kb
Host smart-743b3b82-74af-41a0-8ef6-63cae4bcf251
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185231686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1185231686
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4286163647
Short name T76
Test name
Test status
Simulation time 3439768498 ps
CPU time 37.57 seconds
Started Jun 05 05:34:21 PM PDT 24
Finished Jun 05 05:34:59 PM PDT 24
Peak memory 214480 kb
Host smart-5f4ab528-00bb-44ed-bd71-e2a1da65c942
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286163647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.4286163647
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.652787270
Short name T439
Test name
Test status
Simulation time 3825587473 ps
CPU time 29.39 seconds
Started Jun 05 05:34:23 PM PDT 24
Finished Jun 05 05:34:53 PM PDT 24
Peak memory 212020 kb
Host smart-7c0358a1-e252-441c-ba1e-1d83b34025b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652787270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.652787270
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3379143596
Short name T369
Test name
Test status
Simulation time 3602628262 ps
CPU time 33.07 seconds
Started Jun 05 05:34:22 PM PDT 24
Finished Jun 05 05:34:56 PM PDT 24
Peak memory 218584 kb
Host smart-c426c0f1-f9b3-4e36-bdf7-7ffb24a9dbae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379143596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3379143596
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1007717760
Short name T120
Test name
Test status
Simulation time 4056274352 ps
CPU time 175.5 seconds
Started Jun 05 05:34:21 PM PDT 24
Finished Jun 05 05:37:17 PM PDT 24
Peak memory 214944 kb
Host smart-3f92db91-1a4f-46ed-bc65-1226ae5f1cea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007717760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1007717760
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2546272270
Short name T360
Test name
Test status
Simulation time 1426822717 ps
CPU time 11.6 seconds
Started Jun 05 05:34:31 PM PDT 24
Finished Jun 05 05:34:43 PM PDT 24
Peak memory 217912 kb
Host smart-129718db-818b-4503-bf93-14c59eb945d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546272270 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2546272270
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3845909162
Short name T372
Test name
Test status
Simulation time 14172729690 ps
CPU time 28.7 seconds
Started Jun 05 05:34:29 PM PDT 24
Finished Jun 05 05:34:58 PM PDT 24
Peak memory 212468 kb
Host smart-ad72c27a-2b5e-4dc7-b941-599ae7bba910
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845909162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3845909162
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2641374137
Short name T84
Test name
Test status
Simulation time 10414285447 ps
CPU time 71.92 seconds
Started Jun 05 05:34:24 PM PDT 24
Finished Jun 05 05:35:36 PM PDT 24
Peak memory 215484 kb
Host smart-7e31a6bd-1086-4036-9db4-8743547a4158
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641374137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2641374137
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1445108829
Short name T421
Test name
Test status
Simulation time 994313182 ps
CPU time 17.91 seconds
Started Jun 05 05:34:30 PM PDT 24
Finished Jun 05 05:34:49 PM PDT 24
Peak memory 212428 kb
Host smart-cef07149-c7e7-4ff7-afc6-bea9e451234c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445108829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1445108829
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1271803332
Short name T368
Test name
Test status
Simulation time 3926571097 ps
CPU time 35.11 seconds
Started Jun 05 05:34:23 PM PDT 24
Finished Jun 05 05:34:59 PM PDT 24
Peak memory 217676 kb
Host smart-3223f0b7-072e-47e8-a142-ac55ba47302f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271803332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1271803332
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2591477379
Short name T119
Test name
Test status
Simulation time 1177970107 ps
CPU time 80.63 seconds
Started Jun 05 05:34:24 PM PDT 24
Finished Jun 05 05:35:46 PM PDT 24
Peak memory 213904 kb
Host smart-ccc77020-26d4-4893-a0db-7b31592e64af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591477379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2591477379
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1889008215
Short name T101
Test name
Test status
Simulation time 2983959728 ps
CPU time 21.48 seconds
Started Jun 05 05:33:08 PM PDT 24
Finished Jun 05 05:33:30 PM PDT 24
Peak memory 211508 kb
Host smart-0db2acbb-d596-40f8-bd00-8b94dbc88cc0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889008215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1889008215
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2569128018
Short name T435
Test name
Test status
Simulation time 1275784874 ps
CPU time 16.39 seconds
Started Jun 05 05:33:06 PM PDT 24
Finished Jun 05 05:33:23 PM PDT 24
Peak memory 211292 kb
Host smart-fb0e308a-5079-424a-b4cb-55bec8904e04
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569128018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2569128018
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2146925510
Short name T381
Test name
Test status
Simulation time 847159152 ps
CPU time 15.2 seconds
Started Jun 05 05:33:08 PM PDT 24
Finished Jun 05 05:33:24 PM PDT 24
Peak memory 212204 kb
Host smart-db464463-e3d3-458e-850d-c0bbee6d6f40
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146925510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2146925510
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3301385639
Short name T361
Test name
Test status
Simulation time 3041123897 ps
CPU time 25.65 seconds
Started Jun 05 05:33:17 PM PDT 24
Finished Jun 05 05:33:43 PM PDT 24
Peak memory 216364 kb
Host smart-7545cbfb-e5af-4f90-9604-3609d09482d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301385639 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3301385639
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3827223257
Short name T382
Test name
Test status
Simulation time 8743946416 ps
CPU time 31.32 seconds
Started Jun 05 05:33:07 PM PDT 24
Finished Jun 05 05:33:39 PM PDT 24
Peak memory 212056 kb
Host smart-f490a1e3-2183-4622-9acb-2aa822fc6f3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827223257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3827223257
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1717886951
Short name T397
Test name
Test status
Simulation time 27445318210 ps
CPU time 27.61 seconds
Started Jun 05 05:33:09 PM PDT 24
Finished Jun 05 05:33:37 PM PDT 24
Peak memory 211264 kb
Host smart-6809abbe-f945-43e5-b271-430aae7c64bf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717886951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1717886951
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2775974685
Short name T427
Test name
Test status
Simulation time 2397036069 ps
CPU time 12.15 seconds
Started Jun 05 05:33:08 PM PDT 24
Finished Jun 05 05:33:21 PM PDT 24
Peak memory 211316 kb
Host smart-419160c6-b659-4883-b8fc-a423ca91d00c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775974685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2775974685
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1605342223
Short name T96
Test name
Test status
Simulation time 2842250835 ps
CPU time 36.77 seconds
Started Jun 05 05:33:09 PM PDT 24
Finished Jun 05 05:33:46 PM PDT 24
Peak memory 213452 kb
Host smart-eb585340-9532-485b-9541-93190318589e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605342223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1605342223
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.483276470
Short name T409
Test name
Test status
Simulation time 53372477686 ps
CPU time 32.18 seconds
Started Jun 05 05:33:09 PM PDT 24
Finished Jun 05 05:33:43 PM PDT 24
Peak memory 212660 kb
Host smart-da6585aa-d07c-4624-b8ae-8b3e386e3b63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483276470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.483276470
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1368903265
Short name T399
Test name
Test status
Simulation time 177816442 ps
CPU time 13.1 seconds
Started Jun 05 05:33:08 PM PDT 24
Finished Jun 05 05:33:22 PM PDT 24
Peak memory 217520 kb
Host smart-f478c6b5-983d-4c58-9dc2-6a92aa3cc264
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368903265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1368903265
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.15670603
Short name T108
Test name
Test status
Simulation time 13397501697 ps
CPU time 23.7 seconds
Started Jun 05 05:33:26 PM PDT 24
Finished Jun 05 05:33:50 PM PDT 24
Peak memory 212512 kb
Host smart-225c5a07-deee-4605-918a-a090b8b6b11c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15670603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasi
ng.15670603
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.37426333
Short name T378
Test name
Test status
Simulation time 2747569683 ps
CPU time 8.67 seconds
Started Jun 05 05:33:24 PM PDT 24
Finished Jun 05 05:33:33 PM PDT 24
Peak memory 211364 kb
Host smart-bcbc0c5c-5af3-4fdf-89f4-671a61e037e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37426333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_ba
sh.37426333
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4040641424
Short name T442
Test name
Test status
Simulation time 676799522 ps
CPU time 18.67 seconds
Started Jun 05 05:33:24 PM PDT 24
Finished Jun 05 05:33:43 PM PDT 24
Peak memory 211916 kb
Host smart-4f7546a9-21cb-46bd-beba-bb3a804e49a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040641424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.4040641424
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1905711816
Short name T390
Test name
Test status
Simulation time 5604877162 ps
CPU time 17.22 seconds
Started Jun 05 05:33:26 PM PDT 24
Finished Jun 05 05:33:44 PM PDT 24
Peak memory 217876 kb
Host smart-40ba6d29-334e-4687-bf3a-efcd1eeaf1d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905711816 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1905711816
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3994404705
Short name T103
Test name
Test status
Simulation time 3162539125 ps
CPU time 13.57 seconds
Started Jun 05 05:33:26 PM PDT 24
Finished Jun 05 05:33:40 PM PDT 24
Peak memory 211368 kb
Host smart-20f06a3f-ca15-4b72-aa5b-5ae8f9cada1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994404705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3994404705
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1065551508
Short name T403
Test name
Test status
Simulation time 1835647004 ps
CPU time 17.91 seconds
Started Jun 05 05:33:24 PM PDT 24
Finished Jun 05 05:33:43 PM PDT 24
Peak memory 211192 kb
Host smart-b753ddb7-1c1e-45aa-9970-066c430626e6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065551508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1065551508
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2336579414
Short name T365
Test name
Test status
Simulation time 6882037869 ps
CPU time 18.53 seconds
Started Jun 05 05:33:17 PM PDT 24
Finished Jun 05 05:33:36 PM PDT 24
Peak memory 211300 kb
Host smart-f8889765-ba98-4f64-8f1c-97159cc53156
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336579414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2336579414
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3947573123
Short name T405
Test name
Test status
Simulation time 17091843728 ps
CPU time 105.8 seconds
Started Jun 05 05:33:18 PM PDT 24
Finished Jun 05 05:35:05 PM PDT 24
Peak memory 215468 kb
Host smart-f2cc834b-0543-4798-9ff9-d2f14a9cf8d6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947573123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3947573123
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3245269359
Short name T83
Test name
Test status
Simulation time 176423546 ps
CPU time 8.38 seconds
Started Jun 05 05:33:24 PM PDT 24
Finished Jun 05 05:33:33 PM PDT 24
Peak memory 211604 kb
Host smart-f173b4f0-a8c8-4f83-8eff-633944319c03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245269359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3245269359
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1942811776
Short name T451
Test name
Test status
Simulation time 636355822 ps
CPU time 11.32 seconds
Started Jun 05 05:33:18 PM PDT 24
Finished Jun 05 05:33:30 PM PDT 24
Peak memory 217136 kb
Host smart-e34e76f2-8249-4db7-8380-51362dc29a75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942811776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1942811776
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1252070011
Short name T114
Test name
Test status
Simulation time 11982536342 ps
CPU time 166.92 seconds
Started Jun 05 05:33:17 PM PDT 24
Finished Jun 05 05:36:04 PM PDT 24
Peak memory 215368 kb
Host smart-50fe8889-db6d-4a7b-be1c-c5454401b9dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252070011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1252070011
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.367733565
Short name T376
Test name
Test status
Simulation time 3294724423 ps
CPU time 8.3 seconds
Started Jun 05 05:33:31 PM PDT 24
Finished Jun 05 05:33:40 PM PDT 24
Peak memory 211400 kb
Host smart-4c71c9ab-1d8e-4b4e-a9e9-a8479c925b84
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367733565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.367733565
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3758884095
Short name T408
Test name
Test status
Simulation time 2566171144 ps
CPU time 16.15 seconds
Started Jun 05 05:33:31 PM PDT 24
Finished Jun 05 05:33:48 PM PDT 24
Peak memory 219508 kb
Host smart-0969ecc7-114c-4edc-8c5e-6884e23b0e72
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758884095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3758884095
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.302390102
Short name T109
Test name
Test status
Simulation time 14038137023 ps
CPU time 31.89 seconds
Started Jun 05 05:33:30 PM PDT 24
Finished Jun 05 05:34:02 PM PDT 24
Peak memory 212152 kb
Host smart-eadb2cd2-ad9e-4739-a546-12ef0dd0fe97
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302390102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.302390102
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1355125726
Short name T386
Test name
Test status
Simulation time 1849012960 ps
CPU time 19.91 seconds
Started Jun 05 05:33:32 PM PDT 24
Finished Jun 05 05:33:52 PM PDT 24
Peak memory 217420 kb
Host smart-81e52cd4-ef83-4c59-8d63-289c068acb59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355125726 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1355125726
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.817414104
Short name T97
Test name
Test status
Simulation time 687878633 ps
CPU time 7.99 seconds
Started Jun 05 05:33:30 PM PDT 24
Finished Jun 05 05:33:39 PM PDT 24
Peak memory 211256 kb
Host smart-36ab6356-f3d4-433d-964e-61e12ebf5661
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817414104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.817414104
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2879646224
Short name T383
Test name
Test status
Simulation time 1378607938 ps
CPU time 12.75 seconds
Started Jun 05 05:33:31 PM PDT 24
Finished Jun 05 05:33:45 PM PDT 24
Peak memory 211128 kb
Host smart-1ade10d7-f5b8-42b8-9046-f481b2c28ccd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879646224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2879646224
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1164784246
Short name T444
Test name
Test status
Simulation time 9192392314 ps
CPU time 22.41 seconds
Started Jun 05 05:33:31 PM PDT 24
Finished Jun 05 05:33:54 PM PDT 24
Peak memory 211324 kb
Host smart-27dcd12a-d39b-4fc6-9e85-116ad40d018c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164784246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1164784246
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3260568357
Short name T417
Test name
Test status
Simulation time 23316917924 ps
CPU time 73.4 seconds
Started Jun 05 05:33:28 PM PDT 24
Finished Jun 05 05:34:42 PM PDT 24
Peak memory 214468 kb
Host smart-0bc853c5-2919-4ab7-9cbf-b16994be49dd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260568357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3260568357
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.228717744
Short name T447
Test name
Test status
Simulation time 15413248848 ps
CPU time 34.39 seconds
Started Jun 05 05:33:32 PM PDT 24
Finished Jun 05 05:34:07 PM PDT 24
Peak memory 212888 kb
Host smart-f5b7de8f-271e-4d9c-838f-3ef3ecdcd47e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228717744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.228717744
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3961778472
Short name T359
Test name
Test status
Simulation time 2424879724 ps
CPU time 26.32 seconds
Started Jun 05 05:33:24 PM PDT 24
Finished Jun 05 05:33:50 PM PDT 24
Peak memory 218740 kb
Host smart-5ef4bb14-2c7f-4a8d-9296-654f31648f08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961778472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3961778472
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1364160393
Short name T454
Test name
Test status
Simulation time 507452991 ps
CPU time 79.5 seconds
Started Jun 05 05:33:26 PM PDT 24
Finished Jun 05 05:34:46 PM PDT 24
Peak memory 213880 kb
Host smart-f7540845-c37b-4f6b-8a7d-37c87f48c738
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364160393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1364160393
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1967472961
Short name T404
Test name
Test status
Simulation time 33910990981 ps
CPU time 24.54 seconds
Started Jun 05 05:33:38 PM PDT 24
Finished Jun 05 05:34:03 PM PDT 24
Peak memory 216912 kb
Host smart-aae9a14a-ac65-4092-9219-d7951e13e7cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967472961 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1967472961
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.143874425
Short name T398
Test name
Test status
Simulation time 6284260899 ps
CPU time 22.18 seconds
Started Jun 05 05:33:40 PM PDT 24
Finished Jun 05 05:34:03 PM PDT 24
Peak memory 212304 kb
Host smart-fbff94d9-748f-456a-85ed-5fe35057d3c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143874425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.143874425
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.503729774
Short name T94
Test name
Test status
Simulation time 67580743302 ps
CPU time 103.18 seconds
Started Jun 05 05:33:31 PM PDT 24
Finished Jun 05 05:35:15 PM PDT 24
Peak memory 214476 kb
Host smart-c1a73eeb-003f-4f31-b103-3101b7cb0a20
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503729774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.503729774
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1531811484
Short name T81
Test name
Test status
Simulation time 184307690 ps
CPU time 12.08 seconds
Started Jun 05 05:33:38 PM PDT 24
Finished Jun 05 05:33:51 PM PDT 24
Peak memory 211356 kb
Host smart-9041763f-a8c0-4e0b-8199-6c7704f737cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531811484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1531811484
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.884983984
Short name T374
Test name
Test status
Simulation time 1941674536 ps
CPU time 14.99 seconds
Started Jun 05 05:33:33 PM PDT 24
Finished Jun 05 05:33:49 PM PDT 24
Peak memory 217520 kb
Host smart-718cfaf4-cbba-4eb8-973d-0462f01344a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884983984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.884983984
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3144196097
Short name T64
Test name
Test status
Simulation time 15195496887 ps
CPU time 98.73 seconds
Started Jun 05 05:33:32 PM PDT 24
Finished Jun 05 05:35:12 PM PDT 24
Peak memory 214024 kb
Host smart-04b36f51-ba8f-4631-8ef6-31581694751e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144196097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3144196097
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1439447721
Short name T387
Test name
Test status
Simulation time 35504480802 ps
CPU time 29.2 seconds
Started Jun 05 05:33:45 PM PDT 24
Finished Jun 05 05:34:14 PM PDT 24
Peak memory 217616 kb
Host smart-11427298-579c-42d2-9915-2e0b8fd64ec6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439447721 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1439447721
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.925580340
Short name T367
Test name
Test status
Simulation time 687818425 ps
CPU time 8.34 seconds
Started Jun 05 05:33:38 PM PDT 24
Finished Jun 05 05:33:47 PM PDT 24
Peak memory 211332 kb
Host smart-e16ad797-02de-48b3-9949-9ff22182dea4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925580340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.925580340
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.104035852
Short name T113
Test name
Test status
Simulation time 26406994812 ps
CPU time 78.41 seconds
Started Jun 05 05:33:37 PM PDT 24
Finished Jun 05 05:34:56 PM PDT 24
Peak memory 214556 kb
Host smart-41743535-ae22-4720-9a09-4955c59b9042
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104035852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.104035852
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.420736715
Short name T69
Test name
Test status
Simulation time 4352525957 ps
CPU time 30.22 seconds
Started Jun 05 05:33:46 PM PDT 24
Finished Jun 05 05:34:16 PM PDT 24
Peak memory 212720 kb
Host smart-f53b09d8-56c5-4924-a50d-6698af62b1b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420736715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.420736715
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1976003596
Short name T56
Test name
Test status
Simulation time 4618830048 ps
CPU time 24.86 seconds
Started Jun 05 05:33:40 PM PDT 24
Finished Jun 05 05:34:05 PM PDT 24
Peak memory 218676 kb
Host smart-639e6745-1023-4b5a-8018-7e9b5cb375d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976003596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1976003596
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2224614593
Short name T428
Test name
Test status
Simulation time 6430783016 ps
CPU time 26.51 seconds
Started Jun 05 05:33:47 PM PDT 24
Finished Jun 05 05:34:14 PM PDT 24
Peak memory 218516 kb
Host smart-a208262f-5a72-4146-8c4d-a00024fe9cf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224614593 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2224614593
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.937193797
Short name T68
Test name
Test status
Simulation time 12653577579 ps
CPU time 19.36 seconds
Started Jun 05 05:33:45 PM PDT 24
Finished Jun 05 05:34:04 PM PDT 24
Peak memory 212400 kb
Host smart-bbb62a90-39d4-4c7f-b17e-da358afe56d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937193797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.937193797
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.157727221
Short name T80
Test name
Test status
Simulation time 15913943585 ps
CPU time 124.96 seconds
Started Jun 05 05:33:47 PM PDT 24
Finished Jun 05 05:35:52 PM PDT 24
Peak memory 213488 kb
Host smart-7614aa5d-14bb-4b4b-8b67-5c9778a419ca
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157727221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.157727221
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3918784315
Short name T380
Test name
Test status
Simulation time 25122024749 ps
CPU time 33.77 seconds
Started Jun 05 05:33:45 PM PDT 24
Finished Jun 05 05:34:19 PM PDT 24
Peak memory 212712 kb
Host smart-2dbb8622-78ac-49d5-b46d-4b0cdd060c97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918784315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3918784315
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.584390778
Short name T431
Test name
Test status
Simulation time 8475337478 ps
CPU time 24.24 seconds
Started Jun 05 05:33:44 PM PDT 24
Finished Jun 05 05:34:09 PM PDT 24
Peak memory 219600 kb
Host smart-92102c46-cdaf-4d39-aa34-3c23cec9b223
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584390778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.584390778
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3247430023
Short name T449
Test name
Test status
Simulation time 8278248437 ps
CPU time 101.8 seconds
Started Jun 05 05:33:45 PM PDT 24
Finished Jun 05 05:35:27 PM PDT 24
Peak memory 213896 kb
Host smart-c8945901-3e98-49c8-86cf-26886a05b6aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247430023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3247430023
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.669177336
Short name T394
Test name
Test status
Simulation time 372906308 ps
CPU time 9.05 seconds
Started Jun 05 05:33:52 PM PDT 24
Finished Jun 05 05:34:02 PM PDT 24
Peak memory 216716 kb
Host smart-ce7d0c78-427f-4aac-90ae-7ceeb3d9eb5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669177336 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.669177336
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3693019788
Short name T432
Test name
Test status
Simulation time 346279400 ps
CPU time 8.05 seconds
Started Jun 05 05:33:52 PM PDT 24
Finished Jun 05 05:34:00 PM PDT 24
Peak memory 211320 kb
Host smart-143f3016-c383-4a13-83b0-b314dc7e1854
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693019788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3693019788
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1476198615
Short name T395
Test name
Test status
Simulation time 10110221656 ps
CPU time 114.38 seconds
Started Jun 05 05:33:46 PM PDT 24
Finished Jun 05 05:35:41 PM PDT 24
Peak memory 215516 kb
Host smart-4f393dfe-55c3-451f-8607-49bfb47e6407
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476198615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1476198615
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2568468879
Short name T450
Test name
Test status
Simulation time 17402800567 ps
CPU time 27.79 seconds
Started Jun 05 05:33:52 PM PDT 24
Finished Jun 05 05:34:20 PM PDT 24
Peak memory 212452 kb
Host smart-c5b9fd75-ec75-48ae-850a-8354beae1780
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568468879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2568468879
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2124795516
Short name T430
Test name
Test status
Simulation time 3854708242 ps
CPU time 33.01 seconds
Started Jun 05 05:33:55 PM PDT 24
Finished Jun 05 05:34:29 PM PDT 24
Peak memory 218432 kb
Host smart-9e042dd0-e024-4ea5-acf5-1bf994dee96d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124795516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2124795516
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2213935582
Short name T121
Test name
Test status
Simulation time 3135322196 ps
CPU time 97.83 seconds
Started Jun 05 05:33:53 PM PDT 24
Finished Jun 05 05:35:32 PM PDT 24
Peak memory 213676 kb
Host smart-40576609-b3d3-4ab1-a0e6-c716aaa66d87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213935582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2213935582
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3775226111
Short name T384
Test name
Test status
Simulation time 10039471828 ps
CPU time 33.22 seconds
Started Jun 05 05:34:00 PM PDT 24
Finished Jun 05 05:34:33 PM PDT 24
Peak memory 218776 kb
Host smart-4f14e3c2-2816-4a75-8da4-ec81595d67ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775226111 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3775226111
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1605498788
Short name T400
Test name
Test status
Simulation time 5272534471 ps
CPU time 22.43 seconds
Started Jun 05 05:34:01 PM PDT 24
Finished Jun 05 05:34:23 PM PDT 24
Peak memory 212112 kb
Host smart-01b127c1-3a5a-4371-bb21-105e4900762a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605498788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1605498788
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.332194557
Short name T388
Test name
Test status
Simulation time 19713585448 ps
CPU time 69.93 seconds
Started Jun 05 05:33:53 PM PDT 24
Finished Jun 05 05:35:03 PM PDT 24
Peak memory 214484 kb
Host smart-b6f090a8-abbf-42af-82da-33c7b5f784cd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332194557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.332194557
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4022502367
Short name T105
Test name
Test status
Simulation time 801965662 ps
CPU time 11.83 seconds
Started Jun 05 05:34:01 PM PDT 24
Finished Jun 05 05:34:13 PM PDT 24
Peak memory 212812 kb
Host smart-bf938421-d114-4e7c-babd-98afe650f25a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022502367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.4022502367
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.4104325184
Short name T385
Test name
Test status
Simulation time 1828877079 ps
CPU time 11.49 seconds
Started Jun 05 05:33:53 PM PDT 24
Finished Jun 05 05:34:05 PM PDT 24
Peak memory 217484 kb
Host smart-4026cfa7-807f-4eda-b8ef-46be8b9c0971
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104325184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.4104325184
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2819422966
Short name T118
Test name
Test status
Simulation time 17125534267 ps
CPU time 99.79 seconds
Started Jun 05 05:33:52 PM PDT 24
Finished Jun 05 05:35:33 PM PDT 24
Peak memory 214100 kb
Host smart-8100d8cd-7a5f-4e3c-b817-fcc1546e3443
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819422966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2819422966
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1986559176
Short name T306
Test name
Test status
Simulation time 5392769137 ps
CPU time 29.14 seconds
Started Jun 05 05:15:27 PM PDT 24
Finished Jun 05 05:15:57 PM PDT 24
Peak memory 212252 kb
Host smart-17a0a179-bb12-4666-b01c-58275a7f4787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986559176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1986559176
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4243110220
Short name T281
Test name
Test status
Simulation time 160412375640 ps
CPU time 391.77 seconds
Started Jun 05 05:15:30 PM PDT 24
Finished Jun 05 05:22:02 PM PDT 24
Peak memory 239744 kb
Host smart-8a8ea3a0-9215-47c3-a32e-938d657a3a27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243110220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.4243110220
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1722340743
Short name T190
Test name
Test status
Simulation time 71873287279 ps
CPU time 58.42 seconds
Started Jun 05 05:15:32 PM PDT 24
Finished Jun 05 05:16:30 PM PDT 24
Peak memory 212880 kb
Host smart-3c7496c0-fe67-4308-a82b-75c9c1b92d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722340743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1722340743
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3466905715
Short name T274
Test name
Test status
Simulation time 9495339637 ps
CPU time 24.47 seconds
Started Jun 05 05:15:21 PM PDT 24
Finished Jun 05 05:15:46 PM PDT 24
Peak memory 211620 kb
Host smart-809db5e6-9e32-4414-be56-55ce983b5fed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3466905715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3466905715
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3159262053
Short name T244
Test name
Test status
Simulation time 666534911 ps
CPU time 20.85 seconds
Started Jun 05 05:15:22 PM PDT 24
Finished Jun 05 05:15:43 PM PDT 24
Peak memory 217060 kb
Host smart-8f3478ed-3b07-40c3-8303-af42799f053f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159262053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3159262053
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.4131998091
Short name T90
Test name
Test status
Simulation time 3102835814 ps
CPU time 57.05 seconds
Started Jun 05 05:15:20 PM PDT 24
Finished Jun 05 05:16:18 PM PDT 24
Peak memory 219292 kb
Host smart-f6ea27a7-8203-48f0-873b-b187a6e310bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131998091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.4131998091
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3114701913
Short name T175
Test name
Test status
Simulation time 857024155 ps
CPU time 14.28 seconds
Started Jun 05 05:15:26 PM PDT 24
Finished Jun 05 05:15:41 PM PDT 24
Peak memory 211376 kb
Host smart-ae4a01e5-c732-485c-816b-47c2ea06c9a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114701913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3114701913
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1218712762
Short name T264
Test name
Test status
Simulation time 4312090738 ps
CPU time 107.36 seconds
Started Jun 05 05:15:30 PM PDT 24
Finished Jun 05 05:17:18 PM PDT 24
Peak memory 239720 kb
Host smart-0f879561-52ab-4021-bb50-0e82ee2f3cbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218712762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1218712762
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1251511941
Short name T157
Test name
Test status
Simulation time 1874572749 ps
CPU time 21.67 seconds
Started Jun 05 05:15:27 PM PDT 24
Finished Jun 05 05:15:50 PM PDT 24
Peak memory 212552 kb
Host smart-22476a34-7d6a-4749-941f-b6fa0d582e64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1251511941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1251511941
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1988550170
Short name T38
Test name
Test status
Simulation time 9076556615 ps
CPU time 148.72 seconds
Started Jun 05 05:15:29 PM PDT 24
Finished Jun 05 05:17:59 PM PDT 24
Peak memory 239184 kb
Host smart-825bdba7-cc94-445e-995f-be9e18008f01
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988550170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1988550170
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2624327283
Short name T145
Test name
Test status
Simulation time 4675099240 ps
CPU time 48.7 seconds
Started Jun 05 05:15:29 PM PDT 24
Finished Jun 05 05:16:18 PM PDT 24
Peak memory 217756 kb
Host smart-90430203-c6a5-459e-b232-e6ddbf9df55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624327283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2624327283
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.678006463
Short name T218
Test name
Test status
Simulation time 764253285 ps
CPU time 20.49 seconds
Started Jun 05 05:15:26 PM PDT 24
Finished Jun 05 05:15:47 PM PDT 24
Peak memory 217512 kb
Host smart-f9894f02-ecff-4c2d-a03a-504b15c45501
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678006463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.678006463
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.283550187
Short name T222
Test name
Test status
Simulation time 167690443 ps
CPU time 8.25 seconds
Started Jun 05 05:15:52 PM PDT 24
Finished Jun 05 05:16:01 PM PDT 24
Peak memory 211296 kb
Host smart-cfeca60a-7af9-4d21-80b0-ba8dc93aabb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283550187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.283550187
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.493281175
Short name T292
Test name
Test status
Simulation time 159781029954 ps
CPU time 573.52 seconds
Started Jun 05 05:15:52 PM PDT 24
Finished Jun 05 05:25:27 PM PDT 24
Peak memory 215792 kb
Host smart-4b02e784-0df7-4e5a-be8e-b68fac3b6c91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493281175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_c
orrupt_sig_fatal_chk.493281175
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2502747807
Short name T239
Test name
Test status
Simulation time 5669240007 ps
CPU time 30.06 seconds
Started Jun 05 05:15:51 PM PDT 24
Finished Jun 05 05:16:22 PM PDT 24
Peak memory 215008 kb
Host smart-d78815ab-252c-428a-83d3-e8eebeb98e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502747807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2502747807
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1282420715
Short name T355
Test name
Test status
Simulation time 352405763 ps
CPU time 20.54 seconds
Started Jun 05 05:15:52 PM PDT 24
Finished Jun 05 05:16:14 PM PDT 24
Peak memory 216960 kb
Host smart-a62a2589-dbb1-4bd9-92c9-dcab0192263c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282420715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1282420715
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2155044668
Short name T58
Test name
Test status
Simulation time 1689169641 ps
CPU time 24.76 seconds
Started Jun 05 05:15:50 PM PDT 24
Finished Jun 05 05:16:15 PM PDT 24
Peak memory 218016 kb
Host smart-498915d5-3eca-48c1-9c35-a246d84a4e72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155044668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2155044668
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.657192009
Short name T255
Test name
Test status
Simulation time 1261793045 ps
CPU time 10.89 seconds
Started Jun 05 05:15:59 PM PDT 24
Finished Jun 05 05:16:11 PM PDT 24
Peak memory 211556 kb
Host smart-326a9125-e8db-41b1-b6bc-fff057680f0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657192009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.657192009
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.87956842
Short name T197
Test name
Test status
Simulation time 8749433699 ps
CPU time 106.14 seconds
Started Jun 05 05:16:00 PM PDT 24
Finished Jun 05 05:17:47 PM PDT 24
Peak memory 239708 kb
Host smart-e734c35d-e2bb-4413-893e-468ca85bd063
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87956842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_co
rrupt_sig_fatal_chk.87956842
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2310598753
Short name T227
Test name
Test status
Simulation time 9705656253 ps
CPU time 33.75 seconds
Started Jun 05 05:15:50 PM PDT 24
Finished Jun 05 05:16:24 PM PDT 24
Peak memory 215016 kb
Host smart-f9ed786f-e3df-4ff1-aaa3-fd5ff3717d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310598753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2310598753
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.371855811
Short name T174
Test name
Test status
Simulation time 964055299 ps
CPU time 16.53 seconds
Started Jun 05 05:15:50 PM PDT 24
Finished Jun 05 05:16:07 PM PDT 24
Peak memory 211256 kb
Host smart-f0a54f24-9059-4dc2-b2a4-38507e639488
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=371855811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.371855811
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.543242549
Short name T243
Test name
Test status
Simulation time 15078925381 ps
CPU time 48.5 seconds
Started Jun 05 05:15:51 PM PDT 24
Finished Jun 05 05:16:41 PM PDT 24
Peak memory 217764 kb
Host smart-4e54ccc0-c95f-439b-8709-f1e68767051b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543242549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.543242549
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3535531296
Short name T209
Test name
Test status
Simulation time 12334776765 ps
CPU time 157.53 seconds
Started Jun 05 05:15:52 PM PDT 24
Finished Jun 05 05:18:30 PM PDT 24
Peak memory 219292 kb
Host smart-a202e252-1f33-4103-9943-3dc7d28eda48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535531296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3535531296
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2321714894
Short name T17
Test name
Test status
Simulation time 688217341 ps
CPU time 8.4 seconds
Started Jun 05 05:15:58 PM PDT 24
Finished Jun 05 05:16:07 PM PDT 24
Peak memory 211356 kb
Host smart-13acd1c5-b25e-4dd9-9f17-9eff80775903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321714894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2321714894
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.372111754
Short name T141
Test name
Test status
Simulation time 11273677077 ps
CPU time 201.7 seconds
Started Jun 05 05:15:58 PM PDT 24
Finished Jun 05 05:19:21 PM PDT 24
Peak memory 239840 kb
Host smart-47f9f492-d7b2-4cb8-b8b1-5a8f92f06938
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372111754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.372111754
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1210187712
Short name T8
Test name
Test status
Simulation time 11195520145 ps
CPU time 26.78 seconds
Started Jun 05 05:15:59 PM PDT 24
Finished Jun 05 05:16:27 PM PDT 24
Peak memory 211724 kb
Host smart-5f42f486-27e0-42ff-b942-33c185d9b5ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1210187712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1210187712
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3060899174
Short name T358
Test name
Test status
Simulation time 12226924859 ps
CPU time 34.46 seconds
Started Jun 05 05:16:02 PM PDT 24
Finished Jun 05 05:16:37 PM PDT 24
Peak memory 217688 kb
Host smart-7d56f425-016b-42e2-b2a0-1e09b928b175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060899174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3060899174
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3668634101
Short name T341
Test name
Test status
Simulation time 20899684868 ps
CPU time 101.37 seconds
Started Jun 05 05:15:57 PM PDT 24
Finished Jun 05 05:17:39 PM PDT 24
Peak memory 219604 kb
Host smart-489c2ec0-fe99-49d7-bf69-19d1e22b1914
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668634101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3668634101
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2974504157
Short name T23
Test name
Test status
Simulation time 48113414911 ps
CPU time 539.7 seconds
Started Jun 05 05:15:58 PM PDT 24
Finished Jun 05 05:24:58 PM PDT 24
Peak memory 229724 kb
Host smart-dc45315b-8d36-4ac2-8530-c84167f13740
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974504157 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.2974504157
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.622781050
Short name T353
Test name
Test status
Simulation time 3613610120 ps
CPU time 30.32 seconds
Started Jun 05 05:16:09 PM PDT 24
Finished Jun 05 05:16:40 PM PDT 24
Peak memory 211888 kb
Host smart-3f9dfdc0-a34c-49c7-805d-d117f7df6cef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622781050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.622781050
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1829231704
Short name T340
Test name
Test status
Simulation time 268401203551 ps
CPU time 612.48 seconds
Started Jun 05 05:15:59 PM PDT 24
Finished Jun 05 05:26:12 PM PDT 24
Peak memory 240132 kb
Host smart-bb524860-6662-46d6-b23d-33ab32e5b5d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829231704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1829231704
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1624250498
Short name T42
Test name
Test status
Simulation time 20820089446 ps
CPU time 65.94 seconds
Started Jun 05 05:16:07 PM PDT 24
Finished Jun 05 05:17:14 PM PDT 24
Peak memory 214932 kb
Host smart-d71e6c8d-ce91-469e-9299-e54a0a0b8f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624250498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1624250498
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2283172611
Short name T248
Test name
Test status
Simulation time 1319089064 ps
CPU time 10.31 seconds
Started Jun 05 05:16:01 PM PDT 24
Finished Jun 05 05:16:12 PM PDT 24
Peak memory 212456 kb
Host smart-63cf2808-fba7-4e2d-a898-caa433b1a02e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2283172611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2283172611
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1859499288
Short name T293
Test name
Test status
Simulation time 4383166710 ps
CPU time 34.24 seconds
Started Jun 05 05:15:57 PM PDT 24
Finished Jun 05 05:16:32 PM PDT 24
Peak memory 217036 kb
Host smart-7084356a-fef9-4cf4-bdd6-b51a520da773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859499288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1859499288
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.827220077
Short name T208
Test name
Test status
Simulation time 1280816789 ps
CPU time 23.04 seconds
Started Jun 05 05:15:59 PM PDT 24
Finished Jun 05 05:16:22 PM PDT 24
Peak memory 212636 kb
Host smart-2452640f-e9cd-4ff3-9ca0-a9e01e1ab8ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827220077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.827220077
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2672927157
Short name T172
Test name
Test status
Simulation time 30926390993 ps
CPU time 24.3 seconds
Started Jun 05 05:16:14 PM PDT 24
Finished Jun 05 05:16:39 PM PDT 24
Peak memory 212268 kb
Host smart-1ce43365-b416-45e1-b8c6-9dec02a696c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672927157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2672927157
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2637741507
Short name T151
Test name
Test status
Simulation time 681144190 ps
CPU time 24.04 seconds
Started Jun 05 05:16:06 PM PDT 24
Finished Jun 05 05:16:31 PM PDT 24
Peak memory 213660 kb
Host smart-7a51db93-42bd-40a0-9fa5-aea6c3e15a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637741507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2637741507
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1559258265
Short name T188
Test name
Test status
Simulation time 5047132132 ps
CPU time 25.5 seconds
Started Jun 05 05:16:09 PM PDT 24
Finished Jun 05 05:16:35 PM PDT 24
Peak memory 211424 kb
Host smart-8e117a45-e753-43e5-afe9-7e1466572789
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1559258265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1559258265
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.940370575
Short name T260
Test name
Test status
Simulation time 8066731736 ps
CPU time 70.16 seconds
Started Jun 05 05:16:08 PM PDT 24
Finished Jun 05 05:17:19 PM PDT 24
Peak memory 217124 kb
Host smart-acde2676-0212-46a6-90f1-16a97892e05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940370575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.940370575
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.498175261
Short name T284
Test name
Test status
Simulation time 338565315 ps
CPU time 10.93 seconds
Started Jun 05 05:16:15 PM PDT 24
Finished Jun 05 05:16:26 PM PDT 24
Peak memory 211276 kb
Host smart-2b3e7a08-0f9b-4669-b486-f983c2b20fab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498175261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.498175261
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3322371494
Short name T49
Test name
Test status
Simulation time 72592867055 ps
CPU time 290.41 seconds
Started Jun 05 05:16:16 PM PDT 24
Finished Jun 05 05:21:08 PM PDT 24
Peak memory 224804 kb
Host smart-d509d59f-7877-4f2f-a8a2-035b60289953
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322371494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3322371494
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1022533442
Short name T233
Test name
Test status
Simulation time 6366148861 ps
CPU time 54.94 seconds
Started Jun 05 05:16:13 PM PDT 24
Finished Jun 05 05:17:08 PM PDT 24
Peak memory 214920 kb
Host smart-3ce9d02b-a138-4956-aba3-fe657bf24d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022533442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1022533442
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2796652111
Short name T303
Test name
Test status
Simulation time 15391062020 ps
CPU time 32.44 seconds
Started Jun 05 05:16:14 PM PDT 24
Finished Jun 05 05:16:47 PM PDT 24
Peak memory 212704 kb
Host smart-ddd03929-4bce-42a2-a082-e06303a375cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2796652111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2796652111
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1807666550
Short name T133
Test name
Test status
Simulation time 7546386409 ps
CPU time 64.78 seconds
Started Jun 05 05:16:18 PM PDT 24
Finished Jun 05 05:17:23 PM PDT 24
Peak memory 217972 kb
Host smart-c00abd4b-342f-4d40-9c29-f10abbd12259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807666550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1807666550
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3250733524
Short name T177
Test name
Test status
Simulation time 2870725544 ps
CPU time 39.09 seconds
Started Jun 05 05:16:15 PM PDT 24
Finished Jun 05 05:16:55 PM PDT 24
Peak memory 213396 kb
Host smart-3970ff41-f74a-4795-a10a-cf879ebcf110
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250733524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3250733524
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2021503119
Short name T287
Test name
Test status
Simulation time 689137339 ps
CPU time 8.46 seconds
Started Jun 05 05:16:23 PM PDT 24
Finished Jun 05 05:16:32 PM PDT 24
Peak memory 211360 kb
Host smart-55ebd548-79a8-4e1e-9db5-2a78e3078803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021503119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2021503119
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3406417791
Short name T207
Test name
Test status
Simulation time 18296744263 ps
CPU time 214.89 seconds
Started Jun 05 05:16:16 PM PDT 24
Finished Jun 05 05:19:52 PM PDT 24
Peak memory 219544 kb
Host smart-2de83045-2394-484e-941e-eca5f8194c45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406417791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3406417791
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1577878777
Short name T296
Test name
Test status
Simulation time 6879541748 ps
CPU time 29.81 seconds
Started Jun 05 05:16:16 PM PDT 24
Finished Jun 05 05:16:47 PM PDT 24
Peak memory 216408 kb
Host smart-6e9ab8d7-0f5d-4927-b798-d6e89d4bbf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577878777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1577878777
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.4266644274
Short name T154
Test name
Test status
Simulation time 6843129470 ps
CPU time 28.98 seconds
Started Jun 05 05:16:15 PM PDT 24
Finished Jun 05 05:16:45 PM PDT 24
Peak memory 212760 kb
Host smart-ada5a4e1-d82c-4e11-a41c-a01a6425c00d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4266644274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.4266644274
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2214169761
Short name T194
Test name
Test status
Simulation time 13949401514 ps
CPU time 81.47 seconds
Started Jun 05 05:16:16 PM PDT 24
Finished Jun 05 05:17:38 PM PDT 24
Peak memory 215144 kb
Host smart-40ed6213-bf30-4e37-a9fc-5a7c3c40f4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214169761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2214169761
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.419240687
Short name T225
Test name
Test status
Simulation time 71951025505 ps
CPU time 188.61 seconds
Started Jun 05 05:16:15 PM PDT 24
Finished Jun 05 05:19:25 PM PDT 24
Peak memory 220480 kb
Host smart-038b2fdc-3b22-410f-9aad-824f4c80e4de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419240687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.419240687
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1059280299
Short name T330
Test name
Test status
Simulation time 3420939771 ps
CPU time 27.68 seconds
Started Jun 05 05:16:23 PM PDT 24
Finished Jun 05 05:16:52 PM PDT 24
Peak memory 211860 kb
Host smart-1bd682c4-7e14-4564-b4b4-5be43443df2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059280299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1059280299
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.500858291
Short name T230
Test name
Test status
Simulation time 18300095885 ps
CPU time 266.54 seconds
Started Jun 05 05:16:25 PM PDT 24
Finished Jun 05 05:20:52 PM PDT 24
Peak memory 237612 kb
Host smart-9ab2013f-d52d-483f-b4a5-d2936b93d93c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500858291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.500858291
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.704507221
Short name T310
Test name
Test status
Simulation time 16426282614 ps
CPU time 59.49 seconds
Started Jun 05 05:16:21 PM PDT 24
Finished Jun 05 05:17:21 PM PDT 24
Peak memory 215020 kb
Host smart-72f273b6-fb7e-45e7-aab9-2f4e258b5a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704507221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.704507221
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2015299909
Short name T155
Test name
Test status
Simulation time 363407059 ps
CPU time 10.23 seconds
Started Jun 05 05:16:24 PM PDT 24
Finished Jun 05 05:16:35 PM PDT 24
Peak memory 211108 kb
Host smart-89daa2a2-7532-44d2-b292-08ead75c3518
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2015299909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2015299909
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.623576166
Short name T320
Test name
Test status
Simulation time 12036725703 ps
CPU time 60.03 seconds
Started Jun 05 05:16:21 PM PDT 24
Finished Jun 05 05:17:22 PM PDT 24
Peak memory 220608 kb
Host smart-03ec829e-afdc-4473-bdc8-7fdbab83caaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623576166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.623576166
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.855245948
Short name T324
Test name
Test status
Simulation time 29369658728 ps
CPU time 31.14 seconds
Started Jun 05 05:16:32 PM PDT 24
Finished Jun 05 05:17:04 PM PDT 24
Peak memory 212248 kb
Host smart-31f35fb8-c972-4cf3-a2cc-fd946d371b84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855245948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.855245948
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2990331312
Short name T259
Test name
Test status
Simulation time 255966360210 ps
CPU time 323.91 seconds
Started Jun 05 05:16:34 PM PDT 24
Finished Jun 05 05:21:58 PM PDT 24
Peak memory 216972 kb
Host smart-cd00aa3c-35b1-47dc-9ff5-c91e5eb1eb38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990331312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2990331312
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3130020307
Short name T251
Test name
Test status
Simulation time 5220898200 ps
CPU time 49.92 seconds
Started Jun 05 05:16:32 PM PDT 24
Finished Jun 05 05:17:22 PM PDT 24
Peak memory 215216 kb
Host smart-525713d8-c730-4194-93d3-1e991d0eae15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130020307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3130020307
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3561140131
Short name T167
Test name
Test status
Simulation time 4136114545 ps
CPU time 24.88 seconds
Started Jun 05 05:16:33 PM PDT 24
Finished Jun 05 05:16:58 PM PDT 24
Peak memory 211280 kb
Host smart-e2e3c1c5-6642-4766-b623-d52bb320a663
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3561140131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3561140131
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2865132285
Short name T323
Test name
Test status
Simulation time 6263358793 ps
CPU time 28.1 seconds
Started Jun 05 05:16:22 PM PDT 24
Finished Jun 05 05:16:51 PM PDT 24
Peak memory 218196 kb
Host smart-fb61b26a-15ef-42c0-b2c3-264a309cd6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865132285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2865132285
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3421315055
Short name T45
Test name
Test status
Simulation time 775082056 ps
CPU time 10.65 seconds
Started Jun 05 05:16:22 PM PDT 24
Finished Jun 05 05:16:34 PM PDT 24
Peak memory 213372 kb
Host smart-06fbc4dc-ca28-40bd-bc90-68ec9299697e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421315055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3421315055
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1683688640
Short name T226
Test name
Test status
Simulation time 8758442435 ps
CPU time 33.4 seconds
Started Jun 05 05:16:31 PM PDT 24
Finished Jun 05 05:17:04 PM PDT 24
Peak memory 212140 kb
Host smart-2a06a8f7-993e-4bf3-a20d-df5d142e99ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683688640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1683688640
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2847058169
Short name T213
Test name
Test status
Simulation time 11085186018 ps
CPU time 61.61 seconds
Started Jun 05 05:16:35 PM PDT 24
Finished Jun 05 05:17:37 PM PDT 24
Peak memory 215684 kb
Host smart-1756197d-1145-4bbc-b1ac-ee10eadebb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847058169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2847058169
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.944595162
Short name T351
Test name
Test status
Simulation time 1052710136 ps
CPU time 16.37 seconds
Started Jun 05 05:16:33 PM PDT 24
Finished Jun 05 05:16:50 PM PDT 24
Peak memory 212564 kb
Host smart-20c82888-dec8-4278-aaac-0b1394fd94af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=944595162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.944595162
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.714977770
Short name T325
Test name
Test status
Simulation time 8537132197 ps
CPU time 89.56 seconds
Started Jun 05 05:16:34 PM PDT 24
Finished Jun 05 05:18:05 PM PDT 24
Peak memory 216700 kb
Host smart-9bf695e0-2185-4a7b-9611-5324d344640b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714977770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.714977770
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.99597589
Short name T319
Test name
Test status
Simulation time 12382598097 ps
CPU time 55.96 seconds
Started Jun 05 05:16:33 PM PDT 24
Finished Jun 05 05:17:29 PM PDT 24
Peak memory 219144 kb
Host smart-2378b6af-6bd0-410e-8dbf-3d5b703f7ed0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99597589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 19.rom_ctrl_stress_all.99597589
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.577789169
Short name T182
Test name
Test status
Simulation time 9754582214 ps
CPU time 23.66 seconds
Started Jun 05 05:15:25 PM PDT 24
Finished Jun 05 05:15:50 PM PDT 24
Peak memory 211860 kb
Host smart-1a8d72b8-0c80-4ab9-bb91-26864d3c02db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577789169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.577789169
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.272955
Short name T282
Test name
Test status
Simulation time 3899873345 ps
CPU time 213.94 seconds
Started Jun 05 05:15:30 PM PDT 24
Finished Jun 05 05:19:04 PM PDT 24
Peak memory 239760 kb
Host smart-615b5f3f-6a8d-4671-9d1d-8c43692dff66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_si
g_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corru
pt_sig_fatal_chk.272955
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2642800734
Short name T232
Test name
Test status
Simulation time 5089051123 ps
CPU time 49.31 seconds
Started Jun 05 05:15:28 PM PDT 24
Finished Jun 05 05:16:19 PM PDT 24
Peak memory 215000 kb
Host smart-e3d4dab8-4fe2-4c31-ac85-49c32085e120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642800734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2642800734
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3143307628
Short name T210
Test name
Test status
Simulation time 3196201353 ps
CPU time 28.97 seconds
Started Jun 05 05:15:28 PM PDT 24
Finished Jun 05 05:15:58 PM PDT 24
Peak memory 211312 kb
Host smart-d2ec7787-6937-40b8-ab9b-89e80f5ec8f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3143307628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3143307628
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3619887132
Short name T35
Test name
Test status
Simulation time 8407975010 ps
CPU time 133.1 seconds
Started Jun 05 05:15:26 PM PDT 24
Finished Jun 05 05:17:40 PM PDT 24
Peak memory 236616 kb
Host smart-86fbe951-d6ae-469c-97d2-33e066d3360d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619887132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3619887132
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.4258741577
Short name T235
Test name
Test status
Simulation time 15106323528 ps
CPU time 42.18 seconds
Started Jun 05 05:15:28 PM PDT 24
Finished Jun 05 05:16:11 PM PDT 24
Peak memory 218112 kb
Host smart-f77ce634-000a-442b-942b-7c4bdb7ed471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258741577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.4258741577
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1166796261
Short name T245
Test name
Test status
Simulation time 1202369405 ps
CPU time 12.51 seconds
Started Jun 05 05:16:37 PM PDT 24
Finished Jun 05 05:16:50 PM PDT 24
Peak memory 211352 kb
Host smart-21d907ba-61e4-47da-9e9b-d46652c44f95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166796261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1166796261
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2606551798
Short name T112
Test name
Test status
Simulation time 82837480877 ps
CPU time 396.35 seconds
Started Jun 05 05:16:33 PM PDT 24
Finished Jun 05 05:23:10 PM PDT 24
Peak memory 228172 kb
Host smart-a74d5352-a477-4b8c-9554-8a9acfa121ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606551798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2606551798
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1833384839
Short name T357
Test name
Test status
Simulation time 3257675227 ps
CPU time 39.52 seconds
Started Jun 05 05:16:34 PM PDT 24
Finished Jun 05 05:17:14 PM PDT 24
Peak memory 214648 kb
Host smart-ed17a6a7-668e-40d9-8135-9f6240ec1806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833384839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1833384839
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1148046355
Short name T297
Test name
Test status
Simulation time 458616059 ps
CPU time 10.46 seconds
Started Jun 05 05:16:32 PM PDT 24
Finished Jun 05 05:16:43 PM PDT 24
Peak memory 212216 kb
Host smart-5cac0a60-f53c-44b8-9d91-28a050913ee7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1148046355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1148046355
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1656004013
Short name T72
Test name
Test status
Simulation time 4188194213 ps
CPU time 32.91 seconds
Started Jun 05 05:16:38 PM PDT 24
Finished Jun 05 05:17:12 PM PDT 24
Peak memory 211864 kb
Host smart-5dd4acac-8cb2-422d-9b83-91d31db92da4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656004013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1656004013
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2852619454
Short name T181
Test name
Test status
Simulation time 147370408647 ps
CPU time 781.16 seconds
Started Jun 05 05:16:37 PM PDT 24
Finished Jun 05 05:29:38 PM PDT 24
Peak memory 225076 kb
Host smart-5a9fc0a4-d492-4ee6-b6cc-e0e49c145c7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852619454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2852619454
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.987315201
Short name T26
Test name
Test status
Simulation time 2060885529 ps
CPU time 19.19 seconds
Started Jun 05 05:16:40 PM PDT 24
Finished Jun 05 05:16:59 PM PDT 24
Peak memory 214676 kb
Host smart-c24c0bdb-8e05-43f4-a61c-4fabaee052f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987315201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.987315201
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1550228931
Short name T217
Test name
Test status
Simulation time 751390599 ps
CPU time 10.2 seconds
Started Jun 05 05:16:37 PM PDT 24
Finished Jun 05 05:16:47 PM PDT 24
Peak memory 212564 kb
Host smart-ce524ea8-ef74-4e7e-8fc6-9faf1f9a0947
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1550228931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1550228931
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.890724897
Short name T191
Test name
Test status
Simulation time 2062893308 ps
CPU time 26.84 seconds
Started Jun 05 05:16:39 PM PDT 24
Finished Jun 05 05:17:06 PM PDT 24
Peak memory 215560 kb
Host smart-71c33b79-2146-4a73-a394-1fc930caf18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890724897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.890724897
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2225842856
Short name T195
Test name
Test status
Simulation time 43326422813 ps
CPU time 96.38 seconds
Started Jun 05 05:16:38 PM PDT 24
Finished Jun 05 05:18:15 PM PDT 24
Peak memory 219564 kb
Host smart-64b53b3a-3ecb-4b12-a68b-11b6fe79dc52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225842856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2225842856
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.4193422507
Short name T162
Test name
Test status
Simulation time 5500764383 ps
CPU time 16.58 seconds
Started Jun 05 05:16:43 PM PDT 24
Finished Jun 05 05:17:00 PM PDT 24
Peak memory 211388 kb
Host smart-6839196a-16c7-427b-b731-0d3fe43e3477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193422507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.4193422507
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2730608120
Short name T272
Test name
Test status
Simulation time 148713557020 ps
CPU time 437.4 seconds
Started Jun 05 05:16:39 PM PDT 24
Finished Jun 05 05:23:57 PM PDT 24
Peak memory 240336 kb
Host smart-797a79c8-e2c3-46d7-b294-87298926e91e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730608120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2730608120
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1461387865
Short name T304
Test name
Test status
Simulation time 5581251385 ps
CPU time 51.45 seconds
Started Jun 05 05:16:44 PM PDT 24
Finished Jun 05 05:17:36 PM PDT 24
Peak memory 214192 kb
Host smart-82b93fd4-26b5-4262-9307-1473992a1ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461387865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1461387865
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2713417648
Short name T158
Test name
Test status
Simulation time 7436025261 ps
CPU time 27.55 seconds
Started Jun 05 05:16:37 PM PDT 24
Finished Jun 05 05:17:05 PM PDT 24
Peak memory 212540 kb
Host smart-900379c4-f197-45ff-a366-432415c0c121
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713417648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2713417648
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.471966223
Short name T134
Test name
Test status
Simulation time 2751679556 ps
CPU time 36.12 seconds
Started Jun 05 05:16:35 PM PDT 24
Finished Jun 05 05:17:11 PM PDT 24
Peak memory 215728 kb
Host smart-285f60ba-b3d6-40a2-932b-655de9b8af98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471966223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.471966223
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3523959464
Short name T176
Test name
Test status
Simulation time 3046212696 ps
CPU time 32.21 seconds
Started Jun 05 05:16:38 PM PDT 24
Finished Jun 05 05:17:10 PM PDT 24
Peak memory 212240 kb
Host smart-356b7e75-365a-4151-ad09-711371344eea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523959464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3523959464
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1122882178
Short name T51
Test name
Test status
Simulation time 69361336443 ps
CPU time 7466.6 seconds
Started Jun 05 05:16:46 PM PDT 24
Finished Jun 05 07:21:14 PM PDT 24
Peak memory 235740 kb
Host smart-c3a02b63-6f3f-4a91-9713-8bc3ca0b968a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122882178 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.1122882178
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2068996961
Short name T70
Test name
Test status
Simulation time 2746309217 ps
CPU time 24.42 seconds
Started Jun 05 05:16:52 PM PDT 24
Finished Jun 05 05:17:17 PM PDT 24
Peak memory 211864 kb
Host smart-94dd80c3-acc5-49f9-811e-a5604ef66f5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068996961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2068996961
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.889060497
Short name T131
Test name
Test status
Simulation time 49795977712 ps
CPU time 314.2 seconds
Started Jun 05 05:16:46 PM PDT 24
Finished Jun 05 05:22:01 PM PDT 24
Peak memory 230648 kb
Host smart-e12b69e6-54ef-4917-8c8b-0df9da807273
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889060497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.889060497
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3781442197
Short name T165
Test name
Test status
Simulation time 36750774558 ps
CPU time 60.29 seconds
Started Jun 05 05:16:43 PM PDT 24
Finished Jun 05 05:17:43 PM PDT 24
Peak memory 215000 kb
Host smart-bfd90b65-6970-42f0-be02-7dd1f205721b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781442197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3781442197
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.508018677
Short name T160
Test name
Test status
Simulation time 1817259821 ps
CPU time 21.02 seconds
Started Jun 05 05:16:42 PM PDT 24
Finished Jun 05 05:17:04 PM PDT 24
Peak memory 211236 kb
Host smart-3af2e0df-1cb8-49d2-a8b5-6bb9f86f5b7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=508018677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.508018677
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1763396834
Short name T11
Test name
Test status
Simulation time 8196008555 ps
CPU time 73.62 seconds
Started Jun 05 05:16:45 PM PDT 24
Finished Jun 05 05:17:59 PM PDT 24
Peak memory 217340 kb
Host smart-b33b2307-e1e8-4869-9297-ae0b950fcfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763396834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1763396834
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.873855447
Short name T9
Test name
Test status
Simulation time 12297037804 ps
CPU time 114.36 seconds
Started Jun 05 05:16:44 PM PDT 24
Finished Jun 05 05:18:39 PM PDT 24
Peak memory 219576 kb
Host smart-8d9b7b26-a60b-45c0-bc3d-a03140d6689c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873855447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.873855447
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3536948765
Short name T198
Test name
Test status
Simulation time 2673673528 ps
CPU time 24.18 seconds
Started Jun 05 05:16:52 PM PDT 24
Finished Jun 05 05:17:17 PM PDT 24
Peak memory 211384 kb
Host smart-80436f16-f1ee-4ffd-8a80-e6e979b1c9e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536948765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3536948765
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3494642104
Short name T266
Test name
Test status
Simulation time 6323619698 ps
CPU time 237.36 seconds
Started Jun 05 05:16:50 PM PDT 24
Finished Jun 05 05:20:48 PM PDT 24
Peak memory 224612 kb
Host smart-75a31dad-ccbd-45cc-b60a-eeb58dc86a5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494642104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3494642104
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2822495723
Short name T25
Test name
Test status
Simulation time 350020213 ps
CPU time 19.29 seconds
Started Jun 05 05:16:52 PM PDT 24
Finished Jun 05 05:17:12 PM PDT 24
Peak memory 214832 kb
Host smart-485d25d0-0f0f-4644-92be-f901768d7c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822495723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2822495723
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2104235769
Short name T189
Test name
Test status
Simulation time 1793195243 ps
CPU time 20.75 seconds
Started Jun 05 05:16:52 PM PDT 24
Finished Jun 05 05:17:14 PM PDT 24
Peak memory 211276 kb
Host smart-d459ea69-331a-4302-9f2e-80979ec2f157
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2104235769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2104235769
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3450080723
Short name T328
Test name
Test status
Simulation time 4282741968 ps
CPU time 20.05 seconds
Started Jun 05 05:16:50 PM PDT 24
Finished Jun 05 05:17:11 PM PDT 24
Peak memory 217256 kb
Host smart-c1d78269-1d7f-4a68-887f-94589c4f74b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450080723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3450080723
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.337907569
Short name T299
Test name
Test status
Simulation time 87340203382 ps
CPU time 101.35 seconds
Started Jun 05 05:16:51 PM PDT 24
Finished Jun 05 05:18:34 PM PDT 24
Peak memory 219420 kb
Host smart-d4b40195-0424-45ca-a5d1-fa40db92e466
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337907569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.337907569
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1199134656
Short name T169
Test name
Test status
Simulation time 49520310743 ps
CPU time 25.28 seconds
Started Jun 05 05:16:58 PM PDT 24
Finished Jun 05 05:17:24 PM PDT 24
Peak memory 212252 kb
Host smart-bd61947a-c47f-42f1-b990-ba6abca61063
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199134656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1199134656
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.4066420379
Short name T315
Test name
Test status
Simulation time 6633075151 ps
CPU time 447.53 seconds
Started Jun 05 05:16:54 PM PDT 24
Finished Jun 05 05:24:22 PM PDT 24
Peak memory 239432 kb
Host smart-df07210a-f323-441f-80c8-593fcd42dc0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066420379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.4066420379
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.371807708
Short name T342
Test name
Test status
Simulation time 16323012646 ps
CPU time 66.36 seconds
Started Jun 05 05:16:51 PM PDT 24
Finished Jun 05 05:17:58 PM PDT 24
Peak memory 217220 kb
Host smart-627b639f-5887-4be2-a448-5af1a559331b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371807708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.371807708
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2786195789
Short name T159
Test name
Test status
Simulation time 5687730762 ps
CPU time 27.01 seconds
Started Jun 05 05:16:52 PM PDT 24
Finished Jun 05 05:17:20 PM PDT 24
Peak memory 212812 kb
Host smart-f51a861f-0365-4fa1-a2d8-e6315ff2b23d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2786195789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2786195789
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3466983295
Short name T295
Test name
Test status
Simulation time 2758393802 ps
CPU time 38.08 seconds
Started Jun 05 05:16:52 PM PDT 24
Finished Jun 05 05:17:31 PM PDT 24
Peak memory 215832 kb
Host smart-64814451-9da5-43b9-adec-3726e4eb3156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466983295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3466983295
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.131216580
Short name T129
Test name
Test status
Simulation time 1955489152 ps
CPU time 37.61 seconds
Started Jun 05 05:16:52 PM PDT 24
Finished Jun 05 05:17:30 PM PDT 24
Peak memory 217516 kb
Host smart-8d04215b-bec7-4e1e-af36-a1ef1f2416f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131216580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.131216580
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.77127613
Short name T52
Test name
Test status
Simulation time 19216339066 ps
CPU time 730.14 seconds
Started Jun 05 05:16:49 PM PDT 24
Finished Jun 05 05:29:00 PM PDT 24
Peak memory 235768 kb
Host smart-3b71f18c-f627-4d69-ae06-68b7b7f17663
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77127613 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.77127613
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2457357880
Short name T339
Test name
Test status
Simulation time 331858079 ps
CPU time 8.53 seconds
Started Jun 05 05:16:59 PM PDT 24
Finished Jun 05 05:17:09 PM PDT 24
Peak memory 211316 kb
Host smart-39d072fe-b6f6-456f-a679-41caad8ff162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457357880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2457357880
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.694528466
Short name T192
Test name
Test status
Simulation time 28740217533 ps
CPU time 254.73 seconds
Started Jun 05 05:16:58 PM PDT 24
Finished Jun 05 05:21:13 PM PDT 24
Peak memory 224596 kb
Host smart-72afdbb0-0fff-4700-adaf-2a571ddaec7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694528466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.694528466
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2032847098
Short name T273
Test name
Test status
Simulation time 15413972702 ps
CPU time 67.53 seconds
Started Jun 05 05:16:58 PM PDT 24
Finished Jun 05 05:18:06 PM PDT 24
Peak memory 214968 kb
Host smart-9ef82059-bb10-4990-8896-1460ecee59e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032847098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2032847098
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1140975361
Short name T170
Test name
Test status
Simulation time 5014743377 ps
CPU time 15.33 seconds
Started Jun 05 05:16:59 PM PDT 24
Finished Jun 05 05:17:15 PM PDT 24
Peak memory 212816 kb
Host smart-76cf0193-c86f-46f8-bb7b-5465dd1f5836
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1140975361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1140975361
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1190329112
Short name T349
Test name
Test status
Simulation time 3947245174 ps
CPU time 43.47 seconds
Started Jun 05 05:17:00 PM PDT 24
Finished Jun 05 05:17:44 PM PDT 24
Peak memory 215692 kb
Host smart-a28ed183-6325-40b4-a5b8-d45a86e5c435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190329112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1190329112
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1090732835
Short name T345
Test name
Test status
Simulation time 7942715281 ps
CPU time 23.73 seconds
Started Jun 05 05:17:07 PM PDT 24
Finished Jun 05 05:17:32 PM PDT 24
Peak memory 212156 kb
Host smart-187845f0-b7bc-44f2-8bcb-21755b12f0e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090732835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1090732835
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.609030442
Short name T33
Test name
Test status
Simulation time 120706566515 ps
CPU time 582.23 seconds
Started Jun 05 05:17:01 PM PDT 24
Finished Jun 05 05:26:44 PM PDT 24
Peak memory 225460 kb
Host smart-74134b25-c81a-412f-96d5-65839109e14c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609030442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.609030442
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.761034922
Short name T288
Test name
Test status
Simulation time 339183316 ps
CPU time 19.18 seconds
Started Jun 05 05:17:00 PM PDT 24
Finished Jun 05 05:17:20 PM PDT 24
Peak memory 214904 kb
Host smart-4d8e0d0d-7436-4175-8cde-428c94872a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761034922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.761034922
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3949643582
Short name T156
Test name
Test status
Simulation time 4327713973 ps
CPU time 36.66 seconds
Started Jun 05 05:16:58 PM PDT 24
Finished Jun 05 05:17:35 PM PDT 24
Peak memory 211328 kb
Host smart-2a5d0a22-71f5-4ff0-abda-3b40c618a68b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3949643582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3949643582
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.395827826
Short name T59
Test name
Test status
Simulation time 1385281603 ps
CPU time 20.72 seconds
Started Jun 05 05:16:59 PM PDT 24
Finished Jun 05 05:17:20 PM PDT 24
Peak memory 217668 kb
Host smart-4a614802-2d52-440b-90ef-ebb36944a024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395827826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.395827826
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2888499706
Short name T238
Test name
Test status
Simulation time 1449529586 ps
CPU time 28.01 seconds
Started Jun 05 05:16:59 PM PDT 24
Finished Jun 05 05:17:28 PM PDT 24
Peak memory 217116 kb
Host smart-07ea539e-eee9-48dc-8115-15b7bfa0b34c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888499706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2888499706
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.170253855
Short name T318
Test name
Test status
Simulation time 2361212223 ps
CPU time 18.33 seconds
Started Jun 05 05:17:05 PM PDT 24
Finished Jun 05 05:17:24 PM PDT 24
Peak memory 211428 kb
Host smart-bcac27f9-389e-4950-8415-87beaedfa65a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170253855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.170253855
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.785440182
Short name T202
Test name
Test status
Simulation time 5732189925 ps
CPU time 138.84 seconds
Started Jun 05 05:17:07 PM PDT 24
Finished Jun 05 05:19:27 PM PDT 24
Peak memory 233628 kb
Host smart-85861971-422e-40a6-8467-eaa1fd2919e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785440182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.785440182
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3179125320
Short name T27
Test name
Test status
Simulation time 332610402 ps
CPU time 19.97 seconds
Started Jun 05 05:17:07 PM PDT 24
Finished Jun 05 05:17:27 PM PDT 24
Peak memory 214692 kb
Host smart-a9fd5627-15df-481d-99fb-b3c9d1f5a63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179125320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3179125320
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1967277392
Short name T161
Test name
Test status
Simulation time 5842242768 ps
CPU time 18.66 seconds
Started Jun 05 05:17:06 PM PDT 24
Finished Jun 05 05:17:25 PM PDT 24
Peak memory 212832 kb
Host smart-1833785b-12ab-4059-94c1-935aa1205535
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1967277392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1967277392
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.782107316
Short name T240
Test name
Test status
Simulation time 6999418964 ps
CPU time 60.79 seconds
Started Jun 05 05:17:05 PM PDT 24
Finished Jun 05 05:18:06 PM PDT 24
Peak memory 217820 kb
Host smart-6df14b35-db59-4eed-bdf4-d93ee2cb4d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782107316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.782107316
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1903928069
Short name T187
Test name
Test status
Simulation time 11838039950 ps
CPU time 56.35 seconds
Started Jun 05 05:17:06 PM PDT 24
Finished Jun 05 05:18:03 PM PDT 24
Peak memory 218264 kb
Host smart-25e52dfb-c204-42da-8c3c-4e5f382057b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903928069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1903928069
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1313445111
Short name T258
Test name
Test status
Simulation time 1098498869 ps
CPU time 8.22 seconds
Started Jun 05 05:17:13 PM PDT 24
Finished Jun 05 05:17:21 PM PDT 24
Peak memory 211568 kb
Host smart-589b53ca-e2ea-4435-9b22-d445e3cc77a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313445111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1313445111
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2905799188
Short name T135
Test name
Test status
Simulation time 141381801065 ps
CPU time 482.94 seconds
Started Jun 05 05:17:16 PM PDT 24
Finished Jun 05 05:25:19 PM PDT 24
Peak memory 239648 kb
Host smart-99e996eb-1bff-4cb4-aa46-849649dd63ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905799188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2905799188
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1597098522
Short name T43
Test name
Test status
Simulation time 3475832157 ps
CPU time 41.03 seconds
Started Jun 05 05:17:14 PM PDT 24
Finished Jun 05 05:17:55 PM PDT 24
Peak memory 214796 kb
Host smart-604d49cc-abc2-436c-83de-223eedba2a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597098522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1597098522
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3964948517
Short name T214
Test name
Test status
Simulation time 782064418 ps
CPU time 15.48 seconds
Started Jun 05 05:17:05 PM PDT 24
Finished Jun 05 05:17:20 PM PDT 24
Peak memory 212480 kb
Host smart-725fb444-d30d-4a42-bdb1-4728494a3815
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3964948517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3964948517
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.7339751
Short name T12
Test name
Test status
Simulation time 1380156487 ps
CPU time 19.74 seconds
Started Jun 05 05:17:07 PM PDT 24
Finished Jun 05 05:17:27 PM PDT 24
Peak memory 216600 kb
Host smart-b3789947-a344-4435-9063-0c1d7f87aa24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7339751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.7339751
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2618277996
Short name T237
Test name
Test status
Simulation time 7294050246 ps
CPU time 64.57 seconds
Started Jun 05 05:17:08 PM PDT 24
Finished Jun 05 05:18:13 PM PDT 24
Peak memory 218004 kb
Host smart-a07a65c4-bcef-425e-9fa2-c03f0a30f383
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618277996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2618277996
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1779177691
Short name T205
Test name
Test status
Simulation time 660716159 ps
CPU time 8.3 seconds
Started Jun 05 05:15:35 PM PDT 24
Finished Jun 05 05:15:44 PM PDT 24
Peak memory 211364 kb
Host smart-b6c6ed51-56a9-444d-a154-9fa111ed1204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779177691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1779177691
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3504254908
Short name T221
Test name
Test status
Simulation time 139134321456 ps
CPU time 281.78 seconds
Started Jun 05 05:15:28 PM PDT 24
Finished Jun 05 05:20:11 PM PDT 24
Peak memory 237228 kb
Host smart-dabcd0c1-cb1a-4cfb-87ed-f8b6fbf93046
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504254908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3504254908
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.29782484
Short name T47
Test name
Test status
Simulation time 5731102012 ps
CPU time 55.57 seconds
Started Jun 05 05:15:28 PM PDT 24
Finished Jun 05 05:16:25 PM PDT 24
Peak memory 215032 kb
Host smart-404e5df9-79dc-4e4e-ae2b-90058b286ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29782484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.29782484
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4204031738
Short name T196
Test name
Test status
Simulation time 687784760 ps
CPU time 10.38 seconds
Started Jun 05 05:15:28 PM PDT 24
Finished Jun 05 05:15:39 PM PDT 24
Peak memory 211520 kb
Host smart-aa274f7b-4e20-496e-98b1-0bddebd911db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4204031738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.4204031738
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3215260068
Short name T37
Test name
Test status
Simulation time 6685263779 ps
CPU time 128.27 seconds
Started Jun 05 05:15:36 PM PDT 24
Finished Jun 05 05:17:45 PM PDT 24
Peak memory 237524 kb
Host smart-63f2bdcd-2e38-4bea-9901-6fe77468e8af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215260068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3215260068
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3590506929
Short name T132
Test name
Test status
Simulation time 5072398380 ps
CPU time 47.77 seconds
Started Jun 05 05:15:46 PM PDT 24
Finished Jun 05 05:16:34 PM PDT 24
Peak memory 215328 kb
Host smart-0099a53f-4b41-4139-9107-2ae93862b85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590506929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3590506929
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.620547970
Short name T309
Test name
Test status
Simulation time 450996204 ps
CPU time 27.95 seconds
Started Jun 05 05:15:26 PM PDT 24
Finished Jun 05 05:15:55 PM PDT 24
Peak memory 211600 kb
Host smart-710e9eba-9a0a-4594-ae68-62c69f317a34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620547970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.620547970
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1006584974
Short name T46
Test name
Test status
Simulation time 6755339296 ps
CPU time 29.36 seconds
Started Jun 05 05:17:20 PM PDT 24
Finished Jun 05 05:17:50 PM PDT 24
Peak memory 212176 kb
Host smart-9c3210a0-fe0c-4fbd-8418-66e662cca3dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006584974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1006584974
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3487928725
Short name T338
Test name
Test status
Simulation time 106495410933 ps
CPU time 239.91 seconds
Started Jun 05 05:17:16 PM PDT 24
Finished Jun 05 05:21:17 PM PDT 24
Peak memory 215980 kb
Host smart-52f4b468-1acd-411f-8886-4ffcc2225aba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487928725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3487928725
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3244826050
Short name T144
Test name
Test status
Simulation time 1731345250 ps
CPU time 30.68 seconds
Started Jun 05 05:17:16 PM PDT 24
Finished Jun 05 05:17:47 PM PDT 24
Peak memory 214572 kb
Host smart-52701602-6caf-4b21-b4f7-981a74a8c08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244826050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3244826050
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2632652701
Short name T270
Test name
Test status
Simulation time 185698786 ps
CPU time 10.08 seconds
Started Jun 05 05:17:14 PM PDT 24
Finished Jun 05 05:17:24 PM PDT 24
Peak memory 212188 kb
Host smart-1e9f43b4-f7b0-4157-ac8f-24a49a54ce48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2632652701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2632652701
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2410047164
Short name T138
Test name
Test status
Simulation time 2031465798 ps
CPU time 23.14 seconds
Started Jun 05 05:17:15 PM PDT 24
Finished Jun 05 05:17:38 PM PDT 24
Peak memory 215008 kb
Host smart-514e8882-8a96-4202-8599-684c0fab73f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410047164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2410047164
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3961580131
Short name T249
Test name
Test status
Simulation time 1514840658 ps
CPU time 24.74 seconds
Started Jun 05 05:17:15 PM PDT 24
Finished Jun 05 05:17:40 PM PDT 24
Peak memory 216844 kb
Host smart-f0482b70-d43c-4ef9-8325-c4ec2807ed79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961580131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3961580131
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.4194003974
Short name T317
Test name
Test status
Simulation time 4117824331 ps
CPU time 21.5 seconds
Started Jun 05 05:17:20 PM PDT 24
Finished Jun 05 05:17:42 PM PDT 24
Peak memory 211672 kb
Host smart-723dfea7-1a06-478d-aa24-d8b153f87fe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194003974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.4194003974
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4030753974
Short name T32
Test name
Test status
Simulation time 4134403717 ps
CPU time 297.45 seconds
Started Jun 05 05:17:21 PM PDT 24
Finished Jun 05 05:22:19 PM PDT 24
Peak memory 229456 kb
Host smart-203bcafb-48eb-4550-8df3-5c990bb70b45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030753974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.4030753974
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.825736165
Short name T201
Test name
Test status
Simulation time 6874430794 ps
CPU time 43.46 seconds
Started Jun 05 05:17:24 PM PDT 24
Finished Jun 05 05:18:08 PM PDT 24
Peak memory 215320 kb
Host smart-0c0210d0-81cd-453b-9e68-393cf70d7f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825736165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.825736165
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3345836268
Short name T185
Test name
Test status
Simulation time 1940090152 ps
CPU time 22.09 seconds
Started Jun 05 05:17:24 PM PDT 24
Finished Jun 05 05:17:47 PM PDT 24
Peak memory 211176 kb
Host smart-9f719af9-5c7f-49c7-8677-e9136fa2caea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3345836268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3345836268
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2647645030
Short name T16
Test name
Test status
Simulation time 15792907729 ps
CPU time 46.77 seconds
Started Jun 05 05:17:21 PM PDT 24
Finished Jun 05 05:18:08 PM PDT 24
Peak memory 217776 kb
Host smart-c9f55f1e-f7d6-4bd3-b0bb-67093c426c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647645030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2647645030
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1259601215
Short name T137
Test name
Test status
Simulation time 3576368743 ps
CPU time 52.69 seconds
Started Jun 05 05:17:21 PM PDT 24
Finished Jun 05 05:18:14 PM PDT 24
Peak memory 219260 kb
Host smart-4eee89da-b0aa-46d7-a3f8-45e44aac1f55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259601215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1259601215
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.739348698
Short name T344
Test name
Test status
Simulation time 169104051 ps
CPU time 8.46 seconds
Started Jun 05 05:17:32 PM PDT 24
Finished Jun 05 05:17:41 PM PDT 24
Peak memory 211364 kb
Host smart-d23ed872-cee3-46cd-95f0-83635be42165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739348698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.739348698
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2855144388
Short name T193
Test name
Test status
Simulation time 171005568431 ps
CPU time 813.74 seconds
Started Jun 05 05:17:32 PM PDT 24
Finished Jun 05 05:31:07 PM PDT 24
Peak memory 239264 kb
Host smart-e675e2d8-7dd5-4b49-923d-fab357406c66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855144388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2855144388
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.4248553769
Short name T327
Test name
Test status
Simulation time 1127388989 ps
CPU time 24.92 seconds
Started Jun 05 05:17:31 PM PDT 24
Finished Jun 05 05:17:57 PM PDT 24
Peak memory 214780 kb
Host smart-e16cf510-8a73-4930-a881-76761f720bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248553769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.4248553769
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2374979556
Short name T283
Test name
Test status
Simulation time 2275171149 ps
CPU time 23.65 seconds
Started Jun 05 05:17:29 PM PDT 24
Finished Jun 05 05:17:54 PM PDT 24
Peak memory 212180 kb
Host smart-5d4c0651-f9de-40f5-87d8-da8a725a33e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2374979556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2374979556
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3061830523
Short name T203
Test name
Test status
Simulation time 11905580994 ps
CPU time 61.08 seconds
Started Jun 05 05:17:21 PM PDT 24
Finished Jun 05 05:18:22 PM PDT 24
Peak memory 217564 kb
Host smart-0bbc8341-5a5e-4ade-924a-867845fdfb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061830523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3061830523
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3507498544
Short name T326
Test name
Test status
Simulation time 6062581620 ps
CPU time 65.75 seconds
Started Jun 05 05:17:21 PM PDT 24
Finished Jun 05 05:18:27 PM PDT 24
Peak memory 219180 kb
Host smart-c06756f9-9ad8-449e-a9b8-5cc19ecd955c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507498544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3507498544
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1638253563
Short name T267
Test name
Test status
Simulation time 4097431914 ps
CPU time 19.75 seconds
Started Jun 05 05:17:37 PM PDT 24
Finished Jun 05 05:17:57 PM PDT 24
Peak memory 211416 kb
Host smart-41d50df5-f6f0-4dc2-abf0-59023f303c42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638253563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1638253563
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3460343984
Short name T216
Test name
Test status
Simulation time 233770551198 ps
CPU time 566.72 seconds
Started Jun 05 05:17:29 PM PDT 24
Finished Jun 05 05:26:56 PM PDT 24
Peak memory 216664 kb
Host smart-12a34bbb-946b-4330-a95e-69030a5cd133
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460343984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3460343984
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3699849790
Short name T171
Test name
Test status
Simulation time 50365446142 ps
CPU time 64.93 seconds
Started Jun 05 05:17:32 PM PDT 24
Finished Jun 05 05:18:38 PM PDT 24
Peak memory 215124 kb
Host smart-9e1ba261-b54c-4075-b2a1-1f41ca6c1a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699849790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3699849790
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1111851447
Short name T254
Test name
Test status
Simulation time 5902889120 ps
CPU time 31.26 seconds
Started Jun 05 05:17:30 PM PDT 24
Finished Jun 05 05:18:02 PM PDT 24
Peak memory 211276 kb
Host smart-66894272-3fc5-4d10-bbc9-d4a6893e60c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1111851447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1111851447
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1126776613
Short name T229
Test name
Test status
Simulation time 1433307822 ps
CPU time 19.46 seconds
Started Jun 05 05:17:32 PM PDT 24
Finished Jun 05 05:17:52 PM PDT 24
Peak memory 216928 kb
Host smart-68849f2a-914a-4819-8782-3d32a7ad6f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126776613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1126776613
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.656897538
Short name T307
Test name
Test status
Simulation time 12334653629 ps
CPU time 108.58 seconds
Started Jun 05 05:17:32 PM PDT 24
Finished Jun 05 05:19:22 PM PDT 24
Peak memory 219252 kb
Host smart-7fa14676-24e1-4606-a0c5-6060105a23d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656897538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.656897538
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4018616027
Short name T163
Test name
Test status
Simulation time 3886569249 ps
CPU time 29.82 seconds
Started Jun 05 05:17:44 PM PDT 24
Finished Jun 05 05:18:15 PM PDT 24
Peak memory 211856 kb
Host smart-dcbfb5a9-126b-4148-8cdd-76816f8e7f0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018616027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4018616027
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1602761275
Short name T336
Test name
Test status
Simulation time 417516255285 ps
CPU time 323.07 seconds
Started Jun 05 05:17:39 PM PDT 24
Finished Jun 05 05:23:02 PM PDT 24
Peak memory 228264 kb
Host smart-79bd1210-8551-4506-b823-e30354a7c887
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602761275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1602761275
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.273959015
Short name T316
Test name
Test status
Simulation time 28269246302 ps
CPU time 63.83 seconds
Started Jun 05 05:17:44 PM PDT 24
Finished Jun 05 05:18:49 PM PDT 24
Peak memory 213904 kb
Host smart-b3cfb406-ab61-4642-9b5a-d154f34ca861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273959015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.273959015
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2790844705
Short name T173
Test name
Test status
Simulation time 15262978988 ps
CPU time 30.06 seconds
Started Jun 05 05:17:38 PM PDT 24
Finished Jun 05 05:18:09 PM PDT 24
Peak memory 211624 kb
Host smart-feb8d384-5b08-4de5-8681-6e55850e8292
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2790844705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2790844705
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.218765210
Short name T86
Test name
Test status
Simulation time 7525671632 ps
CPU time 71.05 seconds
Started Jun 05 05:17:38 PM PDT 24
Finished Jun 05 05:18:50 PM PDT 24
Peak memory 218324 kb
Host smart-a4f535d8-91fb-4363-a805-2ea00cb5c163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218765210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.218765210
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1788917178
Short name T286
Test name
Test status
Simulation time 1483251998 ps
CPU time 43.21 seconds
Started Jun 05 05:17:38 PM PDT 24
Finished Jun 05 05:18:22 PM PDT 24
Peak memory 219024 kb
Host smart-e4163f7f-2c55-4a53-b619-6c16a503dc64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788917178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1788917178
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3777301068
Short name T280
Test name
Test status
Simulation time 848033205 ps
CPU time 13.78 seconds
Started Jun 05 05:17:46 PM PDT 24
Finished Jun 05 05:18:01 PM PDT 24
Peak memory 211340 kb
Host smart-c8e556b9-b41e-459c-81f4-c9c3cb72f9e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777301068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3777301068
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.729505856
Short name T346
Test name
Test status
Simulation time 3822542984 ps
CPU time 250.73 seconds
Started Jun 05 05:17:37 PM PDT 24
Finished Jun 05 05:21:49 PM PDT 24
Peak memory 240684 kb
Host smart-2b8a34a7-d2d6-4a0a-bfa5-9175e5c08384
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729505856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.729505856
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1720208998
Short name T321
Test name
Test status
Simulation time 3115049430 ps
CPU time 39.61 seconds
Started Jun 05 05:17:48 PM PDT 24
Finished Jun 05 05:18:28 PM PDT 24
Peak memory 214708 kb
Host smart-0945bbf4-5547-4bd6-9c24-28ff981b5f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720208998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1720208998
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3133770530
Short name T1
Test name
Test status
Simulation time 180199773 ps
CPU time 10.79 seconds
Started Jun 05 05:17:39 PM PDT 24
Finished Jun 05 05:17:50 PM PDT 24
Peak memory 211512 kb
Host smart-c68159fc-bc8a-466a-bf0d-bcedc1c54c39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3133770530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3133770530
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3717515038
Short name T285
Test name
Test status
Simulation time 2721808057 ps
CPU time 36.94 seconds
Started Jun 05 05:17:44 PM PDT 24
Finished Jun 05 05:18:21 PM PDT 24
Peak memory 217344 kb
Host smart-dfead036-79f8-4a64-851f-48f291ccd6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717515038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3717515038
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1701959729
Short name T220
Test name
Test status
Simulation time 8779581031 ps
CPU time 81.74 seconds
Started Jun 05 05:17:36 PM PDT 24
Finished Jun 05 05:18:58 PM PDT 24
Peak memory 219268 kb
Host smart-08005620-53c2-47ba-b19f-adc1ece586ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701959729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1701959729
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.4161054382
Short name T74
Test name
Test status
Simulation time 7370550900 ps
CPU time 30.6 seconds
Started Jun 05 05:17:44 PM PDT 24
Finished Jun 05 05:18:15 PM PDT 24
Peak memory 212244 kb
Host smart-0969cb4d-6315-4cbc-b045-a47cd70f3cb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161054382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.4161054382
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.508383225
Short name T269
Test name
Test status
Simulation time 37546770451 ps
CPU time 416.59 seconds
Started Jun 05 05:17:49 PM PDT 24
Finished Jun 05 05:24:46 PM PDT 24
Peak memory 233612 kb
Host smart-6209d0e6-b7b6-4b6d-bb69-8db08f4e5cae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508383225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.508383225
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3156881333
Short name T298
Test name
Test status
Simulation time 9228875998 ps
CPU time 69.27 seconds
Started Jun 05 05:17:44 PM PDT 24
Finished Jun 05 05:18:54 PM PDT 24
Peak memory 215024 kb
Host smart-4e680c4f-24e0-48e2-814f-c9f2d0703979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156881333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3156881333
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.286815138
Short name T212
Test name
Test status
Simulation time 8180882111 ps
CPU time 22.69 seconds
Started Jun 05 05:17:49 PM PDT 24
Finished Jun 05 05:18:12 PM PDT 24
Peak memory 212752 kb
Host smart-38239339-66b4-4dbf-a800-f555360a9dbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=286815138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.286815138
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2809479816
Short name T30
Test name
Test status
Simulation time 8732495126 ps
CPU time 68.86 seconds
Started Jun 05 05:17:45 PM PDT 24
Finished Jun 05 05:18:55 PM PDT 24
Peak memory 216884 kb
Host smart-4116b3ff-b129-402b-a8c5-489090439f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809479816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2809479816
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.2135696714
Short name T7
Test name
Test status
Simulation time 18557547204 ps
CPU time 118.59 seconds
Started Jun 05 05:17:44 PM PDT 24
Finished Jun 05 05:19:43 PM PDT 24
Peak memory 220320 kb
Host smart-e12e1d37-018c-4722-b9b6-1ba735f4b815
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135696714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.2135696714
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2677435998
Short name T54
Test name
Test status
Simulation time 27068852478 ps
CPU time 1077.46 seconds
Started Jun 05 05:17:44 PM PDT 24
Finished Jun 05 05:35:42 PM PDT 24
Peak memory 230224 kb
Host smart-f9399c7c-a1f7-46a8-9f80-0903a0b7f71e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677435998 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.2677435998
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2361547541
Short name T322
Test name
Test status
Simulation time 689572977 ps
CPU time 8.15 seconds
Started Jun 05 05:17:53 PM PDT 24
Finished Jun 05 05:18:01 PM PDT 24
Peak memory 211360 kb
Host smart-e7698922-ef3a-46c7-bdd0-636335810d96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361547541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2361547541
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1047519105
Short name T305
Test name
Test status
Simulation time 29645776526 ps
CPU time 583.85 seconds
Started Jun 05 05:17:52 PM PDT 24
Finished Jun 05 05:27:37 PM PDT 24
Peak memory 234344 kb
Host smart-69b34d0c-a800-41e6-96c8-d6f77be6844b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047519105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1047519105
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1505142597
Short name T278
Test name
Test status
Simulation time 7471783030 ps
CPU time 25.96 seconds
Started Jun 05 05:17:52 PM PDT 24
Finished Jun 05 05:18:19 PM PDT 24
Peak memory 213196 kb
Host smart-7e7e06cd-2b8f-404d-99c4-68f1c4b82508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505142597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1505142597
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.123090368
Short name T337
Test name
Test status
Simulation time 5692012921 ps
CPU time 28.87 seconds
Started Jun 05 05:17:52 PM PDT 24
Finished Jun 05 05:18:21 PM PDT 24
Peak memory 211304 kb
Host smart-42a302b5-ddb0-4b0c-9a82-47f5a650bada
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=123090368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.123090368
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.537164029
Short name T250
Test name
Test status
Simulation time 8349832149 ps
CPU time 66.79 seconds
Started Jun 05 05:17:46 PM PDT 24
Finished Jun 05 05:18:54 PM PDT 24
Peak memory 216796 kb
Host smart-80560cd9-4494-4964-ad1d-d7105cffe743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537164029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.537164029
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1164029263
Short name T62
Test name
Test status
Simulation time 50526570775 ps
CPU time 103.26 seconds
Started Jun 05 05:17:44 PM PDT 24
Finished Jun 05 05:19:28 PM PDT 24
Peak memory 216560 kb
Host smart-db1d6493-f32e-44bf-84a4-03e69e557497
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164029263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1164029263
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.4069785439
Short name T5
Test name
Test status
Simulation time 14280237727 ps
CPU time 31.88 seconds
Started Jun 05 05:17:49 PM PDT 24
Finished Jun 05 05:18:22 PM PDT 24
Peak memory 212156 kb
Host smart-61a98b32-ed0f-422f-af7f-4c5818a4fa6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069785439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.4069785439
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4271427165
Short name T136
Test name
Test status
Simulation time 8648190499 ps
CPU time 238.47 seconds
Started Jun 05 05:17:53 PM PDT 24
Finished Jun 05 05:21:52 PM PDT 24
Peak memory 240800 kb
Host smart-9bff7ba4-61ca-432b-af48-647f1741efc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271427165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4271427165
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.273834549
Short name T313
Test name
Test status
Simulation time 10112247088 ps
CPU time 46.31 seconds
Started Jun 05 05:17:55 PM PDT 24
Finished Jun 05 05:18:42 PM PDT 24
Peak memory 215092 kb
Host smart-ca4ab97f-b52f-4009-be97-9e0a87257230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273834549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.273834549
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1257956762
Short name T183
Test name
Test status
Simulation time 184788702 ps
CPU time 10.78 seconds
Started Jun 05 05:17:53 PM PDT 24
Finished Jun 05 05:18:05 PM PDT 24
Peak memory 212444 kb
Host smart-bce505dc-6fc5-448f-a0ae-1539ed2a10d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1257956762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1257956762
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2589981105
Short name T302
Test name
Test status
Simulation time 1377275827 ps
CPU time 20.41 seconds
Started Jun 05 05:17:51 PM PDT 24
Finished Jun 05 05:18:12 PM PDT 24
Peak memory 216376 kb
Host smart-76189cb8-9be9-4154-990c-94995a133a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589981105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2589981105
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.4235795105
Short name T252
Test name
Test status
Simulation time 12464701466 ps
CPU time 29.32 seconds
Started Jun 05 05:17:56 PM PDT 24
Finished Jun 05 05:18:25 PM PDT 24
Peak memory 212816 kb
Host smart-807d7b0c-22c6-41e4-a87d-33a08e236b76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235795105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.4235795105
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.527986912
Short name T308
Test name
Test status
Simulation time 167386895 ps
CPU time 8.71 seconds
Started Jun 05 05:17:59 PM PDT 24
Finished Jun 05 05:18:09 PM PDT 24
Peak memory 211364 kb
Host smart-f6f5d86f-dd3c-4caf-8346-2270c3ace509
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527986912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.527986912
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3081578527
Short name T228
Test name
Test status
Simulation time 325719725971 ps
CPU time 974.57 seconds
Started Jun 05 05:18:00 PM PDT 24
Finished Jun 05 05:34:15 PM PDT 24
Peak memory 234748 kb
Host smart-5447dc01-b618-4c38-b68d-c90eb268525b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081578527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3081578527
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2416783584
Short name T186
Test name
Test status
Simulation time 9178630310 ps
CPU time 34.58 seconds
Started Jun 05 05:17:59 PM PDT 24
Finished Jun 05 05:18:34 PM PDT 24
Peak memory 215468 kb
Host smart-842860e5-348f-4572-ac0f-fc2569c1c923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416783584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2416783584
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.193012313
Short name T14
Test name
Test status
Simulation time 1119943175 ps
CPU time 17.38 seconds
Started Jun 05 05:18:02 PM PDT 24
Finished Jun 05 05:18:20 PM PDT 24
Peak memory 212256 kb
Host smart-dc821c4a-524b-4558-9c0e-a53aeaaf142c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=193012313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.193012313
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.219302386
Short name T261
Test name
Test status
Simulation time 10500769658 ps
CPU time 59.07 seconds
Started Jun 05 05:17:53 PM PDT 24
Finished Jun 05 05:18:53 PM PDT 24
Peak memory 215684 kb
Host smart-dff97227-a02e-47dc-9394-6858ffad3135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219302386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.219302386
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.267017040
Short name T128
Test name
Test status
Simulation time 1763492994 ps
CPU time 81 seconds
Started Jun 05 05:18:05 PM PDT 24
Finished Jun 05 05:19:27 PM PDT 24
Peak memory 227376 kb
Host smart-de7aaf47-8009-4870-b9e4-799e25a97b93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267017040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.267017040
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1759418716
Short name T73
Test name
Test status
Simulation time 15729927706 ps
CPU time 31.75 seconds
Started Jun 05 05:15:35 PM PDT 24
Finished Jun 05 05:16:07 PM PDT 24
Peak memory 212132 kb
Host smart-af72f550-63c8-478c-8afe-fcf99820ddd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759418716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1759418716
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.40706025
Short name T40
Test name
Test status
Simulation time 43987469733 ps
CPU time 660.9 seconds
Started Jun 05 05:15:44 PM PDT 24
Finished Jun 05 05:26:46 PM PDT 24
Peak memory 237700 kb
Host smart-3b51333e-92f5-4505-a6b7-fbfa1596f1e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40706025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_cor
rupt_sig_fatal_chk.40706025
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.910224408
Short name T257
Test name
Test status
Simulation time 17675450385 ps
CPU time 48.5 seconds
Started Jun 05 05:15:34 PM PDT 24
Finished Jun 05 05:16:23 PM PDT 24
Peak memory 215004 kb
Host smart-70570aa8-b1b7-426a-b8ca-72eb8d8de6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910224408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.910224408
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1577906822
Short name T335
Test name
Test status
Simulation time 10173731993 ps
CPU time 26.22 seconds
Started Jun 05 05:15:36 PM PDT 24
Finished Jun 05 05:16:04 PM PDT 24
Peak memory 211700 kb
Host smart-62938c02-12b7-4e59-a9b8-455b24a7fa23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1577906822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1577906822
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3046894586
Short name T36
Test name
Test status
Simulation time 405085215 ps
CPU time 232.25 seconds
Started Jun 05 05:15:38 PM PDT 24
Finished Jun 05 05:19:31 PM PDT 24
Peak memory 237956 kb
Host smart-da5d7e9b-5cfb-4526-b81e-0b883c642d29
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046894586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3046894586
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.425285521
Short name T147
Test name
Test status
Simulation time 1196227855 ps
CPU time 20.2 seconds
Started Jun 05 05:15:35 PM PDT 24
Finished Jun 05 05:15:56 PM PDT 24
Peak memory 217688 kb
Host smart-ae8ac144-2fa6-4314-9167-6ec1013d9414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425285521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.425285521
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.531840069
Short name T130
Test name
Test status
Simulation time 8258268024 ps
CPU time 73.45 seconds
Started Jun 05 05:15:39 PM PDT 24
Finished Jun 05 05:16:53 PM PDT 24
Peak memory 220424 kb
Host smart-59fd939a-a022-4ab5-b948-52b89a975532
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531840069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.531840069
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.213625957
Short name T184
Test name
Test status
Simulation time 688808540 ps
CPU time 8.25 seconds
Started Jun 05 05:17:59 PM PDT 24
Finished Jun 05 05:18:08 PM PDT 24
Peak memory 211340 kb
Host smart-64726052-c580-482c-9a70-bbd83a718655
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213625957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.213625957
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2983652193
Short name T13
Test name
Test status
Simulation time 14711783110 ps
CPU time 280.71 seconds
Started Jun 05 05:17:59 PM PDT 24
Finished Jun 05 05:22:40 PM PDT 24
Peak memory 229452 kb
Host smart-c84a86b7-ed7a-4707-b7fd-39e5da1b6cc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983652193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2983652193
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.691024108
Short name T2
Test name
Test status
Simulation time 4436134036 ps
CPU time 45.75 seconds
Started Jun 05 05:17:58 PM PDT 24
Finished Jun 05 05:18:45 PM PDT 24
Peak memory 215196 kb
Host smart-1bca3d2c-0d97-4844-96a2-001bbf06aa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691024108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.691024108
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2836129381
Short name T152
Test name
Test status
Simulation time 3403359336 ps
CPU time 28.34 seconds
Started Jun 05 05:18:00 PM PDT 24
Finished Jun 05 05:18:29 PM PDT 24
Peak memory 211248 kb
Host smart-3843a78e-6e8a-42a9-b619-fb8953c9c6ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2836129381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2836129381
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1736009789
Short name T265
Test name
Test status
Simulation time 24687135188 ps
CPU time 55.04 seconds
Started Jun 05 05:18:01 PM PDT 24
Finished Jun 05 05:18:56 PM PDT 24
Peak memory 218140 kb
Host smart-253cefa9-3309-4b8f-92fc-cd927e352f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736009789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1736009789
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.465613072
Short name T352
Test name
Test status
Simulation time 1735242132 ps
CPU time 24.75 seconds
Started Jun 05 05:18:00 PM PDT 24
Finished Jun 05 05:18:25 PM PDT 24
Peak memory 217520 kb
Host smart-af5d3fef-bb09-4eb0-b618-ee5463530f15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465613072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.465613072
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2710823687
Short name T44
Test name
Test status
Simulation time 3236989125 ps
CPU time 25.87 seconds
Started Jun 05 05:17:59 PM PDT 24
Finished Jun 05 05:18:26 PM PDT 24
Peak memory 211888 kb
Host smart-d1df3ce1-a3f7-4101-a196-5ff1f41422b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710823687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2710823687
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3946568067
Short name T291
Test name
Test status
Simulation time 35648609848 ps
CPU time 375.53 seconds
Started Jun 05 05:18:03 PM PDT 24
Finished Jun 05 05:24:19 PM PDT 24
Peak memory 216920 kb
Host smart-73d6b966-261b-4a66-9f7b-9be4cc46d318
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946568067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3946568067
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2980130557
Short name T20
Test name
Test status
Simulation time 6176214185 ps
CPU time 39.39 seconds
Started Jun 05 05:18:04 PM PDT 24
Finished Jun 05 05:18:44 PM PDT 24
Peak memory 215292 kb
Host smart-c4e68a5e-f25e-4484-a193-535a5e0edd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980130557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2980130557
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3227159901
Short name T333
Test name
Test status
Simulation time 5615417750 ps
CPU time 25.46 seconds
Started Jun 05 05:18:00 PM PDT 24
Finished Jun 05 05:18:26 PM PDT 24
Peak memory 212452 kb
Host smart-13871a66-475d-4ee1-9a17-262dd74e0f23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3227159901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3227159901
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2017036426
Short name T60
Test name
Test status
Simulation time 44117842870 ps
CPU time 63.84 seconds
Started Jun 05 05:18:00 PM PDT 24
Finished Jun 05 05:19:04 PM PDT 24
Peak memory 218280 kb
Host smart-5ff69e3f-8282-487b-8cbe-64751b099087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017036426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2017036426
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3243230034
Short name T312
Test name
Test status
Simulation time 63901117043 ps
CPU time 100.17 seconds
Started Jun 05 05:18:03 PM PDT 24
Finished Jun 05 05:19:44 PM PDT 24
Peak memory 219252 kb
Host smart-a9f5367a-fe9c-4f53-a838-94b56b20d524
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243230034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3243230034
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1184335418
Short name T29
Test name
Test status
Simulation time 108212795510 ps
CPU time 608.33 seconds
Started Jun 05 05:18:12 PM PDT 24
Finished Jun 05 05:28:21 PM PDT 24
Peak memory 240636 kb
Host smart-0b9c5f2a-767b-4550-8274-87732344049d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184335418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1184335418
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3402610968
Short name T142
Test name
Test status
Simulation time 6520407683 ps
CPU time 56.08 seconds
Started Jun 05 05:18:13 PM PDT 24
Finished Jun 05 05:19:10 PM PDT 24
Peak memory 212928 kb
Host smart-1473e2e7-678f-41eb-8643-4108e9325d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402610968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3402610968
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2408039336
Short name T179
Test name
Test status
Simulation time 2473455877 ps
CPU time 25.19 seconds
Started Jun 05 05:18:13 PM PDT 24
Finished Jun 05 05:18:39 PM PDT 24
Peak memory 211236 kb
Host smart-ccaad600-1b2b-4cab-a391-53b930e6eca2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2408039336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2408039336
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.98461006
Short name T300
Test name
Test status
Simulation time 7271595121 ps
CPU time 62.35 seconds
Started Jun 05 05:17:58 PM PDT 24
Finished Jun 05 05:19:01 PM PDT 24
Peak memory 217588 kb
Host smart-a596af8d-aae3-4953-a4a4-a4a585fe991d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98461006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.98461006
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.689822456
Short name T276
Test name
Test status
Simulation time 15150381266 ps
CPU time 153.68 seconds
Started Jun 05 05:18:02 PM PDT 24
Finished Jun 05 05:20:36 PM PDT 24
Peak memory 220956 kb
Host smart-72c73401-d7c5-4e58-9120-193f5fc0f563
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689822456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.689822456
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.4254819903
Short name T180
Test name
Test status
Simulation time 9176663451 ps
CPU time 21.95 seconds
Started Jun 05 05:18:12 PM PDT 24
Finished Jun 05 05:18:35 PM PDT 24
Peak memory 212316 kb
Host smart-9d2fccc9-d593-4f6f-b3c0-af77cdc8e592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254819903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.4254819903
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3668299812
Short name T223
Test name
Test status
Simulation time 7702846163 ps
CPU time 139.87 seconds
Started Jun 05 05:18:12 PM PDT 24
Finished Jun 05 05:20:33 PM PDT 24
Peak memory 239884 kb
Host smart-eb0d2274-fcc7-4939-8075-7f32e68005a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668299812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3668299812
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1230435578
Short name T354
Test name
Test status
Simulation time 21768733424 ps
CPU time 50.33 seconds
Started Jun 05 05:18:13 PM PDT 24
Finished Jun 05 05:19:04 PM PDT 24
Peak memory 214932 kb
Host smart-1358f00f-759b-45ce-a907-7cfabc1abbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230435578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1230435578
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.166200512
Short name T329
Test name
Test status
Simulation time 14220823456 ps
CPU time 20.21 seconds
Started Jun 05 05:18:13 PM PDT 24
Finished Jun 05 05:18:34 PM PDT 24
Peak memory 213044 kb
Host smart-3669d033-5c4a-4e8f-bc30-d369dca31573
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=166200512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.166200512
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1090218903
Short name T356
Test name
Test status
Simulation time 439730893 ps
CPU time 20.41 seconds
Started Jun 05 05:18:12 PM PDT 24
Finished Jun 05 05:18:34 PM PDT 24
Peak memory 217196 kb
Host smart-f49f97f7-96ea-4b1b-9374-2269a9d762ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090218903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1090218903
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2281435733
Short name T246
Test name
Test status
Simulation time 9302567172 ps
CPU time 40.2 seconds
Started Jun 05 05:18:14 PM PDT 24
Finished Jun 05 05:18:55 PM PDT 24
Peak memory 216096 kb
Host smart-69193a75-b3b2-4a49-bb6b-75b034660a62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281435733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2281435733
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1511550404
Short name T55
Test name
Test status
Simulation time 21743714331 ps
CPU time 850.71 seconds
Started Jun 05 05:18:12 PM PDT 24
Finished Jun 05 05:32:24 PM PDT 24
Peak memory 230044 kb
Host smart-18b31427-fb76-493d-be85-62e67a2ef904
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511550404 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1511550404
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.4034113232
Short name T242
Test name
Test status
Simulation time 5148106841 ps
CPU time 23.66 seconds
Started Jun 05 05:18:15 PM PDT 24
Finished Jun 05 05:18:39 PM PDT 24
Peak memory 211384 kb
Host smart-7597134e-4028-4d48-a991-35392745b08e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034113232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.4034113232
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1754109608
Short name T4
Test name
Test status
Simulation time 7028961660 ps
CPU time 62.2 seconds
Started Jun 05 05:18:11 PM PDT 24
Finished Jun 05 05:19:14 PM PDT 24
Peak memory 215208 kb
Host smart-a3323360-6587-4279-aca9-8db112d2428f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754109608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1754109608
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1532452856
Short name T314
Test name
Test status
Simulation time 355228741 ps
CPU time 10.75 seconds
Started Jun 05 05:18:13 PM PDT 24
Finished Jun 05 05:18:25 PM PDT 24
Peak memory 212452 kb
Host smart-7311efef-e10f-4b46-8b9e-8605314e97f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1532452856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1532452856
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1580896214
Short name T168
Test name
Test status
Simulation time 4582317652 ps
CPU time 47.63 seconds
Started Jun 05 05:18:12 PM PDT 24
Finished Jun 05 05:19:01 PM PDT 24
Peak memory 217272 kb
Host smart-494306e0-1714-4dd9-b058-48dcfa21d3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580896214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1580896214
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.303336647
Short name T331
Test name
Test status
Simulation time 14424548694 ps
CPU time 107.08 seconds
Started Jun 05 05:18:11 PM PDT 24
Finished Jun 05 05:19:59 PM PDT 24
Peak memory 220396 kb
Host smart-ba6f480c-c549-4077-983a-c19cdf4baba0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303336647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.303336647
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2341531731
Short name T71
Test name
Test status
Simulation time 2951766490 ps
CPU time 27 seconds
Started Jun 05 05:18:14 PM PDT 24
Finished Jun 05 05:18:42 PM PDT 24
Peak memory 211644 kb
Host smart-ba395d0f-5eb2-4c83-8967-2a5617c8bc16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341531731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2341531731
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2248244862
Short name T48
Test name
Test status
Simulation time 82860804805 ps
CPU time 812.66 seconds
Started Jun 05 05:18:10 PM PDT 24
Finished Jun 05 05:31:43 PM PDT 24
Peak memory 225552 kb
Host smart-1ef5af59-30e4-43d7-a6b8-30a27c7c1254
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248244862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2248244862
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3191990174
Short name T149
Test name
Test status
Simulation time 7889684209 ps
CPU time 32.98 seconds
Started Jun 05 05:18:11 PM PDT 24
Finished Jun 05 05:18:45 PM PDT 24
Peak memory 215304 kb
Host smart-f07fbe4c-aca2-4171-820e-727ff08a7d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191990174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3191990174
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.329533822
Short name T241
Test name
Test status
Simulation time 5398255219 ps
CPU time 25.59 seconds
Started Jun 05 05:18:13 PM PDT 24
Finished Jun 05 05:18:39 PM PDT 24
Peak memory 212596 kb
Host smart-74fefcbb-62e9-4679-aa7b-55ca98935a25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=329533822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.329533822
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1785927952
Short name T41
Test name
Test status
Simulation time 5598774490 ps
CPU time 57.87 seconds
Started Jun 05 05:18:13 PM PDT 24
Finished Jun 05 05:19:11 PM PDT 24
Peak memory 216288 kb
Host smart-484a19b4-6df4-443b-a55d-b569fd344061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785927952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1785927952
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.927538386
Short name T275
Test name
Test status
Simulation time 1790490507 ps
CPU time 43.78 seconds
Started Jun 05 05:18:12 PM PDT 24
Finished Jun 05 05:18:57 PM PDT 24
Peak memory 219232 kb
Host smart-6b235ecc-9b6b-4863-8541-1b9542283853
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927538386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.927538386
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2091900918
Short name T290
Test name
Test status
Simulation time 2069596375 ps
CPU time 22.16 seconds
Started Jun 05 05:18:20 PM PDT 24
Finished Jun 05 05:18:43 PM PDT 24
Peak memory 212104 kb
Host smart-f2d8c871-694c-4802-b987-02307fb7d315
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091900918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2091900918
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1150648261
Short name T253
Test name
Test status
Simulation time 8257000633 ps
CPU time 369.76 seconds
Started Jun 05 05:18:13 PM PDT 24
Finished Jun 05 05:24:24 PM PDT 24
Peak memory 237728 kb
Host smart-5e39c125-5746-40b9-be77-c7345a996b9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150648261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1150648261
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3944284629
Short name T166
Test name
Test status
Simulation time 17024653857 ps
CPU time 68.78 seconds
Started Jun 05 05:18:11 PM PDT 24
Finished Jun 05 05:19:21 PM PDT 24
Peak memory 214100 kb
Host smart-d4fc05c3-c65c-4d20-8fba-5220315ce0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944284629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3944284629
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1560580008
Short name T234
Test name
Test status
Simulation time 4820768477 ps
CPU time 18.22 seconds
Started Jun 05 05:18:14 PM PDT 24
Finished Jun 05 05:18:33 PM PDT 24
Peak memory 211708 kb
Host smart-3cec9922-127e-4a5b-82c9-837f91124f6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1560580008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1560580008
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2444994409
Short name T231
Test name
Test status
Simulation time 54654943788 ps
CPU time 67.74 seconds
Started Jun 05 05:18:12 PM PDT 24
Finished Jun 05 05:19:21 PM PDT 24
Peak memory 218528 kb
Host smart-69f9f1f7-3849-4e18-8ff0-099fffe729ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444994409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2444994409
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2263565332
Short name T164
Test name
Test status
Simulation time 28227250443 ps
CPU time 80.11 seconds
Started Jun 05 05:18:11 PM PDT 24
Finished Jun 05 05:19:32 PM PDT 24
Peak memory 219588 kb
Host smart-1b889c8d-e573-461f-8bfd-633f2978ba64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263565332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2263565332
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3962651263
Short name T347
Test name
Test status
Simulation time 3671330411 ps
CPU time 30.28 seconds
Started Jun 05 05:18:20 PM PDT 24
Finished Jun 05 05:18:51 PM PDT 24
Peak memory 211952 kb
Host smart-302be29a-9952-4bfb-8bde-958daa127000
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962651263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3962651263
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.342961375
Short name T31
Test name
Test status
Simulation time 106581462059 ps
CPU time 574.85 seconds
Started Jun 05 05:18:20 PM PDT 24
Finished Jun 05 05:27:56 PM PDT 24
Peak memory 228920 kb
Host smart-21d9ca62-31a9-4569-a3bd-f14230f93aca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342961375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.342961375
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1603044353
Short name T146
Test name
Test status
Simulation time 3739263158 ps
CPU time 43.73 seconds
Started Jun 05 05:18:20 PM PDT 24
Finished Jun 05 05:19:04 PM PDT 24
Peak memory 214660 kb
Host smart-a0389da9-6a2f-4a24-929a-785385794040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603044353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1603044353
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1154422817
Short name T125
Test name
Test status
Simulation time 1323240488 ps
CPU time 18.68 seconds
Started Jun 05 05:18:20 PM PDT 24
Finished Jun 05 05:18:40 PM PDT 24
Peak memory 212428 kb
Host smart-9d042949-7df1-4e16-85bd-88de279bd60d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1154422817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1154422817
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3200180480
Short name T247
Test name
Test status
Simulation time 65668727963 ps
CPU time 63.73 seconds
Started Jun 05 05:18:20 PM PDT 24
Finished Jun 05 05:19:25 PM PDT 24
Peak memory 217416 kb
Host smart-6d4275d6-085f-427a-9300-f099fd787c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200180480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3200180480
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1333970446
Short name T91
Test name
Test status
Simulation time 751864290 ps
CPU time 44.07 seconds
Started Jun 05 05:18:22 PM PDT 24
Finished Jun 05 05:19:07 PM PDT 24
Peak memory 219220 kb
Host smart-4923d01e-0c96-4cda-aa1e-5ef8960bbc70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333970446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1333970446
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.4036818363
Short name T75
Test name
Test status
Simulation time 174329751 ps
CPU time 8.28 seconds
Started Jun 05 05:18:21 PM PDT 24
Finished Jun 05 05:18:30 PM PDT 24
Peak memory 211356 kb
Host smart-af1bfe76-204a-4798-8ab2-6e5e2f3593bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036818363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.4036818363
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2225093527
Short name T200
Test name
Test status
Simulation time 7590019905 ps
CPU time 157.84 seconds
Started Jun 05 05:18:24 PM PDT 24
Finished Jun 05 05:21:02 PM PDT 24
Peak memory 225468 kb
Host smart-0f9d545d-f1b5-43b8-86ae-695d4cc11498
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225093527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2225093527
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2196805456
Short name T153
Test name
Test status
Simulation time 9375783480 ps
CPU time 48.55 seconds
Started Jun 05 05:18:20 PM PDT 24
Finished Jun 05 05:19:10 PM PDT 24
Peak memory 215040 kb
Host smart-cb2f36b1-f71e-42db-8401-9624d8704af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196805456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2196805456
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2060675439
Short name T127
Test name
Test status
Simulation time 3701672124 ps
CPU time 22.22 seconds
Started Jun 05 05:18:23 PM PDT 24
Finished Jun 05 05:18:46 PM PDT 24
Peak memory 211308 kb
Host smart-99760d95-1044-4fc7-8e54-462a090012c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2060675439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2060675439
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3302216225
Short name T219
Test name
Test status
Simulation time 8727186332 ps
CPU time 85.39 seconds
Started Jun 05 05:18:21 PM PDT 24
Finished Jun 05 05:19:48 PM PDT 24
Peak memory 216620 kb
Host smart-0d2792ab-86f5-4e1e-9dd6-d0df4b7cad29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302216225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3302216225
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1222484603
Short name T271
Test name
Test status
Simulation time 1422010723 ps
CPU time 80.68 seconds
Started Jun 05 05:18:20 PM PDT 24
Finished Jun 05 05:19:42 PM PDT 24
Peak memory 219228 kb
Host smart-3bb1f2cf-85a9-46ab-a1a3-95fe2e06802c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222484603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1222484603
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3776248827
Short name T277
Test name
Test status
Simulation time 4249838004 ps
CPU time 15.66 seconds
Started Jun 05 05:18:21 PM PDT 24
Finished Jun 05 05:18:38 PM PDT 24
Peak memory 211420 kb
Host smart-199e491c-b3b3-4957-8cab-d0432e74da69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776248827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3776248827
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2974703802
Short name T204
Test name
Test status
Simulation time 2314936418 ps
CPU time 154.3 seconds
Started Jun 05 05:18:22 PM PDT 24
Finished Jun 05 05:20:57 PM PDT 24
Peak memory 224444 kb
Host smart-c805041e-e84f-4369-bbe4-099e566146a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974703802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2974703802
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3679276545
Short name T289
Test name
Test status
Simulation time 353786674 ps
CPU time 19.19 seconds
Started Jun 05 05:18:21 PM PDT 24
Finished Jun 05 05:18:41 PM PDT 24
Peak memory 214628 kb
Host smart-b33ee6f6-471e-43f2-9925-3ccfa564655e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679276545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3679276545
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3974415189
Short name T294
Test name
Test status
Simulation time 3321934283 ps
CPU time 16.45 seconds
Started Jun 05 05:18:24 PM PDT 24
Finished Jun 05 05:18:41 PM PDT 24
Peak memory 212532 kb
Host smart-878f236b-68bb-4c11-8996-dba99c1af28d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3974415189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3974415189
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2343196854
Short name T85
Test name
Test status
Simulation time 5611748056 ps
CPU time 62.07 seconds
Started Jun 05 05:18:21 PM PDT 24
Finished Jun 05 05:19:24 PM PDT 24
Peak memory 216844 kb
Host smart-c64233c5-c377-462b-8716-15ae9bec480f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343196854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2343196854
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.4197635732
Short name T311
Test name
Test status
Simulation time 930711533 ps
CPU time 23.92 seconds
Started Jun 05 05:18:20 PM PDT 24
Finished Jun 05 05:18:45 PM PDT 24
Peak memory 217460 kb
Host smart-8ac51077-a735-4848-9f78-dc0ee68e1640
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197635732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.4197635732
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2661430239
Short name T143
Test name
Test status
Simulation time 4140312185 ps
CPU time 32.2 seconds
Started Jun 05 05:15:36 PM PDT 24
Finished Jun 05 05:16:09 PM PDT 24
Peak memory 211868 kb
Host smart-217796e1-db96-4715-952f-bce237ef4446
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661430239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2661430239
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3601185325
Short name T211
Test name
Test status
Simulation time 201730134598 ps
CPU time 616.02 seconds
Started Jun 05 05:15:36 PM PDT 24
Finished Jun 05 05:25:53 PM PDT 24
Peak memory 240464 kb
Host smart-55a55c8e-06d6-464b-9787-0260acd3ccd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601185325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3601185325
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4025577909
Short name T150
Test name
Test status
Simulation time 14503953613 ps
CPU time 63.45 seconds
Started Jun 05 05:15:36 PM PDT 24
Finished Jun 05 05:16:41 PM PDT 24
Peak memory 219708 kb
Host smart-585608ee-6788-470b-a794-61048eda14ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025577909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.4025577909
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1403864026
Short name T215
Test name
Test status
Simulation time 3395134704 ps
CPU time 30.23 seconds
Started Jun 05 05:15:43 PM PDT 24
Finished Jun 05 05:16:14 PM PDT 24
Peak memory 211300 kb
Host smart-dde05843-3833-40c8-b071-961148193605
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1403864026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1403864026
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2333209952
Short name T89
Test name
Test status
Simulation time 26996870357 ps
CPU time 66.79 seconds
Started Jun 05 05:15:39 PM PDT 24
Finished Jun 05 05:16:46 PM PDT 24
Peak memory 218312 kb
Host smart-76fcf56f-b3f1-49f7-93ac-75fefd809391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333209952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2333209952
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.423825228
Short name T139
Test name
Test status
Simulation time 5099289488 ps
CPU time 56.66 seconds
Started Jun 05 05:15:35 PM PDT 24
Finished Jun 05 05:16:33 PM PDT 24
Peak memory 221764 kb
Host smart-ef0bf345-3f7e-4cf6-9b78-fc494e08b48d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423825228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.423825228
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3539306705
Short name T53
Test name
Test status
Simulation time 238487124632 ps
CPU time 2238.08 seconds
Started Jun 05 05:15:43 PM PDT 24
Finished Jun 05 05:53:03 PM PDT 24
Peak memory 243968 kb
Host smart-5ec36c73-6740-465a-b760-98cdc84fb225
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539306705 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.3539306705
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.425993439
Short name T263
Test name
Test status
Simulation time 18177085639 ps
CPU time 32.9 seconds
Started Jun 05 05:15:44 PM PDT 24
Finished Jun 05 05:16:18 PM PDT 24
Peak memory 212192 kb
Host smart-fadf5cc1-1b6c-480e-8d81-5b4cc8df9b52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425993439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.425993439
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3680123349
Short name T350
Test name
Test status
Simulation time 125936637112 ps
CPU time 595.83 seconds
Started Jun 05 05:15:35 PM PDT 24
Finished Jun 05 05:25:31 PM PDT 24
Peak memory 237604 kb
Host smart-897cf5d8-33df-4407-a5e2-f66b32a7158b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680123349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3680123349
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.409055702
Short name T301
Test name
Test status
Simulation time 332495408 ps
CPU time 19.43 seconds
Started Jun 05 05:15:42 PM PDT 24
Finished Jun 05 05:16:02 PM PDT 24
Peak memory 214648 kb
Host smart-50b09eae-f0dd-4eeb-a660-67b74ceb31bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409055702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.409055702
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3807322652
Short name T19
Test name
Test status
Simulation time 3476713625 ps
CPU time 29.97 seconds
Started Jun 05 05:15:43 PM PDT 24
Finished Jun 05 05:16:15 PM PDT 24
Peak memory 211276 kb
Host smart-ef19ed29-05ae-45f7-a440-e4326581cfc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3807322652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3807322652
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1966645225
Short name T140
Test name
Test status
Simulation time 13647341070 ps
CPU time 45.84 seconds
Started Jun 05 05:15:35 PM PDT 24
Finished Jun 05 05:16:22 PM PDT 24
Peak memory 214612 kb
Host smart-6d7cdcbf-4a06-4c8c-8511-521d377b4f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966645225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1966645225
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1427595603
Short name T256
Test name
Test status
Simulation time 1405667893 ps
CPU time 32.85 seconds
Started Jun 05 05:15:37 PM PDT 24
Finished Jun 05 05:16:11 PM PDT 24
Peak memory 218528 kb
Host smart-d2bf68eb-1ddc-4452-ad08-0d59841cc587
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427595603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1427595603
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.692969494
Short name T61
Test name
Test status
Simulation time 264360825 ps
CPU time 8.64 seconds
Started Jun 05 05:15:43 PM PDT 24
Finished Jun 05 05:15:53 PM PDT 24
Peak memory 211364 kb
Host smart-0a222f2b-1b3a-4a46-a3d3-aab9174e84d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692969494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.692969494
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3683768240
Short name T50
Test name
Test status
Simulation time 4387463549 ps
CPU time 143.98 seconds
Started Jun 05 05:15:41 PM PDT 24
Finished Jun 05 05:18:05 PM PDT 24
Peak memory 216816 kb
Host smart-d8ef995d-e629-400d-9fe0-a48ae9a0a903
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683768240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3683768240
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1064729195
Short name T236
Test name
Test status
Simulation time 674700804 ps
CPU time 19.27 seconds
Started Jun 05 05:15:42 PM PDT 24
Finished Jun 05 05:16:02 PM PDT 24
Peak memory 214704 kb
Host smart-ebc700d5-23dc-4424-bbc3-2e5529e4fc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064729195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1064729195
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3403689399
Short name T348
Test name
Test status
Simulation time 2471042952 ps
CPU time 10.81 seconds
Started Jun 05 05:15:42 PM PDT 24
Finished Jun 05 05:15:54 PM PDT 24
Peak memory 211612 kb
Host smart-bba42f6e-a1ee-4493-a957-bbc1c47358cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3403689399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3403689399
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.984473269
Short name T178
Test name
Test status
Simulation time 1503391531 ps
CPU time 20.74 seconds
Started Jun 05 05:15:43 PM PDT 24
Finished Jun 05 05:16:05 PM PDT 24
Peak memory 217436 kb
Host smart-419beecc-1ec2-4ca3-8e91-cf01119347e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984473269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.984473269
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3047618605
Short name T126
Test name
Test status
Simulation time 5244920517 ps
CPU time 78.59 seconds
Started Jun 05 05:15:43 PM PDT 24
Finished Jun 05 05:17:03 PM PDT 24
Peak memory 220336 kb
Host smart-af6bce31-e28d-4475-ad40-a7eeff064057
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047618605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3047618605
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3490035490
Short name T22
Test name
Test status
Simulation time 231136641644 ps
CPU time 4141.89 seconds
Started Jun 05 05:15:46 PM PDT 24
Finished Jun 05 06:24:49 PM PDT 24
Peak memory 250044 kb
Host smart-7a36dc1d-9300-46e2-a883-4c3ef097fee3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490035490 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3490035490
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1533093884
Short name T206
Test name
Test status
Simulation time 8540690357 ps
CPU time 22.33 seconds
Started Jun 05 05:15:45 PM PDT 24
Finished Jun 05 05:16:08 PM PDT 24
Peak memory 211400 kb
Host smart-55aa969c-26b4-4629-a2e6-0fd1ca5b506d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533093884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1533093884
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1364689251
Short name T343
Test name
Test status
Simulation time 6777392033 ps
CPU time 214.31 seconds
Started Jun 05 05:15:43 PM PDT 24
Finished Jun 05 05:19:19 PM PDT 24
Peak memory 233728 kb
Host smart-59e1de94-dad5-4a57-ae1b-3ed65a431f2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364689251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1364689251
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3642201385
Short name T279
Test name
Test status
Simulation time 12505626103 ps
CPU time 34.92 seconds
Started Jun 05 05:15:44 PM PDT 24
Finished Jun 05 05:16:20 PM PDT 24
Peak memory 214904 kb
Host smart-2547249d-fbf7-46da-b935-a26bf9526fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642201385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3642201385
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1121460822
Short name T224
Test name
Test status
Simulation time 179582320 ps
CPU time 10.58 seconds
Started Jun 05 05:15:44 PM PDT 24
Finished Jun 05 05:15:56 PM PDT 24
Peak memory 212796 kb
Host smart-c3685265-d34d-4515-93cf-d3966e86309a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1121460822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1121460822
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2545132336
Short name T332
Test name
Test status
Simulation time 2766818953 ps
CPU time 41.67 seconds
Started Jun 05 05:15:42 PM PDT 24
Finished Jun 05 05:16:24 PM PDT 24
Peak memory 216580 kb
Host smart-b3ab45fe-4dde-4e36-a8bb-02cd9c73219e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545132336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2545132336
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3299542887
Short name T39
Test name
Test status
Simulation time 2053216120 ps
CPU time 31.03 seconds
Started Jun 05 05:15:43 PM PDT 24
Finished Jun 05 05:16:16 PM PDT 24
Peak memory 215116 kb
Host smart-86717cf0-603a-456b-b7b5-e807f9457f42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299542887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3299542887
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.509775551
Short name T24
Test name
Test status
Simulation time 338347078 ps
CPU time 8.74 seconds
Started Jun 05 05:15:51 PM PDT 24
Finished Jun 05 05:16:00 PM PDT 24
Peak memory 211364 kb
Host smart-3f868d0c-0d9f-48d6-8513-5cd2335c0488
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509775551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.509775551
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2046913481
Short name T199
Test name
Test status
Simulation time 11788902462 ps
CPU time 177.43 seconds
Started Jun 05 05:15:49 PM PDT 24
Finished Jun 05 05:18:47 PM PDT 24
Peak memory 216076 kb
Host smart-8afa45ea-84fc-48be-89be-87d109496d8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046913481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2046913481
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.885122349
Short name T148
Test name
Test status
Simulation time 28843534863 ps
CPU time 65.62 seconds
Started Jun 05 05:15:51 PM PDT 24
Finished Jun 05 05:16:58 PM PDT 24
Peak memory 214980 kb
Host smart-e9424d77-f01b-4c5a-a82c-acf2b9d065a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885122349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.885122349
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3262049138
Short name T262
Test name
Test status
Simulation time 16034471531 ps
CPU time 32.06 seconds
Started Jun 05 05:15:44 PM PDT 24
Finished Jun 05 05:16:17 PM PDT 24
Peak memory 212764 kb
Host smart-ed126991-65ec-41c4-abfe-309fb78ce940
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3262049138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3262049138
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.648333655
Short name T334
Test name
Test status
Simulation time 7704097913 ps
CPU time 82.16 seconds
Started Jun 05 05:15:46 PM PDT 24
Finished Jun 05 05:17:09 PM PDT 24
Peak memory 215124 kb
Host smart-3b027e6a-9b4d-4fde-bddc-6cd6256e1ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648333655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.648333655
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3862399311
Short name T111
Test name
Test status
Simulation time 55873440953 ps
CPU time 141.85 seconds
Started Jun 05 05:15:45 PM PDT 24
Finished Jun 05 05:18:08 PM PDT 24
Peak memory 221004 kb
Host smart-c46aa8d4-5e7d-423b-8637-c5038e0810d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862399311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3862399311
Directory /workspace/9.rom_ctrl_stress_all/latest
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