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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.22 96.89 91.85 97.72 100.00 98.28 97.45 98.37


Total test records in report: 451
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T302 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3684726313 Jun 07 08:07:55 PM PDT 24 Jun 07 08:13:41 PM PDT 24 17218772812 ps
T303 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1223636316 Jun 07 08:07:12 PM PDT 24 Jun 07 08:10:51 PM PDT 24 16927554773 ps
T304 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.4241898216 Jun 07 08:07:33 PM PDT 24 Jun 07 08:08:37 PM PDT 24 28735693252 ps
T305 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1603877717 Jun 07 08:07:57 PM PDT 24 Jun 07 08:18:08 PM PDT 24 71825802442 ps
T306 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1624510646 Jun 07 08:06:55 PM PDT 24 Jun 07 08:09:30 PM PDT 24 4630720842 ps
T307 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3672383849 Jun 07 08:07:39 PM PDT 24 Jun 07 08:08:04 PM PDT 24 1833163184 ps
T308 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1910059113 Jun 07 08:07:57 PM PDT 24 Jun 07 08:08:24 PM PDT 24 14897295043 ps
T309 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.830493996 Jun 07 08:07:32 PM PDT 24 Jun 07 08:10:16 PM PDT 24 9443930684 ps
T310 /workspace/coverage/default/15.rom_ctrl_alert_test.1737815262 Jun 07 08:07:10 PM PDT 24 Jun 07 08:07:28 PM PDT 24 4441421566 ps
T311 /workspace/coverage/default/2.rom_ctrl_stress_all.2335997648 Jun 07 08:06:48 PM PDT 24 Jun 07 08:09:28 PM PDT 24 15428955058 ps
T312 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.23582429 Jun 07 08:07:56 PM PDT 24 Jun 07 08:14:36 PM PDT 24 44339518661 ps
T313 /workspace/coverage/default/26.rom_ctrl_stress_all.637463944 Jun 07 08:07:30 PM PDT 24 Jun 07 08:07:54 PM PDT 24 1386888568 ps
T314 /workspace/coverage/default/16.rom_ctrl_alert_test.3834468049 Jun 07 08:07:11 PM PDT 24 Jun 07 08:07:42 PM PDT 24 3102379884 ps
T315 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.303634883 Jun 07 08:07:01 PM PDT 24 Jun 07 08:07:20 PM PDT 24 1277068614 ps
T316 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.563521309 Jun 07 08:07:45 PM PDT 24 Jun 07 08:08:19 PM PDT 24 17826365416 ps
T317 /workspace/coverage/default/7.rom_ctrl_smoke.1901646209 Jun 07 08:07:05 PM PDT 24 Jun 07 08:07:51 PM PDT 24 27000365406 ps
T318 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.438944955 Jun 07 08:07:47 PM PDT 24 Jun 07 08:08:49 PM PDT 24 32816742031 ps
T319 /workspace/coverage/default/7.rom_ctrl_stress_all.2306572898 Jun 07 08:06:54 PM PDT 24 Jun 07 08:07:14 PM PDT 24 4409052690 ps
T320 /workspace/coverage/default/24.rom_ctrl_stress_all.1245987933 Jun 07 08:07:27 PM PDT 24 Jun 07 08:09:00 PM PDT 24 15980592681 ps
T321 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3699090231 Jun 07 08:08:03 PM PDT 24 Jun 07 08:11:32 PM PDT 24 20266046037 ps
T322 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1633245912 Jun 07 08:07:35 PM PDT 24 Jun 07 08:08:06 PM PDT 24 2347276267 ps
T323 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3865091853 Jun 07 08:07:07 PM PDT 24 Jun 07 08:11:22 PM PDT 24 14802080080 ps
T324 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1569670435 Jun 07 08:07:39 PM PDT 24 Jun 07 08:12:39 PM PDT 24 22719063183 ps
T325 /workspace/coverage/default/20.rom_ctrl_alert_test.2577338472 Jun 07 08:07:25 PM PDT 24 Jun 07 08:07:35 PM PDT 24 635038445 ps
T326 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2385053690 Jun 07 08:07:40 PM PDT 24 Jun 07 08:07:56 PM PDT 24 368517683 ps
T327 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.918294930 Jun 07 08:06:48 PM PDT 24 Jun 07 08:10:27 PM PDT 24 8214047860 ps
T328 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3688348384 Jun 07 08:07:03 PM PDT 24 Jun 07 08:07:23 PM PDT 24 2539495117 ps
T329 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4239891959 Jun 07 08:08:06 PM PDT 24 Jun 07 08:12:00 PM PDT 24 14222749504 ps
T330 /workspace/coverage/default/12.rom_ctrl_alert_test.1580849013 Jun 07 08:07:12 PM PDT 24 Jun 07 08:07:44 PM PDT 24 3488845013 ps
T331 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3515603425 Jun 07 08:07:05 PM PDT 24 Jun 07 08:12:27 PM PDT 24 50292453449 ps
T332 /workspace/coverage/default/40.rom_ctrl_smoke.216613755 Jun 07 08:07:55 PM PDT 24 Jun 07 08:08:19 PM PDT 24 1717968426 ps
T333 /workspace/coverage/default/20.rom_ctrl_stress_all.3414340102 Jun 07 08:07:20 PM PDT 24 Jun 07 08:08:05 PM PDT 24 2685455243 ps
T334 /workspace/coverage/default/31.rom_ctrl_alert_test.2555755263 Jun 07 08:07:39 PM PDT 24 Jun 07 08:07:53 PM PDT 24 172555060 ps
T46 /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3127224027 Jun 07 08:07:45 PM PDT 24 Jun 07 08:25:09 PM PDT 24 51089968720 ps
T335 /workspace/coverage/default/1.rom_ctrl_stress_all.2052387260 Jun 07 08:06:47 PM PDT 24 Jun 07 08:09:30 PM PDT 24 16286877842 ps
T336 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4277386799 Jun 07 08:07:10 PM PDT 24 Jun 07 08:07:25 PM PDT 24 3660418823 ps
T337 /workspace/coverage/default/42.rom_ctrl_stress_all.3971920758 Jun 07 08:07:56 PM PDT 24 Jun 07 08:08:39 PM PDT 24 2607937658 ps
T338 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.385810386 Jun 07 08:07:45 PM PDT 24 Jun 07 08:08:18 PM PDT 24 4801851625 ps
T339 /workspace/coverage/default/3.rom_ctrl_stress_all.2280633866 Jun 07 08:06:48 PM PDT 24 Jun 07 08:07:37 PM PDT 24 20542365837 ps
T340 /workspace/coverage/default/22.rom_ctrl_stress_all.67644634 Jun 07 08:07:24 PM PDT 24 Jun 07 08:08:07 PM PDT 24 3053638797 ps
T341 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.572068470 Jun 07 08:07:32 PM PDT 24 Jun 07 08:14:40 PM PDT 24 39195761113 ps
T342 /workspace/coverage/default/9.rom_ctrl_smoke.3151985030 Jun 07 08:07:04 PM PDT 24 Jun 07 08:07:39 PM PDT 24 1562647930 ps
T343 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3289271800 Jun 07 08:06:55 PM PDT 24 Jun 07 08:07:20 PM PDT 24 675909101 ps
T344 /workspace/coverage/default/7.rom_ctrl_alert_test.2040722592 Jun 07 08:07:06 PM PDT 24 Jun 07 08:07:34 PM PDT 24 6670983694 ps
T345 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4209345600 Jun 07 08:06:39 PM PDT 24 Jun 07 08:10:04 PM PDT 24 5954035043 ps
T346 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3780011883 Jun 07 08:07:56 PM PDT 24 Jun 07 08:08:18 PM PDT 24 689492178 ps
T347 /workspace/coverage/default/29.rom_ctrl_alert_test.2137195224 Jun 07 08:07:40 PM PDT 24 Jun 07 08:08:05 PM PDT 24 1946081739 ps
T348 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3967266143 Jun 07 08:07:37 PM PDT 24 Jun 07 08:08:23 PM PDT 24 14560752729 ps
T349 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3266970067 Jun 07 08:08:06 PM PDT 24 Jun 07 08:08:25 PM PDT 24 10277535364 ps
T350 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.807171752 Jun 07 08:07:17 PM PDT 24 Jun 07 08:08:25 PM PDT 24 14435414275 ps
T351 /workspace/coverage/default/19.rom_ctrl_alert_test.4269503284 Jun 07 08:07:23 PM PDT 24 Jun 07 08:07:43 PM PDT 24 6233927848 ps
T352 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.439170418 Jun 07 08:06:56 PM PDT 24 Jun 07 08:07:13 PM PDT 24 684140074 ps
T353 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.73181732 Jun 07 08:07:47 PM PDT 24 Jun 07 08:09:59 PM PDT 24 1589486319 ps
T354 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.777160526 Jun 07 08:06:51 PM PDT 24 Jun 07 08:07:37 PM PDT 24 8371367000 ps
T355 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1870101975 Jun 07 08:06:55 PM PDT 24 Jun 07 08:10:13 PM PDT 24 11428578540 ps
T356 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3505130104 Jun 07 08:08:01 PM PDT 24 Jun 07 08:08:27 PM PDT 24 7182867384 ps
T357 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.974726536 Jun 07 08:07:48 PM PDT 24 Jun 07 08:08:22 PM PDT 24 4115543893 ps
T47 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3118233716 Jun 07 07:33:19 PM PDT 24 Jun 07 07:33:45 PM PDT 24 8493048309 ps
T62 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3128795444 Jun 07 07:33:12 PM PDT 24 Jun 07 07:33:50 PM PDT 24 8519398246 ps
T63 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1721703109 Jun 07 07:33:18 PM PDT 24 Jun 07 07:33:52 PM PDT 24 6137700557 ps
T106 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.483744672 Jun 07 07:33:10 PM PDT 24 Jun 07 07:33:27 PM PDT 24 1709589718 ps
T70 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2036897599 Jun 07 07:33:16 PM PDT 24 Jun 07 07:33:32 PM PDT 24 175270425 ps
T71 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2965385145 Jun 07 07:33:20 PM PDT 24 Jun 07 07:34:53 PM PDT 24 22292744474 ps
T48 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3340359784 Jun 07 07:33:21 PM PDT 24 Jun 07 07:34:00 PM PDT 24 7900939242 ps
T358 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2481700021 Jun 07 07:33:12 PM PDT 24 Jun 07 07:33:49 PM PDT 24 15724453582 ps
T49 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2201527072 Jun 07 07:33:21 PM PDT 24 Jun 07 07:33:55 PM PDT 24 15695200683 ps
T50 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.924546119 Jun 07 07:33:22 PM PDT 24 Jun 07 07:33:50 PM PDT 24 4531468697 ps
T72 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4179849643 Jun 07 07:33:21 PM PDT 24 Jun 07 07:33:37 PM PDT 24 736550163 ps
T51 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.410046350 Jun 07 07:33:29 PM PDT 24 Jun 07 07:33:45 PM PDT 24 3130955054 ps
T73 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1778706680 Jun 07 07:33:21 PM PDT 24 Jun 07 07:33:50 PM PDT 24 5596136460 ps
T69 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1388253861 Jun 07 07:33:18 PM PDT 24 Jun 07 07:33:32 PM PDT 24 2284817039 ps
T74 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3385859385 Jun 07 07:33:25 PM PDT 24 Jun 07 07:33:37 PM PDT 24 169199866 ps
T359 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2566765238 Jun 07 07:33:27 PM PDT 24 Jun 07 07:33:38 PM PDT 24 704750346 ps
T58 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2300451444 Jun 07 07:33:30 PM PDT 24 Jun 07 07:35:16 PM PDT 24 3588386310 ps
T360 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2506425594 Jun 07 07:33:25 PM PDT 24 Jun 07 07:33:37 PM PDT 24 175581088 ps
T59 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.457323763 Jun 07 07:33:20 PM PDT 24 Jun 07 07:36:01 PM PDT 24 3345587680 ps
T107 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1931560813 Jun 07 07:33:31 PM PDT 24 Jun 07 07:33:46 PM PDT 24 1643660526 ps
T60 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3820612233 Jun 07 07:33:23 PM PDT 24 Jun 07 07:36:06 PM PDT 24 5762109546 ps
T361 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2143413302 Jun 07 07:33:15 PM PDT 24 Jun 07 07:33:53 PM PDT 24 29814098636 ps
T75 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.414489246 Jun 07 07:33:29 PM PDT 24 Jun 07 07:34:34 PM PDT 24 15167602911 ps
T362 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4239877273 Jun 07 07:33:07 PM PDT 24 Jun 07 07:33:33 PM PDT 24 1622429085 ps
T363 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3254105534 Jun 07 07:33:16 PM PDT 24 Jun 07 07:33:48 PM PDT 24 9874357188 ps
T76 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1579056250 Jun 07 07:33:30 PM PDT 24 Jun 07 07:35:41 PM PDT 24 30822501544 ps
T77 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3606260191 Jun 07 07:33:10 PM PDT 24 Jun 07 07:35:05 PM PDT 24 24689826171 ps
T78 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1129089768 Jun 07 07:33:22 PM PDT 24 Jun 07 07:35:37 PM PDT 24 38101844577 ps
T364 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1751584982 Jun 07 07:33:12 PM PDT 24 Jun 07 07:33:47 PM PDT 24 4293050149 ps
T79 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.600914960 Jun 07 07:33:19 PM PDT 24 Jun 07 07:33:37 PM PDT 24 3202603704 ps
T365 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1013965374 Jun 07 07:33:10 PM PDT 24 Jun 07 07:33:50 PM PDT 24 17036161102 ps
T99 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1639875028 Jun 07 07:33:18 PM PDT 24 Jun 07 07:33:48 PM PDT 24 4757814346 ps
T366 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3774484063 Jun 07 07:33:30 PM PDT 24 Jun 07 07:33:54 PM PDT 24 18959660463 ps
T117 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.66468372 Jun 07 07:33:10 PM PDT 24 Jun 07 07:34:51 PM PDT 24 14421115086 ps
T367 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3542484419 Jun 07 07:33:11 PM PDT 24 Jun 07 07:33:49 PM PDT 24 17889845044 ps
T113 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1360990873 Jun 07 07:33:08 PM PDT 24 Jun 07 07:34:37 PM PDT 24 1249794193 ps
T368 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.714914555 Jun 07 07:33:09 PM PDT 24 Jun 07 07:33:45 PM PDT 24 16343089318 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.499500058 Jun 07 07:33:07 PM PDT 24 Jun 07 07:33:19 PM PDT 24 174261641 ps
T100 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3603866777 Jun 07 07:33:12 PM PDT 24 Jun 07 07:33:25 PM PDT 24 2059829250 ps
T370 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1502214184 Jun 07 07:33:11 PM PDT 24 Jun 07 07:34:50 PM PDT 24 102055246744 ps
T371 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1731031912 Jun 07 07:33:07 PM PDT 24 Jun 07 07:33:26 PM PDT 24 939257743 ps
T372 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1781720524 Jun 07 07:33:15 PM PDT 24 Jun 07 07:33:35 PM PDT 24 5946609024 ps
T84 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2554732051 Jun 07 07:33:16 PM PDT 24 Jun 07 07:34:27 PM PDT 24 7256351355 ps
T373 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.435214931 Jun 07 07:33:18 PM PDT 24 Jun 07 07:33:31 PM PDT 24 177695508 ps
T114 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.966774090 Jun 07 07:33:15 PM PDT 24 Jun 07 07:34:42 PM PDT 24 734020183 ps
T119 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4008442978 Jun 07 07:33:20 PM PDT 24 Jun 07 07:36:17 PM PDT 24 22263578909 ps
T124 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1034528279 Jun 07 07:33:18 PM PDT 24 Jun 07 07:36:02 PM PDT 24 2118035230 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.863247964 Jun 07 07:33:11 PM PDT 24 Jun 07 07:33:37 PM PDT 24 17643285763 ps
T375 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3204980493 Jun 07 07:33:08 PM PDT 24 Jun 07 07:33:25 PM PDT 24 176086875 ps
T101 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1704670819 Jun 07 07:33:22 PM PDT 24 Jun 07 07:33:57 PM PDT 24 7057809628 ps
T376 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2041919485 Jun 07 07:33:18 PM PDT 24 Jun 07 07:33:44 PM PDT 24 5686373143 ps
T377 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4175568167 Jun 07 07:33:17 PM PDT 24 Jun 07 07:33:36 PM PDT 24 4835905687 ps
T378 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1194710666 Jun 07 07:33:27 PM PDT 24 Jun 07 07:34:02 PM PDT 24 57373263391 ps
T379 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2545199965 Jun 07 07:33:20 PM PDT 24 Jun 07 07:34:20 PM PDT 24 4133778543 ps
T118 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2027672535 Jun 07 07:33:09 PM PDT 24 Jun 07 07:34:51 PM PDT 24 4787246143 ps
T102 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3582546640 Jun 07 07:33:10 PM PDT 24 Jun 07 07:33:41 PM PDT 24 5869169732 ps
T380 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1817376851 Jun 07 07:33:20 PM PDT 24 Jun 07 07:33:47 PM PDT 24 2432047722 ps
T381 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3653430758 Jun 07 07:33:07 PM PDT 24 Jun 07 07:33:25 PM PDT 24 571073977 ps
T382 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1193067699 Jun 07 07:33:20 PM PDT 24 Jun 07 07:33:52 PM PDT 24 28589745345 ps
T383 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2085638268 Jun 07 07:33:10 PM PDT 24 Jun 07 07:33:24 PM PDT 24 332022927 ps
T384 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1299406183 Jun 07 07:33:20 PM PDT 24 Jun 07 07:33:47 PM PDT 24 11377465411 ps
T385 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4189949283 Jun 07 07:33:08 PM PDT 24 Jun 07 07:33:25 PM PDT 24 2127776421 ps
T386 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3281892535 Jun 07 07:33:18 PM PDT 24 Jun 07 07:33:32 PM PDT 24 1099001370 ps
T387 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3188010266 Jun 07 07:33:20 PM PDT 24 Jun 07 07:35:02 PM PDT 24 7328074850 ps
T85 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2020315236 Jun 07 07:33:22 PM PDT 24 Jun 07 07:33:43 PM PDT 24 5894943014 ps
T103 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2912085992 Jun 07 07:33:07 PM PDT 24 Jun 07 07:33:38 PM PDT 24 6102027437 ps
T388 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4160171620 Jun 07 07:33:20 PM PDT 24 Jun 07 07:33:49 PM PDT 24 4104487612 ps
T389 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.43765358 Jun 07 07:33:21 PM PDT 24 Jun 07 07:35:21 PM PDT 24 51971415733 ps
T115 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2589316803 Jun 07 07:33:18 PM PDT 24 Jun 07 07:36:10 PM PDT 24 11012498381 ps
T86 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.427711544 Jun 07 07:33:12 PM PDT 24 Jun 07 07:33:46 PM PDT 24 3375545580 ps
T390 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.505794862 Jun 07 07:33:11 PM PDT 24 Jun 07 07:33:24 PM PDT 24 371987533 ps
T391 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.252645173 Jun 07 07:33:06 PM PDT 24 Jun 07 07:33:28 PM PDT 24 2658503619 ps
T392 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.584414651 Jun 07 07:33:22 PM PDT 24 Jun 07 07:33:59 PM PDT 24 8561639615 ps
T393 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3168557977 Jun 07 07:33:28 PM PDT 24 Jun 07 07:33:55 PM PDT 24 5585289324 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3398143923 Jun 07 07:33:10 PM PDT 24 Jun 07 07:33:41 PM PDT 24 4597781493 ps
T395 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2372670745 Jun 07 07:33:19 PM PDT 24 Jun 07 07:33:45 PM PDT 24 1476772693 ps
T87 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3869131244 Jun 07 07:33:13 PM PDT 24 Jun 07 07:35:36 PM PDT 24 33613496215 ps
T396 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4173039837 Jun 07 07:33:14 PM PDT 24 Jun 07 07:33:50 PM PDT 24 9389002081 ps
T116 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1106853044 Jun 07 07:33:30 PM PDT 24 Jun 07 07:36:26 PM PDT 24 15988586392 ps
T397 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4010345841 Jun 07 07:33:22 PM PDT 24 Jun 07 07:34:05 PM PDT 24 2992846565 ps
T398 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2749890650 Jun 07 07:33:29 PM PDT 24 Jun 07 07:36:10 PM PDT 24 492838417 ps
T104 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2062878489 Jun 07 07:33:18 PM PDT 24 Jun 07 07:33:46 PM PDT 24 2851366819 ps
T399 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2437520279 Jun 07 07:33:19 PM PDT 24 Jun 07 07:34:57 PM PDT 24 35427563552 ps
T400 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2538400011 Jun 07 07:33:11 PM PDT 24 Jun 07 07:33:24 PM PDT 24 660558317 ps
T401 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.838645247 Jun 07 07:33:31 PM PDT 24 Jun 07 07:33:59 PM PDT 24 2689783571 ps
T402 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1895546691 Jun 07 07:33:25 PM PDT 24 Jun 07 07:33:40 PM PDT 24 570519602 ps
T88 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.513951457 Jun 07 07:33:23 PM PDT 24 Jun 07 07:35:33 PM PDT 24 60188322964 ps
T403 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1477756172 Jun 07 07:33:30 PM PDT 24 Jun 07 07:34:04 PM PDT 24 12277086559 ps
T404 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.609773902 Jun 07 07:33:22 PM PDT 24 Jun 07 07:35:41 PM PDT 24 74818124890 ps
T405 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2975883641 Jun 07 07:33:20 PM PDT 24 Jun 07 07:33:54 PM PDT 24 14382804472 ps
T406 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.370453205 Jun 07 07:33:12 PM PDT 24 Jun 07 07:33:25 PM PDT 24 169115348 ps
T123 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3689577051 Jun 07 07:33:19 PM PDT 24 Jun 07 07:35:54 PM PDT 24 709558965 ps
T407 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1738538113 Jun 07 07:33:12 PM PDT 24 Jun 07 07:33:33 PM PDT 24 178461464 ps
T408 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.870720692 Jun 07 07:33:32 PM PDT 24 Jun 07 07:33:47 PM PDT 24 438321670 ps
T409 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3254406936 Jun 07 07:33:21 PM PDT 24 Jun 07 07:33:57 PM PDT 24 15404952756 ps
T121 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2420152276 Jun 07 07:33:12 PM PDT 24 Jun 07 07:36:12 PM PDT 24 12496357691 ps
T120 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.868945488 Jun 07 07:33:20 PM PDT 24 Jun 07 07:34:56 PM PDT 24 1468393102 ps
T410 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1454374715 Jun 07 07:33:20 PM PDT 24 Jun 07 07:34:00 PM PDT 24 13942588025 ps
T411 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.654475840 Jun 07 07:33:17 PM PDT 24 Jun 07 07:33:36 PM PDT 24 14096782079 ps
T412 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3250736021 Jun 07 07:33:15 PM PDT 24 Jun 07 07:33:45 PM PDT 24 11913254332 ps
T91 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.474729855 Jun 07 07:33:25 PM PDT 24 Jun 07 07:33:37 PM PDT 24 167562002 ps
T413 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.40291360 Jun 07 07:33:25 PM PDT 24 Jun 07 07:34:01 PM PDT 24 24542060568 ps
T414 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4165334949 Jun 07 07:33:10 PM PDT 24 Jun 07 07:36:35 PM PDT 24 96813939771 ps
T415 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1711463563 Jun 07 07:33:15 PM PDT 24 Jun 07 07:33:29 PM PDT 24 461848988 ps
T89 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.147552153 Jun 07 07:33:32 PM PDT 24 Jun 07 07:35:57 PM PDT 24 53422332297 ps
T416 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.862395799 Jun 07 07:33:10 PM PDT 24 Jun 07 07:33:48 PM PDT 24 6398073437 ps
T417 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3140707724 Jun 07 07:33:19 PM PDT 24 Jun 07 07:35:33 PM PDT 24 18645802608 ps
T418 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2898546794 Jun 07 07:33:11 PM PDT 24 Jun 07 07:33:42 PM PDT 24 2211557223 ps
T122 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.552205352 Jun 07 07:33:11 PM PDT 24 Jun 07 07:34:48 PM PDT 24 8048240748 ps
T419 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2154186665 Jun 07 07:33:12 PM PDT 24 Jun 07 07:33:32 PM PDT 24 1025844244 ps
T420 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4264040513 Jun 07 07:33:07 PM PDT 24 Jun 07 07:33:42 PM PDT 24 32664787682 ps
T421 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1730039114 Jun 07 07:33:17 PM PDT 24 Jun 07 07:33:54 PM PDT 24 6787423388 ps
T422 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2723225061 Jun 07 07:33:09 PM PDT 24 Jun 07 07:33:50 PM PDT 24 15679455923 ps
T90 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2962491161 Jun 07 07:33:11 PM PDT 24 Jun 07 07:33:44 PM PDT 24 3359214505 ps
T423 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2539252650 Jun 07 07:33:21 PM PDT 24 Jun 07 07:33:45 PM PDT 24 1389793047 ps
T424 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3322323795 Jun 07 07:33:32 PM PDT 24 Jun 07 07:33:50 PM PDT 24 4866350624 ps
T425 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4125315426 Jun 07 07:33:11 PM PDT 24 Jun 07 07:33:41 PM PDT 24 2794882379 ps
T426 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2474140035 Jun 07 07:33:16 PM PDT 24 Jun 07 07:34:52 PM PDT 24 4041987373 ps
T427 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1667274981 Jun 07 07:33:09 PM PDT 24 Jun 07 07:33:42 PM PDT 24 6422060939 ps
T428 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1188409133 Jun 07 07:33:11 PM PDT 24 Jun 07 07:33:28 PM PDT 24 2621249514 ps
T429 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2931215020 Jun 07 07:33:24 PM PDT 24 Jun 07 07:33:36 PM PDT 24 167626095 ps
T430 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.902448164 Jun 07 07:33:20 PM PDT 24 Jun 07 07:33:44 PM PDT 24 5424492593 ps
T431 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4078236120 Jun 07 07:33:29 PM PDT 24 Jun 07 07:33:58 PM PDT 24 4836565053 ps
T432 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2786112250 Jun 07 07:33:15 PM PDT 24 Jun 07 07:33:53 PM PDT 24 4253892169 ps
T433 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2836333560 Jun 07 07:33:15 PM PDT 24 Jun 07 07:33:39 PM PDT 24 6245266354 ps
T434 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2307946751 Jun 07 07:33:21 PM PDT 24 Jun 07 07:34:22 PM PDT 24 4479720302 ps
T435 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2586358445 Jun 07 07:33:13 PM PDT 24 Jun 07 07:33:44 PM PDT 24 2851631352 ps
T436 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2584300035 Jun 07 07:33:19 PM PDT 24 Jun 07 07:33:47 PM PDT 24 2936227664 ps
T437 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3668781824 Jun 07 07:33:15 PM PDT 24 Jun 07 07:33:53 PM PDT 24 15300811545 ps
T438 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.995995403 Jun 07 07:33:19 PM PDT 24 Jun 07 07:33:35 PM PDT 24 601419796 ps
T439 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3855642775 Jun 07 07:33:11 PM PDT 24 Jun 07 07:33:46 PM PDT 24 15072639793 ps
T440 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2793326728 Jun 07 07:33:08 PM PDT 24 Jun 07 07:33:21 PM PDT 24 661396758 ps
T441 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3781733877 Jun 07 07:33:11 PM PDT 24 Jun 07 07:34:45 PM PDT 24 8244599950 ps
T442 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1462348039 Jun 07 07:33:18 PM PDT 24 Jun 07 07:33:54 PM PDT 24 15655651191 ps
T443 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2273426820 Jun 07 07:33:31 PM PDT 24 Jun 07 07:34:07 PM PDT 24 3674538755 ps
T444 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.685019246 Jun 07 07:33:18 PM PDT 24 Jun 07 07:33:56 PM PDT 24 14059992548 ps
T445 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.767779165 Jun 07 07:33:13 PM PDT 24 Jun 07 07:33:52 PM PDT 24 15989711030 ps
T446 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2586709448 Jun 07 07:33:17 PM PDT 24 Jun 07 07:34:54 PM PDT 24 2040868593 ps
T447 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3125845424 Jun 07 07:33:23 PM PDT 24 Jun 07 07:33:56 PM PDT 24 7537093113 ps
T448 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.372470502 Jun 07 07:33:20 PM PDT 24 Jun 07 07:33:55 PM PDT 24 8066254925 ps
T449 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1396521379 Jun 07 07:33:11 PM PDT 24 Jun 07 07:33:45 PM PDT 24 13961415714 ps
T450 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4160249451 Jun 07 07:33:21 PM PDT 24 Jun 07 07:33:40 PM PDT 24 966133254 ps
T451 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.312448792 Jun 07 07:33:09 PM PDT 24 Jun 07 07:33:53 PM PDT 24 706322056 ps
T112 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2575782549 Jun 07 07:33:24 PM PDT 24 Jun 07 07:35:13 PM PDT 24 20760315401 ps

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3661429823
Short name T10
Test name
Test status
Simulation time 14304373625 ps
CPU time 107.93 seconds
Started Jun 07 08:07:29 PM PDT 24
Finished Jun 07 08:09:19 PM PDT 24
Peak memory 219736 kb
Host smart-b56301a7-c9a9-4ac4-ab6c-9df26ac1c922
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661429823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3661429823
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2479887946
Short name T11
Test name
Test status
Simulation time 90637438771 ps
CPU time 923.33 seconds
Started Jun 07 08:07:58 PM PDT 24
Finished Jun 07 08:23:23 PM PDT 24
Peak memory 236556 kb
Host smart-026b8a73-f47c-4f7c-9845-3d75a49153c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479887946 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2479887946
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.848648547
Short name T18
Test name
Test status
Simulation time 51373505786 ps
CPU time 605.98 seconds
Started Jun 07 08:07:20 PM PDT 24
Finished Jun 07 08:17:27 PM PDT 24
Peak memory 234768 kb
Host smart-9e4dcb27-833a-4889-9a62-493ebc533e9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848648547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.848648547
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2687569003
Short name T192
Test name
Test status
Simulation time 184139667927 ps
CPU time 889.66 seconds
Started Jun 07 08:07:09 PM PDT 24
Finished Jun 07 08:22:01 PM PDT 24
Peak memory 235772 kb
Host smart-3bcaf895-ea04-4516-9156-92bbe8a896a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687569003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2687569003
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3820612233
Short name T60
Test name
Test status
Simulation time 5762109546 ps
CPU time 158.7 seconds
Started Jun 07 07:33:23 PM PDT 24
Finished Jun 07 07:36:06 PM PDT 24
Peak memory 219288 kb
Host smart-1e4bb8a4-c0de-461d-b9b8-157320f1751e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820612233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3820612233
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2679754428
Short name T14
Test name
Test status
Simulation time 10093877147 ps
CPU time 44.72 seconds
Started Jun 07 08:07:19 PM PDT 24
Finished Jun 07 08:08:05 PM PDT 24
Peak memory 216328 kb
Host smart-0cba1993-85af-47c9-bda6-1c8c6ae0c002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679754428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2679754428
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2136280409
Short name T20
Test name
Test status
Simulation time 914038783 ps
CPU time 225 seconds
Started Jun 07 08:06:50 PM PDT 24
Finished Jun 07 08:10:38 PM PDT 24
Peak memory 238100 kb
Host smart-93877d4a-5995-4b21-9922-958b1db09bd7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136280409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2136280409
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2965385145
Short name T71
Test name
Test status
Simulation time 22292744474 ps
CPU time 88.86 seconds
Started Jun 07 07:33:20 PM PDT 24
Finished Jun 07 07:34:53 PM PDT 24
Peak memory 219240 kb
Host smart-b88ce504-6937-46ba-9de1-32ed6d595566
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965385145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2965385145
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2776102533
Short name T24
Test name
Test status
Simulation time 4282624285 ps
CPU time 15.81 seconds
Started Jun 07 08:07:42 PM PDT 24
Finished Jun 07 08:08:03 PM PDT 24
Peak memory 216932 kb
Host smart-97f9403c-fbd2-435c-b529-24905cea91c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776102533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2776102533
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3689577051
Short name T123
Test name
Test status
Simulation time 709558965 ps
CPU time 150.69 seconds
Started Jun 07 07:33:19 PM PDT 24
Finished Jun 07 07:35:54 PM PDT 24
Peak memory 214500 kb
Host smart-2021a7fc-7f72-4a71-98be-5bf82842178c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689577051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3689577051
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2714547240
Short name T23
Test name
Test status
Simulation time 23139864713 ps
CPU time 52.42 seconds
Started Jun 07 08:07:46 PM PDT 24
Finished Jun 07 08:08:43 PM PDT 24
Peak memory 219088 kb
Host smart-4aa8deee-ab6e-4dba-a22a-f4cb8dab011e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714547240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2714547240
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2837680025
Short name T262
Test name
Test status
Simulation time 332702193 ps
CPU time 19.09 seconds
Started Jun 07 08:06:40 PM PDT 24
Finished Jun 07 08:07:02 PM PDT 24
Peak memory 219016 kb
Host smart-04432659-9176-4ea2-b170-8949f2a327cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837680025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2837680025
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2810162523
Short name T13
Test name
Test status
Simulation time 73979214553 ps
CPU time 617.61 seconds
Started Jun 07 08:06:48 PM PDT 24
Finished Jun 07 08:17:08 PM PDT 24
Peak memory 235632 kb
Host smart-1a2e182b-81e8-4f21-ba37-ab87ee24b694
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810162523 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2810162523
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.552205352
Short name T122
Test name
Test status
Simulation time 8048240748 ps
CPU time 92.04 seconds
Started Jun 07 07:33:11 PM PDT 24
Finished Jun 07 07:34:48 PM PDT 24
Peak memory 214256 kb
Host smart-3673454b-7a3c-4525-8cdb-9545d3c552c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552205352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.552205352
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1034528279
Short name T124
Test name
Test status
Simulation time 2118035230 ps
CPU time 159.93 seconds
Started Jun 07 07:33:18 PM PDT 24
Finished Jun 07 07:36:02 PM PDT 24
Peak memory 218560 kb
Host smart-d3c7c84f-2be1-4195-8f44-0221205e8b74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034528279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1034528279
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2575782549
Short name T112
Test name
Test status
Simulation time 20760315401 ps
CPU time 105.65 seconds
Started Jun 07 07:33:24 PM PDT 24
Finished Jun 07 07:35:13 PM PDT 24
Peak memory 214300 kb
Host smart-7c6c8196-80d0-4978-8eeb-0375d2249347
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575782549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2575782549
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2912085992
Short name T103
Test name
Test status
Simulation time 6102027437 ps
CPU time 27.06 seconds
Started Jun 07 07:33:07 PM PDT 24
Finished Jun 07 07:33:38 PM PDT 24
Peak memory 212700 kb
Host smart-233d8f4b-014f-4b37-92cb-0d1cec54deaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912085992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2912085992
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.147552153
Short name T89
Test name
Test status
Simulation time 53422332297 ps
CPU time 140.76 seconds
Started Jun 07 07:33:32 PM PDT 24
Finished Jun 07 07:35:57 PM PDT 24
Peak memory 215312 kb
Host smart-02823d3a-7f3f-451b-bd25-d804e8d24941
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147552153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.147552153
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3135834569
Short name T105
Test name
Test status
Simulation time 1632675547 ps
CPU time 30.2 seconds
Started Jun 07 08:07:31 PM PDT 24
Finished Jun 07 08:08:04 PM PDT 24
Peak memory 216216 kb
Host smart-de4c1a0c-07c0-47d8-bf8e-85fa4159f125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135834569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3135834569
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3418678283
Short name T3
Test name
Test status
Simulation time 300927401240 ps
CPU time 459.61 seconds
Started Jun 07 08:07:35 PM PDT 24
Finished Jun 07 08:15:18 PM PDT 24
Peak memory 236024 kb
Host smart-2143b2d3-c396-4b9a-85b1-4f460ebea5e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418678283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3418678283
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.499500058
Short name T369
Test name
Test status
Simulation time 174261641 ps
CPU time 8.25 seconds
Started Jun 07 07:33:07 PM PDT 24
Finished Jun 07 07:33:19 PM PDT 24
Peak memory 210988 kb
Host smart-79049baf-77a5-4d88-aac8-1bc4548596c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499500058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.499500058
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2538400011
Short name T400
Test name
Test status
Simulation time 660558317 ps
CPU time 8.67 seconds
Started Jun 07 07:33:11 PM PDT 24
Finished Jun 07 07:33:24 PM PDT 24
Peak memory 211000 kb
Host smart-64dd79be-900d-46aa-9800-cae946ce7fb2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538400011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2538400011
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3204980493
Short name T375
Test name
Test status
Simulation time 176086875 ps
CPU time 11.8 seconds
Started Jun 07 07:33:08 PM PDT 24
Finished Jun 07 07:33:25 PM PDT 24
Peak memory 212232 kb
Host smart-1525afb5-cde0-489c-97ea-d7ea6a7f7845
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204980493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3204980493
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1396521379
Short name T449
Test name
Test status
Simulation time 13961415714 ps
CPU time 29.36 seconds
Started Jun 07 07:33:11 PM PDT 24
Finished Jun 07 07:33:45 PM PDT 24
Peak memory 216460 kb
Host smart-edb51881-e452-40ba-a57a-729702961175
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396521379 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1396521379
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2085638268
Short name T383
Test name
Test status
Simulation time 332022927 ps
CPU time 8.48 seconds
Started Jun 07 07:33:10 PM PDT 24
Finished Jun 07 07:33:24 PM PDT 24
Peak memory 211292 kb
Host smart-c0b9ea0a-03bb-437c-a985-f0e5601de0a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085638268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2085638268
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.252645173
Short name T391
Test name
Test status
Simulation time 2658503619 ps
CPU time 17.12 seconds
Started Jun 07 07:33:06 PM PDT 24
Finished Jun 07 07:33:28 PM PDT 24
Peak memory 210824 kb
Host smart-d6f3833b-f466-4a11-9897-83f9d167a173
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252645173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.252645173
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4189949283
Short name T385
Test name
Test status
Simulation time 2127776421 ps
CPU time 12.08 seconds
Started Jun 07 07:33:08 PM PDT 24
Finished Jun 07 07:33:25 PM PDT 24
Peak memory 210768 kb
Host smart-24dda1bd-4ced-4a02-8dc0-fdd375c962ee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189949283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.4189949283
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.4165334949
Short name T414
Test name
Test status
Simulation time 96813939771 ps
CPU time 199.68 seconds
Started Jun 07 07:33:10 PM PDT 24
Finished Jun 07 07:36:35 PM PDT 24
Peak memory 215276 kb
Host smart-4fd2c128-1357-4b3c-9593-9d2ea1616f3b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165334949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.4165334949
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3653430758
Short name T381
Test name
Test status
Simulation time 571073977 ps
CPU time 13.85 seconds
Started Jun 07 07:33:07 PM PDT 24
Finished Jun 07 07:33:25 PM PDT 24
Peak memory 217488 kb
Host smart-d94f3f3b-9c47-49e4-a39e-a2c5d562b95d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653430758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3653430758
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2027672535
Short name T118
Test name
Test status
Simulation time 4787246143 ps
CPU time 96.59 seconds
Started Jun 07 07:33:09 PM PDT 24
Finished Jun 07 07:34:51 PM PDT 24
Peak memory 214308 kb
Host smart-9466f410-42ff-45b2-b515-5b9b49cb6798
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027672535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2027672535
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1731031912
Short name T371
Test name
Test status
Simulation time 939257743 ps
CPU time 14 seconds
Started Jun 07 07:33:07 PM PDT 24
Finished Jun 07 07:33:26 PM PDT 24
Peak memory 210972 kb
Host smart-79ba4c60-555e-4458-a362-00512aff8ab2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731031912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1731031912
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2793326728
Short name T440
Test name
Test status
Simulation time 661396758 ps
CPU time 8.48 seconds
Started Jun 07 07:33:08 PM PDT 24
Finished Jun 07 07:33:21 PM PDT 24
Peak memory 211016 kb
Host smart-dc4c8a74-7a8c-4c6b-8600-869587ebe1d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793326728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2793326728
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3398143923
Short name T394
Test name
Test status
Simulation time 4597781493 ps
CPU time 26.07 seconds
Started Jun 07 07:33:10 PM PDT 24
Finished Jun 07 07:33:41 PM PDT 24
Peak memory 212176 kb
Host smart-7eb016d2-a71a-4909-9457-37520f954829
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398143923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3398143923
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.505794862
Short name T390
Test name
Test status
Simulation time 371987533 ps
CPU time 8.28 seconds
Started Jun 07 07:33:11 PM PDT 24
Finished Jun 07 07:33:24 PM PDT 24
Peak memory 219236 kb
Host smart-8a5d5ee8-e845-4687-ae69-8fd594945086
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505794862 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.505794862
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3542484419
Short name T367
Test name
Test status
Simulation time 17889845044 ps
CPU time 32.83 seconds
Started Jun 07 07:33:11 PM PDT 24
Finished Jun 07 07:33:49 PM PDT 24
Peak memory 212296 kb
Host smart-2253ec17-940c-423e-9657-ef0984453797
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542484419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3542484419
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1751584982
Short name T364
Test name
Test status
Simulation time 4293050149 ps
CPU time 30.3 seconds
Started Jun 07 07:33:12 PM PDT 24
Finished Jun 07 07:33:47 PM PDT 24
Peak memory 210856 kb
Host smart-a6e7fac1-e1ed-4cb2-9d78-9a3f9710ab6a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751584982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1751584982
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2481700021
Short name T358
Test name
Test status
Simulation time 15724453582 ps
CPU time 31.69 seconds
Started Jun 07 07:33:12 PM PDT 24
Finished Jun 07 07:33:49 PM PDT 24
Peak memory 210844 kb
Host smart-4eb2ea22-a833-47b5-ba66-51a79004d357
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481700021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2481700021
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3606260191
Short name T77
Test name
Test status
Simulation time 24689826171 ps
CPU time 110.03 seconds
Started Jun 07 07:33:10 PM PDT 24
Finished Jun 07 07:35:05 PM PDT 24
Peak memory 214148 kb
Host smart-f0daf374-8a12-4573-b4ca-4c5b8e712f86
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606260191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3606260191
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.4264040513
Short name T420
Test name
Test status
Simulation time 32664787682 ps
CPU time 29.86 seconds
Started Jun 07 07:33:07 PM PDT 24
Finished Jun 07 07:33:42 PM PDT 24
Peak memory 213060 kb
Host smart-e7dc7d05-2086-4795-b1f9-ecc2af09bee9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264040513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.4264040513
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3668781824
Short name T437
Test name
Test status
Simulation time 15300811545 ps
CPU time 33.4 seconds
Started Jun 07 07:33:15 PM PDT 24
Finished Jun 07 07:33:53 PM PDT 24
Peak memory 218756 kb
Host smart-cc2815f2-6f93-4004-b477-7977e347a962
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668781824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3668781824
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1360990873
Short name T113
Test name
Test status
Simulation time 1249794193 ps
CPU time 83.89 seconds
Started Jun 07 07:33:08 PM PDT 24
Finished Jun 07 07:34:37 PM PDT 24
Peak memory 214044 kb
Host smart-12c6e522-1a3c-421c-bc21-38484f6da450
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360990873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1360990873
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3125845424
Short name T447
Test name
Test status
Simulation time 7537093113 ps
CPU time 28.85 seconds
Started Jun 07 07:33:23 PM PDT 24
Finished Jun 07 07:33:56 PM PDT 24
Peak memory 217128 kb
Host smart-1372ec52-7a84-4cf9-b43b-f00c0f27ffe3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125845424 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3125845424
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2931215020
Short name T429
Test name
Test status
Simulation time 167626095 ps
CPU time 8.27 seconds
Started Jun 07 07:33:24 PM PDT 24
Finished Jun 07 07:33:36 PM PDT 24
Peak memory 211064 kb
Host smart-15f87723-d9e1-4068-a510-0ecc9b884670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931215020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2931215020
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3140707724
Short name T417
Test name
Test status
Simulation time 18645802608 ps
CPU time 129.98 seconds
Started Jun 07 07:33:19 PM PDT 24
Finished Jun 07 07:35:33 PM PDT 24
Peak memory 219276 kb
Host smart-a7c9859e-8f98-4469-b092-bdaffac7d5e1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140707724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3140707724
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1462348039
Short name T442
Test name
Test status
Simulation time 15655651191 ps
CPU time 31.05 seconds
Started Jun 07 07:33:18 PM PDT 24
Finished Jun 07 07:33:54 PM PDT 24
Peak memory 212884 kb
Host smart-885073a1-2045-4dc0-b585-6a2445531cea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462348039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1462348039
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4160171620
Short name T388
Test name
Test status
Simulation time 4104487612 ps
CPU time 25.19 seconds
Started Jun 07 07:33:20 PM PDT 24
Finished Jun 07 07:33:49 PM PDT 24
Peak memory 217724 kb
Host smart-bdb868e5-9204-4193-a54d-bf2a7a1f92c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160171620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.4160171620
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4008442978
Short name T119
Test name
Test status
Simulation time 22263578909 ps
CPU time 172.89 seconds
Started Jun 07 07:33:20 PM PDT 24
Finished Jun 07 07:36:17 PM PDT 24
Peak memory 214620 kb
Host smart-4d8b7f7b-267c-4584-bc16-fc55c9cf5551
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008442978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.4008442978
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.924546119
Short name T50
Test name
Test status
Simulation time 4531468697 ps
CPU time 22.65 seconds
Started Jun 07 07:33:22 PM PDT 24
Finished Jun 07 07:33:50 PM PDT 24
Peak memory 214896 kb
Host smart-ef1826a2-f55c-4e1e-8c47-969b9c10ba0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924546119 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.924546119
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3385859385
Short name T74
Test name
Test status
Simulation time 169199866 ps
CPU time 8.43 seconds
Started Jun 07 07:33:25 PM PDT 24
Finished Jun 07 07:33:37 PM PDT 24
Peak memory 211148 kb
Host smart-9da2701b-d71c-48af-9236-21a036256071
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385859385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3385859385
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2307946751
Short name T434
Test name
Test status
Simulation time 4479720302 ps
CPU time 57.19 seconds
Started Jun 07 07:33:21 PM PDT 24
Finished Jun 07 07:34:22 PM PDT 24
Peak memory 215732 kb
Host smart-3ebbf095-3182-49aa-bb7d-cbc1fb53b061
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307946751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2307946751
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1721703109
Short name T63
Test name
Test status
Simulation time 6137700557 ps
CPU time 29.98 seconds
Started Jun 07 07:33:18 PM PDT 24
Finished Jun 07 07:33:52 PM PDT 24
Peak memory 213048 kb
Host smart-5078822d-b2f2-4b31-b393-539e9013f65a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721703109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1721703109
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.902448164
Short name T430
Test name
Test status
Simulation time 5424492593 ps
CPU time 19.27 seconds
Started Jun 07 07:33:20 PM PDT 24
Finished Jun 07 07:33:44 PM PDT 24
Peak memory 218508 kb
Host smart-185e4efe-f5c2-4239-935f-fc06db004aa5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902448164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.902448164
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.868945488
Short name T120
Test name
Test status
Simulation time 1468393102 ps
CPU time 90.73 seconds
Started Jun 07 07:33:20 PM PDT 24
Finished Jun 07 07:34:56 PM PDT 24
Peak memory 213964 kb
Host smart-2885372c-dd43-4dd1-9892-95d880851ae0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868945488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.868945488
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1388253861
Short name T69
Test name
Test status
Simulation time 2284817039 ps
CPU time 9.46 seconds
Started Jun 07 07:33:18 PM PDT 24
Finished Jun 07 07:33:32 PM PDT 24
Peak memory 217232 kb
Host smart-cd62b601-bd10-445b-b2ca-800282673b4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388253861 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1388253861
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.584414651
Short name T392
Test name
Test status
Simulation time 8561639615 ps
CPU time 32.86 seconds
Started Jun 07 07:33:22 PM PDT 24
Finished Jun 07 07:33:59 PM PDT 24
Peak memory 212084 kb
Host smart-7fc5a2d2-51d4-433e-9b7c-2d6723ac8acd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584414651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.584414651
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4010345841
Short name T397
Test name
Test status
Simulation time 2992846565 ps
CPU time 38.14 seconds
Started Jun 07 07:33:22 PM PDT 24
Finished Jun 07 07:34:05 PM PDT 24
Peak memory 214188 kb
Host smart-15a6ed28-b001-41fa-a035-2679ba203ff7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010345841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.4010345841
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1639875028
Short name T99
Test name
Test status
Simulation time 4757814346 ps
CPU time 25.78 seconds
Started Jun 07 07:33:18 PM PDT 24
Finished Jun 07 07:33:48 PM PDT 24
Peak memory 212972 kb
Host smart-0bae900b-e739-4651-9031-94175bfd7693
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639875028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1639875028
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2372670745
Short name T395
Test name
Test status
Simulation time 1476772693 ps
CPU time 21.3 seconds
Started Jun 07 07:33:19 PM PDT 24
Finished Jun 07 07:33:45 PM PDT 24
Peak memory 219040 kb
Host smart-75473d85-8a44-45bc-a79a-7077e4ac6180
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372670745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2372670745
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2589316803
Short name T115
Test name
Test status
Simulation time 11012498381 ps
CPU time 168.22 seconds
Started Jun 07 07:33:18 PM PDT 24
Finished Jun 07 07:36:10 PM PDT 24
Peak memory 214652 kb
Host smart-d6ac9c2b-8b4b-4750-aa9f-adf07f6a6bfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589316803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2589316803
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.372470502
Short name T448
Test name
Test status
Simulation time 8066254925 ps
CPU time 30.66 seconds
Started Jun 07 07:33:20 PM PDT 24
Finished Jun 07 07:33:55 PM PDT 24
Peak memory 216560 kb
Host smart-565896f9-3b1f-45b3-9497-7249d86a2126
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372470502 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.372470502
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2041919485
Short name T376
Test name
Test status
Simulation time 5686373143 ps
CPU time 20.78 seconds
Started Jun 07 07:33:18 PM PDT 24
Finished Jun 07 07:33:44 PM PDT 24
Peak memory 212300 kb
Host smart-8b3bbe33-8c5e-4759-8aa6-6c1c267bf040
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041919485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2041919485
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1129089768
Short name T78
Test name
Test status
Simulation time 38101844577 ps
CPU time 130.3 seconds
Started Jun 07 07:33:22 PM PDT 24
Finished Jun 07 07:35:37 PM PDT 24
Peak memory 214192 kb
Host smart-5c1f15a7-1e12-4518-a51b-beea4c8465bb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129089768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1129089768
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2975883641
Short name T405
Test name
Test status
Simulation time 14382804472 ps
CPU time 29.71 seconds
Started Jun 07 07:33:20 PM PDT 24
Finished Jun 07 07:33:54 PM PDT 24
Peak memory 212900 kb
Host smart-e1fe6957-d37a-4272-a4fe-da1be6a063e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975883641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2975883641
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3340359784
Short name T48
Test name
Test status
Simulation time 7900939242 ps
CPU time 33.76 seconds
Started Jun 07 07:33:21 PM PDT 24
Finished Jun 07 07:34:00 PM PDT 24
Peak memory 217920 kb
Host smart-e686972f-8707-4e43-9603-91063399637b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340359784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3340359784
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2201527072
Short name T49
Test name
Test status
Simulation time 15695200683 ps
CPU time 29.35 seconds
Started Jun 07 07:33:21 PM PDT 24
Finished Jun 07 07:33:55 PM PDT 24
Peak memory 217584 kb
Host smart-824f1f39-e8d9-442b-a912-1d4e93d23b36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201527072 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2201527072
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2584300035
Short name T436
Test name
Test status
Simulation time 2936227664 ps
CPU time 24.03 seconds
Started Jun 07 07:33:19 PM PDT 24
Finished Jun 07 07:33:47 PM PDT 24
Peak memory 212228 kb
Host smart-2bf52aaf-6d60-46c0-8909-20c6e7f12ee7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584300035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2584300035
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.609773902
Short name T404
Test name
Test status
Simulation time 74818124890 ps
CPU time 133.69 seconds
Started Jun 07 07:33:22 PM PDT 24
Finished Jun 07 07:35:41 PM PDT 24
Peak memory 214176 kb
Host smart-84de02d8-275d-415c-a95e-687328ecf2f5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609773902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.609773902
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1704670819
Short name T101
Test name
Test status
Simulation time 7057809628 ps
CPU time 29.76 seconds
Started Jun 07 07:33:22 PM PDT 24
Finished Jun 07 07:33:57 PM PDT 24
Peak memory 212928 kb
Host smart-62a98a2f-3559-41f1-99b9-23a8d4bfa41f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704670819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1704670819
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2539252650
Short name T423
Test name
Test status
Simulation time 1389793047 ps
CPU time 19.88 seconds
Started Jun 07 07:33:21 PM PDT 24
Finished Jun 07 07:33:45 PM PDT 24
Peak memory 217200 kb
Host smart-03050896-857a-4e8c-b1fc-168e246dd11a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539252650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2539252650
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2506425594
Short name T360
Test name
Test status
Simulation time 175581088 ps
CPU time 8.71 seconds
Started Jun 07 07:33:25 PM PDT 24
Finished Jun 07 07:33:37 PM PDT 24
Peak memory 214512 kb
Host smart-15ce14a7-1562-420d-b16b-5e9e9c839e10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506425594 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2506425594
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.474729855
Short name T91
Test name
Test status
Simulation time 167562002 ps
CPU time 8.33 seconds
Started Jun 07 07:33:25 PM PDT 24
Finished Jun 07 07:33:37 PM PDT 24
Peak memory 210920 kb
Host smart-0e21d5bf-7eff-445e-8cb1-8ab85d16b225
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474729855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.474729855
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3254406936
Short name T409
Test name
Test status
Simulation time 15404952756 ps
CPU time 31.62 seconds
Started Jun 07 07:33:21 PM PDT 24
Finished Jun 07 07:33:57 PM PDT 24
Peak memory 212544 kb
Host smart-801f170c-2b8b-442c-8257-546e5717d97d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254406936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3254406936
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1895546691
Short name T402
Test name
Test status
Simulation time 570519602 ps
CPU time 11.74 seconds
Started Jun 07 07:33:25 PM PDT 24
Finished Jun 07 07:33:40 PM PDT 24
Peak memory 216572 kb
Host smart-bcb0994c-f024-4603-833b-b7d79219e2e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895546691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1895546691
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3118233716
Short name T47
Test name
Test status
Simulation time 8493048309 ps
CPU time 21.14 seconds
Started Jun 07 07:33:19 PM PDT 24
Finished Jun 07 07:33:45 PM PDT 24
Peak memory 214052 kb
Host smart-9381cb4d-abd9-4a74-8d96-526dc1c9c2bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118233716 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3118233716
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4175568167
Short name T377
Test name
Test status
Simulation time 4835905687 ps
CPU time 15.37 seconds
Started Jun 07 07:33:17 PM PDT 24
Finished Jun 07 07:33:36 PM PDT 24
Peak memory 211824 kb
Host smart-7691ebfc-48e1-47aa-8b82-c783e17f4f19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175568167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.4175568167
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.43765358
Short name T389
Test name
Test status
Simulation time 51971415733 ps
CPU time 115.06 seconds
Started Jun 07 07:33:21 PM PDT 24
Finished Jun 07 07:35:21 PM PDT 24
Peak memory 214184 kb
Host smart-a8465a66-1ced-42c8-a045-66603141e73c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43765358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pas
sthru_mem_tl_intg_err.43765358
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4179849643
Short name T72
Test name
Test status
Simulation time 736550163 ps
CPU time 12.05 seconds
Started Jun 07 07:33:21 PM PDT 24
Finished Jun 07 07:33:37 PM PDT 24
Peak memory 212668 kb
Host smart-0b9d6de0-a100-4463-af5a-7a13bfc9e220
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179849643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.4179849643
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.40291360
Short name T413
Test name
Test status
Simulation time 24542060568 ps
CPU time 32.22 seconds
Started Jun 07 07:33:25 PM PDT 24
Finished Jun 07 07:34:01 PM PDT 24
Peak memory 218724 kb
Host smart-537cfc63-6fd4-41fc-aaf9-22e3a399dae9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40291360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.40291360
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3188010266
Short name T387
Test name
Test status
Simulation time 7328074850 ps
CPU time 97.7 seconds
Started Jun 07 07:33:20 PM PDT 24
Finished Jun 07 07:35:02 PM PDT 24
Peak memory 214088 kb
Host smart-63f8c7e1-875b-42e4-9d6b-989d64e27cc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188010266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3188010266
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.410046350
Short name T51
Test name
Test status
Simulation time 3130955054 ps
CPU time 13.6 seconds
Started Jun 07 07:33:29 PM PDT 24
Finished Jun 07 07:33:45 PM PDT 24
Peak memory 216536 kb
Host smart-a676cf4c-97fe-4c76-9fb4-0279027df6be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410046350 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.410046350
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1931560813
Short name T107
Test name
Test status
Simulation time 1643660526 ps
CPU time 11.45 seconds
Started Jun 07 07:33:31 PM PDT 24
Finished Jun 07 07:33:46 PM PDT 24
Peak memory 212344 kb
Host smart-1b234fce-0b78-4826-bb18-a95ebec5f3df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931560813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1931560813
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1579056250
Short name T76
Test name
Test status
Simulation time 30822501544 ps
CPU time 127.5 seconds
Started Jun 07 07:33:30 PM PDT 24
Finished Jun 07 07:35:41 PM PDT 24
Peak memory 214512 kb
Host smart-62d2f180-c689-411f-8c73-ea2f9a08e11c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579056250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1579056250
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.870720692
Short name T408
Test name
Test status
Simulation time 438321670 ps
CPU time 11.88 seconds
Started Jun 07 07:33:32 PM PDT 24
Finished Jun 07 07:33:47 PM PDT 24
Peak memory 212508 kb
Host smart-7e2d6f4d-ba63-4dc5-82c5-6c524e9df96d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870720692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.870720692
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2273426820
Short name T443
Test name
Test status
Simulation time 3674538755 ps
CPU time 32.7 seconds
Started Jun 07 07:33:31 PM PDT 24
Finished Jun 07 07:34:07 PM PDT 24
Peak memory 218244 kb
Host smart-3533edc0-3115-453f-88fc-2d5d3a82c13c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273426820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2273426820
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1106853044
Short name T116
Test name
Test status
Simulation time 15988586392 ps
CPU time 173.71 seconds
Started Jun 07 07:33:30 PM PDT 24
Finished Jun 07 07:36:26 PM PDT 24
Peak memory 214552 kb
Host smart-93317c26-79de-4997-b707-f77abb492f86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106853044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1106853044
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3774484063
Short name T366
Test name
Test status
Simulation time 18959660463 ps
CPU time 20.23 seconds
Started Jun 07 07:33:30 PM PDT 24
Finished Jun 07 07:33:54 PM PDT 24
Peak memory 216012 kb
Host smart-ebb51875-8d9c-432b-b2ab-cc27c0133b99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774484063 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3774484063
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3168557977
Short name T393
Test name
Test status
Simulation time 5585289324 ps
CPU time 23.93 seconds
Started Jun 07 07:33:28 PM PDT 24
Finished Jun 07 07:33:55 PM PDT 24
Peak memory 212632 kb
Host smart-0b133618-0cee-4274-94ae-85d8de8d6fc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168557977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3168557977
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.414489246
Short name T75
Test name
Test status
Simulation time 15167602911 ps
CPU time 61.97 seconds
Started Jun 07 07:33:29 PM PDT 24
Finished Jun 07 07:34:34 PM PDT 24
Peak memory 219216 kb
Host smart-84339365-1fac-4df1-a122-06c2d1aa32da
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414489246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.414489246
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.838645247
Short name T401
Test name
Test status
Simulation time 2689783571 ps
CPU time 24.73 seconds
Started Jun 07 07:33:31 PM PDT 24
Finished Jun 07 07:33:59 PM PDT 24
Peak memory 212276 kb
Host smart-6002b3a3-9b0e-4d94-86f3-19d749f8f882
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838645247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.838645247
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4078236120
Short name T431
Test name
Test status
Simulation time 4836565053 ps
CPU time 26.13 seconds
Started Jun 07 07:33:29 PM PDT 24
Finished Jun 07 07:33:58 PM PDT 24
Peak memory 218752 kb
Host smart-04349cdc-bc6e-4956-8e9a-d381eba94391
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078236120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.4078236120
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2749890650
Short name T398
Test name
Test status
Simulation time 492838417 ps
CPU time 157.81 seconds
Started Jun 07 07:33:29 PM PDT 24
Finished Jun 07 07:36:10 PM PDT 24
Peak memory 219188 kb
Host smart-1583277f-1e10-4370-a961-105eccbdec50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749890650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2749890650
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2566765238
Short name T359
Test name
Test status
Simulation time 704750346 ps
CPU time 8.54 seconds
Started Jun 07 07:33:27 PM PDT 24
Finished Jun 07 07:33:38 PM PDT 24
Peak memory 214688 kb
Host smart-d0973b86-3dd4-43ac-9179-8c7bf922c8d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566765238 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2566765238
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3322323795
Short name T424
Test name
Test status
Simulation time 4866350624 ps
CPU time 15.25 seconds
Started Jun 07 07:33:32 PM PDT 24
Finished Jun 07 07:33:50 PM PDT 24
Peak memory 211656 kb
Host smart-4a9c7ea7-56b0-4005-88d4-67abefda66d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322323795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3322323795
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1477756172
Short name T403
Test name
Test status
Simulation time 12277086559 ps
CPU time 30.22 seconds
Started Jun 07 07:33:30 PM PDT 24
Finished Jun 07 07:34:04 PM PDT 24
Peak memory 213148 kb
Host smart-4659cad5-7f0b-4020-9346-6fd686d307de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477756172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1477756172
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1194710666
Short name T378
Test name
Test status
Simulation time 57373263391 ps
CPU time 32.09 seconds
Started Jun 07 07:33:27 PM PDT 24
Finished Jun 07 07:34:02 PM PDT 24
Peak memory 219108 kb
Host smart-1d3b2b4d-9224-446e-9b3c-c35b40dc8703
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194710666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1194710666
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2300451444
Short name T58
Test name
Test status
Simulation time 3588386310 ps
CPU time 101.75 seconds
Started Jun 07 07:33:30 PM PDT 24
Finished Jun 07 07:35:16 PM PDT 24
Peak memory 213908 kb
Host smart-584f8414-7dfa-4dd7-b810-13e2e20eae0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300451444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2300451444
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2962491161
Short name T90
Test name
Test status
Simulation time 3359214505 ps
CPU time 27.36 seconds
Started Jun 07 07:33:11 PM PDT 24
Finished Jun 07 07:33:44 PM PDT 24
Peak memory 212120 kb
Host smart-ea66a624-452e-4d4a-b031-d11c4a93c8b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962491161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2962491161
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1711463563
Short name T415
Test name
Test status
Simulation time 461848988 ps
CPU time 9.96 seconds
Started Jun 07 07:33:15 PM PDT 24
Finished Jun 07 07:33:29 PM PDT 24
Peak memory 210944 kb
Host smart-85568e32-3cf9-4867-8a9c-3c5382e1b1b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711463563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1711463563
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2723225061
Short name T422
Test name
Test status
Simulation time 15679455923 ps
CPU time 35.76 seconds
Started Jun 07 07:33:09 PM PDT 24
Finished Jun 07 07:33:50 PM PDT 24
Peak memory 212176 kb
Host smart-d804b290-d8aa-4a62-b0c0-f1282e6cbf11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723225061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2723225061
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2154186665
Short name T419
Test name
Test status
Simulation time 1025844244 ps
CPU time 15.04 seconds
Started Jun 07 07:33:12 PM PDT 24
Finished Jun 07 07:33:32 PM PDT 24
Peak memory 217000 kb
Host smart-f818b8f1-c62e-45a7-92ac-3db48f0822bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154186665 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2154186665
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.862395799
Short name T416
Test name
Test status
Simulation time 6398073437 ps
CPU time 32.94 seconds
Started Jun 07 07:33:10 PM PDT 24
Finished Jun 07 07:33:48 PM PDT 24
Peak memory 212164 kb
Host smart-07be00cd-833e-42b2-b04f-845ddcda6a96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862395799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.862395799
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1781720524
Short name T372
Test name
Test status
Simulation time 5946609024 ps
CPU time 16.17 seconds
Started Jun 07 07:33:15 PM PDT 24
Finished Jun 07 07:33:35 PM PDT 24
Peak memory 211096 kb
Host smart-e2a15a42-e6b9-4b19-83e5-e230ea0b8f1d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781720524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1781720524
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1667274981
Short name T427
Test name
Test status
Simulation time 6422060939 ps
CPU time 27.53 seconds
Started Jun 07 07:33:09 PM PDT 24
Finished Jun 07 07:33:42 PM PDT 24
Peak memory 210800 kb
Host smart-1b63664f-46e9-4cf6-849c-36b1b6c048cc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667274981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1667274981
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.312448792
Short name T451
Test name
Test status
Simulation time 706322056 ps
CPU time 38.66 seconds
Started Jun 07 07:33:09 PM PDT 24
Finished Jun 07 07:33:53 PM PDT 24
Peak memory 219180 kb
Host smart-45dd42f3-0c04-4018-bc2d-c4ae30ec9405
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312448792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.312448792
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4125315426
Short name T425
Test name
Test status
Simulation time 2794882379 ps
CPU time 25.13 seconds
Started Jun 07 07:33:11 PM PDT 24
Finished Jun 07 07:33:41 PM PDT 24
Peak memory 212548 kb
Host smart-e965b9ba-7195-4d2b-9045-56777e6ee7c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125315426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.4125315426
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4239877273
Short name T362
Test name
Test status
Simulation time 1622429085 ps
CPU time 22.35 seconds
Started Jun 07 07:33:07 PM PDT 24
Finished Jun 07 07:33:33 PM PDT 24
Peak memory 217356 kb
Host smart-08460e14-38c3-4660-ac6d-761f37fe28b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239877273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.4239877273
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.66468372
Short name T117
Test name
Test status
Simulation time 14421115086 ps
CPU time 96.35 seconds
Started Jun 07 07:33:10 PM PDT 24
Finished Jun 07 07:34:51 PM PDT 24
Peak memory 214032 kb
Host smart-2aa9f3c5-0104-463f-8688-d4fda88de3eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66468372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg
_err.66468372
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3128795444
Short name T62
Test name
Test status
Simulation time 8519398246 ps
CPU time 32.71 seconds
Started Jun 07 07:33:12 PM PDT 24
Finished Jun 07 07:33:50 PM PDT 24
Peak memory 212144 kb
Host smart-e6fd3f45-1d41-47f3-920b-62823b7c4d6a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128795444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3128795444
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.714914555
Short name T368
Test name
Test status
Simulation time 16343089318 ps
CPU time 30 seconds
Started Jun 07 07:33:09 PM PDT 24
Finished Jun 07 07:33:45 PM PDT 24
Peak memory 212156 kb
Host smart-c88dca0c-1087-4692-91e0-58a9ce15b31c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714914555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.714914555
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1738538113
Short name T407
Test name
Test status
Simulation time 178461464 ps
CPU time 15.71 seconds
Started Jun 07 07:33:12 PM PDT 24
Finished Jun 07 07:33:33 PM PDT 24
Peak memory 212124 kb
Host smart-48175a8c-bbdb-4bd9-af18-23ed79929c54
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738538113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1738538113
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1188409133
Short name T428
Test name
Test status
Simulation time 2621249514 ps
CPU time 11.76 seconds
Started Jun 07 07:33:11 PM PDT 24
Finished Jun 07 07:33:28 PM PDT 24
Peak memory 213708 kb
Host smart-d8b93fbb-8d36-4742-9351-6e0cb417183d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188409133 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1188409133
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1013965374
Short name T365
Test name
Test status
Simulation time 17036161102 ps
CPU time 34.34 seconds
Started Jun 07 07:33:10 PM PDT 24
Finished Jun 07 07:33:50 PM PDT 24
Peak memory 212696 kb
Host smart-2012442e-7a22-412b-a60e-593266d8bd22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013965374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1013965374
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3855642775
Short name T439
Test name
Test status
Simulation time 15072639793 ps
CPU time 29.49 seconds
Started Jun 07 07:33:11 PM PDT 24
Finished Jun 07 07:33:46 PM PDT 24
Peak memory 211044 kb
Host smart-59a1dba0-bef9-457f-8b11-a7a398dea6b9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855642775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3855642775
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.370453205
Short name T406
Test name
Test status
Simulation time 169115348 ps
CPU time 8.4 seconds
Started Jun 07 07:33:12 PM PDT 24
Finished Jun 07 07:33:25 PM PDT 24
Peak memory 210788 kb
Host smart-58bf07be-94dc-42d3-8792-6f2f46b8438d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370453205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
370453205
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1502214184
Short name T370
Test name
Test status
Simulation time 102055246744 ps
CPU time 94.18 seconds
Started Jun 07 07:33:11 PM PDT 24
Finished Jun 07 07:34:50 PM PDT 24
Peak memory 214140 kb
Host smart-456ddd94-4fc6-499b-afa9-31ee633a56d5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502214184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1502214184
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3582546640
Short name T102
Test name
Test status
Simulation time 5869169732 ps
CPU time 25.39 seconds
Started Jun 07 07:33:10 PM PDT 24
Finished Jun 07 07:33:41 PM PDT 24
Peak memory 212956 kb
Host smart-692c5be3-856c-416c-b26a-76752ae6afa0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582546640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3582546640
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4173039837
Short name T396
Test name
Test status
Simulation time 9389002081 ps
CPU time 31.39 seconds
Started Jun 07 07:33:14 PM PDT 24
Finished Jun 07 07:33:50 PM PDT 24
Peak memory 212272 kb
Host smart-746d2621-dd6a-41ab-951f-d1fc865eede4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173039837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.4173039837
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.483744672
Short name T106
Test name
Test status
Simulation time 1709589718 ps
CPU time 11.45 seconds
Started Jun 07 07:33:10 PM PDT 24
Finished Jun 07 07:33:27 PM PDT 24
Peak memory 211056 kb
Host smart-747d5b5b-64a7-4618-ab71-8dd7b975aee3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483744672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.483744672
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.767779165
Short name T445
Test name
Test status
Simulation time 15989711030 ps
CPU time 35.29 seconds
Started Jun 07 07:33:13 PM PDT 24
Finished Jun 07 07:33:52 PM PDT 24
Peak memory 212468 kb
Host smart-dc117fb3-f725-4596-8980-40a075634a90
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767779165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.767779165
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3250736021
Short name T412
Test name
Test status
Simulation time 11913254332 ps
CPU time 25.54 seconds
Started Jun 07 07:33:15 PM PDT 24
Finished Jun 07 07:33:45 PM PDT 24
Peak memory 215772 kb
Host smart-bd39ea08-7a92-4d9c-8e1f-2f9c182b1948
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250736021 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3250736021
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.427711544
Short name T86
Test name
Test status
Simulation time 3375545580 ps
CPU time 29.09 seconds
Started Jun 07 07:33:12 PM PDT 24
Finished Jun 07 07:33:46 PM PDT 24
Peak memory 212032 kb
Host smart-4282730e-b90b-49c8-8466-d6fc8afb2c0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427711544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.427711544
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.654475840
Short name T411
Test name
Test status
Simulation time 14096782079 ps
CPU time 15.14 seconds
Started Jun 07 07:33:17 PM PDT 24
Finished Jun 07 07:33:36 PM PDT 24
Peak memory 211128 kb
Host smart-6f6ca0c4-6b7f-4322-9743-3a030fc60f27
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654475840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.654475840
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.863247964
Short name T374
Test name
Test status
Simulation time 17643285763 ps
CPU time 21.37 seconds
Started Jun 07 07:33:11 PM PDT 24
Finished Jun 07 07:33:37 PM PDT 24
Peak memory 211108 kb
Host smart-d522f07d-dff5-4355-8c76-5b559a1c6bdd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863247964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
863247964
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3869131244
Short name T87
Test name
Test status
Simulation time 33613496215 ps
CPU time 138.34 seconds
Started Jun 07 07:33:13 PM PDT 24
Finished Jun 07 07:35:36 PM PDT 24
Peak memory 214108 kb
Host smart-3beea179-34ef-4e93-a8d3-c473ffc4b299
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869131244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3869131244
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3603866777
Short name T100
Test name
Test status
Simulation time 2059829250 ps
CPU time 8.19 seconds
Started Jun 07 07:33:12 PM PDT 24
Finished Jun 07 07:33:25 PM PDT 24
Peak memory 211520 kb
Host smart-81f0e081-5b2f-4e1a-8d07-9424c8782e1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603866777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3603866777
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2898546794
Short name T418
Test name
Test status
Simulation time 2211557223 ps
CPU time 25.78 seconds
Started Jun 07 07:33:11 PM PDT 24
Finished Jun 07 07:33:42 PM PDT 24
Peak memory 218848 kb
Host smart-81e56624-e5ef-4a8d-98dc-9902aef4bf73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898546794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2898546794
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2420152276
Short name T121
Test name
Test status
Simulation time 12496357691 ps
CPU time 174.93 seconds
Started Jun 07 07:33:12 PM PDT 24
Finished Jun 07 07:36:12 PM PDT 24
Peak memory 214612 kb
Host smart-77e16995-d021-4395-b7d1-539b602e54c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420152276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2420152276
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2786112250
Short name T432
Test name
Test status
Simulation time 4253892169 ps
CPU time 33.78 seconds
Started Jun 07 07:33:15 PM PDT 24
Finished Jun 07 07:33:53 PM PDT 24
Peak memory 216828 kb
Host smart-385314f3-d1aa-4ec3-af23-b1d65a7e8481
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786112250 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2786112250
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2586358445
Short name T435
Test name
Test status
Simulation time 2851631352 ps
CPU time 26.2 seconds
Started Jun 07 07:33:13 PM PDT 24
Finished Jun 07 07:33:44 PM PDT 24
Peak memory 211996 kb
Host smart-e21e6f76-4124-4429-aaad-6bff271546a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586358445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2586358445
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3781733877
Short name T441
Test name
Test status
Simulation time 8244599950 ps
CPU time 88.82 seconds
Started Jun 07 07:33:11 PM PDT 24
Finished Jun 07 07:34:45 PM PDT 24
Peak memory 214104 kb
Host smart-26fb70b8-6c12-4a87-9ad5-761d3d50590a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781733877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3781733877
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2036897599
Short name T70
Test name
Test status
Simulation time 175270425 ps
CPU time 12.11 seconds
Started Jun 07 07:33:16 PM PDT 24
Finished Jun 07 07:33:32 PM PDT 24
Peak memory 212692 kb
Host smart-619e0b6e-adf6-4e0d-a528-5aeabc91381b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036897599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2036897599
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3254105534
Short name T363
Test name
Test status
Simulation time 9874357188 ps
CPU time 28.08 seconds
Started Jun 07 07:33:16 PM PDT 24
Finished Jun 07 07:33:48 PM PDT 24
Peak memory 217808 kb
Host smart-3dc902fa-7c4b-4cfe-aa0c-fd53bb689736
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254105534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3254105534
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2474140035
Short name T426
Test name
Test status
Simulation time 4041987373 ps
CPU time 92.21 seconds
Started Jun 07 07:33:16 PM PDT 24
Finished Jun 07 07:34:52 PM PDT 24
Peak memory 212856 kb
Host smart-8bb5d498-5fde-49de-ae82-9b1d2ffc8329
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474140035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2474140035
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.435214931
Short name T373
Test name
Test status
Simulation time 177695508 ps
CPU time 9.01 seconds
Started Jun 07 07:33:18 PM PDT 24
Finished Jun 07 07:33:31 PM PDT 24
Peak memory 218684 kb
Host smart-fe52184f-8e1f-49af-a291-4994b9ee47b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435214931 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.435214931
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2836333560
Short name T433
Test name
Test status
Simulation time 6245266354 ps
CPU time 19.51 seconds
Started Jun 07 07:33:15 PM PDT 24
Finished Jun 07 07:33:39 PM PDT 24
Peak memory 212588 kb
Host smart-6117fc21-392b-4a69-af4a-b643025ac0c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836333560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2836333560
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2554732051
Short name T84
Test name
Test status
Simulation time 7256351355 ps
CPU time 66.98 seconds
Started Jun 07 07:33:16 PM PDT 24
Finished Jun 07 07:34:27 PM PDT 24
Peak memory 215808 kb
Host smart-735f0efd-4a9b-4cba-a0c1-cf4c5b9e8a7f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554732051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2554732051
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2062878489
Short name T104
Test name
Test status
Simulation time 2851366819 ps
CPU time 24.29 seconds
Started Jun 07 07:33:18 PM PDT 24
Finished Jun 07 07:33:46 PM PDT 24
Peak memory 212420 kb
Host smart-e94ffab7-112b-4361-87fb-f82805875252
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062878489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2062878489
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2143413302
Short name T361
Test name
Test status
Simulation time 29814098636 ps
CPU time 33.03 seconds
Started Jun 07 07:33:15 PM PDT 24
Finished Jun 07 07:33:53 PM PDT 24
Peak memory 218920 kb
Host smart-1484acb7-020c-432a-abb5-7dc95266c01b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143413302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2143413302
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.966774090
Short name T114
Test name
Test status
Simulation time 734020183 ps
CPU time 82.13 seconds
Started Jun 07 07:33:15 PM PDT 24
Finished Jun 07 07:34:42 PM PDT 24
Peak memory 213968 kb
Host smart-c19e0ac5-e93a-40ce-b8ba-dd9108b1c3a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966774090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.966774090
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4160249451
Short name T450
Test name
Test status
Simulation time 966133254 ps
CPU time 14.36 seconds
Started Jun 07 07:33:21 PM PDT 24
Finished Jun 07 07:33:40 PM PDT 24
Peak memory 214396 kb
Host smart-b6fdd191-fdfb-4ea1-9558-46cc6cac659f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160249451 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4160249451
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1299406183
Short name T384
Test name
Test status
Simulation time 11377465411 ps
CPU time 22.93 seconds
Started Jun 07 07:33:20 PM PDT 24
Finished Jun 07 07:33:47 PM PDT 24
Peak memory 212884 kb
Host smart-e967c036-6fd7-4e55-b2c7-78b28c2d9ecc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299406183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1299406183
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2545199965
Short name T379
Test name
Test status
Simulation time 4133778543 ps
CPU time 56.33 seconds
Started Jun 07 07:33:20 PM PDT 24
Finished Jun 07 07:34:20 PM PDT 24
Peak memory 214588 kb
Host smart-ddfd174e-bb8e-4dbc-b736-cea897f73c6b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545199965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2545199965
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.600914960
Short name T79
Test name
Test status
Simulation time 3202603704 ps
CPU time 12.94 seconds
Started Jun 07 07:33:19 PM PDT 24
Finished Jun 07 07:33:37 PM PDT 24
Peak memory 211952 kb
Host smart-d5d45133-0c3a-4cb6-9157-98c089648678
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600914960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.600914960
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1454374715
Short name T410
Test name
Test status
Simulation time 13942588025 ps
CPU time 35.66 seconds
Started Jun 07 07:33:20 PM PDT 24
Finished Jun 07 07:34:00 PM PDT 24
Peak memory 219152 kb
Host smart-cff8c685-a2ed-4aea-8ae4-32a499e2e70e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454374715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1454374715
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.457323763
Short name T59
Test name
Test status
Simulation time 3345587680 ps
CPU time 157.06 seconds
Started Jun 07 07:33:20 PM PDT 24
Finished Jun 07 07:36:01 PM PDT 24
Peak memory 214084 kb
Host smart-e3fce44f-7cc9-4549-947f-266fd5a2a0a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457323763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.457323763
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1817376851
Short name T380
Test name
Test status
Simulation time 2432047722 ps
CPU time 22.68 seconds
Started Jun 07 07:33:20 PM PDT 24
Finished Jun 07 07:33:47 PM PDT 24
Peak memory 219280 kb
Host smart-412e1538-01ba-4ba2-a120-92c8135a1589
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817376851 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1817376851
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1778706680
Short name T73
Test name
Test status
Simulation time 5596136460 ps
CPU time 25.45 seconds
Started Jun 07 07:33:21 PM PDT 24
Finished Jun 07 07:33:50 PM PDT 24
Peak memory 212620 kb
Host smart-7350ada2-870a-4dd4-be44-e619bc52c8f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778706680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1778706680
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.513951457
Short name T88
Test name
Test status
Simulation time 60188322964 ps
CPU time 126.04 seconds
Started Jun 07 07:33:23 PM PDT 24
Finished Jun 07 07:35:33 PM PDT 24
Peak memory 214216 kb
Host smart-2e01b15e-3eb9-4ca4-b52b-e833f7e9e3eb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513951457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.513951457
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.685019246
Short name T444
Test name
Test status
Simulation time 14059992548 ps
CPU time 33.51 seconds
Started Jun 07 07:33:18 PM PDT 24
Finished Jun 07 07:33:56 PM PDT 24
Peak memory 213016 kb
Host smart-00a8218c-9eef-447a-8bfe-a6b411691942
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685019246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.685019246
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1730039114
Short name T421
Test name
Test status
Simulation time 6787423388 ps
CPU time 32.45 seconds
Started Jun 07 07:33:17 PM PDT 24
Finished Jun 07 07:33:54 PM PDT 24
Peak memory 217760 kb
Host smart-62f88f5f-98f2-4f86-8cc7-c1414816be80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730039114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1730039114
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3281892535
Short name T386
Test name
Test status
Simulation time 1099001370 ps
CPU time 9.47 seconds
Started Jun 07 07:33:18 PM PDT 24
Finished Jun 07 07:33:32 PM PDT 24
Peak memory 217456 kb
Host smart-8d060733-e086-4b7a-ac1e-ae8ef34f3903
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281892535 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3281892535
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2020315236
Short name T85
Test name
Test status
Simulation time 5894943014 ps
CPU time 17.06 seconds
Started Jun 07 07:33:22 PM PDT 24
Finished Jun 07 07:33:43 PM PDT 24
Peak memory 212888 kb
Host smart-e49fe21a-58b4-48b8-ab30-b0bcdae71132
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020315236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2020315236
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2437520279
Short name T399
Test name
Test status
Simulation time 35427563552 ps
CPU time 94.12 seconds
Started Jun 07 07:33:19 PM PDT 24
Finished Jun 07 07:34:57 PM PDT 24
Peak memory 214116 kb
Host smart-c47a552d-8a25-4d12-8ce1-372f30798351
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437520279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2437520279
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.995995403
Short name T438
Test name
Test status
Simulation time 601419796 ps
CPU time 12.1 seconds
Started Jun 07 07:33:19 PM PDT 24
Finished Jun 07 07:33:35 PM PDT 24
Peak memory 211664 kb
Host smart-2b5518ee-ef1f-49ed-b61c-1dd2434f204d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995995403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.995995403
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1193067699
Short name T382
Test name
Test status
Simulation time 28589745345 ps
CPU time 27.31 seconds
Started Jun 07 07:33:20 PM PDT 24
Finished Jun 07 07:33:52 PM PDT 24
Peak memory 219012 kb
Host smart-8c61a7c8-0ab4-4a48-8719-be9a8878a648
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193067699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1193067699
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2586709448
Short name T446
Test name
Test status
Simulation time 2040868593 ps
CPU time 92.94 seconds
Started Jun 07 07:33:17 PM PDT 24
Finished Jun 07 07:34:54 PM PDT 24
Peak memory 213872 kb
Host smart-19700f7e-6f95-4455-8abd-77f43d77f1e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586709448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2586709448
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.585516357
Short name T181
Test name
Test status
Simulation time 4397002834 ps
CPU time 22.8 seconds
Started Jun 07 08:06:49 PM PDT 24
Finished Jun 07 08:07:15 PM PDT 24
Peak memory 217152 kb
Host smart-33aad3b4-43e7-4684-9557-b606fb0be26c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585516357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.585516357
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4209345600
Short name T345
Test name
Test status
Simulation time 5954035043 ps
CPU time 202.54 seconds
Started Jun 07 08:06:39 PM PDT 24
Finished Jun 07 08:10:04 PM PDT 24
Peak memory 240428 kb
Host smart-46967144-76b0-4ddb-9ae3-4fac95707448
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209345600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.4209345600
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.154463709
Short name T227
Test name
Test status
Simulation time 2668519811 ps
CPU time 25.61 seconds
Started Jun 07 08:06:42 PM PDT 24
Finished Jun 07 08:07:10 PM PDT 24
Peak memory 219104 kb
Host smart-83d82ea1-0a46-4952-b1eb-895a72592f43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=154463709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.154463709
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.137168541
Short name T21
Test name
Test status
Simulation time 13692931433 ps
CPU time 138.53 seconds
Started Jun 07 08:06:50 PM PDT 24
Finished Jun 07 08:09:11 PM PDT 24
Peak memory 233956 kb
Host smart-40e2ced1-edf1-4f46-bd3a-fa3052632bb5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137168541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.137168541
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3388527134
Short name T53
Test name
Test status
Simulation time 4939362750 ps
CPU time 35.73 seconds
Started Jun 07 08:06:40 PM PDT 24
Finished Jun 07 08:07:18 PM PDT 24
Peak memory 216044 kb
Host smart-809ba047-c6b1-492d-8f38-aaf4f4e23ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388527134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3388527134
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1643329242
Short name T297
Test name
Test status
Simulation time 22729391128 ps
CPU time 116.29 seconds
Started Jun 07 08:06:39 PM PDT 24
Finished Jun 07 08:08:37 PM PDT 24
Peak memory 219020 kb
Host smart-cd53d90c-4c98-4f6f-bbf9-f4e547f23786
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643329242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1643329242
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.448968166
Short name T240
Test name
Test status
Simulation time 174586018 ps
CPU time 8.54 seconds
Started Jun 07 08:06:49 PM PDT 24
Finished Jun 07 08:07:00 PM PDT 24
Peak memory 216840 kb
Host smart-f5cc9462-575e-4099-87af-4704b97c4ab5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448968166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.448968166
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.784227935
Short name T242
Test name
Test status
Simulation time 13381546735 ps
CPU time 320.3 seconds
Started Jun 07 08:06:49 PM PDT 24
Finished Jun 07 08:12:12 PM PDT 24
Peak memory 239668 kb
Host smart-a568d175-b7dc-4c78-8743-f816bfe36747
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784227935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.784227935
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1114320728
Short name T219
Test name
Test status
Simulation time 2996763533 ps
CPU time 20.09 seconds
Started Jun 07 08:06:51 PM PDT 24
Finished Jun 07 08:07:13 PM PDT 24
Peak memory 219056 kb
Host smart-6e644be6-b6d9-4a81-9d5a-e8e7aba1cc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114320728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1114320728
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.4090670478
Short name T207
Test name
Test status
Simulation time 10946884039 ps
CPU time 28.89 seconds
Started Jun 07 08:06:49 PM PDT 24
Finished Jun 07 08:07:20 PM PDT 24
Peak memory 219160 kb
Host smart-4b266a30-28f2-4e40-90e3-5c3476fbfadc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4090670478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.4090670478
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1536941685
Short name T30
Test name
Test status
Simulation time 12011571110 ps
CPU time 237.19 seconds
Started Jun 07 08:06:50 PM PDT 24
Finished Jun 07 08:10:50 PM PDT 24
Peak memory 234816 kb
Host smart-9fc8243a-c629-4d44-bec3-03ca2bc7c3e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536941685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1536941685
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.4070378491
Short name T259
Test name
Test status
Simulation time 362757773 ps
CPU time 20.06 seconds
Started Jun 07 08:06:52 PM PDT 24
Finished Jun 07 08:07:14 PM PDT 24
Peak memory 216240 kb
Host smart-6710fd5c-b2aa-4f21-9e62-081b4cf10f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070378491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.4070378491
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2052387260
Short name T335
Test name
Test status
Simulation time 16286877842 ps
CPU time 161.16 seconds
Started Jun 07 08:06:47 PM PDT 24
Finished Jun 07 08:09:30 PM PDT 24
Peak memory 219672 kb
Host smart-e05649ad-807d-4e7b-b985-90656ab48f34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052387260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2052387260
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1764579554
Short name T65
Test name
Test status
Simulation time 14391037229 ps
CPU time 30.07 seconds
Started Jun 07 08:07:04 PM PDT 24
Finished Jun 07 08:07:36 PM PDT 24
Peak memory 217136 kb
Host smart-757349d2-69aa-4229-9843-8e1eddc7f338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764579554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1764579554
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1551296998
Short name T33
Test name
Test status
Simulation time 113450252703 ps
CPU time 365.8 seconds
Started Jun 07 08:07:05 PM PDT 24
Finished Jun 07 08:13:13 PM PDT 24
Peak memory 227848 kb
Host smart-edd3af9f-19b1-4902-9ba7-2011f0da41ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551296998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1551296998
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1177375579
Short name T41
Test name
Test status
Simulation time 346122675 ps
CPU time 19.25 seconds
Started Jun 07 08:07:04 PM PDT 24
Finished Jun 07 08:07:25 PM PDT 24
Peak memory 218988 kb
Host smart-96e6ac65-9ec9-40df-b90f-f4eff58e8333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177375579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1177375579
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1266332257
Short name T235
Test name
Test status
Simulation time 3465460858 ps
CPU time 31.12 seconds
Started Jun 07 08:07:03 PM PDT 24
Finished Jun 07 08:07:36 PM PDT 24
Peak memory 219120 kb
Host smart-5eaf6248-1fc7-4099-afc0-bf0dd2f8e099
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1266332257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1266332257
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1343634181
Short name T186
Test name
Test status
Simulation time 10310716945 ps
CPU time 39.03 seconds
Started Jun 07 08:07:02 PM PDT 24
Finished Jun 07 08:07:43 PM PDT 24
Peak memory 218564 kb
Host smart-4490833f-11be-48b4-b7b1-703ed0aceb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343634181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1343634181
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1326583865
Short name T174
Test name
Test status
Simulation time 2878116083 ps
CPU time 47.1 seconds
Started Jun 07 08:07:03 PM PDT 24
Finished Jun 07 08:07:51 PM PDT 24
Peak memory 219072 kb
Host smart-4a6d1a32-331d-4fc8-baae-5658fcfd8654
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326583865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1326583865
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1966277430
Short name T150
Test name
Test status
Simulation time 8547678447 ps
CPU time 33.96 seconds
Started Jun 07 08:07:03 PM PDT 24
Finished Jun 07 08:07:39 PM PDT 24
Peak memory 217264 kb
Host smart-6b784386-6202-471f-92eb-619095aad464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966277430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1966277430
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1313645031
Short name T198
Test name
Test status
Simulation time 28196936970 ps
CPU time 335.56 seconds
Started Jun 07 08:07:04 PM PDT 24
Finished Jun 07 08:12:41 PM PDT 24
Peak memory 219360 kb
Host smart-6cca0043-3650-4f5e-a9f1-9807f5f15249
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313645031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1313645031
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.414986015
Short name T163
Test name
Test status
Simulation time 28805448664 ps
CPU time 61.72 seconds
Started Jun 07 08:07:04 PM PDT 24
Finished Jun 07 08:08:07 PM PDT 24
Peak memory 219096 kb
Host smart-57066684-2eed-458d-a5ee-20c781c19ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414986015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.414986015
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.303634883
Short name T315
Test name
Test status
Simulation time 1277068614 ps
CPU time 18.3 seconds
Started Jun 07 08:07:01 PM PDT 24
Finished Jun 07 08:07:20 PM PDT 24
Peak memory 219048 kb
Host smart-f2074533-8812-45ef-9d92-7a588ea6016e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=303634883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.303634883
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2271483681
Short name T168
Test name
Test status
Simulation time 5840112848 ps
CPU time 61.21 seconds
Started Jun 07 08:07:03 PM PDT 24
Finished Jun 07 08:08:05 PM PDT 24
Peak memory 216252 kb
Host smart-429ce25f-a24b-47a4-b093-417872bb1d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271483681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2271483681
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.93314048
Short name T8
Test name
Test status
Simulation time 5258615235 ps
CPU time 45.63 seconds
Started Jun 07 08:07:02 PM PDT 24
Finished Jun 07 08:07:49 PM PDT 24
Peak memory 219080 kb
Host smart-c9be1ba9-29ca-41ef-b723-b7a511ebdb12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93314048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 11.rom_ctrl_stress_all.93314048
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1580849013
Short name T330
Test name
Test status
Simulation time 3488845013 ps
CPU time 29 seconds
Started Jun 07 08:07:12 PM PDT 24
Finished Jun 07 08:07:44 PM PDT 24
Peak memory 217028 kb
Host smart-bcd90394-b01a-4a06-8398-071c9c37acdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580849013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1580849013
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.250355439
Short name T191
Test name
Test status
Simulation time 6879609041 ps
CPU time 60.51 seconds
Started Jun 07 08:07:10 PM PDT 24
Finished Jun 07 08:08:13 PM PDT 24
Peak memory 219116 kb
Host smart-fa0b0af4-c805-492b-babe-e68803697799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250355439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.250355439
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.377562
Short name T4
Test name
Test status
Simulation time 3863990738 ps
CPU time 32.32 seconds
Started Jun 07 08:07:11 PM PDT 24
Finished Jun 07 08:07:46 PM PDT 24
Peak memory 219096 kb
Host smart-5b3445ca-cb07-426d-b4db-c594b743b36a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=377562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.377562
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.4213649818
Short name T185
Test name
Test status
Simulation time 6854704333 ps
CPU time 56.54 seconds
Started Jun 07 08:07:09 PM PDT 24
Finished Jun 07 08:08:07 PM PDT 24
Peak memory 216476 kb
Host smart-b74fb85f-c8ac-4a14-b0bb-b2f11a9988a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213649818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.4213649818
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1034819587
Short name T158
Test name
Test status
Simulation time 8391587748 ps
CPU time 81.04 seconds
Started Jun 07 08:07:12 PM PDT 24
Finished Jun 07 08:08:36 PM PDT 24
Peak memory 216824 kb
Host smart-25a225a0-22d5-41bd-a89b-c8051b954290
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034819587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1034819587
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3175481086
Short name T64
Test name
Test status
Simulation time 12588561692 ps
CPU time 28.16 seconds
Started Jun 07 08:07:09 PM PDT 24
Finished Jun 07 08:07:40 PM PDT 24
Peak memory 217112 kb
Host smart-dd723062-8e75-40a1-8e2a-eaa113b843d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175481086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3175481086
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3650342791
Short name T93
Test name
Test status
Simulation time 669076140 ps
CPU time 24.16 seconds
Started Jun 07 08:07:11 PM PDT 24
Finished Jun 07 08:07:38 PM PDT 24
Peak memory 218100 kb
Host smart-a30529c6-9e0e-4eba-a84d-dc2bb56eaab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650342791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3650342791
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2875702028
Short name T260
Test name
Test status
Simulation time 4678307725 ps
CPU time 32.24 seconds
Started Jun 07 08:07:11 PM PDT 24
Finished Jun 07 08:07:45 PM PDT 24
Peak memory 219208 kb
Host smart-02b1fa4f-a464-4ebc-8545-46c86f77f6b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2875702028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2875702028
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3337157916
Short name T129
Test name
Test status
Simulation time 1546106290 ps
CPU time 20.14 seconds
Started Jun 07 08:07:09 PM PDT 24
Finished Jun 07 08:07:32 PM PDT 24
Peak memory 216120 kb
Host smart-be1fd631-6e94-4447-bc28-976f3ca8e29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337157916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3337157916
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1693231332
Short name T80
Test name
Test status
Simulation time 22485425193 ps
CPU time 63.68 seconds
Started Jun 07 08:07:09 PM PDT 24
Finished Jun 07 08:08:15 PM PDT 24
Peak memory 219144 kb
Host smart-f7f8cf39-8934-4cfa-8574-9641ed545614
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693231332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1693231332
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1281719196
Short name T252
Test name
Test status
Simulation time 174682684 ps
CPU time 8.48 seconds
Started Jun 07 08:07:10 PM PDT 24
Finished Jun 07 08:07:21 PM PDT 24
Peak memory 216848 kb
Host smart-a32850f9-b5b6-4176-8cb7-d06a682a0e00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281719196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1281719196
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3865091853
Short name T323
Test name
Test status
Simulation time 14802080080 ps
CPU time 253.34 seconds
Started Jun 07 08:07:07 PM PDT 24
Finished Jun 07 08:11:22 PM PDT 24
Peak memory 219324 kb
Host smart-962d5335-79fe-4b7a-850d-e5dbcbdb3fb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865091853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3865091853
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2896756682
Short name T142
Test name
Test status
Simulation time 5494631446 ps
CPU time 53.13 seconds
Started Jun 07 08:07:10 PM PDT 24
Finished Jun 07 08:08:06 PM PDT 24
Peak memory 219172 kb
Host smart-e5275e72-8e68-4ac3-8cef-ce29d6ec38a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896756682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2896756682
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4277386799
Short name T336
Test name
Test status
Simulation time 3660418823 ps
CPU time 12.02 seconds
Started Jun 07 08:07:10 PM PDT 24
Finished Jun 07 08:07:25 PM PDT 24
Peak memory 219120 kb
Host smart-a231b38d-17b4-4a34-9369-eee1f451625d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4277386799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4277386799
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2000755198
Short name T98
Test name
Test status
Simulation time 11903269976 ps
CPU time 54.43 seconds
Started Jun 07 08:07:10 PM PDT 24
Finished Jun 07 08:08:07 PM PDT 24
Peak memory 217856 kb
Host smart-70931323-8ba8-4343-96e2-173cca2e826b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000755198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2000755198
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1859559919
Short name T245
Test name
Test status
Simulation time 1095441490 ps
CPU time 37.13 seconds
Started Jun 07 08:07:10 PM PDT 24
Finished Jun 07 08:07:50 PM PDT 24
Peak memory 218992 kb
Host smart-9c9abe2c-7767-45fb-9505-7cc6ebea7296
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859559919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1859559919
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1737815262
Short name T310
Test name
Test status
Simulation time 4441421566 ps
CPU time 15.53 seconds
Started Jun 07 08:07:10 PM PDT 24
Finished Jun 07 08:07:28 PM PDT 24
Peak memory 217112 kb
Host smart-31401cc7-b0e2-4c31-92c5-41829fe2ad16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737815262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1737815262
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1223636316
Short name T303
Test name
Test status
Simulation time 16927554773 ps
CPU time 215.88 seconds
Started Jun 07 08:07:12 PM PDT 24
Finished Jun 07 08:10:51 PM PDT 24
Peak memory 237696 kb
Host smart-c0449757-78ff-4a63-a2e3-31ba2c3e0e22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223636316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1223636316
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1282888075
Short name T256
Test name
Test status
Simulation time 1356674770 ps
CPU time 28.32 seconds
Started Jun 07 08:07:11 PM PDT 24
Finished Jun 07 08:07:42 PM PDT 24
Peak memory 218244 kb
Host smart-a1e68e96-1e06-43e4-b19b-aa04f44b54be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282888075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1282888075
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3701274457
Short name T1
Test name
Test status
Simulation time 3632649953 ps
CPU time 12.3 seconds
Started Jun 07 08:07:10 PM PDT 24
Finished Jun 07 08:07:24 PM PDT 24
Peak memory 219104 kb
Host smart-f70672eb-2b65-4f4a-ab84-86ff88302479
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3701274457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3701274457
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3335428853
Short name T241
Test name
Test status
Simulation time 67282303937 ps
CPU time 79.06 seconds
Started Jun 07 08:07:10 PM PDT 24
Finished Jun 07 08:08:32 PM PDT 24
Peak memory 215884 kb
Host smart-922dadd5-666c-4f78-bfe8-250f008b8158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335428853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3335428853
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1872717379
Short name T81
Test name
Test status
Simulation time 2941753220 ps
CPU time 34.89 seconds
Started Jun 07 08:07:10 PM PDT 24
Finished Jun 07 08:07:48 PM PDT 24
Peak memory 219032 kb
Host smart-4f8c1b9d-dc26-48c3-baa8-dd43a5171dc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872717379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1872717379
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3834468049
Short name T314
Test name
Test status
Simulation time 3102379884 ps
CPU time 28.24 seconds
Started Jun 07 08:07:11 PM PDT 24
Finished Jun 07 08:07:42 PM PDT 24
Peak memory 216932 kb
Host smart-af493ca3-60f5-4c9c-8b02-b1b10abbd24e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834468049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3834468049
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.171687340
Short name T37
Test name
Test status
Simulation time 2644921958 ps
CPU time 209.41 seconds
Started Jun 07 08:07:11 PM PDT 24
Finished Jun 07 08:10:43 PM PDT 24
Peak memory 233552 kb
Host smart-664db6db-39f9-4044-b523-bb8de3e7548b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171687340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.171687340
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.778315152
Short name T140
Test name
Test status
Simulation time 3290102176 ps
CPU time 22.81 seconds
Started Jun 07 08:07:11 PM PDT 24
Finished Jun 07 08:07:37 PM PDT 24
Peak memory 219044 kb
Host smart-d4872d67-976d-4d23-a98c-d9bc45c2713b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778315152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.778315152
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1557002640
Short name T224
Test name
Test status
Simulation time 3034288354 ps
CPU time 27.88 seconds
Started Jun 07 08:07:13 PM PDT 24
Finished Jun 07 08:07:44 PM PDT 24
Peak memory 219144 kb
Host smart-92efdbc4-696d-44d0-ab2c-dcff541dca6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1557002640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1557002640
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3176894134
Short name T169
Test name
Test status
Simulation time 5952223463 ps
CPU time 43.29 seconds
Started Jun 07 08:07:10 PM PDT 24
Finished Jun 07 08:07:56 PM PDT 24
Peak memory 216264 kb
Host smart-b4a3b33e-2df8-4fa4-a00c-8e69b51e52bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176894134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3176894134
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.530537187
Short name T269
Test name
Test status
Simulation time 9989579595 ps
CPU time 100.2 seconds
Started Jun 07 08:07:09 PM PDT 24
Finished Jun 07 08:08:52 PM PDT 24
Peak memory 217120 kb
Host smart-e4e52685-560e-4c8b-83cc-2339588ba831
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530537187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.530537187
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1204584422
Short name T66
Test name
Test status
Simulation time 6900722875 ps
CPU time 27.11 seconds
Started Jun 07 08:07:18 PM PDT 24
Finished Jun 07 08:07:46 PM PDT 24
Peak memory 217152 kb
Host smart-01a35260-c067-40f9-af8c-45cabf288abe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204584422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1204584422
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.319614142
Short name T42
Test name
Test status
Simulation time 165838727294 ps
CPU time 494.35 seconds
Started Jun 07 08:07:13 PM PDT 24
Finished Jun 07 08:15:30 PM PDT 24
Peak memory 226928 kb
Host smart-003682fd-0f03-4d61-83b4-eee297347269
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319614142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.319614142
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.760599506
Short name T28
Test name
Test status
Simulation time 10273047376 ps
CPU time 35.96 seconds
Started Jun 07 08:07:13 PM PDT 24
Finished Jun 07 08:07:52 PM PDT 24
Peak memory 219104 kb
Host smart-42aeb3c6-252f-4bbd-b8f4-4f77f178f8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760599506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.760599506
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2197365340
Short name T157
Test name
Test status
Simulation time 3318693870 ps
CPU time 28.24 seconds
Started Jun 07 08:07:13 PM PDT 24
Finished Jun 07 08:07:44 PM PDT 24
Peak memory 211100 kb
Host smart-187323a0-0445-4220-a032-797589b2e636
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2197365340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2197365340
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2061507021
Short name T223
Test name
Test status
Simulation time 9563049045 ps
CPU time 63.89 seconds
Started Jun 07 08:07:11 PM PDT 24
Finished Jun 07 08:08:18 PM PDT 24
Peak memory 216552 kb
Host smart-f6206e0c-8438-4c80-9dc4-85027663e23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061507021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2061507021
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3216784611
Short name T127
Test name
Test status
Simulation time 2019102940 ps
CPU time 26.94 seconds
Started Jun 07 08:07:11 PM PDT 24
Finished Jun 07 08:07:40 PM PDT 24
Peak memory 219024 kb
Host smart-f49ac638-ddf7-4e79-8e49-cc512abff8c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216784611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3216784611
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2953246485
Short name T173
Test name
Test status
Simulation time 6574216013 ps
CPU time 27.92 seconds
Started Jun 07 08:07:18 PM PDT 24
Finished Jun 07 08:07:48 PM PDT 24
Peak memory 217220 kb
Host smart-51956fe3-d867-4e1a-a4cf-0161b1dce9b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953246485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2953246485
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3595539601
Short name T253
Test name
Test status
Simulation time 338039558031 ps
CPU time 645.21 seconds
Started Jun 07 08:07:24 PM PDT 24
Finished Jun 07 08:18:11 PM PDT 24
Peak memory 215464 kb
Host smart-be96e94b-8ff4-4f41-b1be-5ffd6b03cdb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595539601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3595539601
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.807171752
Short name T350
Test name
Test status
Simulation time 14435414275 ps
CPU time 65.39 seconds
Started Jun 07 08:07:17 PM PDT 24
Finished Jun 07 08:08:25 PM PDT 24
Peak memory 219068 kb
Host smart-c2416f77-31de-4fc6-9115-1435f4a8be7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807171752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.807171752
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3458617598
Short name T199
Test name
Test status
Simulation time 3241970610 ps
CPU time 27.59 seconds
Started Jun 07 08:07:18 PM PDT 24
Finished Jun 07 08:07:48 PM PDT 24
Peak memory 219140 kb
Host smart-6c6f2546-1161-486a-a365-1de5d7d3b311
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3458617598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3458617598
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2484071890
Short name T132
Test name
Test status
Simulation time 11600084031 ps
CPU time 60.9 seconds
Started Jun 07 08:07:19 PM PDT 24
Finished Jun 07 08:08:21 PM PDT 24
Peak memory 217584 kb
Host smart-5773f554-eea1-4663-b42e-6d89c2da9593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484071890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2484071890
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3490972702
Short name T151
Test name
Test status
Simulation time 10097291739 ps
CPU time 107.71 seconds
Started Jun 07 08:07:17 PM PDT 24
Finished Jun 07 08:09:06 PM PDT 24
Peak memory 219968 kb
Host smart-6ba9b56d-8b70-42a0-94a8-08837ce89719
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490972702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3490972702
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.4269503284
Short name T351
Test name
Test status
Simulation time 6233927848 ps
CPU time 18.68 seconds
Started Jun 07 08:07:23 PM PDT 24
Finished Jun 07 08:07:43 PM PDT 24
Peak memory 217128 kb
Host smart-d5b2571d-3ba7-4ced-9c0d-0da2cb63928a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269503284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.4269503284
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1275302241
Short name T226
Test name
Test status
Simulation time 2444204143 ps
CPU time 24.17 seconds
Started Jun 07 08:07:18 PM PDT 24
Finished Jun 07 08:07:44 PM PDT 24
Peak memory 218356 kb
Host smart-41c17983-d702-44dd-b5c7-b787f7210f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275302241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1275302241
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1237082805
Short name T146
Test name
Test status
Simulation time 3092926500 ps
CPU time 15.83 seconds
Started Jun 07 08:07:17 PM PDT 24
Finished Jun 07 08:07:35 PM PDT 24
Peak memory 219148 kb
Host smart-f0d08a8f-c125-4309-8dce-1cea7500d270
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1237082805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1237082805
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.4133624152
Short name T296
Test name
Test status
Simulation time 4919666451 ps
CPU time 49.14 seconds
Started Jun 07 08:07:18 PM PDT 24
Finished Jun 07 08:08:09 PM PDT 24
Peak memory 217344 kb
Host smart-69031b66-74db-4221-b60e-20ebcd506eb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133624152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.4133624152
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2088334851
Short name T95
Test name
Test status
Simulation time 6031611709 ps
CPU time 18.32 seconds
Started Jun 07 08:06:49 PM PDT 24
Finished Jun 07 08:07:10 PM PDT 24
Peak memory 217096 kb
Host smart-c106ec3e-1406-4523-92b1-935f701ba84f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088334851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2088334851
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.918294930
Short name T327
Test name
Test status
Simulation time 8214047860 ps
CPU time 216.06 seconds
Started Jun 07 08:06:48 PM PDT 24
Finished Jun 07 08:10:27 PM PDT 24
Peak memory 219356 kb
Host smart-a67350c6-02d1-4ac1-ba92-794d54325a3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918294930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.918294930
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4253823841
Short name T231
Test name
Test status
Simulation time 3142149425 ps
CPU time 38.78 seconds
Started Jun 07 08:06:50 PM PDT 24
Finished Jun 07 08:07:31 PM PDT 24
Peak memory 219060 kb
Host smart-fe3617ac-f0d8-473a-85bd-944ec8ebeb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253823841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.4253823841
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2993793804
Short name T141
Test name
Test status
Simulation time 7216150571 ps
CPU time 27.61 seconds
Started Jun 07 08:06:52 PM PDT 24
Finished Jun 07 08:07:22 PM PDT 24
Peak memory 219172 kb
Host smart-014f02fd-362c-46fd-991c-4ffcb81e9a93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2993793804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2993793804
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.809648229
Short name T22
Test name
Test status
Simulation time 2544980542 ps
CPU time 240.97 seconds
Started Jun 07 08:06:50 PM PDT 24
Finished Jun 07 08:10:53 PM PDT 24
Peak memory 235488 kb
Host smart-039bfe98-8a9e-4195-ac18-b8cc88f1a27f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809648229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.809648229
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3225437666
Short name T204
Test name
Test status
Simulation time 2662190749 ps
CPU time 42.62 seconds
Started Jun 07 08:06:52 PM PDT 24
Finished Jun 07 08:07:36 PM PDT 24
Peak memory 214828 kb
Host smart-8b7c39ff-8e0f-478c-b614-6fb96100ecff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225437666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3225437666
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2335997648
Short name T311
Test name
Test status
Simulation time 15428955058 ps
CPU time 156.99 seconds
Started Jun 07 08:06:48 PM PDT 24
Finished Jun 07 08:09:28 PM PDT 24
Peak memory 219764 kb
Host smart-00cc1a7e-bb41-4f1f-8203-f20f80d50cce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335997648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2335997648
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2577338472
Short name T325
Test name
Test status
Simulation time 635038445 ps
CPU time 8.52 seconds
Started Jun 07 08:07:25 PM PDT 24
Finished Jun 07 08:07:35 PM PDT 24
Peak memory 216704 kb
Host smart-1a5c99e2-900f-478b-8504-6cf61145e67f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577338472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2577338472
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.200159781
Short name T288
Test name
Test status
Simulation time 115363014695 ps
CPU time 417.07 seconds
Started Jun 07 08:07:25 PM PDT 24
Finished Jun 07 08:14:23 PM PDT 24
Peak memory 238316 kb
Host smart-6420d39c-9f22-4f8c-b1a9-fa091a00b4c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200159781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.200159781
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2195671426
Short name T280
Test name
Test status
Simulation time 43640177983 ps
CPU time 60.99 seconds
Started Jun 07 08:07:25 PM PDT 24
Finished Jun 07 08:08:28 PM PDT 24
Peak memory 218908 kb
Host smart-9537154e-880a-422f-834a-e34e95ef47d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195671426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2195671426
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1670330756
Short name T170
Test name
Test status
Simulation time 11981228964 ps
CPU time 23.03 seconds
Started Jun 07 08:07:19 PM PDT 24
Finished Jun 07 08:07:44 PM PDT 24
Peak memory 219228 kb
Host smart-d40710d0-048a-4a5d-9e1f-aac49db9362b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1670330756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1670330756
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.921780008
Short name T177
Test name
Test status
Simulation time 30533320866 ps
CPU time 62.03 seconds
Started Jun 07 08:07:17 PM PDT 24
Finished Jun 07 08:08:21 PM PDT 24
Peak memory 217988 kb
Host smart-4dd012fb-a1b8-4662-b2ab-8d39f45b122b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921780008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.921780008
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3414340102
Short name T333
Test name
Test status
Simulation time 2685455243 ps
CPU time 43.99 seconds
Started Jun 07 08:07:20 PM PDT 24
Finished Jun 07 08:08:05 PM PDT 24
Peak memory 219064 kb
Host smart-4c6d49fd-3634-4d01-a8a2-7f2f12e5cc5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414340102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3414340102
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.367663436
Short name T68
Test name
Test status
Simulation time 76483526541 ps
CPU time 31.72 seconds
Started Jun 07 08:07:26 PM PDT 24
Finished Jun 07 08:08:00 PM PDT 24
Peak memory 217176 kb
Host smart-76bfde81-dfba-4e5c-8850-3342a36dd3da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367663436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.367663436
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1855069291
Short name T234
Test name
Test status
Simulation time 16955661329 ps
CPU time 214.2 seconds
Started Jun 07 08:07:26 PM PDT 24
Finished Jun 07 08:11:02 PM PDT 24
Peak memory 238712 kb
Host smart-2d43bda2-fb9d-4932-94c6-befd72ac43b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855069291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1855069291
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3954072543
Short name T287
Test name
Test status
Simulation time 3927887424 ps
CPU time 44.03 seconds
Started Jun 07 08:07:23 PM PDT 24
Finished Jun 07 08:08:09 PM PDT 24
Peak memory 218648 kb
Host smart-e5bb04eb-4a41-4d1c-a36a-cbbc1a50c7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954072543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3954072543
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.950317242
Short name T9
Test name
Test status
Simulation time 8263005301 ps
CPU time 23.7 seconds
Started Jun 07 08:07:27 PM PDT 24
Finished Jun 07 08:07:53 PM PDT 24
Peak memory 219060 kb
Host smart-3bed88cf-0b81-48c9-a4cd-ddb7912da870
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=950317242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.950317242
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.4065399623
Short name T265
Test name
Test status
Simulation time 10165493656 ps
CPU time 41.97 seconds
Started Jun 07 08:07:22 PM PDT 24
Finished Jun 07 08:08:06 PM PDT 24
Peak memory 216952 kb
Host smart-815b1be1-9a05-4150-99f1-ead183a69abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065399623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.4065399623
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3836053865
Short name T196
Test name
Test status
Simulation time 1116075174 ps
CPU time 10.75 seconds
Started Jun 07 08:07:24 PM PDT 24
Finished Jun 07 08:07:36 PM PDT 24
Peak memory 218028 kb
Host smart-856759f2-e998-40c1-8b11-b3dc8ad81cf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836053865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3836053865
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3571673543
Short name T167
Test name
Test status
Simulation time 4402363229 ps
CPU time 25.93 seconds
Started Jun 07 08:07:24 PM PDT 24
Finished Jun 07 08:07:52 PM PDT 24
Peak memory 217296 kb
Host smart-f1bf29fd-bd30-4134-b7e3-e66b0da4aae6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571673543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3571673543
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4076669384
Short name T171
Test name
Test status
Simulation time 17175324055 ps
CPU time 385.39 seconds
Started Jun 07 08:07:25 PM PDT 24
Finished Jun 07 08:13:52 PM PDT 24
Peak memory 234796 kb
Host smart-6cb642a3-f3fd-4371-bbb0-73c48514e7dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076669384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.4076669384
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3901269479
Short name T205
Test name
Test status
Simulation time 1323395706 ps
CPU time 19.27 seconds
Started Jun 07 08:07:25 PM PDT 24
Finished Jun 07 08:07:46 PM PDT 24
Peak memory 219008 kb
Host smart-514b557b-991c-4ccb-be77-f56663985822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901269479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3901269479
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1064315673
Short name T148
Test name
Test status
Simulation time 81884513628 ps
CPU time 37.61 seconds
Started Jun 07 08:07:23 PM PDT 24
Finished Jun 07 08:08:02 PM PDT 24
Peak memory 219148 kb
Host smart-3e8f8cd6-20be-447b-ba97-e10923a836e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1064315673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1064315673
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2464420515
Short name T294
Test name
Test status
Simulation time 2712416333 ps
CPU time 31.92 seconds
Started Jun 07 08:07:24 PM PDT 24
Finished Jun 07 08:07:57 PM PDT 24
Peak memory 215224 kb
Host smart-269636ff-931e-463f-bed9-e45ca3a28a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464420515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2464420515
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.67644634
Short name T340
Test name
Test status
Simulation time 3053638797 ps
CPU time 41.53 seconds
Started Jun 07 08:07:24 PM PDT 24
Finished Jun 07 08:08:07 PM PDT 24
Peak memory 217416 kb
Host smart-d9974f04-d3bf-43d1-96b1-7c888d879c4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67644634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 22.rom_ctrl_stress_all.67644634
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.948569334
Short name T190
Test name
Test status
Simulation time 505297548 ps
CPU time 11.88 seconds
Started Jun 07 08:07:26 PM PDT 24
Finished Jun 07 08:07:39 PM PDT 24
Peak memory 216224 kb
Host smart-ffb30de2-e187-408c-a476-8da373448eaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948569334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.948569334
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2855240897
Short name T35
Test name
Test status
Simulation time 336830086514 ps
CPU time 749.44 seconds
Started Jun 07 08:07:27 PM PDT 24
Finished Jun 07 08:19:59 PM PDT 24
Peak memory 238172 kb
Host smart-735c4604-d9dc-432e-8692-7b6e968d30be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855240897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2855240897
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3370135124
Short name T166
Test name
Test status
Simulation time 96313665840 ps
CPU time 65.26 seconds
Started Jun 07 08:07:26 PM PDT 24
Finished Jun 07 08:08:33 PM PDT 24
Peak memory 219080 kb
Host smart-d48fa2f3-9469-4f44-b9d1-ec20d41e03c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370135124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3370135124
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.199036205
Short name T220
Test name
Test status
Simulation time 3284601558 ps
CPU time 28.81 seconds
Started Jun 07 08:07:26 PM PDT 24
Finished Jun 07 08:07:57 PM PDT 24
Peak memory 219144 kb
Host smart-590098b7-784f-4cbb-83b5-9f7604afd721
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=199036205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.199036205
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3225878194
Short name T299
Test name
Test status
Simulation time 6248000392 ps
CPU time 55.46 seconds
Started Jun 07 08:07:22 PM PDT 24
Finished Jun 07 08:08:19 PM PDT 24
Peak memory 216852 kb
Host smart-e37e465c-4277-41f9-a207-7c9b5b42d707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225878194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3225878194
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.4085790577
Short name T189
Test name
Test status
Simulation time 4296975780 ps
CPU time 35.06 seconds
Started Jun 07 08:07:25 PM PDT 24
Finished Jun 07 08:08:02 PM PDT 24
Peak memory 216884 kb
Host smart-5e035fe3-7106-4372-a3a5-4f59fb7a6ebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085790577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.4085790577
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.895733544
Short name T210
Test name
Test status
Simulation time 228221234028 ps
CPU time 583.49 seconds
Started Jun 07 08:07:25 PM PDT 24
Finished Jun 07 08:17:10 PM PDT 24
Peak memory 237736 kb
Host smart-66428729-d09a-4f3c-b162-44ceea9a2847
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895733544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.895733544
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3824749763
Short name T267
Test name
Test status
Simulation time 10706177421 ps
CPU time 34.06 seconds
Started Jun 07 08:07:26 PM PDT 24
Finished Jun 07 08:08:01 PM PDT 24
Peak memory 219132 kb
Host smart-95830bfa-37f3-4aa9-b48d-1573210f8889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824749763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3824749763
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.255499614
Short name T111
Test name
Test status
Simulation time 5686941862 ps
CPU time 24.83 seconds
Started Jun 07 08:07:27 PM PDT 24
Finished Jun 07 08:07:53 PM PDT 24
Peak memory 219180 kb
Host smart-034ab914-a1d6-43c9-8497-4305dd6fb1e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=255499614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.255499614
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.568615307
Short name T16
Test name
Test status
Simulation time 36436575195 ps
CPU time 64.99 seconds
Started Jun 07 08:07:29 PM PDT 24
Finished Jun 07 08:08:36 PM PDT 24
Peak memory 215944 kb
Host smart-96d87788-e728-4a67-8ea6-01c2bcabc9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568615307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.568615307
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1245987933
Short name T320
Test name
Test status
Simulation time 15980592681 ps
CPU time 91.1 seconds
Started Jun 07 08:07:27 PM PDT 24
Finished Jun 07 08:09:00 PM PDT 24
Peak memory 217812 kb
Host smart-ebd77263-355f-43a1-bbe1-8c870b4b8bf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245987933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1245987933
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2723040581
Short name T208
Test name
Test status
Simulation time 2480120188 ps
CPU time 22.62 seconds
Started Jun 07 08:07:31 PM PDT 24
Finished Jun 07 08:07:57 PM PDT 24
Peak memory 216936 kb
Host smart-a03c8870-81c3-4c93-9dea-a159e2d8e8e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723040581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2723040581
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.358391637
Short name T40
Test name
Test status
Simulation time 1376274233 ps
CPU time 19.57 seconds
Started Jun 07 08:07:31 PM PDT 24
Finished Jun 07 08:07:54 PM PDT 24
Peak memory 218972 kb
Host smart-1aee04f0-2017-4a7b-99b0-9db58ea226bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358391637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.358391637
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1108504195
Short name T110
Test name
Test status
Simulation time 643691697 ps
CPU time 10.61 seconds
Started Jun 07 08:07:31 PM PDT 24
Finished Jun 07 08:07:45 PM PDT 24
Peak memory 219076 kb
Host smart-f711376d-7289-45fc-bb74-ee4095fd6ead
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1108504195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1108504195
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2408044340
Short name T162
Test name
Test status
Simulation time 4754128479 ps
CPU time 50.25 seconds
Started Jun 07 08:07:32 PM PDT 24
Finished Jun 07 08:08:27 PM PDT 24
Peak memory 217472 kb
Host smart-3149839d-f87f-49c1-9a45-6923621e8314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408044340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2408044340
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.4139004135
Short name T233
Test name
Test status
Simulation time 2325376960 ps
CPU time 47.04 seconds
Started Jun 07 08:07:30 PM PDT 24
Finished Jun 07 08:08:20 PM PDT 24
Peak memory 219080 kb
Host smart-8deeb1f6-3228-4d49-adc2-43d43c2632a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139004135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.4139004135
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3786017799
Short name T96
Test name
Test status
Simulation time 14716253005 ps
CPU time 23.3 seconds
Started Jun 07 08:07:32 PM PDT 24
Finished Jun 07 08:07:59 PM PDT 24
Peak memory 217272 kb
Host smart-aa2a0caa-8fca-4657-8914-889085d48cf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786017799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3786017799
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.572068470
Short name T341
Test name
Test status
Simulation time 39195761113 ps
CPU time 423.83 seconds
Started Jun 07 08:07:32 PM PDT 24
Finished Jun 07 08:14:40 PM PDT 24
Peak memory 233084 kb
Host smart-25e6f37d-f4c6-4fbd-8184-700810e2f52f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572068470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.572068470
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.174369122
Short name T136
Test name
Test status
Simulation time 7017811027 ps
CPU time 41.05 seconds
Started Jun 07 08:07:30 PM PDT 24
Finished Jun 07 08:08:13 PM PDT 24
Peak memory 219124 kb
Host smart-ee740bbb-bd89-4b06-a50e-1ac551dc3837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174369122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.174369122
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.430013960
Short name T125
Test name
Test status
Simulation time 15537829264 ps
CPU time 27.59 seconds
Started Jun 07 08:07:34 PM PDT 24
Finished Jun 07 08:08:05 PM PDT 24
Peak memory 219200 kb
Host smart-9e8c0656-814b-4f46-a7e5-940b5f2d1d9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=430013960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.430013960
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2771944287
Short name T52
Test name
Test status
Simulation time 4125318261 ps
CPU time 45.58 seconds
Started Jun 07 08:07:31 PM PDT 24
Finished Jun 07 08:08:20 PM PDT 24
Peak memory 216088 kb
Host smart-c29b0117-6a29-4df4-b737-39cae040bd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771944287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2771944287
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.637463944
Short name T313
Test name
Test status
Simulation time 1386888568 ps
CPU time 21.56 seconds
Started Jun 07 08:07:30 PM PDT 24
Finished Jun 07 08:07:54 PM PDT 24
Peak memory 218892 kb
Host smart-b11a4088-a92d-4072-9f40-22fb36322539
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637463944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.637463944
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3880089959
Short name T271
Test name
Test status
Simulation time 688392093 ps
CPU time 8.56 seconds
Started Jun 07 08:07:31 PM PDT 24
Finished Jun 07 08:07:44 PM PDT 24
Peak memory 216620 kb
Host smart-72e31a72-ae0f-4dd4-b1d8-58847fb7d8ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880089959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3880089959
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.830493996
Short name T309
Test name
Test status
Simulation time 9443930684 ps
CPU time 160.2 seconds
Started Jun 07 08:07:32 PM PDT 24
Finished Jun 07 08:10:16 PM PDT 24
Peak memory 219244 kb
Host smart-779ca3d3-19ae-43e5-b629-e74487f3254b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830493996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.830493996
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.4241898216
Short name T304
Test name
Test status
Simulation time 28735693252 ps
CPU time 60.03 seconds
Started Jun 07 08:07:33 PM PDT 24
Finished Jun 07 08:08:37 PM PDT 24
Peak memory 218888 kb
Host smart-e793b1ea-2f71-48a1-870f-c8f206118693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241898216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.4241898216
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.4199742517
Short name T147
Test name
Test status
Simulation time 831055512 ps
CPU time 10.31 seconds
Started Jun 07 08:07:32 PM PDT 24
Finished Jun 07 08:07:46 PM PDT 24
Peak memory 219000 kb
Host smart-47b6015f-a3ac-4b67-b79d-c5e9ed117fb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4199742517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.4199742517
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1089075198
Short name T268
Test name
Test status
Simulation time 6463917132 ps
CPU time 88.53 seconds
Started Jun 07 08:07:33 PM PDT 24
Finished Jun 07 08:09:06 PM PDT 24
Peak memory 227148 kb
Host smart-e3e57912-e247-483e-bd17-30bb51d7c00c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089075198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1089075198
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.4264714853
Short name T161
Test name
Test status
Simulation time 3677450422 ps
CPU time 29.4 seconds
Started Jun 07 08:07:38 PM PDT 24
Finished Jun 07 08:08:12 PM PDT 24
Peak memory 216904 kb
Host smart-d9a789a0-d4f3-4bf9-be81-a29db3f19bc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264714853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.4264714853
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1066471101
Short name T203
Test name
Test status
Simulation time 75116631052 ps
CPU time 663.03 seconds
Started Jun 07 08:07:31 PM PDT 24
Finished Jun 07 08:18:38 PM PDT 24
Peak memory 239044 kb
Host smart-389372f6-78ef-4532-a998-b0f398690569
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066471101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1066471101
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1633245912
Short name T322
Test name
Test status
Simulation time 2347276267 ps
CPU time 28 seconds
Started Jun 07 08:07:35 PM PDT 24
Finished Jun 07 08:08:06 PM PDT 24
Peak memory 215252 kb
Host smart-fc7feae9-9cae-4c06-ad1e-a6c2a313daad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633245912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1633245912
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1365386601
Short name T300
Test name
Test status
Simulation time 3881664221 ps
CPU time 22.5 seconds
Started Jun 07 08:07:32 PM PDT 24
Finished Jun 07 08:07:59 PM PDT 24
Peak memory 219112 kb
Host smart-c0724c85-6977-48a9-a0b1-572a4cc48d39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1365386601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1365386601
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2014970878
Short name T6
Test name
Test status
Simulation time 5238983506 ps
CPU time 56.14 seconds
Started Jun 07 08:07:30 PM PDT 24
Finished Jun 07 08:08:29 PM PDT 24
Peak memory 216456 kb
Host smart-63ed918c-3650-47d0-8755-ac5b936d0fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014970878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2014970878
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1498672866
Short name T255
Test name
Test status
Simulation time 11789487745 ps
CPU time 126.74 seconds
Started Jun 07 08:07:31 PM PDT 24
Finished Jun 07 08:09:40 PM PDT 24
Peak memory 219156 kb
Host smart-a357dc96-eb36-443c-8ec2-37fda070b744
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498672866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1498672866
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2137195224
Short name T347
Test name
Test status
Simulation time 1946081739 ps
CPU time 19.55 seconds
Started Jun 07 08:07:40 PM PDT 24
Finished Jun 07 08:08:05 PM PDT 24
Peak memory 216844 kb
Host smart-908213db-2b17-428b-b4b5-7bae9005caba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137195224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2137195224
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1156827776
Short name T212
Test name
Test status
Simulation time 65791336319 ps
CPU time 260.1 seconds
Started Jun 07 08:07:40 PM PDT 24
Finished Jun 07 08:12:05 PM PDT 24
Peak memory 233500 kb
Host smart-86a8f3e1-6fcf-42c4-98de-cffda3763d8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156827776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1156827776
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3967266143
Short name T348
Test name
Test status
Simulation time 14560752729 ps
CPU time 42.4 seconds
Started Jun 07 08:07:37 PM PDT 24
Finished Jun 07 08:08:23 PM PDT 24
Peak memory 219132 kb
Host smart-09e8f1d6-9529-467f-bb0a-2389de98d330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967266143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3967266143
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2385053690
Short name T326
Test name
Test status
Simulation time 368517683 ps
CPU time 10.71 seconds
Started Jun 07 08:07:40 PM PDT 24
Finished Jun 07 08:07:56 PM PDT 24
Peak memory 219120 kb
Host smart-4637b69d-f26b-464a-b9c7-f1a2998c572f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2385053690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2385053690
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2853961226
Short name T193
Test name
Test status
Simulation time 38847341748 ps
CPU time 55.02 seconds
Started Jun 07 08:07:38 PM PDT 24
Finished Jun 07 08:08:36 PM PDT 24
Peak memory 217412 kb
Host smart-b12b713c-06ba-4fa4-9268-c288d7a2c24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853961226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2853961226
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.379107331
Short name T281
Test name
Test status
Simulation time 2982089381 ps
CPU time 33.64 seconds
Started Jun 07 08:07:41 PM PDT 24
Finished Jun 07 08:08:19 PM PDT 24
Peak memory 219060 kb
Host smart-53804161-8e59-43cd-a8ea-99b5be8b398f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379107331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.379107331
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3674020078
Short name T164
Test name
Test status
Simulation time 2748519849 ps
CPU time 16.07 seconds
Started Jun 07 08:06:49 PM PDT 24
Finished Jun 07 08:07:08 PM PDT 24
Peak memory 216948 kb
Host smart-96e071fe-ed5c-4662-b9a8-82e3ce531ccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674020078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3674020078
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.618955559
Short name T34
Test name
Test status
Simulation time 7531260878 ps
CPU time 241.91 seconds
Started Jun 07 08:06:48 PM PDT 24
Finished Jun 07 08:10:52 PM PDT 24
Peak memory 230308 kb
Host smart-ae11c457-0769-4758-b88a-7b78e69327b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618955559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.618955559
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2460711014
Short name T57
Test name
Test status
Simulation time 5923376697 ps
CPU time 39.27 seconds
Started Jun 07 08:06:49 PM PDT 24
Finished Jun 07 08:07:31 PM PDT 24
Peak memory 219104 kb
Host smart-fd623ce8-f2de-4f05-b090-c6f839bb2021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460711014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2460711014
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4058378291
Short name T286
Test name
Test status
Simulation time 14650765207 ps
CPU time 30.24 seconds
Started Jun 07 08:06:49 PM PDT 24
Finished Jun 07 08:07:22 PM PDT 24
Peak memory 219200 kb
Host smart-35b9ed9c-0f59-4726-8272-666e31e4892f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4058378291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.4058378291
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.931141019
Short name T31
Test name
Test status
Simulation time 297900002 ps
CPU time 118.35 seconds
Started Jun 07 08:06:48 PM PDT 24
Finished Jun 07 08:08:49 PM PDT 24
Peak memory 234684 kb
Host smart-cc0098b0-8be5-4785-991b-6b1897f4b998
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931141019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.931141019
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2274759141
Short name T61
Test name
Test status
Simulation time 1060851016 ps
CPU time 23.46 seconds
Started Jun 07 08:06:49 PM PDT 24
Finished Jun 07 08:07:15 PM PDT 24
Peak memory 215756 kb
Host smart-5b981569-553d-4563-b1e2-715bf6c84b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274759141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2274759141
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2280633866
Short name T339
Test name
Test status
Simulation time 20542365837 ps
CPU time 46.25 seconds
Started Jun 07 08:06:48 PM PDT 24
Finished Jun 07 08:07:37 PM PDT 24
Peak memory 217372 kb
Host smart-69914f0d-7824-4a33-aec3-97f489a72f1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280633866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2280633866
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2655302834
Short name T12
Test name
Test status
Simulation time 99800947171 ps
CPU time 1032.55 seconds
Started Jun 07 08:06:49 PM PDT 24
Finished Jun 07 08:24:04 PM PDT 24
Peak memory 237800 kb
Host smart-636294dd-36ce-46f0-93c4-8dfe62bf5fde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655302834 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.2655302834
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2108015891
Short name T221
Test name
Test status
Simulation time 198863962941 ps
CPU time 475.18 seconds
Started Jun 07 08:07:38 PM PDT 24
Finished Jun 07 08:15:37 PM PDT 24
Peak memory 227532 kb
Host smart-23b948d1-9ad2-4b68-b4ee-671dd3a55da3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108015891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2108015891
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2554104148
Short name T137
Test name
Test status
Simulation time 13545441589 ps
CPU time 43.91 seconds
Started Jun 07 08:07:40 PM PDT 24
Finished Jun 07 08:08:29 PM PDT 24
Peak memory 219052 kb
Host smart-dd2f69f6-99e8-4f33-8828-721bd83d699a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554104148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2554104148
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3589673689
Short name T301
Test name
Test status
Simulation time 4347198661 ps
CPU time 28.53 seconds
Started Jun 07 08:07:41 PM PDT 24
Finished Jun 07 08:08:15 PM PDT 24
Peak memory 219176 kb
Host smart-88fbc1c0-4d92-4e55-a75d-435f1a3d0b4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3589673689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3589673689
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2072575176
Short name T128
Test name
Test status
Simulation time 26961755188 ps
CPU time 57.86 seconds
Started Jun 07 08:07:39 PM PDT 24
Finished Jun 07 08:08:41 PM PDT 24
Peak memory 216256 kb
Host smart-5b294ed5-095a-4e9f-90aa-f42c181a99f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072575176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2072575176
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3243643122
Short name T248
Test name
Test status
Simulation time 3450670498 ps
CPU time 40.34 seconds
Started Jun 07 08:07:39 PM PDT 24
Finished Jun 07 08:08:24 PM PDT 24
Peak memory 219048 kb
Host smart-7c2b722d-294b-48a9-b5c3-46da372e0961
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243643122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3243643122
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2555755263
Short name T334
Test name
Test status
Simulation time 172555060 ps
CPU time 8.57 seconds
Started Jun 07 08:07:39 PM PDT 24
Finished Jun 07 08:07:53 PM PDT 24
Peak memory 216672 kb
Host smart-670d77d4-7592-4072-9c27-64c223d5eb2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555755263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2555755263
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2901785549
Short name T266
Test name
Test status
Simulation time 1193375647 ps
CPU time 125.1 seconds
Started Jun 07 08:07:39 PM PDT 24
Finished Jun 07 08:09:49 PM PDT 24
Peak memory 227612 kb
Host smart-6ded44bf-f37d-4851-b927-cf4844465253
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901785549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2901785549
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3672383849
Short name T307
Test name
Test status
Simulation time 1833163184 ps
CPU time 19.7 seconds
Started Jun 07 08:07:39 PM PDT 24
Finished Jun 07 08:08:04 PM PDT 24
Peak memory 218996 kb
Host smart-1623803c-7aac-4aab-b72a-024c001f8388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672383849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3672383849
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1687132386
Short name T54
Test name
Test status
Simulation time 17130294581 ps
CPU time 35.25 seconds
Started Jun 07 08:07:39 PM PDT 24
Finished Jun 07 08:08:20 PM PDT 24
Peak memory 219192 kb
Host smart-fb110c72-0095-40d1-9c9b-3835767cd5a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1687132386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1687132386
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.287367978
Short name T257
Test name
Test status
Simulation time 1211943498 ps
CPU time 20.83 seconds
Started Jun 07 08:07:38 PM PDT 24
Finished Jun 07 08:08:03 PM PDT 24
Peak memory 216600 kb
Host smart-39652365-eb66-4bda-9361-1da14a833724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287367978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.287367978
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2358133068
Short name T293
Test name
Test status
Simulation time 13337492529 ps
CPU time 33.89 seconds
Started Jun 07 08:07:38 PM PDT 24
Finished Jun 07 08:08:17 PM PDT 24
Peak memory 213180 kb
Host smart-7158816f-8eac-4176-a0fa-bc207fb317c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358133068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2358133068
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2249414277
Short name T56
Test name
Test status
Simulation time 7718337837 ps
CPU time 31.78 seconds
Started Jun 07 08:07:47 PM PDT 24
Finished Jun 07 08:08:24 PM PDT 24
Peak memory 217152 kb
Host smart-0e9b2efa-6273-42ea-aead-1adfe10e6df5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249414277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2249414277
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1569670435
Short name T324
Test name
Test status
Simulation time 22719063183 ps
CPU time 295.1 seconds
Started Jun 07 08:07:39 PM PDT 24
Finished Jun 07 08:12:39 PM PDT 24
Peak memory 238932 kb
Host smart-ca9ce9bb-b92e-45e5-8575-7780697af7d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569670435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1569670435
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.385810386
Short name T338
Test name
Test status
Simulation time 4801851625 ps
CPU time 27.89 seconds
Started Jun 07 08:07:45 PM PDT 24
Finished Jun 07 08:08:18 PM PDT 24
Peak memory 219036 kb
Host smart-a28f9f57-2f92-4907-b5fc-c823bd4f1e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385810386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.385810386
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2566444360
Short name T215
Test name
Test status
Simulation time 184478002 ps
CPU time 10.67 seconds
Started Jun 07 08:07:42 PM PDT 24
Finished Jun 07 08:07:57 PM PDT 24
Peak memory 219076 kb
Host smart-ab02fb0b-7b49-49c4-9bc6-f4c1dacc8215
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2566444360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2566444360
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3698130926
Short name T249
Test name
Test status
Simulation time 17075344407 ps
CPU time 45.55 seconds
Started Jun 07 08:07:39 PM PDT 24
Finished Jun 07 08:08:30 PM PDT 24
Peak memory 216620 kb
Host smart-8e0cf2ae-e825-4a92-b5eb-bea382a4d89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698130926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3698130926
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3829019039
Short name T82
Test name
Test status
Simulation time 44908320988 ps
CPU time 105.49 seconds
Started Jun 07 08:07:40 PM PDT 24
Finished Jun 07 08:09:31 PM PDT 24
Peak memory 218780 kb
Host smart-7db7cf75-f297-4ce5-93bf-7d2a46bad0ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829019039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3829019039
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2232305263
Short name T135
Test name
Test status
Simulation time 8562355610 ps
CPU time 21.58 seconds
Started Jun 07 08:07:46 PM PDT 24
Finished Jun 07 08:08:12 PM PDT 24
Peak memory 216704 kb
Host smart-996e1b8c-6402-4b81-a8e5-cdaf2836096e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232305263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2232305263
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1453717932
Short name T246
Test name
Test status
Simulation time 6689568722 ps
CPU time 240.72 seconds
Started Jun 07 08:07:47 PM PDT 24
Finished Jun 07 08:11:53 PM PDT 24
Peak memory 217464 kb
Host smart-85e22d79-ed3e-4d0f-bc43-c355a9ce3baa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453717932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1453717932
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3958511883
Short name T272
Test name
Test status
Simulation time 346175214 ps
CPU time 19.23 seconds
Started Jun 07 08:07:47 PM PDT 24
Finished Jun 07 08:08:11 PM PDT 24
Peak memory 218900 kb
Host smart-478e0198-c591-4e81-9113-e3a58da1c9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958511883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3958511883
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.563521309
Short name T316
Test name
Test status
Simulation time 17826365416 ps
CPU time 29.64 seconds
Started Jun 07 08:07:45 PM PDT 24
Finished Jun 07 08:08:19 PM PDT 24
Peak memory 219196 kb
Host smart-28d39075-05f6-4fd0-9725-1bd790471827
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=563521309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.563521309
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1018073205
Short name T153
Test name
Test status
Simulation time 680747979 ps
CPU time 21.14 seconds
Started Jun 07 08:07:47 PM PDT 24
Finished Jun 07 08:08:13 PM PDT 24
Peak memory 215048 kb
Host smart-d1815d03-c140-427e-805c-b5f4d3977146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018073205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1018073205
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3942470635
Short name T160
Test name
Test status
Simulation time 19513722167 ps
CPU time 126.14 seconds
Started Jun 07 08:07:44 PM PDT 24
Finished Jun 07 08:09:55 PM PDT 24
Peak memory 219088 kb
Host smart-418f8be2-2f74-4d65-8ce0-25a12eaae90b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942470635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3942470635
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1075655039
Short name T213
Test name
Test status
Simulation time 1647912759 ps
CPU time 11.49 seconds
Started Jun 07 08:07:45 PM PDT 24
Finished Jun 07 08:08:01 PM PDT 24
Peak memory 216852 kb
Host smart-a3647385-f3c9-483a-90b2-8a9d6d3c13d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075655039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1075655039
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1738395896
Short name T244
Test name
Test status
Simulation time 60625946684 ps
CPU time 403.07 seconds
Started Jun 07 08:07:47 PM PDT 24
Finished Jun 07 08:14:34 PM PDT 24
Peak memory 237708 kb
Host smart-6c740e77-e5d8-4f16-b076-3047192e0465
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738395896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1738395896
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.974726536
Short name T357
Test name
Test status
Simulation time 4115543893 ps
CPU time 28.88 seconds
Started Jun 07 08:07:48 PM PDT 24
Finished Jun 07 08:08:22 PM PDT 24
Peak memory 215272 kb
Host smart-942a6bc0-44fe-4bf0-9240-941f0cec33b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974726536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.974726536
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.902702963
Short name T225
Test name
Test status
Simulation time 340681900 ps
CPU time 12.98 seconds
Started Jun 07 08:07:47 PM PDT 24
Finished Jun 07 08:08:05 PM PDT 24
Peak memory 218364 kb
Host smart-14afcbf5-e4ee-4508-addf-1cb4eeb55cc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=902702963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.902702963
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1690301589
Short name T228
Test name
Test status
Simulation time 5703859331 ps
CPU time 59.67 seconds
Started Jun 07 08:07:44 PM PDT 24
Finished Jun 07 08:08:48 PM PDT 24
Peak memory 216796 kb
Host smart-ec069b15-eed0-4307-9fc1-a05684fc64b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690301589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1690301589
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.4257431509
Short name T209
Test name
Test status
Simulation time 414193931 ps
CPU time 25.15 seconds
Started Jun 07 08:07:47 PM PDT 24
Finished Jun 07 08:08:17 PM PDT 24
Peak memory 218960 kb
Host smart-66b6eeea-6232-49b4-9eb2-db764813cfb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257431509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.4257431509
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3127224027
Short name T46
Test name
Test status
Simulation time 51089968720 ps
CPU time 1038.23 seconds
Started Jun 07 08:07:45 PM PDT 24
Finished Jun 07 08:25:09 PM PDT 24
Peak memory 231700 kb
Host smart-be4cad09-f61b-4849-b629-615eb6c1276e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127224027 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.3127224027
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.794831736
Short name T67
Test name
Test status
Simulation time 14456330390 ps
CPU time 21.23 seconds
Started Jun 07 08:07:46 PM PDT 24
Finished Jun 07 08:08:12 PM PDT 24
Peak memory 217200 kb
Host smart-8200477b-649d-49cc-ac21-1599ea1d0a77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794831736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.794831736
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.979892473
Short name T264
Test name
Test status
Simulation time 5984033162 ps
CPU time 188.35 seconds
Started Jun 07 08:07:45 PM PDT 24
Finished Jun 07 08:10:58 PM PDT 24
Peak memory 226416 kb
Host smart-163ab888-249b-4489-b1db-cf8a4f513c79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979892473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.979892473
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1475222386
Short name T27
Test name
Test status
Simulation time 5343663464 ps
CPU time 36.33 seconds
Started Jun 07 08:07:47 PM PDT 24
Finished Jun 07 08:08:28 PM PDT 24
Peak memory 219100 kb
Host smart-0bbb908d-27b2-40cd-a855-d91794d72a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475222386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1475222386
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4249682924
Short name T194
Test name
Test status
Simulation time 1513142580 ps
CPU time 20.87 seconds
Started Jun 07 08:07:47 PM PDT 24
Finished Jun 07 08:08:13 PM PDT 24
Peak memory 219056 kb
Host smart-ee857020-1ceb-460e-822a-6fef20baa52e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4249682924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4249682924
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.71836393
Short name T7
Test name
Test status
Simulation time 16415736327 ps
CPU time 48.46 seconds
Started Jun 07 08:07:45 PM PDT 24
Finished Jun 07 08:08:38 PM PDT 24
Peak memory 216280 kb
Host smart-06e0063c-207d-430c-b738-4d0512ad8d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71836393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.71836393
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1809237825
Short name T184
Test name
Test status
Simulation time 4106271272 ps
CPU time 37.3 seconds
Started Jun 07 08:07:45 PM PDT 24
Finished Jun 07 08:08:28 PM PDT 24
Peak memory 218940 kb
Host smart-d5233180-08e6-4c0b-a632-5f60dadb98f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809237825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1809237825
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3491133388
Short name T152
Test name
Test status
Simulation time 4129484011 ps
CPU time 32.65 seconds
Started Jun 07 08:07:47 PM PDT 24
Finished Jun 07 08:08:24 PM PDT 24
Peak memory 216900 kb
Host smart-046d03f3-d2f4-45eb-9d80-c005fb6df72f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491133388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3491133388
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.73181732
Short name T353
Test name
Test status
Simulation time 1589486319 ps
CPU time 127.08 seconds
Started Jun 07 08:07:47 PM PDT 24
Finished Jun 07 08:09:59 PM PDT 24
Peak memory 238204 kb
Host smart-d7bd4a3a-8bbc-49e4-a70f-f9f19d78cea5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73181732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_co
rrupt_sig_fatal_chk.73181732
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.438944955
Short name T318
Test name
Test status
Simulation time 32816742031 ps
CPU time 57 seconds
Started Jun 07 08:07:47 PM PDT 24
Finished Jun 07 08:08:49 PM PDT 24
Peak memory 219052 kb
Host smart-7283a3e5-5190-4e9a-bf45-39c7dd1645c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438944955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.438944955
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.662700463
Short name T239
Test name
Test status
Simulation time 5731783542 ps
CPU time 16.05 seconds
Started Jun 07 08:07:46 PM PDT 24
Finished Jun 07 08:08:07 PM PDT 24
Peak memory 219088 kb
Host smart-5d6f5773-b73f-4dd7-a97c-98fa096a0dac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=662700463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.662700463
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.4016228173
Short name T83
Test name
Test status
Simulation time 346871557 ps
CPU time 20.95 seconds
Started Jun 07 08:07:47 PM PDT 24
Finished Jun 07 08:08:13 PM PDT 24
Peak memory 216348 kb
Host smart-f567f9be-de65-44fa-a496-04a6d0c29dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016228173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.4016228173
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1323690222
Short name T236
Test name
Test status
Simulation time 15342094914 ps
CPU time 60.88 seconds
Started Jun 07 08:07:47 PM PDT 24
Finished Jun 07 08:08:53 PM PDT 24
Peak memory 219212 kb
Host smart-7a42b160-6650-46e2-a799-383a6c5282dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323690222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1323690222
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1784736578
Short name T276
Test name
Test status
Simulation time 10185569807 ps
CPU time 24.52 seconds
Started Jun 07 08:07:49 PM PDT 24
Finished Jun 07 08:08:18 PM PDT 24
Peak memory 217280 kb
Host smart-e250dfe2-eac2-4384-b2c4-61399a279585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784736578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1784736578
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3468895174
Short name T263
Test name
Test status
Simulation time 130864672849 ps
CPU time 502.16 seconds
Started Jun 07 08:07:46 PM PDT 24
Finished Jun 07 08:16:14 PM PDT 24
Peak memory 241756 kb
Host smart-3c18364a-9159-4990-bfdc-cd589354ba4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468895174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3468895174
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2479396338
Short name T216
Test name
Test status
Simulation time 9978018913 ps
CPU time 24.68 seconds
Started Jun 07 08:07:48 PM PDT 24
Finished Jun 07 08:08:18 PM PDT 24
Peak memory 219104 kb
Host smart-14e93023-6ffd-4c8a-9475-aecd0158ddeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2479396338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2479396338
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1121679977
Short name T218
Test name
Test status
Simulation time 14537004145 ps
CPU time 30.72 seconds
Started Jun 07 08:07:47 PM PDT 24
Finished Jun 07 08:08:23 PM PDT 24
Peak memory 217312 kb
Host smart-03471e8c-b729-490d-ba28-66659e8b6e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121679977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1121679977
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3186470061
Short name T17
Test name
Test status
Simulation time 16912261533 ps
CPU time 153.43 seconds
Started Jun 07 08:07:46 PM PDT 24
Finished Jun 07 08:10:24 PM PDT 24
Peak memory 221332 kb
Host smart-a0b49b86-1016-4098-bfbf-1a6617afe096
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186470061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3186470061
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3811948453
Short name T232
Test name
Test status
Simulation time 7501201804 ps
CPU time 31.15 seconds
Started Jun 07 08:07:54 PM PDT 24
Finished Jun 07 08:08:29 PM PDT 24
Peak memory 217284 kb
Host smart-814061f4-b21b-476d-91ea-e9a3545cad90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811948453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3811948453
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.23582429
Short name T312
Test name
Test status
Simulation time 44339518661 ps
CPU time 397.01 seconds
Started Jun 07 08:07:56 PM PDT 24
Finished Jun 07 08:14:36 PM PDT 24
Peak memory 237636 kb
Host smart-2f3db565-887e-434f-a6a4-e0c595bb5837
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23582429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_co
rrupt_sig_fatal_chk.23582429
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3261852378
Short name T195
Test name
Test status
Simulation time 35315643226 ps
CPU time 47.89 seconds
Started Jun 07 08:07:56 PM PDT 24
Finished Jun 07 08:08:46 PM PDT 24
Peak memory 219084 kb
Host smart-b10142f5-6c27-48b0-ad7c-d4509660b5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261852378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3261852378
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1910059113
Short name T308
Test name
Test status
Simulation time 14897295043 ps
CPU time 24.84 seconds
Started Jun 07 08:07:57 PM PDT 24
Finished Jun 07 08:08:24 PM PDT 24
Peak memory 219176 kb
Host smart-8b02756d-6226-4d89-8e78-7b2c8e857229
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1910059113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1910059113
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1134877972
Short name T275
Test name
Test status
Simulation time 1384662232 ps
CPU time 20.73 seconds
Started Jun 07 08:07:48 PM PDT 24
Finished Jun 07 08:08:13 PM PDT 24
Peak memory 215368 kb
Host smart-822d8ab1-c0c4-4ae7-a4b9-ce3ea17f2d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134877972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1134877972
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1955270934
Short name T261
Test name
Test status
Simulation time 52947276012 ps
CPU time 140.04 seconds
Started Jun 07 08:07:48 PM PDT 24
Finished Jun 07 08:10:13 PM PDT 24
Peak memory 227292 kb
Host smart-de73a7d6-7b51-4481-8a09-6d8df6c3c2ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955270934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1955270934
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1969078009
Short name T250
Test name
Test status
Simulation time 1759483431 ps
CPU time 12.16 seconds
Started Jun 07 08:07:53 PM PDT 24
Finished Jun 07 08:08:08 PM PDT 24
Peak memory 216604 kb
Host smart-3d43a6c1-faa4-4cc2-a776-43633957ef9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969078009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1969078009
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1753293444
Short name T36
Test name
Test status
Simulation time 25426830889 ps
CPU time 550.95 seconds
Started Jun 07 08:07:57 PM PDT 24
Finished Jun 07 08:17:11 PM PDT 24
Peak memory 240128 kb
Host smart-5d6fcc81-fbd4-4244-871d-0c061213eafa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753293444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1753293444
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2424816263
Short name T277
Test name
Test status
Simulation time 117094086285 ps
CPU time 64.25 seconds
Started Jun 07 08:07:53 PM PDT 24
Finished Jun 07 08:09:00 PM PDT 24
Peak memory 219064 kb
Host smart-9e06fc17-57cc-45bd-8602-f68c3011bd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424816263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2424816263
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1838402224
Short name T284
Test name
Test status
Simulation time 1416209131 ps
CPU time 13.51 seconds
Started Jun 07 08:07:56 PM PDT 24
Finished Jun 07 08:08:12 PM PDT 24
Peak memory 218412 kb
Host smart-c307f599-5831-4663-a23f-eabfecb1df6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1838402224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1838402224
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1287078606
Short name T155
Test name
Test status
Simulation time 346530280 ps
CPU time 21.21 seconds
Started Jun 07 08:07:54 PM PDT 24
Finished Jun 07 08:08:18 PM PDT 24
Peak memory 216324 kb
Host smart-aec628b6-9f5e-42ce-8814-35e23c919099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287078606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1287078606
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2020846364
Short name T165
Test name
Test status
Simulation time 34167564408 ps
CPU time 71.47 seconds
Started Jun 07 08:07:53 PM PDT 24
Finished Jun 07 08:09:08 PM PDT 24
Peak memory 219140 kb
Host smart-78e34573-1377-4f8a-a60a-50ae652d5522
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020846364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2020846364
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2367331837
Short name T94
Test name
Test status
Simulation time 3836094721 ps
CPU time 27.25 seconds
Started Jun 07 08:06:49 PM PDT 24
Finished Jun 07 08:07:19 PM PDT 24
Peak memory 216900 kb
Host smart-362a6623-c740-485a-af7f-3f0561c1f95a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367331837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2367331837
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.4106743507
Short name T222
Test name
Test status
Simulation time 187520260804 ps
CPU time 608.35 seconds
Started Jun 07 08:06:50 PM PDT 24
Finished Jun 07 08:17:01 PM PDT 24
Peak memory 225096 kb
Host smart-81b024af-434a-4bd6-a36d-24ec1fc892e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106743507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.4106743507
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.777160526
Short name T354
Test name
Test status
Simulation time 8371367000 ps
CPU time 44.35 seconds
Started Jun 07 08:06:51 PM PDT 24
Finished Jun 07 08:07:37 PM PDT 24
Peak memory 219128 kb
Host smart-fd509b5b-9102-4e9d-8648-0c6749bc3c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777160526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.777160526
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2102279492
Short name T26
Test name
Test status
Simulation time 727948679 ps
CPU time 10.34 seconds
Started Jun 07 08:06:49 PM PDT 24
Finished Jun 07 08:07:01 PM PDT 24
Peak memory 219076 kb
Host smart-09ff9574-4abf-453a-af81-939931ede709
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2102279492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2102279492
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1217290514
Short name T175
Test name
Test status
Simulation time 11778566573 ps
CPU time 60.3 seconds
Started Jun 07 08:06:48 PM PDT 24
Finished Jun 07 08:07:51 PM PDT 24
Peak memory 216528 kb
Host smart-b8edac5e-65ff-4a14-9920-c8f1b7452970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217290514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1217290514
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1205490670
Short name T214
Test name
Test status
Simulation time 33104971658 ps
CPU time 100.44 seconds
Started Jun 07 08:06:50 PM PDT 24
Finished Jun 07 08:08:33 PM PDT 24
Peak memory 219112 kb
Host smart-1900c783-388b-4d6f-bf01-81b332a6758d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205490670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1205490670
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1278104059
Short name T229
Test name
Test status
Simulation time 14729440557 ps
CPU time 31.24 seconds
Started Jun 07 08:07:54 PM PDT 24
Finished Jun 07 08:08:28 PM PDT 24
Peak memory 217168 kb
Host smart-567d228a-663b-4808-a603-b64f71a37a7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278104059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1278104059
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1578411181
Short name T201
Test name
Test status
Simulation time 249845439215 ps
CPU time 523.04 seconds
Started Jun 07 08:07:53 PM PDT 24
Finished Jun 07 08:16:40 PM PDT 24
Peak memory 237520 kb
Host smart-71a75b84-6738-41ed-ab63-384b4698e53e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578411181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1578411181
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1235552262
Short name T238
Test name
Test status
Simulation time 2991748386 ps
CPU time 24.38 seconds
Started Jun 07 08:07:54 PM PDT 24
Finished Jun 07 08:08:21 PM PDT 24
Peak memory 218960 kb
Host smart-99514d18-785d-4257-8c06-4d483b85c34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235552262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1235552262
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.4277040319
Short name T154
Test name
Test status
Simulation time 4563511078 ps
CPU time 23.94 seconds
Started Jun 07 08:07:56 PM PDT 24
Finished Jun 07 08:08:23 PM PDT 24
Peak memory 219192 kb
Host smart-8c474496-2390-43c1-ba50-cc707c9f96db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4277040319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.4277040319
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.216613755
Short name T332
Test name
Test status
Simulation time 1717968426 ps
CPU time 20.48 seconds
Started Jun 07 08:07:55 PM PDT 24
Finished Jun 07 08:08:19 PM PDT 24
Peak memory 215948 kb
Host smart-527991e4-1e53-4a61-9c55-a5c39a949006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216613755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.216613755
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3397167689
Short name T179
Test name
Test status
Simulation time 5659763109 ps
CPU time 60.25 seconds
Started Jun 07 08:07:54 PM PDT 24
Finished Jun 07 08:08:58 PM PDT 24
Peak memory 217488 kb
Host smart-46e59908-f2a1-458b-8ac7-1a1fdcd6b2da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397167689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3397167689
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3547911865
Short name T176
Test name
Test status
Simulation time 7868317683 ps
CPU time 21.4 seconds
Started Jun 07 08:07:56 PM PDT 24
Finished Jun 07 08:08:20 PM PDT 24
Peak memory 217044 kb
Host smart-17982e1a-ac08-4d6c-a9f9-0c16060d6553
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547911865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3547911865
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3125169192
Short name T19
Test name
Test status
Simulation time 20598867092 ps
CPU time 382.94 seconds
Started Jun 07 08:07:54 PM PDT 24
Finished Jun 07 08:14:20 PM PDT 24
Peak memory 240648 kb
Host smart-3d76882c-e254-422c-b82a-02b33ceea4da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125169192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3125169192
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3780011883
Short name T346
Test name
Test status
Simulation time 689492178 ps
CPU time 19.31 seconds
Started Jun 07 08:07:56 PM PDT 24
Finished Jun 07 08:08:18 PM PDT 24
Peak memory 218980 kb
Host smart-f344f50b-3893-4c10-b8f4-0139f20f4a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780011883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3780011883
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3407457258
Short name T202
Test name
Test status
Simulation time 614048871 ps
CPU time 14.77 seconds
Started Jun 07 08:07:53 PM PDT 24
Finished Jun 07 08:08:11 PM PDT 24
Peak memory 219052 kb
Host smart-3528bffd-9d8d-4e59-b510-cd331b73e617
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3407457258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3407457258
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2530112319
Short name T97
Test name
Test status
Simulation time 362143588 ps
CPU time 20.91 seconds
Started Jun 07 08:07:53 PM PDT 24
Finished Jun 07 08:08:17 PM PDT 24
Peak memory 215916 kb
Host smart-00bc0aed-2739-41e5-84b6-25b42ad40ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530112319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2530112319
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.638346502
Short name T133
Test name
Test status
Simulation time 8392305056 ps
CPU time 99.12 seconds
Started Jun 07 08:07:57 PM PDT 24
Finished Jun 07 08:09:39 PM PDT 24
Peak memory 219968 kb
Host smart-d6923ec1-c119-44a4-9a33-06a87129ae34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638346502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.638346502
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4031228765
Short name T237
Test name
Test status
Simulation time 172741968 ps
CPU time 8.55 seconds
Started Jun 07 08:07:54 PM PDT 24
Finished Jun 07 08:08:06 PM PDT 24
Peak memory 216760 kb
Host smart-21c7dc91-49ee-41c1-bd83-5b8f9cf7991b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031228765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4031228765
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1603877717
Short name T305
Test name
Test status
Simulation time 71825802442 ps
CPU time 608.42 seconds
Started Jun 07 08:07:57 PM PDT 24
Finished Jun 07 08:18:08 PM PDT 24
Peak memory 225940 kb
Host smart-ea1896bb-9fde-473b-a57b-8904a8429137
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603877717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1603877717
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2271898487
Short name T139
Test name
Test status
Simulation time 21635585854 ps
CPU time 49.15 seconds
Started Jun 07 08:07:57 PM PDT 24
Finished Jun 07 08:08:49 PM PDT 24
Peak memory 219112 kb
Host smart-fa9a84f1-2631-4a69-901a-c797f30559ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271898487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2271898487
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2195095757
Short name T290
Test name
Test status
Simulation time 1434569882 ps
CPU time 14.28 seconds
Started Jun 07 08:07:56 PM PDT 24
Finished Jun 07 08:08:13 PM PDT 24
Peak memory 219044 kb
Host smart-17d0d470-9db3-46dc-a359-3be621d29f10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2195095757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2195095757
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2935923530
Short name T15
Test name
Test status
Simulation time 367743642 ps
CPU time 20.73 seconds
Started Jun 07 08:07:53 PM PDT 24
Finished Jun 07 08:08:17 PM PDT 24
Peak memory 215988 kb
Host smart-08641439-46ae-4bac-acf2-f1ca6bd91a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935923530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2935923530
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3971920758
Short name T337
Test name
Test status
Simulation time 2607937658 ps
CPU time 40.27 seconds
Started Jun 07 08:07:56 PM PDT 24
Finished Jun 07 08:08:39 PM PDT 24
Peak memory 219024 kb
Host smart-bf3f4505-d63e-42bc-b699-bae0ea82ed70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971920758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3971920758
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2632941027
Short name T45
Test name
Test status
Simulation time 74186718609 ps
CPU time 2771.73 seconds
Started Jun 07 08:07:54 PM PDT 24
Finished Jun 07 08:54:10 PM PDT 24
Peak memory 251812 kb
Host smart-56cfb003-d9f7-4f05-ae7c-c3edc2bab3ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632941027 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2632941027
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.4007728158
Short name T25
Test name
Test status
Simulation time 174631468 ps
CPU time 8.48 seconds
Started Jun 07 08:08:03 PM PDT 24
Finished Jun 07 08:08:15 PM PDT 24
Peak memory 216628 kb
Host smart-34591cf2-c8b5-4b72-8ecf-cd340415f177
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007728158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.4007728158
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3684726313
Short name T302
Test name
Test status
Simulation time 17218772812 ps
CPU time 342.94 seconds
Started Jun 07 08:07:55 PM PDT 24
Finished Jun 07 08:13:41 PM PDT 24
Peak memory 240192 kb
Host smart-9cb173c2-3b58-47b9-aeac-2fd9a3bb84ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684726313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3684726313
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4229217028
Short name T217
Test name
Test status
Simulation time 480338278 ps
CPU time 19.83 seconds
Started Jun 07 08:07:53 PM PDT 24
Finished Jun 07 08:08:16 PM PDT 24
Peak memory 218968 kb
Host smart-4905ef41-9a44-4531-aafc-94dc30cd4232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229217028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4229217028
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1799232899
Short name T291
Test name
Test status
Simulation time 1750534729 ps
CPU time 22.1 seconds
Started Jun 07 08:07:55 PM PDT 24
Finished Jun 07 08:08:20 PM PDT 24
Peak memory 219080 kb
Host smart-7720feeb-e843-491f-b89f-05fd07b4fd83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1799232899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1799232899
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2096854991
Short name T126
Test name
Test status
Simulation time 7832127997 ps
CPU time 53.67 seconds
Started Jun 07 08:07:54 PM PDT 24
Finished Jun 07 08:08:51 PM PDT 24
Peak memory 217252 kb
Host smart-5c497f96-82f0-423c-88af-0947885cb900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096854991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2096854991
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.930981515
Short name T131
Test name
Test status
Simulation time 9561516160 ps
CPU time 67.76 seconds
Started Jun 07 08:07:56 PM PDT 24
Finished Jun 07 08:09:07 PM PDT 24
Peak memory 219096 kb
Host smart-0b67df31-4896-45a6-97cb-c59c8c75db3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930981515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.930981515
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2297075833
Short name T43
Test name
Test status
Simulation time 10612839169 ps
CPU time 23.83 seconds
Started Jun 07 08:08:03 PM PDT 24
Finished Jun 07 08:08:30 PM PDT 24
Peak memory 217288 kb
Host smart-be4e68c7-b053-4d01-8835-d325a472ff41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297075833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2297075833
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3613511707
Short name T38
Test name
Test status
Simulation time 127415077244 ps
CPU time 630.29 seconds
Started Jun 07 08:08:04 PM PDT 24
Finished Jun 07 08:18:38 PM PDT 24
Peak memory 234856 kb
Host smart-35399554-5d14-42cf-b2dc-4666eab09227
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613511707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3613511707
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2301786503
Short name T230
Test name
Test status
Simulation time 1225865125 ps
CPU time 27.52 seconds
Started Jun 07 08:08:03 PM PDT 24
Finished Jun 07 08:08:34 PM PDT 24
Peak memory 219012 kb
Host smart-a2e62eea-8159-4546-92ff-13c81ca6262e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301786503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2301786503
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3505130104
Short name T356
Test name
Test status
Simulation time 7182867384 ps
CPU time 24.58 seconds
Started Jun 07 08:08:01 PM PDT 24
Finished Jun 07 08:08:27 PM PDT 24
Peak memory 219172 kb
Host smart-8edf77aa-5ff4-4e89-9f24-a3082d81da06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3505130104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3505130104
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1634158065
Short name T130
Test name
Test status
Simulation time 25978466687 ps
CPU time 70.82 seconds
Started Jun 07 08:08:03 PM PDT 24
Finished Jun 07 08:09:18 PM PDT 24
Peak memory 217524 kb
Host smart-904836ea-292f-4f8a-80ff-25652d6e0d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634158065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1634158065
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1941491322
Short name T180
Test name
Test status
Simulation time 34685805509 ps
CPU time 82.67 seconds
Started Jun 07 08:08:02 PM PDT 24
Finished Jun 07 08:09:27 PM PDT 24
Peak memory 219068 kb
Host smart-63f16fc0-41bb-44a4-8aa9-50ebf5f9a7ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941491322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1941491322
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.837707644
Short name T188
Test name
Test status
Simulation time 570861140 ps
CPU time 8.41 seconds
Started Jun 07 08:08:03 PM PDT 24
Finished Jun 07 08:08:15 PM PDT 24
Peak memory 216808 kb
Host smart-8b61121f-500c-46d0-9408-1a04b703ee5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837707644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.837707644
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4239891959
Short name T329
Test name
Test status
Simulation time 14222749504 ps
CPU time 231.42 seconds
Started Jun 07 08:08:06 PM PDT 24
Finished Jun 07 08:12:00 PM PDT 24
Peak memory 239800 kb
Host smart-571d9a81-8bb8-464b-b108-9fdadf36dfd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239891959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.4239891959
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3266970067
Short name T349
Test name
Test status
Simulation time 10277535364 ps
CPU time 15.77 seconds
Started Jun 07 08:08:06 PM PDT 24
Finished Jun 07 08:08:25 PM PDT 24
Peak memory 217452 kb
Host smart-e1bf981a-85eb-455e-94c0-7a0d5b47f658
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3266970067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3266970067
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3391737416
Short name T289
Test name
Test status
Simulation time 5864712780 ps
CPU time 54.6 seconds
Started Jun 07 08:08:03 PM PDT 24
Finished Jun 07 08:09:00 PM PDT 24
Peak memory 216284 kb
Host smart-ac7a6243-2b63-4327-9611-493f32cfcfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391737416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3391737416
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3530466259
Short name T298
Test name
Test status
Simulation time 2199240485 ps
CPU time 35.38 seconds
Started Jun 07 08:08:03 PM PDT 24
Finished Jun 07 08:08:42 PM PDT 24
Peak memory 218676 kb
Host smart-6e7a8f1f-16f4-460f-82bc-742ff126acc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530466259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3530466259
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.394226214
Short name T197
Test name
Test status
Simulation time 2613558620 ps
CPU time 17.15 seconds
Started Jun 07 08:08:03 PM PDT 24
Finished Jun 07 08:08:24 PM PDT 24
Peak memory 216816 kb
Host smart-e663f870-b6ae-4a15-9811-cb980a9edd93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394226214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.394226214
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3699090231
Short name T321
Test name
Test status
Simulation time 20266046037 ps
CPU time 206.26 seconds
Started Jun 07 08:08:03 PM PDT 24
Finished Jun 07 08:11:32 PM PDT 24
Peak memory 219360 kb
Host smart-4418669f-7940-49a0-af60-a2946c4bf429
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699090231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3699090231
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3193848430
Short name T279
Test name
Test status
Simulation time 15108424908 ps
CPU time 34.35 seconds
Started Jun 07 08:08:03 PM PDT 24
Finished Jun 07 08:08:41 PM PDT 24
Peak memory 219200 kb
Host smart-1f0350a4-02bc-4ce4-9177-6693306712e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193848430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3193848430
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2597351394
Short name T32
Test name
Test status
Simulation time 6187332914 ps
CPU time 28.75 seconds
Started Jun 07 08:08:04 PM PDT 24
Finished Jun 07 08:08:37 PM PDT 24
Peak memory 219172 kb
Host smart-aec2e2d9-c32e-44ac-9d9c-dd87a86d9ad8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2597351394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2597351394
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.519005159
Short name T187
Test name
Test status
Simulation time 353063012 ps
CPU time 19.65 seconds
Started Jun 07 08:08:04 PM PDT 24
Finished Jun 07 08:08:27 PM PDT 24
Peak memory 216328 kb
Host smart-779d3a5f-21b2-4061-abcc-b3e9dff5dc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519005159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.519005159
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1501196121
Short name T206
Test name
Test status
Simulation time 8606648092 ps
CPU time 31.13 seconds
Started Jun 07 08:08:02 PM PDT 24
Finished Jun 07 08:08:36 PM PDT 24
Peak memory 214316 kb
Host smart-c84c272f-2c84-41fb-b5c1-7abb1b32391c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501196121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1501196121
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.656191982
Short name T149
Test name
Test status
Simulation time 661184151 ps
CPU time 8.35 seconds
Started Jun 07 08:08:03 PM PDT 24
Finished Jun 07 08:08:16 PM PDT 24
Peak memory 216860 kb
Host smart-80936f4f-6411-4424-92e1-8dbf72b6998d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656191982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.656191982
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3897962134
Short name T247
Test name
Test status
Simulation time 32211737902 ps
CPU time 165.07 seconds
Started Jun 07 08:08:04 PM PDT 24
Finished Jun 07 08:10:53 PM PDT 24
Peak memory 225936 kb
Host smart-b1e672b8-1479-46e0-8b42-5c0b56a33ddb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897962134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3897962134
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3038611853
Short name T283
Test name
Test status
Simulation time 4185246457 ps
CPU time 46.39 seconds
Started Jun 07 08:08:02 PM PDT 24
Finished Jun 07 08:08:51 PM PDT 24
Peak memory 219076 kb
Host smart-e4720cad-f98f-46a3-bc44-390187c9dca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038611853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3038611853
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.621248890
Short name T144
Test name
Test status
Simulation time 7844751660 ps
CPU time 32.23 seconds
Started Jun 07 08:08:01 PM PDT 24
Finished Jun 07 08:08:35 PM PDT 24
Peak memory 211420 kb
Host smart-a527ed3c-8e16-49bb-bb7c-624622208079
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=621248890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.621248890
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2932158122
Short name T134
Test name
Test status
Simulation time 30679962938 ps
CPU time 61.42 seconds
Started Jun 07 08:08:03 PM PDT 24
Finished Jun 07 08:09:09 PM PDT 24
Peak memory 216580 kb
Host smart-62ead091-c3e9-48b4-8dbe-e0d7659b7e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932158122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2932158122
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1936326535
Short name T183
Test name
Test status
Simulation time 13327905159 ps
CPU time 70.69 seconds
Started Jun 07 08:08:04 PM PDT 24
Finished Jun 07 08:09:18 PM PDT 24
Peak memory 219108 kb
Host smart-b7e8fb27-b8fd-446c-9c0d-6e944fd274f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936326535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1936326535
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1273172734
Short name T178
Test name
Test status
Simulation time 13677350122 ps
CPU time 29.52 seconds
Started Jun 07 08:08:03 PM PDT 24
Finished Jun 07 08:08:37 PM PDT 24
Peak memory 217044 kb
Host smart-ba6b2d49-a776-4b26-9802-b96915dd41cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273172734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1273172734
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1600085697
Short name T295
Test name
Test status
Simulation time 84065554130 ps
CPU time 414.61 seconds
Started Jun 07 08:08:03 PM PDT 24
Finished Jun 07 08:15:01 PM PDT 24
Peak memory 237624 kb
Host smart-47a3b75b-50f5-42ba-abb9-fabe5d54b465
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600085697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1600085697
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.862595514
Short name T270
Test name
Test status
Simulation time 17565985389 ps
CPU time 35.97 seconds
Started Jun 07 08:08:02 PM PDT 24
Finished Jun 07 08:08:40 PM PDT 24
Peak memory 218932 kb
Host smart-1dca6d8c-05db-428e-91e5-9b5271a3cd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862595514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.862595514
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.717709612
Short name T182
Test name
Test status
Simulation time 2424854136 ps
CPU time 14.64 seconds
Started Jun 07 08:08:02 PM PDT 24
Finished Jun 07 08:08:19 PM PDT 24
Peak memory 219148 kb
Host smart-af205451-cb2c-466e-96ca-1ecdb4c0cb53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=717709612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.717709612
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3704204085
Short name T285
Test name
Test status
Simulation time 7438626996 ps
CPU time 68.62 seconds
Started Jun 07 08:08:03 PM PDT 24
Finished Jun 07 08:09:15 PM PDT 24
Peak memory 215788 kb
Host smart-b62f00bf-722a-4fa6-98a5-27de292cc019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704204085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3704204085
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1266208758
Short name T5
Test name
Test status
Simulation time 9733991615 ps
CPU time 96.5 seconds
Started Jun 07 08:08:03 PM PDT 24
Finished Jun 07 08:09:42 PM PDT 24
Peak memory 219112 kb
Host smart-f2eef224-7825-4961-bfb0-eb9e9d3a17d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266208758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1266208758
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.166667528
Short name T200
Test name
Test status
Simulation time 1352923065 ps
CPU time 16.87 seconds
Started Jun 07 08:08:12 PM PDT 24
Finished Jun 07 08:08:33 PM PDT 24
Peak memory 216900 kb
Host smart-522516fe-d719-40c5-a17b-f1250bd08ac5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166667528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.166667528
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3113898098
Short name T278
Test name
Test status
Simulation time 75384338839 ps
CPU time 462.97 seconds
Started Jun 07 08:08:05 PM PDT 24
Finished Jun 07 08:15:51 PM PDT 24
Peak memory 216336 kb
Host smart-d4f71d0a-e9f8-4ef4-8165-0d7b4fe820f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113898098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3113898098
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.370549917
Short name T145
Test name
Test status
Simulation time 20848822161 ps
CPU time 48.71 seconds
Started Jun 07 08:08:10 PM PDT 24
Finished Jun 07 08:09:02 PM PDT 24
Peak memory 219132 kb
Host smart-aeaeaf57-d48f-44a0-a5e3-1fbd99b39063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370549917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.370549917
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1736104211
Short name T109
Test name
Test status
Simulation time 13134233170 ps
CPU time 29.2 seconds
Started Jun 07 08:08:02 PM PDT 24
Finished Jun 07 08:08:34 PM PDT 24
Peak memory 219148 kb
Host smart-c96b58cb-7288-4dcc-b588-cbde1a14102b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1736104211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1736104211
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1024275507
Short name T172
Test name
Test status
Simulation time 1391058304 ps
CPU time 30.97 seconds
Started Jun 07 08:08:03 PM PDT 24
Finished Jun 07 08:08:38 PM PDT 24
Peak memory 216016 kb
Host smart-4c5537e7-c34a-4b7e-ac3a-841b2fa357cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024275507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1024275507
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1080546664
Short name T254
Test name
Test status
Simulation time 16140835869 ps
CPU time 162.5 seconds
Started Jun 07 08:08:06 PM PDT 24
Finished Jun 07 08:10:52 PM PDT 24
Peak memory 220972 kb
Host smart-a7199cb5-4136-4a35-934d-cf3a8644e41d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080546664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1080546664
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2982124679
Short name T2
Test name
Test status
Simulation time 1647272497 ps
CPU time 8.4 seconds
Started Jun 07 08:06:56 PM PDT 24
Finished Jun 07 08:07:05 PM PDT 24
Peak memory 216848 kb
Host smart-7b73d131-8d54-4b14-99ae-84844ad8ea7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982124679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2982124679
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1899773695
Short name T44
Test name
Test status
Simulation time 234196079123 ps
CPU time 588.97 seconds
Started Jun 07 08:06:56 PM PDT 24
Finished Jun 07 08:16:47 PM PDT 24
Peak memory 239420 kb
Host smart-2df6240f-a76a-4baf-90c7-0af718ad6cd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899773695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1899773695
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3688348384
Short name T328
Test name
Test status
Simulation time 2539495117 ps
CPU time 19.43 seconds
Started Jun 07 08:07:03 PM PDT 24
Finished Jun 07 08:07:23 PM PDT 24
Peak memory 218948 kb
Host smart-2bb54ac7-4816-47cf-9a8b-028c22fcd82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688348384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3688348384
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2968082930
Short name T138
Test name
Test status
Simulation time 6015289951 ps
CPU time 27.56 seconds
Started Jun 07 08:06:55 PM PDT 24
Finished Jun 07 08:07:24 PM PDT 24
Peak memory 219164 kb
Host smart-e759cd6e-a445-4a10-95a2-d0450eca02ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2968082930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2968082930
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.977853007
Short name T108
Test name
Test status
Simulation time 4439411572 ps
CPU time 46.57 seconds
Started Jun 07 08:06:57 PM PDT 24
Finished Jun 07 08:07:45 PM PDT 24
Peak memory 216584 kb
Host smart-69989ed6-352f-4d2e-922c-b6dfeeec8ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977853007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.977853007
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1213714565
Short name T282
Test name
Test status
Simulation time 34425892095 ps
CPU time 97.97 seconds
Started Jun 07 08:06:55 PM PDT 24
Finished Jun 07 08:08:34 PM PDT 24
Peak memory 219156 kb
Host smart-cb448591-f3ed-45cb-a9c3-e86ee48068d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213714565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1213714565
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2357100488
Short name T211
Test name
Test status
Simulation time 16853384236 ps
CPU time 27.06 seconds
Started Jun 07 08:06:56 PM PDT 24
Finished Jun 07 08:07:24 PM PDT 24
Peak memory 217288 kb
Host smart-c4f5b1ea-7506-427f-a647-b197fb40e2f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357100488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2357100488
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1870101975
Short name T355
Test name
Test status
Simulation time 11428578540 ps
CPU time 197.12 seconds
Started Jun 07 08:06:55 PM PDT 24
Finished Jun 07 08:10:13 PM PDT 24
Peak memory 238452 kb
Host smart-75a9d9e5-2260-42ed-9c98-06d6ccf1acbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870101975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1870101975
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3289271800
Short name T343
Test name
Test status
Simulation time 675909101 ps
CPU time 24.06 seconds
Started Jun 07 08:06:55 PM PDT 24
Finished Jun 07 08:07:20 PM PDT 24
Peak memory 219004 kb
Host smart-6c00842e-3e32-4106-8a1a-6d662eb6ba30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289271800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3289271800
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3404578079
Short name T143
Test name
Test status
Simulation time 6220163198 ps
CPU time 27.78 seconds
Started Jun 07 08:07:04 PM PDT 24
Finished Jun 07 08:07:35 PM PDT 24
Peak memory 219072 kb
Host smart-43e26dcd-3cc4-45f4-ae33-a6518b0cfda3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3404578079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3404578079
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1342280409
Short name T159
Test name
Test status
Simulation time 8274312972 ps
CPU time 36.67 seconds
Started Jun 07 08:06:55 PM PDT 24
Finished Jun 07 08:07:33 PM PDT 24
Peak memory 216260 kb
Host smart-1ff3959a-c55c-4f66-bee6-0de0aa188657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342280409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1342280409
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1866596981
Short name T92
Test name
Test status
Simulation time 54233380871 ps
CPU time 126.76 seconds
Started Jun 07 08:06:55 PM PDT 24
Finished Jun 07 08:09:03 PM PDT 24
Peak memory 219088 kb
Host smart-b4e591fa-6ff5-4aa2-9b2f-4edd4e0cb170
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866596981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1866596981
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2040722592
Short name T344
Test name
Test status
Simulation time 6670983694 ps
CPU time 25.67 seconds
Started Jun 07 08:07:06 PM PDT 24
Finished Jun 07 08:07:34 PM PDT 24
Peak memory 217068 kb
Host smart-56f59db3-7cec-4221-912f-7433055d089c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040722592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2040722592
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1624510646
Short name T306
Test name
Test status
Simulation time 4630720842 ps
CPU time 153.35 seconds
Started Jun 07 08:06:55 PM PDT 24
Finished Jun 07 08:09:30 PM PDT 24
Peak memory 225824 kb
Host smart-405a5d05-c114-4911-89ce-c9055fb522a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624510646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1624510646
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3795588015
Short name T39
Test name
Test status
Simulation time 1375745184 ps
CPU time 19.53 seconds
Started Jun 07 08:07:04 PM PDT 24
Finished Jun 07 08:07:26 PM PDT 24
Peak memory 218860 kb
Host smart-46a82c18-dc97-4a08-a683-dd4656a68aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795588015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3795588015
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.439170418
Short name T352
Test name
Test status
Simulation time 684140074 ps
CPU time 15.27 seconds
Started Jun 07 08:06:56 PM PDT 24
Finished Jun 07 08:07:13 PM PDT 24
Peak memory 218364 kb
Host smart-5023abfc-9dfc-4f14-8dc5-fc5522c11d93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=439170418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.439170418
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1901646209
Short name T317
Test name
Test status
Simulation time 27000365406 ps
CPU time 43.97 seconds
Started Jun 07 08:07:05 PM PDT 24
Finished Jun 07 08:07:51 PM PDT 24
Peak memory 216200 kb
Host smart-85b70573-5acd-4d0c-855d-e14add4f4c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901646209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1901646209
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2306572898
Short name T319
Test name
Test status
Simulation time 4409052690 ps
CPU time 19.75 seconds
Started Jun 07 08:06:54 PM PDT 24
Finished Jun 07 08:07:14 PM PDT 24
Peak memory 218488 kb
Host smart-52909e23-099d-401c-b84c-37c292514af9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306572898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2306572898
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1332276300
Short name T156
Test name
Test status
Simulation time 514312596 ps
CPU time 12.14 seconds
Started Jun 07 08:06:57 PM PDT 24
Finished Jun 07 08:07:11 PM PDT 24
Peak memory 216820 kb
Host smart-9a03d93e-a003-4920-8338-3af9e4025a18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332276300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1332276300
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3515603425
Short name T331
Test name
Test status
Simulation time 50292453449 ps
CPU time 319.27 seconds
Started Jun 07 08:07:05 PM PDT 24
Finished Jun 07 08:12:27 PM PDT 24
Peak memory 235012 kb
Host smart-7afb0fbf-c82e-42f3-88b8-7c56e5548121
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515603425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3515603425
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1660657272
Short name T55
Test name
Test status
Simulation time 5811524440 ps
CPU time 30.94 seconds
Started Jun 07 08:06:56 PM PDT 24
Finished Jun 07 08:07:28 PM PDT 24
Peak memory 219136 kb
Host smart-44d7eae3-92f4-4300-865d-4b79a0b78efa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1660657272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1660657272
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3569043944
Short name T292
Test name
Test status
Simulation time 6415339636 ps
CPU time 59.05 seconds
Started Jun 07 08:06:54 PM PDT 24
Finished Jun 07 08:07:54 PM PDT 24
Peak memory 216972 kb
Host smart-3a3a0817-4eee-4cab-ae1f-a900694872c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569043944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3569043944
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3099223337
Short name T29
Test name
Test status
Simulation time 25445169216 ps
CPU time 78.75 seconds
Started Jun 07 08:06:57 PM PDT 24
Finished Jun 07 08:08:17 PM PDT 24
Peak memory 219148 kb
Host smart-5ad654ab-97a4-417c-970f-640163726384
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099223337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3099223337
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2305236809
Short name T243
Test name
Test status
Simulation time 3935525190 ps
CPU time 30.87 seconds
Started Jun 07 08:07:04 PM PDT 24
Finished Jun 07 08:07:37 PM PDT 24
Peak memory 216840 kb
Host smart-96f69e8d-37fb-43f1-90e2-6557a1ee0c02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305236809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2305236809
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.4121492971
Short name T251
Test name
Test status
Simulation time 41716263375 ps
CPU time 597.81 seconds
Started Jun 07 08:07:02 PM PDT 24
Finished Jun 07 08:17:01 PM PDT 24
Peak memory 238196 kb
Host smart-16af315c-1001-45f0-9580-ac6f0742318a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121492971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.4121492971
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.995054991
Short name T274
Test name
Test status
Simulation time 14586519082 ps
CPU time 43.62 seconds
Started Jun 07 08:07:02 PM PDT 24
Finished Jun 07 08:07:46 PM PDT 24
Peak memory 219088 kb
Host smart-0c2d21e0-fb60-4f35-bec6-2e5c1c715646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995054991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.995054991
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1670507750
Short name T258
Test name
Test status
Simulation time 17123122390 ps
CPU time 33.81 seconds
Started Jun 07 08:07:04 PM PDT 24
Finished Jun 07 08:07:39 PM PDT 24
Peak memory 219168 kb
Host smart-efda2781-66e3-45f9-ae69-15bf9e745029
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1670507750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1670507750
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3151985030
Short name T342
Test name
Test status
Simulation time 1562647930 ps
CPU time 32.38 seconds
Started Jun 07 08:07:04 PM PDT 24
Finished Jun 07 08:07:39 PM PDT 24
Peak memory 216004 kb
Host smart-2718f782-26aa-4685-91f6-6eb581929251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151985030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3151985030
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1576739627
Short name T273
Test name
Test status
Simulation time 2813730740 ps
CPU time 56.96 seconds
Started Jun 07 08:07:03 PM PDT 24
Finished Jun 07 08:08:02 PM PDT 24
Peak memory 219072 kb
Host smart-a87d59d2-ca4a-4bf1-89e2-1918dad9bfe6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576739627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1576739627
Directory /workspace/9.rom_ctrl_stress_all/latest
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