Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.29 96.89 92.13 97.72 100.00 98.62 97.30 98.37


Total test records in report: 460
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T296 /workspace/coverage/default/5.rom_ctrl_smoke.1331167415 Jun 09 01:06:13 PM PDT 24 Jun 09 01:07:33 PM PDT 24 33555295737 ps
T297 /workspace/coverage/default/14.rom_ctrl_stress_all.698517509 Jun 09 01:06:28 PM PDT 24 Jun 09 01:06:40 PM PDT 24 225723701 ps
T298 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3274564839 Jun 09 01:06:18 PM PDT 24 Jun 09 01:07:24 PM PDT 24 31277200545 ps
T299 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3220216419 Jun 09 01:07:21 PM PDT 24 Jun 09 01:07:36 PM PDT 24 2323218221 ps
T300 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.721365417 Jun 09 01:07:19 PM PDT 24 Jun 09 01:07:51 PM PDT 24 4334306993 ps
T301 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3023901686 Jun 09 01:07:20 PM PDT 24 Jun 09 01:17:08 PM PDT 24 51334770050 ps
T302 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1760383241 Jun 09 01:05:56 PM PDT 24 Jun 09 01:06:07 PM PDT 24 1030738353 ps
T303 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2296133327 Jun 09 01:06:06 PM PDT 24 Jun 09 01:06:43 PM PDT 24 2816517893 ps
T304 /workspace/coverage/default/5.rom_ctrl_stress_all.3376046561 Jun 09 01:06:12 PM PDT 24 Jun 09 01:07:56 PM PDT 24 37822948989 ps
T305 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2021334427 Jun 09 01:07:05 PM PDT 24 Jun 09 01:16:25 PM PDT 24 45409388469 ps
T306 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1039424964 Jun 09 01:07:28 PM PDT 24 Jun 09 01:08:23 PM PDT 24 79663258412 ps
T307 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3128211728 Jun 09 01:06:24 PM PDT 24 Jun 09 01:06:49 PM PDT 24 9387633626 ps
T308 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.4287634642 Jun 09 01:05:58 PM PDT 24 Jun 09 01:11:29 PM PDT 24 9131654396 ps
T309 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1640257642 Jun 09 01:06:25 PM PDT 24 Jun 09 01:16:37 PM PDT 24 77496090037 ps
T310 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1921137747 Jun 09 01:07:59 PM PDT 24 Jun 09 01:12:53 PM PDT 24 4588796061 ps
T311 /workspace/coverage/default/8.rom_ctrl_alert_test.3207794891 Jun 09 01:06:19 PM PDT 24 Jun 09 01:06:48 PM PDT 24 14610072486 ps
T312 /workspace/coverage/default/34.rom_ctrl_smoke.2158268053 Jun 09 01:07:33 PM PDT 24 Jun 09 01:08:42 PM PDT 24 24562099293 ps
T313 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1185313174 Jun 09 01:07:46 PM PDT 24 Jun 09 01:08:05 PM PDT 24 1361586444 ps
T314 /workspace/coverage/default/39.rom_ctrl_alert_test.2583362455 Jun 09 01:07:56 PM PDT 24 Jun 09 01:08:28 PM PDT 24 7690719342 ps
T315 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.4144289075 Jun 09 01:07:58 PM PDT 24 Jun 09 01:08:17 PM PDT 24 1363096589 ps
T316 /workspace/coverage/default/13.rom_ctrl_stress_all.2271955753 Jun 09 01:06:20 PM PDT 24 Jun 09 01:07:00 PM PDT 24 704438135 ps
T317 /workspace/coverage/default/43.rom_ctrl_alert_test.5496916 Jun 09 01:08:10 PM PDT 24 Jun 09 01:08:36 PM PDT 24 5973449975 ps
T318 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1531311537 Jun 09 01:06:15 PM PDT 24 Jun 09 01:06:51 PM PDT 24 2570581835 ps
T319 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.474964257 Jun 09 01:07:34 PM PDT 24 Jun 09 01:07:45 PM PDT 24 185478685 ps
T27 /workspace/coverage/default/4.rom_ctrl_sec_cm.1665714734 Jun 09 01:06:09 PM PDT 24 Jun 09 01:08:20 PM PDT 24 2807873373 ps
T320 /workspace/coverage/default/28.rom_ctrl_stress_all.725854799 Jun 09 01:07:23 PM PDT 24 Jun 09 01:09:06 PM PDT 24 13867493039 ps
T321 /workspace/coverage/default/36.rom_ctrl_alert_test.2487591688 Jun 09 01:07:44 PM PDT 24 Jun 09 01:08:07 PM PDT 24 2288673863 ps
T322 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3691824691 Jun 09 01:06:23 PM PDT 24 Jun 09 01:09:14 PM PDT 24 11171171250 ps
T323 /workspace/coverage/default/28.rom_ctrl_alert_test.47384515 Jun 09 01:07:21 PM PDT 24 Jun 09 01:07:48 PM PDT 24 15054520088 ps
T324 /workspace/coverage/default/38.rom_ctrl_smoke.612649275 Jun 09 01:07:46 PM PDT 24 Jun 09 01:08:54 PM PDT 24 22058920108 ps
T325 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.4135499115 Jun 09 01:07:39 PM PDT 24 Jun 09 01:08:48 PM PDT 24 22011957467 ps
T326 /workspace/coverage/default/49.rom_ctrl_alert_test.3473074224 Jun 09 01:08:31 PM PDT 24 Jun 09 01:08:48 PM PDT 24 1271100844 ps
T327 /workspace/coverage/default/1.rom_ctrl_alert_test.2852000095 Jun 09 01:06:07 PM PDT 24 Jun 09 01:06:39 PM PDT 24 26234111800 ps
T328 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.4281592799 Jun 09 01:07:58 PM PDT 24 Jun 09 01:17:44 PM PDT 24 188790001870 ps
T329 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2862877056 Jun 09 01:06:23 PM PDT 24 Jun 09 01:06:33 PM PDT 24 756508606 ps
T330 /workspace/coverage/default/31.rom_ctrl_stress_all.998735315 Jun 09 01:07:28 PM PDT 24 Jun 09 01:10:22 PM PDT 24 18866769064 ps
T331 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3922230460 Jun 09 01:07:44 PM PDT 24 Jun 09 01:08:31 PM PDT 24 16468232462 ps
T332 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3871960693 Jun 09 01:07:40 PM PDT 24 Jun 09 01:07:59 PM PDT 24 4707722967 ps
T28 /workspace/coverage/default/2.rom_ctrl_sec_cm.3654608826 Jun 09 01:06:08 PM PDT 24 Jun 09 01:08:20 PM PDT 24 3738493076 ps
T333 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3456906970 Jun 09 01:06:22 PM PDT 24 Jun 09 01:09:09 PM PDT 24 11429014776 ps
T334 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4135159344 Jun 09 01:06:53 PM PDT 24 Jun 09 01:07:31 PM PDT 24 12196942756 ps
T335 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1958174731 Jun 09 01:07:00 PM PDT 24 Jun 09 01:07:38 PM PDT 24 11804055114 ps
T336 /workspace/coverage/default/0.rom_ctrl_alert_test.2180774440 Jun 09 01:05:57 PM PDT 24 Jun 09 01:06:24 PM PDT 24 5583531909 ps
T337 /workspace/coverage/default/2.rom_ctrl_smoke.1374037419 Jun 09 01:06:04 PM PDT 24 Jun 09 01:07:15 PM PDT 24 6656405193 ps
T338 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1606770750 Jun 09 01:07:29 PM PDT 24 Jun 09 01:11:32 PM PDT 24 55122217514 ps
T339 /workspace/coverage/default/29.rom_ctrl_alert_test.536849564 Jun 09 01:07:29 PM PDT 24 Jun 09 01:07:37 PM PDT 24 689539306 ps
T340 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.4101257272 Jun 09 01:06:32 PM PDT 24 Jun 09 01:07:42 PM PDT 24 34199486987 ps
T341 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1319289644 Jun 09 01:06:43 PM PDT 24 Jun 09 01:07:06 PM PDT 24 7226255486 ps
T342 /workspace/coverage/default/42.rom_ctrl_stress_all.901002253 Jun 09 01:07:57 PM PDT 24 Jun 09 01:10:43 PM PDT 24 17234311330 ps
T343 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2615140540 Jun 09 01:07:48 PM PDT 24 Jun 09 01:15:01 PM PDT 24 37790114369 ps
T344 /workspace/coverage/default/47.rom_ctrl_stress_all.2498886893 Jun 09 01:08:17 PM PDT 24 Jun 09 01:09:46 PM PDT 24 6878594632 ps
T345 /workspace/coverage/default/20.rom_ctrl_stress_all.4206802311 Jun 09 01:06:44 PM PDT 24 Jun 09 01:09:29 PM PDT 24 16470552736 ps
T346 /workspace/coverage/default/17.rom_ctrl_smoke.1858444324 Jun 09 01:06:33 PM PDT 24 Jun 09 01:06:54 PM PDT 24 2159803558 ps
T347 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3736420698 Jun 09 01:07:00 PM PDT 24 Jun 09 01:17:49 PM PDT 24 167174465302 ps
T348 /workspace/coverage/default/46.rom_ctrl_alert_test.2603668653 Jun 09 01:08:14 PM PDT 24 Jun 09 01:08:40 PM PDT 24 16372425730 ps
T349 /workspace/coverage/default/44.rom_ctrl_smoke.1820809612 Jun 09 01:08:10 PM PDT 24 Jun 09 01:09:13 PM PDT 24 46289780892 ps
T350 /workspace/coverage/default/41.rom_ctrl_stress_all.4228624135 Jun 09 01:07:55 PM PDT 24 Jun 09 01:08:47 PM PDT 24 40436443627 ps
T351 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.860844610 Jun 09 01:06:05 PM PDT 24 Jun 09 01:06:24 PM PDT 24 2688526915 ps
T352 /workspace/coverage/default/11.rom_ctrl_alert_test.2820446888 Jun 09 01:06:25 PM PDT 24 Jun 09 01:06:52 PM PDT 24 3034017462 ps
T353 /workspace/coverage/default/27.rom_ctrl_smoke.4006111907 Jun 09 01:07:20 PM PDT 24 Jun 09 01:08:05 PM PDT 24 19583899006 ps
T354 /workspace/coverage/default/6.rom_ctrl_alert_test.3413930235 Jun 09 01:06:24 PM PDT 24 Jun 09 01:06:55 PM PDT 24 7811845939 ps
T355 /workspace/coverage/default/35.rom_ctrl_alert_test.4143566356 Jun 09 01:07:40 PM PDT 24 Jun 09 01:08:02 PM PDT 24 8540710414 ps
T356 /workspace/coverage/default/46.rom_ctrl_stress_all.2710156864 Jun 09 01:08:16 PM PDT 24 Jun 09 01:09:21 PM PDT 24 13431567071 ps
T357 /workspace/coverage/default/16.rom_ctrl_alert_test.4061712981 Jun 09 01:06:34 PM PDT 24 Jun 09 01:07:09 PM PDT 24 4169918825 ps
T358 /workspace/coverage/default/7.rom_ctrl_stress_all.954699853 Jun 09 01:06:17 PM PDT 24 Jun 09 01:08:43 PM PDT 24 34127507793 ps
T359 /workspace/coverage/default/13.rom_ctrl_smoke.1439632501 Jun 09 01:06:23 PM PDT 24 Jun 09 01:06:53 PM PDT 24 1182364627 ps
T54 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1066118928 Jun 09 12:29:02 PM PDT 24 Jun 09 12:31:20 PM PDT 24 17198071491 ps
T55 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2897299084 Jun 09 12:28:56 PM PDT 24 Jun 09 12:30:35 PM PDT 24 11299441148 ps
T360 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3132368178 Jun 09 12:28:52 PM PDT 24 Jun 09 12:29:14 PM PDT 24 5551241021 ps
T56 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2526177368 Jun 09 12:29:18 PM PDT 24 Jun 09 12:30:35 PM PDT 24 6663872129 ps
T60 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2993975099 Jun 09 12:29:03 PM PDT 24 Jun 09 12:29:35 PM PDT 24 4157532138 ps
T82 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3749405596 Jun 09 12:29:20 PM PDT 24 Jun 09 12:29:52 PM PDT 24 3394739819 ps
T361 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1780840575 Jun 09 12:29:01 PM PDT 24 Jun 09 12:29:18 PM PDT 24 982229055 ps
T362 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1317780836 Jun 09 12:29:08 PM PDT 24 Jun 09 12:29:29 PM PDT 24 9201529769 ps
T51 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3241743291 Jun 09 12:29:14 PM PDT 24 Jun 09 12:30:43 PM PDT 24 3354523850 ps
T363 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1030234539 Jun 09 12:29:04 PM PDT 24 Jun 09 12:29:24 PM PDT 24 4407831215 ps
T88 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2030292922 Jun 09 12:29:23 PM PDT 24 Jun 09 12:31:46 PM PDT 24 28232558340 ps
T61 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2044802980 Jun 09 12:29:36 PM PDT 24 Jun 09 12:31:35 PM PDT 24 53825186629 ps
T364 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.547918731 Jun 09 12:29:02 PM PDT 24 Jun 09 12:29:23 PM PDT 24 4440717502 ps
T52 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3902971812 Jun 09 12:28:57 PM PDT 24 Jun 09 12:31:34 PM PDT 24 651176026 ps
T62 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1992875950 Jun 09 12:28:56 PM PDT 24 Jun 09 12:30:55 PM PDT 24 13464245883 ps
T89 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1426613248 Jun 09 12:29:03 PM PDT 24 Jun 09 12:29:28 PM PDT 24 10493830776 ps
T365 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.673651334 Jun 09 12:29:27 PM PDT 24 Jun 09 12:29:51 PM PDT 24 10572660287 ps
T366 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3283099350 Jun 09 12:29:30 PM PDT 24 Jun 09 12:29:59 PM PDT 24 2809546623 ps
T367 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1420211790 Jun 09 12:29:17 PM PDT 24 Jun 09 12:29:37 PM PDT 24 7627509848 ps
T63 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4116261735 Jun 09 12:29:03 PM PDT 24 Jun 09 12:29:30 PM PDT 24 3032658141 ps
T368 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2020997238 Jun 09 12:28:53 PM PDT 24 Jun 09 12:29:31 PM PDT 24 4111866849 ps
T53 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.84730032 Jun 09 12:29:02 PM PDT 24 Jun 09 12:31:45 PM PDT 24 2700579744 ps
T369 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1953640381 Jun 09 12:29:00 PM PDT 24 Jun 09 12:29:18 PM PDT 24 2680123406 ps
T99 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.537156033 Jun 09 12:29:05 PM PDT 24 Jun 09 12:30:32 PM PDT 24 4435006609 ps
T64 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1791700225 Jun 09 12:28:56 PM PDT 24 Jun 09 12:29:22 PM PDT 24 4095498897 ps
T83 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1824557150 Jun 09 12:29:27 PM PDT 24 Jun 09 12:29:36 PM PDT 24 176284964 ps
T65 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.750984621 Jun 09 12:28:56 PM PDT 24 Jun 09 12:29:06 PM PDT 24 252107039 ps
T97 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2464390537 Jun 09 12:29:03 PM PDT 24 Jun 09 12:31:41 PM PDT 24 2562818106 ps
T84 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2038981245 Jun 09 12:28:57 PM PDT 24 Jun 09 12:29:06 PM PDT 24 167563397 ps
T370 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3342276630 Jun 09 12:29:30 PM PDT 24 Jun 09 12:29:44 PM PDT 24 666497066 ps
T100 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1448316749 Jun 09 12:29:27 PM PDT 24 Jun 09 12:31:13 PM PDT 24 4067072424 ps
T371 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.920137275 Jun 09 12:28:54 PM PDT 24 Jun 09 12:30:14 PM PDT 24 6722946360 ps
T85 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.808511855 Jun 09 12:29:14 PM PDT 24 Jun 09 12:29:35 PM PDT 24 7346218714 ps
T86 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2822849532 Jun 09 12:29:01 PM PDT 24 Jun 09 12:29:14 PM PDT 24 1706307663 ps
T372 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.639064673 Jun 09 12:28:59 PM PDT 24 Jun 09 12:29:08 PM PDT 24 1267467825 ps
T66 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3612053823 Jun 09 12:29:21 PM PDT 24 Jun 09 12:30:32 PM PDT 24 10526538500 ps
T87 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2213869948 Jun 09 12:29:05 PM PDT 24 Jun 09 12:29:14 PM PDT 24 338359369 ps
T67 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2228738531 Jun 09 12:29:03 PM PDT 24 Jun 09 12:29:41 PM PDT 24 1857904583 ps
T373 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1935242140 Jun 09 12:28:54 PM PDT 24 Jun 09 12:29:13 PM PDT 24 2951604862 ps
T98 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2833530153 Jun 09 12:29:00 PM PDT 24 Jun 09 12:31:36 PM PDT 24 1194462529 ps
T374 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.510298357 Jun 09 12:29:10 PM PDT 24 Jun 09 12:29:34 PM PDT 24 2393237943 ps
T101 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3754496122 Jun 09 12:29:19 PM PDT 24 Jun 09 12:32:14 PM PDT 24 8745797353 ps
T102 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3748885290 Jun 09 12:29:22 PM PDT 24 Jun 09 12:32:09 PM PDT 24 5370817418 ps
T375 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.658586546 Jun 09 12:29:03 PM PDT 24 Jun 09 12:29:21 PM PDT 24 5115421415 ps
T376 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.624185045 Jun 09 12:29:01 PM PDT 24 Jun 09 12:29:11 PM PDT 24 181679800 ps
T377 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1262305955 Jun 09 12:28:52 PM PDT 24 Jun 09 12:29:20 PM PDT 24 2648441424 ps
T378 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2771097140 Jun 09 12:29:28 PM PDT 24 Jun 09 12:30:00 PM PDT 24 12970005661 ps
T379 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1714331765 Jun 09 12:29:06 PM PDT 24 Jun 09 12:29:32 PM PDT 24 11598549477 ps
T380 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.357586814 Jun 09 12:29:07 PM PDT 24 Jun 09 12:29:19 PM PDT 24 672544823 ps
T381 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.140682417 Jun 09 12:29:09 PM PDT 24 Jun 09 12:29:20 PM PDT 24 1649434789 ps
T382 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.138356245 Jun 09 12:29:28 PM PDT 24 Jun 09 12:29:53 PM PDT 24 37640080791 ps
T72 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1542742560 Jun 09 12:29:03 PM PDT 24 Jun 09 12:29:34 PM PDT 24 22676608208 ps
T383 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.625508714 Jun 09 12:29:07 PM PDT 24 Jun 09 12:29:29 PM PDT 24 9178260197 ps
T73 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.924303422 Jun 09 12:29:01 PM PDT 24 Jun 09 12:29:21 PM PDT 24 6803958925 ps
T384 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4250629212 Jun 09 12:29:36 PM PDT 24 Jun 09 12:29:56 PM PDT 24 8526828297 ps
T385 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1102739627 Jun 09 12:29:20 PM PDT 24 Jun 09 12:29:51 PM PDT 24 11985066420 ps
T386 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1585744125 Jun 09 12:28:54 PM PDT 24 Jun 09 12:29:22 PM PDT 24 4208280090 ps
T387 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2857902572 Jun 09 12:29:07 PM PDT 24 Jun 09 12:29:29 PM PDT 24 4833759349 ps
T388 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.307641943 Jun 09 12:28:58 PM PDT 24 Jun 09 12:29:11 PM PDT 24 2139907736 ps
T389 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.682916694 Jun 09 12:29:04 PM PDT 24 Jun 09 12:29:27 PM PDT 24 2333397085 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2695275199 Jun 09 12:29:04 PM PDT 24 Jun 09 12:29:22 PM PDT 24 2157154590 ps
T391 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.996358127 Jun 09 12:29:01 PM PDT 24 Jun 09 12:29:11 PM PDT 24 167660307 ps
T392 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2567334444 Jun 09 12:29:03 PM PDT 24 Jun 09 12:29:33 PM PDT 24 11177731708 ps
T107 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1909585424 Jun 09 12:28:57 PM PDT 24 Jun 09 12:31:45 PM PDT 24 2448603048 ps
T393 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3777842328 Jun 09 12:29:27 PM PDT 24 Jun 09 12:29:36 PM PDT 24 173860614 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3094157494 Jun 09 12:28:56 PM PDT 24 Jun 09 12:29:04 PM PDT 24 216575064 ps
T106 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.511262983 Jun 09 12:29:06 PM PDT 24 Jun 09 12:30:26 PM PDT 24 229763125 ps
T395 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2083321423 Jun 09 12:29:18 PM PDT 24 Jun 09 12:29:48 PM PDT 24 4032979074 ps
T103 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3985667316 Jun 09 12:28:56 PM PDT 24 Jun 09 12:30:19 PM PDT 24 262976472 ps
T396 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1818586031 Jun 09 12:28:58 PM PDT 24 Jun 09 12:29:12 PM PDT 24 5974390895 ps
T397 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2569501801 Jun 09 12:29:21 PM PDT 24 Jun 09 12:31:56 PM PDT 24 44129638655 ps
T398 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.22095782 Jun 09 12:29:09 PM PDT 24 Jun 09 12:29:40 PM PDT 24 3497191246 ps
T74 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1865304470 Jun 09 12:30:17 PM PDT 24 Jun 09 12:30:36 PM PDT 24 14788601374 ps
T399 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2809561644 Jun 09 12:29:03 PM PDT 24 Jun 09 12:29:19 PM PDT 24 4494124351 ps
T400 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.285135068 Jun 09 12:29:29 PM PDT 24 Jun 09 12:30:51 PM PDT 24 840355398 ps
T401 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3552252396 Jun 09 12:29:15 PM PDT 24 Jun 09 12:29:24 PM PDT 24 699584990 ps
T75 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1826732428 Jun 09 12:28:58 PM PDT 24 Jun 09 12:29:30 PM PDT 24 14273763972 ps
T76 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2385772753 Jun 09 12:29:06 PM PDT 24 Jun 09 12:30:35 PM PDT 24 47626291412 ps
T402 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.144401037 Jun 09 12:28:59 PM PDT 24 Jun 09 12:29:16 PM PDT 24 1252213558 ps
T77 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1427103738 Jun 09 12:28:58 PM PDT 24 Jun 09 12:30:44 PM PDT 24 12058994133 ps
T403 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3381649317 Jun 09 12:28:58 PM PDT 24 Jun 09 12:29:31 PM PDT 24 8190553221 ps
T404 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1594432253 Jun 09 12:29:17 PM PDT 24 Jun 09 12:29:55 PM PDT 24 2080580669 ps
T405 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3707671505 Jun 09 12:28:59 PM PDT 24 Jun 09 12:31:48 PM PDT 24 2872514024 ps
T406 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2423582647 Jun 09 12:29:18 PM PDT 24 Jun 09 12:29:33 PM PDT 24 4440250356 ps
T407 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1208254020 Jun 09 12:29:02 PM PDT 24 Jun 09 12:29:32 PM PDT 24 3650543736 ps
T408 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3772603828 Jun 09 12:28:53 PM PDT 24 Jun 09 12:29:22 PM PDT 24 3721738864 ps
T409 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2742126896 Jun 09 12:29:00 PM PDT 24 Jun 09 12:29:24 PM PDT 24 31899928906 ps
T410 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4237920029 Jun 09 12:28:57 PM PDT 24 Jun 09 12:31:55 PM PDT 24 87749645296 ps
T411 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2568519513 Jun 09 12:29:06 PM PDT 24 Jun 09 12:29:31 PM PDT 24 2731489408 ps
T412 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1967985049 Jun 09 12:29:13 PM PDT 24 Jun 09 12:29:22 PM PDT 24 1178690786 ps
T413 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.827558689 Jun 09 12:29:09 PM PDT 24 Jun 09 12:29:19 PM PDT 24 497396418 ps
T414 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3579298720 Jun 09 12:29:02 PM PDT 24 Jun 09 12:29:15 PM PDT 24 175310208 ps
T415 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2811222064 Jun 09 12:30:10 PM PDT 24 Jun 09 12:30:34 PM PDT 24 5242510224 ps
T416 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1056278187 Jun 09 12:28:59 PM PDT 24 Jun 09 12:29:08 PM PDT 24 169373822 ps
T417 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1498423394 Jun 09 12:29:22 PM PDT 24 Jun 09 12:31:40 PM PDT 24 65714913623 ps
T418 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.80036580 Jun 09 12:29:26 PM PDT 24 Jun 09 12:29:49 PM PDT 24 2609740249 ps
T419 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4069692521 Jun 09 12:29:25 PM PDT 24 Jun 09 12:32:19 PM PDT 24 14845047837 ps
T420 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1466439372 Jun 09 12:29:29 PM PDT 24 Jun 09 12:29:47 PM PDT 24 1500648015 ps
T421 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1300002218 Jun 09 12:30:11 PM PDT 24 Jun 09 12:30:36 PM PDT 24 2898633700 ps
T422 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.579497042 Jun 09 12:29:00 PM PDT 24 Jun 09 12:29:33 PM PDT 24 3333968189 ps
T423 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3753636516 Jun 09 12:28:58 PM PDT 24 Jun 09 12:29:24 PM PDT 24 12057957444 ps
T424 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.8835358 Jun 09 12:29:09 PM PDT 24 Jun 09 12:29:18 PM PDT 24 171034976 ps
T80 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1234597282 Jun 09 12:29:01 PM PDT 24 Jun 09 12:32:12 PM PDT 24 37423996050 ps
T78 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1447130071 Jun 09 12:29:00 PM PDT 24 Jun 09 12:29:18 PM PDT 24 1403013124 ps
T425 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3627614026 Jun 09 12:29:02 PM PDT 24 Jun 09 12:31:53 PM PDT 24 3672167647 ps
T426 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4138326941 Jun 09 12:29:43 PM PDT 24 Jun 09 12:29:52 PM PDT 24 167532137 ps
T427 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2524499049 Jun 09 12:28:53 PM PDT 24 Jun 09 12:29:07 PM PDT 24 635974666 ps
T428 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3816271050 Jun 09 12:28:57 PM PDT 24 Jun 09 12:29:11 PM PDT 24 579125084 ps
T429 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2418797826 Jun 09 12:28:59 PM PDT 24 Jun 09 12:29:25 PM PDT 24 3225659764 ps
T81 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2976617599 Jun 09 12:28:55 PM PDT 24 Jun 09 12:29:23 PM PDT 24 21150312366 ps
T430 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4259124690 Jun 09 12:29:06 PM PDT 24 Jun 09 12:30:06 PM PDT 24 4501560551 ps
T431 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1799897002 Jun 09 12:28:58 PM PDT 24 Jun 09 12:30:20 PM PDT 24 245511632 ps
T79 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3404282651 Jun 09 12:29:27 PM PDT 24 Jun 09 12:29:58 PM PDT 24 17662803517 ps
T432 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1455983034 Jun 09 12:29:25 PM PDT 24 Jun 09 12:29:52 PM PDT 24 3055520962 ps
T433 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3600943848 Jun 09 12:28:53 PM PDT 24 Jun 09 12:29:05 PM PDT 24 684225770 ps
T434 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1153837822 Jun 09 12:29:29 PM PDT 24 Jun 09 12:30:52 PM PDT 24 363926961 ps
T435 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2682673493 Jun 09 12:29:16 PM PDT 24 Jun 09 12:29:35 PM PDT 24 3027563570 ps
T436 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.900410972 Jun 09 12:29:16 PM PDT 24 Jun 09 12:29:41 PM PDT 24 3926720162 ps
T437 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1503701266 Jun 09 12:29:04 PM PDT 24 Jun 09 12:29:36 PM PDT 24 4270077425 ps
T438 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2565519625 Jun 09 12:29:00 PM PDT 24 Jun 09 12:29:15 PM PDT 24 1827497200 ps
T439 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1629475307 Jun 09 12:29:01 PM PDT 24 Jun 09 12:29:15 PM PDT 24 222702731 ps
T440 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1508308566 Jun 09 12:29:22 PM PDT 24 Jun 09 12:29:45 PM PDT 24 2534730481 ps
T105 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1968073211 Jun 09 12:28:57 PM PDT 24 Jun 09 12:30:23 PM PDT 24 670487925 ps
T441 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4263137961 Jun 09 12:29:01 PM PDT 24 Jun 09 12:29:13 PM PDT 24 761580674 ps
T442 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1310735137 Jun 09 12:28:59 PM PDT 24 Jun 09 12:29:10 PM PDT 24 829303368 ps
T443 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3354066888 Jun 09 12:28:57 PM PDT 24 Jun 09 12:29:09 PM PDT 24 750108217 ps
T444 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3387076919 Jun 09 12:28:54 PM PDT 24 Jun 09 12:29:03 PM PDT 24 174201935 ps
T445 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1468181230 Jun 09 12:28:56 PM PDT 24 Jun 09 12:29:20 PM PDT 24 25254995607 ps
T446 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2120992825 Jun 09 12:29:04 PM PDT 24 Jun 09 12:30:15 PM PDT 24 20596839745 ps
T104 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1018883977 Jun 09 12:29:03 PM PDT 24 Jun 09 12:31:58 PM PDT 24 7514230702 ps
T447 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3867165612 Jun 09 12:28:56 PM PDT 24 Jun 09 12:29:23 PM PDT 24 3082279481 ps
T448 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3065629770 Jun 09 12:29:08 PM PDT 24 Jun 09 12:29:37 PM PDT 24 6911138077 ps
T449 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1667740240 Jun 09 12:29:31 PM PDT 24 Jun 09 12:29:40 PM PDT 24 2354531903 ps
T450 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3725397900 Jun 09 12:28:56 PM PDT 24 Jun 09 12:29:25 PM PDT 24 6374034451 ps
T451 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.885352926 Jun 09 12:29:05 PM PDT 24 Jun 09 12:29:30 PM PDT 24 2777561455 ps
T452 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2485347826 Jun 09 12:29:07 PM PDT 24 Jun 09 12:29:20 PM PDT 24 1268373548 ps
T453 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3477917169 Jun 09 12:29:15 PM PDT 24 Jun 09 12:29:41 PM PDT 24 11549853187 ps
T454 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1895545064 Jun 09 12:29:03 PM PDT 24 Jun 09 12:29:36 PM PDT 24 12106359194 ps
T455 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1431298853 Jun 09 12:29:02 PM PDT 24 Jun 09 12:29:21 PM PDT 24 3449007944 ps
T456 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4130084197 Jun 09 12:30:15 PM PDT 24 Jun 09 12:30:44 PM PDT 24 13513106797 ps
T457 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2116750647 Jun 09 12:29:12 PM PDT 24 Jun 09 12:29:39 PM PDT 24 4725299362 ps
T458 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4158771940 Jun 09 12:29:11 PM PDT 24 Jun 09 12:30:24 PM PDT 24 2016824334 ps
T459 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3381463577 Jun 09 12:29:02 PM PDT 24 Jun 09 12:31:50 PM PDT 24 20026616207 ps
T460 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1575488957 Jun 09 12:29:00 PM PDT 24 Jun 09 12:29:31 PM PDT 24 15701181528 ps

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.465718605
Short name T4
Test name
Test status
Simulation time 16289580351 ps
CPU time 155.27 seconds
Started Jun 09 01:06:11 PM PDT 24
Finished Jun 09 01:08:46 PM PDT 24
Peak memory 221036 kb
Host smart-a906a3d1-1d47-4177-bb01-f3907620afa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465718605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.465718605
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3034417553
Short name T13
Test name
Test status
Simulation time 47394258368 ps
CPU time 2303.17 seconds
Started Jun 09 01:06:06 PM PDT 24
Finished Jun 09 01:44:30 PM PDT 24
Peak memory 234684 kb
Host smart-b4acded3-f79d-41f2-b1d7-44b3ddbd6cbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034417553 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.3034417553
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1901297813
Short name T30
Test name
Test status
Simulation time 189395366506 ps
CPU time 579.61 seconds
Started Jun 09 01:06:06 PM PDT 24
Finished Jun 09 01:15:46 PM PDT 24
Peak memory 236540 kb
Host smart-460ecdf2-cce4-49ec-b8c2-d71e0e91f96c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901297813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1901297813
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2464390537
Short name T97
Test name
Test status
Simulation time 2562818106 ps
CPU time 157.64 seconds
Started Jun 09 12:29:03 PM PDT 24
Finished Jun 09 12:31:41 PM PDT 24
Peak memory 214132 kb
Host smart-9e304593-4631-4eda-b79a-1879313b31c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464390537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2464390537
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.602701426
Short name T6
Test name
Test status
Simulation time 25468010568 ps
CPU time 139.5 seconds
Started Jun 09 01:06:04 PM PDT 24
Finished Jun 09 01:08:24 PM PDT 24
Peak memory 234916 kb
Host smart-a7c92607-f527-4b44-aa57-00f97454ef04
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602701426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.602701426
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2228738531
Short name T67
Test name
Test status
Simulation time 1857904583 ps
CPU time 37.07 seconds
Started Jun 09 12:29:03 PM PDT 24
Finished Jun 09 12:29:41 PM PDT 24
Peak memory 213904 kb
Host smart-a21b1fa1-7786-489d-9969-7fb7b2226143
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228738531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2228738531
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2033280633
Short name T3
Test name
Test status
Simulation time 14740528407 ps
CPU time 274.1 seconds
Started Jun 09 01:07:35 PM PDT 24
Finished Jun 09 01:12:09 PM PDT 24
Peak memory 213180 kb
Host smart-c174d3ab-7282-484d-90d3-b5c859f98d34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033280633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2033280633
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3754496122
Short name T101
Test name
Test status
Simulation time 8745797353 ps
CPU time 174.37 seconds
Started Jun 09 12:29:19 PM PDT 24
Finished Jun 09 12:32:14 PM PDT 24
Peak memory 215460 kb
Host smart-25dcc6b6-a917-4201-9b07-f8b098da1773
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754496122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3754496122
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3217589503
Short name T10
Test name
Test status
Simulation time 6443094445 ps
CPU time 28.14 seconds
Started Jun 09 01:06:22 PM PDT 24
Finished Jun 09 01:06:51 PM PDT 24
Peak memory 217208 kb
Host smart-893ecad9-b69c-4f24-ad3e-54c89b300cce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217589503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3217589503
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2044802980
Short name T61
Test name
Test status
Simulation time 53825186629 ps
CPU time 118.68 seconds
Started Jun 09 12:29:36 PM PDT 24
Finished Jun 09 12:31:35 PM PDT 24
Peak memory 214092 kb
Host smart-4d530d9b-e0a9-43b3-ae48-7e55b8972f74
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044802980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2044802980
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2688974841
Short name T35
Test name
Test status
Simulation time 1649477099 ps
CPU time 19.71 seconds
Started Jun 09 01:06:24 PM PDT 24
Finished Jun 09 01:06:43 PM PDT 24
Peak memory 218916 kb
Host smart-98c589a4-0c32-4bb8-a28a-df71f610f934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688974841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2688974841
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1176957727
Short name T41
Test name
Test status
Simulation time 7260980286 ps
CPU time 60.87 seconds
Started Jun 09 01:06:22 PM PDT 24
Finished Jun 09 01:07:23 PM PDT 24
Peak memory 219016 kb
Host smart-47a77ae4-44f4-4127-b909-49e730f1901e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176957727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1176957727
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3283742330
Short name T39
Test name
Test status
Simulation time 6842307863 ps
CPU time 57.68 seconds
Started Jun 09 01:06:31 PM PDT 24
Finished Jun 09 01:07:29 PM PDT 24
Peak memory 219048 kb
Host smart-fa01f46a-2c47-4dc4-a134-6efb9ad48245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283742330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3283742330
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3748885290
Short name T102
Test name
Test status
Simulation time 5370817418 ps
CPU time 167.1 seconds
Started Jun 09 12:29:22 PM PDT 24
Finished Jun 09 12:32:09 PM PDT 24
Peak memory 214472 kb
Host smart-3a5e2c20-60c6-4bd7-88bd-b262bd29a95d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748885290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3748885290
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3576813579
Short name T70
Test name
Test status
Simulation time 9858749400 ps
CPU time 122.52 seconds
Started Jun 09 01:06:49 PM PDT 24
Finished Jun 09 01:08:52 PM PDT 24
Peak memory 220220 kb
Host smart-9ef9c4cd-1b01-43ca-b889-336366ad416c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576813579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3576813579
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3902971812
Short name T52
Test name
Test status
Simulation time 651176026 ps
CPU time 155.9 seconds
Started Jun 09 12:28:57 PM PDT 24
Finished Jun 09 12:31:34 PM PDT 24
Peak memory 214304 kb
Host smart-e36f0dae-3b55-46f7-ae2b-7b08a92c3023
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902971812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3902971812
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.864399810
Short name T112
Test name
Test status
Simulation time 11707617360 ps
CPU time 26.79 seconds
Started Jun 09 01:05:57 PM PDT 24
Finished Jun 09 01:06:24 PM PDT 24
Peak memory 219356 kb
Host smart-238d30d1-23c7-4d60-819d-c45911b92270
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=864399810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.864399810
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1791700225
Short name T64
Test name
Test status
Simulation time 4095498897 ps
CPU time 25.01 seconds
Started Jun 09 12:28:56 PM PDT 24
Finished Jun 09 12:29:22 PM PDT 24
Peak memory 212676 kb
Host smart-4a58a803-68f6-4b22-a543-9c553d73e09c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791700225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1791700225
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3227730167
Short name T16
Test name
Test status
Simulation time 70745735320 ps
CPU time 2671.57 seconds
Started Jun 09 01:08:12 PM PDT 24
Finished Jun 09 01:52:44 PM PDT 24
Peak memory 251792 kb
Host smart-54858f67-b547-4990-9b8a-b8749f67efd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227730167 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3227730167
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4130084197
Short name T456
Test name
Test status
Simulation time 13513106797 ps
CPU time 28.47 seconds
Started Jun 09 12:30:15 PM PDT 24
Finished Jun 09 12:30:44 PM PDT 24
Peak memory 212144 kb
Host smart-e66a9a52-c3d3-43e2-8156-440c3049812a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130084197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.4130084197
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1300002218
Short name T421
Test name
Test status
Simulation time 2898633700 ps
CPU time 25.01 seconds
Started Jun 09 12:30:11 PM PDT 24
Finished Jun 09 12:30:36 PM PDT 24
Peak memory 211360 kb
Host smart-a544b7d8-96ff-4855-b7d3-ece1f4ffa58a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300002218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1300002218
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1585744125
Short name T386
Test name
Test status
Simulation time 4208280090 ps
CPU time 27.43 seconds
Started Jun 09 12:28:54 PM PDT 24
Finished Jun 09 12:29:22 PM PDT 24
Peak memory 211980 kb
Host smart-bf616677-0d67-4736-b87c-35f2227b5750
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585744125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1585744125
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3600943848
Short name T433
Test name
Test status
Simulation time 684225770 ps
CPU time 11.14 seconds
Started Jun 09 12:28:53 PM PDT 24
Finished Jun 09 12:29:05 PM PDT 24
Peak memory 216404 kb
Host smart-77742343-728f-41a3-a426-501f324c95cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600943848 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3600943848
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3725397900
Short name T450
Test name
Test status
Simulation time 6374034451 ps
CPU time 27.45 seconds
Started Jun 09 12:28:56 PM PDT 24
Finished Jun 09 12:29:25 PM PDT 24
Peak memory 212568 kb
Host smart-9aadaf8b-5c64-40e3-8b8a-f01785cdb696
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725397900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3725397900
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3772603828
Short name T408
Test name
Test status
Simulation time 3721738864 ps
CPU time 28.38 seconds
Started Jun 09 12:28:53 PM PDT 24
Finished Jun 09 12:29:22 PM PDT 24
Peak memory 210788 kb
Host smart-5e8e6231-6773-4a6f-8ffd-8f15ce3abe41
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772603828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3772603828
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2811222064
Short name T415
Test name
Test status
Simulation time 5242510224 ps
CPU time 23.17 seconds
Started Jun 09 12:30:10 PM PDT 24
Finished Jun 09 12:30:34 PM PDT 24
Peak memory 210784 kb
Host smart-90e1549b-bd1a-412e-8840-17d614c121fe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811222064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2811222064
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.920137275
Short name T371
Test name
Test status
Simulation time 6722946360 ps
CPU time 79.25 seconds
Started Jun 09 12:28:54 PM PDT 24
Finished Jun 09 12:30:14 PM PDT 24
Peak memory 214772 kb
Host smart-6de8f60f-28e1-457e-a2eb-c1b17c288fb9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920137275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.920137275
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3132368178
Short name T360
Test name
Test status
Simulation time 5551241021 ps
CPU time 21.38 seconds
Started Jun 09 12:28:52 PM PDT 24
Finished Jun 09 12:29:14 PM PDT 24
Peak memory 218964 kb
Host smart-89e243b5-ddbb-4730-ada1-d858d880deb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132368178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3132368178
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1447130071
Short name T78
Test name
Test status
Simulation time 1403013124 ps
CPU time 16.86 seconds
Started Jun 09 12:29:00 PM PDT 24
Finished Jun 09 12:29:18 PM PDT 24
Peak memory 211432 kb
Host smart-84e07b1d-cc2d-4258-a6c2-13b1f8bdfa5d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447130071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1447130071
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1865304470
Short name T74
Test name
Test status
Simulation time 14788601374 ps
CPU time 18.35 seconds
Started Jun 09 12:30:17 PM PDT 24
Finished Jun 09 12:30:36 PM PDT 24
Peak memory 212356 kb
Host smart-c7fd7b22-87de-4a9c-9df8-273f9ad2fdbd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865304470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1865304470
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1262305955
Short name T377
Test name
Test status
Simulation time 2648441424 ps
CPU time 27.25 seconds
Started Jun 09 12:28:52 PM PDT 24
Finished Jun 09 12:29:20 PM PDT 24
Peak memory 210996 kb
Host smart-b47155af-fc90-4c58-8a2f-f996407a40f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262305955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1262305955
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3753636516
Short name T423
Test name
Test status
Simulation time 12057957444 ps
CPU time 25.14 seconds
Started Jun 09 12:28:58 PM PDT 24
Finished Jun 09 12:29:24 PM PDT 24
Peak memory 218592 kb
Host smart-71a7b44f-62e6-47e7-b963-8457c928d6b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753636516 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3753636516
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3094157494
Short name T394
Test name
Test status
Simulation time 216575064 ps
CPU time 8.3 seconds
Started Jun 09 12:28:56 PM PDT 24
Finished Jun 09 12:29:04 PM PDT 24
Peak memory 211336 kb
Host smart-bd411c5f-20bb-4c5c-9d15-253a34f942d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094157494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3094157494
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3387076919
Short name T444
Test name
Test status
Simulation time 174201935 ps
CPU time 8.07 seconds
Started Jun 09 12:28:54 PM PDT 24
Finished Jun 09 12:29:03 PM PDT 24
Peak memory 210668 kb
Host smart-a766f4d9-7872-4e28-b11b-f0cfec1ff38c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387076919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3387076919
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2020997238
Short name T368
Test name
Test status
Simulation time 4111866849 ps
CPU time 32.08 seconds
Started Jun 09 12:28:53 PM PDT 24
Finished Jun 09 12:29:31 PM PDT 24
Peak memory 210704 kb
Host smart-3870782f-5d28-4083-8918-ca6edfb43953
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020997238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2020997238
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2897299084
Short name T55
Test name
Test status
Simulation time 11299441148 ps
CPU time 98.36 seconds
Started Jun 09 12:28:56 PM PDT 24
Finished Jun 09 12:30:35 PM PDT 24
Peak memory 214112 kb
Host smart-1b9f1ae5-3559-4505-b0c8-6b2eb0c6e95a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897299084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2897299084
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2038981245
Short name T84
Test name
Test status
Simulation time 167563397 ps
CPU time 8.35 seconds
Started Jun 09 12:28:57 PM PDT 24
Finished Jun 09 12:29:06 PM PDT 24
Peak memory 211720 kb
Host smart-89733e8b-dffc-47a9-a654-47b3d899e82e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038981245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2038981245
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2524499049
Short name T427
Test name
Test status
Simulation time 635974666 ps
CPU time 12.97 seconds
Started Jun 09 12:28:53 PM PDT 24
Finished Jun 09 12:29:07 PM PDT 24
Peak memory 217712 kb
Host smart-ae2d8e75-7fff-4b9a-b691-b7c441121485
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524499049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2524499049
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1799897002
Short name T431
Test name
Test status
Simulation time 245511632 ps
CPU time 80.95 seconds
Started Jun 09 12:28:58 PM PDT 24
Finished Jun 09 12:30:20 PM PDT 24
Peak memory 213888 kb
Host smart-6be91508-dc20-4bb3-bea5-60fac0954290
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799897002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1799897002
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.885352926
Short name T451
Test name
Test status
Simulation time 2777561455 ps
CPU time 25.1 seconds
Started Jun 09 12:29:05 PM PDT 24
Finished Jun 09 12:29:30 PM PDT 24
Peak memory 216748 kb
Host smart-9b43ab4f-0a53-456c-a398-2458f5158261
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885352926 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.885352926
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.658586546
Short name T375
Test name
Test status
Simulation time 5115421415 ps
CPU time 17.45 seconds
Started Jun 09 12:29:03 PM PDT 24
Finished Jun 09 12:29:21 PM PDT 24
Peak memory 212464 kb
Host smart-1e10e3d3-9fa9-46ad-b35b-73247c0607f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658586546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.658586546
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2120992825
Short name T446
Test name
Test status
Simulation time 20596839745 ps
CPU time 69.59 seconds
Started Jun 09 12:29:04 PM PDT 24
Finished Jun 09 12:30:15 PM PDT 24
Peak memory 219156 kb
Host smart-2c218afe-d3e5-434e-88d1-60feedb30da3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120992825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2120992825
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2822849532
Short name T86
Test name
Test status
Simulation time 1706307663 ps
CPU time 11.26 seconds
Started Jun 09 12:29:01 PM PDT 24
Finished Jun 09 12:29:14 PM PDT 24
Peak memory 211312 kb
Host smart-366422c6-1385-4b68-bcc7-9c47f96ba9f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822849532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2822849532
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1030234539
Short name T363
Test name
Test status
Simulation time 4407831215 ps
CPU time 18.99 seconds
Started Jun 09 12:29:04 PM PDT 24
Finished Jun 09 12:29:24 PM PDT 24
Peak memory 218892 kb
Host smart-9a03e303-6e85-49fc-af8a-384e4396b904
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030234539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1030234539
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2423582647
Short name T406
Test name
Test status
Simulation time 4440250356 ps
CPU time 13.88 seconds
Started Jun 09 12:29:18 PM PDT 24
Finished Jun 09 12:29:33 PM PDT 24
Peak memory 217028 kb
Host smart-276d7d3a-13f9-442e-954c-0b833b3467e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423582647 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2423582647
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1967985049
Short name T412
Test name
Test status
Simulation time 1178690786 ps
CPU time 8.42 seconds
Started Jun 09 12:29:13 PM PDT 24
Finished Jun 09 12:29:22 PM PDT 24
Peak memory 211256 kb
Host smart-743cc052-f19e-4cad-990a-f97efa72b4ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967985049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1967985049
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2385772753
Short name T76
Test name
Test status
Simulation time 47626291412 ps
CPU time 88.37 seconds
Started Jun 09 12:29:06 PM PDT 24
Finished Jun 09 12:30:35 PM PDT 24
Peak memory 214108 kb
Host smart-6bc3c43c-d924-495d-af8b-01ed532136ab
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385772753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2385772753
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1824557150
Short name T83
Test name
Test status
Simulation time 176284964 ps
CPU time 8.27 seconds
Started Jun 09 12:29:27 PM PDT 24
Finished Jun 09 12:29:36 PM PDT 24
Peak memory 211716 kb
Host smart-3b1b5145-f487-4952-940d-f57375091877
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824557150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1824557150
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.510298357
Short name T374
Test name
Test status
Simulation time 2393237943 ps
CPU time 23.9 seconds
Started Jun 09 12:29:10 PM PDT 24
Finished Jun 09 12:29:34 PM PDT 24
Peak memory 218444 kb
Host smart-1b15bdc7-1c2d-4665-b77c-a67e08ec79e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510298357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.510298357
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2682673493
Short name T435
Test name
Test status
Simulation time 3027563570 ps
CPU time 18.2 seconds
Started Jun 09 12:29:16 PM PDT 24
Finished Jun 09 12:29:35 PM PDT 24
Peak memory 216156 kb
Host smart-e253a6e9-62d0-49a8-ae5e-4d4425296a7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682673493 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2682673493
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.4138326941
Short name T426
Test name
Test status
Simulation time 167532137 ps
CPU time 8.25 seconds
Started Jun 09 12:29:43 PM PDT 24
Finished Jun 09 12:29:52 PM PDT 24
Peak memory 210928 kb
Host smart-025832af-6dc5-4085-9061-5d4a5caa8e1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138326941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.4138326941
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1594432253
Short name T404
Test name
Test status
Simulation time 2080580669 ps
CPU time 37.18 seconds
Started Jun 09 12:29:17 PM PDT 24
Finished Jun 09 12:29:55 PM PDT 24
Peak memory 214100 kb
Host smart-ac126496-3bd3-451d-9ccd-ad8f31f59581
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594432253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1594432253
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3065629770
Short name T448
Test name
Test status
Simulation time 6911138077 ps
CPU time 28.68 seconds
Started Jun 09 12:29:08 PM PDT 24
Finished Jun 09 12:29:37 PM PDT 24
Peak memory 213204 kb
Host smart-f05467f2-6f2f-4dd4-94bd-2793159cb9cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065629770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3065629770
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3283099350
Short name T366
Test name
Test status
Simulation time 2809546623 ps
CPU time 29.63 seconds
Started Jun 09 12:29:30 PM PDT 24
Finished Jun 09 12:29:59 PM PDT 24
Peak memory 217500 kb
Host smart-61e51b3e-3a13-43e9-b5ec-9face2a05174
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283099350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3283099350
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3552252396
Short name T401
Test name
Test status
Simulation time 699584990 ps
CPU time 8.59 seconds
Started Jun 09 12:29:15 PM PDT 24
Finished Jun 09 12:29:24 PM PDT 24
Peak memory 215716 kb
Host smart-3ed47e72-eefa-4cc4-8bd9-65bbcfc288a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552252396 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3552252396
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1667740240
Short name T449
Test name
Test status
Simulation time 2354531903 ps
CPU time 8.25 seconds
Started Jun 09 12:29:31 PM PDT 24
Finished Jun 09 12:29:40 PM PDT 24
Peak memory 211308 kb
Host smart-c3bb4b06-38ee-43ef-96aa-7261b660e20a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667740240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1667740240
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3612053823
Short name T66
Test name
Test status
Simulation time 10526538500 ps
CPU time 70.87 seconds
Started Jun 09 12:29:21 PM PDT 24
Finished Jun 09 12:30:32 PM PDT 24
Peak memory 214136 kb
Host smart-882565ce-cdc5-4c5e-b34c-9077a1c44810
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612053823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3612053823
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.827558689
Short name T413
Test name
Test status
Simulation time 497396418 ps
CPU time 9.84 seconds
Started Jun 09 12:29:09 PM PDT 24
Finished Jun 09 12:29:19 PM PDT 24
Peak memory 211328 kb
Host smart-96dad13d-5e76-49f4-a9e8-96ad3b622725
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827558689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.827558689
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.22095782
Short name T398
Test name
Test status
Simulation time 3497191246 ps
CPU time 31.46 seconds
Started Jun 09 12:29:09 PM PDT 24
Finished Jun 09 12:29:40 PM PDT 24
Peak memory 218556 kb
Host smart-d3c414eb-9499-4325-9f39-099c61790539
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22095782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.22095782
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1448316749
Short name T100
Test name
Test status
Simulation time 4067072424 ps
CPU time 104.9 seconds
Started Jun 09 12:29:27 PM PDT 24
Finished Jun 09 12:31:13 PM PDT 24
Peak memory 213804 kb
Host smart-32bbc2a3-872d-4bc5-86ec-f97dab4337cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448316749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1448316749
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1466439372
Short name T420
Test name
Test status
Simulation time 1500648015 ps
CPU time 18.25 seconds
Started Jun 09 12:29:29 PM PDT 24
Finished Jun 09 12:29:47 PM PDT 24
Peak memory 216900 kb
Host smart-7c84a46f-2923-46ca-bd86-ee1f62c0b91f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466439372 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1466439372
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.138356245
Short name T382
Test name
Test status
Simulation time 37640080791 ps
CPU time 24.79 seconds
Started Jun 09 12:29:28 PM PDT 24
Finished Jun 09 12:29:53 PM PDT 24
Peak memory 212288 kb
Host smart-b914adcd-c413-45ad-9f2d-5f66b0259609
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138356245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.138356245
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2526177368
Short name T56
Test name
Test status
Simulation time 6663872129 ps
CPU time 76.43 seconds
Started Jun 09 12:29:18 PM PDT 24
Finished Jun 09 12:30:35 PM PDT 24
Peak memory 214792 kb
Host smart-123e3a6f-2903-4a84-b163-1b5e473fa257
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526177368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2526177368
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1508308566
Short name T440
Test name
Test status
Simulation time 2534730481 ps
CPU time 23.2 seconds
Started Jun 09 12:29:22 PM PDT 24
Finished Jun 09 12:29:45 PM PDT 24
Peak memory 212640 kb
Host smart-ca93e7b4-0a8a-4c8b-859e-421e7482f345
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508308566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1508308566
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1420211790
Short name T367
Test name
Test status
Simulation time 7627509848 ps
CPU time 20.13 seconds
Started Jun 09 12:29:17 PM PDT 24
Finished Jun 09 12:29:37 PM PDT 24
Peak memory 218808 kb
Host smart-10350dbd-0c5e-4647-8e32-45223392ea9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420211790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1420211790
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.285135068
Short name T400
Test name
Test status
Simulation time 840355398 ps
CPU time 81.65 seconds
Started Jun 09 12:29:29 PM PDT 24
Finished Jun 09 12:30:51 PM PDT 24
Peak memory 213724 kb
Host smart-301909d7-1df3-4a7a-9aa4-ce07b71d5a63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285135068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.285135068
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2568519513
Short name T411
Test name
Test status
Simulation time 2731489408 ps
CPU time 24.35 seconds
Started Jun 09 12:29:06 PM PDT 24
Finished Jun 09 12:29:31 PM PDT 24
Peak memory 217964 kb
Host smart-c01110f9-3cf9-49b4-8b88-7d5ef6913f23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568519513 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2568519513
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.140682417
Short name T381
Test name
Test status
Simulation time 1649434789 ps
CPU time 10.97 seconds
Started Jun 09 12:29:09 PM PDT 24
Finished Jun 09 12:29:20 PM PDT 24
Peak memory 211012 kb
Host smart-a20916c3-bb26-4448-9959-44091827a112
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140682417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.140682417
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4158771940
Short name T458
Test name
Test status
Simulation time 2016824334 ps
CPU time 72.2 seconds
Started Jun 09 12:29:11 PM PDT 24
Finished Jun 09 12:30:24 PM PDT 24
Peak memory 215152 kb
Host smart-6a522893-a3b2-4ca3-93e4-6576cc57adc8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158771940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.4158771940
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.8835358
Short name T424
Test name
Test status
Simulation time 171034976 ps
CPU time 8.25 seconds
Started Jun 09 12:29:09 PM PDT 24
Finished Jun 09 12:29:18 PM PDT 24
Peak memory 211356 kb
Host smart-9c5d6c4d-1458-400c-be64-b9be3cc1fdd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8835358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctr
l_same_csr_outstanding.8835358
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.900410972
Short name T436
Test name
Test status
Simulation time 3926720162 ps
CPU time 24.95 seconds
Started Jun 09 12:29:16 PM PDT 24
Finished Jun 09 12:29:41 PM PDT 24
Peak memory 218660 kb
Host smart-f7829cc3-a395-43e9-a58c-2516abddc8c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900410972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.900410972
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.511262983
Short name T106
Test name
Test status
Simulation time 229763125 ps
CPU time 79.23 seconds
Started Jun 09 12:29:06 PM PDT 24
Finished Jun 09 12:30:26 PM PDT 24
Peak memory 213936 kb
Host smart-2b96a67d-0414-4427-8f59-4b6d3d4adb87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511262983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.511262983
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2083321423
Short name T395
Test name
Test status
Simulation time 4032979074 ps
CPU time 30.29 seconds
Started Jun 09 12:29:18 PM PDT 24
Finished Jun 09 12:29:48 PM PDT 24
Peak memory 219152 kb
Host smart-bfd5c79f-494b-4fc9-a839-febd245dd8c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083321423 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2083321423
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.80036580
Short name T418
Test name
Test status
Simulation time 2609740249 ps
CPU time 23.35 seconds
Started Jun 09 12:29:26 PM PDT 24
Finished Jun 09 12:29:49 PM PDT 24
Peak memory 212152 kb
Host smart-73871366-c358-4156-adb1-57be23b6442f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80036580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.80036580
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1498423394
Short name T417
Test name
Test status
Simulation time 65714913623 ps
CPU time 137.81 seconds
Started Jun 09 12:29:22 PM PDT 24
Finished Jun 09 12:31:40 PM PDT 24
Peak memory 214160 kb
Host smart-b232b6f2-1dbe-4149-9336-25eb5dee4367
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498423394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1498423394
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3477917169
Short name T453
Test name
Test status
Simulation time 11549853187 ps
CPU time 25.78 seconds
Started Jun 09 12:29:15 PM PDT 24
Finished Jun 09 12:29:41 PM PDT 24
Peak memory 212968 kb
Host smart-065659a4-2b58-4d69-9dd0-933b42f24e48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477917169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3477917169
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3241743291
Short name T51
Test name
Test status
Simulation time 3354523850 ps
CPU time 84.23 seconds
Started Jun 09 12:29:14 PM PDT 24
Finished Jun 09 12:30:43 PM PDT 24
Peak memory 213844 kb
Host smart-c82efb2b-8a65-4357-8a51-04632a7093eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241743291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3241743291
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3342276630
Short name T370
Test name
Test status
Simulation time 666497066 ps
CPU time 13.19 seconds
Started Jun 09 12:29:30 PM PDT 24
Finished Jun 09 12:29:44 PM PDT 24
Peak memory 215320 kb
Host smart-be9a6518-bcdf-4246-9efa-ab34bae18f9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342276630 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3342276630
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4250629212
Short name T384
Test name
Test status
Simulation time 8526828297 ps
CPU time 19.76 seconds
Started Jun 09 12:29:36 PM PDT 24
Finished Jun 09 12:29:56 PM PDT 24
Peak memory 212380 kb
Host smart-ab398c71-4d2d-4be9-8a5f-e55919bf26f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250629212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.4250629212
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2569501801
Short name T397
Test name
Test status
Simulation time 44129638655 ps
CPU time 154.78 seconds
Started Jun 09 12:29:21 PM PDT 24
Finished Jun 09 12:31:56 PM PDT 24
Peak memory 215352 kb
Host smart-416c74ef-20bd-4b05-ba68-9378f081e618
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569501801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2569501801
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.808511855
Short name T85
Test name
Test status
Simulation time 7346218714 ps
CPU time 21.29 seconds
Started Jun 09 12:29:14 PM PDT 24
Finished Jun 09 12:29:35 PM PDT 24
Peak memory 213036 kb
Host smart-50c5ddc1-89a1-461b-8cc7-111d382034e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808511855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.808511855
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1317780836
Short name T362
Test name
Test status
Simulation time 9201529769 ps
CPU time 21.09 seconds
Started Jun 09 12:29:08 PM PDT 24
Finished Jun 09 12:29:29 PM PDT 24
Peak memory 218604 kb
Host smart-0316dffc-cb2d-4101-9954-9b7b77454d40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317780836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1317780836
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4069692521
Short name T419
Test name
Test status
Simulation time 14845047837 ps
CPU time 172.88 seconds
Started Jun 09 12:29:25 PM PDT 24
Finished Jun 09 12:32:19 PM PDT 24
Peak memory 213332 kb
Host smart-a1bd8b0b-33e3-4103-aad4-e1dc41cdb6a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069692521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.4069692521
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3777842328
Short name T393
Test name
Test status
Simulation time 173860614 ps
CPU time 8.62 seconds
Started Jun 09 12:29:27 PM PDT 24
Finished Jun 09 12:29:36 PM PDT 24
Peak memory 215140 kb
Host smart-110caa63-4f0e-457a-8f0c-67a23f5cfb40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777842328 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3777842328
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1455983034
Short name T432
Test name
Test status
Simulation time 3055520962 ps
CPU time 25.9 seconds
Started Jun 09 12:29:25 PM PDT 24
Finished Jun 09 12:29:52 PM PDT 24
Peak memory 212060 kb
Host smart-d3d78e40-8440-4310-8e67-82a565edb1b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455983034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1455983034
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3749405596
Short name T82
Test name
Test status
Simulation time 3394739819 ps
CPU time 31.3 seconds
Started Jun 09 12:29:20 PM PDT 24
Finished Jun 09 12:29:52 PM PDT 24
Peak memory 212832 kb
Host smart-109dd877-2354-494f-bfec-6756b07a6e2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749405596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3749405596
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2116750647
Short name T457
Test name
Test status
Simulation time 4725299362 ps
CPU time 26.34 seconds
Started Jun 09 12:29:12 PM PDT 24
Finished Jun 09 12:29:39 PM PDT 24
Peak memory 218492 kb
Host smart-ff4d76af-4cb9-4ce8-8fb6-256d25c0fd5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116750647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2116750647
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.537156033
Short name T99
Test name
Test status
Simulation time 4435006609 ps
CPU time 86.06 seconds
Started Jun 09 12:29:05 PM PDT 24
Finished Jun 09 12:30:32 PM PDT 24
Peak memory 213764 kb
Host smart-c633a12e-69ad-43b8-9d69-b7fc5aac8b70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537156033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.537156033
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.673651334
Short name T365
Test name
Test status
Simulation time 10572660287 ps
CPU time 23.49 seconds
Started Jun 09 12:29:27 PM PDT 24
Finished Jun 09 12:29:51 PM PDT 24
Peak memory 219152 kb
Host smart-0ca48cda-21b5-43c7-928d-3af3fab6c487
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673651334 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.673651334
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3404282651
Short name T79
Test name
Test status
Simulation time 17662803517 ps
CPU time 31.02 seconds
Started Jun 09 12:29:27 PM PDT 24
Finished Jun 09 12:29:58 PM PDT 24
Peak memory 212644 kb
Host smart-f79e3b63-8f08-412e-9735-ba0a1c849edf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404282651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3404282651
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2030292922
Short name T88
Test name
Test status
Simulation time 28232558340 ps
CPU time 142.98 seconds
Started Jun 09 12:29:23 PM PDT 24
Finished Jun 09 12:31:46 PM PDT 24
Peak memory 215528 kb
Host smart-afebb0ca-c2bf-45a3-8328-189ccbfe6d73
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030292922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2030292922
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1102739627
Short name T385
Test name
Test status
Simulation time 11985066420 ps
CPU time 29.78 seconds
Started Jun 09 12:29:20 PM PDT 24
Finished Jun 09 12:29:51 PM PDT 24
Peak memory 212792 kb
Host smart-d720b0aa-c9bf-4e49-ab91-f85ec3c609a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102739627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1102739627
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2771097140
Short name T378
Test name
Test status
Simulation time 12970005661 ps
CPU time 31.62 seconds
Started Jun 09 12:29:28 PM PDT 24
Finished Jun 09 12:30:00 PM PDT 24
Peak memory 217756 kb
Host smart-0eb1b480-5df1-43e0-bc52-946ef12649f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771097140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2771097140
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1153837822
Short name T434
Test name
Test status
Simulation time 363926961 ps
CPU time 82.81 seconds
Started Jun 09 12:29:29 PM PDT 24
Finished Jun 09 12:30:52 PM PDT 24
Peak memory 214860 kb
Host smart-26bba984-486e-4683-8a2b-af846186cea0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153837822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1153837822
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.625508714
Short name T383
Test name
Test status
Simulation time 9178260197 ps
CPU time 21.72 seconds
Started Jun 09 12:29:07 PM PDT 24
Finished Jun 09 12:29:29 PM PDT 24
Peak memory 211960 kb
Host smart-3fca731e-4ad9-4421-8892-55a3fc92bbab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625508714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.625508714
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2485347826
Short name T452
Test name
Test status
Simulation time 1268373548 ps
CPU time 8.06 seconds
Started Jun 09 12:29:07 PM PDT 24
Finished Jun 09 12:29:20 PM PDT 24
Peak memory 210960 kb
Host smart-7a730b26-23fe-4e75-b6cc-b45423b2883b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485347826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2485347826
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.357586814
Short name T380
Test name
Test status
Simulation time 672544823 ps
CPU time 11.54 seconds
Started Jun 09 12:29:07 PM PDT 24
Finished Jun 09 12:29:19 PM PDT 24
Peak memory 210956 kb
Host smart-8f499021-f787-42bc-a029-a7f9c896b8c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357586814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.357586814
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1575488957
Short name T460
Test name
Test status
Simulation time 15701181528 ps
CPU time 30.38 seconds
Started Jun 09 12:29:00 PM PDT 24
Finished Jun 09 12:29:31 PM PDT 24
Peak memory 218044 kb
Host smart-c1edf7b4-316e-402c-8ef2-83642d56f6e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575488957 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1575488957
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3381649317
Short name T403
Test name
Test status
Simulation time 8190553221 ps
CPU time 32.39 seconds
Started Jun 09 12:28:58 PM PDT 24
Finished Jun 09 12:29:31 PM PDT 24
Peak memory 212244 kb
Host smart-d8d7a58f-a6f8-4ce6-abd2-ccf1221979c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381649317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3381649317
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1310735137
Short name T442
Test name
Test status
Simulation time 829303368 ps
CPU time 11.08 seconds
Started Jun 09 12:28:59 PM PDT 24
Finished Jun 09 12:29:10 PM PDT 24
Peak memory 210644 kb
Host smart-85218934-138e-446a-b52a-2d538fe5abed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310735137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1310735137
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.307641943
Short name T388
Test name
Test status
Simulation time 2139907736 ps
CPU time 11.93 seconds
Started Jun 09 12:28:58 PM PDT 24
Finished Jun 09 12:29:11 PM PDT 24
Peak memory 210676 kb
Host smart-3382517b-4d2d-4751-97ed-0886b2b8c013
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307641943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
307641943
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1234597282
Short name T80
Test name
Test status
Simulation time 37423996050 ps
CPU time 189.81 seconds
Started Jun 09 12:29:01 PM PDT 24
Finished Jun 09 12:32:12 PM PDT 24
Peak memory 215488 kb
Host smart-f6b470c8-d4ce-4da1-8b9c-1105d0330674
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234597282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1234597282
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.750984621
Short name T65
Test name
Test status
Simulation time 252107039 ps
CPU time 8.61 seconds
Started Jun 09 12:28:56 PM PDT 24
Finished Jun 09 12:29:06 PM PDT 24
Peak memory 211848 kb
Host smart-f0ca82d7-272b-4a84-9b64-ceba40b52a67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750984621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.750984621
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3354066888
Short name T443
Test name
Test status
Simulation time 750108217 ps
CPU time 11.16 seconds
Started Jun 09 12:28:57 PM PDT 24
Finished Jun 09 12:29:09 PM PDT 24
Peak memory 217340 kb
Host smart-aa397fec-28c0-4246-acf0-77926f75073a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354066888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3354066888
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3985667316
Short name T103
Test name
Test status
Simulation time 262976472 ps
CPU time 82.68 seconds
Started Jun 09 12:28:56 PM PDT 24
Finished Jun 09 12:30:19 PM PDT 24
Peak memory 214992 kb
Host smart-b0057d28-28f9-48db-98e2-333a6a0c64a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985667316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3985667316
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1818586031
Short name T396
Test name
Test status
Simulation time 5974390895 ps
CPU time 13.1 seconds
Started Jun 09 12:28:58 PM PDT 24
Finished Jun 09 12:29:12 PM PDT 24
Peak memory 211428 kb
Host smart-d0707f0e-9e84-4f38-9a5d-7a740cdae4e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818586031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1818586031
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.996358127
Short name T391
Test name
Test status
Simulation time 167660307 ps
CPU time 8.46 seconds
Started Jun 09 12:29:01 PM PDT 24
Finished Jun 09 12:29:11 PM PDT 24
Peak memory 210936 kb
Host smart-ce0ec8b8-8d40-44c0-897a-082995fdd22b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996358127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.996358127
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2976617599
Short name T81
Test name
Test status
Simulation time 21150312366 ps
CPU time 27.11 seconds
Started Jun 09 12:28:55 PM PDT 24
Finished Jun 09 12:29:23 PM PDT 24
Peak memory 212304 kb
Host smart-91d9ef02-ca4b-4e5d-8b3b-d94381268e0e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976617599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2976617599
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2857902572
Short name T387
Test name
Test status
Simulation time 4833759349 ps
CPU time 21.59 seconds
Started Jun 09 12:29:07 PM PDT 24
Finished Jun 09 12:29:29 PM PDT 24
Peak memory 216540 kb
Host smart-2688b18d-8581-4148-a5e9-2b0358702a3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857902572 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2857902572
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.639064673
Short name T372
Test name
Test status
Simulation time 1267467825 ps
CPU time 8.13 seconds
Started Jun 09 12:28:59 PM PDT 24
Finished Jun 09 12:29:08 PM PDT 24
Peak memory 211116 kb
Host smart-c2b84cc7-66d5-4b09-a7b6-a6a22758033d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639064673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.639064673
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1503701266
Short name T437
Test name
Test status
Simulation time 4270077425 ps
CPU time 31.25 seconds
Started Jun 09 12:29:04 PM PDT 24
Finished Jun 09 12:29:36 PM PDT 24
Peak memory 210756 kb
Host smart-0ca42101-d4d3-4348-a936-8bd14acc11a1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503701266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1503701266
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.144401037
Short name T402
Test name
Test status
Simulation time 1252213558 ps
CPU time 15.69 seconds
Started Jun 09 12:28:59 PM PDT 24
Finished Jun 09 12:29:16 PM PDT 24
Peak memory 210700 kb
Host smart-9a2f0171-f678-470f-973c-ed87a603e600
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144401037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
144401037
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3867165612
Short name T447
Test name
Test status
Simulation time 3082279481 ps
CPU time 26.05 seconds
Started Jun 09 12:28:56 PM PDT 24
Finished Jun 09 12:29:23 PM PDT 24
Peak memory 212480 kb
Host smart-9a3b7ce7-dcca-43c7-ba58-d0b2498bd4dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867165612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3867165612
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.579497042
Short name T422
Test name
Test status
Simulation time 3333968189 ps
CPU time 32.2 seconds
Started Jun 09 12:29:00 PM PDT 24
Finished Jun 09 12:29:33 PM PDT 24
Peak memory 217676 kb
Host smart-bec19af2-9fc2-4995-a023-1b3bc0741965
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579497042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.579497042
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1968073211
Short name T105
Test name
Test status
Simulation time 670487925 ps
CPU time 85.06 seconds
Started Jun 09 12:28:57 PM PDT 24
Finished Jun 09 12:30:23 PM PDT 24
Peak memory 213636 kb
Host smart-524fad1d-cec0-4904-af4c-11b3aa99065a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968073211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1968073211
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1826732428
Short name T75
Test name
Test status
Simulation time 14273763972 ps
CPU time 31.25 seconds
Started Jun 09 12:28:58 PM PDT 24
Finished Jun 09 12:29:30 PM PDT 24
Peak memory 212476 kb
Host smart-45f1d5d6-c300-4313-b727-637cc1efebfb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826732428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1826732428
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1056278187
Short name T416
Test name
Test status
Simulation time 169373822 ps
CPU time 8.59 seconds
Started Jun 09 12:28:59 PM PDT 24
Finished Jun 09 12:29:08 PM PDT 24
Peak memory 210996 kb
Host smart-a38697ae-9775-4adc-9eb3-f0cb70aa0130
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056278187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1056278187
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4263137961
Short name T441
Test name
Test status
Simulation time 761580674 ps
CPU time 11.47 seconds
Started Jun 09 12:29:01 PM PDT 24
Finished Jun 09 12:29:13 PM PDT 24
Peak memory 210872 kb
Host smart-fa368ef8-e9bf-44a4-89c6-e9864d5eea6a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263137961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4263137961
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.624185045
Short name T376
Test name
Test status
Simulation time 181679800 ps
CPU time 8.51 seconds
Started Jun 09 12:29:01 PM PDT 24
Finished Jun 09 12:29:11 PM PDT 24
Peak memory 214324 kb
Host smart-faebf988-c7e7-48bb-8f77-777b65d41c7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624185045 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.624185045
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1426613248
Short name T89
Test name
Test status
Simulation time 10493830776 ps
CPU time 24.63 seconds
Started Jun 09 12:29:03 PM PDT 24
Finished Jun 09 12:29:28 PM PDT 24
Peak memory 212520 kb
Host smart-b4519401-9dff-4db2-86ac-7c6e433298c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426613248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1426613248
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2742126896
Short name T409
Test name
Test status
Simulation time 31899928906 ps
CPU time 23.98 seconds
Started Jun 09 12:29:00 PM PDT 24
Finished Jun 09 12:29:24 PM PDT 24
Peak memory 210408 kb
Host smart-ac5ca69b-563a-450f-a9c9-711731e9b06a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742126896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2742126896
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1935242140
Short name T373
Test name
Test status
Simulation time 2951604862 ps
CPU time 18.84 seconds
Started Jun 09 12:28:54 PM PDT 24
Finished Jun 09 12:29:13 PM PDT 24
Peak memory 210680 kb
Host smart-ffeea3a6-b376-49c0-a3eb-b5a202797494
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935242140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1935242140
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1427103738
Short name T77
Test name
Test status
Simulation time 12058994133 ps
CPU time 106.31 seconds
Started Jun 09 12:28:58 PM PDT 24
Finished Jun 09 12:30:44 PM PDT 24
Peak memory 214160 kb
Host smart-87e6f6f5-dbe8-402c-9af3-905a033819fc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427103738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1427103738
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3816271050
Short name T428
Test name
Test status
Simulation time 579125084 ps
CPU time 13.03 seconds
Started Jun 09 12:28:57 PM PDT 24
Finished Jun 09 12:29:11 PM PDT 24
Peak memory 211320 kb
Host smart-1a835c40-4c54-4760-bc59-e08c2e51bccf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816271050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3816271050
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2695275199
Short name T390
Test name
Test status
Simulation time 2157154590 ps
CPU time 17.39 seconds
Started Jun 09 12:29:04 PM PDT 24
Finished Jun 09 12:29:22 PM PDT 24
Peak memory 218468 kb
Host smart-102499d1-d65e-408e-b1e8-c5edc986ff6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695275199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2695275199
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3707671505
Short name T405
Test name
Test status
Simulation time 2872514024 ps
CPU time 168.93 seconds
Started Jun 09 12:28:59 PM PDT 24
Finished Jun 09 12:31:48 PM PDT 24
Peak memory 214244 kb
Host smart-e425912f-21fd-440b-b30f-dd28caa1b632
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707671505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3707671505
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2809561644
Short name T399
Test name
Test status
Simulation time 4494124351 ps
CPU time 14.99 seconds
Started Jun 09 12:29:03 PM PDT 24
Finished Jun 09 12:29:19 PM PDT 24
Peak memory 217456 kb
Host smart-222995aa-0f31-479c-b210-de0ae866e0a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809561644 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2809561644
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2418797826
Short name T429
Test name
Test status
Simulation time 3225659764 ps
CPU time 25.79 seconds
Started Jun 09 12:28:59 PM PDT 24
Finished Jun 09 12:29:25 PM PDT 24
Peak memory 212036 kb
Host smart-8a006a6a-2947-4771-a03d-e6999f8a4239
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418797826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2418797826
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4237920029
Short name T410
Test name
Test status
Simulation time 87749645296 ps
CPU time 177.3 seconds
Started Jun 09 12:28:57 PM PDT 24
Finished Jun 09 12:31:55 PM PDT 24
Peak memory 215068 kb
Host smart-eb5482fc-19dc-4c6f-9573-365695fcd6d8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237920029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4237920029
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2565519625
Short name T438
Test name
Test status
Simulation time 1827497200 ps
CPU time 14.55 seconds
Started Jun 09 12:29:00 PM PDT 24
Finished Jun 09 12:29:15 PM PDT 24
Peak memory 212544 kb
Host smart-9a4d777a-277f-48e4-8498-a73f6f58e607
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565519625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2565519625
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.547918731
Short name T364
Test name
Test status
Simulation time 4440717502 ps
CPU time 20.07 seconds
Started Jun 09 12:29:02 PM PDT 24
Finished Jun 09 12:29:23 PM PDT 24
Peak memory 218792 kb
Host smart-b8d56e5f-0dbd-4956-909c-fdbc2ff1cf52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547918731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.547918731
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1909585424
Short name T107
Test name
Test status
Simulation time 2448603048 ps
CPU time 167.47 seconds
Started Jun 09 12:28:57 PM PDT 24
Finished Jun 09 12:31:45 PM PDT 24
Peak memory 214160 kb
Host smart-5172435b-1d6f-42bd-9793-3cb7868f31aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909585424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1909585424
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1953640381
Short name T369
Test name
Test status
Simulation time 2680123406 ps
CPU time 17.38 seconds
Started Jun 09 12:29:00 PM PDT 24
Finished Jun 09 12:29:18 PM PDT 24
Peak memory 216088 kb
Host smart-74cb7f14-b9c1-4875-910c-e13d57a50e90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953640381 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1953640381
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1468181230
Short name T445
Test name
Test status
Simulation time 25254995607 ps
CPU time 23.53 seconds
Started Jun 09 12:28:56 PM PDT 24
Finished Jun 09 12:29:20 PM PDT 24
Peak memory 212464 kb
Host smart-fd34227d-59b3-4213-9fbc-93cbb8de6d86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468181230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1468181230
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1992875950
Short name T62
Test name
Test status
Simulation time 13464245883 ps
CPU time 117.16 seconds
Started Jun 09 12:28:56 PM PDT 24
Finished Jun 09 12:30:55 PM PDT 24
Peak memory 214140 kb
Host smart-4db6f99b-86a8-47ad-8684-ac43fae1d183
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992875950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1992875950
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1208254020
Short name T407
Test name
Test status
Simulation time 3650543736 ps
CPU time 28.72 seconds
Started Jun 09 12:29:02 PM PDT 24
Finished Jun 09 12:29:32 PM PDT 24
Peak memory 212292 kb
Host smart-264e453d-1172-4c2d-be67-208f5acf2ecb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208254020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1208254020
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1629475307
Short name T439
Test name
Test status
Simulation time 222702731 ps
CPU time 12.65 seconds
Started Jun 09 12:29:01 PM PDT 24
Finished Jun 09 12:29:15 PM PDT 24
Peak memory 217392 kb
Host smart-33492671-5774-48d0-b639-20634daf649e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629475307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1629475307
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2833530153
Short name T98
Test name
Test status
Simulation time 1194462529 ps
CPU time 154.82 seconds
Started Jun 09 12:29:00 PM PDT 24
Finished Jun 09 12:31:36 PM PDT 24
Peak memory 214016 kb
Host smart-39aad84e-a3eb-4d07-b12a-2b6af26a6f1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833530153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2833530153
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1431298853
Short name T455
Test name
Test status
Simulation time 3449007944 ps
CPU time 18.96 seconds
Started Jun 09 12:29:02 PM PDT 24
Finished Jun 09 12:29:21 PM PDT 24
Peak memory 219132 kb
Host smart-d7034e39-07e7-4b88-992a-c857966db472
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431298853 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1431298853
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1542742560
Short name T72
Test name
Test status
Simulation time 22676608208 ps
CPU time 29.62 seconds
Started Jun 09 12:29:03 PM PDT 24
Finished Jun 09 12:29:34 PM PDT 24
Peak memory 212320 kb
Host smart-fddabc10-1093-4e2b-8bb0-562701c6e92c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542742560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1542742560
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1066118928
Short name T54
Test name
Test status
Simulation time 17198071491 ps
CPU time 137.05 seconds
Started Jun 09 12:29:02 PM PDT 24
Finished Jun 09 12:31:20 PM PDT 24
Peak memory 211920 kb
Host smart-530b2ba5-aad0-42cf-aec2-a9a6ff39a466
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066118928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1066118928
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2993975099
Short name T60
Test name
Test status
Simulation time 4157532138 ps
CPU time 31.81 seconds
Started Jun 09 12:29:03 PM PDT 24
Finished Jun 09 12:29:35 PM PDT 24
Peak memory 212372 kb
Host smart-28df6149-e981-420a-8aac-167ef076c6dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993975099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2993975099
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1780840575
Short name T361
Test name
Test status
Simulation time 982229055 ps
CPU time 15.59 seconds
Started Jun 09 12:29:01 PM PDT 24
Finished Jun 09 12:29:18 PM PDT 24
Peak memory 217496 kb
Host smart-01662775-d0c9-4b93-b02f-2c8196a20090
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780840575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1780840575
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1018883977
Short name T104
Test name
Test status
Simulation time 7514230702 ps
CPU time 173.35 seconds
Started Jun 09 12:29:03 PM PDT 24
Finished Jun 09 12:31:58 PM PDT 24
Peak memory 219164 kb
Host smart-a59317d4-19bc-43e2-b749-8b20719434b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018883977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1018883977
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1714331765
Short name T379
Test name
Test status
Simulation time 11598549477 ps
CPU time 26.11 seconds
Started Jun 09 12:29:06 PM PDT 24
Finished Jun 09 12:29:32 PM PDT 24
Peak memory 218064 kb
Host smart-3bd4ec14-fe65-4b65-8f22-d49fb23aeb0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714331765 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1714331765
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.924303422
Short name T73
Test name
Test status
Simulation time 6803958925 ps
CPU time 19 seconds
Started Jun 09 12:29:01 PM PDT 24
Finished Jun 09 12:29:21 PM PDT 24
Peak memory 212748 kb
Host smart-c8b77809-2dd8-42f6-b07c-6bf93dfe0f5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924303422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.924303422
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.4259124690
Short name T430
Test name
Test status
Simulation time 4501560551 ps
CPU time 59.12 seconds
Started Jun 09 12:29:06 PM PDT 24
Finished Jun 09 12:30:06 PM PDT 24
Peak memory 219156 kb
Host smart-ef7d470f-aaa7-4101-a422-b60e87c8ddb1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259124690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.4259124690
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2213869948
Short name T87
Test name
Test status
Simulation time 338359369 ps
CPU time 8.42 seconds
Started Jun 09 12:29:05 PM PDT 24
Finished Jun 09 12:29:14 PM PDT 24
Peak memory 211608 kb
Host smart-38aeda25-c843-4cba-b959-09a4b36e5cc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213869948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2213869948
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2567334444
Short name T392
Test name
Test status
Simulation time 11177731708 ps
CPU time 28.59 seconds
Started Jun 09 12:29:03 PM PDT 24
Finished Jun 09 12:29:33 PM PDT 24
Peak memory 217896 kb
Host smart-9c69129d-2f15-4b3c-ac16-fc33481e5dbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567334444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2567334444
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.84730032
Short name T53
Test name
Test status
Simulation time 2700579744 ps
CPU time 162.59 seconds
Started Jun 09 12:29:02 PM PDT 24
Finished Jun 09 12:31:45 PM PDT 24
Peak memory 219172 kb
Host smart-458ba7ed-ce2f-424e-9177-1625235bf690
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84730032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg
_err.84730032
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.682916694
Short name T389
Test name
Test status
Simulation time 2333397085 ps
CPU time 22.04 seconds
Started Jun 09 12:29:04 PM PDT 24
Finished Jun 09 12:29:27 PM PDT 24
Peak memory 219160 kb
Host smart-ba540249-1048-45f7-b6d0-ad145ba8d48c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682916694 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.682916694
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4116261735
Short name T63
Test name
Test status
Simulation time 3032658141 ps
CPU time 26.27 seconds
Started Jun 09 12:29:03 PM PDT 24
Finished Jun 09 12:29:30 PM PDT 24
Peak memory 211592 kb
Host smart-fff2c2b0-79d1-480b-a37a-2990b40370cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116261735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.4116261735
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3381463577
Short name T459
Test name
Test status
Simulation time 20026616207 ps
CPU time 166.86 seconds
Started Jun 09 12:29:02 PM PDT 24
Finished Jun 09 12:31:50 PM PDT 24
Peak memory 215548 kb
Host smart-d63f93f4-b2c0-46b7-be51-0cae16f306e1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381463577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3381463577
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3579298720
Short name T414
Test name
Test status
Simulation time 175310208 ps
CPU time 12.04 seconds
Started Jun 09 12:29:02 PM PDT 24
Finished Jun 09 12:29:15 PM PDT 24
Peak memory 212832 kb
Host smart-33d54914-2450-4c22-9445-1c2ffd5b033b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579298720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3579298720
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1895545064
Short name T454
Test name
Test status
Simulation time 12106359194 ps
CPU time 32.25 seconds
Started Jun 09 12:29:03 PM PDT 24
Finished Jun 09 12:29:36 PM PDT 24
Peak memory 219032 kb
Host smart-205407ca-4a95-44cb-a8e9-abca8bf3090f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895545064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1895545064
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3627614026
Short name T425
Test name
Test status
Simulation time 3672167647 ps
CPU time 170.41 seconds
Started Jun 09 12:29:02 PM PDT 24
Finished Jun 09 12:31:53 PM PDT 24
Peak memory 214364 kb
Host smart-f8df5059-f703-4ffc-8aaa-2c7048d23e27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627614026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3627614026
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2180774440
Short name T336
Test name
Test status
Simulation time 5583531909 ps
CPU time 25.96 seconds
Started Jun 09 01:05:57 PM PDT 24
Finished Jun 09 01:06:24 PM PDT 24
Peak memory 217080 kb
Host smart-badf596c-6170-4487-9c74-d2d794b8e76f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180774440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2180774440
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.712887640
Short name T205
Test name
Test status
Simulation time 6694116407 ps
CPU time 228.71 seconds
Started Jun 09 01:06:00 PM PDT 24
Finished Jun 09 01:09:49 PM PDT 24
Peak memory 225984 kb
Host smart-93f0414c-4284-4187-aab9-670dbc230e90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712887640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.712887640
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.936945644
Short name T228
Test name
Test status
Simulation time 1322344764 ps
CPU time 19.35 seconds
Started Jun 09 01:05:57 PM PDT 24
Finished Jun 09 01:06:17 PM PDT 24
Peak memory 218944 kb
Host smart-d3c05795-f353-419c-b299-1032357aca98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936945644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.936945644
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1760383241
Short name T302
Test name
Test status
Simulation time 1030738353 ps
CPU time 10.6 seconds
Started Jun 09 01:05:56 PM PDT 24
Finished Jun 09 01:06:07 PM PDT 24
Peak memory 219000 kb
Host smart-f99513e4-b6b3-4226-9170-eb800f5a2886
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1760383241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1760383241
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3558130051
Short name T21
Test name
Test status
Simulation time 547922600 ps
CPU time 221.78 seconds
Started Jun 09 01:05:57 PM PDT 24
Finished Jun 09 01:09:39 PM PDT 24
Peak memory 237476 kb
Host smart-debcca40-e832-460a-9e8a-e90f0105eaa5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558130051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3558130051
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1791371641
Short name T19
Test name
Test status
Simulation time 21748824326 ps
CPU time 58 seconds
Started Jun 09 01:05:59 PM PDT 24
Finished Jun 09 01:06:57 PM PDT 24
Peak memory 216744 kb
Host smart-20b88fd6-069d-435c-83e9-2f805562468e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791371641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1791371641
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.228069357
Short name T193
Test name
Test status
Simulation time 7058380602 ps
CPU time 81.24 seconds
Started Jun 09 01:06:01 PM PDT 24
Finished Jun 09 01:07:22 PM PDT 24
Peak memory 219048 kb
Host smart-d6e157a0-8fea-4a3e-bad3-5c4a7664f6ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228069357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.228069357
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2852000095
Short name T327
Test name
Test status
Simulation time 26234111800 ps
CPU time 30.88 seconds
Started Jun 09 01:06:07 PM PDT 24
Finished Jun 09 01:06:39 PM PDT 24
Peak memory 216972 kb
Host smart-8404f599-9af6-4822-91ef-f718901deaeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852000095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2852000095
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.4287634642
Short name T308
Test name
Test status
Simulation time 9131654396 ps
CPU time 330.92 seconds
Started Jun 09 01:05:58 PM PDT 24
Finished Jun 09 01:11:29 PM PDT 24
Peak memory 238164 kb
Host smart-e4538e2c-260f-4ff5-b4b5-834f27f6e8fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287634642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.4287634642
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1603853737
Short name T255
Test name
Test status
Simulation time 487775336 ps
CPU time 19.05 seconds
Started Jun 09 01:05:59 PM PDT 24
Finished Jun 09 01:06:19 PM PDT 24
Peak memory 218920 kb
Host smart-bd8df6c5-af33-4247-867d-f429c2cac695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603853737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1603853737
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1048137833
Short name T96
Test name
Test status
Simulation time 6447293016 ps
CPU time 58.18 seconds
Started Jun 09 01:06:01 PM PDT 24
Finished Jun 09 01:06:59 PM PDT 24
Peak memory 216240 kb
Host smart-f5e25e96-62d3-4390-a8c0-118e96eb3495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048137833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1048137833
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.509948750
Short name T128
Test name
Test status
Simulation time 23730908297 ps
CPU time 119.95 seconds
Started Jun 09 01:05:57 PM PDT 24
Finished Jun 09 01:07:58 PM PDT 24
Peak memory 227288 kb
Host smart-457e8982-7b6a-442b-81c3-e752bee883c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509948750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.509948750
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.136860397
Short name T143
Test name
Test status
Simulation time 168982111 ps
CPU time 8.27 seconds
Started Jun 09 01:06:20 PM PDT 24
Finished Jun 09 01:06:29 PM PDT 24
Peak memory 216632 kb
Host smart-4749ffcc-93c1-4c17-92a6-8b0ea00a74c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136860397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.136860397
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2833617739
Short name T212
Test name
Test status
Simulation time 3783739801 ps
CPU time 260.86 seconds
Started Jun 09 01:06:21 PM PDT 24
Finished Jun 09 01:10:42 PM PDT 24
Peak memory 239004 kb
Host smart-99390ca1-c36d-471a-9e5a-f7b49dfd9936
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833617739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2833617739
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3128211728
Short name T307
Test name
Test status
Simulation time 9387633626 ps
CPU time 24.73 seconds
Started Jun 09 01:06:24 PM PDT 24
Finished Jun 09 01:06:49 PM PDT 24
Peak memory 218128 kb
Host smart-01a6b33f-948f-474a-aae8-5c50fb06f347
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3128211728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3128211728
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.116964313
Short name T71
Test name
Test status
Simulation time 574158976 ps
CPU time 20.34 seconds
Started Jun 09 01:06:22 PM PDT 24
Finished Jun 09 01:06:42 PM PDT 24
Peak memory 216392 kb
Host smart-baf2c8ee-e916-4d00-bd86-1bc11b9051dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116964313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.116964313
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2832832522
Short name T285
Test name
Test status
Simulation time 4823979452 ps
CPU time 78.62 seconds
Started Jun 09 01:06:22 PM PDT 24
Finished Jun 09 01:07:41 PM PDT 24
Peak memory 220000 kb
Host smart-76ab2697-0eee-4291-a313-4b69ee46ed33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832832522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2832832522
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2820446888
Short name T352
Test name
Test status
Simulation time 3034017462 ps
CPU time 26.49 seconds
Started Jun 09 01:06:25 PM PDT 24
Finished Jun 09 01:06:52 PM PDT 24
Peak memory 216772 kb
Host smart-9084ee06-63e2-49a7-943a-499b3aad90de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820446888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2820446888
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.4141621277
Short name T252
Test name
Test status
Simulation time 211849716225 ps
CPU time 649.51 seconds
Started Jun 09 01:06:21 PM PDT 24
Finished Jun 09 01:17:11 PM PDT 24
Peak memory 238108 kb
Host smart-d3a146db-2111-444a-9c65-0b50b656f8e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141621277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.4141621277
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1751185169
Short name T219
Test name
Test status
Simulation time 3651305888 ps
CPU time 30.46 seconds
Started Jun 09 01:06:22 PM PDT 24
Finished Jun 09 01:06:53 PM PDT 24
Peak memory 219028 kb
Host smart-448552d2-d170-4db8-8611-1111345807ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1751185169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1751185169
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1464883117
Short name T294
Test name
Test status
Simulation time 24179889662 ps
CPU time 51.77 seconds
Started Jun 09 01:06:25 PM PDT 24
Finished Jun 09 01:07:17 PM PDT 24
Peak memory 218432 kb
Host smart-3f674ed6-3711-45da-afd4-2ce005c0748a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464883117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1464883117
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3805608822
Short name T8
Test name
Test status
Simulation time 10444719303 ps
CPU time 57.53 seconds
Started Jun 09 01:06:22 PM PDT 24
Finished Jun 09 01:07:20 PM PDT 24
Peak memory 217512 kb
Host smart-9d96ea12-7b5c-4a33-b4e0-557b98627188
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805608822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3805608822
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3456906970
Short name T333
Test name
Test status
Simulation time 11429014776 ps
CPU time 166.74 seconds
Started Jun 09 01:06:22 PM PDT 24
Finished Jun 09 01:09:09 PM PDT 24
Peak memory 224852 kb
Host smart-4ae99dcf-d4b4-404a-82c4-d78ed3622d72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456906970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3456906970
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.581358419
Short name T150
Test name
Test status
Simulation time 5137091560 ps
CPU time 48.32 seconds
Started Jun 09 01:06:25 PM PDT 24
Finished Jun 09 01:07:14 PM PDT 24
Peak memory 219048 kb
Host smart-fbfda21f-91b6-4d8f-9c48-d3f9c97eb22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581358419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.581358419
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2862877056
Short name T329
Test name
Test status
Simulation time 756508606 ps
CPU time 10.59 seconds
Started Jun 09 01:06:23 PM PDT 24
Finished Jun 09 01:06:33 PM PDT 24
Peak memory 219004 kb
Host smart-a4b86e6e-0055-4e0e-8fb5-8b41620a0a52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2862877056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2862877056
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.4289669009
Short name T266
Test name
Test status
Simulation time 3559514847 ps
CPU time 53.59 seconds
Started Jun 09 01:06:22 PM PDT 24
Finished Jun 09 01:07:15 PM PDT 24
Peak memory 219028 kb
Host smart-2cccfa68-91cf-49f0-a7a5-ab4a4ca10de0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289669009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.4289669009
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2705741158
Short name T249
Test name
Test status
Simulation time 5825828768 ps
CPU time 26 seconds
Started Jun 09 01:06:28 PM PDT 24
Finished Jun 09 01:06:54 PM PDT 24
Peak memory 217076 kb
Host smart-75a11518-0d2b-4835-8311-3e25051c1400
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705741158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2705741158
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1640257642
Short name T309
Test name
Test status
Simulation time 77496090037 ps
CPU time 611.52 seconds
Started Jun 09 01:06:25 PM PDT 24
Finished Jun 09 01:16:37 PM PDT 24
Peak memory 217452 kb
Host smart-ce84c4a6-9320-4517-ad7d-bf0dc56d30ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640257642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1640257642
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1098842087
Short name T151
Test name
Test status
Simulation time 4945565135 ps
CPU time 38.84 seconds
Started Jun 09 01:06:27 PM PDT 24
Finished Jun 09 01:07:06 PM PDT 24
Peak memory 219036 kb
Host smart-67d73a8c-ed37-44f8-9d20-a64a4f2e7e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098842087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1098842087
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4051151395
Short name T194
Test name
Test status
Simulation time 220068529 ps
CPU time 10.74 seconds
Started Jun 09 01:06:21 PM PDT 24
Finished Jun 09 01:06:32 PM PDT 24
Peak memory 218932 kb
Host smart-aac24a96-9a6a-4f52-a756-23e8c5cda118
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4051151395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4051151395
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1439632501
Short name T359
Test name
Test status
Simulation time 1182364627 ps
CPU time 29.72 seconds
Started Jun 09 01:06:23 PM PDT 24
Finished Jun 09 01:06:53 PM PDT 24
Peak memory 216392 kb
Host smart-158c7c09-d987-4502-8835-4f2d13ae0f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439632501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1439632501
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2271955753
Short name T316
Test name
Test status
Simulation time 704438135 ps
CPU time 39.56 seconds
Started Jun 09 01:06:20 PM PDT 24
Finished Jun 09 01:07:00 PM PDT 24
Peak memory 218876 kb
Host smart-77854385-042f-460f-9890-f0c55fce0e7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271955753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2271955753
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.614892819
Short name T14
Test name
Test status
Simulation time 100756235596 ps
CPU time 1901.45 seconds
Started Jun 09 01:06:26 PM PDT 24
Finished Jun 09 01:38:08 PM PDT 24
Peak memory 233028 kb
Host smart-e416f9ef-5828-44be-81ee-f4d05fbf5aeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614892819 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.614892819
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.535094714
Short name T274
Test name
Test status
Simulation time 751395317 ps
CPU time 8.25 seconds
Started Jun 09 01:06:26 PM PDT 24
Finished Jun 09 01:06:35 PM PDT 24
Peak memory 216664 kb
Host smart-35245215-b563-47ad-9f94-fd0a1c2b41c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535094714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.535094714
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2370297994
Short name T269
Test name
Test status
Simulation time 32448499870 ps
CPU time 292.32 seconds
Started Jun 09 01:06:27 PM PDT 24
Finished Jun 09 01:11:20 PM PDT 24
Peak memory 236876 kb
Host smart-aca9b7bc-83e2-4011-a6a6-17b69e37f167
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370297994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2370297994
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.296013692
Short name T218
Test name
Test status
Simulation time 1270026881 ps
CPU time 19.02 seconds
Started Jun 09 01:06:29 PM PDT 24
Finished Jun 09 01:06:49 PM PDT 24
Peak memory 218952 kb
Host smart-4e033dbf-ed1b-41af-9b74-927da2eb115d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296013692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.296013692
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.107112916
Short name T170
Test name
Test status
Simulation time 9963688271 ps
CPU time 24.09 seconds
Started Jun 09 01:06:28 PM PDT 24
Finished Jun 09 01:06:52 PM PDT 24
Peak memory 219028 kb
Host smart-7f25d786-b707-463c-8e62-5fc3259ba6e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=107112916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.107112916
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2250646789
Short name T227
Test name
Test status
Simulation time 360598047 ps
CPU time 19 seconds
Started Jun 09 01:06:29 PM PDT 24
Finished Jun 09 01:06:49 PM PDT 24
Peak memory 217380 kb
Host smart-b9acb68d-65b2-439a-b04d-ee17a52b512a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250646789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2250646789
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.698517509
Short name T297
Test name
Test status
Simulation time 225723701 ps
CPU time 11.67 seconds
Started Jun 09 01:06:28 PM PDT 24
Finished Jun 09 01:06:40 PM PDT 24
Peak memory 218140 kb
Host smart-870d1b7d-9125-4243-a21c-78efb814c7a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698517509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.698517509
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2764121663
Short name T137
Test name
Test status
Simulation time 14502021085 ps
CPU time 17.54 seconds
Started Jun 09 01:06:29 PM PDT 24
Finished Jun 09 01:06:46 PM PDT 24
Peak memory 217196 kb
Host smart-0dfde54c-493d-4b8e-8cb9-a990b50aae7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764121663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2764121663
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3492241984
Short name T33
Test name
Test status
Simulation time 48154671916 ps
CPU time 367.15 seconds
Started Jun 09 01:06:28 PM PDT 24
Finished Jun 09 01:12:35 PM PDT 24
Peak memory 236984 kb
Host smart-593a4ad2-3b18-4679-a485-19335cd147d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492241984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3492241984
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2360688197
Short name T250
Test name
Test status
Simulation time 8228500426 ps
CPU time 46.23 seconds
Started Jun 09 01:06:27 PM PDT 24
Finished Jun 09 01:07:13 PM PDT 24
Peak memory 219064 kb
Host smart-fc5bc748-faf5-4390-8537-395e89e02258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360688197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2360688197
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3464728319
Short name T223
Test name
Test status
Simulation time 4110241102 ps
CPU time 33.44 seconds
Started Jun 09 01:06:28 PM PDT 24
Finished Jun 09 01:07:02 PM PDT 24
Peak memory 211068 kb
Host smart-1feb53bf-2dbc-410c-97c9-407c88ac612e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3464728319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3464728319
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1259924899
Short name T48
Test name
Test status
Simulation time 29165037810 ps
CPU time 66.43 seconds
Started Jun 09 01:06:25 PM PDT 24
Finished Jun 09 01:07:32 PM PDT 24
Peak memory 216336 kb
Host smart-80c6a41d-2f10-4f88-818b-c114fb8b6050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259924899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1259924899
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.619168117
Short name T93
Test name
Test status
Simulation time 8423005185 ps
CPU time 47.88 seconds
Started Jun 09 01:06:28 PM PDT 24
Finished Jun 09 01:07:17 PM PDT 24
Peak memory 219080 kb
Host smart-d53b0fb8-2833-4aa5-837e-82bafc17518e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619168117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.619168117
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2759353936
Short name T42
Test name
Test status
Simulation time 255234384689 ps
CPU time 2465.29 seconds
Started Jun 09 01:06:28 PM PDT 24
Finished Jun 09 01:47:34 PM PDT 24
Peak memory 243744 kb
Host smart-7967367f-f55e-426c-84ca-aad5c08d3d8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759353936 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.2759353936
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.4061712981
Short name T357
Test name
Test status
Simulation time 4169918825 ps
CPU time 34.88 seconds
Started Jun 09 01:06:34 PM PDT 24
Finished Jun 09 01:07:09 PM PDT 24
Peak memory 216852 kb
Host smart-78b09622-3d44-45a8-ad4e-cf161cf053c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061712981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.4061712981
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.899813439
Short name T179
Test name
Test status
Simulation time 247826639212 ps
CPU time 491.53 seconds
Started Jun 09 01:06:29 PM PDT 24
Finished Jun 09 01:14:41 PM PDT 24
Peak memory 237276 kb
Host smart-8f92b2ac-1968-483f-a1ce-6fa13ae73548
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899813439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.899813439
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1435966317
Short name T287
Test name
Test status
Simulation time 11921675452 ps
CPU time 29.63 seconds
Started Jun 09 01:06:27 PM PDT 24
Finished Jun 09 01:06:57 PM PDT 24
Peak memory 219132 kb
Host smart-ede1a6b4-be9a-4f93-942c-c5dabf0ca8d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1435966317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1435966317
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2477904938
Short name T11
Test name
Test status
Simulation time 27563408882 ps
CPU time 59.83 seconds
Started Jun 09 01:06:28 PM PDT 24
Finished Jun 09 01:07:28 PM PDT 24
Peak memory 216112 kb
Host smart-87de569b-c1ff-4151-aba7-fc7af209183e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477904938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2477904938
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2228769407
Short name T230
Test name
Test status
Simulation time 80327867906 ps
CPU time 68.74 seconds
Started Jun 09 01:06:28 PM PDT 24
Finished Jun 09 01:07:37 PM PDT 24
Peak memory 216908 kb
Host smart-0203c7df-e011-4893-b3c3-f74716481068
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228769407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2228769407
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2378280405
Short name T190
Test name
Test status
Simulation time 5427716430 ps
CPU time 29.39 seconds
Started Jun 09 01:06:32 PM PDT 24
Finished Jun 09 01:07:02 PM PDT 24
Peak memory 217060 kb
Host smart-165539a4-0591-4b50-971a-da76ae351770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378280405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2378280405
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.965352413
Short name T201
Test name
Test status
Simulation time 27166533099 ps
CPU time 316.73 seconds
Started Jun 09 01:06:35 PM PDT 24
Finished Jun 09 01:11:52 PM PDT 24
Peak memory 228828 kb
Host smart-3a67c554-55ed-46af-bb83-2f08dc0839ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965352413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.965352413
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.4101257272
Short name T340
Test name
Test status
Simulation time 34199486987 ps
CPU time 69.17 seconds
Started Jun 09 01:06:32 PM PDT 24
Finished Jun 09 01:07:42 PM PDT 24
Peak memory 219060 kb
Host smart-0fca9ccb-16bf-45cf-8d01-c8a9af364a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101257272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.4101257272
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2237073085
Short name T246
Test name
Test status
Simulation time 3481822671 ps
CPU time 31.1 seconds
Started Jun 09 01:06:33 PM PDT 24
Finished Jun 09 01:07:04 PM PDT 24
Peak memory 219052 kb
Host smart-ee0796a9-be9a-44b9-834c-fa6c6a3deaeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2237073085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2237073085
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1858444324
Short name T346
Test name
Test status
Simulation time 2159803558 ps
CPU time 20.6 seconds
Started Jun 09 01:06:33 PM PDT 24
Finished Jun 09 01:06:54 PM PDT 24
Peak memory 215504 kb
Host smart-194febec-9f4a-4099-badf-1356673e8e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858444324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1858444324
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3194154112
Short name T138
Test name
Test status
Simulation time 14209835744 ps
CPU time 44.95 seconds
Started Jun 09 01:06:32 PM PDT 24
Finished Jun 09 01:07:17 PM PDT 24
Peak memory 216912 kb
Host smart-2f475764-9047-4295-aad5-c11c1f10c30e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194154112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3194154112
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2054111236
Short name T57
Test name
Test status
Simulation time 1775909199 ps
CPU time 19.34 seconds
Started Jun 09 01:06:38 PM PDT 24
Finished Jun 09 01:06:57 PM PDT 24
Peak memory 216708 kb
Host smart-df3326bc-fee5-4310-abc0-9722377db5f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054111236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2054111236
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3726050872
Short name T232
Test name
Test status
Simulation time 166091904456 ps
CPU time 390.06 seconds
Started Jun 09 01:06:32 PM PDT 24
Finished Jun 09 01:13:03 PM PDT 24
Peak memory 224492 kb
Host smart-de1928a7-1839-46a9-b328-092ec1b714b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726050872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3726050872
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3132176019
Short name T263
Test name
Test status
Simulation time 8017888783 ps
CPU time 68.99 seconds
Started Jun 09 01:06:31 PM PDT 24
Finished Jun 09 01:07:41 PM PDT 24
Peak memory 219032 kb
Host smart-c178b971-beef-41fb-97a1-67c72ffa59d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132176019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3132176019
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.516681056
Short name T280
Test name
Test status
Simulation time 3629089431 ps
CPU time 20.26 seconds
Started Jun 09 01:06:32 PM PDT 24
Finished Jun 09 01:06:53 PM PDT 24
Peak memory 219072 kb
Host smart-df1f12f8-63a0-4e94-be92-b7d3c2b7a237
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=516681056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.516681056
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3257887555
Short name T152
Test name
Test status
Simulation time 534417073 ps
CPU time 24.02 seconds
Started Jun 09 01:06:31 PM PDT 24
Finished Jun 09 01:06:56 PM PDT 24
Peak memory 216348 kb
Host smart-99c3487a-e979-4ff9-9add-cf77f4d4aa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257887555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3257887555
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1003521385
Short name T284
Test name
Test status
Simulation time 32980849584 ps
CPU time 93.45 seconds
Started Jun 09 01:06:34 PM PDT 24
Finished Jun 09 01:08:08 PM PDT 24
Peak memory 220596 kb
Host smart-5b4158ae-f54d-4683-aab7-38db4edca3e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003521385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1003521385
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2828572910
Short name T155
Test name
Test status
Simulation time 3972928870 ps
CPU time 31.08 seconds
Started Jun 09 01:06:37 PM PDT 24
Finished Jun 09 01:07:09 PM PDT 24
Peak memory 216688 kb
Host smart-d5b94b2d-272b-4d2f-a4a2-0068ceb6595d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828572910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2828572910
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3584654636
Short name T238
Test name
Test status
Simulation time 348458617602 ps
CPU time 680.5 seconds
Started Jun 09 01:06:39 PM PDT 24
Finished Jun 09 01:18:00 PM PDT 24
Peak memory 233192 kb
Host smart-e8ed460c-bebc-428e-95c0-61ea3bb27081
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584654636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3584654636
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2096224571
Short name T209
Test name
Test status
Simulation time 339068354 ps
CPU time 19 seconds
Started Jun 09 01:06:39 PM PDT 24
Finished Jun 09 01:06:58 PM PDT 24
Peak memory 218916 kb
Host smart-4c75e8e4-1bb2-4195-9e40-5819f3de0bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096224571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2096224571
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1445021970
Short name T264
Test name
Test status
Simulation time 8172536835 ps
CPU time 23.62 seconds
Started Jun 09 01:06:39 PM PDT 24
Finished Jun 09 01:07:03 PM PDT 24
Peak memory 219048 kb
Host smart-82aa2e88-0166-49ff-bba6-63d5e87d5266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1445021970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1445021970
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2636735171
Short name T90
Test name
Test status
Simulation time 1448733510 ps
CPU time 20.08 seconds
Started Jun 09 01:06:38 PM PDT 24
Finished Jun 09 01:06:58 PM PDT 24
Peak memory 216632 kb
Host smart-1235a45d-1671-4101-8fe8-4f1c6009deed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636735171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2636735171
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2004062905
Short name T276
Test name
Test status
Simulation time 7127181406 ps
CPU time 24.54 seconds
Started Jun 09 01:06:37 PM PDT 24
Finished Jun 09 01:07:02 PM PDT 24
Peak memory 219044 kb
Host smart-06d54419-c7cf-4ee4-81d0-0c45f8fa2052
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004062905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2004062905
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.986249667
Short name T7
Test name
Test status
Simulation time 673402864 ps
CPU time 10.6 seconds
Started Jun 09 01:06:04 PM PDT 24
Finished Jun 09 01:06:15 PM PDT 24
Peak memory 216624 kb
Host smart-e060734f-2f81-4465-98d2-50f3bc32b4c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986249667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.986249667
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3907148729
Short name T40
Test name
Test status
Simulation time 8698735088 ps
CPU time 68.91 seconds
Started Jun 09 01:06:06 PM PDT 24
Finished Jun 09 01:07:16 PM PDT 24
Peak memory 219064 kb
Host smart-f971b11c-c17c-480f-b95b-8af9835e533e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907148729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3907148729
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.860844610
Short name T351
Test name
Test status
Simulation time 2688526915 ps
CPU time 19.19 seconds
Started Jun 09 01:06:05 PM PDT 24
Finished Jun 09 01:06:24 PM PDT 24
Peak memory 219068 kb
Host smart-a08abe86-28b7-4070-8ddf-eea32d755657
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=860844610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.860844610
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3654608826
Short name T28
Test name
Test status
Simulation time 3738493076 ps
CPU time 131.62 seconds
Started Jun 09 01:06:08 PM PDT 24
Finished Jun 09 01:08:20 PM PDT 24
Peak memory 236872 kb
Host smart-c4ce43a8-f7bf-4d07-883e-48299d23c828
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654608826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3654608826
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1374037419
Short name T337
Test name
Test status
Simulation time 6656405193 ps
CPU time 70.33 seconds
Started Jun 09 01:06:04 PM PDT 24
Finished Jun 09 01:07:15 PM PDT 24
Peak memory 216752 kb
Host smart-8cbb7791-d186-4bac-9585-60f0f0d36af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374037419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1374037419
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3747500424
Short name T229
Test name
Test status
Simulation time 104013467651 ps
CPU time 182.78 seconds
Started Jun 09 01:06:05 PM PDT 24
Finished Jun 09 01:09:09 PM PDT 24
Peak memory 220964 kb
Host smart-32eaa196-6c8b-444d-b9ca-13fc6a109b44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747500424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3747500424
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3811718569
Short name T220
Test name
Test status
Simulation time 345869014 ps
CPU time 10.61 seconds
Started Jun 09 01:06:43 PM PDT 24
Finished Jun 09 01:06:54 PM PDT 24
Peak memory 216796 kb
Host smart-4461cda7-fd2c-4f96-b475-4d0eef4500a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811718569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3811718569
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1948295802
Short name T108
Test name
Test status
Simulation time 21138878490 ps
CPU time 311.11 seconds
Started Jun 09 01:06:44 PM PDT 24
Finished Jun 09 01:11:56 PM PDT 24
Peak memory 224832 kb
Host smart-deb3d44d-440e-4840-b9cc-e130bec441e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948295802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1948295802
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2606471145
Short name T5
Test name
Test status
Simulation time 70777874980 ps
CPU time 48.06 seconds
Started Jun 09 01:06:46 PM PDT 24
Finished Jun 09 01:07:35 PM PDT 24
Peak memory 219060 kb
Host smart-8f689e9b-2d8f-444d-8fd3-702b1ef35097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606471145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2606471145
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1319289644
Short name T341
Test name
Test status
Simulation time 7226255486 ps
CPU time 22.1 seconds
Started Jun 09 01:06:43 PM PDT 24
Finished Jun 09 01:07:06 PM PDT 24
Peak memory 211396 kb
Host smart-c8f8249d-93d6-485a-be37-bb79fa69150d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1319289644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1319289644
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3633054297
Short name T268
Test name
Test status
Simulation time 2306802483 ps
CPU time 41.2 seconds
Started Jun 09 01:06:43 PM PDT 24
Finished Jun 09 01:07:25 PM PDT 24
Peak memory 217460 kb
Host smart-5a3b5490-b6ed-4691-ae8e-f5ed21d54c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633054297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3633054297
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.4206802311
Short name T345
Test name
Test status
Simulation time 16470552736 ps
CPU time 165.27 seconds
Started Jun 09 01:06:44 PM PDT 24
Finished Jun 09 01:09:29 PM PDT 24
Peak memory 219060 kb
Host smart-2b336f27-1254-4991-9468-2b5912cfa2f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206802311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.4206802311
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1706934529
Short name T248
Test name
Test status
Simulation time 611577703 ps
CPU time 8.5 seconds
Started Jun 09 01:06:55 PM PDT 24
Finished Jun 09 01:07:04 PM PDT 24
Peak memory 216644 kb
Host smart-65551ca4-28e6-4e38-b1d9-671d5d01d39a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706934529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1706934529
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3674815616
Short name T282
Test name
Test status
Simulation time 5810289784 ps
CPU time 256.36 seconds
Started Jun 09 01:06:58 PM PDT 24
Finished Jun 09 01:11:14 PM PDT 24
Peak memory 240192 kb
Host smart-c121545a-2180-4234-8d11-ad9dd31fed4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674815616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3674815616
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4135159344
Short name T334
Test name
Test status
Simulation time 12196942756 ps
CPU time 37.66 seconds
Started Jun 09 01:06:53 PM PDT 24
Finished Jun 09 01:07:31 PM PDT 24
Peak memory 218964 kb
Host smart-b702105e-42c8-4362-9664-47f15e1dc948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135159344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4135159344
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.19352989
Short name T254
Test name
Test status
Simulation time 52832297623 ps
CPU time 34.65 seconds
Started Jun 09 01:06:47 PM PDT 24
Finished Jun 09 01:07:22 PM PDT 24
Peak memory 217392 kb
Host smart-d0784385-2267-45df-82d0-8d49e7c4c6e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19352989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.19352989
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2424375252
Short name T206
Test name
Test status
Simulation time 25285283309 ps
CPU time 53.26 seconds
Started Jun 09 01:06:48 PM PDT 24
Finished Jun 09 01:07:41 PM PDT 24
Peak memory 215652 kb
Host smart-2e787026-30bf-4c51-a16b-bf40248f26b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424375252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2424375252
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.4063833714
Short name T147
Test name
Test status
Simulation time 345701357 ps
CPU time 8.1 seconds
Started Jun 09 01:06:57 PM PDT 24
Finished Jun 09 01:07:06 PM PDT 24
Peak memory 216664 kb
Host smart-a7a30234-7879-4df3-92b7-5a4ff0cd159a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063833714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.4063833714
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3736420698
Short name T347
Test name
Test status
Simulation time 167174465302 ps
CPU time 648.52 seconds
Started Jun 09 01:07:00 PM PDT 24
Finished Jun 09 01:17:49 PM PDT 24
Peak memory 234444 kb
Host smart-a8575d7b-c0f4-4dde-ae7f-971e8c26b83d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736420698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3736420698
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2509026202
Short name T213
Test name
Test status
Simulation time 13624221928 ps
CPU time 30.83 seconds
Started Jun 09 01:07:00 PM PDT 24
Finished Jun 09 01:07:31 PM PDT 24
Peak memory 215260 kb
Host smart-aa2c01ae-3b1e-4dd0-b98e-c8464be2739a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509026202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2509026202
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1794770160
Short name T110
Test name
Test status
Simulation time 4133202815 ps
CPU time 26.13 seconds
Started Jun 09 01:06:57 PM PDT 24
Finished Jun 09 01:07:24 PM PDT 24
Peak memory 217300 kb
Host smart-ad153964-b3ca-45df-a6f4-909561c10f65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1794770160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1794770160
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.353921263
Short name T115
Test name
Test status
Simulation time 350037044 ps
CPU time 20.21 seconds
Started Jun 09 01:06:56 PM PDT 24
Finished Jun 09 01:07:17 PM PDT 24
Peak memory 216644 kb
Host smart-37aea10f-919e-40ab-93bb-0a84bef2c179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353921263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.353921263
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2008825174
Short name T161
Test name
Test status
Simulation time 8915387187 ps
CPU time 43.66 seconds
Started Jun 09 01:06:56 PM PDT 24
Finished Jun 09 01:07:40 PM PDT 24
Peak memory 218924 kb
Host smart-566904b0-90eb-4688-aef7-2e62ac722e7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008825174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2008825174
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1886374599
Short name T270
Test name
Test status
Simulation time 3936198282 ps
CPU time 14.85 seconds
Started Jun 09 01:07:00 PM PDT 24
Finished Jun 09 01:07:15 PM PDT 24
Peak memory 216636 kb
Host smart-67765de8-5fd7-4558-8711-9969db69d98e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886374599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1886374599
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3513010873
Short name T38
Test name
Test status
Simulation time 220880770868 ps
CPU time 588.85 seconds
Started Jun 09 01:07:04 PM PDT 24
Finished Jun 09 01:16:53 PM PDT 24
Peak memory 219300 kb
Host smart-9b56addf-69dc-40f2-9c67-f29412cc5113
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513010873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3513010873
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1958174731
Short name T335
Test name
Test status
Simulation time 11804055114 ps
CPU time 38.07 seconds
Started Jun 09 01:07:00 PM PDT 24
Finished Jun 09 01:07:38 PM PDT 24
Peak memory 219028 kb
Host smart-a1228974-ac36-4030-9057-aaeb3e5636d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958174731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1958174731
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.606474520
Short name T244
Test name
Test status
Simulation time 8224887909 ps
CPU time 23.96 seconds
Started Jun 09 01:06:59 PM PDT 24
Finished Jun 09 01:07:23 PM PDT 24
Peak memory 219128 kb
Host smart-b3846523-75cd-403f-a6a4-ead4c61aeae5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=606474520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.606474520
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1893273014
Short name T259
Test name
Test status
Simulation time 703813611 ps
CPU time 20.14 seconds
Started Jun 09 01:06:59 PM PDT 24
Finished Jun 09 01:07:19 PM PDT 24
Peak memory 215172 kb
Host smart-cb37d9be-c1d1-4d4a-90f3-ea0b59c2f3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893273014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1893273014
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1176593534
Short name T265
Test name
Test status
Simulation time 63210512484 ps
CPU time 150.65 seconds
Started Jun 09 01:06:58 PM PDT 24
Finished Jun 09 01:09:29 PM PDT 24
Peak memory 227260 kb
Host smart-cff0c3b8-53b4-4b20-8be0-1a498cd666ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176593534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1176593534
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3737995740
Short name T24
Test name
Test status
Simulation time 10265707233 ps
CPU time 23.81 seconds
Started Jun 09 01:07:05 PM PDT 24
Finished Jun 09 01:07:30 PM PDT 24
Peak memory 217244 kb
Host smart-2c46dabc-aaab-4cc3-a2be-ece28256b330
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737995740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3737995740
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2021334427
Short name T305
Test name
Test status
Simulation time 45409388469 ps
CPU time 560.32 seconds
Started Jun 09 01:07:05 PM PDT 24
Finished Jun 09 01:16:25 PM PDT 24
Peak memory 233312 kb
Host smart-556efbbf-fceb-49f1-9c55-9fa8d21210a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021334427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2021334427
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1248018978
Short name T174
Test name
Test status
Simulation time 8532683811 ps
CPU time 70.58 seconds
Started Jun 09 01:07:05 PM PDT 24
Finished Jun 09 01:08:16 PM PDT 24
Peak memory 219064 kb
Host smart-06779eb7-5663-4fdd-9a69-c1b831e1dec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248018978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1248018978
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3266177946
Short name T135
Test name
Test status
Simulation time 2379093977 ps
CPU time 14.9 seconds
Started Jun 09 01:07:05 PM PDT 24
Finished Jun 09 01:07:20 PM PDT 24
Peak memory 218640 kb
Host smart-c8a64d43-7db3-4560-833b-f1a97d4975b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3266177946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3266177946
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1364403743
Short name T258
Test name
Test status
Simulation time 385406354 ps
CPU time 20.33 seconds
Started Jun 09 01:07:02 PM PDT 24
Finished Jun 09 01:07:23 PM PDT 24
Peak memory 215776 kb
Host smart-114fccb6-fa86-48e2-94d8-a85b8150ea20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364403743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1364403743
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2721502645
Short name T148
Test name
Test status
Simulation time 33439336595 ps
CPU time 86.37 seconds
Started Jun 09 01:06:57 PM PDT 24
Finished Jun 09 01:08:24 PM PDT 24
Peak memory 216688 kb
Host smart-0fe09448-022e-4521-9c44-018565aefc1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721502645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2721502645
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3011303278
Short name T58
Test name
Test status
Simulation time 172394274 ps
CPU time 8.53 seconds
Started Jun 09 01:07:19 PM PDT 24
Finished Jun 09 01:07:28 PM PDT 24
Peak memory 216756 kb
Host smart-d6a557c5-9be0-41ea-8d2a-a75d67c282e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011303278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3011303278
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.662701787
Short name T180
Test name
Test status
Simulation time 64626633813 ps
CPU time 418.33 seconds
Started Jun 09 01:07:11 PM PDT 24
Finished Jun 09 01:14:10 PM PDT 24
Peak memory 237456 kb
Host smart-72461ef0-5a2a-4e44-82a1-71252fb6eb22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662701787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.662701787
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3877163678
Short name T36
Test name
Test status
Simulation time 13772289957 ps
CPU time 47.73 seconds
Started Jun 09 01:07:09 PM PDT 24
Finished Jun 09 01:07:57 PM PDT 24
Peak memory 219016 kb
Host smart-547edab3-101c-434b-ae19-57e709655e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877163678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3877163678
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2243229207
Short name T153
Test name
Test status
Simulation time 1148807295 ps
CPU time 10.17 seconds
Started Jun 09 01:07:20 PM PDT 24
Finished Jun 09 01:07:31 PM PDT 24
Peak memory 218980 kb
Host smart-ac03dfad-e660-45bc-971f-3d245b1687f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2243229207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2243229207
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.444661389
Short name T214
Test name
Test status
Simulation time 5656175404 ps
CPU time 66.41 seconds
Started Jun 09 01:07:04 PM PDT 24
Finished Jun 09 01:08:11 PM PDT 24
Peak memory 216612 kb
Host smart-3e419efa-da0d-479f-8f83-8afb74f177cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444661389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.444661389
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1720025527
Short name T49
Test name
Test status
Simulation time 15785375393 ps
CPU time 74.85 seconds
Started Jun 09 01:07:19 PM PDT 24
Finished Jun 09 01:08:35 PM PDT 24
Peak memory 216232 kb
Host smart-fdc0e8fd-a8f3-469c-b791-ce56298ea5a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720025527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1720025527
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2462694823
Short name T243
Test name
Test status
Simulation time 1762408799 ps
CPU time 19.02 seconds
Started Jun 09 01:07:21 PM PDT 24
Finished Jun 09 01:07:40 PM PDT 24
Peak memory 216728 kb
Host smart-f41be52e-2de9-4207-a80a-733ce4e6444c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462694823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2462694823
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.4201780036
Short name T173
Test name
Test status
Simulation time 62219934261 ps
CPU time 391.16 seconds
Started Jun 09 01:07:11 PM PDT 24
Finished Jun 09 01:13:42 PM PDT 24
Peak memory 237652 kb
Host smart-dee53914-36f9-4686-b767-3038a6873524
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201780036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.4201780036
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1860009878
Short name T291
Test name
Test status
Simulation time 9303511068 ps
CPU time 45.81 seconds
Started Jun 09 01:07:19 PM PDT 24
Finished Jun 09 01:08:05 PM PDT 24
Peak memory 219048 kb
Host smart-05a288fa-8fed-44ef-817f-39c7b9b322eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860009878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1860009878
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.721365417
Short name T300
Test name
Test status
Simulation time 4334306993 ps
CPU time 32.16 seconds
Started Jun 09 01:07:19 PM PDT 24
Finished Jun 09 01:07:51 PM PDT 24
Peak memory 219108 kb
Host smart-65ac877a-5017-449a-b622-5232052a2cc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=721365417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.721365417
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1847025326
Short name T131
Test name
Test status
Simulation time 527967430 ps
CPU time 22.73 seconds
Started Jun 09 01:07:11 PM PDT 24
Finished Jun 09 01:07:34 PM PDT 24
Peak memory 216612 kb
Host smart-213c623a-8426-45ac-ba86-916da72bf92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847025326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1847025326
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1651406853
Short name T1
Test name
Test status
Simulation time 8156919298 ps
CPU time 73.1 seconds
Started Jun 09 01:07:19 PM PDT 24
Finished Jun 09 01:08:32 PM PDT 24
Peak memory 219084 kb
Host smart-e4205f95-c2cb-4167-a09f-57a7bac0be8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651406853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1651406853
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3248195062
Short name T292
Test name
Test status
Simulation time 167440989 ps
CPU time 8.37 seconds
Started Jun 09 01:07:21 PM PDT 24
Finished Jun 09 01:07:30 PM PDT 24
Peak memory 217024 kb
Host smart-ecedddea-8634-4b59-b724-70ebbbae38c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248195062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3248195062
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3023901686
Short name T301
Test name
Test status
Simulation time 51334770050 ps
CPU time 587.61 seconds
Started Jun 09 01:07:20 PM PDT 24
Finished Jun 09 01:17:08 PM PDT 24
Peak memory 219308 kb
Host smart-de5145ac-ee3d-4f81-8407-961fe8a4b28a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023901686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3023901686
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.4272767304
Short name T162
Test name
Test status
Simulation time 4782646604 ps
CPU time 47.77 seconds
Started Jun 09 01:07:21 PM PDT 24
Finished Jun 09 01:08:09 PM PDT 24
Peak memory 218352 kb
Host smart-150ef477-0f67-45b6-8962-1229166377ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272767304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.4272767304
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1808944173
Short name T92
Test name
Test status
Simulation time 2594096052 ps
CPU time 25.84 seconds
Started Jun 09 01:07:21 PM PDT 24
Finished Jun 09 01:07:47 PM PDT 24
Peak memory 219052 kb
Host smart-0f1ad263-c90e-44f7-a59a-12ab1faaefcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1808944173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1808944173
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.4006111907
Short name T353
Test name
Test status
Simulation time 19583899006 ps
CPU time 45.19 seconds
Started Jun 09 01:07:20 PM PDT 24
Finished Jun 09 01:08:05 PM PDT 24
Peak memory 216144 kb
Host smart-1a20fc82-3c14-4e20-be10-b0cfc95cc92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006111907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.4006111907
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1034875344
Short name T236
Test name
Test status
Simulation time 4336117915 ps
CPU time 46.64 seconds
Started Jun 09 01:07:19 PM PDT 24
Finished Jun 09 01:08:06 PM PDT 24
Peak memory 214208 kb
Host smart-b988fe00-a688-4c40-b9ca-dee0bbed897a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034875344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1034875344
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.47384515
Short name T323
Test name
Test status
Simulation time 15054520088 ps
CPU time 26.61 seconds
Started Jun 09 01:07:21 PM PDT 24
Finished Jun 09 01:07:48 PM PDT 24
Peak memory 217216 kb
Host smart-46571656-6475-4d72-b29d-dec3abcc55bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47384515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.47384515
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2016132318
Short name T210
Test name
Test status
Simulation time 419106420305 ps
CPU time 570.76 seconds
Started Jun 09 01:07:22 PM PDT 24
Finished Jun 09 01:16:53 PM PDT 24
Peak memory 223948 kb
Host smart-d9babe03-b00d-4bb4-893f-eda5551d05a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016132318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2016132318
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3968628639
Short name T207
Test name
Test status
Simulation time 125544293614 ps
CPU time 69.08 seconds
Started Jun 09 01:07:22 PM PDT 24
Finished Jun 09 01:08:31 PM PDT 24
Peak memory 218932 kb
Host smart-9d771ae9-311e-431b-9c13-3d29baeb2bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968628639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3968628639
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2433915186
Short name T91
Test name
Test status
Simulation time 2947762798 ps
CPU time 18.73 seconds
Started Jun 09 01:07:23 PM PDT 24
Finished Jun 09 01:07:43 PM PDT 24
Peak memory 211328 kb
Host smart-1f5f972b-2151-4dca-b67b-a37ae0edba90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2433915186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2433915186
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3895757177
Short name T123
Test name
Test status
Simulation time 1365981411 ps
CPU time 30.14 seconds
Started Jun 09 01:07:24 PM PDT 24
Finished Jun 09 01:07:54 PM PDT 24
Peak memory 215988 kb
Host smart-a043e77a-c181-4e5a-a1ad-c44b67ceb1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895757177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3895757177
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.725854799
Short name T320
Test name
Test status
Simulation time 13867493039 ps
CPU time 102.06 seconds
Started Jun 09 01:07:23 PM PDT 24
Finished Jun 09 01:09:06 PM PDT 24
Peak memory 220912 kb
Host smart-f553abd0-bcf7-4195-a90d-fb16e87173bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725854799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.725854799
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.536849564
Short name T339
Test name
Test status
Simulation time 689539306 ps
CPU time 8.23 seconds
Started Jun 09 01:07:29 PM PDT 24
Finished Jun 09 01:07:37 PM PDT 24
Peak memory 216760 kb
Host smart-a5e20ba1-fd26-468e-8361-6a9e299177d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536849564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.536849564
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1606770750
Short name T338
Test name
Test status
Simulation time 55122217514 ps
CPU time 242.67 seconds
Started Jun 09 01:07:29 PM PDT 24
Finished Jun 09 01:11:32 PM PDT 24
Peak memory 236508 kb
Host smart-af0f4ce2-f37e-4f2d-b21b-e5889955d081
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606770750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1606770750
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3334729004
Short name T26
Test name
Test status
Simulation time 1874599846 ps
CPU time 25.12 seconds
Started Jun 09 01:07:27 PM PDT 24
Finished Jun 09 01:07:53 PM PDT 24
Peak memory 218192 kb
Host smart-7d175dac-b138-48e4-9a89-8f7f42defec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334729004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3334729004
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3220216419
Short name T299
Test name
Test status
Simulation time 2323218221 ps
CPU time 14.31 seconds
Started Jun 09 01:07:21 PM PDT 24
Finished Jun 09 01:07:36 PM PDT 24
Peak memory 211260 kb
Host smart-699a8a24-37f5-4ead-a023-b5fecb074006
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3220216419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3220216419
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.40268638
Short name T242
Test name
Test status
Simulation time 10285954128 ps
CPU time 40.78 seconds
Started Jun 09 01:07:23 PM PDT 24
Finished Jun 09 01:08:04 PM PDT 24
Peak memory 215900 kb
Host smart-4791f4e8-4a85-4179-bb89-52a688320530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40268638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.40268638
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.925243879
Short name T69
Test name
Test status
Simulation time 33955076671 ps
CPU time 181.26 seconds
Started Jun 09 01:07:22 PM PDT 24
Finished Jun 09 01:10:23 PM PDT 24
Peak memory 220560 kb
Host smart-a4504117-1f98-47e4-8d3d-e8b13e3e7b17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925243879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.925243879
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3245553637
Short name T192
Test name
Test status
Simulation time 11092716400 ps
CPU time 29.84 seconds
Started Jun 09 01:06:05 PM PDT 24
Finished Jun 09 01:06:36 PM PDT 24
Peak memory 217248 kb
Host smart-ae839ded-5baf-462b-9107-9204b46b6989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245553637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3245553637
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2308423929
Short name T20
Test name
Test status
Simulation time 17904411793 ps
CPU time 290.58 seconds
Started Jun 09 01:06:03 PM PDT 24
Finished Jun 09 01:10:54 PM PDT 24
Peak memory 239484 kb
Host smart-950f53ee-55b1-4522-81bc-0aa873464f74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308423929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2308423929
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1296564195
Short name T191
Test name
Test status
Simulation time 2197186275 ps
CPU time 19.04 seconds
Started Jun 09 01:06:06 PM PDT 24
Finished Jun 09 01:06:25 PM PDT 24
Peak memory 218980 kb
Host smart-9c43c13e-c022-4638-922b-7f3471fcb5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296564195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1296564195
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1462209073
Short name T156
Test name
Test status
Simulation time 16095909203 ps
CPU time 32.5 seconds
Started Jun 09 01:06:07 PM PDT 24
Finished Jun 09 01:06:40 PM PDT 24
Peak memory 211380 kb
Host smart-0f632e42-0220-4ceb-b64d-95da3e6e0b85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1462209073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1462209073
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3668781817
Short name T22
Test name
Test status
Simulation time 1956765598 ps
CPU time 128.26 seconds
Started Jun 09 01:06:07 PM PDT 24
Finished Jun 09 01:08:16 PM PDT 24
Peak memory 234956 kb
Host smart-e03b2e61-43ed-48e8-9eb9-879e7d5dbfbb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668781817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3668781817
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2501143536
Short name T68
Test name
Test status
Simulation time 3108413542 ps
CPU time 27.67 seconds
Started Jun 09 01:06:06 PM PDT 24
Finished Jun 09 01:06:34 PM PDT 24
Peak memory 216540 kb
Host smart-01266ca6-cadb-4eae-b5b8-150b86b1a0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501143536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2501143536
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.180910889
Short name T247
Test name
Test status
Simulation time 1030987287 ps
CPU time 44.74 seconds
Started Jun 09 01:06:07 PM PDT 24
Finished Jun 09 01:06:52 PM PDT 24
Peak memory 218916 kb
Host smart-42f227f7-7c14-432b-ad9b-db8117591d82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180910889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.180910889
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2338266456
Short name T240
Test name
Test status
Simulation time 7551559881 ps
CPU time 30.65 seconds
Started Jun 09 01:07:27 PM PDT 24
Finished Jun 09 01:07:58 PM PDT 24
Peak memory 217068 kb
Host smart-f2365f14-a8b0-4199-b80b-c0d58b43e7ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338266456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2338266456
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.4241745784
Short name T198
Test name
Test status
Simulation time 77664860614 ps
CPU time 765.16 seconds
Started Jun 09 01:07:31 PM PDT 24
Finished Jun 09 01:20:17 PM PDT 24
Peak memory 239364 kb
Host smart-87108e85-ae84-4083-b827-e5fd25165c7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241745784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.4241745784
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2921769460
Short name T166
Test name
Test status
Simulation time 1375187522 ps
CPU time 19.49 seconds
Started Jun 09 01:07:29 PM PDT 24
Finished Jun 09 01:07:49 PM PDT 24
Peak memory 218900 kb
Host smart-5b5a506c-d7fd-415e-81f0-450f4acf022a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921769460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2921769460
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2085631062
Short name T119
Test name
Test status
Simulation time 2625610160 ps
CPU time 25.93 seconds
Started Jun 09 01:07:27 PM PDT 24
Finished Jun 09 01:07:53 PM PDT 24
Peak memory 211052 kb
Host smart-9cdf4b5b-c11a-4d27-b03d-469bf597a918
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2085631062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2085631062
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2597358382
Short name T37
Test name
Test status
Simulation time 8165162722 ps
CPU time 67.68 seconds
Started Jun 09 01:07:28 PM PDT 24
Finished Jun 09 01:08:36 PM PDT 24
Peak memory 216568 kb
Host smart-c810c07a-e0fa-4d35-9eb7-3301eae2e765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597358382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2597358382
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3330160677
Short name T181
Test name
Test status
Simulation time 33768294333 ps
CPU time 74.48 seconds
Started Jun 09 01:07:30 PM PDT 24
Finished Jun 09 01:08:45 PM PDT 24
Peak memory 219036 kb
Host smart-a443c04e-7d68-4918-bb7e-7e9acfc5e144
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330160677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3330160677
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1147392482
Short name T288
Test name
Test status
Simulation time 232838322184 ps
CPU time 1543.32 seconds
Started Jun 09 01:07:30 PM PDT 24
Finished Jun 09 01:33:14 PM PDT 24
Peak memory 239192 kb
Host smart-688764d5-d800-4c91-9b60-fbfce3723d47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147392482 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1147392482
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3286294762
Short name T273
Test name
Test status
Simulation time 14687751853 ps
CPU time 29.16 seconds
Started Jun 09 01:07:26 PM PDT 24
Finished Jun 09 01:07:55 PM PDT 24
Peak memory 217392 kb
Host smart-e64fdc09-53c5-443f-869b-481fa115cda4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286294762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3286294762
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.4290573364
Short name T233
Test name
Test status
Simulation time 105081773422 ps
CPU time 313.28 seconds
Started Jun 09 01:07:29 PM PDT 24
Finished Jun 09 01:12:43 PM PDT 24
Peak memory 215504 kb
Host smart-e947c17c-6021-4ac6-bc8a-14649e55db19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290573364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.4290573364
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1039424964
Short name T306
Test name
Test status
Simulation time 79663258412 ps
CPU time 54.6 seconds
Started Jun 09 01:07:28 PM PDT 24
Finished Jun 09 01:08:23 PM PDT 24
Peak memory 219036 kb
Host smart-3888b041-13d0-4955-bbc0-d4d90105c1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039424964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1039424964
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3547965217
Short name T272
Test name
Test status
Simulation time 8361356771 ps
CPU time 33.47 seconds
Started Jun 09 01:07:27 PM PDT 24
Finished Jun 09 01:08:01 PM PDT 24
Peak memory 219108 kb
Host smart-817e390d-a059-4032-88ae-8ce3918fe22f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3547965217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3547965217
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2757002507
Short name T202
Test name
Test status
Simulation time 27982470464 ps
CPU time 59.57 seconds
Started Jun 09 01:07:30 PM PDT 24
Finished Jun 09 01:08:30 PM PDT 24
Peak memory 217088 kb
Host smart-dc2f2909-dbb8-4aa6-9381-1d9a3e29e609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757002507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2757002507
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.998735315
Short name T330
Test name
Test status
Simulation time 18866769064 ps
CPU time 174.12 seconds
Started Jun 09 01:07:28 PM PDT 24
Finished Jun 09 01:10:22 PM PDT 24
Peak memory 227260 kb
Host smart-19b1284d-30ee-456a-a409-65317c01535c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998735315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.998735315
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2227450625
Short name T283
Test name
Test status
Simulation time 31646485417 ps
CPU time 1216.54 seconds
Started Jun 09 01:07:29 PM PDT 24
Finished Jun 09 01:27:46 PM PDT 24
Peak memory 231680 kb
Host smart-ed6c6ab5-6182-4129-a41a-1f4cd94e6f57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227450625 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2227450625
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3271384488
Short name T59
Test name
Test status
Simulation time 174658886 ps
CPU time 8.17 seconds
Started Jun 09 01:07:42 PM PDT 24
Finished Jun 09 01:07:51 PM PDT 24
Peak memory 216052 kb
Host smart-9f960fe2-0fa2-47d7-b486-13e25574866c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271384488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3271384488
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1448627023
Short name T237
Test name
Test status
Simulation time 285452176314 ps
CPU time 681.16 seconds
Started Jun 09 01:07:42 PM PDT 24
Finished Jun 09 01:19:04 PM PDT 24
Peak memory 237504 kb
Host smart-8ba4955f-5527-4c6e-b100-188ae58dfde2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448627023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1448627023
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3954458463
Short name T231
Test name
Test status
Simulation time 4264817916 ps
CPU time 27.7 seconds
Started Jun 09 01:07:35 PM PDT 24
Finished Jun 09 01:08:02 PM PDT 24
Peak memory 215208 kb
Host smart-141f67c3-708f-40e4-a029-1c4bae852357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954458463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3954458463
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.474964257
Short name T319
Test name
Test status
Simulation time 185478685 ps
CPU time 10.68 seconds
Started Jun 09 01:07:34 PM PDT 24
Finished Jun 09 01:07:45 PM PDT 24
Peak memory 218984 kb
Host smart-475bba3f-e53d-4552-80ad-d1ae7ebef48f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=474964257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.474964257
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.704149258
Short name T17
Test name
Test status
Simulation time 67872604429 ps
CPU time 63.46 seconds
Started Jun 09 01:07:28 PM PDT 24
Finished Jun 09 01:08:32 PM PDT 24
Peak memory 215988 kb
Host smart-35150758-a259-494e-8e43-4a1fe98476f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704149258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.704149258
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3210918529
Short name T203
Test name
Test status
Simulation time 22277526451 ps
CPU time 125.37 seconds
Started Jun 09 01:07:26 PM PDT 24
Finished Jun 09 01:09:32 PM PDT 24
Peak memory 222088 kb
Host smart-cfc95a8f-83a1-46ef-bda0-f3d526a8c267
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210918529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3210918529
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1041789659
Short name T139
Test name
Test status
Simulation time 2496073786 ps
CPU time 14.8 seconds
Started Jun 09 01:07:34 PM PDT 24
Finished Jun 09 01:07:49 PM PDT 24
Peak memory 216824 kb
Host smart-bcb2166e-96bb-473f-b640-c05b317e4698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041789659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1041789659
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1659946494
Short name T239
Test name
Test status
Simulation time 221243419389 ps
CPU time 591.59 seconds
Started Jun 09 01:07:42 PM PDT 24
Finished Jun 09 01:17:34 PM PDT 24
Peak memory 225464 kb
Host smart-c2544580-3cfd-4c1c-80f0-d9e522e99823
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659946494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1659946494
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1956881667
Short name T129
Test name
Test status
Simulation time 3599768533 ps
CPU time 42.28 seconds
Started Jun 09 01:07:36 PM PDT 24
Finished Jun 09 01:08:18 PM PDT 24
Peak memory 218944 kb
Host smart-2488cf95-3130-481e-ab8d-044096d3fbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956881667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1956881667
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2281936654
Short name T199
Test name
Test status
Simulation time 8279496029 ps
CPU time 23.96 seconds
Started Jun 09 01:07:36 PM PDT 24
Finished Jun 09 01:08:00 PM PDT 24
Peak memory 217344 kb
Host smart-a49ce3fa-91aa-44d4-8c69-1557e0644801
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2281936654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2281936654
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3397588085
Short name T113
Test name
Test status
Simulation time 47919184758 ps
CPU time 49.49 seconds
Started Jun 09 01:07:42 PM PDT 24
Finished Jun 09 01:08:32 PM PDT 24
Peak memory 215872 kb
Host smart-b249e495-4d46-4980-9626-4daecea20a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397588085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3397588085
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.4245535755
Short name T12
Test name
Test status
Simulation time 16650531414 ps
CPU time 116.49 seconds
Started Jun 09 01:07:42 PM PDT 24
Finished Jun 09 01:09:39 PM PDT 24
Peak memory 219908 kb
Host smart-8418a44f-5074-47ea-8924-3903d1e40de0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245535755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.4245535755
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1065882235
Short name T15
Test name
Test status
Simulation time 62520247331 ps
CPU time 2039.47 seconds
Started Jun 09 01:07:36 PM PDT 24
Finished Jun 09 01:41:35 PM PDT 24
Peak memory 249856 kb
Host smart-fcc657e4-cd1a-42a1-800c-5cd77f71115b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065882235 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.1065882235
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2202415578
Short name T126
Test name
Test status
Simulation time 1397202245 ps
CPU time 18.07 seconds
Started Jun 09 01:07:39 PM PDT 24
Finished Jun 09 01:07:58 PM PDT 24
Peak memory 216232 kb
Host smart-40beb245-836a-47b8-882e-09549905c1c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202415578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2202415578
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.4135499115
Short name T325
Test name
Test status
Simulation time 22011957467 ps
CPU time 69.07 seconds
Started Jun 09 01:07:39 PM PDT 24
Finished Jun 09 01:08:48 PM PDT 24
Peak memory 219068 kb
Host smart-687a22b6-bac1-4c60-9046-7f59df22b13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135499115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.4135499115
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3847337987
Short name T164
Test name
Test status
Simulation time 15405513168 ps
CPU time 31.58 seconds
Started Jun 09 01:07:35 PM PDT 24
Finished Jun 09 01:08:07 PM PDT 24
Peak memory 219080 kb
Host smart-4de3574d-31ab-46ee-9660-e52fba03ca28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3847337987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3847337987
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2158268053
Short name T312
Test name
Test status
Simulation time 24562099293 ps
CPU time 68.81 seconds
Started Jun 09 01:07:33 PM PDT 24
Finished Jun 09 01:08:42 PM PDT 24
Peak memory 217896 kb
Host smart-3d9140ce-c64d-45df-8f9c-965e32e0fab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158268053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2158268053
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.417745161
Short name T211
Test name
Test status
Simulation time 6336710313 ps
CPU time 30.35 seconds
Started Jun 09 01:07:35 PM PDT 24
Finished Jun 09 01:08:06 PM PDT 24
Peak memory 217452 kb
Host smart-11cb73aa-6f3c-4d71-98c8-a35504996f71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417745161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.417745161
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.4143566356
Short name T355
Test name
Test status
Simulation time 8540710414 ps
CPU time 21.53 seconds
Started Jun 09 01:07:40 PM PDT 24
Finished Jun 09 01:08:02 PM PDT 24
Peak memory 217028 kb
Host smart-188fe612-b6e8-44ed-beff-5899515212a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143566356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.4143566356
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3994541430
Short name T34
Test name
Test status
Simulation time 23271150183 ps
CPU time 356.2 seconds
Started Jun 09 01:07:39 PM PDT 24
Finished Jun 09 01:13:35 PM PDT 24
Peak memory 234588 kb
Host smart-29657f23-33f9-429e-8244-75fd43df9a10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994541430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3994541430
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3871960693
Short name T332
Test name
Test status
Simulation time 4707722967 ps
CPU time 19.23 seconds
Started Jun 09 01:07:40 PM PDT 24
Finished Jun 09 01:07:59 PM PDT 24
Peak memory 219016 kb
Host smart-33ecbc2a-8745-4c65-89f7-0ae2e85b5b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871960693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3871960693
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4251922010
Short name T95
Test name
Test status
Simulation time 476911955 ps
CPU time 10.35 seconds
Started Jun 09 01:07:40 PM PDT 24
Finished Jun 09 01:07:51 PM PDT 24
Peak memory 218984 kb
Host smart-9349ec65-4dee-4c5c-a104-8741fc4082fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4251922010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4251922010
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3904453902
Short name T18
Test name
Test status
Simulation time 695087548 ps
CPU time 25.08 seconds
Started Jun 09 01:07:39 PM PDT 24
Finished Jun 09 01:08:05 PM PDT 24
Peak memory 215888 kb
Host smart-ea259c0e-ba56-4737-b79d-6e769d24f3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904453902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3904453902
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1183453200
Short name T186
Test name
Test status
Simulation time 1191423024 ps
CPU time 32.69 seconds
Started Jun 09 01:07:40 PM PDT 24
Finished Jun 09 01:08:13 PM PDT 24
Peak memory 216176 kb
Host smart-79be370e-0abb-42f6-8070-aff79a851863
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183453200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1183453200
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2487591688
Short name T321
Test name
Test status
Simulation time 2288673863 ps
CPU time 22.95 seconds
Started Jun 09 01:07:44 PM PDT 24
Finished Jun 09 01:08:07 PM PDT 24
Peak memory 216868 kb
Host smart-bd950002-11bc-4ad7-8eca-34a31f3ac145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487591688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2487591688
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3724011709
Short name T221
Test name
Test status
Simulation time 768475419714 ps
CPU time 1022.89 seconds
Started Jun 09 01:07:45 PM PDT 24
Finished Jun 09 01:24:48 PM PDT 24
Peak memory 225460 kb
Host smart-805834ad-70c9-4460-a454-bd0ac93177e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724011709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3724011709
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3922230460
Short name T331
Test name
Test status
Simulation time 16468232462 ps
CPU time 46.87 seconds
Started Jun 09 01:07:44 PM PDT 24
Finished Jun 09 01:08:31 PM PDT 24
Peak memory 219052 kb
Host smart-3c7f744c-04de-4331-9d73-cad53a9a85c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922230460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3922230460
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2643322377
Short name T216
Test name
Test status
Simulation time 80403723354 ps
CPU time 34.52 seconds
Started Jun 09 01:07:40 PM PDT 24
Finished Jun 09 01:08:15 PM PDT 24
Peak memory 219112 kb
Host smart-a173daf0-6f5c-43f7-8760-6533be08b090
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2643322377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2643322377
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1746259813
Short name T241
Test name
Test status
Simulation time 36732958065 ps
CPU time 78.09 seconds
Started Jun 09 01:07:39 PM PDT 24
Finished Jun 09 01:08:58 PM PDT 24
Peak memory 216564 kb
Host smart-49cb3ac4-1432-4c3a-b9a6-b80156e6ce4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746259813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1746259813
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3626307440
Short name T50
Test name
Test status
Simulation time 56918409466 ps
CPU time 122.02 seconds
Started Jun 09 01:07:39 PM PDT 24
Finished Jun 09 01:09:41 PM PDT 24
Peak memory 220324 kb
Host smart-489624e0-58a4-4817-8b75-9dfe72df9a39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626307440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3626307440
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1705587936
Short name T200
Test name
Test status
Simulation time 27157607375 ps
CPU time 33.51 seconds
Started Jun 09 01:07:43 PM PDT 24
Finished Jun 09 01:08:17 PM PDT 24
Peak memory 217060 kb
Host smart-7a06de24-77bc-4d18-8831-b394d73bea94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705587936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1705587936
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2615140540
Short name T343
Test name
Test status
Simulation time 37790114369 ps
CPU time 433.53 seconds
Started Jun 09 01:07:48 PM PDT 24
Finished Jun 09 01:15:01 PM PDT 24
Peak memory 237584 kb
Host smart-86dd855a-8a8a-4a80-9321-cbb01d9b00fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615140540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2615140540
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2457943683
Short name T275
Test name
Test status
Simulation time 342868187 ps
CPU time 18.65 seconds
Started Jun 09 01:07:45 PM PDT 24
Finished Jun 09 01:08:04 PM PDT 24
Peak memory 218940 kb
Host smart-5780be16-aee9-4873-a0ae-1cc3992c6809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457943683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2457943683
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1185313174
Short name T313
Test name
Test status
Simulation time 1361586444 ps
CPU time 18.65 seconds
Started Jun 09 01:07:46 PM PDT 24
Finished Jun 09 01:08:05 PM PDT 24
Peak memory 219004 kb
Host smart-51988494-63b1-4951-b373-9d558ad24ed6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1185313174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1185313174
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3195332237
Short name T289
Test name
Test status
Simulation time 17839437278 ps
CPU time 45.4 seconds
Started Jun 09 01:07:46 PM PDT 24
Finished Jun 09 01:08:32 PM PDT 24
Peak memory 217136 kb
Host smart-767400a7-08a8-4598-b303-f5bf07ab0b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195332237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3195332237
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1644345576
Short name T290
Test name
Test status
Simulation time 1295981604 ps
CPU time 48.77 seconds
Started Jun 09 01:07:48 PM PDT 24
Finished Jun 09 01:08:37 PM PDT 24
Peak memory 218964 kb
Host smart-63ff1a95-e14e-4e46-9733-ea3c3964fe49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644345576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1644345576
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2893787763
Short name T197
Test name
Test status
Simulation time 3251095963 ps
CPU time 26.99 seconds
Started Jun 09 01:07:51 PM PDT 24
Finished Jun 09 01:08:19 PM PDT 24
Peak memory 216860 kb
Host smart-15336a60-5472-442b-a522-1c175845246f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893787763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2893787763
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1725542604
Short name T32
Test name
Test status
Simulation time 41236610460 ps
CPU time 538.34 seconds
Started Jun 09 01:07:51 PM PDT 24
Finished Jun 09 01:16:50 PM PDT 24
Peak memory 242436 kb
Host smart-881ac1ad-b2a5-4b43-bcf4-4e4be44afec2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725542604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1725542604
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2069804004
Short name T182
Test name
Test status
Simulation time 30658718875 ps
CPU time 49.44 seconds
Started Jun 09 01:07:52 PM PDT 24
Finished Jun 09 01:08:42 PM PDT 24
Peak memory 219044 kb
Host smart-72b95f9d-7b60-4547-9454-6f7dfac9b7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069804004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2069804004
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.387910397
Short name T159
Test name
Test status
Simulation time 178960503 ps
CPU time 10.39 seconds
Started Jun 09 01:07:51 PM PDT 24
Finished Jun 09 01:08:02 PM PDT 24
Peak memory 218984 kb
Host smart-becc5b97-b474-47c1-a419-d2e59d3a17be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=387910397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.387910397
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.612649275
Short name T324
Test name
Test status
Simulation time 22058920108 ps
CPU time 67.4 seconds
Started Jun 09 01:07:46 PM PDT 24
Finished Jun 09 01:08:54 PM PDT 24
Peak memory 217424 kb
Host smart-334dddb8-0629-4030-b865-a2b92e5f660d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612649275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.612649275
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3686150970
Short name T130
Test name
Test status
Simulation time 2793009921 ps
CPU time 39.58 seconds
Started Jun 09 01:07:53 PM PDT 24
Finished Jun 09 01:08:33 PM PDT 24
Peak memory 218944 kb
Host smart-66f67833-ed4b-4b64-8612-040262f6c270
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686150970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3686150970
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2583362455
Short name T314
Test name
Test status
Simulation time 7690719342 ps
CPU time 30.94 seconds
Started Jun 09 01:07:56 PM PDT 24
Finished Jun 09 01:08:28 PM PDT 24
Peak memory 217108 kb
Host smart-59a64d2b-2f28-438d-91f2-f27cb0ba1c3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583362455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2583362455
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2494254197
Short name T175
Test name
Test status
Simulation time 98756195854 ps
CPU time 492.8 seconds
Started Jun 09 01:07:53 PM PDT 24
Finished Jun 09 01:16:06 PM PDT 24
Peak memory 233932 kb
Host smart-fde95ee9-0de3-4de4-8500-15b5ec59c1e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494254197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2494254197
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.183372483
Short name T140
Test name
Test status
Simulation time 2527743104 ps
CPU time 23.98 seconds
Started Jun 09 01:07:57 PM PDT 24
Finished Jun 09 01:08:22 PM PDT 24
Peak memory 215248 kb
Host smart-94dede6b-729c-4207-82cf-dff1a490f11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183372483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.183372483
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.457190630
Short name T163
Test name
Test status
Simulation time 3938485387 ps
CPU time 21.71 seconds
Started Jun 09 01:07:53 PM PDT 24
Finished Jun 09 01:08:15 PM PDT 24
Peak memory 219012 kb
Host smart-5fcd00cb-61c3-4b8d-9b80-7063928166d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=457190630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.457190630
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2103081814
Short name T187
Test name
Test status
Simulation time 1424134909 ps
CPU time 19.78 seconds
Started Jun 09 01:07:51 PM PDT 24
Finished Jun 09 01:08:11 PM PDT 24
Peak memory 215840 kb
Host smart-817709d3-0fec-43ce-90dc-7a95c343da9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103081814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2103081814
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.257672032
Short name T117
Test name
Test status
Simulation time 5014305876 ps
CPU time 30.81 seconds
Started Jun 09 01:07:51 PM PDT 24
Finished Jun 09 01:08:23 PM PDT 24
Peak memory 213880 kb
Host smart-798741f6-9922-4377-aac2-8a10c22f990c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257672032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.257672032
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2009348477
Short name T146
Test name
Test status
Simulation time 3374455338 ps
CPU time 18.94 seconds
Started Jun 09 01:06:13 PM PDT 24
Finished Jun 09 01:06:32 PM PDT 24
Peak memory 216888 kb
Host smart-2c91e321-4cec-4061-9a70-5c66184722eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009348477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2009348477
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1903716402
Short name T253
Test name
Test status
Simulation time 13293912004 ps
CPU time 264.83 seconds
Started Jun 09 01:06:05 PM PDT 24
Finished Jun 09 01:10:30 PM PDT 24
Peak memory 247320 kb
Host smart-1b9c6ea9-4f09-48bd-869b-b790d9bd84bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903716402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1903716402
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2296133327
Short name T303
Test name
Test status
Simulation time 2816517893 ps
CPU time 36.99 seconds
Started Jun 09 01:06:06 PM PDT 24
Finished Jun 09 01:06:43 PM PDT 24
Peak memory 218964 kb
Host smart-915dbcf3-7d7e-4e32-bbb9-776d4237804f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296133327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2296133327
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1419574445
Short name T261
Test name
Test status
Simulation time 340299698 ps
CPU time 10.62 seconds
Started Jun 09 01:06:06 PM PDT 24
Finished Jun 09 01:06:17 PM PDT 24
Peak memory 218996 kb
Host smart-031f95aa-51c0-47dd-889e-1b51aca4f7e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1419574445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1419574445
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1665714734
Short name T27
Test name
Test status
Simulation time 2807873373 ps
CPU time 130.67 seconds
Started Jun 09 01:06:09 PM PDT 24
Finished Jun 09 01:08:20 PM PDT 24
Peak memory 234560 kb
Host smart-0246984d-5897-44c5-8103-53d6d59ca38c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665714734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1665714734
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3639732090
Short name T167
Test name
Test status
Simulation time 6334176436 ps
CPU time 25 seconds
Started Jun 09 01:06:08 PM PDT 24
Finished Jun 09 01:06:33 PM PDT 24
Peak memory 216180 kb
Host smart-93c2856b-8773-4ca9-ae7e-985644521bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639732090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3639732090
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3234391595
Short name T121
Test name
Test status
Simulation time 11792700427 ps
CPU time 105.83 seconds
Started Jun 09 01:06:04 PM PDT 24
Finished Jun 09 01:07:50 PM PDT 24
Peak memory 227468 kb
Host smart-afca79c8-635c-4fb9-9839-536aace6caa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234391595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3234391595
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.539475902
Short name T224
Test name
Test status
Simulation time 4102690308 ps
CPU time 32.35 seconds
Started Jun 09 01:07:57 PM PDT 24
Finished Jun 09 01:08:30 PM PDT 24
Peak memory 216316 kb
Host smart-8fe2cd0f-8805-47f3-b325-00b3c671e6bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539475902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.539475902
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1921137747
Short name T310
Test name
Test status
Simulation time 4588796061 ps
CPU time 294.35 seconds
Started Jun 09 01:07:59 PM PDT 24
Finished Jun 09 01:12:53 PM PDT 24
Peak memory 233896 kb
Host smart-f4b67f62-a4b6-46b6-8e73-97161350f4c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921137747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1921137747
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2328484852
Short name T295
Test name
Test status
Simulation time 2198875319 ps
CPU time 19.56 seconds
Started Jun 09 01:07:56 PM PDT 24
Finished Jun 09 01:08:16 PM PDT 24
Peak memory 218976 kb
Host smart-32a148cf-e578-4de0-9065-8cecc8dddf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328484852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2328484852
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1380493717
Short name T222
Test name
Test status
Simulation time 13128346275 ps
CPU time 29.06 seconds
Started Jun 09 01:07:58 PM PDT 24
Finished Jun 09 01:08:27 PM PDT 24
Peak memory 219104 kb
Host smart-aaa8a00b-5ab8-414f-9df2-c185c6c10527
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1380493717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1380493717
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.778381336
Short name T2
Test name
Test status
Simulation time 1357303053 ps
CPU time 21.24 seconds
Started Jun 09 01:08:00 PM PDT 24
Finished Jun 09 01:08:21 PM PDT 24
Peak memory 216236 kb
Host smart-bfe52968-8811-4103-afe3-f1fcdb778ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778381336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.778381336
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1566338991
Short name T157
Test name
Test status
Simulation time 17801595121 ps
CPU time 36.34 seconds
Started Jun 09 01:07:55 PM PDT 24
Finished Jun 09 01:08:32 PM PDT 24
Peak memory 216744 kb
Host smart-6b1d7275-0fd3-45bd-9810-3b5a69aaec75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566338991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1566338991
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2326607537
Short name T160
Test name
Test status
Simulation time 5208159867 ps
CPU time 24.23 seconds
Started Jun 09 01:07:58 PM PDT 24
Finished Jun 09 01:08:22 PM PDT 24
Peak memory 217080 kb
Host smart-5530be36-2c2c-499f-ab67-bfbfbfaa0f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326607537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2326607537
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.4281592799
Short name T328
Test name
Test status
Simulation time 188790001870 ps
CPU time 585.69 seconds
Started Jun 09 01:07:58 PM PDT 24
Finished Jun 09 01:17:44 PM PDT 24
Peak memory 240616 kb
Host smart-7cd284be-6805-44c2-a412-83046edff2b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281592799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.4281592799
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3417979454
Short name T134
Test name
Test status
Simulation time 497525863 ps
CPU time 22.53 seconds
Started Jun 09 01:07:56 PM PDT 24
Finished Jun 09 01:08:19 PM PDT 24
Peak memory 218940 kb
Host smart-a976a5ff-45fd-409e-8e5e-8ec27e7280d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417979454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3417979454
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.956272763
Short name T169
Test name
Test status
Simulation time 1468581484 ps
CPU time 12.89 seconds
Started Jun 09 01:07:56 PM PDT 24
Finished Jun 09 01:08:09 PM PDT 24
Peak memory 218452 kb
Host smart-1b2fcef6-3997-490b-832c-ac868e12525e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=956272763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.956272763
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.725634098
Short name T125
Test name
Test status
Simulation time 12299571034 ps
CPU time 56.22 seconds
Started Jun 09 01:07:59 PM PDT 24
Finished Jun 09 01:08:55 PM PDT 24
Peak memory 217292 kb
Host smart-1cf3f78f-078b-4eed-bfed-8e18e72cde86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725634098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.725634098
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.4228624135
Short name T350
Test name
Test status
Simulation time 40436443627 ps
CPU time 52.46 seconds
Started Jun 09 01:07:55 PM PDT 24
Finished Jun 09 01:08:47 PM PDT 24
Peak memory 219076 kb
Host smart-511dc2e3-bc86-4792-878c-cac41a07c707
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228624135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.4228624135
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3908039413
Short name T43
Test name
Test status
Simulation time 119956119514 ps
CPU time 2381.88 seconds
Started Jun 09 01:07:58 PM PDT 24
Finished Jun 09 01:47:41 PM PDT 24
Peak memory 249008 kb
Host smart-1e35500c-d7b7-4f98-8cff-0ef1cfc2f396
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908039413 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3908039413
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2022986581
Short name T171
Test name
Test status
Simulation time 10930200902 ps
CPU time 24.19 seconds
Started Jun 09 01:08:03 PM PDT 24
Finished Jun 09 01:08:28 PM PDT 24
Peak memory 217212 kb
Host smart-d044ba39-c103-4d9c-8392-228286d75a11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022986581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2022986581
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1350339906
Short name T168
Test name
Test status
Simulation time 12226032964 ps
CPU time 241.04 seconds
Started Jun 09 01:08:02 PM PDT 24
Finished Jun 09 01:12:04 PM PDT 24
Peak memory 238340 kb
Host smart-3888ac24-2e99-4e64-a1ff-5a7f3e59a4c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350339906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1350339906
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2900586278
Short name T118
Test name
Test status
Simulation time 1012537794 ps
CPU time 22.15 seconds
Started Jun 09 01:08:03 PM PDT 24
Finished Jun 09 01:08:25 PM PDT 24
Peak memory 218936 kb
Host smart-da8b816a-8144-4b63-b5d2-75c1132f0c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900586278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2900586278
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.4144289075
Short name T315
Test name
Test status
Simulation time 1363096589 ps
CPU time 18.77 seconds
Started Jun 09 01:07:58 PM PDT 24
Finished Jun 09 01:08:17 PM PDT 24
Peak memory 218964 kb
Host smart-cd37717e-48f4-43af-ac91-d2f417248e93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4144289075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.4144289075
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2450173048
Short name T120
Test name
Test status
Simulation time 6786641860 ps
CPU time 59.55 seconds
Started Jun 09 01:07:59 PM PDT 24
Finished Jun 09 01:08:59 PM PDT 24
Peak memory 215072 kb
Host smart-31bcb2ae-d2a7-4783-9b10-804e84c22201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450173048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2450173048
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.901002253
Short name T342
Test name
Test status
Simulation time 17234311330 ps
CPU time 165.51 seconds
Started Jun 09 01:07:57 PM PDT 24
Finished Jun 09 01:10:43 PM PDT 24
Peak memory 227240 kb
Host smart-41308728-7171-4d00-962c-9a4b7be559ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901002253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.901002253
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3202524393
Short name T286
Test name
Test status
Simulation time 74377190022 ps
CPU time 3612.29 seconds
Started Jun 09 01:08:05 PM PDT 24
Finished Jun 09 02:08:18 PM PDT 24
Peak memory 235528 kb
Host smart-9e9618e5-4883-4609-be36-720082b4f945
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202524393 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.3202524393
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.5496916
Short name T317
Test name
Test status
Simulation time 5973449975 ps
CPU time 26.22 seconds
Started Jun 09 01:08:10 PM PDT 24
Finished Jun 09 01:08:36 PM PDT 24
Peak memory 217260 kb
Host smart-45958991-0827-45ba-b3df-b826d5824862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5496916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.5496916
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2795489861
Short name T245
Test name
Test status
Simulation time 64856149825 ps
CPU time 583.67 seconds
Started Jun 09 01:08:01 PM PDT 24
Finished Jun 09 01:17:45 PM PDT 24
Peak memory 225868 kb
Host smart-40615312-c457-44b0-b756-f2fb64483b59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795489861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2795489861
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.840081680
Short name T136
Test name
Test status
Simulation time 15595386905 ps
CPU time 57.53 seconds
Started Jun 09 01:08:01 PM PDT 24
Finished Jun 09 01:08:59 PM PDT 24
Peak memory 218880 kb
Host smart-b354a4fc-a059-4b64-8cdf-df7d13dbe2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840081680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.840081680
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1237052934
Short name T217
Test name
Test status
Simulation time 24148264265 ps
CPU time 29.93 seconds
Started Jun 09 01:08:04 PM PDT 24
Finished Jun 09 01:08:34 PM PDT 24
Peak memory 211688 kb
Host smart-8cc107ed-433e-4981-9a70-2702b3c3f9d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1237052934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1237052934
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.675462143
Short name T149
Test name
Test status
Simulation time 17244576089 ps
CPU time 141.87 seconds
Started Jun 09 01:08:02 PM PDT 24
Finished Jun 09 01:10:24 PM PDT 24
Peak memory 220700 kb
Host smart-e693ccdf-b4fe-4e32-8730-069c358cc2a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675462143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.675462143
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2556719918
Short name T293
Test name
Test status
Simulation time 3277435852 ps
CPU time 27.3 seconds
Started Jun 09 01:08:12 PM PDT 24
Finished Jun 09 01:08:40 PM PDT 24
Peak memory 216760 kb
Host smart-54d56dfd-19d9-4dff-ac8e-8a274111831a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556719918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2556719918
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3897366374
Short name T189
Test name
Test status
Simulation time 1316446139 ps
CPU time 99.12 seconds
Started Jun 09 01:08:08 PM PDT 24
Finished Jun 09 01:09:47 PM PDT 24
Peak memory 237608 kb
Host smart-914d154b-813f-4773-9e0f-9ed4f83f1493
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897366374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3897366374
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3367578707
Short name T208
Test name
Test status
Simulation time 12153081412 ps
CPU time 55.88 seconds
Started Jun 09 01:08:10 PM PDT 24
Finished Jun 09 01:09:06 PM PDT 24
Peak memory 219004 kb
Host smart-7f2e708a-eada-47a0-a1f3-ba4665e493e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367578707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3367578707
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2902299254
Short name T94
Test name
Test status
Simulation time 977742447 ps
CPU time 14.09 seconds
Started Jun 09 01:08:09 PM PDT 24
Finished Jun 09 01:08:24 PM PDT 24
Peak memory 217256 kb
Host smart-988201da-7a62-48ab-aa93-fb7011a1576e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2902299254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2902299254
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1820809612
Short name T349
Test name
Test status
Simulation time 46289780892 ps
CPU time 62.78 seconds
Started Jun 09 01:08:10 PM PDT 24
Finished Jun 09 01:09:13 PM PDT 24
Peak memory 216792 kb
Host smart-b5fdbb0f-14e3-491b-a967-c40c790f8028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820809612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1820809612
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1366733140
Short name T251
Test name
Test status
Simulation time 233204870 ps
CPU time 11.51 seconds
Started Jun 09 01:08:10 PM PDT 24
Finished Jun 09 01:08:22 PM PDT 24
Peak memory 218124 kb
Host smart-f57340fe-7b02-4ee1-bbdb-692f48cda503
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366733140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1366733140
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3229563905
Short name T46
Test name
Test status
Simulation time 395582395533 ps
CPU time 4130.75 seconds
Started Jun 09 01:08:12 PM PDT 24
Finished Jun 09 02:17:03 PM PDT 24
Peak memory 265448 kb
Host smart-adc97201-3df5-4cba-913e-1d22563f3987
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229563905 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.3229563905
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3298758111
Short name T281
Test name
Test status
Simulation time 1195173405 ps
CPU time 16.11 seconds
Started Jun 09 01:08:14 PM PDT 24
Finished Jun 09 01:08:31 PM PDT 24
Peak memory 216828 kb
Host smart-ace7f6b0-1ee6-4787-9dd1-1612dfe613de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298758111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3298758111
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1600670201
Short name T260
Test name
Test status
Simulation time 57651414679 ps
CPU time 576.87 seconds
Started Jun 09 01:08:09 PM PDT 24
Finished Jun 09 01:17:46 PM PDT 24
Peak memory 225436 kb
Host smart-6ae3e5e7-8da9-4841-9227-a7f119d41c92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600670201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1600670201
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3923556072
Short name T277
Test name
Test status
Simulation time 4416253683 ps
CPU time 34.92 seconds
Started Jun 09 01:08:11 PM PDT 24
Finished Jun 09 01:08:46 PM PDT 24
Peak memory 219032 kb
Host smart-edc4ffc5-1f84-461f-b4d3-1390435f05b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923556072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3923556072
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2016491858
Short name T178
Test name
Test status
Simulation time 2872431260 ps
CPU time 26.19 seconds
Started Jun 09 01:08:09 PM PDT 24
Finished Jun 09 01:08:35 PM PDT 24
Peak memory 211068 kb
Host smart-53e4dab7-c1ad-4e32-9a94-8e50824148c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2016491858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2016491858
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3625280616
Short name T204
Test name
Test status
Simulation time 3633979229 ps
CPU time 41.58 seconds
Started Jun 09 01:08:10 PM PDT 24
Finished Jun 09 01:08:52 PM PDT 24
Peak memory 216160 kb
Host smart-419b2346-1def-4c0d-b886-96b490b39485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625280616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3625280616
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3112676535
Short name T144
Test name
Test status
Simulation time 2800542099 ps
CPU time 47.45 seconds
Started Jun 09 01:08:11 PM PDT 24
Finished Jun 09 01:08:59 PM PDT 24
Peak memory 218952 kb
Host smart-3fbc308f-2b18-42a4-ad25-71374d765670
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112676535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3112676535
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2603668653
Short name T348
Test name
Test status
Simulation time 16372425730 ps
CPU time 25.26 seconds
Started Jun 09 01:08:14 PM PDT 24
Finished Jun 09 01:08:40 PM PDT 24
Peak memory 217212 kb
Host smart-babaf18b-2f8b-4a77-9e40-75df8a239212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603668653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2603668653
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4067975400
Short name T225
Test name
Test status
Simulation time 5056950197 ps
CPU time 237.14 seconds
Started Jun 09 01:08:14 PM PDT 24
Finished Jun 09 01:12:12 PM PDT 24
Peak memory 229156 kb
Host smart-a5d71788-3096-46ab-96e6-56caca1698b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067975400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.4067975400
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4228986187
Short name T116
Test name
Test status
Simulation time 15058806288 ps
CPU time 43.03 seconds
Started Jun 09 01:08:14 PM PDT 24
Finished Jun 09 01:08:58 PM PDT 24
Peak memory 219040 kb
Host smart-bae5b1c1-f099-4d81-9aeb-ccc88e40b888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228986187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4228986187
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.731823060
Short name T141
Test name
Test status
Simulation time 2478297112 ps
CPU time 18.68 seconds
Started Jun 09 01:08:13 PM PDT 24
Finished Jun 09 01:08:32 PM PDT 24
Peak memory 211540 kb
Host smart-176e4806-0de2-427f-bc7c-cb81b8f171b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=731823060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.731823060
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2492289570
Short name T133
Test name
Test status
Simulation time 4566804623 ps
CPU time 43.52 seconds
Started Jun 09 01:08:14 PM PDT 24
Finished Jun 09 01:08:58 PM PDT 24
Peak memory 215616 kb
Host smart-c78eface-7a75-4127-8352-43e68e1175e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492289570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2492289570
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2710156864
Short name T356
Test name
Test status
Simulation time 13431567071 ps
CPU time 64.1 seconds
Started Jun 09 01:08:16 PM PDT 24
Finished Jun 09 01:09:21 PM PDT 24
Peak memory 218032 kb
Host smart-1a663ffe-50d2-4513-a1c8-f9d808d2a7fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710156864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2710156864
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2933175691
Short name T154
Test name
Test status
Simulation time 46261941229 ps
CPU time 27.01 seconds
Started Jun 09 01:08:23 PM PDT 24
Finished Jun 09 01:08:50 PM PDT 24
Peak memory 217204 kb
Host smart-fed33f8d-a450-48f0-a52f-29e36c9139c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933175691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2933175691
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.950955553
Short name T226
Test name
Test status
Simulation time 22188264878 ps
CPU time 404.58 seconds
Started Jun 09 01:08:15 PM PDT 24
Finished Jun 09 01:15:00 PM PDT 24
Peak memory 239352 kb
Host smart-891b63a5-48c4-4a58-980f-fd0ff55dd29c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950955553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.950955553
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2579547451
Short name T111
Test name
Test status
Simulation time 32808352364 ps
CPU time 68.51 seconds
Started Jun 09 01:08:21 PM PDT 24
Finished Jun 09 01:09:30 PM PDT 24
Peak memory 218964 kb
Host smart-1e022f89-8f1b-4638-b52b-630f1d4bd926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579547451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2579547451
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2137087770
Short name T195
Test name
Test status
Simulation time 2470708351 ps
CPU time 10.44 seconds
Started Jun 09 01:08:13 PM PDT 24
Finished Jun 09 01:08:24 PM PDT 24
Peak memory 219044 kb
Host smart-dbd3cf36-6296-42ec-83b3-c5818e5025cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2137087770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2137087770
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.319109493
Short name T124
Test name
Test status
Simulation time 457300466 ps
CPU time 19.77 seconds
Started Jun 09 01:08:16 PM PDT 24
Finished Jun 09 01:08:36 PM PDT 24
Peak memory 215812 kb
Host smart-fd4893ea-5171-43b2-b670-3fccf5b61b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319109493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.319109493
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2498886893
Short name T344
Test name
Test status
Simulation time 6878594632 ps
CPU time 89.67 seconds
Started Jun 09 01:08:17 PM PDT 24
Finished Jun 09 01:09:46 PM PDT 24
Peak memory 221136 kb
Host smart-ea840de8-6e8d-47d7-a4b2-518a84319f12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498886893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2498886893
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.3318714482
Short name T47
Test name
Test status
Simulation time 73017336967 ps
CPU time 2576.51 seconds
Started Jun 09 01:08:20 PM PDT 24
Finished Jun 09 01:51:17 PM PDT 24
Peak memory 233008 kb
Host smart-81c016c4-a45e-4e04-8265-f72ce80cb11f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318714482 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.3318714482
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.825269046
Short name T267
Test name
Test status
Simulation time 6396352240 ps
CPU time 27.14 seconds
Started Jun 09 01:08:30 PM PDT 24
Finished Jun 09 01:08:58 PM PDT 24
Peak memory 217160 kb
Host smart-12463174-be20-4733-815a-5baac655e8ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825269046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.825269046
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1328961693
Short name T177
Test name
Test status
Simulation time 232932396744 ps
CPU time 567.25 seconds
Started Jun 09 01:08:19 PM PDT 24
Finished Jun 09 01:17:47 PM PDT 24
Peak memory 234412 kb
Host smart-1451d9fd-fff2-49d6-86f0-95f1b28a287c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328961693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1328961693
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.734556911
Short name T145
Test name
Test status
Simulation time 16436539565 ps
CPU time 71.69 seconds
Started Jun 09 01:08:25 PM PDT 24
Finished Jun 09 01:09:37 PM PDT 24
Peak memory 218908 kb
Host smart-1c159fc3-0fca-42c9-bedd-aac5643cde79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734556911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.734556911
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.673908764
Short name T279
Test name
Test status
Simulation time 2516723732 ps
CPU time 25.1 seconds
Started Jun 09 01:08:20 PM PDT 24
Finished Jun 09 01:08:45 PM PDT 24
Peak memory 219064 kb
Host smart-cfbdc514-c08c-47c4-bed7-9d2850a46078
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=673908764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.673908764
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1987283830
Short name T235
Test name
Test status
Simulation time 52382692298 ps
CPU time 68.09 seconds
Started Jun 09 01:08:19 PM PDT 24
Finished Jun 09 01:09:28 PM PDT 24
Peak memory 217936 kb
Host smart-59d5f717-ba78-4646-b7be-c737083833ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987283830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1987283830
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2348559754
Short name T215
Test name
Test status
Simulation time 4358342733 ps
CPU time 69.73 seconds
Started Jun 09 01:08:20 PM PDT 24
Finished Jun 09 01:09:30 PM PDT 24
Peak memory 227268 kb
Host smart-2d18585b-44f0-47ab-8ff5-82134d763f33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348559754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2348559754
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3473074224
Short name T326
Test name
Test status
Simulation time 1271100844 ps
CPU time 16.42 seconds
Started Jun 09 01:08:31 PM PDT 24
Finished Jun 09 01:08:48 PM PDT 24
Peak memory 216852 kb
Host smart-75e81248-4132-4b05-acb9-7fdea1675cc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473074224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3473074224
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3456942721
Short name T29
Test name
Test status
Simulation time 65979884484 ps
CPU time 364.6 seconds
Started Jun 09 01:08:25 PM PDT 24
Finished Jun 09 01:14:30 PM PDT 24
Peak memory 240616 kb
Host smart-35018f6b-962c-4a60-b37f-6a05be2555f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456942721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3456942721
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1345153217
Short name T262
Test name
Test status
Simulation time 861397514 ps
CPU time 25.17 seconds
Started Jun 09 01:08:26 PM PDT 24
Finished Jun 09 01:08:51 PM PDT 24
Peak memory 218016 kb
Host smart-468a3396-c0ab-414e-b13c-12ef43b3a0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345153217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1345153217
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1711552689
Short name T256
Test name
Test status
Simulation time 1851784871 ps
CPU time 21.53 seconds
Started Jun 09 01:08:26 PM PDT 24
Finished Jun 09 01:08:48 PM PDT 24
Peak memory 218984 kb
Host smart-f71ee512-32cf-4150-a2e3-ba2a2195f324
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1711552689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1711552689
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3736365908
Short name T114
Test name
Test status
Simulation time 363929290 ps
CPU time 20.51 seconds
Started Jun 09 01:08:31 PM PDT 24
Finished Jun 09 01:08:52 PM PDT 24
Peak memory 216336 kb
Host smart-d8cfc5bb-a333-4188-8b23-df8b0f6e2fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736365908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3736365908
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1281110126
Short name T109
Test name
Test status
Simulation time 29570344515 ps
CPU time 68.89 seconds
Started Jun 09 01:08:30 PM PDT 24
Finished Jun 09 01:09:39 PM PDT 24
Peak memory 219080 kb
Host smart-d794a65a-e86b-4bb1-a08f-f43e5e029fc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281110126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1281110126
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.4215211066
Short name T23
Test name
Test status
Simulation time 689663631 ps
CPU time 8.29 seconds
Started Jun 09 01:06:11 PM PDT 24
Finished Jun 09 01:06:19 PM PDT 24
Peak memory 216432 kb
Host smart-0e31a900-9f0c-4acb-b4a4-84c0eb06af8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215211066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.4215211066
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.302734194
Short name T184
Test name
Test status
Simulation time 185592194114 ps
CPU time 718.49 seconds
Started Jun 09 01:06:21 PM PDT 24
Finished Jun 09 01:18:20 PM PDT 24
Peak memory 235208 kb
Host smart-de2fec5b-9011-412c-99b8-cf4b1860d955
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302734194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.302734194
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1205538101
Short name T271
Test name
Test status
Simulation time 8903465511 ps
CPU time 43.48 seconds
Started Jun 09 01:06:11 PM PDT 24
Finished Jun 09 01:06:54 PM PDT 24
Peak memory 219036 kb
Host smart-929f9c7d-5bc9-423a-ac36-329cad0246aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205538101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1205538101
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2766189844
Short name T127
Test name
Test status
Simulation time 178620999 ps
CPU time 10.35 seconds
Started Jun 09 01:06:11 PM PDT 24
Finished Jun 09 01:06:22 PM PDT 24
Peak memory 218976 kb
Host smart-451b2629-b818-4ff7-9cb4-e47a17deac7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2766189844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2766189844
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1331167415
Short name T296
Test name
Test status
Simulation time 33555295737 ps
CPU time 79.32 seconds
Started Jun 09 01:06:13 PM PDT 24
Finished Jun 09 01:07:33 PM PDT 24
Peak memory 216228 kb
Host smart-55164d2b-7bee-40c9-b3df-2c5cb1ba29f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331167415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1331167415
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3376046561
Short name T304
Test name
Test status
Simulation time 37822948989 ps
CPU time 104.47 seconds
Started Jun 09 01:06:12 PM PDT 24
Finished Jun 09 01:07:56 PM PDT 24
Peak memory 227292 kb
Host smart-bf3084bd-ed79-474a-a1a7-87c0a0cc8f40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376046561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3376046561
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3413930235
Short name T354
Test name
Test status
Simulation time 7811845939 ps
CPU time 30.64 seconds
Started Jun 09 01:06:24 PM PDT 24
Finished Jun 09 01:06:55 PM PDT 24
Peak memory 216084 kb
Host smart-adb1af8d-c94a-4666-9da0-9ea18434f8f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413930235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3413930235
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3916443882
Short name T9
Test name
Test status
Simulation time 10630019081 ps
CPU time 178.33 seconds
Started Jun 09 01:06:12 PM PDT 24
Finished Jun 09 01:09:11 PM PDT 24
Peak memory 216444 kb
Host smart-915582c9-318f-4c08-8c28-880a3e1057c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916443882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3916443882
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2855611362
Short name T183
Test name
Test status
Simulation time 32895187469 ps
CPU time 56.18 seconds
Started Jun 09 01:06:11 PM PDT 24
Finished Jun 09 01:07:07 PM PDT 24
Peak memory 219056 kb
Host smart-70d735a2-3db0-4296-a4e5-5e26effb72b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855611362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2855611362
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2146720434
Short name T176
Test name
Test status
Simulation time 740298263 ps
CPU time 15.09 seconds
Started Jun 09 01:06:09 PM PDT 24
Finished Jun 09 01:06:24 PM PDT 24
Peak memory 218784 kb
Host smart-651b7abc-4e8f-42dc-8441-4c3310e9bd8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2146720434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2146720434
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2382074233
Short name T188
Test name
Test status
Simulation time 4211277759 ps
CPU time 46.95 seconds
Started Jun 09 01:06:12 PM PDT 24
Finished Jun 09 01:06:59 PM PDT 24
Peak memory 215944 kb
Host smart-0540b200-f561-4703-b7e3-9782672c1a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382074233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2382074233
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.774280256
Short name T44
Test name
Test status
Simulation time 23881217042 ps
CPU time 8487.62 seconds
Started Jun 09 01:06:18 PM PDT 24
Finished Jun 09 03:27:47 PM PDT 24
Peak memory 235508 kb
Host smart-96043119-0563-4b57-84ef-cea932bedbff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774280256 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.774280256
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.13482122
Short name T165
Test name
Test status
Simulation time 4418589451 ps
CPU time 21.83 seconds
Started Jun 09 01:06:15 PM PDT 24
Finished Jun 09 01:06:37 PM PDT 24
Peak memory 217200 kb
Host smart-92beaa14-c3d4-4420-8890-d840ded30da2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13482122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.13482122
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.885133036
Short name T31
Test name
Test status
Simulation time 2841579209 ps
CPU time 223.01 seconds
Started Jun 09 01:06:24 PM PDT 24
Finished Jun 09 01:10:08 PM PDT 24
Peak memory 236984 kb
Host smart-e97bf59c-7e4b-4724-b37f-049c822f34b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885133036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.885133036
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3274564839
Short name T298
Test name
Test status
Simulation time 31277200545 ps
CPU time 65.1 seconds
Started Jun 09 01:06:18 PM PDT 24
Finished Jun 09 01:07:24 PM PDT 24
Peak memory 219020 kb
Host smart-f5c003a6-20c5-4762-a316-d4f0ff550aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274564839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3274564839
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3795454155
Short name T122
Test name
Test status
Simulation time 696108253 ps
CPU time 10.28 seconds
Started Jun 09 01:06:24 PM PDT 24
Finished Jun 09 01:06:35 PM PDT 24
Peak memory 218980 kb
Host smart-a0dac3c1-3889-4ddb-9353-dc20ccbaf17b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3795454155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3795454155
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3193534692
Short name T196
Test name
Test status
Simulation time 15857777642 ps
CPU time 49.58 seconds
Started Jun 09 01:06:16 PM PDT 24
Finished Jun 09 01:07:06 PM PDT 24
Peak memory 216740 kb
Host smart-175812c0-94fc-4aeb-877a-878e84f255cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193534692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3193534692
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.954699853
Short name T358
Test name
Test status
Simulation time 34127507793 ps
CPU time 145.91 seconds
Started Jun 09 01:06:17 PM PDT 24
Finished Jun 09 01:08:43 PM PDT 24
Peak memory 219792 kb
Host smart-c35ee9c9-41ac-43f9-a9ea-0dacc47ff880
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954699853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.954699853
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3207794891
Short name T311
Test name
Test status
Simulation time 14610072486 ps
CPU time 28.96 seconds
Started Jun 09 01:06:19 PM PDT 24
Finished Jun 09 01:06:48 PM PDT 24
Peak memory 217468 kb
Host smart-17ffe945-e2c0-4fbf-aa9b-83637c130c58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207794891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3207794891
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3691824691
Short name T322
Test name
Test status
Simulation time 11171171250 ps
CPU time 170.91 seconds
Started Jun 09 01:06:23 PM PDT 24
Finished Jun 09 01:09:14 PM PDT 24
Peak memory 225824 kb
Host smart-2a800f00-eaf1-4122-8078-8766f3b18af9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691824691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3691824691
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1531311537
Short name T318
Test name
Test status
Simulation time 2570581835 ps
CPU time 35.36 seconds
Started Jun 09 01:06:15 PM PDT 24
Finished Jun 09 01:06:51 PM PDT 24
Peak memory 218996 kb
Host smart-29d3f845-ab97-47bc-924a-666496d5a309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531311537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1531311537
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2378501493
Short name T142
Test name
Test status
Simulation time 3609876246 ps
CPU time 30.48 seconds
Started Jun 09 01:06:18 PM PDT 24
Finished Jun 09 01:06:48 PM PDT 24
Peak memory 219044 kb
Host smart-cdda9f8d-c72e-432b-89ac-1151a384aed9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2378501493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2378501493
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2271320474
Short name T185
Test name
Test status
Simulation time 8605486337 ps
CPU time 33.42 seconds
Started Jun 09 01:06:14 PM PDT 24
Finished Jun 09 01:06:48 PM PDT 24
Peak memory 215748 kb
Host smart-f3d54e5d-be8c-4472-9c06-8a70082c5601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271320474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2271320474
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.946213536
Short name T257
Test name
Test status
Simulation time 10998593694 ps
CPU time 85.92 seconds
Started Jun 09 01:06:18 PM PDT 24
Finished Jun 09 01:07:45 PM PDT 24
Peak memory 221900 kb
Host smart-a086a0de-09ae-405f-b929-f646e3f7bdc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946213536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.946213536
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2489606825
Short name T158
Test name
Test status
Simulation time 3180231523 ps
CPU time 26.22 seconds
Started Jun 09 01:06:21 PM PDT 24
Finished Jun 09 01:06:47 PM PDT 24
Peak memory 216864 kb
Host smart-de05743d-94e1-4162-92d1-0ec9e32471f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489606825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2489606825
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.176270423
Short name T278
Test name
Test status
Simulation time 8043598460 ps
CPU time 159.15 seconds
Started Jun 09 01:06:25 PM PDT 24
Finished Jun 09 01:09:04 PM PDT 24
Peak memory 239056 kb
Host smart-f6872638-8649-442e-a4d0-50696fabd144
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176270423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.176270423
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3137801770
Short name T25
Test name
Test status
Simulation time 1321321562 ps
CPU time 18.67 seconds
Started Jun 09 01:06:21 PM PDT 24
Finished Jun 09 01:06:40 PM PDT 24
Peak memory 218940 kb
Host smart-f5f2fa54-0294-47fa-ba7c-25a2e4f4cb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137801770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3137801770
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.116956699
Short name T132
Test name
Test status
Simulation time 184501370 ps
CPU time 10.46 seconds
Started Jun 09 01:06:17 PM PDT 24
Finished Jun 09 01:06:28 PM PDT 24
Peak memory 218984 kb
Host smart-4eb3ab5f-8110-422a-a0b6-186cc540368b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=116956699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.116956699
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2362219159
Short name T172
Test name
Test status
Simulation time 6784697784 ps
CPU time 39.37 seconds
Started Jun 09 01:06:23 PM PDT 24
Finished Jun 09 01:07:03 PM PDT 24
Peak memory 216012 kb
Host smart-dee74c7c-0eff-4c9b-89e1-5ab9bafd8e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362219159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2362219159
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.550884267
Short name T234
Test name
Test status
Simulation time 23658492428 ps
CPU time 114.5 seconds
Started Jun 09 01:06:19 PM PDT 24
Finished Jun 09 01:08:14 PM PDT 24
Peak memory 217884 kb
Host smart-5da34565-7fb7-4b88-8a57-3aba38caf4e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550884267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.550884267
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.994990533
Short name T45
Test name
Test status
Simulation time 175823555677 ps
CPU time 1589.36 seconds
Started Jun 09 01:06:24 PM PDT 24
Finished Jun 09 01:32:54 PM PDT 24
Peak memory 243756 kb
Host smart-0906c31e-ded5-400d-85d5-1253643b4a9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994990533 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.994990533
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%