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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.33 96.89 92.28 97.72 100.00 98.62 97.45 98.37


Total test records in report: 457
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T301 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3097192973 Jun 10 07:42:06 PM PDT 24 Jun 10 07:44:34 PM PDT 24 2096018361 ps
T302 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.99053009 Jun 10 07:41:04 PM PDT 24 Jun 10 07:45:00 PM PDT 24 8132010556 ps
T303 /workspace/coverage/default/35.rom_ctrl_smoke.775426439 Jun 10 07:42:20 PM PDT 24 Jun 10 07:43:08 PM PDT 24 14351004111 ps
T304 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1576232871 Jun 10 07:42:09 PM PDT 24 Jun 10 07:46:34 PM PDT 24 13081662463 ps
T305 /workspace/coverage/default/45.rom_ctrl_smoke.3462896546 Jun 10 07:42:44 PM PDT 24 Jun 10 07:43:05 PM PDT 24 1264587180 ps
T306 /workspace/coverage/default/42.rom_ctrl_stress_all.3977770432 Jun 10 07:42:29 PM PDT 24 Jun 10 07:44:05 PM PDT 24 6895527982 ps
T307 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3004254325 Jun 10 07:42:06 PM PDT 24 Jun 10 07:42:29 PM PDT 24 5979986328 ps
T308 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1103111891 Jun 10 07:41:44 PM PDT 24 Jun 10 07:42:03 PM PDT 24 2389700533 ps
T309 /workspace/coverage/default/40.rom_ctrl_smoke.4293773794 Jun 10 07:42:30 PM PDT 24 Jun 10 07:43:30 PM PDT 24 23631128766 ps
T310 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3432096473 Jun 10 07:40:52 PM PDT 24 Jun 10 07:41:29 PM PDT 24 16481052980 ps
T311 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2307338370 Jun 10 07:41:25 PM PDT 24 Jun 10 07:42:21 PM PDT 24 5577197476 ps
T312 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.4016488469 Jun 10 07:42:01 PM PDT 24 Jun 10 07:42:37 PM PDT 24 4900830259 ps
T313 /workspace/coverage/default/30.rom_ctrl_smoke.1636096433 Jun 10 07:42:02 PM PDT 24 Jun 10 07:43:16 PM PDT 24 5817121476 ps
T314 /workspace/coverage/default/44.rom_ctrl_alert_test.988022661 Jun 10 07:42:39 PM PDT 24 Jun 10 07:43:01 PM PDT 24 1654843952 ps
T315 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.4185777811 Jun 10 07:42:46 PM PDT 24 Jun 10 07:43:36 PM PDT 24 17750536901 ps
T316 /workspace/coverage/default/3.rom_ctrl_smoke.2437092008 Jun 10 07:41:07 PM PDT 24 Jun 10 07:41:57 PM PDT 24 4675550358 ps
T317 /workspace/coverage/default/7.rom_ctrl_stress_all.2051021314 Jun 10 07:41:07 PM PDT 24 Jun 10 07:42:18 PM PDT 24 7195089736 ps
T318 /workspace/coverage/default/12.rom_ctrl_alert_test.396583556 Jun 10 07:41:20 PM PDT 24 Jun 10 07:41:56 PM PDT 24 4100791561 ps
T319 /workspace/coverage/default/9.rom_ctrl_alert_test.368014424 Jun 10 07:41:15 PM PDT 24 Jun 10 07:41:47 PM PDT 24 7021695608 ps
T320 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2496425874 Jun 10 07:41:06 PM PDT 24 Jun 10 07:41:19 PM PDT 24 790901125 ps
T321 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.526110821 Jun 10 07:41:20 PM PDT 24 Jun 10 07:41:50 PM PDT 24 11708426249 ps
T322 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1779068206 Jun 10 07:41:48 PM PDT 24 Jun 10 07:42:17 PM PDT 24 22551174559 ps
T323 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1445801731 Jun 10 07:41:05 PM PDT 24 Jun 10 07:50:17 PM PDT 24 181538474414 ps
T324 /workspace/coverage/default/6.rom_ctrl_alert_test.1419578917 Jun 10 07:41:07 PM PDT 24 Jun 10 07:41:28 PM PDT 24 6435182595 ps
T325 /workspace/coverage/default/39.rom_ctrl_alert_test.821092520 Jun 10 07:42:28 PM PDT 24 Jun 10 07:43:03 PM PDT 24 14806419547 ps
T326 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.4264829829 Jun 10 07:41:14 PM PDT 24 Jun 10 07:52:32 PM PDT 24 72663669934 ps
T327 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1525877715 Jun 10 07:42:36 PM PDT 24 Jun 10 07:42:50 PM PDT 24 184306318 ps
T328 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4043246473 Jun 10 07:41:31 PM PDT 24 Jun 10 07:41:59 PM PDT 24 3039573664 ps
T329 /workspace/coverage/default/4.rom_ctrl_smoke.3336533886 Jun 10 07:41:07 PM PDT 24 Jun 10 07:42:04 PM PDT 24 26214040352 ps
T330 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2792553439 Jun 10 07:41:50 PM PDT 24 Jun 10 07:49:03 PM PDT 24 207286052327 ps
T331 /workspace/coverage/default/13.rom_ctrl_alert_test.2686146511 Jun 10 07:41:27 PM PDT 24 Jun 10 07:41:44 PM PDT 24 3113717703 ps
T332 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2322042243 Jun 10 07:42:38 PM PDT 24 Jun 10 07:43:13 PM PDT 24 13426461814 ps
T333 /workspace/coverage/default/7.rom_ctrl_alert_test.1004176955 Jun 10 07:41:04 PM PDT 24 Jun 10 07:41:37 PM PDT 24 4001979908 ps
T334 /workspace/coverage/default/43.rom_ctrl_alert_test.1723129566 Jun 10 07:42:36 PM PDT 24 Jun 10 07:42:57 PM PDT 24 1299785712 ps
T335 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2099234434 Jun 10 07:41:26 PM PDT 24 Jun 10 07:47:35 PM PDT 24 227526589531 ps
T336 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4169976191 Jun 10 07:42:50 PM PDT 24 Jun 10 07:43:12 PM PDT 24 347200955 ps
T337 /workspace/coverage/default/13.rom_ctrl_stress_all.2383413857 Jun 10 07:41:24 PM PDT 24 Jun 10 07:42:28 PM PDT 24 6709671545 ps
T338 /workspace/coverage/default/16.rom_ctrl_smoke.505978066 Jun 10 07:41:32 PM PDT 24 Jun 10 07:42:37 PM PDT 24 60627599750 ps
T339 /workspace/coverage/default/5.rom_ctrl_alert_test.3969106107 Jun 10 07:41:04 PM PDT 24 Jun 10 07:41:22 PM PDT 24 2467210203 ps
T340 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1903532335 Jun 10 07:42:19 PM PDT 24 Jun 10 07:42:54 PM PDT 24 2170741848 ps
T341 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3159980178 Jun 10 07:42:19 PM PDT 24 Jun 10 07:50:00 PM PDT 24 139824248720 ps
T342 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2900767669 Jun 10 07:42:29 PM PDT 24 Jun 10 07:43:41 PM PDT 24 34231130553 ps
T343 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4086224370 Jun 10 07:41:40 PM PDT 24 Jun 10 07:49:09 PM PDT 24 28370083690 ps
T344 /workspace/coverage/default/31.rom_ctrl_smoke.3281581646 Jun 10 07:42:05 PM PDT 24 Jun 10 07:43:04 PM PDT 24 4953123107 ps
T345 /workspace/coverage/default/45.rom_ctrl_stress_all.2059148664 Jun 10 07:42:38 PM PDT 24 Jun 10 07:43:41 PM PDT 24 3547146264 ps
T346 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.512319608 Jun 10 07:42:00 PM PDT 24 Jun 10 07:43:10 PM PDT 24 34575112943 ps
T347 /workspace/coverage/default/11.rom_ctrl_stress_all.2174750788 Jun 10 07:41:15 PM PDT 24 Jun 10 07:41:48 PM PDT 24 2029930429 ps
T348 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2463383847 Jun 10 07:42:29 PM PDT 24 Jun 10 07:46:39 PM PDT 24 5968597556 ps
T349 /workspace/coverage/default/17.rom_ctrl_smoke.1037312219 Jun 10 07:41:32 PM PDT 24 Jun 10 07:42:03 PM PDT 24 1978485473 ps
T350 /workspace/coverage/default/14.rom_ctrl_alert_test.4002033458 Jun 10 07:41:32 PM PDT 24 Jun 10 07:42:06 PM PDT 24 4178734330 ps
T351 /workspace/coverage/default/47.rom_ctrl_smoke.3087096536 Jun 10 07:42:45 PM PDT 24 Jun 10 07:43:40 PM PDT 24 4862634618 ps
T352 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1601800166 Jun 10 07:40:52 PM PDT 24 Jun 10 07:41:31 PM PDT 24 11593939995 ps
T353 /workspace/coverage/default/40.rom_ctrl_alert_test.1778355617 Jun 10 07:42:27 PM PDT 24 Jun 10 07:42:40 PM PDT 24 887848349 ps
T354 /workspace/coverage/default/21.rom_ctrl_stress_all.2231488539 Jun 10 07:41:39 PM PDT 24 Jun 10 07:43:00 PM PDT 24 6635302294 ps
T355 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.290935948 Jun 10 07:41:06 PM PDT 24 Jun 10 07:42:14 PM PDT 24 27286354801 ps
T356 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.863092988 Jun 10 07:41:06 PM PDT 24 Jun 10 07:57:28 PM PDT 24 184654837749 ps
T357 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.94687398 Jun 10 07:42:30 PM PDT 24 Jun 10 07:52:08 PM PDT 24 52215831942 ps
T358 /workspace/coverage/default/26.rom_ctrl_smoke.3767994942 Jun 10 07:41:51 PM PDT 24 Jun 10 07:42:37 PM PDT 24 5267861116 ps
T359 /workspace/coverage/default/2.rom_ctrl_alert_test.2691734243 Jun 10 07:41:04 PM PDT 24 Jun 10 07:41:35 PM PDT 24 15708982618 ps
T360 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1412638573 Jun 10 07:42:36 PM PDT 24 Jun 10 07:43:10 PM PDT 24 6185558022 ps
T361 /workspace/coverage/default/34.rom_ctrl_stress_all.2876251855 Jun 10 07:42:10 PM PDT 24 Jun 10 07:42:53 PM PDT 24 54209226175 ps
T55 /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2455076611 Jun 10 07:42:07 PM PDT 24 Jun 10 08:21:07 PM PDT 24 333351926414 ps
T59 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.791316117 Jun 10 07:33:43 PM PDT 24 Jun 10 07:33:54 PM PDT 24 172603844 ps
T60 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.4129897026 Jun 10 07:33:55 PM PDT 24 Jun 10 07:34:10 PM PDT 24 229302648 ps
T362 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.830800294 Jun 10 07:33:42 PM PDT 24 Jun 10 07:34:02 PM PDT 24 3059789196 ps
T61 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2931119944 Jun 10 07:34:03 PM PDT 24 Jun 10 07:35:02 PM PDT 24 1071144540 ps
T56 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.788410499 Jun 10 07:34:13 PM PDT 24 Jun 10 07:35:50 PM PDT 24 39029353211 ps
T66 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.268105526 Jun 10 07:33:53 PM PDT 24 Jun 10 07:36:58 PM PDT 24 23079773504 ps
T57 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1542170183 Jun 10 07:33:53 PM PDT 24 Jun 10 07:35:31 PM PDT 24 3933491840 ps
T65 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2266418958 Jun 10 07:33:53 PM PDT 24 Jun 10 07:34:17 PM PDT 24 2007142174 ps
T67 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2261640405 Jun 10 07:34:05 PM PDT 24 Jun 10 07:37:07 PM PDT 24 46989984263 ps
T110 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3198357240 Jun 10 07:33:43 PM PDT 24 Jun 10 07:34:16 PM PDT 24 4250767478 ps
T101 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.4110714445 Jun 10 07:34:10 PM PDT 24 Jun 10 07:34:35 PM PDT 24 2496894083 ps
T111 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2067090255 Jun 10 07:34:10 PM PDT 24 Jun 10 07:35:09 PM PDT 24 5154037639 ps
T102 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3420550477 Jun 10 07:34:00 PM PDT 24 Jun 10 07:34:32 PM PDT 24 15392664815 ps
T112 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2730960122 Jun 10 07:34:04 PM PDT 24 Jun 10 07:35:23 PM PDT 24 3119512553 ps
T58 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1839428630 Jun 10 07:34:03 PM PDT 24 Jun 10 07:35:47 PM PDT 24 7309019554 ps
T68 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.423840222 Jun 10 07:34:10 PM PDT 24 Jun 10 07:34:38 PM PDT 24 13652823196 ps
T123 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1595057077 Jun 10 07:34:11 PM PDT 24 Jun 10 07:35:40 PM PDT 24 932453090 ps
T363 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1366999004 Jun 10 07:33:43 PM PDT 24 Jun 10 07:34:02 PM PDT 24 2238606430 ps
T364 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.39137403 Jun 10 07:33:47 PM PDT 24 Jun 10 07:34:27 PM PDT 24 13741401006 ps
T365 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1598817329 Jun 10 07:33:50 PM PDT 24 Jun 10 07:34:43 PM PDT 24 2061267751 ps
T366 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3471756352 Jun 10 07:34:02 PM PDT 24 Jun 10 07:34:30 PM PDT 24 2860632479 ps
T367 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.504865270 Jun 10 07:34:06 PM PDT 24 Jun 10 07:34:39 PM PDT 24 3135953500 ps
T120 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.351517172 Jun 10 07:34:02 PM PDT 24 Jun 10 07:35:42 PM PDT 24 7339587499 ps
T368 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.169679662 Jun 10 07:34:03 PM PDT 24 Jun 10 07:34:27 PM PDT 24 2310988596 ps
T69 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.369119795 Jun 10 07:34:12 PM PDT 24 Jun 10 07:35:33 PM PDT 24 6859800234 ps
T121 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3916770094 Jun 10 07:33:53 PM PDT 24 Jun 10 07:35:22 PM PDT 24 1062199973 ps
T369 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2242205880 Jun 10 07:33:55 PM PDT 24 Jun 10 07:34:25 PM PDT 24 35058826100 ps
T70 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.865461297 Jun 10 07:33:55 PM PDT 24 Jun 10 07:34:23 PM PDT 24 3104009205 ps
T370 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.592244320 Jun 10 07:33:42 PM PDT 24 Jun 10 07:34:16 PM PDT 24 4290158638 ps
T371 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1898009517 Jun 10 07:34:14 PM PDT 24 Jun 10 07:34:26 PM PDT 24 389516926 ps
T71 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2522508502 Jun 10 07:34:03 PM PDT 24 Jun 10 07:34:14 PM PDT 24 687721515 ps
T372 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1575238022 Jun 10 07:33:56 PM PDT 24 Jun 10 07:34:31 PM PDT 24 4347762928 ps
T115 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3119859009 Jun 10 07:33:55 PM PDT 24 Jun 10 07:36:43 PM PDT 24 2342235737 ps
T373 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.691862813 Jun 10 07:33:52 PM PDT 24 Jun 10 07:34:08 PM PDT 24 694299778 ps
T374 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3768016777 Jun 10 07:34:05 PM PDT 24 Jun 10 07:34:22 PM PDT 24 8179642766 ps
T375 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.75203216 Jun 10 07:33:53 PM PDT 24 Jun 10 07:34:15 PM PDT 24 1804797713 ps
T376 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1846220361 Jun 10 07:33:58 PM PDT 24 Jun 10 07:34:13 PM PDT 24 345903241 ps
T377 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2379102374 Jun 10 07:34:04 PM PDT 24 Jun 10 07:34:14 PM PDT 24 688383725 ps
T103 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.163645643 Jun 10 07:33:44 PM PDT 24 Jun 10 07:33:58 PM PDT 24 3167089723 ps
T378 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3805040298 Jun 10 07:34:07 PM PDT 24 Jun 10 07:34:36 PM PDT 24 8470947498 ps
T379 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1228880659 Jun 10 07:33:58 PM PDT 24 Jun 10 07:34:10 PM PDT 24 529666293 ps
T72 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3611944965 Jun 10 07:33:47 PM PDT 24 Jun 10 07:34:27 PM PDT 24 705947710 ps
T73 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.347160170 Jun 10 07:33:48 PM PDT 24 Jun 10 07:34:19 PM PDT 24 12899047672 ps
T380 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.365589965 Jun 10 07:34:13 PM PDT 24 Jun 10 07:34:28 PM PDT 24 1032377949 ps
T116 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2755290885 Jun 10 07:34:01 PM PDT 24 Jun 10 07:36:54 PM PDT 24 3164345544 ps
T381 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1957797816 Jun 10 07:34:03 PM PDT 24 Jun 10 07:34:19 PM PDT 24 4304291098 ps
T104 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3973993806 Jun 10 07:34:04 PM PDT 24 Jun 10 07:34:23 PM PDT 24 1684161458 ps
T82 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3242981740 Jun 10 07:33:52 PM PDT 24 Jun 10 07:34:31 PM PDT 24 6844334123 ps
T105 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.889724622 Jun 10 07:33:54 PM PDT 24 Jun 10 07:34:27 PM PDT 24 4019447886 ps
T382 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3440782021 Jun 10 07:33:58 PM PDT 24 Jun 10 07:34:14 PM PDT 24 2049395105 ps
T106 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2590811683 Jun 10 07:34:04 PM PDT 24 Jun 10 07:34:31 PM PDT 24 11547565736 ps
T83 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2821042227 Jun 10 07:33:46 PM PDT 24 Jun 10 07:34:15 PM PDT 24 2576064879 ps
T383 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2903785767 Jun 10 07:33:51 PM PDT 24 Jun 10 07:34:05 PM PDT 24 689597559 ps
T107 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3331442763 Jun 10 07:33:43 PM PDT 24 Jun 10 07:34:11 PM PDT 24 3690468220 ps
T84 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.543457781 Jun 10 07:34:03 PM PDT 24 Jun 10 07:37:10 PM PDT 24 49173728191 ps
T108 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2739452566 Jun 10 07:33:42 PM PDT 24 Jun 10 07:34:09 PM PDT 24 10810891295 ps
T384 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2183333800 Jun 10 07:33:51 PM PDT 24 Jun 10 07:34:07 PM PDT 24 956227300 ps
T85 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1570026835 Jun 10 07:33:43 PM PDT 24 Jun 10 07:34:17 PM PDT 24 31965707501 ps
T385 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2665594209 Jun 10 07:33:52 PM PDT 24 Jun 10 07:35:16 PM PDT 24 301177432 ps
T386 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1020367014 Jun 10 07:33:41 PM PDT 24 Jun 10 07:34:11 PM PDT 24 1999085571 ps
T89 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3441266925 Jun 10 07:33:41 PM PDT 24 Jun 10 07:34:21 PM PDT 24 27947967046 ps
T387 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3744280922 Jun 10 07:34:04 PM PDT 24 Jun 10 07:34:25 PM PDT 24 6255073083 ps
T388 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2673733337 Jun 10 07:34:03 PM PDT 24 Jun 10 07:34:32 PM PDT 24 11154188584 ps
T389 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2737732441 Jun 10 07:33:46 PM PDT 24 Jun 10 07:34:03 PM PDT 24 442662721 ps
T118 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.16420339 Jun 10 07:33:40 PM PDT 24 Jun 10 07:36:36 PM PDT 24 7270086544 ps
T390 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.215409985 Jun 10 07:33:46 PM PDT 24 Jun 10 07:34:06 PM PDT 24 5616065439 ps
T391 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1262811164 Jun 10 07:33:54 PM PDT 24 Jun 10 07:35:18 PM PDT 24 27372538041 ps
T127 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3509868462 Jun 10 07:33:46 PM PDT 24 Jun 10 07:35:18 PM PDT 24 14110295962 ps
T392 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.199764695 Jun 10 07:34:03 PM PDT 24 Jun 10 07:34:16 PM PDT 24 234635380 ps
T393 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2221464810 Jun 10 07:34:04 PM PDT 24 Jun 10 07:35:21 PM PDT 24 12091354988 ps
T394 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2258799371 Jun 10 07:34:10 PM PDT 24 Jun 10 07:34:33 PM PDT 24 5984212344 ps
T395 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2541223175 Jun 10 07:34:03 PM PDT 24 Jun 10 07:34:28 PM PDT 24 10374439825 ps
T396 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1486265903 Jun 10 07:33:54 PM PDT 24 Jun 10 07:34:04 PM PDT 24 589957658 ps
T397 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2136332842 Jun 10 07:34:02 PM PDT 24 Jun 10 07:34:16 PM PDT 24 1939961489 ps
T398 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3914603221 Jun 10 07:33:40 PM PDT 24 Jun 10 07:34:11 PM PDT 24 7204095484 ps
T399 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.588209341 Jun 10 07:33:54 PM PDT 24 Jun 10 07:34:19 PM PDT 24 2298820596 ps
T126 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1210912787 Jun 10 07:33:48 PM PDT 24 Jun 10 07:35:25 PM PDT 24 26662850478 ps
T400 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4261842929 Jun 10 07:34:09 PM PDT 24 Jun 10 07:34:37 PM PDT 24 2931158486 ps
T401 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.246184767 Jun 10 07:34:05 PM PDT 24 Jun 10 07:34:20 PM PDT 24 591358769 ps
T402 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3735434903 Jun 10 07:33:46 PM PDT 24 Jun 10 07:33:57 PM PDT 24 174406065 ps
T403 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.917890699 Jun 10 07:33:44 PM PDT 24 Jun 10 07:34:07 PM PDT 24 3994401357 ps
T86 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1270385452 Jun 10 07:33:55 PM PDT 24 Jun 10 07:34:15 PM PDT 24 1401739238 ps
T404 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.51107213 Jun 10 07:33:53 PM PDT 24 Jun 10 07:35:17 PM PDT 24 1997163198 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.942249271 Jun 10 07:33:46 PM PDT 24 Jun 10 07:34:13 PM PDT 24 5690534588 ps
T406 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1275222049 Jun 10 07:33:46 PM PDT 24 Jun 10 07:35:13 PM PDT 24 8048637308 ps
T124 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.849847229 Jun 10 07:33:44 PM PDT 24 Jun 10 07:35:29 PM PDT 24 10920693998 ps
T407 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1626320370 Jun 10 07:33:43 PM PDT 24 Jun 10 07:33:58 PM PDT 24 1865782167 ps
T408 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.655243287 Jun 10 07:33:54 PM PDT 24 Jun 10 07:35:38 PM PDT 24 77151298108 ps
T409 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.792238469 Jun 10 07:33:48 PM PDT 24 Jun 10 07:34:08 PM PDT 24 1645128665 ps
T410 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.793528651 Jun 10 07:34:00 PM PDT 24 Jun 10 07:34:26 PM PDT 24 47395500805 ps
T411 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.380381870 Jun 10 07:33:53 PM PDT 24 Jun 10 07:34:09 PM PDT 24 1424377825 ps
T412 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3567336235 Jun 10 07:33:53 PM PDT 24 Jun 10 07:34:15 PM PDT 24 22813571252 ps
T413 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3428206836 Jun 10 07:33:53 PM PDT 24 Jun 10 07:35:02 PM PDT 24 4424714489 ps
T414 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.73086030 Jun 10 07:33:52 PM PDT 24 Jun 10 07:34:22 PM PDT 24 3483589259 ps
T415 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2510370609 Jun 10 07:33:57 PM PDT 24 Jun 10 07:34:14 PM PDT 24 450744060 ps
T416 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3448669529 Jun 10 07:33:53 PM PDT 24 Jun 10 07:34:21 PM PDT 24 11757670063 ps
T417 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2452196204 Jun 10 07:33:45 PM PDT 24 Jun 10 07:34:18 PM PDT 24 3065851118 ps
T418 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1885314545 Jun 10 07:33:44 PM PDT 24 Jun 10 07:34:20 PM PDT 24 4236913154 ps
T419 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.163479232 Jun 10 07:33:41 PM PDT 24 Jun 10 07:36:17 PM PDT 24 16983307587 ps
T420 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1174483241 Jun 10 07:34:02 PM PDT 24 Jun 10 07:34:12 PM PDT 24 868541922 ps
T421 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.131825338 Jun 10 07:33:42 PM PDT 24 Jun 10 07:33:53 PM PDT 24 361113775 ps
T90 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1390668880 Jun 10 07:33:46 PM PDT 24 Jun 10 07:34:21 PM PDT 24 61021012674 ps
T422 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1458159006 Jun 10 07:33:44 PM PDT 24 Jun 10 07:34:17 PM PDT 24 6311712670 ps
T423 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.13890567 Jun 10 07:33:55 PM PDT 24 Jun 10 07:34:10 PM PDT 24 677425342 ps
T424 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2644433802 Jun 10 07:33:45 PM PDT 24 Jun 10 07:34:15 PM PDT 24 12496043813 ps
T425 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4092422587 Jun 10 07:33:50 PM PDT 24 Jun 10 07:34:04 PM PDT 24 7354392962 ps
T426 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1783907648 Jun 10 07:33:59 PM PDT 24 Jun 10 07:34:25 PM PDT 24 13055949310 ps
T427 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2924858200 Jun 10 07:34:02 PM PDT 24 Jun 10 07:34:28 PM PDT 24 4106182246 ps
T428 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1718725713 Jun 10 07:33:52 PM PDT 24 Jun 10 07:35:46 PM PDT 24 40362090320 ps
T117 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3257187511 Jun 10 07:33:54 PM PDT 24 Jun 10 07:35:18 PM PDT 24 246275916 ps
T429 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1468790318 Jun 10 07:33:46 PM PDT 24 Jun 10 07:33:57 PM PDT 24 762861792 ps
T430 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.976800556 Jun 10 07:33:55 PM PDT 24 Jun 10 07:34:08 PM PDT 24 170692809 ps
T91 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1718597540 Jun 10 07:34:06 PM PDT 24 Jun 10 07:35:53 PM PDT 24 11852429632 ps
T431 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2867966312 Jun 10 07:33:51 PM PDT 24 Jun 10 07:34:00 PM PDT 24 1833615756 ps
T432 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2559684487 Jun 10 07:33:42 PM PDT 24 Jun 10 07:34:15 PM PDT 24 41103558795 ps
T433 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1215005388 Jun 10 07:34:01 PM PDT 24 Jun 10 07:34:12 PM PDT 24 673644529 ps
T434 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3563904252 Jun 10 07:33:53 PM PDT 24 Jun 10 07:34:16 PM PDT 24 9194845483 ps
T87 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1481913201 Jun 10 07:33:56 PM PDT 24 Jun 10 07:35:53 PM PDT 24 13270036439 ps
T435 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2949137467 Jun 10 07:34:02 PM PDT 24 Jun 10 07:34:14 PM PDT 24 273128185 ps
T436 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.814975124 Jun 10 07:33:46 PM PDT 24 Jun 10 07:34:19 PM PDT 24 17365025552 ps
T437 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2581892348 Jun 10 07:33:54 PM PDT 24 Jun 10 07:34:05 PM PDT 24 331659060 ps
T119 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.685467302 Jun 10 07:34:01 PM PDT 24 Jun 10 07:36:40 PM PDT 24 378198042 ps
T438 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1243460546 Jun 10 07:34:03 PM PDT 24 Jun 10 07:34:31 PM PDT 24 5154712142 ps
T439 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2344636001 Jun 10 07:34:02 PM PDT 24 Jun 10 07:34:12 PM PDT 24 687701517 ps
T440 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2879256500 Jun 10 07:33:51 PM PDT 24 Jun 10 07:34:04 PM PDT 24 3285154949 ps
T441 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3426949636 Jun 10 07:34:04 PM PDT 24 Jun 10 07:34:15 PM PDT 24 170903651 ps
T442 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3617450216 Jun 10 07:34:04 PM PDT 24 Jun 10 07:34:33 PM PDT 24 13630351591 ps
T443 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3200163924 Jun 10 07:33:53 PM PDT 24 Jun 10 07:34:17 PM PDT 24 23628076726 ps
T444 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1814777824 Jun 10 07:33:53 PM PDT 24 Jun 10 07:35:31 PM PDT 24 2604351112 ps
T445 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.181668699 Jun 10 07:33:43 PM PDT 24 Jun 10 07:34:03 PM PDT 24 2452906584 ps
T125 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3669449902 Jun 10 07:33:51 PM PDT 24 Jun 10 07:35:27 PM PDT 24 12019179619 ps
T446 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.666665743 Jun 10 07:33:53 PM PDT 24 Jun 10 07:34:16 PM PDT 24 7852631517 ps
T447 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1462430424 Jun 10 07:33:43 PM PDT 24 Jun 10 07:33:54 PM PDT 24 339268689 ps
T448 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1207684100 Jun 10 07:33:53 PM PDT 24 Jun 10 07:34:22 PM PDT 24 3126158696 ps
T122 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4231406017 Jun 10 07:34:02 PM PDT 24 Jun 10 07:35:46 PM PDT 24 3721512439 ps
T449 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.135490534 Jun 10 07:33:42 PM PDT 24 Jun 10 07:34:11 PM PDT 24 8856846241 ps
T450 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4218522192 Jun 10 07:34:03 PM PDT 24 Jun 10 07:34:25 PM PDT 24 8241095430 ps
T451 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3837543748 Jun 10 07:33:46 PM PDT 24 Jun 10 07:34:08 PM PDT 24 32981438808 ps
T452 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3476869674 Jun 10 07:34:02 PM PDT 24 Jun 10 07:36:55 PM PDT 24 11500397867 ps
T88 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1552721267 Jun 10 07:33:54 PM PDT 24 Jun 10 07:34:27 PM PDT 24 3992709608 ps
T453 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3274801595 Jun 10 07:34:12 PM PDT 24 Jun 10 07:34:46 PM PDT 24 2861665579 ps
T454 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2700688625 Jun 10 07:34:10 PM PDT 24 Jun 10 07:34:45 PM PDT 24 4445389528 ps
T455 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.462402395 Jun 10 07:33:43 PM PDT 24 Jun 10 07:34:16 PM PDT 24 3969739314 ps
T456 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3370238800 Jun 10 07:33:52 PM PDT 24 Jun 10 07:34:21 PM PDT 24 39986347033 ps
T457 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1526680014 Jun 10 07:33:53 PM PDT 24 Jun 10 07:34:07 PM PDT 24 636612523 ps

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1050332162
Short name T8
Test name
Test status
Simulation time 282516598099 ps
CPU time 2688.3 seconds
Started Jun 10 07:41:06 PM PDT 24
Finished Jun 10 08:25:57 PM PDT 24
Peak memory 243880 kb
Host smart-53eb70cb-930b-4ec5-b88d-e8aadce31538
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050332162 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.1050332162
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4100825118
Short name T9
Test name
Test status
Simulation time 279106182149 ps
CPU time 748.86 seconds
Started Jun 10 07:41:49 PM PDT 24
Finished Jun 10 07:54:20 PM PDT 24
Peak memory 237884 kb
Host smart-82e63a35-ec14-4c39-b870-74e2defa7696
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100825118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.4100825118
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.872201483
Short name T48
Test name
Test status
Simulation time 4681277576 ps
CPU time 16.88 seconds
Started Jun 10 07:41:43 PM PDT 24
Finished Jun 10 07:42:02 PM PDT 24
Peak memory 217148 kb
Host smart-776581dd-7910-46bd-914d-de1e41f5da4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872201483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.872201483
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1542170183
Short name T57
Test name
Test status
Simulation time 3933491840 ps
CPU time 95.82 seconds
Started Jun 10 07:33:53 PM PDT 24
Finished Jun 10 07:35:31 PM PDT 24
Peak memory 213696 kb
Host smart-d51df81c-92ca-4161-b3fb-f7c13951da2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542170183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1542170183
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1845626792
Short name T44
Test name
Test status
Simulation time 4779068218 ps
CPU time 364.08 seconds
Started Jun 10 07:42:46 PM PDT 24
Finished Jun 10 07:48:52 PM PDT 24
Peak memory 238792 kb
Host smart-9ed7e059-d4fd-4036-8647-c200672c7ce9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845626792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1845626792
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2854529450
Short name T21
Test name
Test status
Simulation time 7169688878 ps
CPU time 249.58 seconds
Started Jun 10 07:40:52 PM PDT 24
Finished Jun 10 07:45:04 PM PDT 24
Peak memory 234788 kb
Host smart-167234d1-f93d-4381-b400-e9415af3a5b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854529450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2854529450
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2383468786
Short name T5
Test name
Test status
Simulation time 6254662457 ps
CPU time 94.41 seconds
Started Jun 10 07:41:15 PM PDT 24
Finished Jun 10 07:42:52 PM PDT 24
Peak memory 219836 kb
Host smart-961164ca-dcee-4ba8-8ef0-58c25aadc15d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383468786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2383468786
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2755290885
Short name T116
Test name
Test status
Simulation time 3164345544 ps
CPU time 171.45 seconds
Started Jun 10 07:34:01 PM PDT 24
Finished Jun 10 07:36:54 PM PDT 24
Peak memory 219244 kb
Host smart-61de19b3-278f-4d01-876b-1e78445958be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755290885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2755290885
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.268105526
Short name T66
Test name
Test status
Simulation time 23079773504 ps
CPU time 182.65 seconds
Started Jun 10 07:33:53 PM PDT 24
Finished Jun 10 07:36:58 PM PDT 24
Peak memory 215696 kb
Host smart-414bbf22-5c17-41de-aae8-3d88a42e3cb8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268105526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.268105526
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.16420339
Short name T118
Test name
Test status
Simulation time 7270086544 ps
CPU time 173.37 seconds
Started Jun 10 07:33:40 PM PDT 24
Finished Jun 10 07:36:36 PM PDT 24
Peak memory 214412 kb
Host smart-3d2864fd-1d43-4595-8d86-d5f062b6d6b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16420339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg
_err.16420339
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3412488954
Short name T132
Test name
Test status
Simulation time 147600007280 ps
CPU time 66.41 seconds
Started Jun 10 07:41:20 PM PDT 24
Finished Jun 10 07:42:28 PM PDT 24
Peak memory 219140 kb
Host smart-c6ca3ec3-5e51-4604-a426-3dbe962ef828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412488954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3412488954
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3088343402
Short name T157
Test name
Test status
Simulation time 4095662834 ps
CPU time 44.37 seconds
Started Jun 10 07:41:48 PM PDT 24
Finished Jun 10 07:42:34 PM PDT 24
Peak memory 218996 kb
Host smart-25b3566e-39a8-40ba-845d-a32c57453e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088343402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3088343402
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2599796265
Short name T42
Test name
Test status
Simulation time 26308231322 ps
CPU time 395.84 seconds
Started Jun 10 07:42:30 PM PDT 24
Finished Jun 10 07:49:10 PM PDT 24
Peak memory 240000 kb
Host smart-e7d99023-99d8-4ab9-bbb8-60888c61fa16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599796265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2599796265
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3242981740
Short name T82
Test name
Test status
Simulation time 6844334123 ps
CPU time 37.76 seconds
Started Jun 10 07:33:52 PM PDT 24
Finished Jun 10 07:34:31 PM PDT 24
Peak memory 214144 kb
Host smart-06b6b0a9-0519-4b5b-8171-563765e1f2f6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242981740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3242981740
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4231406017
Short name T122
Test name
Test status
Simulation time 3721512439 ps
CPU time 102.44 seconds
Started Jun 10 07:34:02 PM PDT 24
Finished Jun 10 07:35:46 PM PDT 24
Peak memory 213584 kb
Host smart-1664373a-433d-4a95-b29e-acef6b924645
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231406017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.4231406017
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.883137748
Short name T142
Test name
Test status
Simulation time 2467688237 ps
CPU time 24.05 seconds
Started Jun 10 07:41:15 PM PDT 24
Finished Jun 10 07:41:42 PM PDT 24
Peak memory 219212 kb
Host smart-9ca1000c-b25a-4bd8-a639-d22185c59a39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=883137748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.883137748
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2739452566
Short name T108
Test name
Test status
Simulation time 10810891295 ps
CPU time 24.63 seconds
Started Jun 10 07:33:42 PM PDT 24
Finished Jun 10 07:34:09 PM PDT 24
Peak memory 212868 kb
Host smart-5ab80b2f-57c4-4ca8-b85a-02fc340b892e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739452566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2739452566
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1693001495
Short name T92
Test name
Test status
Simulation time 14029685015 ps
CPU time 29.34 seconds
Started Jun 10 07:41:39 PM PDT 24
Finished Jun 10 07:42:09 PM PDT 24
Peak memory 219176 kb
Host smart-736b9235-88f7-4dae-a356-b658ea7bcff0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1693001495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1693001495
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1481592219
Short name T143
Test name
Test status
Simulation time 2748987032 ps
CPU time 8.65 seconds
Started Jun 10 07:41:16 PM PDT 24
Finished Jun 10 07:41:27 PM PDT 24
Peak memory 216764 kb
Host smart-aee11f0a-2ed6-4d6a-8688-c853eeb68a2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481592219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1481592219
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3988287081
Short name T13
Test name
Test status
Simulation time 6821147856 ps
CPU time 34.14 seconds
Started Jun 10 07:40:51 PM PDT 24
Finished Jun 10 07:41:28 PM PDT 24
Peak memory 214128 kb
Host smart-9003f3a7-1d87-4c59-bd0f-42cbaa350cc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988287081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3988287081
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3198357240
Short name T110
Test name
Test status
Simulation time 4250767478 ps
CPU time 30.43 seconds
Started Jun 10 07:33:43 PM PDT 24
Finished Jun 10 07:34:16 PM PDT 24
Peak memory 212256 kb
Host smart-6c9affef-9ad8-4579-8355-cac5d7b9b8c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198357240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3198357240
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.462402395
Short name T455
Test name
Test status
Simulation time 3969739314 ps
CPU time 30.61 seconds
Started Jun 10 07:33:43 PM PDT 24
Finished Jun 10 07:34:16 PM PDT 24
Peak memory 211912 kb
Host smart-06c3399b-e090-4541-8c11-c3ae69282cdc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462402395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.462402395
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1020367014
Short name T386
Test name
Test status
Simulation time 1999085571 ps
CPU time 27.25 seconds
Started Jun 10 07:33:41 PM PDT 24
Finished Jun 10 07:34:11 PM PDT 24
Peak memory 212004 kb
Host smart-2679e5f4-719e-4ad5-8bd6-76a28062500c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020367014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1020367014
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2183333800
Short name T384
Test name
Test status
Simulation time 956227300 ps
CPU time 14.86 seconds
Started Jun 10 07:33:51 PM PDT 24
Finished Jun 10 07:34:07 PM PDT 24
Peak memory 216120 kb
Host smart-d44fb89f-c937-408c-af53-0515e139c8a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183333800 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2183333800
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3914603221
Short name T398
Test name
Test status
Simulation time 7204095484 ps
CPU time 28.85 seconds
Started Jun 10 07:33:40 PM PDT 24
Finished Jun 10 07:34:11 PM PDT 24
Peak memory 210924 kb
Host smart-29c7bc13-dd65-4992-8569-7d5f20b3b6ef
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914603221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3914603221
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.830800294
Short name T362
Test name
Test status
Simulation time 3059789196 ps
CPU time 17.3 seconds
Started Jun 10 07:33:42 PM PDT 24
Finished Jun 10 07:34:02 PM PDT 24
Peak memory 210952 kb
Host smart-015102f6-0cf3-4d95-a585-7bd70a423b11
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830800294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
830800294
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.163479232
Short name T419
Test name
Test status
Simulation time 16983307587 ps
CPU time 153.65 seconds
Started Jun 10 07:33:41 PM PDT 24
Finished Jun 10 07:36:17 PM PDT 24
Peak memory 215228 kb
Host smart-3e2de49a-2b58-4300-aabf-f1992eb9d83f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163479232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.163479232
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1626320370
Short name T407
Test name
Test status
Simulation time 1865782167 ps
CPU time 12.6 seconds
Started Jun 10 07:33:43 PM PDT 24
Finished Jun 10 07:33:58 PM PDT 24
Peak memory 210984 kb
Host smart-40bdde59-d9d7-44f0-9f00-53f84a3bd461
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626320370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1626320370
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.592244320
Short name T370
Test name
Test status
Simulation time 4290158638 ps
CPU time 30.51 seconds
Started Jun 10 07:33:42 PM PDT 24
Finished Jun 10 07:34:16 PM PDT 24
Peak memory 219152 kb
Host smart-b187afce-0b82-4951-9c9c-f94dba59f2b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592244320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.592244320
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.131825338
Short name T421
Test name
Test status
Simulation time 361113775 ps
CPU time 8 seconds
Started Jun 10 07:33:42 PM PDT 24
Finished Jun 10 07:33:53 PM PDT 24
Peak memory 210972 kb
Host smart-4ef00296-f858-4f7b-ab48-5ea638f08aa0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131825338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.131825338
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.215409985
Short name T390
Test name
Test status
Simulation time 5616065439 ps
CPU time 17.81 seconds
Started Jun 10 07:33:46 PM PDT 24
Finished Jun 10 07:34:06 PM PDT 24
Peak memory 212200 kb
Host smart-d9086867-06a4-425f-b434-4e4c16573f68
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215409985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.215409985
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.135490534
Short name T449
Test name
Test status
Simulation time 8856846241 ps
CPU time 25.45 seconds
Started Jun 10 07:33:42 PM PDT 24
Finished Jun 10 07:34:11 PM PDT 24
Peak memory 212520 kb
Host smart-c1220998-7bfb-486a-b448-1ceae008c25a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135490534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.135490534
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.181668699
Short name T445
Test name
Test status
Simulation time 2452906584 ps
CPU time 16.7 seconds
Started Jun 10 07:33:43 PM PDT 24
Finished Jun 10 07:34:03 PM PDT 24
Peak memory 217568 kb
Host smart-a44cfa1a-7742-4b26-8e86-90087077adc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181668699 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.181668699
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3331442763
Short name T107
Test name
Test status
Simulation time 3690468220 ps
CPU time 25.04 seconds
Started Jun 10 07:33:43 PM PDT 24
Finished Jun 10 07:34:11 PM PDT 24
Peak memory 212076 kb
Host smart-177cfa13-cff3-4a41-8477-6c84a8ed6abb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331442763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3331442763
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2559684487
Short name T432
Test name
Test status
Simulation time 41103558795 ps
CPU time 30.63 seconds
Started Jun 10 07:33:42 PM PDT 24
Finished Jun 10 07:34:15 PM PDT 24
Peak memory 211212 kb
Host smart-8be486aa-3cbf-403f-9abc-29e0685e322e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559684487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2559684487
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1462430424
Short name T447
Test name
Test status
Simulation time 339268689 ps
CPU time 7.99 seconds
Started Jun 10 07:33:43 PM PDT 24
Finished Jun 10 07:33:54 PM PDT 24
Peak memory 210684 kb
Host smart-ef0f8fb0-53e8-446c-9606-f77b2c8b486c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462430424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1462430424
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3611944965
Short name T72
Test name
Test status
Simulation time 705947710 ps
CPU time 38.47 seconds
Started Jun 10 07:33:47 PM PDT 24
Finished Jun 10 07:34:27 PM PDT 24
Peak memory 214064 kb
Host smart-a11201ab-753c-4a94-a3a3-eb6da2aa20de
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611944965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3611944965
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.380381870
Short name T411
Test name
Test status
Simulation time 1424377825 ps
CPU time 13.33 seconds
Started Jun 10 07:33:53 PM PDT 24
Finished Jun 10 07:34:09 PM PDT 24
Peak memory 211320 kb
Host smart-9ee1b169-4d15-4fa2-9ee3-93eb02d8d01e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380381870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.380381870
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1458159006
Short name T422
Test name
Test status
Simulation time 6311712670 ps
CPU time 30.44 seconds
Started Jun 10 07:33:44 PM PDT 24
Finished Jun 10 07:34:17 PM PDT 24
Peak memory 219148 kb
Host smart-055d5a20-7616-48df-8d4e-dc6b1de0ac22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458159006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1458159006
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3669449902
Short name T125
Test name
Test status
Simulation time 12019179619 ps
CPU time 95.34 seconds
Started Jun 10 07:33:51 PM PDT 24
Finished Jun 10 07:35:27 PM PDT 24
Peak memory 214212 kb
Host smart-443a5543-2823-4e61-a34a-e925e1319a3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669449902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3669449902
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1207684100
Short name T448
Test name
Test status
Simulation time 3126158696 ps
CPU time 26.57 seconds
Started Jun 10 07:33:53 PM PDT 24
Finished Jun 10 07:34:22 PM PDT 24
Peak memory 215636 kb
Host smart-73b1ad25-e53c-4c95-bf2b-2283369f5324
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207684100 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1207684100
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3448669529
Short name T416
Test name
Test status
Simulation time 11757670063 ps
CPU time 25.29 seconds
Started Jun 10 07:33:53 PM PDT 24
Finished Jun 10 07:34:21 PM PDT 24
Peak memory 212780 kb
Host smart-70087bde-4ff0-4cc9-85a8-ff29bb7f42bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448669529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3448669529
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1262811164
Short name T391
Test name
Test status
Simulation time 27372538041 ps
CPU time 81.64 seconds
Started Jun 10 07:33:54 PM PDT 24
Finished Jun 10 07:35:18 PM PDT 24
Peak memory 219272 kb
Host smart-8bc5e3b7-91e6-4574-b044-2333c97a0fa8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262811164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1262811164
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2879256500
Short name T440
Test name
Test status
Simulation time 3285154949 ps
CPU time 11.94 seconds
Started Jun 10 07:33:51 PM PDT 24
Finished Jun 10 07:34:04 PM PDT 24
Peak memory 211552 kb
Host smart-5e2f0cf6-c4a3-464b-8cb5-c15dedd8daa6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879256500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2879256500
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2242205880
Short name T369
Test name
Test status
Simulation time 35058826100 ps
CPU time 27.5 seconds
Started Jun 10 07:33:55 PM PDT 24
Finished Jun 10 07:34:25 PM PDT 24
Peak memory 217960 kb
Host smart-d3b780c7-9522-429e-9988-f496dfa2bd64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242205880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2242205880
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3119859009
Short name T115
Test name
Test status
Simulation time 2342235737 ps
CPU time 165.28 seconds
Started Jun 10 07:33:55 PM PDT 24
Finished Jun 10 07:36:43 PM PDT 24
Peak memory 214224 kb
Host smart-dfe58015-3e4b-4837-a615-ca1a92997981
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119859009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3119859009
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2949137467
Short name T435
Test name
Test status
Simulation time 273128185 ps
CPU time 10.64 seconds
Started Jun 10 07:34:02 PM PDT 24
Finished Jun 10 07:34:14 PM PDT 24
Peak memory 216852 kb
Host smart-23f65d47-d5c9-4b76-bd0e-a151d683dfbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949137467 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2949137467
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1575238022
Short name T372
Test name
Test status
Simulation time 4347762928 ps
CPU time 32.47 seconds
Started Jun 10 07:33:56 PM PDT 24
Finished Jun 10 07:34:31 PM PDT 24
Peak memory 212080 kb
Host smart-2a306fab-d4c6-4e35-9344-0cdff2a8c9e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575238022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1575238022
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3420550477
Short name T102
Test name
Test status
Simulation time 15392664815 ps
CPU time 30.4 seconds
Started Jun 10 07:34:00 PM PDT 24
Finished Jun 10 07:34:32 PM PDT 24
Peak memory 213036 kb
Host smart-039edd46-c4ce-43eb-9aa1-46f8625ab0c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420550477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3420550477
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1243460546
Short name T438
Test name
Test status
Simulation time 5154712142 ps
CPU time 26 seconds
Started Jun 10 07:34:03 PM PDT 24
Finished Jun 10 07:34:31 PM PDT 24
Peak memory 219164 kb
Host smart-f810f851-30c8-4e7a-9ba2-c6dd354db955
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243460546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1243460546
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.169679662
Short name T368
Test name
Test status
Simulation time 2310988596 ps
CPU time 21.98 seconds
Started Jun 10 07:34:03 PM PDT 24
Finished Jun 10 07:34:27 PM PDT 24
Peak memory 219276 kb
Host smart-19e7a37b-1628-428c-a2cd-ef5e6fc081cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169679662 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.169679662
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3617450216
Short name T442
Test name
Test status
Simulation time 13630351591 ps
CPU time 27.16 seconds
Started Jun 10 07:34:04 PM PDT 24
Finished Jun 10 07:34:33 PM PDT 24
Peak memory 212616 kb
Host smart-f9810ae3-a32e-415f-9fe7-427360497f90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617450216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3617450216
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2221464810
Short name T393
Test name
Test status
Simulation time 12091354988 ps
CPU time 75.69 seconds
Started Jun 10 07:34:04 PM PDT 24
Finished Jun 10 07:35:21 PM PDT 24
Peak memory 214124 kb
Host smart-0acef2c5-8539-4b83-917b-0205fe1da909
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221464810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2221464810
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2590811683
Short name T106
Test name
Test status
Simulation time 11547565736 ps
CPU time 25.37 seconds
Started Jun 10 07:34:04 PM PDT 24
Finished Jun 10 07:34:31 PM PDT 24
Peak memory 212692 kb
Host smart-884293bc-58ad-4d49-987a-4ab5ae8472be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590811683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2590811683
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.504865270
Short name T367
Test name
Test status
Simulation time 3135953500 ps
CPU time 31.47 seconds
Started Jun 10 07:34:06 PM PDT 24
Finished Jun 10 07:34:39 PM PDT 24
Peak memory 218992 kb
Host smart-596656d9-43b6-47f2-8779-6947bcde971a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504865270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.504865270
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3476869674
Short name T452
Test name
Test status
Simulation time 11500397867 ps
CPU time 171.03 seconds
Started Jun 10 07:34:02 PM PDT 24
Finished Jun 10 07:36:55 PM PDT 24
Peak memory 214640 kb
Host smart-7b158fbe-5403-4adf-bc15-6056011da540
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476869674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3476869674
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3744280922
Short name T387
Test name
Test status
Simulation time 6255073083 ps
CPU time 18.93 seconds
Started Jun 10 07:34:04 PM PDT 24
Finished Jun 10 07:34:25 PM PDT 24
Peak memory 217656 kb
Host smart-9eee8500-d1d0-40a7-8ec6-3817246a8c5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744280922 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3744280922
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2379102374
Short name T377
Test name
Test status
Simulation time 688383725 ps
CPU time 8.18 seconds
Started Jun 10 07:34:04 PM PDT 24
Finished Jun 10 07:34:14 PM PDT 24
Peak memory 211164 kb
Host smart-6f602951-b2d5-4c35-8cdf-b73914ce2b2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379102374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2379102374
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1718597540
Short name T91
Test name
Test status
Simulation time 11852429632 ps
CPU time 104.95 seconds
Started Jun 10 07:34:06 PM PDT 24
Finished Jun 10 07:35:53 PM PDT 24
Peak memory 214660 kb
Host smart-1ff92907-6fd9-423c-b764-450bdfc90cad
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718597540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1718597540
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4218522192
Short name T450
Test name
Test status
Simulation time 8241095430 ps
CPU time 20.4 seconds
Started Jun 10 07:34:03 PM PDT 24
Finished Jun 10 07:34:25 PM PDT 24
Peak memory 212276 kb
Host smart-85b9bda4-4b92-425c-81ad-d01dfd06802c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218522192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.4218522192
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3805040298
Short name T378
Test name
Test status
Simulation time 8470947498 ps
CPU time 27.24 seconds
Started Jun 10 07:34:07 PM PDT 24
Finished Jun 10 07:34:36 PM PDT 24
Peak memory 219176 kb
Host smart-5ea0532a-d789-445e-8923-af64bd132a16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805040298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3805040298
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1839428630
Short name T58
Test name
Test status
Simulation time 7309019554 ps
CPU time 101.65 seconds
Started Jun 10 07:34:03 PM PDT 24
Finished Jun 10 07:35:47 PM PDT 24
Peak memory 215320 kb
Host smart-e83c8556-cbc4-4455-914d-ded2983ac97c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839428630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1839428630
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2541223175
Short name T395
Test name
Test status
Simulation time 10374439825 ps
CPU time 23.44 seconds
Started Jun 10 07:34:03 PM PDT 24
Finished Jun 10 07:34:28 PM PDT 24
Peak memory 217740 kb
Host smart-bbbbfddd-86de-470b-b9fb-016d95429367
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541223175 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2541223175
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3426949636
Short name T441
Test name
Test status
Simulation time 170903651 ps
CPU time 8.48 seconds
Started Jun 10 07:34:04 PM PDT 24
Finished Jun 10 07:34:15 PM PDT 24
Peak memory 211216 kb
Host smart-fdf57673-08d4-411c-8b59-02fdae70bf41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426949636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3426949636
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2730960122
Short name T112
Test name
Test status
Simulation time 3119512553 ps
CPU time 77.19 seconds
Started Jun 10 07:34:04 PM PDT 24
Finished Jun 10 07:35:23 PM PDT 24
Peak memory 215416 kb
Host smart-6c0da7a0-d551-49f0-a0fe-3c1e1a650bd9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730960122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2730960122
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2136332842
Short name T397
Test name
Test status
Simulation time 1939961489 ps
CPU time 12 seconds
Started Jun 10 07:34:02 PM PDT 24
Finished Jun 10 07:34:16 PM PDT 24
Peak memory 212684 kb
Host smart-280bc86f-783a-45ca-b892-4e3be9003c5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136332842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2136332842
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3768016777
Short name T374
Test name
Test status
Simulation time 8179642766 ps
CPU time 15.82 seconds
Started Jun 10 07:34:05 PM PDT 24
Finished Jun 10 07:34:22 PM PDT 24
Peak memory 217892 kb
Host smart-75f434c4-854c-4487-b22e-e2b2bfc37b8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768016777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3768016777
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1215005388
Short name T433
Test name
Test status
Simulation time 673644529 ps
CPU time 8.44 seconds
Started Jun 10 07:34:01 PM PDT 24
Finished Jun 10 07:34:12 PM PDT 24
Peak memory 216372 kb
Host smart-20f77f01-903c-46af-887f-caec6602640b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215005388 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1215005388
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2344636001
Short name T439
Test name
Test status
Simulation time 687701517 ps
CPU time 8.14 seconds
Started Jun 10 07:34:02 PM PDT 24
Finished Jun 10 07:34:12 PM PDT 24
Peak memory 211244 kb
Host smart-71a2f7e8-2fa7-4aad-af15-c74ed103a81b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344636001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2344636001
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.543457781
Short name T84
Test name
Test status
Simulation time 49173728191 ps
CPU time 185.27 seconds
Started Jun 10 07:34:03 PM PDT 24
Finished Jun 10 07:37:10 PM PDT 24
Peak memory 215280 kb
Host smart-7d5d22db-e420-48e8-ad9f-6669ceaabe3b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543457781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.543457781
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2673733337
Short name T388
Test name
Test status
Simulation time 11154188584 ps
CPU time 27.1 seconds
Started Jun 10 07:34:03 PM PDT 24
Finished Jun 10 07:34:32 PM PDT 24
Peak memory 212992 kb
Host smart-8f3a3def-db14-4f2d-9060-63683f61eb38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673733337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2673733337
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.199764695
Short name T392
Test name
Test status
Simulation time 234635380 ps
CPU time 11.87 seconds
Started Jun 10 07:34:03 PM PDT 24
Finished Jun 10 07:34:16 PM PDT 24
Peak memory 217372 kb
Host smart-0fd01518-a6aa-42f7-8c5c-dc1990939ef9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199764695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.199764695
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.685467302
Short name T119
Test name
Test status
Simulation time 378198042 ps
CPU time 156.96 seconds
Started Jun 10 07:34:01 PM PDT 24
Finished Jun 10 07:36:40 PM PDT 24
Peak memory 214488 kb
Host smart-8f473348-223f-4de8-a976-73e434694bee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685467302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.685467302
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3471756352
Short name T366
Test name
Test status
Simulation time 2860632479 ps
CPU time 26.18 seconds
Started Jun 10 07:34:02 PM PDT 24
Finished Jun 10 07:34:30 PM PDT 24
Peak memory 218364 kb
Host smart-31ffbb60-7100-47d0-ac56-7c0dc56ef4f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471756352 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3471756352
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1957797816
Short name T381
Test name
Test status
Simulation time 4304291098 ps
CPU time 14.15 seconds
Started Jun 10 07:34:03 PM PDT 24
Finished Jun 10 07:34:19 PM PDT 24
Peak memory 211100 kb
Host smart-dabe16ff-97d4-479f-92f3-455a18463ad9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957797816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1957797816
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2261640405
Short name T67
Test name
Test status
Simulation time 46989984263 ps
CPU time 179.54 seconds
Started Jun 10 07:34:05 PM PDT 24
Finished Jun 10 07:37:07 PM PDT 24
Peak memory 215416 kb
Host smart-b677725a-129e-4abd-830d-9b0490242d61
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261640405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2261640405
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1174483241
Short name T420
Test name
Test status
Simulation time 868541922 ps
CPU time 8.17 seconds
Started Jun 10 07:34:02 PM PDT 24
Finished Jun 10 07:34:12 PM PDT 24
Peak memory 211480 kb
Host smart-a3cbad76-a242-445c-86c7-8454dbf55f4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174483241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1174483241
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2924858200
Short name T427
Test name
Test status
Simulation time 4106182246 ps
CPU time 23.8 seconds
Started Jun 10 07:34:02 PM PDT 24
Finished Jun 10 07:34:28 PM PDT 24
Peak memory 218504 kb
Host smart-78965726-8726-4978-a7aa-a5d1a826c533
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924858200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2924858200
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.351517172
Short name T120
Test name
Test status
Simulation time 7339587499 ps
CPU time 98.14 seconds
Started Jun 10 07:34:02 PM PDT 24
Finished Jun 10 07:35:42 PM PDT 24
Peak memory 219276 kb
Host smart-c8267243-0839-4720-92d4-0e54cd60c158
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351517172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.351517172
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.793528651
Short name T410
Test name
Test status
Simulation time 47395500805 ps
CPU time 24.53 seconds
Started Jun 10 07:34:00 PM PDT 24
Finished Jun 10 07:34:26 PM PDT 24
Peak memory 217196 kb
Host smart-1558ccc9-fa6e-4e4e-82bf-327407e9ae38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793528651 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.793528651
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2522508502
Short name T71
Test name
Test status
Simulation time 687721515 ps
CPU time 8.09 seconds
Started Jun 10 07:34:03 PM PDT 24
Finished Jun 10 07:34:14 PM PDT 24
Peak memory 211344 kb
Host smart-3305e082-f857-489f-887e-60e248827034
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522508502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2522508502
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2931119944
Short name T61
Test name
Test status
Simulation time 1071144540 ps
CPU time 57.65 seconds
Started Jun 10 07:34:03 PM PDT 24
Finished Jun 10 07:35:02 PM PDT 24
Peak memory 215240 kb
Host smart-691b99b3-c381-4e32-bf03-c003322be299
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931119944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2931119944
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3973993806
Short name T104
Test name
Test status
Simulation time 1684161458 ps
CPU time 17.74 seconds
Started Jun 10 07:34:04 PM PDT 24
Finished Jun 10 07:34:23 PM PDT 24
Peak memory 212464 kb
Host smart-b1216426-ed44-4dcf-85e6-5900a79aa77d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973993806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3973993806
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.246184767
Short name T401
Test name
Test status
Simulation time 591358769 ps
CPU time 13.44 seconds
Started Jun 10 07:34:05 PM PDT 24
Finished Jun 10 07:34:20 PM PDT 24
Peak memory 219168 kb
Host smart-f32e3ba4-e9b7-4b90-9b9f-c1b38eb541e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246184767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.246184767
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.365589965
Short name T380
Test name
Test status
Simulation time 1032377949 ps
CPU time 12.09 seconds
Started Jun 10 07:34:13 PM PDT 24
Finished Jun 10 07:34:28 PM PDT 24
Peak memory 215788 kb
Host smart-c82914e8-eb0d-4f64-bf3f-e900203ad60c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365589965 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.365589965
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.423840222
Short name T68
Test name
Test status
Simulation time 13652823196 ps
CPU time 26.82 seconds
Started Jun 10 07:34:10 PM PDT 24
Finished Jun 10 07:34:38 PM PDT 24
Peak memory 212592 kb
Host smart-2d40d592-afdd-4009-9cc3-cbd009a1f3a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423840222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.423840222
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2067090255
Short name T111
Test name
Test status
Simulation time 5154037639 ps
CPU time 56.63 seconds
Started Jun 10 07:34:10 PM PDT 24
Finished Jun 10 07:35:09 PM PDT 24
Peak memory 219232 kb
Host smart-6a458cd5-bbf8-46b6-843e-c1d5c5910a8f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067090255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2067090255
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.4110714445
Short name T101
Test name
Test status
Simulation time 2496894083 ps
CPU time 22.63 seconds
Started Jun 10 07:34:10 PM PDT 24
Finished Jun 10 07:34:35 PM PDT 24
Peak memory 212556 kb
Host smart-496ef52f-2357-4a9f-a226-5d6687ad6488
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110714445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.4110714445
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3274801595
Short name T453
Test name
Test status
Simulation time 2861665579 ps
CPU time 31.1 seconds
Started Jun 10 07:34:12 PM PDT 24
Finished Jun 10 07:34:46 PM PDT 24
Peak memory 218788 kb
Host smart-5fc644c3-370a-44ea-ab8a-a82524e53161
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274801595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3274801595
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.788410499
Short name T56
Test name
Test status
Simulation time 39029353211 ps
CPU time 93.75 seconds
Started Jun 10 07:34:13 PM PDT 24
Finished Jun 10 07:35:50 PM PDT 24
Peak memory 214164 kb
Host smart-f6155909-1ff6-4473-b79d-10450dcfbcf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788410499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.788410499
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1898009517
Short name T371
Test name
Test status
Simulation time 389516926 ps
CPU time 9.11 seconds
Started Jun 10 07:34:14 PM PDT 24
Finished Jun 10 07:34:26 PM PDT 24
Peak memory 217228 kb
Host smart-4655a194-cb9a-4bb7-8241-89cb756c7c84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898009517 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1898009517
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2700688625
Short name T454
Test name
Test status
Simulation time 4445389528 ps
CPU time 32.52 seconds
Started Jun 10 07:34:10 PM PDT 24
Finished Jun 10 07:34:45 PM PDT 24
Peak memory 211956 kb
Host smart-fc2cae16-cec5-45cd-849f-ac39a7b8bd98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700688625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2700688625
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.369119795
Short name T69
Test name
Test status
Simulation time 6859800234 ps
CPU time 77.31 seconds
Started Jun 10 07:34:12 PM PDT 24
Finished Jun 10 07:35:33 PM PDT 24
Peak memory 215332 kb
Host smart-325e0d5c-8b3e-47fa-ae4a-5880daf1bba8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369119795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.369119795
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4261842929
Short name T400
Test name
Test status
Simulation time 2931158486 ps
CPU time 26.44 seconds
Started Jun 10 07:34:09 PM PDT 24
Finished Jun 10 07:34:37 PM PDT 24
Peak memory 212476 kb
Host smart-482877a5-3845-42c6-8f7f-4e27e40e5a7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261842929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.4261842929
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2258799371
Short name T394
Test name
Test status
Simulation time 5984212344 ps
CPU time 21.17 seconds
Started Jun 10 07:34:10 PM PDT 24
Finished Jun 10 07:34:33 PM PDT 24
Peak memory 217852 kb
Host smart-e919d6c3-c633-4dd9-a861-8eef203e3a72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258799371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2258799371
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1595057077
Short name T123
Test name
Test status
Simulation time 932453090 ps
CPU time 86.58 seconds
Started Jun 10 07:34:11 PM PDT 24
Finished Jun 10 07:35:40 PM PDT 24
Peak memory 214000 kb
Host smart-c2b9abf5-0b24-4e00-92a6-501dddb99150
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595057077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1595057077
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1570026835
Short name T85
Test name
Test status
Simulation time 31965707501 ps
CPU time 30.95 seconds
Started Jun 10 07:33:43 PM PDT 24
Finished Jun 10 07:34:17 PM PDT 24
Peak memory 212564 kb
Host smart-c189da76-bfac-42fd-a2be-eee28e77ba3b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570026835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1570026835
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2581892348
Short name T437
Test name
Test status
Simulation time 331659060 ps
CPU time 8.18 seconds
Started Jun 10 07:33:54 PM PDT 24
Finished Jun 10 07:34:05 PM PDT 24
Peak memory 211040 kb
Host smart-3594603a-85fc-40f5-a1b0-96400d82d56e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581892348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2581892348
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2821042227
Short name T83
Test name
Test status
Simulation time 2576064879 ps
CPU time 26.68 seconds
Started Jun 10 07:33:46 PM PDT 24
Finished Jun 10 07:34:15 PM PDT 24
Peak memory 212036 kb
Host smart-65bd5631-1313-4167-b53b-af649ae16345
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821042227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2821042227
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1885314545
Short name T418
Test name
Test status
Simulation time 4236913154 ps
CPU time 33.09 seconds
Started Jun 10 07:33:44 PM PDT 24
Finished Jun 10 07:34:20 PM PDT 24
Peak memory 217864 kb
Host smart-5d2c2534-1eab-4493-9e36-f42fe27e0ec8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885314545 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1885314545
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.73086030
Short name T414
Test name
Test status
Simulation time 3483589259 ps
CPU time 28.75 seconds
Started Jun 10 07:33:52 PM PDT 24
Finished Jun 10 07:34:22 PM PDT 24
Peak memory 212080 kb
Host smart-ee32fe64-e34d-4e68-bd9e-83445d3e755a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73086030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.73086030
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.75203216
Short name T375
Test name
Test status
Simulation time 1804797713 ps
CPU time 19.12 seconds
Started Jun 10 07:33:53 PM PDT 24
Finished Jun 10 07:34:15 PM PDT 24
Peak memory 210752 kb
Host smart-2b6fecdf-efd1-404c-b63b-b906894612fe
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75203216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_
mem_partial_access.75203216
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3563904252
Short name T434
Test name
Test status
Simulation time 9194845483 ps
CPU time 21.06 seconds
Started Jun 10 07:33:53 PM PDT 24
Finished Jun 10 07:34:16 PM PDT 24
Peak memory 211192 kb
Host smart-6b91a345-14a5-4100-b8b0-9410e48d9066
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563904252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3563904252
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.39137403
Short name T364
Test name
Test status
Simulation time 13741401006 ps
CPU time 38.08 seconds
Started Jun 10 07:33:47 PM PDT 24
Finished Jun 10 07:34:27 PM PDT 24
Peak memory 219212 kb
Host smart-c3fd4797-5ac8-42f9-aa61-4df5a49f5986
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39137403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pass
thru_mem_tl_intg_err.39137403
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3837543748
Short name T451
Test name
Test status
Simulation time 32981438808 ps
CPU time 20.37 seconds
Started Jun 10 07:33:46 PM PDT 24
Finished Jun 10 07:34:08 PM PDT 24
Peak memory 212820 kb
Host smart-db004e29-7761-485d-a894-88b1518ef5f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837543748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3837543748
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2737732441
Short name T389
Test name
Test status
Simulation time 442662721 ps
CPU time 14.09 seconds
Started Jun 10 07:33:46 PM PDT 24
Finished Jun 10 07:34:03 PM PDT 24
Peak memory 217568 kb
Host smart-ae94c64d-b899-4406-ae4b-8bd2dc55c27d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737732441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2737732441
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1210912787
Short name T126
Test name
Test status
Simulation time 26662850478 ps
CPU time 95.19 seconds
Started Jun 10 07:33:48 PM PDT 24
Finished Jun 10 07:35:25 PM PDT 24
Peak memory 214328 kb
Host smart-59950c62-5f1a-48b4-b729-d34859737b41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210912787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1210912787
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1390668880
Short name T90
Test name
Test status
Simulation time 61021012674 ps
CPU time 32.97 seconds
Started Jun 10 07:33:46 PM PDT 24
Finished Jun 10 07:34:21 PM PDT 24
Peak memory 212396 kb
Host smart-2804adae-ebb6-4f43-bd6a-f98f58f48dc7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390668880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1390668880
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3735434903
Short name T402
Test name
Test status
Simulation time 174406065 ps
CPU time 8.45 seconds
Started Jun 10 07:33:46 PM PDT 24
Finished Jun 10 07:33:57 PM PDT 24
Peak memory 211048 kb
Host smart-e032ecb7-d951-4603-af69-34fe70bad5a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735434903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3735434903
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3441266925
Short name T89
Test name
Test status
Simulation time 27947967046 ps
CPU time 36.36 seconds
Started Jun 10 07:33:41 PM PDT 24
Finished Jun 10 07:34:21 PM PDT 24
Peak memory 212384 kb
Host smart-824df7e2-f02e-481b-92b1-6ac0c0e8f54e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441266925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3441266925
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4092422587
Short name T425
Test name
Test status
Simulation time 7354392962 ps
CPU time 13.17 seconds
Started Jun 10 07:33:50 PM PDT 24
Finished Jun 10 07:34:04 PM PDT 24
Peak memory 216836 kb
Host smart-0f539ab8-c3ba-4aad-8a82-a9bfa9b5e850
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092422587 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.4092422587
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.666665743
Short name T446
Test name
Test status
Simulation time 7852631517 ps
CPU time 20.56 seconds
Started Jun 10 07:33:53 PM PDT 24
Finished Jun 10 07:34:16 PM PDT 24
Peak memory 211956 kb
Host smart-87885a5f-dac1-4308-a272-1eb85dabb619
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666665743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.666665743
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3200163924
Short name T443
Test name
Test status
Simulation time 23628076726 ps
CPU time 21.47 seconds
Started Jun 10 07:33:53 PM PDT 24
Finished Jun 10 07:34:17 PM PDT 24
Peak memory 210932 kb
Host smart-df3fca82-fb9e-41a9-ab88-abb4179727ca
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200163924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3200163924
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1486265903
Short name T396
Test name
Test status
Simulation time 589957658 ps
CPU time 8.05 seconds
Started Jun 10 07:33:54 PM PDT 24
Finished Jun 10 07:34:04 PM PDT 24
Peak memory 210568 kb
Host smart-00ea94d6-7400-4e3a-8772-94b92014c6b3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486265903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1486265903
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1598817329
Short name T365
Test name
Test status
Simulation time 2061267751 ps
CPU time 51.89 seconds
Started Jun 10 07:33:50 PM PDT 24
Finished Jun 10 07:34:43 PM PDT 24
Peak memory 214120 kb
Host smart-bc5b8037-7400-4059-aca1-c69ec4ddfc00
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598817329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1598817329
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.942249271
Short name T405
Test name
Test status
Simulation time 5690534588 ps
CPU time 24.95 seconds
Started Jun 10 07:33:46 PM PDT 24
Finished Jun 10 07:34:13 PM PDT 24
Peak memory 213004 kb
Host smart-f22e2b86-c9b2-4864-b624-4d7e9fd80579
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942249271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.942249271
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2452196204
Short name T417
Test name
Test status
Simulation time 3065851118 ps
CPU time 30.87 seconds
Started Jun 10 07:33:45 PM PDT 24
Finished Jun 10 07:34:18 PM PDT 24
Peak memory 219144 kb
Host smart-0a849d01-780a-480e-9377-4d422f8e2d80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452196204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2452196204
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.849847229
Short name T124
Test name
Test status
Simulation time 10920693998 ps
CPU time 102.71 seconds
Started Jun 10 07:33:44 PM PDT 24
Finished Jun 10 07:35:29 PM PDT 24
Peak memory 214180 kb
Host smart-eea82122-c86f-47ff-ab31-3930cf43323d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849847229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.849847229
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.917890699
Short name T403
Test name
Test status
Simulation time 3994401357 ps
CPU time 20.81 seconds
Started Jun 10 07:33:44 PM PDT 24
Finished Jun 10 07:34:07 PM PDT 24
Peak memory 211916 kb
Host smart-b93221ad-e98e-4df7-9f14-8e9cf4962d53
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917890699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.917890699
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.791316117
Short name T59
Test name
Test status
Simulation time 172603844 ps
CPU time 8.73 seconds
Started Jun 10 07:33:43 PM PDT 24
Finished Jun 10 07:33:54 PM PDT 24
Peak memory 211048 kb
Host smart-0be29a12-28fb-4fbc-aabe-50d8b8e7421d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791316117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.791316117
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1366999004
Short name T363
Test name
Test status
Simulation time 2238606430 ps
CPU time 15.59 seconds
Started Jun 10 07:33:43 PM PDT 24
Finished Jun 10 07:34:02 PM PDT 24
Peak memory 212364 kb
Host smart-7e1bf36c-ee51-4a40-bc8b-569559366c59
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366999004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1366999004
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1468790318
Short name T429
Test name
Test status
Simulation time 762861792 ps
CPU time 8.73 seconds
Started Jun 10 07:33:46 PM PDT 24
Finished Jun 10 07:33:57 PM PDT 24
Peak memory 216780 kb
Host smart-52aeb042-759c-424a-8614-77b7e2cca1e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468790318 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1468790318
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.347160170
Short name T73
Test name
Test status
Simulation time 12899047672 ps
CPU time 28.55 seconds
Started Jun 10 07:33:48 PM PDT 24
Finished Jun 10 07:34:19 PM PDT 24
Peak memory 212600 kb
Host smart-c12c31c2-ea92-4661-b651-c9c5705e804c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347160170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.347160170
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.814975124
Short name T436
Test name
Test status
Simulation time 17365025552 ps
CPU time 31.48 seconds
Started Jun 10 07:33:46 PM PDT 24
Finished Jun 10 07:34:19 PM PDT 24
Peak memory 210856 kb
Host smart-b99e0b8d-72bb-4a3c-a23e-582045badda7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814975124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.814975124
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2644433802
Short name T424
Test name
Test status
Simulation time 12496043813 ps
CPU time 27.22 seconds
Started Jun 10 07:33:45 PM PDT 24
Finished Jun 10 07:34:15 PM PDT 24
Peak memory 211052 kb
Host smart-e7a79c54-8581-41c1-a632-4b7f1769b2f8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644433802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2644433802
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1275222049
Short name T406
Test name
Test status
Simulation time 8048637308 ps
CPU time 85.11 seconds
Started Jun 10 07:33:46 PM PDT 24
Finished Jun 10 07:35:13 PM PDT 24
Peak memory 211716 kb
Host smart-123e34ee-31bf-4fd5-9742-e7a7b26f02f0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275222049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1275222049
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.163645643
Short name T103
Test name
Test status
Simulation time 3167089723 ps
CPU time 11.66 seconds
Started Jun 10 07:33:44 PM PDT 24
Finished Jun 10 07:33:58 PM PDT 24
Peak memory 211464 kb
Host smart-6de95e9c-9e8f-40b9-a2ed-43f0902b1d78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163645643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.163645643
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.792238469
Short name T409
Test name
Test status
Simulation time 1645128665 ps
CPU time 18.41 seconds
Started Jun 10 07:33:48 PM PDT 24
Finished Jun 10 07:34:08 PM PDT 24
Peak memory 218524 kb
Host smart-17e0a8b6-8937-4b35-aeee-4f827b0cbe5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792238469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.792238469
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3509868462
Short name T127
Test name
Test status
Simulation time 14110295962 ps
CPU time 89.06 seconds
Started Jun 10 07:33:46 PM PDT 24
Finished Jun 10 07:35:18 PM PDT 24
Peak memory 219272 kb
Host smart-8ce5d709-bbb6-400a-b3df-a8f6eb19d83f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509868462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3509868462
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.691862813
Short name T373
Test name
Test status
Simulation time 694299778 ps
CPU time 13.68 seconds
Started Jun 10 07:33:52 PM PDT 24
Finished Jun 10 07:34:08 PM PDT 24
Peak memory 215228 kb
Host smart-14741888-7e79-4239-b671-f567e8820ed0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691862813 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.691862813
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.13890567
Short name T423
Test name
Test status
Simulation time 677425342 ps
CPU time 13.05 seconds
Started Jun 10 07:33:55 PM PDT 24
Finished Jun 10 07:34:10 PM PDT 24
Peak memory 212280 kb
Host smart-7362ec99-ec6d-483b-b2d0-2be9a33794d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13890567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.13890567
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.588209341
Short name T399
Test name
Test status
Simulation time 2298820596 ps
CPU time 22.51 seconds
Started Jun 10 07:33:54 PM PDT 24
Finished Jun 10 07:34:19 PM PDT 24
Peak memory 212676 kb
Host smart-e49b1b45-220a-4772-af31-d4e1484040a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588209341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.588209341
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2903785767
Short name T383
Test name
Test status
Simulation time 689597559 ps
CPU time 13.41 seconds
Started Jun 10 07:33:51 PM PDT 24
Finished Jun 10 07:34:05 PM PDT 24
Peak memory 216644 kb
Host smart-a3a06ca4-f3e2-427d-b82f-7fab6aa65f9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903785767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2903785767
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3257187511
Short name T117
Test name
Test status
Simulation time 246275916 ps
CPU time 81.53 seconds
Started Jun 10 07:33:54 PM PDT 24
Finished Jun 10 07:35:18 PM PDT 24
Peak memory 214056 kb
Host smart-e6a27d86-9754-4b64-9791-92fecdc9cb5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257187511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3257187511
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1228880659
Short name T379
Test name
Test status
Simulation time 529666293 ps
CPU time 10.2 seconds
Started Jun 10 07:33:58 PM PDT 24
Finished Jun 10 07:34:10 PM PDT 24
Peak memory 215620 kb
Host smart-fe6d899a-7933-48bd-a2c1-57697ac012cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228880659 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1228880659
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1552721267
Short name T88
Test name
Test status
Simulation time 3992709608 ps
CPU time 31.07 seconds
Started Jun 10 07:33:54 PM PDT 24
Finished Jun 10 07:34:27 PM PDT 24
Peak memory 211696 kb
Host smart-fc431288-b725-4116-8ec0-eaccc73e18be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552721267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1552721267
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1718725713
Short name T428
Test name
Test status
Simulation time 40362090320 ps
CPU time 111.7 seconds
Started Jun 10 07:33:52 PM PDT 24
Finished Jun 10 07:35:46 PM PDT 24
Peak memory 214180 kb
Host smart-de7eead5-9bc2-42ee-ac88-406847c258c5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718725713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1718725713
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2510370609
Short name T415
Test name
Test status
Simulation time 450744060 ps
CPU time 15.39 seconds
Started Jun 10 07:33:57 PM PDT 24
Finished Jun 10 07:34:14 PM PDT 24
Peak memory 212812 kb
Host smart-b74a23c0-d50b-45af-a280-4df4f3a10b9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510370609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2510370609
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.976800556
Short name T430
Test name
Test status
Simulation time 170692809 ps
CPU time 11.51 seconds
Started Jun 10 07:33:55 PM PDT 24
Finished Jun 10 07:34:08 PM PDT 24
Peak memory 218732 kb
Host smart-065ce36c-bf5c-4e34-901d-3553988f896a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976800556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.976800556
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3916770094
Short name T121
Test name
Test status
Simulation time 1062199973 ps
CPU time 86.11 seconds
Started Jun 10 07:33:53 PM PDT 24
Finished Jun 10 07:35:22 PM PDT 24
Peak memory 213868 kb
Host smart-5c1b863d-af09-468e-91d5-c6bb916b77ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916770094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3916770094
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2266418958
Short name T65
Test name
Test status
Simulation time 2007142174 ps
CPU time 21.57 seconds
Started Jun 10 07:33:53 PM PDT 24
Finished Jun 10 07:34:17 PM PDT 24
Peak memory 216128 kb
Host smart-12d4c5c0-a121-41cb-a608-b31a7f52051f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266418958 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2266418958
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2867966312
Short name T431
Test name
Test status
Simulation time 1833615756 ps
CPU time 8.17 seconds
Started Jun 10 07:33:51 PM PDT 24
Finished Jun 10 07:34:00 PM PDT 24
Peak memory 211160 kb
Host smart-195be858-e5d4-45eb-9760-afb2d8d3e633
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867966312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2867966312
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3428206836
Short name T413
Test name
Test status
Simulation time 4424714489 ps
CPU time 66.92 seconds
Started Jun 10 07:33:53 PM PDT 24
Finished Jun 10 07:35:02 PM PDT 24
Peak memory 214724 kb
Host smart-0a87d442-044f-436b-98f0-9e54ba0bf7f1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428206836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3428206836
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.4129897026
Short name T60
Test name
Test status
Simulation time 229302648 ps
CPU time 12.35 seconds
Started Jun 10 07:33:55 PM PDT 24
Finished Jun 10 07:34:10 PM PDT 24
Peak memory 212508 kb
Host smart-3cd05de8-9647-45e1-aed5-3287898bf22f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129897026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.4129897026
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1846220361
Short name T376
Test name
Test status
Simulation time 345903241 ps
CPU time 12.67 seconds
Started Jun 10 07:33:58 PM PDT 24
Finished Jun 10 07:34:13 PM PDT 24
Peak memory 217540 kb
Host smart-1479cb1d-3b5e-45e0-a164-a6088100544a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846220361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1846220361
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.51107213
Short name T404
Test name
Test status
Simulation time 1997163198 ps
CPU time 81.05 seconds
Started Jun 10 07:33:53 PM PDT 24
Finished Jun 10 07:35:17 PM PDT 24
Peak memory 213052 kb
Host smart-3f8ad975-fb6b-4883-9727-361d7c2bc176
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51107213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg
_err.51107213
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3567336235
Short name T412
Test name
Test status
Simulation time 22813571252 ps
CPU time 19.84 seconds
Started Jun 10 07:33:53 PM PDT 24
Finished Jun 10 07:34:15 PM PDT 24
Peak memory 217268 kb
Host smart-13cc239e-0745-4378-a32d-29e647e02d4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567336235 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3567336235
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.865461297
Short name T70
Test name
Test status
Simulation time 3104009205 ps
CPU time 26.71 seconds
Started Jun 10 07:33:55 PM PDT 24
Finished Jun 10 07:34:23 PM PDT 24
Peak memory 212168 kb
Host smart-872b9578-4ec3-48b8-a453-029a28e5e778
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865461297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.865461297
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1481913201
Short name T87
Test name
Test status
Simulation time 13270036439 ps
CPU time 114.93 seconds
Started Jun 10 07:33:56 PM PDT 24
Finished Jun 10 07:35:53 PM PDT 24
Peak memory 214428 kb
Host smart-b985ed3a-adf2-4f72-bd12-c9a4239123ec
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481913201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1481913201
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1783907648
Short name T426
Test name
Test status
Simulation time 13055949310 ps
CPU time 24.57 seconds
Started Jun 10 07:33:59 PM PDT 24
Finished Jun 10 07:34:25 PM PDT 24
Peak memory 213180 kb
Host smart-faf1a9f1-43b5-4354-a1af-805a8343300e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783907648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1783907648
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1526680014
Short name T457
Test name
Test status
Simulation time 636612523 ps
CPU time 12.53 seconds
Started Jun 10 07:33:53 PM PDT 24
Finished Jun 10 07:34:07 PM PDT 24
Peak memory 218744 kb
Host smart-8be349c2-7340-4e82-843e-17eda7f6544e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526680014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1526680014
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2665594209
Short name T385
Test name
Test status
Simulation time 301177432 ps
CPU time 83.14 seconds
Started Jun 10 07:33:52 PM PDT 24
Finished Jun 10 07:35:16 PM PDT 24
Peak memory 213600 kb
Host smart-c51d7f67-91fc-49bc-ba14-d2e4cc8a48d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665594209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2665594209
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3370238800
Short name T456
Test name
Test status
Simulation time 39986347033 ps
CPU time 26.89 seconds
Started Jun 10 07:33:52 PM PDT 24
Finished Jun 10 07:34:21 PM PDT 24
Peak memory 218812 kb
Host smart-452446d2-dfa1-4486-b464-0277b6702318
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370238800 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3370238800
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1270385452
Short name T86
Test name
Test status
Simulation time 1401739238 ps
CPU time 17.25 seconds
Started Jun 10 07:33:55 PM PDT 24
Finished Jun 10 07:34:15 PM PDT 24
Peak memory 212032 kb
Host smart-d3e5d539-461a-4f07-a7c8-67aa0ef22076
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270385452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1270385452
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.655243287
Short name T408
Test name
Test status
Simulation time 77151298108 ps
CPU time 102.07 seconds
Started Jun 10 07:33:54 PM PDT 24
Finished Jun 10 07:35:38 PM PDT 24
Peak memory 215220 kb
Host smart-d1ab220c-cfa4-4cac-988d-c491b63980a4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655243287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.655243287
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.889724622
Short name T105
Test name
Test status
Simulation time 4019447886 ps
CPU time 30.18 seconds
Started Jun 10 07:33:54 PM PDT 24
Finished Jun 10 07:34:27 PM PDT 24
Peak memory 212544 kb
Host smart-d575e5a2-38e5-442c-9c5b-65213211778d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889724622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.889724622
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3440782021
Short name T382
Test name
Test status
Simulation time 2049395105 ps
CPU time 14.26 seconds
Started Jun 10 07:33:58 PM PDT 24
Finished Jun 10 07:34:14 PM PDT 24
Peak memory 216760 kb
Host smart-e1fc1a61-c5b8-4261-8635-9bb80ab7663e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440782021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3440782021
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1814777824
Short name T444
Test name
Test status
Simulation time 2604351112 ps
CPU time 96.31 seconds
Started Jun 10 07:33:53 PM PDT 24
Finished Jun 10 07:35:31 PM PDT 24
Peak memory 213896 kb
Host smart-a3fad593-2e7f-4aef-b721-bf5495694be9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814777824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1814777824
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3011565114
Short name T258
Test name
Test status
Simulation time 3951329187 ps
CPU time 31.18 seconds
Started Jun 10 07:40:51 PM PDT 24
Finished Jun 10 07:41:25 PM PDT 24
Peak memory 216940 kb
Host smart-2ae1d55e-355b-4d46-80fe-07c21fdba6c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011565114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3011565114
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3555859966
Short name T141
Test name
Test status
Simulation time 40011909720 ps
CPU time 237.69 seconds
Started Jun 10 07:40:52 PM PDT 24
Finished Jun 10 07:44:52 PM PDT 24
Peak memory 239128 kb
Host smart-da3f7970-78ed-40b5-ad25-199208dd6d8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555859966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3555859966
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2991303141
Short name T184
Test name
Test status
Simulation time 20818267415 ps
CPU time 35.82 seconds
Started Jun 10 07:40:52 PM PDT 24
Finished Jun 10 07:41:30 PM PDT 24
Peak memory 218932 kb
Host smart-10fbee81-a8e2-43fc-a538-35ab2007c3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991303141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2991303141
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.205514245
Short name T180
Test name
Test status
Simulation time 4441004279 ps
CPU time 24.14 seconds
Started Jun 10 07:40:52 PM PDT 24
Finished Jun 10 07:41:18 PM PDT 24
Peak memory 211744 kb
Host smart-56ec6de2-ca47-47b4-9504-e90c2b8cbf5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=205514245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.205514245
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2518374364
Short name T26
Test name
Test status
Simulation time 1588741457 ps
CPU time 230.08 seconds
Started Jun 10 07:40:52 PM PDT 24
Finished Jun 10 07:44:44 PM PDT 24
Peak memory 237312 kb
Host smart-2036d496-59ef-4a64-b636-5e6c429ecac3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518374364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2518374364
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2816552143
Short name T79
Test name
Test status
Simulation time 11860944148 ps
CPU time 70.07 seconds
Started Jun 10 07:40:52 PM PDT 24
Finished Jun 10 07:42:04 PM PDT 24
Peak memory 215636 kb
Host smart-9f1df3b9-ae6a-405a-8834-4a50cf7b33ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816552143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2816552143
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3791637874
Short name T97
Test name
Test status
Simulation time 11162340648 ps
CPU time 21.17 seconds
Started Jun 10 07:40:55 PM PDT 24
Finished Jun 10 07:41:18 PM PDT 24
Peak memory 217164 kb
Host smart-2f20df8a-8ba3-414f-8c9b-00fc288a4bee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791637874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3791637874
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1504248293
Short name T94
Test name
Test status
Simulation time 7007659268 ps
CPU time 218.77 seconds
Started Jun 10 07:40:52 PM PDT 24
Finished Jun 10 07:44:33 PM PDT 24
Peak memory 219292 kb
Host smart-61d0ed2b-7e01-446e-9a22-dd8e9d119b82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504248293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1504248293
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1601800166
Short name T352
Test name
Test status
Simulation time 11593939995 ps
CPU time 37.25 seconds
Started Jun 10 07:40:52 PM PDT 24
Finished Jun 10 07:41:31 PM PDT 24
Peak memory 219024 kb
Host smart-07ece6c4-c851-4bb6-a7a7-754a6919791e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601800166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1601800166
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3432096473
Short name T310
Test name
Test status
Simulation time 16481052980 ps
CPU time 34.51 seconds
Started Jun 10 07:40:52 PM PDT 24
Finished Jun 10 07:41:29 PM PDT 24
Peak memory 211448 kb
Host smart-d925bcb4-ce90-457a-8ba5-657fc9e28d5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3432096473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3432096473
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1588195750
Short name T230
Test name
Test status
Simulation time 2100113025 ps
CPU time 19.72 seconds
Started Jun 10 07:40:50 PM PDT 24
Finished Jun 10 07:41:11 PM PDT 24
Peak memory 216940 kb
Host smart-249adfd6-46e0-4e06-9a85-8f0eb5e9e2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588195750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1588195750
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.302318433
Short name T176
Test name
Test status
Simulation time 3961324840 ps
CPU time 39.74 seconds
Started Jun 10 07:40:53 PM PDT 24
Finished Jun 10 07:41:35 PM PDT 24
Peak memory 219088 kb
Host smart-71c86495-c2a4-4a94-8a3f-b77aa70980a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302318433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.302318433
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.295784649
Short name T54
Test name
Test status
Simulation time 124108945809 ps
CPU time 2460.34 seconds
Started Jun 10 07:40:51 PM PDT 24
Finished Jun 10 08:21:54 PM PDT 24
Peak memory 235624 kb
Host smart-932b069f-19ae-4a8f-9653-40a711f8f140
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295784649 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.295784649
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3172630202
Short name T32
Test name
Test status
Simulation time 3019639484 ps
CPU time 26.99 seconds
Started Jun 10 07:41:30 PM PDT 24
Finished Jun 10 07:41:59 PM PDT 24
Peak memory 216776 kb
Host smart-a37b4a86-8011-4422-a4eb-6558401b9e07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172630202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3172630202
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1974859190
Short name T146
Test name
Test status
Simulation time 72641860893 ps
CPU time 511.87 seconds
Started Jun 10 07:41:15 PM PDT 24
Finished Jun 10 07:49:49 PM PDT 24
Peak memory 242096 kb
Host smart-75abd70a-ef38-4a1f-8911-e88992400fe2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974859190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1974859190
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2436015047
Short name T264
Test name
Test status
Simulation time 4306753860 ps
CPU time 47.12 seconds
Started Jun 10 07:41:25 PM PDT 24
Finished Jun 10 07:42:15 PM PDT 24
Peak memory 219104 kb
Host smart-9fc3ec01-a52f-411d-a58c-69ec7578b235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436015047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2436015047
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.42962919
Short name T152
Test name
Test status
Simulation time 29853705656 ps
CPU time 60.1 seconds
Started Jun 10 07:41:16 PM PDT 24
Finished Jun 10 07:42:18 PM PDT 24
Peak memory 217060 kb
Host smart-1bae9aa9-052a-410a-bb07-79178f01ee79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42962919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.42962919
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.798120982
Short name T161
Test name
Test status
Simulation time 2122984853 ps
CPU time 26.32 seconds
Started Jun 10 07:41:16 PM PDT 24
Finished Jun 10 07:41:44 PM PDT 24
Peak memory 217656 kb
Host smart-0495d470-e84c-419d-8030-86bb329e4fdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798120982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.798120982
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2607371507
Short name T246
Test name
Test status
Simulation time 35498474401 ps
CPU time 383.92 seconds
Started Jun 10 07:41:24 PM PDT 24
Finished Jun 10 07:47:52 PM PDT 24
Peak memory 216608 kb
Host smart-43956876-6806-4663-be49-65c8a2f86cc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607371507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2607371507
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.92549682
Short name T163
Test name
Test status
Simulation time 16051636220 ps
CPU time 68.27 seconds
Started Jun 10 07:41:26 PM PDT 24
Finished Jun 10 07:42:38 PM PDT 24
Peak memory 219108 kb
Host smart-ea727075-9dc0-49de-836f-52921cb9107d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92549682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.92549682
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.589776747
Short name T273
Test name
Test status
Simulation time 221328098 ps
CPU time 10.37 seconds
Started Jun 10 07:41:13 PM PDT 24
Finished Jun 10 07:41:26 PM PDT 24
Peak memory 219084 kb
Host smart-4ad1ac04-2c8e-4aae-89f9-de019eecf37e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=589776747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.589776747
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1485730211
Short name T206
Test name
Test status
Simulation time 360055025 ps
CPU time 21.06 seconds
Started Jun 10 07:41:15 PM PDT 24
Finished Jun 10 07:41:38 PM PDT 24
Peak memory 215824 kb
Host smart-17be014c-0398-4e9e-914a-bc4ddd54ee94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485730211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1485730211
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2174750788
Short name T347
Test name
Test status
Simulation time 2029930429 ps
CPU time 29.98 seconds
Started Jun 10 07:41:15 PM PDT 24
Finished Jun 10 07:41:48 PM PDT 24
Peak memory 218984 kb
Host smart-1017005d-8ee6-45f2-9b30-81d3d5384a82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174750788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2174750788
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.396583556
Short name T318
Test name
Test status
Simulation time 4100791561 ps
CPU time 33.27 seconds
Started Jun 10 07:41:20 PM PDT 24
Finished Jun 10 07:41:56 PM PDT 24
Peak memory 216808 kb
Host smart-f51bfdbe-e6ac-4cc3-978a-e375e666d6a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396583556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.396583556
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.968485271
Short name T31
Test name
Test status
Simulation time 118119624044 ps
CPU time 630.62 seconds
Started Jun 10 07:41:24 PM PDT 24
Finished Jun 10 07:51:59 PM PDT 24
Peak memory 224772 kb
Host smart-34bb95ff-2f0a-4a23-a8b8-a2b5f6cd5f1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968485271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.968485271
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2309545331
Short name T256
Test name
Test status
Simulation time 511231818 ps
CPU time 13.85 seconds
Started Jun 10 07:41:16 PM PDT 24
Finished Jun 10 07:41:32 PM PDT 24
Peak memory 219172 kb
Host smart-441814cd-12cc-4bf7-9969-8377546b0272
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2309545331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2309545331
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2510390359
Short name T193
Test name
Test status
Simulation time 554871946 ps
CPU time 23 seconds
Started Jun 10 07:41:15 PM PDT 24
Finished Jun 10 07:41:41 PM PDT 24
Peak memory 215032 kb
Host smart-d8e752b0-61f2-4af4-9def-ca67665b53f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510390359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2510390359
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2686146511
Short name T331
Test name
Test status
Simulation time 3113717703 ps
CPU time 13.46 seconds
Started Jun 10 07:41:27 PM PDT 24
Finished Jun 10 07:41:44 PM PDT 24
Peak memory 216904 kb
Host smart-2f8c9baf-d410-4309-930d-1ffb50d91b51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686146511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2686146511
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.950550498
Short name T18
Test name
Test status
Simulation time 166732720006 ps
CPU time 560.04 seconds
Started Jun 10 07:41:26 PM PDT 24
Finished Jun 10 07:50:50 PM PDT 24
Peak memory 227148 kb
Host smart-2a8b5766-5dfb-4e7a-baa7-e2040aeede82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950550498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.950550498
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2342318821
Short name T7
Test name
Test status
Simulation time 3418831508 ps
CPU time 39.64 seconds
Started Jun 10 07:41:29 PM PDT 24
Finished Jun 10 07:42:11 PM PDT 24
Peak memory 219148 kb
Host smart-f424a898-340b-4030-9675-c09eea59b003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342318821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2342318821
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.331091652
Short name T262
Test name
Test status
Simulation time 2239271414 ps
CPU time 24.13 seconds
Started Jun 10 07:41:25 PM PDT 24
Finished Jun 10 07:41:53 PM PDT 24
Peak memory 219136 kb
Host smart-3bacc9c9-9cda-4043-a084-da9a44e100d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=331091652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.331091652
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.687759986
Short name T96
Test name
Test status
Simulation time 8233374976 ps
CPU time 77.49 seconds
Started Jun 10 07:41:28 PM PDT 24
Finished Jun 10 07:42:48 PM PDT 24
Peak memory 215764 kb
Host smart-284e55ca-bff3-4de9-b0bb-8012bc7a6ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687759986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.687759986
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2383413857
Short name T337
Test name
Test status
Simulation time 6709671545 ps
CPU time 61.23 seconds
Started Jun 10 07:41:24 PM PDT 24
Finished Jun 10 07:42:28 PM PDT 24
Peak memory 218012 kb
Host smart-cc39c938-35de-41a8-9e3b-3cc924dc658f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383413857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2383413857
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.4002033458
Short name T350
Test name
Test status
Simulation time 4178734330 ps
CPU time 32.85 seconds
Started Jun 10 07:41:32 PM PDT 24
Finished Jun 10 07:42:06 PM PDT 24
Peak memory 216896 kb
Host smart-e2db0d13-9e7c-4cbe-8155-e57ca1eaaf83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002033458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.4002033458
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4167261251
Short name T215
Test name
Test status
Simulation time 2622176187 ps
CPU time 170.16 seconds
Started Jun 10 07:41:24 PM PDT 24
Finished Jun 10 07:44:17 PM PDT 24
Peak memory 224492 kb
Host smart-79c063cf-dd31-4f82-8db3-3c377b474b2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167261251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.4167261251
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3638423367
Short name T158
Test name
Test status
Simulation time 31230723278 ps
CPU time 60.37 seconds
Started Jun 10 07:41:31 PM PDT 24
Finished Jun 10 07:42:33 PM PDT 24
Peak memory 218748 kb
Host smart-db5f2218-2840-4600-a0ed-85577d65b681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638423367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3638423367
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4043246473
Short name T328
Test name
Test status
Simulation time 3039573664 ps
CPU time 26.39 seconds
Started Jun 10 07:41:31 PM PDT 24
Finished Jun 10 07:41:59 PM PDT 24
Peak memory 218880 kb
Host smart-dab2503e-22ce-45d1-b396-61fc585396ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4043246473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4043246473
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3028848090
Short name T213
Test name
Test status
Simulation time 1519172861 ps
CPU time 32.77 seconds
Started Jun 10 07:41:31 PM PDT 24
Finished Jun 10 07:42:06 PM PDT 24
Peak memory 218976 kb
Host smart-91a28ca0-506a-4d00-8bce-b13cfa0b02d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028848090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3028848090
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2283420991
Short name T17
Test name
Test status
Simulation time 10147725653 ps
CPU time 23.93 seconds
Started Jun 10 07:41:25 PM PDT 24
Finished Jun 10 07:41:52 PM PDT 24
Peak memory 217264 kb
Host smart-3a6f3d98-b757-4f12-bd65-1a1bf29673dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283420991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2283420991
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1804997698
Short name T93
Test name
Test status
Simulation time 3771095835 ps
CPU time 257.65 seconds
Started Jun 10 07:41:30 PM PDT 24
Finished Jun 10 07:45:49 PM PDT 24
Peak memory 239696 kb
Host smart-58e45498-b8a3-4661-ba60-72901ad58189
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804997698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1804997698
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2307338370
Short name T311
Test name
Test status
Simulation time 5577197476 ps
CPU time 51.73 seconds
Started Jun 10 07:41:25 PM PDT 24
Finished Jun 10 07:42:21 PM PDT 24
Peak memory 219064 kb
Host smart-9f120c46-0fda-4e02-947a-561727424957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307338370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2307338370
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.539805053
Short name T147
Test name
Test status
Simulation time 187767484 ps
CPU time 10.58 seconds
Started Jun 10 07:41:30 PM PDT 24
Finished Jun 10 07:41:43 PM PDT 24
Peak memory 219004 kb
Host smart-0c6a4188-789c-4749-b6f6-1aefcc8da8bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=539805053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.539805053
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.4016031555
Short name T35
Test name
Test status
Simulation time 703073507 ps
CPU time 24.94 seconds
Started Jun 10 07:41:25 PM PDT 24
Finished Jun 10 07:41:53 PM PDT 24
Peak memory 216228 kb
Host smart-ddb36ccd-5b07-4c6d-b5b9-9a06a3c5a7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016031555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.4016031555
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1400412029
Short name T177
Test name
Test status
Simulation time 13831462037 ps
CPU time 167.19 seconds
Started Jun 10 07:41:24 PM PDT 24
Finished Jun 10 07:44:15 PM PDT 24
Peak memory 227332 kb
Host smart-40b54249-1538-4afa-b96b-e421023e8079
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400412029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1400412029
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3527660330
Short name T261
Test name
Test status
Simulation time 660239388 ps
CPU time 8.28 seconds
Started Jun 10 07:41:27 PM PDT 24
Finished Jun 10 07:41:39 PM PDT 24
Peak memory 216828 kb
Host smart-49348416-4699-4ac3-858e-6b29b21df075
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527660330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3527660330
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2099234434
Short name T335
Test name
Test status
Simulation time 227526589531 ps
CPU time 365.41 seconds
Started Jun 10 07:41:26 PM PDT 24
Finished Jun 10 07:47:35 PM PDT 24
Peak memory 236016 kb
Host smart-48d83718-0c6c-4f0b-aa03-48077b19cfd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099234434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2099234434
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.968617149
Short name T228
Test name
Test status
Simulation time 7870068646 ps
CPU time 44.21 seconds
Started Jun 10 07:41:26 PM PDT 24
Finished Jun 10 07:42:14 PM PDT 24
Peak memory 219080 kb
Host smart-c305a8f6-59bc-4b70-8661-0f8bb4c23ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968617149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.968617149
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.4181957611
Short name T165
Test name
Test status
Simulation time 2775852371 ps
CPU time 26.85 seconds
Started Jun 10 07:41:25 PM PDT 24
Finished Jun 10 07:41:56 PM PDT 24
Peak memory 219108 kb
Host smart-722d0a34-de1d-4c0d-917b-e8ab665d9465
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4181957611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.4181957611
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.505978066
Short name T338
Test name
Test status
Simulation time 60627599750 ps
CPU time 63.19 seconds
Started Jun 10 07:41:32 PM PDT 24
Finished Jun 10 07:42:37 PM PDT 24
Peak memory 215760 kb
Host smart-721d08c6-842c-47b0-a257-9438c836ef62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505978066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.505978066
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.807550069
Short name T207
Test name
Test status
Simulation time 555995249 ps
CPU time 33.4 seconds
Started Jun 10 07:41:26 PM PDT 24
Finished Jun 10 07:42:03 PM PDT 24
Peak memory 219044 kb
Host smart-968b34ba-3b58-41b1-b35d-5b745f21de05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807550069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.807550069
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.266962832
Short name T45
Test name
Test status
Simulation time 2763413801 ps
CPU time 24.25 seconds
Started Jun 10 07:41:38 PM PDT 24
Finished Jun 10 07:42:04 PM PDT 24
Peak memory 216896 kb
Host smart-cec7e24d-a913-4a15-8b39-68e9df98f669
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266962832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.266962832
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3010401729
Short name T38
Test name
Test status
Simulation time 19218966088 ps
CPU time 244.63 seconds
Started Jun 10 07:41:31 PM PDT 24
Finished Jun 10 07:45:37 PM PDT 24
Peak memory 235384 kb
Host smart-f9e3a837-5a77-4d69-9f2f-0bb2765e73b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010401729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3010401729
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2663476369
Short name T300
Test name
Test status
Simulation time 350807399 ps
CPU time 18.82 seconds
Started Jun 10 07:41:31 PM PDT 24
Finished Jun 10 07:41:52 PM PDT 24
Peak memory 218936 kb
Host smart-ec271ba0-9ae4-4116-b489-1f46d874ab16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663476369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2663476369
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3823541687
Short name T245
Test name
Test status
Simulation time 6855007308 ps
CPU time 20.66 seconds
Started Jun 10 07:41:25 PM PDT 24
Finished Jun 10 07:41:49 PM PDT 24
Peak memory 211740 kb
Host smart-869b0f5a-5a0a-4a90-9b28-98b0828540e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3823541687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3823541687
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1037312219
Short name T349
Test name
Test status
Simulation time 1978485473 ps
CPU time 29.6 seconds
Started Jun 10 07:41:32 PM PDT 24
Finished Jun 10 07:42:03 PM PDT 24
Peak memory 216312 kb
Host smart-3bfccc69-e29c-4339-888e-7712b589a21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037312219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1037312219
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3484708745
Short name T169
Test name
Test status
Simulation time 12130704006 ps
CPU time 39.04 seconds
Started Jun 10 07:41:25 PM PDT 24
Finished Jun 10 07:42:08 PM PDT 24
Peak memory 218960 kb
Host smart-595ae94f-8cf1-4529-9974-eb5bc5492c26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484708745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3484708745
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1983927841
Short name T226
Test name
Test status
Simulation time 8212395871 ps
CPU time 21.62 seconds
Started Jun 10 07:41:41 PM PDT 24
Finished Jun 10 07:42:04 PM PDT 24
Peak memory 217260 kb
Host smart-64a72ce1-d079-4b5e-947a-320f964032de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983927841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1983927841
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.440782180
Short name T296
Test name
Test status
Simulation time 14655637778 ps
CPU time 209.44 seconds
Started Jun 10 07:41:44 PM PDT 24
Finished Jun 10 07:45:15 PM PDT 24
Peak memory 228024 kb
Host smart-148e4c19-9b86-4b51-ab72-21b29b0f5918
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440782180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.440782180
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2477299079
Short name T199
Test name
Test status
Simulation time 11448862420 ps
CPU time 26.59 seconds
Started Jun 10 07:41:43 PM PDT 24
Finished Jun 10 07:42:11 PM PDT 24
Peak memory 211764 kb
Host smart-4f8d8a2f-b66e-4bed-a92c-cd059eb51be7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2477299079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2477299079
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3875253042
Short name T12
Test name
Test status
Simulation time 24964244253 ps
CPU time 55.53 seconds
Started Jun 10 07:41:43 PM PDT 24
Finished Jun 10 07:42:40 PM PDT 24
Peak memory 215620 kb
Host smart-9e263cdc-6a91-41a5-9a10-8b6f4f0a10f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875253042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3875253042
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3956806108
Short name T227
Test name
Test status
Simulation time 6905404415 ps
CPU time 47.63 seconds
Started Jun 10 07:41:42 PM PDT 24
Finished Jun 10 07:42:31 PM PDT 24
Peak memory 219480 kb
Host smart-cdc2ac00-f3b2-421b-a26e-9afa3bb1892a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956806108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3956806108
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1955206233
Short name T63
Test name
Test status
Simulation time 7886641611 ps
CPU time 20.81 seconds
Started Jun 10 07:41:40 PM PDT 24
Finished Jun 10 07:42:02 PM PDT 24
Peak memory 217144 kb
Host smart-7592f187-0caf-486e-b7fd-12b3d88e2253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955206233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1955206233
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1313515012
Short name T270
Test name
Test status
Simulation time 3018576814 ps
CPU time 212.39 seconds
Started Jun 10 07:41:43 PM PDT 24
Finished Jun 10 07:45:17 PM PDT 24
Peak memory 240296 kb
Host smart-08085c8f-e184-4975-bc2b-9fee5e663cd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313515012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1313515012
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1975707461
Short name T167
Test name
Test status
Simulation time 3664284516 ps
CPU time 19.51 seconds
Started Jun 10 07:41:40 PM PDT 24
Finished Jun 10 07:42:00 PM PDT 24
Peak memory 219056 kb
Host smart-5258a897-9923-4e89-a218-ed365aa4f6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975707461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1975707461
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2874313140
Short name T113
Test name
Test status
Simulation time 412836242 ps
CPU time 10.33 seconds
Started Jun 10 07:41:39 PM PDT 24
Finished Jun 10 07:41:51 PM PDT 24
Peak memory 219076 kb
Host smart-4cd63fdc-1e1e-4b4a-971e-9251d828f97c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2874313140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2874313140
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3380158966
Short name T136
Test name
Test status
Simulation time 1344679449 ps
CPU time 19.74 seconds
Started Jun 10 07:41:40 PM PDT 24
Finished Jun 10 07:42:01 PM PDT 24
Peak memory 216608 kb
Host smart-3eab7c35-47d9-4567-9f07-77b5f62afaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380158966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3380158966
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.4202768741
Short name T257
Test name
Test status
Simulation time 17589837962 ps
CPU time 52.71 seconds
Started Jun 10 07:41:43 PM PDT 24
Finished Jun 10 07:42:37 PM PDT 24
Peak memory 220248 kb
Host smart-ca0b154e-220d-4bfd-8a8f-ffbcc8bad679
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202768741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.4202768741
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2691734243
Short name T359
Test name
Test status
Simulation time 15708982618 ps
CPU time 30.38 seconds
Started Jun 10 07:41:04 PM PDT 24
Finished Jun 10 07:41:35 PM PDT 24
Peak memory 216980 kb
Host smart-2e1f66b8-6988-48e7-95c7-96f3a00d5a30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691734243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2691734243
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.823584533
Short name T192
Test name
Test status
Simulation time 52392356975 ps
CPU time 294.81 seconds
Started Jun 10 07:40:53 PM PDT 24
Finished Jun 10 07:45:50 PM PDT 24
Peak memory 229588 kb
Host smart-d7808fb1-89ee-4daa-9577-086a1db1d3bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823584533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.823584533
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2045565806
Short name T204
Test name
Test status
Simulation time 8163889884 ps
CPU time 68.54 seconds
Started Jun 10 07:40:53 PM PDT 24
Finished Jun 10 07:42:04 PM PDT 24
Peak memory 219096 kb
Host smart-54770118-5dda-4c59-bfb3-c04e6c5e8841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045565806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2045565806
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1578061276
Short name T129
Test name
Test status
Simulation time 3880162090 ps
CPU time 32.13 seconds
Started Jun 10 07:40:54 PM PDT 24
Finished Jun 10 07:41:28 PM PDT 24
Peak memory 219100 kb
Host smart-76d7a89a-994b-48e0-9b16-eb626ca82278
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1578061276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1578061276
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2573317814
Short name T20
Test name
Test status
Simulation time 4195525329 ps
CPU time 139.91 seconds
Started Jun 10 07:41:04 PM PDT 24
Finished Jun 10 07:43:25 PM PDT 24
Peak memory 241176 kb
Host smart-16949e68-90e5-4977-96d2-664167c24b11
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573317814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2573317814
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.286282076
Short name T252
Test name
Test status
Simulation time 3114506758 ps
CPU time 20.74 seconds
Started Jun 10 07:40:53 PM PDT 24
Finished Jun 10 07:41:16 PM PDT 24
Peak memory 215108 kb
Host smart-9c22a598-7889-4c8f-8335-0967ee6a412f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286282076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.286282076
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.4115058673
Short name T186
Test name
Test status
Simulation time 13086861633 ps
CPU time 47.16 seconds
Started Jun 10 07:40:54 PM PDT 24
Finished Jun 10 07:41:43 PM PDT 24
Peak memory 217452 kb
Host smart-97e7ae86-08f9-4723-a01f-287fdc352a1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115058673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.4115058673
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4086224370
Short name T343
Test name
Test status
Simulation time 28370083690 ps
CPU time 448.22 seconds
Started Jun 10 07:41:40 PM PDT 24
Finished Jun 10 07:49:09 PM PDT 24
Peak memory 237040 kb
Host smart-4d0116e9-472c-46f6-ba73-dd204c3e0bf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086224370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.4086224370
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1106497263
Short name T231
Test name
Test status
Simulation time 2016141473 ps
CPU time 26.82 seconds
Started Jun 10 07:41:42 PM PDT 24
Finished Jun 10 07:42:10 PM PDT 24
Peak memory 218988 kb
Host smart-eef014be-dfc7-49ea-898e-a6b5cec7f5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106497263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1106497263
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2122546779
Short name T266
Test name
Test status
Simulation time 748979179 ps
CPU time 19.99 seconds
Started Jun 10 07:41:40 PM PDT 24
Finished Jun 10 07:42:01 PM PDT 24
Peak memory 216032 kb
Host smart-a7c7211d-986c-4455-bc2b-0e96bf0f560c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122546779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2122546779
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2166125496
Short name T222
Test name
Test status
Simulation time 6921512175 ps
CPU time 76.94 seconds
Started Jun 10 07:41:40 PM PDT 24
Finished Jun 10 07:42:59 PM PDT 24
Peak memory 216692 kb
Host smart-c8745952-c009-4f0a-93e9-18719e37de5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166125496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2166125496
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2468806725
Short name T2
Test name
Test status
Simulation time 10020321936 ps
CPU time 25.4 seconds
Started Jun 10 07:41:38 PM PDT 24
Finished Jun 10 07:42:05 PM PDT 24
Peak memory 217260 kb
Host smart-d8fee881-4271-4c62-9f88-34142f9df747
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468806725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2468806725
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3274519097
Short name T140
Test name
Test status
Simulation time 134990480717 ps
CPU time 582.59 seconds
Started Jun 10 07:41:40 PM PDT 24
Finished Jun 10 07:51:23 PM PDT 24
Peak memory 234740 kb
Host smart-77649f1e-09c4-4399-8ed3-f5f5132b5484
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274519097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3274519097
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3969887348
Short name T189
Test name
Test status
Simulation time 7859041431 ps
CPU time 65.01 seconds
Started Jun 10 07:41:39 PM PDT 24
Finished Jun 10 07:42:45 PM PDT 24
Peak memory 219120 kb
Host smart-b3e73280-a1bb-49e0-b3dd-eb520fa38bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969887348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3969887348
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1103111891
Short name T308
Test name
Test status
Simulation time 2389700533 ps
CPU time 17.12 seconds
Started Jun 10 07:41:44 PM PDT 24
Finished Jun 10 07:42:03 PM PDT 24
Peak memory 219140 kb
Host smart-88384735-2bef-4c4c-8e66-0b88bac0b659
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103111891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1103111891
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2083745519
Short name T16
Test name
Test status
Simulation time 8673307377 ps
CPU time 70.94 seconds
Started Jun 10 07:41:39 PM PDT 24
Finished Jun 10 07:42:52 PM PDT 24
Peak memory 215828 kb
Host smart-9afe018f-3283-4887-9890-f9e72b1cc702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083745519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2083745519
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2231488539
Short name T354
Test name
Test status
Simulation time 6635302294 ps
CPU time 79.17 seconds
Started Jun 10 07:41:39 PM PDT 24
Finished Jun 10 07:43:00 PM PDT 24
Peak memory 219768 kb
Host smart-ffff15c3-57df-4fce-a56f-425d9c18a911
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231488539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2231488539
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2403877606
Short name T52
Test name
Test status
Simulation time 17216919744 ps
CPU time 665.7 seconds
Started Jun 10 07:41:40 PM PDT 24
Finished Jun 10 07:52:46 PM PDT 24
Peak memory 229576 kb
Host smart-b32226ce-b7ec-4fe2-a2a9-5e5c6a64634b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403877606 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2403877606
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.716149765
Short name T188
Test name
Test status
Simulation time 13864330302 ps
CPU time 30.03 seconds
Started Jun 10 07:41:49 PM PDT 24
Finished Jun 10 07:42:21 PM PDT 24
Peak memory 217084 kb
Host smart-a69fc2d6-0f8d-45c5-b156-c6eccb108a77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716149765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.716149765
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1039494649
Short name T190
Test name
Test status
Simulation time 12028456555 ps
CPU time 49.26 seconds
Started Jun 10 07:41:52 PM PDT 24
Finished Jun 10 07:42:44 PM PDT 24
Peak memory 219120 kb
Host smart-3a7277b4-b6a6-44d6-bd6f-50e8234d0256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039494649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1039494649
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2076877678
Short name T183
Test name
Test status
Simulation time 1355280043 ps
CPU time 12.83 seconds
Started Jun 10 07:41:51 PM PDT 24
Finished Jun 10 07:42:07 PM PDT 24
Peak memory 218536 kb
Host smart-54e7505b-3aa6-46f7-99cb-df3eaf2b790e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2076877678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2076877678
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2453834758
Short name T218
Test name
Test status
Simulation time 8549263799 ps
CPU time 74.97 seconds
Started Jun 10 07:41:43 PM PDT 24
Finished Jun 10 07:42:59 PM PDT 24
Peak memory 215444 kb
Host smart-7877e656-9c3c-4969-8aae-c714524cc2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453834758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2453834758
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1860336028
Short name T198
Test name
Test status
Simulation time 37523124951 ps
CPU time 103.22 seconds
Started Jun 10 07:41:51 PM PDT 24
Finished Jun 10 07:43:37 PM PDT 24
Peak memory 219156 kb
Host smart-03aaeecd-4d46-4304-b1a5-946a0ede9431
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860336028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1860336028
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.737077642
Short name T171
Test name
Test status
Simulation time 2850912287 ps
CPU time 24.93 seconds
Started Jun 10 07:41:50 PM PDT 24
Finished Jun 10 07:42:18 PM PDT 24
Peak memory 216940 kb
Host smart-5fd13f74-3207-4b21-bfd3-653738b22330
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737077642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.737077642
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2792553439
Short name T330
Test name
Test status
Simulation time 207286052327 ps
CPU time 430.62 seconds
Started Jun 10 07:41:50 PM PDT 24
Finished Jun 10 07:49:03 PM PDT 24
Peak memory 215524 kb
Host smart-ff180f76-8670-4ee2-b096-bfc58377338e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792553439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2792553439
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3386092204
Short name T191
Test name
Test status
Simulation time 2458155838 ps
CPU time 35.07 seconds
Started Jun 10 07:41:50 PM PDT 24
Finished Jun 10 07:42:28 PM PDT 24
Peak memory 219024 kb
Host smart-a97848ec-19d8-4e89-8b4a-d97f756f109e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386092204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3386092204
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1723026456
Short name T297
Test name
Test status
Simulation time 4678808840 ps
CPU time 24.12 seconds
Started Jun 10 07:41:52 PM PDT 24
Finished Jun 10 07:42:18 PM PDT 24
Peak memory 211460 kb
Host smart-35fc5c56-4757-4ec6-896c-2d5a0d913d04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1723026456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1723026456
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.540319746
Short name T131
Test name
Test status
Simulation time 15616426927 ps
CPU time 57.97 seconds
Started Jun 10 07:41:49 PM PDT 24
Finished Jun 10 07:42:49 PM PDT 24
Peak memory 216776 kb
Host smart-7ad58d18-fe33-450a-bb49-7b7c9bca9dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540319746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.540319746
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1346790555
Short name T205
Test name
Test status
Simulation time 14228616867 ps
CPU time 118.01 seconds
Started Jun 10 07:41:51 PM PDT 24
Finished Jun 10 07:43:51 PM PDT 24
Peak memory 219184 kb
Host smart-3fc57d86-b5ea-453d-9802-4453e8cfa694
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346790555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1346790555
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1049556115
Short name T283
Test name
Test status
Simulation time 7527559136 ps
CPU time 31.05 seconds
Started Jun 10 07:41:52 PM PDT 24
Finished Jun 10 07:42:25 PM PDT 24
Peak memory 217152 kb
Host smart-8382a3e4-f0e5-44c9-ae76-3f5104d6321d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049556115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1049556115
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3880297876
Short name T148
Test name
Test status
Simulation time 162668635033 ps
CPU time 830.09 seconds
Started Jun 10 07:41:50 PM PDT 24
Finished Jun 10 07:55:42 PM PDT 24
Peak memory 235120 kb
Host smart-e54ccd26-6c9a-4b2f-b905-037f650bf697
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880297876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3880297876
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3590219957
Short name T271
Test name
Test status
Simulation time 26661848024 ps
CPU time 63.29 seconds
Started Jun 10 07:41:48 PM PDT 24
Finished Jun 10 07:42:53 PM PDT 24
Peak memory 219124 kb
Host smart-2412399c-6f37-487f-aef7-d238891856a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590219957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3590219957
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.140036125
Short name T15
Test name
Test status
Simulation time 4925040551 ps
CPU time 18.3 seconds
Started Jun 10 07:41:52 PM PDT 24
Finished Jun 10 07:42:13 PM PDT 24
Peak memory 219204 kb
Host smart-5fbfea68-5350-45cb-9654-481b25479ffd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=140036125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.140036125
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.569759546
Short name T225
Test name
Test status
Simulation time 22643242861 ps
CPU time 58.32 seconds
Started Jun 10 07:41:51 PM PDT 24
Finished Jun 10 07:42:52 PM PDT 24
Peak memory 216944 kb
Host smart-4b7f02d8-62c3-4a5e-966c-c58c8b3381de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569759546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.569759546
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.454521200
Short name T247
Test name
Test status
Simulation time 41120602569 ps
CPU time 114.46 seconds
Started Jun 10 07:41:51 PM PDT 24
Finished Jun 10 07:43:48 PM PDT 24
Peak memory 220640 kb
Host smart-c0107f51-bdeb-473d-987c-4a6ac12ffbbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454521200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.454521200
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2862422228
Short name T185
Test name
Test status
Simulation time 3505281716 ps
CPU time 19.02 seconds
Started Jun 10 07:41:50 PM PDT 24
Finished Jun 10 07:42:12 PM PDT 24
Peak memory 216764 kb
Host smart-eba59cea-72d5-4a42-97e6-763b716f8b37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862422228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2862422228
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.800532779
Short name T208
Test name
Test status
Simulation time 143006174009 ps
CPU time 743.25 seconds
Started Jun 10 07:41:47 PM PDT 24
Finished Jun 10 07:54:12 PM PDT 24
Peak memory 234016 kb
Host smart-8d4054f9-daa1-417b-95a2-0607eb333c0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800532779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.800532779
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2582640679
Short name T233
Test name
Test status
Simulation time 338824209 ps
CPU time 19.36 seconds
Started Jun 10 07:41:47 PM PDT 24
Finished Jun 10 07:42:08 PM PDT 24
Peak memory 219020 kb
Host smart-e26e96f7-658e-42f1-9083-0ea3e59bb1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582640679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2582640679
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1779068206
Short name T322
Test name
Test status
Simulation time 22551174559 ps
CPU time 26.91 seconds
Started Jun 10 07:41:48 PM PDT 24
Finished Jun 10 07:42:17 PM PDT 24
Peak memory 219168 kb
Host smart-adfc739c-400f-4cc4-80f5-7c0ee9745535
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1779068206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1779068206
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3864630348
Short name T80
Test name
Test status
Simulation time 17160279606 ps
CPU time 52.72 seconds
Started Jun 10 07:41:50 PM PDT 24
Finished Jun 10 07:42:45 PM PDT 24
Peak memory 216188 kb
Host smart-2fd48826-c573-4e73-8592-36fa7d80dccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864630348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3864630348
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1424966484
Short name T223
Test name
Test status
Simulation time 2917601158 ps
CPU time 88.99 seconds
Started Jun 10 07:41:49 PM PDT 24
Finished Jun 10 07:43:20 PM PDT 24
Peak memory 219556 kb
Host smart-84438cc1-e5a0-4643-a157-5bdb9bdfebf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424966484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1424966484
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1115989672
Short name T240
Test name
Test status
Simulation time 3925402007 ps
CPU time 30.97 seconds
Started Jun 10 07:41:59 PM PDT 24
Finished Jun 10 07:42:32 PM PDT 24
Peak memory 216848 kb
Host smart-1c0014be-492a-4dda-8063-160b9881d0cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115989672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1115989672
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3354278399
Short name T99
Test name
Test status
Simulation time 860281248391 ps
CPU time 699.9 seconds
Started Jun 10 07:41:54 PM PDT 24
Finished Jun 10 07:53:36 PM PDT 24
Peak memory 241168 kb
Host smart-d8a479f5-b52f-42c2-97c0-2f563f76509c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354278399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3354278399
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1888401311
Short name T229
Test name
Test status
Simulation time 1382863518 ps
CPU time 28.6 seconds
Started Jun 10 07:41:52 PM PDT 24
Finished Jun 10 07:42:24 PM PDT 24
Peak memory 218316 kb
Host smart-6ca36a0b-8661-44e4-9a3a-b640f6941584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888401311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1888401311
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.4194355637
Short name T203
Test name
Test status
Simulation time 7597254118 ps
CPU time 32.75 seconds
Started Jun 10 07:41:49 PM PDT 24
Finished Jun 10 07:42:24 PM PDT 24
Peak memory 219116 kb
Host smart-c9962134-b659-4785-b46a-8b11e5727f81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4194355637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.4194355637
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3767994942
Short name T358
Test name
Test status
Simulation time 5267861116 ps
CPU time 43.43 seconds
Started Jun 10 07:41:51 PM PDT 24
Finished Jun 10 07:42:37 PM PDT 24
Peak memory 215816 kb
Host smart-def41b01-1cd8-483b-aff2-bfeca8169be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767994942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3767994942
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3382867463
Short name T76
Test name
Test status
Simulation time 1080507201 ps
CPU time 31.72 seconds
Started Jun 10 07:41:49 PM PDT 24
Finished Jun 10 07:42:23 PM PDT 24
Peak memory 218992 kb
Host smart-c439cc18-e08c-4c5f-824a-ce9209ed6c2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382867463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3382867463
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2015008028
Short name T150
Test name
Test status
Simulation time 2496973554 ps
CPU time 14.56 seconds
Started Jun 10 07:41:57 PM PDT 24
Finished Jun 10 07:42:13 PM PDT 24
Peak memory 216948 kb
Host smart-b788ddc9-e88d-463c-b70a-b3534a4305c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015008028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2015008028
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.809099801
Short name T39
Test name
Test status
Simulation time 25483225965 ps
CPU time 266.16 seconds
Started Jun 10 07:41:57 PM PDT 24
Finished Jun 10 07:46:25 PM PDT 24
Peak memory 235640 kb
Host smart-5ea8c6ea-4c73-44b8-a3eb-120a2a2c945b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809099801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.809099801
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.195027302
Short name T254
Test name
Test status
Simulation time 8179268761 ps
CPU time 33.09 seconds
Started Jun 10 07:42:00 PM PDT 24
Finished Jun 10 07:42:35 PM PDT 24
Peak memory 219068 kb
Host smart-58b6002d-15e6-42d2-9555-ef29a2f4297c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195027302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.195027302
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.892661612
Short name T64
Test name
Test status
Simulation time 178937987 ps
CPU time 10.38 seconds
Started Jun 10 07:41:59 PM PDT 24
Finished Jun 10 07:42:11 PM PDT 24
Peak memory 218996 kb
Host smart-49526459-fdf4-46e6-9513-7cd14c9c47cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=892661612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.892661612
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1904094305
Short name T212
Test name
Test status
Simulation time 26216820599 ps
CPU time 58.8 seconds
Started Jun 10 07:41:58 PM PDT 24
Finished Jun 10 07:42:59 PM PDT 24
Peak memory 217136 kb
Host smart-f2d3e4a7-e614-47e9-9f09-a98071b193eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904094305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1904094305
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.4117236407
Short name T75
Test name
Test status
Simulation time 11465163400 ps
CPU time 112.16 seconds
Started Jun 10 07:41:58 PM PDT 24
Finished Jun 10 07:43:52 PM PDT 24
Peak memory 219116 kb
Host smart-27c0e5dc-c4c4-45e8-80df-b78ec1d597c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117236407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.4117236407
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1051843514
Short name T236
Test name
Test status
Simulation time 7200841015 ps
CPU time 29.86 seconds
Started Jun 10 07:42:01 PM PDT 24
Finished Jun 10 07:42:32 PM PDT 24
Peak memory 217260 kb
Host smart-9d6eb5ff-1100-4a1c-aaf8-ae5116a2fb97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051843514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1051843514
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2033089825
Short name T49
Test name
Test status
Simulation time 246205913658 ps
CPU time 659.66 seconds
Started Jun 10 07:41:57 PM PDT 24
Finished Jun 10 07:52:59 PM PDT 24
Peak memory 240248 kb
Host smart-3184641e-5c19-4ef0-815e-1afee7bc41dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033089825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2033089825
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2230009792
Short name T36
Test name
Test status
Simulation time 1374621370 ps
CPU time 19.9 seconds
Started Jun 10 07:41:57 PM PDT 24
Finished Jun 10 07:42:19 PM PDT 24
Peak memory 218976 kb
Host smart-3f479832-3fda-48e9-bac1-f16af54b4528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230009792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2230009792
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.4016488469
Short name T312
Test name
Test status
Simulation time 4900830259 ps
CPU time 35.01 seconds
Started Jun 10 07:42:01 PM PDT 24
Finished Jun 10 07:42:37 PM PDT 24
Peak memory 219152 kb
Host smart-e8bdf407-729a-4701-bdee-53af5860ae9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4016488469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.4016488469
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1653805740
Short name T217
Test name
Test status
Simulation time 4484190889 ps
CPU time 35.75 seconds
Started Jun 10 07:41:59 PM PDT 24
Finished Jun 10 07:42:37 PM PDT 24
Peak memory 216756 kb
Host smart-db40b54e-c01d-45b9-bde6-5905cacb548e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653805740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1653805740
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2426545806
Short name T182
Test name
Test status
Simulation time 1915390232 ps
CPU time 25.3 seconds
Started Jun 10 07:42:01 PM PDT 24
Finished Jun 10 07:42:27 PM PDT 24
Peak memory 218896 kb
Host smart-28b38cfb-eb18-4fe4-a8ed-b422b4160fe3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426545806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2426545806
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3328148520
Short name T53
Test name
Test status
Simulation time 32606534620 ps
CPU time 657.64 seconds
Started Jun 10 07:42:01 PM PDT 24
Finished Jun 10 07:53:00 PM PDT 24
Peak memory 229888 kb
Host smart-b0cc39a3-f1dd-4a5c-b332-67fd97a11711
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328148520 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3328148520
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1271653746
Short name T224
Test name
Test status
Simulation time 12986075912 ps
CPU time 29.3 seconds
Started Jun 10 07:42:02 PM PDT 24
Finished Jun 10 07:42:33 PM PDT 24
Peak memory 217284 kb
Host smart-2605c7f1-ad95-4d3b-8c8d-ca5f0af0bd98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271653746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1271653746
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1788669030
Short name T211
Test name
Test status
Simulation time 187898249378 ps
CPU time 606.5 seconds
Started Jun 10 07:42:01 PM PDT 24
Finished Jun 10 07:52:09 PM PDT 24
Peak memory 236580 kb
Host smart-18dcf5f8-4eb7-467b-aa7b-dbaa5e13d72d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788669030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1788669030
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.512319608
Short name T346
Test name
Test status
Simulation time 34575112943 ps
CPU time 68.44 seconds
Started Jun 10 07:42:00 PM PDT 24
Finished Jun 10 07:43:10 PM PDT 24
Peak memory 219116 kb
Host smart-59728da9-3e96-430d-aedc-2edf66d7d4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512319608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.512319608
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3126004095
Short name T10
Test name
Test status
Simulation time 691408763 ps
CPU time 12.87 seconds
Started Jun 10 07:42:01 PM PDT 24
Finished Jun 10 07:42:15 PM PDT 24
Peak memory 218656 kb
Host smart-67cd52e2-a6ff-428d-b446-55cf84e26d08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3126004095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3126004095
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3311168370
Short name T6
Test name
Test status
Simulation time 6486070755 ps
CPU time 39.6 seconds
Started Jun 10 07:42:00 PM PDT 24
Finished Jun 10 07:42:41 PM PDT 24
Peak memory 216828 kb
Host smart-c244b531-448e-42ad-a7ef-c7ac1dcbc639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311168370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3311168370
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2994838508
Short name T23
Test name
Test status
Simulation time 1190080706 ps
CPU time 16.13 seconds
Started Jun 10 07:41:06 PM PDT 24
Finished Jun 10 07:41:24 PM PDT 24
Peak memory 216836 kb
Host smart-0b0881b9-58e2-46bc-b42f-76dfc0e0509b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994838508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2994838508
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1445801731
Short name T323
Test name
Test status
Simulation time 181538474414 ps
CPU time 550.32 seconds
Started Jun 10 07:41:05 PM PDT 24
Finished Jun 10 07:50:17 PM PDT 24
Peak memory 237812 kb
Host smart-d73ccb64-d3dc-42f0-88e5-ac9d4fad7e47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445801731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1445801731
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2975937354
Short name T242
Test name
Test status
Simulation time 1375828855 ps
CPU time 19.08 seconds
Started Jun 10 07:41:05 PM PDT 24
Finished Jun 10 07:41:26 PM PDT 24
Peak memory 218992 kb
Host smart-0b4b0b50-f346-4d55-b9f9-d3d3c2b1009f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975937354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2975937354
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3219891192
Short name T33
Test name
Test status
Simulation time 15316593418 ps
CPU time 32.34 seconds
Started Jun 10 07:41:06 PM PDT 24
Finished Jun 10 07:41:40 PM PDT 24
Peak memory 219208 kb
Host smart-91cd7897-b567-4cf5-ad71-2f9171850cd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3219891192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3219891192
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3053276986
Short name T22
Test name
Test status
Simulation time 33112375645 ps
CPU time 137.6 seconds
Started Jun 10 07:41:06 PM PDT 24
Finished Jun 10 07:43:26 PM PDT 24
Peak memory 237912 kb
Host smart-06931674-dca1-4eee-b6b1-8951063c5f8a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053276986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3053276986
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2437092008
Short name T316
Test name
Test status
Simulation time 4675550358 ps
CPU time 48.36 seconds
Started Jun 10 07:41:07 PM PDT 24
Finished Jun 10 07:41:57 PM PDT 24
Peak memory 216756 kb
Host smart-86217cc6-6f53-4b54-ac8c-69d098f2e796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437092008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2437092008
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.428645926
Short name T290
Test name
Test status
Simulation time 3699621344 ps
CPU time 61.09 seconds
Started Jun 10 07:41:06 PM PDT 24
Finished Jun 10 07:42:10 PM PDT 24
Peak memory 219024 kb
Host smart-c64134df-6956-46a6-b57d-9882d8d04912
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428645926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.428645926
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3577112217
Short name T293
Test name
Test status
Simulation time 16302097160 ps
CPU time 32.99 seconds
Started Jun 10 07:42:09 PM PDT 24
Finished Jun 10 07:42:44 PM PDT 24
Peak memory 217260 kb
Host smart-397d7705-8f36-414d-97b3-2a4ab58ce348
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577112217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3577112217
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.382463053
Short name T154
Test name
Test status
Simulation time 372368284679 ps
CPU time 1051.22 seconds
Started Jun 10 07:42:10 PM PDT 24
Finished Jun 10 07:59:43 PM PDT 24
Peak memory 227192 kb
Host smart-ccbe60ad-f721-49e0-8554-81ed2295f862
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382463053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.382463053
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1890671169
Short name T194
Test name
Test status
Simulation time 32024103839 ps
CPU time 68.72 seconds
Started Jun 10 07:42:08 PM PDT 24
Finished Jun 10 07:43:19 PM PDT 24
Peak memory 218960 kb
Host smart-dfaf82fb-8fc3-4a3d-81c3-ffa991619c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890671169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1890671169
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3004254325
Short name T307
Test name
Test status
Simulation time 5979986328 ps
CPU time 20.04 seconds
Started Jun 10 07:42:06 PM PDT 24
Finished Jun 10 07:42:29 PM PDT 24
Peak memory 219300 kb
Host smart-279ea162-3224-4ba5-85a3-66b694275153
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3004254325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3004254325
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1636096433
Short name T313
Test name
Test status
Simulation time 5817121476 ps
CPU time 72.72 seconds
Started Jun 10 07:42:02 PM PDT 24
Finished Jun 10 07:43:16 PM PDT 24
Peak memory 214428 kb
Host smart-25f644bc-d001-4792-8d1e-a8b09be3f4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636096433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1636096433
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.585946584
Short name T135
Test name
Test status
Simulation time 1993616748 ps
CPU time 37.36 seconds
Started Jun 10 07:42:08 PM PDT 24
Finished Jun 10 07:42:48 PM PDT 24
Peak memory 218852 kb
Host smart-0b0782a4-b12d-45a1-b023-2ebbe6a2ebe3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585946584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.585946584
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2455076611
Short name T55
Test name
Test status
Simulation time 333351926414 ps
CPU time 2337.52 seconds
Started Jun 10 07:42:07 PM PDT 24
Finished Jun 10 08:21:07 PM PDT 24
Peak memory 243824 kb
Host smart-a734b1b4-8fca-4f85-8948-f9a1c8b32869
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455076611 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2455076611
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1794197943
Short name T251
Test name
Test status
Simulation time 1178811621 ps
CPU time 8.45 seconds
Started Jun 10 07:42:07 PM PDT 24
Finished Jun 10 07:42:18 PM PDT 24
Peak memory 216916 kb
Host smart-f2f7f5c3-9804-45c6-8b5a-e02eb7c14b1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794197943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1794197943
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3097192973
Short name T301
Test name
Test status
Simulation time 2096018361 ps
CPU time 146.07 seconds
Started Jun 10 07:42:06 PM PDT 24
Finished Jun 10 07:44:34 PM PDT 24
Peak memory 229132 kb
Host smart-3c257b49-baa6-42c4-96c3-46c488bdab9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097192973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3097192973
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1446384437
Short name T4
Test name
Test status
Simulation time 11759492925 ps
CPU time 54.77 seconds
Started Jun 10 07:42:07 PM PDT 24
Finished Jun 10 07:43:04 PM PDT 24
Peak memory 219104 kb
Host smart-eeed9073-3d80-4643-9f57-4a9d2f7303f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446384437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1446384437
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1750983091
Short name T130
Test name
Test status
Simulation time 14079489425 ps
CPU time 29.54 seconds
Started Jun 10 07:42:09 PM PDT 24
Finished Jun 10 07:42:40 PM PDT 24
Peak memory 217484 kb
Host smart-c93aff34-29c2-4c0e-9185-b3a4d34d8db3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1750983091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1750983091
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3281581646
Short name T344
Test name
Test status
Simulation time 4953123107 ps
CPU time 56.66 seconds
Started Jun 10 07:42:05 PM PDT 24
Finished Jun 10 07:43:04 PM PDT 24
Peak memory 216116 kb
Host smart-d8ad9ab1-858f-48b9-8828-5f1e63178d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281581646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3281581646
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1832475512
Short name T221
Test name
Test status
Simulation time 75352380868 ps
CPU time 168.89 seconds
Started Jun 10 07:42:09 PM PDT 24
Finished Jun 10 07:45:01 PM PDT 24
Peak memory 220416 kb
Host smart-4f17ff5a-7e43-4155-b2f8-4de099d146d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832475512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1832475512
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3409274560
Short name T210
Test name
Test status
Simulation time 2100423489 ps
CPU time 15.3 seconds
Started Jun 10 07:42:06 PM PDT 24
Finished Jun 10 07:42:24 PM PDT 24
Peak memory 216676 kb
Host smart-4ed3e05b-9cc6-408d-b20b-cf5a51cc0f1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409274560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3409274560
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1365467710
Short name T292
Test name
Test status
Simulation time 62616140987 ps
CPU time 273.94 seconds
Started Jun 10 07:42:06 PM PDT 24
Finished Jun 10 07:46:42 PM PDT 24
Peak memory 219256 kb
Host smart-b7b45eb0-218d-4ce2-9e43-bf1ca02858df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365467710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1365467710
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3728976322
Short name T3
Test name
Test status
Simulation time 12148113416 ps
CPU time 52.67 seconds
Started Jun 10 07:42:09 PM PDT 24
Finished Jun 10 07:43:04 PM PDT 24
Peak memory 219120 kb
Host smart-45477fe0-d8da-4b8e-b174-678af0f37b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728976322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3728976322
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3936139906
Short name T289
Test name
Test status
Simulation time 723996653 ps
CPU time 10.3 seconds
Started Jun 10 07:42:07 PM PDT 24
Finished Jun 10 07:42:20 PM PDT 24
Peak memory 219152 kb
Host smart-85dfb143-f5ca-486d-8d15-dbe7231ed2f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3936139906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3936139906
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2687855505
Short name T174
Test name
Test status
Simulation time 3299036517 ps
CPU time 47.49 seconds
Started Jun 10 07:42:09 PM PDT 24
Finished Jun 10 07:42:59 PM PDT 24
Peak memory 216388 kb
Host smart-3434582f-990b-4cb3-92a2-2adf0f1c876e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687855505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2687855505
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1416996321
Short name T285
Test name
Test status
Simulation time 12126666763 ps
CPU time 149.57 seconds
Started Jun 10 07:42:06 PM PDT 24
Finished Jun 10 07:44:38 PM PDT 24
Peak memory 219152 kb
Host smart-d9994d39-f824-4ec9-bf29-e8d4ae1e0cfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416996321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1416996321
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2711276314
Short name T153
Test name
Test status
Simulation time 936808393 ps
CPU time 14.37 seconds
Started Jun 10 07:42:07 PM PDT 24
Finished Jun 10 07:42:24 PM PDT 24
Peak memory 216836 kb
Host smart-84d28cf5-e038-4d02-b5a1-924b1befc4cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711276314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2711276314
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1576232871
Short name T304
Test name
Test status
Simulation time 13081662463 ps
CPU time 262.87 seconds
Started Jun 10 07:42:09 PM PDT 24
Finished Jun 10 07:46:34 PM PDT 24
Peak memory 226640 kb
Host smart-c6e7adc5-f346-44b7-a435-1658223394c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576232871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1576232871
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3296941490
Short name T265
Test name
Test status
Simulation time 1376198133 ps
CPU time 19.4 seconds
Started Jun 10 07:42:09 PM PDT 24
Finished Jun 10 07:42:31 PM PDT 24
Peak memory 218964 kb
Host smart-fe6e1609-8ad7-438a-8354-543c3f8f223e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296941490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3296941490
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2058403774
Short name T151
Test name
Test status
Simulation time 13126965922 ps
CPU time 31.3 seconds
Started Jun 10 07:42:08 PM PDT 24
Finished Jun 10 07:42:41 PM PDT 24
Peak memory 219176 kb
Host smart-a63dbbbb-ff06-401a-89dd-1280cd540c10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2058403774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2058403774
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1773454685
Short name T168
Test name
Test status
Simulation time 30326746953 ps
CPU time 67.87 seconds
Started Jun 10 07:42:05 PM PDT 24
Finished Jun 10 07:43:15 PM PDT 24
Peak memory 215872 kb
Host smart-5382f682-d908-4811-812e-e2f707587837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773454685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1773454685
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3876934517
Short name T269
Test name
Test status
Simulation time 98494058149 ps
CPU time 140.92 seconds
Started Jun 10 07:42:07 PM PDT 24
Finished Jun 10 07:44:30 PM PDT 24
Peak memory 219384 kb
Host smart-b8b17cad-a7f5-4e9e-b123-035c99458c9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876934517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3876934517
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3639183518
Short name T201
Test name
Test status
Simulation time 21596891598 ps
CPU time 26.74 seconds
Started Jun 10 07:42:05 PM PDT 24
Finished Jun 10 07:42:34 PM PDT 24
Peak memory 217228 kb
Host smart-8403a863-fafa-42a5-95e4-b71e343b080c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639183518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3639183518
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.181604508
Short name T284
Test name
Test status
Simulation time 67300310000 ps
CPU time 728.91 seconds
Started Jun 10 07:42:08 PM PDT 24
Finished Jun 10 07:54:19 PM PDT 24
Peak memory 234424 kb
Host smart-116f0b9b-e3b1-4c38-b6ce-e772df52fa67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181604508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.181604508
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2020676993
Short name T280
Test name
Test status
Simulation time 9663250584 ps
CPU time 49.36 seconds
Started Jun 10 07:42:08 PM PDT 24
Finished Jun 10 07:42:59 PM PDT 24
Peak memory 219080 kb
Host smart-b0229d5a-538e-4121-b112-b899aa2f7a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020676993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2020676993
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1848373937
Short name T156
Test name
Test status
Simulation time 723471716 ps
CPU time 10.35 seconds
Started Jun 10 07:42:09 PM PDT 24
Finished Jun 10 07:42:21 PM PDT 24
Peak memory 217352 kb
Host smart-7cebba3b-d527-40be-9bbe-eb45cf4268c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1848373937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1848373937
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.966595364
Short name T98
Test name
Test status
Simulation time 3624326827 ps
CPU time 34.67 seconds
Started Jun 10 07:42:08 PM PDT 24
Finished Jun 10 07:42:45 PM PDT 24
Peak memory 215884 kb
Host smart-dabded18-791d-4546-8046-e82defcdcf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966595364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.966595364
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2876251855
Short name T361
Test name
Test status
Simulation time 54209226175 ps
CPU time 41.16 seconds
Started Jun 10 07:42:10 PM PDT 24
Finished Jun 10 07:42:53 PM PDT 24
Peak memory 218980 kb
Host smart-085bd22b-8b15-413b-a1fa-7d5ad3b7f770
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876251855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2876251855
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.4208557826
Short name T202
Test name
Test status
Simulation time 821271399 ps
CPU time 13.94 seconds
Started Jun 10 07:42:18 PM PDT 24
Finished Jun 10 07:42:33 PM PDT 24
Peak memory 216680 kb
Host smart-60f5db2d-2707-4e13-a5ff-43653fb434a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208557826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.4208557826
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.854476186
Short name T43
Test name
Test status
Simulation time 251655503618 ps
CPU time 626.53 seconds
Started Jun 10 07:42:18 PM PDT 24
Finished Jun 10 07:52:46 PM PDT 24
Peak memory 238216 kb
Host smart-a2225c72-4a6e-4b47-bb02-ec9ded9160ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854476186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.854476186
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2066079666
Short name T133
Test name
Test status
Simulation time 1353193075 ps
CPU time 24.73 seconds
Started Jun 10 07:42:18 PM PDT 24
Finished Jun 10 07:42:44 PM PDT 24
Peak memory 215172 kb
Host smart-3b0dc98d-3d75-4aba-bbf4-3f4192f7c781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066079666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2066079666
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3065639127
Short name T100
Test name
Test status
Simulation time 25959603646 ps
CPU time 29.64 seconds
Started Jun 10 07:42:19 PM PDT 24
Finished Jun 10 07:42:50 PM PDT 24
Peak memory 217480 kb
Host smart-2eccfacf-8f47-4198-a68a-440405cc8559
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3065639127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3065639127
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.775426439
Short name T303
Test name
Test status
Simulation time 14351004111 ps
CPU time 46.63 seconds
Started Jun 10 07:42:20 PM PDT 24
Finished Jun 10 07:43:08 PM PDT 24
Peak memory 216172 kb
Host smart-fd0dc7e9-5b42-4c5e-9822-7ba7acf91a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775426439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.775426439
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3959718431
Short name T267
Test name
Test status
Simulation time 5868958454 ps
CPU time 57.81 seconds
Started Jun 10 07:42:19 PM PDT 24
Finished Jun 10 07:43:18 PM PDT 24
Peak memory 220808 kb
Host smart-cc2badf1-9986-4f17-af36-57d655077115
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959718431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3959718431
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3695520402
Short name T238
Test name
Test status
Simulation time 9806953417 ps
CPU time 23.12 seconds
Started Jun 10 07:42:17 PM PDT 24
Finished Jun 10 07:42:40 PM PDT 24
Peak memory 217164 kb
Host smart-c94de3a4-7b29-4fcf-a0cb-ea40f42df296
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695520402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3695520402
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.914501514
Short name T29
Test name
Test status
Simulation time 35610720679 ps
CPU time 299.01 seconds
Started Jun 10 07:42:18 PM PDT 24
Finished Jun 10 07:47:19 PM PDT 24
Peak memory 235752 kb
Host smart-06b1ee19-7af7-43c2-92e4-1821e75a291c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914501514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.914501514
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1903532335
Short name T340
Test name
Test status
Simulation time 2170741848 ps
CPU time 33.7 seconds
Started Jun 10 07:42:19 PM PDT 24
Finished Jun 10 07:42:54 PM PDT 24
Peak memory 219056 kb
Host smart-dc76abd6-2f18-4023-8a49-91933f8b4462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903532335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1903532335
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2035598080
Short name T249
Test name
Test status
Simulation time 18952915655 ps
CPU time 32.55 seconds
Started Jun 10 07:42:20 PM PDT 24
Finished Jun 10 07:42:54 PM PDT 24
Peak memory 217480 kb
Host smart-b3149b2e-160f-46c4-a45d-45e4d1c9e574
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2035598080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2035598080
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2790741513
Short name T196
Test name
Test status
Simulation time 8210080662 ps
CPU time 53.51 seconds
Started Jun 10 07:42:20 PM PDT 24
Finished Jun 10 07:43:15 PM PDT 24
Peak memory 217108 kb
Host smart-82bffd81-8e39-47bd-876f-3be67f3dbc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790741513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2790741513
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.4100437962
Short name T279
Test name
Test status
Simulation time 6204640998 ps
CPU time 90.04 seconds
Started Jun 10 07:42:22 PM PDT 24
Finished Jun 10 07:43:53 PM PDT 24
Peak memory 219580 kb
Host smart-87f59c77-ab4f-4d04-af57-e855ec5fecb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100437962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.4100437962
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3176210283
Short name T277
Test name
Test status
Simulation time 3196193175 ps
CPU time 15.03 seconds
Started Jun 10 07:42:17 PM PDT 24
Finished Jun 10 07:42:33 PM PDT 24
Peak memory 216792 kb
Host smart-86f7ef89-b41b-4cdb-a27f-2f129118ac57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176210283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3176210283
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2590890394
Short name T40
Test name
Test status
Simulation time 616629503808 ps
CPU time 1145.32 seconds
Started Jun 10 07:42:18 PM PDT 24
Finished Jun 10 08:01:25 PM PDT 24
Peak memory 236376 kb
Host smart-ae0ba1e3-5d0f-419e-9fbc-dabb57c50186
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590890394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2590890394
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1404590897
Short name T216
Test name
Test status
Simulation time 28757734666 ps
CPU time 62.76 seconds
Started Jun 10 07:42:19 PM PDT 24
Finished Jun 10 07:43:24 PM PDT 24
Peak memory 219104 kb
Host smart-66c56e92-a13d-4fa3-8136-873953187bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404590897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1404590897
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4199822436
Short name T109
Test name
Test status
Simulation time 5337969502 ps
CPU time 26.68 seconds
Started Jun 10 07:42:19 PM PDT 24
Finished Jun 10 07:42:47 PM PDT 24
Peak memory 219208 kb
Host smart-e469cd3c-2c5f-4bd7-b3e0-b78698f7c324
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4199822436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.4199822436
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.741035674
Short name T160
Test name
Test status
Simulation time 44721321918 ps
CPU time 65.17 seconds
Started Jun 10 07:42:18 PM PDT 24
Finished Jun 10 07:43:25 PM PDT 24
Peak memory 216068 kb
Host smart-642067ce-1042-4063-ad86-38327b22ddc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741035674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.741035674
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1019997442
Short name T138
Test name
Test status
Simulation time 1554838446 ps
CPU time 16.47 seconds
Started Jun 10 07:42:21 PM PDT 24
Finished Jun 10 07:42:39 PM PDT 24
Peak memory 218872 kb
Host smart-1253aa73-7264-41cc-aa85-04254ff8af9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019997442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1019997442
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1114754464
Short name T253
Test name
Test status
Simulation time 340985855 ps
CPU time 10.67 seconds
Started Jun 10 07:42:28 PM PDT 24
Finished Jun 10 07:42:42 PM PDT 24
Peak memory 216756 kb
Host smart-dc433c3e-43bf-4bf2-9ae1-d1a501aa6e60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114754464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1114754464
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3159980178
Short name T341
Test name
Test status
Simulation time 139824248720 ps
CPU time 459.63 seconds
Started Jun 10 07:42:19 PM PDT 24
Finished Jun 10 07:50:00 PM PDT 24
Peak memory 239308 kb
Host smart-1c55a9ca-e42b-412c-aefe-c43b8454e84c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159980178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3159980178
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1956745871
Short name T286
Test name
Test status
Simulation time 6646455501 ps
CPU time 57.77 seconds
Started Jun 10 07:42:19 PM PDT 24
Finished Jun 10 07:43:18 PM PDT 24
Peak memory 219072 kb
Host smart-dbdd7b35-cc13-4b56-b125-c193524a0e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956745871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1956745871
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.784163416
Short name T195
Test name
Test status
Simulation time 9899410012 ps
CPU time 24.75 seconds
Started Jun 10 07:42:18 PM PDT 24
Finished Jun 10 07:42:44 PM PDT 24
Peak memory 219288 kb
Host smart-c4369967-0e93-4c50-b724-bccf343a3248
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=784163416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.784163416
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.254158325
Short name T243
Test name
Test status
Simulation time 23675457055 ps
CPU time 55.95 seconds
Started Jun 10 07:42:22 PM PDT 24
Finished Jun 10 07:43:19 PM PDT 24
Peak memory 217464 kb
Host smart-d8a5319a-61b1-46f8-a1f8-b9f0cd41c70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254158325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.254158325
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1398512447
Short name T14
Test name
Test status
Simulation time 48659600084 ps
CPU time 110.28 seconds
Started Jun 10 07:42:20 PM PDT 24
Finished Jun 10 07:44:12 PM PDT 24
Peak memory 219324 kb
Host smart-4b5c75fd-4471-4d9f-926a-a2134a1e3b4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398512447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1398512447
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1835111159
Short name T50
Test name
Test status
Simulation time 33244904270 ps
CPU time 690.75 seconds
Started Jun 10 07:42:18 PM PDT 24
Finished Jun 10 07:53:50 PM PDT 24
Peak memory 231128 kb
Host smart-7adc09ef-4ac1-4d57-ad59-5b52e1d23d0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835111159 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.1835111159
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.821092520
Short name T325
Test name
Test status
Simulation time 14806419547 ps
CPU time 32.14 seconds
Started Jun 10 07:42:28 PM PDT 24
Finished Jun 10 07:43:03 PM PDT 24
Peak memory 216980 kb
Host smart-28e6d059-3d1f-40f6-8a65-c83c3c3c4477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821092520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.821092520
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2463383847
Short name T348
Test name
Test status
Simulation time 5968597556 ps
CPU time 245.73 seconds
Started Jun 10 07:42:29 PM PDT 24
Finished Jun 10 07:46:39 PM PDT 24
Peak memory 240444 kb
Host smart-c5ef32ef-1e8f-4034-b6f0-b01bcc23a53f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463383847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2463383847
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.653794752
Short name T173
Test name
Test status
Simulation time 342358084 ps
CPU time 19.05 seconds
Started Jun 10 07:42:30 PM PDT 24
Finished Jun 10 07:42:54 PM PDT 24
Peak memory 218972 kb
Host smart-a3dae11e-e3d7-4b67-8584-c800df0e0588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653794752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.653794752
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2140646986
Short name T139
Test name
Test status
Simulation time 11682583160 ps
CPU time 27.22 seconds
Started Jun 10 07:42:27 PM PDT 24
Finished Jun 10 07:42:57 PM PDT 24
Peak memory 219124 kb
Host smart-5b2f020f-6682-4635-8e44-c720a3939a8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2140646986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2140646986
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1706090269
Short name T232
Test name
Test status
Simulation time 15809153259 ps
CPU time 80.22 seconds
Started Jun 10 07:42:28 PM PDT 24
Finished Jun 10 07:43:51 PM PDT 24
Peak memory 215880 kb
Host smart-884a5c14-bc6a-4c05-8294-24c564262b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706090269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1706090269
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.974192788
Short name T34
Test name
Test status
Simulation time 6780342013 ps
CPU time 126.81 seconds
Started Jun 10 07:42:30 PM PDT 24
Finished Jun 10 07:44:41 PM PDT 24
Peak memory 220832 kb
Host smart-5849e0e3-44db-43c3-a059-152ed6a09987
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974192788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.974192788
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3230418263
Short name T30
Test name
Test status
Simulation time 176422827 ps
CPU time 8.39 seconds
Started Jun 10 07:41:05 PM PDT 24
Finished Jun 10 07:41:16 PM PDT 24
Peak memory 216844 kb
Host smart-782ddcfa-563c-4428-9e84-a8bbb7ad1150
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230418263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3230418263
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.4077402328
Short name T145
Test name
Test status
Simulation time 187632647011 ps
CPU time 624.21 seconds
Started Jun 10 07:41:07 PM PDT 24
Finished Jun 10 07:51:34 PM PDT 24
Peak memory 237592 kb
Host smart-62aa721c-3d3a-4140-afee-8de58ec7e649
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077402328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.4077402328
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.290935948
Short name T355
Test name
Test status
Simulation time 27286354801 ps
CPU time 65.58 seconds
Started Jun 10 07:41:06 PM PDT 24
Finished Jun 10 07:42:14 PM PDT 24
Peak memory 219144 kb
Host smart-acd0ecb5-4fe8-4a3c-a1ef-b9c0be2fe6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290935948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.290935948
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1271956485
Short name T197
Test name
Test status
Simulation time 607124795 ps
CPU time 15.13 seconds
Started Jun 10 07:41:05 PM PDT 24
Finished Jun 10 07:41:22 PM PDT 24
Peak memory 219076 kb
Host smart-106cf20c-ab81-4c9c-a5d6-c22b7a3c2af8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1271956485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1271956485
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2788623493
Short name T27
Test name
Test status
Simulation time 4290719152 ps
CPU time 236.42 seconds
Started Jun 10 07:41:06 PM PDT 24
Finished Jun 10 07:45:05 PM PDT 24
Peak memory 234208 kb
Host smart-57453b73-f892-404c-9c5c-605b4c83daec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788623493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2788623493
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3336533886
Short name T329
Test name
Test status
Simulation time 26214040352 ps
CPU time 54.17 seconds
Started Jun 10 07:41:07 PM PDT 24
Finished Jun 10 07:42:04 PM PDT 24
Peak memory 215820 kb
Host smart-e82bca29-49fa-4e2e-be51-10e374836c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336533886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3336533886
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3923923390
Short name T78
Test name
Test status
Simulation time 8335356721 ps
CPU time 111.48 seconds
Started Jun 10 07:41:04 PM PDT 24
Finished Jun 10 07:42:57 PM PDT 24
Peak memory 219124 kb
Host smart-797109ec-ebba-4d37-9a27-c6c35567a934
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923923390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3923923390
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1778355617
Short name T353
Test name
Test status
Simulation time 887848349 ps
CPU time 9.97 seconds
Started Jun 10 07:42:27 PM PDT 24
Finished Jun 10 07:42:40 PM PDT 24
Peak memory 216664 kb
Host smart-ae1335ae-2d0f-4f4b-9f6f-a553548f2477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778355617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1778355617
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.163041180
Short name T172
Test name
Test status
Simulation time 8968787422 ps
CPU time 307.43 seconds
Started Jun 10 07:42:29 PM PDT 24
Finished Jun 10 07:47:40 PM PDT 24
Peak memory 229544 kb
Host smart-b375dfab-bbd4-4594-8d7b-9fda24a28bd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163041180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.163041180
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2900767669
Short name T342
Test name
Test status
Simulation time 34231130553 ps
CPU time 68.41 seconds
Started Jun 10 07:42:29 PM PDT 24
Finished Jun 10 07:43:41 PM PDT 24
Peak memory 219108 kb
Host smart-43302b48-50ea-48d6-865e-db1fb8faffc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900767669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2900767669
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.597157179
Short name T278
Test name
Test status
Simulation time 209248358 ps
CPU time 10.57 seconds
Started Jun 10 07:42:29 PM PDT 24
Finished Jun 10 07:42:43 PM PDT 24
Peak memory 219052 kb
Host smart-d5c16bba-4fee-4ac1-a1aa-4359dad6d085
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=597157179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.597157179
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.4293773794
Short name T309
Test name
Test status
Simulation time 23631128766 ps
CPU time 55.99 seconds
Started Jun 10 07:42:30 PM PDT 24
Finished Jun 10 07:43:30 PM PDT 24
Peak memory 216768 kb
Host smart-05c82c31-20d9-4dab-adbf-fb4e26ee7f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293773794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.4293773794
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3717454771
Short name T144
Test name
Test status
Simulation time 77037838942 ps
CPU time 152.63 seconds
Started Jun 10 07:42:28 PM PDT 24
Finished Jun 10 07:45:04 PM PDT 24
Peak memory 220776 kb
Host smart-f9b0d77c-6f98-4ae8-bbf5-21f203decd0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717454771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3717454771
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.207113997
Short name T263
Test name
Test status
Simulation time 2452545082 ps
CPU time 22.7 seconds
Started Jun 10 07:42:30 PM PDT 24
Finished Jun 10 07:42:57 PM PDT 24
Peak memory 216852 kb
Host smart-e39a0b38-0466-4a07-b2fb-d797728b5c43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207113997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.207113997
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.94687398
Short name T357
Test name
Test status
Simulation time 52215831942 ps
CPU time 573.78 seconds
Started Jun 10 07:42:30 PM PDT 24
Finished Jun 10 07:52:08 PM PDT 24
Peak memory 218644 kb
Host smart-258e31bd-8d11-43bf-ad12-8ff35ea44e1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94687398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_co
rrupt_sig_fatal_chk.94687398
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.4014178460
Short name T1
Test name
Test status
Simulation time 8435263520 ps
CPU time 66.05 seconds
Started Jun 10 07:42:29 PM PDT 24
Finished Jun 10 07:43:39 PM PDT 24
Peak memory 219092 kb
Host smart-2f1c5a35-28a1-478a-be98-50a093d81b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014178460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.4014178460
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1227262130
Short name T179
Test name
Test status
Simulation time 179627021 ps
CPU time 11.07 seconds
Started Jun 10 07:42:28 PM PDT 24
Finished Jun 10 07:42:43 PM PDT 24
Peak memory 219032 kb
Host smart-5f4e94e1-4c53-4cc9-b204-e4e85048690a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1227262130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1227262130
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1001149327
Short name T166
Test name
Test status
Simulation time 5831500044 ps
CPU time 56.59 seconds
Started Jun 10 07:42:28 PM PDT 24
Finished Jun 10 07:43:28 PM PDT 24
Peak memory 216508 kb
Host smart-a0618fed-45c9-4a97-b1a0-48e5ae6292df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001149327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1001149327
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.4232079677
Short name T200
Test name
Test status
Simulation time 802543630 ps
CPU time 11.17 seconds
Started Jun 10 07:42:27 PM PDT 24
Finished Jun 10 07:42:41 PM PDT 24
Peak memory 214148 kb
Host smart-78f903d5-d6e8-4b4a-bd15-1bc6b56be3a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232079677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.4232079677
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1224855938
Short name T62
Test name
Test status
Simulation time 16026289661 ps
CPU time 31.16 seconds
Started Jun 10 07:42:30 PM PDT 24
Finished Jun 10 07:43:05 PM PDT 24
Peak memory 217180 kb
Host smart-4adaa07c-9c49-4787-af74-1cbe5f667ef4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224855938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1224855938
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3666413953
Short name T134
Test name
Test status
Simulation time 42477025496 ps
CPU time 35.55 seconds
Started Jun 10 07:42:28 PM PDT 24
Finished Jun 10 07:43:06 PM PDT 24
Peak memory 219084 kb
Host smart-c4dc704f-1b63-4700-95a2-fc17d4951d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666413953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3666413953
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2974580870
Short name T259
Test name
Test status
Simulation time 6423362684 ps
CPU time 29.17 seconds
Started Jun 10 07:42:28 PM PDT 24
Finished Jun 10 07:43:00 PM PDT 24
Peak memory 219212 kb
Host smart-68631dba-e6d1-4a32-82c8-09d7f001a976
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2974580870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2974580870
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3789916672
Short name T294
Test name
Test status
Simulation time 13225611787 ps
CPU time 67.1 seconds
Started Jun 10 07:42:31 PM PDT 24
Finished Jun 10 07:43:42 PM PDT 24
Peak memory 217572 kb
Host smart-db474dd6-98ff-4e8c-8f77-21c623777ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789916672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3789916672
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3977770432
Short name T306
Test name
Test status
Simulation time 6895527982 ps
CPU time 91.81 seconds
Started Jun 10 07:42:29 PM PDT 24
Finished Jun 10 07:44:05 PM PDT 24
Peak memory 219196 kb
Host smart-35e547fe-5ecf-4af2-94af-b03681ca1dd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977770432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3977770432
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1723129566
Short name T334
Test name
Test status
Simulation time 1299785712 ps
CPU time 16.85 seconds
Started Jun 10 07:42:36 PM PDT 24
Finished Jun 10 07:42:57 PM PDT 24
Peak memory 216920 kb
Host smart-ba7ca8ee-3885-4a7a-aedb-386836cf1b18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723129566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1723129566
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3979027971
Short name T128
Test name
Test status
Simulation time 5497666404 ps
CPU time 183.94 seconds
Started Jun 10 07:42:37 PM PDT 24
Finished Jun 10 07:45:45 PM PDT 24
Peak memory 245900 kb
Host smart-1bf6cfb0-c2f8-489e-ba1c-296b6d25dede
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979027971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3979027971
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3457830170
Short name T241
Test name
Test status
Simulation time 27607542098 ps
CPU time 60.83 seconds
Started Jun 10 07:42:35 PM PDT 24
Finished Jun 10 07:43:39 PM PDT 24
Peak memory 218960 kb
Host smart-8ab58398-e93d-46f3-840c-fe6ccf707aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457830170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3457830170
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1915869245
Short name T114
Test name
Test status
Simulation time 182386425 ps
CPU time 10.09 seconds
Started Jun 10 07:42:45 PM PDT 24
Finished Jun 10 07:42:56 PM PDT 24
Peak memory 219068 kb
Host smart-363ddd55-67f7-4312-923e-34cd146c2210
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1915869245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1915869245
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1273146737
Short name T276
Test name
Test status
Simulation time 29551959870 ps
CPU time 78.3 seconds
Started Jun 10 07:42:31 PM PDT 24
Finished Jun 10 07:43:54 PM PDT 24
Peak memory 217356 kb
Host smart-5864aae6-bbb6-4174-95de-ac327c91eab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273146737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1273146737
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.318525009
Short name T272
Test name
Test status
Simulation time 29249704613 ps
CPU time 229.61 seconds
Started Jun 10 07:42:36 PM PDT 24
Finished Jun 10 07:46:29 PM PDT 24
Peak memory 221924 kb
Host smart-ca2329e7-b70f-4ea3-bfb8-42ffd226563a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318525009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.318525009
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.988022661
Short name T314
Test name
Test status
Simulation time 1654843952 ps
CPU time 18.52 seconds
Started Jun 10 07:42:39 PM PDT 24
Finished Jun 10 07:43:01 PM PDT 24
Peak memory 216748 kb
Host smart-e45a2f60-14cb-4d6e-86e8-0d0698a08674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988022661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.988022661
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2279575662
Short name T37
Test name
Test status
Simulation time 17073205041 ps
CPU time 198.05 seconds
Started Jun 10 07:42:36 PM PDT 24
Finished Jun 10 07:45:58 PM PDT 24
Peak memory 229344 kb
Host smart-2cfd6266-d150-42cf-bd1a-fa7488c338f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279575662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2279575662
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1412638573
Short name T360
Test name
Test status
Simulation time 6185558022 ps
CPU time 29.79 seconds
Started Jun 10 07:42:36 PM PDT 24
Finished Jun 10 07:43:10 PM PDT 24
Peak memory 219128 kb
Host smart-b52d3ab4-7201-47b6-8611-8a4ee27e4e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412638573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1412638573
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1438608994
Short name T244
Test name
Test status
Simulation time 20911862936 ps
CPU time 24.84 seconds
Started Jun 10 07:42:36 PM PDT 24
Finished Jun 10 07:43:04 PM PDT 24
Peak memory 219128 kb
Host smart-4efa4f76-c5bd-4bf7-90f1-712be44f1298
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1438608994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1438608994
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2862295320
Short name T288
Test name
Test status
Simulation time 9722484661 ps
CPU time 56.42 seconds
Started Jun 10 07:42:38 PM PDT 24
Finished Jun 10 07:43:39 PM PDT 24
Peak memory 216136 kb
Host smart-762e1ebb-df93-4787-9f04-7aa259518374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862295320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2862295320
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3130154545
Short name T299
Test name
Test status
Simulation time 6049706198 ps
CPU time 108.26 seconds
Started Jun 10 07:42:36 PM PDT 24
Finished Jun 10 07:44:28 PM PDT 24
Peak memory 219824 kb
Host smart-ae83d1da-230e-49d5-98a6-88239992827d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130154545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3130154545
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2151811827
Short name T51
Test name
Test status
Simulation time 24120396950 ps
CPU time 945.79 seconds
Started Jun 10 07:42:44 PM PDT 24
Finished Jun 10 07:58:32 PM PDT 24
Peak memory 220428 kb
Host smart-e582e97a-404c-45bb-a708-234d6b5be473
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151811827 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2151811827
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.758197344
Short name T291
Test name
Test status
Simulation time 4479622155 ps
CPU time 15.3 seconds
Started Jun 10 07:42:38 PM PDT 24
Finished Jun 10 07:42:57 PM PDT 24
Peak memory 217168 kb
Host smart-c4c306cf-7643-4822-aa1d-fd5b05e5c13b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758197344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.758197344
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1712804785
Short name T260
Test name
Test status
Simulation time 10343315237 ps
CPU time 202.01 seconds
Started Jun 10 07:42:38 PM PDT 24
Finished Jun 10 07:46:04 PM PDT 24
Peak memory 236640 kb
Host smart-5ecb2c84-8384-4547-aa5f-4a241a8501b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712804785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1712804785
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.92805119
Short name T175
Test name
Test status
Simulation time 7310508197 ps
CPU time 33.3 seconds
Started Jun 10 07:42:38 PM PDT 24
Finished Jun 10 07:43:15 PM PDT 24
Peak memory 219124 kb
Host smart-acfab885-0d9d-44f1-8ba9-7c7d0a2ac3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92805119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.92805119
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1777385951
Short name T274
Test name
Test status
Simulation time 3438048551 ps
CPU time 30.35 seconds
Started Jun 10 07:42:35 PM PDT 24
Finished Jun 10 07:43:09 PM PDT 24
Peak memory 219084 kb
Host smart-038f0c78-1a17-4c7e-b188-6ce3336f4917
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1777385951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1777385951
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3462896546
Short name T305
Test name
Test status
Simulation time 1264587180 ps
CPU time 19.53 seconds
Started Jun 10 07:42:44 PM PDT 24
Finished Jun 10 07:43:05 PM PDT 24
Peak memory 216256 kb
Host smart-52b92898-ac28-4a05-b675-cef3a8442362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462896546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3462896546
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2059148664
Short name T345
Test name
Test status
Simulation time 3547146264 ps
CPU time 59.69 seconds
Started Jun 10 07:42:38 PM PDT 24
Finished Jun 10 07:43:41 PM PDT 24
Peak memory 219272 kb
Host smart-5b9ef0a4-4949-4daf-b10d-cae69459f4f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059148664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2059148664
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2658381567
Short name T178
Test name
Test status
Simulation time 3382453484 ps
CPU time 28.96 seconds
Started Jun 10 07:42:39 PM PDT 24
Finished Jun 10 07:43:12 PM PDT 24
Peak memory 216828 kb
Host smart-b689b54f-dc29-4d89-a7c0-6f7e261a3661
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658381567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2658381567
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3549362955
Short name T155
Test name
Test status
Simulation time 63070704952 ps
CPU time 616.22 seconds
Started Jun 10 07:42:37 PM PDT 24
Finished Jun 10 07:52:57 PM PDT 24
Peak memory 233472 kb
Host smart-bc63b68c-aa74-4733-968c-e61f1a10f043
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549362955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3549362955
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4169976191
Short name T336
Test name
Test status
Simulation time 347200955 ps
CPU time 19.38 seconds
Started Jun 10 07:42:50 PM PDT 24
Finished Jun 10 07:43:12 PM PDT 24
Peak memory 218900 kb
Host smart-6d25f642-5eeb-4fc6-a085-9c371f3e53fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169976191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4169976191
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2322042243
Short name T332
Test name
Test status
Simulation time 13426461814 ps
CPU time 30.57 seconds
Started Jun 10 07:42:38 PM PDT 24
Finished Jun 10 07:43:13 PM PDT 24
Peak memory 219168 kb
Host smart-3f3cff9c-a5c2-4126-adee-b87d542a329e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2322042243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2322042243
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1450293932
Short name T214
Test name
Test status
Simulation time 32063755432 ps
CPU time 67.3 seconds
Started Jun 10 07:42:36 PM PDT 24
Finished Jun 10 07:43:46 PM PDT 24
Peak memory 215604 kb
Host smart-989c9402-e314-446d-bbe6-40cc1f5d3977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450293932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1450293932
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3229087984
Short name T95
Test name
Test status
Simulation time 373933769 ps
CPU time 25.18 seconds
Started Jun 10 07:42:36 PM PDT 24
Finished Jun 10 07:43:05 PM PDT 24
Peak memory 218968 kb
Host smart-52bedc6f-ed83-4c74-acef-43c22ba5ed7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229087984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3229087984
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.350042207
Short name T170
Test name
Test status
Simulation time 2133968504 ps
CPU time 15.26 seconds
Started Jun 10 07:42:47 PM PDT 24
Finished Jun 10 07:43:05 PM PDT 24
Peak memory 216648 kb
Host smart-16a5741a-9c71-48b5-ae34-0ff8f1aadc9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350042207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.350042207
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3167500952
Short name T41
Test name
Test status
Simulation time 789876462339 ps
CPU time 1012.42 seconds
Started Jun 10 07:42:46 PM PDT 24
Finished Jun 10 07:59:41 PM PDT 24
Peak memory 219340 kb
Host smart-08cd43e9-65b6-4788-9bc9-5d1d9be5c419
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167500952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3167500952
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3055152585
Short name T187
Test name
Test status
Simulation time 2818587770 ps
CPU time 37.59 seconds
Started Jun 10 07:42:44 PM PDT 24
Finished Jun 10 07:43:23 PM PDT 24
Peak memory 219076 kb
Host smart-eb2c0987-9511-4a43-8e05-842c8ff3ec3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055152585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3055152585
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1525877715
Short name T327
Test name
Test status
Simulation time 184306318 ps
CPU time 10.45 seconds
Started Jun 10 07:42:36 PM PDT 24
Finished Jun 10 07:42:50 PM PDT 24
Peak memory 219056 kb
Host smart-03d0f566-f585-4094-94b5-325b8238526c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1525877715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1525877715
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3087096536
Short name T351
Test name
Test status
Simulation time 4862634618 ps
CPU time 54.26 seconds
Started Jun 10 07:42:45 PM PDT 24
Finished Jun 10 07:43:40 PM PDT 24
Peak memory 216504 kb
Host smart-0ba6511e-cd73-42e6-8fdb-32cf636a44a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087096536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3087096536
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2403729225
Short name T255
Test name
Test status
Simulation time 2211776218 ps
CPU time 31.59 seconds
Started Jun 10 07:42:37 PM PDT 24
Finished Jun 10 07:43:13 PM PDT 24
Peak memory 219080 kb
Host smart-ecd727da-6b0e-43be-a89c-1ec1a88ac043
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403729225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2403729225
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1961707102
Short name T159
Test name
Test status
Simulation time 3998380654 ps
CPU time 31.11 seconds
Started Jun 10 07:42:46 PM PDT 24
Finished Jun 10 07:43:19 PM PDT 24
Peak memory 216904 kb
Host smart-a2ca2958-1b30-43df-b1c4-931e4ff29b23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961707102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1961707102
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2533587493
Short name T19
Test name
Test status
Simulation time 20177984041 ps
CPU time 221.75 seconds
Started Jun 10 07:42:47 PM PDT 24
Finished Jun 10 07:46:32 PM PDT 24
Peak memory 233580 kb
Host smart-81a00385-4baf-409f-9adb-e0b5c3358439
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533587493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2533587493
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.4185777811
Short name T315
Test name
Test status
Simulation time 17750536901 ps
CPU time 47.32 seconds
Started Jun 10 07:42:46 PM PDT 24
Finished Jun 10 07:43:36 PM PDT 24
Peak memory 219088 kb
Host smart-49efc420-f70e-47c5-bff1-948d03fa97db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185777811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.4185777811
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1769247378
Short name T281
Test name
Test status
Simulation time 2888101076 ps
CPU time 10.43 seconds
Started Jun 10 07:42:46 PM PDT 24
Finished Jun 10 07:42:58 PM PDT 24
Peak memory 219116 kb
Host smart-72721b7b-ddaf-4bc5-a0e6-69ef830e7c3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1769247378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1769247378
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1960534692
Short name T235
Test name
Test status
Simulation time 13798840856 ps
CPU time 68.66 seconds
Started Jun 10 07:42:45 PM PDT 24
Finished Jun 10 07:43:55 PM PDT 24
Peak memory 216096 kb
Host smart-9571d12f-a0a2-4cf5-8b14-6593ec553dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960534692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1960534692
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2098816807
Short name T250
Test name
Test status
Simulation time 16105214946 ps
CPU time 93.09 seconds
Started Jun 10 07:42:48 PM PDT 24
Finished Jun 10 07:44:24 PM PDT 24
Peak memory 219164 kb
Host smart-5f2c5775-9624-49e8-bf62-a874e138fd92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098816807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2098816807
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2650231421
Short name T24
Test name
Test status
Simulation time 15406522693 ps
CPU time 645.07 seconds
Started Jun 10 07:42:47 PM PDT 24
Finished Jun 10 07:53:34 PM PDT 24
Peak memory 231352 kb
Host smart-33f6d881-a333-465d-a2cb-eb9373322ea1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650231421 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2650231421
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.397779894
Short name T162
Test name
Test status
Simulation time 2727468653 ps
CPU time 25.25 seconds
Started Jun 10 07:42:47 PM PDT 24
Finished Jun 10 07:43:15 PM PDT 24
Peak memory 216956 kb
Host smart-137322bd-2e97-42d9-b460-1cdf608fc66e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397779894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.397779894
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.33386564
Short name T287
Test name
Test status
Simulation time 2620024252 ps
CPU time 36.02 seconds
Started Jun 10 07:42:50 PM PDT 24
Finished Jun 10 07:43:29 PM PDT 24
Peak memory 218948 kb
Host smart-00d4f698-6e2d-4b5f-8cc1-8b3149c6b4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33386564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.33386564
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.219783647
Short name T219
Test name
Test status
Simulation time 13436444168 ps
CPU time 19.63 seconds
Started Jun 10 07:42:48 PM PDT 24
Finished Jun 10 07:43:11 PM PDT 24
Peak memory 217472 kb
Host smart-d9bf7acf-871c-416c-ba19-76ac7585dee8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=219783647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.219783647
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2491651721
Short name T11
Test name
Test status
Simulation time 2312590498 ps
CPU time 33.52 seconds
Started Jun 10 07:42:47 PM PDT 24
Finished Jun 10 07:43:24 PM PDT 24
Peak memory 216904 kb
Host smart-965bfdc7-69ff-4bbb-a0ab-3d0be7035f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491651721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2491651721
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3703852374
Short name T74
Test name
Test status
Simulation time 13463240176 ps
CPU time 135.09 seconds
Started Jun 10 07:42:47 PM PDT 24
Finished Jun 10 07:45:05 PM PDT 24
Peak memory 219240 kb
Host smart-b67689d6-4250-40f9-b2cf-bbfce6e13a84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703852374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3703852374
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3969106107
Short name T339
Test name
Test status
Simulation time 2467210203 ps
CPU time 16.71 seconds
Started Jun 10 07:41:04 PM PDT 24
Finished Jun 10 07:41:22 PM PDT 24
Peak memory 216980 kb
Host smart-19e09635-af72-4b29-ac31-6baa27abdaee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969106107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3969106107
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1392535084
Short name T149
Test name
Test status
Simulation time 9061909554 ps
CPU time 181.6 seconds
Started Jun 10 07:41:06 PM PDT 24
Finished Jun 10 07:44:10 PM PDT 24
Peak memory 236728 kb
Host smart-44ef7dcc-44fc-4054-a416-28324bd06428
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392535084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1392535084
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2521870980
Short name T234
Test name
Test status
Simulation time 1376464543 ps
CPU time 18.9 seconds
Started Jun 10 07:41:06 PM PDT 24
Finished Jun 10 07:41:27 PM PDT 24
Peak memory 218968 kb
Host smart-58a6093c-6043-4da3-b291-91b84b93fd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521870980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2521870980
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3828532015
Short name T275
Test name
Test status
Simulation time 2924668487 ps
CPU time 27.46 seconds
Started Jun 10 07:41:08 PM PDT 24
Finished Jun 10 07:41:38 PM PDT 24
Peak memory 219040 kb
Host smart-6437d28a-7c30-458d-b53c-b3495a797da2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3828532015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3828532015
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.276430983
Short name T282
Test name
Test status
Simulation time 4648118171 ps
CPU time 52.45 seconds
Started Jun 10 07:41:06 PM PDT 24
Finished Jun 10 07:42:00 PM PDT 24
Peak memory 216764 kb
Host smart-1ccc0b1a-5f77-45cf-9426-fd9efee4aec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276430983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.276430983
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3626605759
Short name T220
Test name
Test status
Simulation time 5761701447 ps
CPU time 76.89 seconds
Started Jun 10 07:41:06 PM PDT 24
Finished Jun 10 07:42:25 PM PDT 24
Peak memory 219128 kb
Host smart-dc4c5e8d-0734-4929-a01f-b4c50a958a6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626605759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3626605759
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1419578917
Short name T324
Test name
Test status
Simulation time 6435182595 ps
CPU time 17.94 seconds
Started Jun 10 07:41:07 PM PDT 24
Finished Jun 10 07:41:28 PM PDT 24
Peak memory 217216 kb
Host smart-6fa51d79-c3e4-4e77-bada-d9466c38d612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419578917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1419578917
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.99053009
Short name T302
Test name
Test status
Simulation time 8132010556 ps
CPU time 235.18 seconds
Started Jun 10 07:41:04 PM PDT 24
Finished Jun 10 07:45:00 PM PDT 24
Peak memory 236116 kb
Host smart-2cd311a3-97c2-433a-a51b-8b255df64bae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99053009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_cor
rupt_sig_fatal_chk.99053009
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.556172628
Short name T46
Test name
Test status
Simulation time 1320867866 ps
CPU time 19.2 seconds
Started Jun 10 07:41:04 PM PDT 24
Finished Jun 10 07:41:24 PM PDT 24
Peak memory 218984 kb
Host smart-8daead28-0fec-43a6-9281-cff2db5a9c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556172628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.556172628
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1975813887
Short name T209
Test name
Test status
Simulation time 25273521789 ps
CPU time 24.77 seconds
Started Jun 10 07:41:06 PM PDT 24
Finished Jun 10 07:41:33 PM PDT 24
Peak memory 219120 kb
Host smart-89963530-7a66-4eae-81cf-70c3f0c42847
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1975813887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1975813887
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.177927072
Short name T28
Test name
Test status
Simulation time 690391787 ps
CPU time 21.08 seconds
Started Jun 10 07:41:05 PM PDT 24
Finished Jun 10 07:41:28 PM PDT 24
Peak memory 216108 kb
Host smart-25428c0e-6ea2-4ba1-b83b-aa6ba3aa37d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177927072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.177927072
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.4021343674
Short name T237
Test name
Test status
Simulation time 3029009620 ps
CPU time 41.56 seconds
Started Jun 10 07:41:04 PM PDT 24
Finished Jun 10 07:41:47 PM PDT 24
Peak memory 219072 kb
Host smart-20307a63-d2b1-4a31-b172-f47e6e63d0ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021343674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.4021343674
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1004176955
Short name T333
Test name
Test status
Simulation time 4001979908 ps
CPU time 31.43 seconds
Started Jun 10 07:41:04 PM PDT 24
Finished Jun 10 07:41:37 PM PDT 24
Peak memory 216836 kb
Host smart-daa34314-7ba0-4ce5-b9cc-58223d189f74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004176955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1004176955
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.863092988
Short name T356
Test name
Test status
Simulation time 184654837749 ps
CPU time 979.8 seconds
Started Jun 10 07:41:06 PM PDT 24
Finished Jun 10 07:57:28 PM PDT 24
Peak memory 238424 kb
Host smart-efec4070-4f8a-4438-bcca-9afd1aadc069
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863092988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.863092988
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2863336284
Short name T248
Test name
Test status
Simulation time 20565070682 ps
CPU time 49.38 seconds
Started Jun 10 07:41:06 PM PDT 24
Finished Jun 10 07:41:57 PM PDT 24
Peak memory 219136 kb
Host smart-90d8284e-f078-4335-8437-1f888007e521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863336284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2863336284
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2496425874
Short name T320
Test name
Test status
Simulation time 790901125 ps
CPU time 10.38 seconds
Started Jun 10 07:41:06 PM PDT 24
Finished Jun 10 07:41:19 PM PDT 24
Peak memory 219068 kb
Host smart-cc52bf0f-4885-44b9-a524-fdfc240d507b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2496425874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2496425874
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.4020748242
Short name T81
Test name
Test status
Simulation time 8051225854 ps
CPU time 58.74 seconds
Started Jun 10 07:41:07 PM PDT 24
Finished Jun 10 07:42:08 PM PDT 24
Peak memory 217576 kb
Host smart-1b62cc95-7a21-462b-9b42-389d2cb71fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020748242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.4020748242
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2051021314
Short name T317
Test name
Test status
Simulation time 7195089736 ps
CPU time 68.55 seconds
Started Jun 10 07:41:07 PM PDT 24
Finished Jun 10 07:42:18 PM PDT 24
Peak memory 218148 kb
Host smart-4e08558f-5e4d-46d1-99cb-ef7b56af8557
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051021314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2051021314
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.4247488023
Short name T25
Test name
Test status
Simulation time 51319513848 ps
CPU time 539.91 seconds
Started Jun 10 07:41:04 PM PDT 24
Finished Jun 10 07:50:05 PM PDT 24
Peak memory 230236 kb
Host smart-61a5cff7-a6f9-45ca-afc0-120f08f78618
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247488023 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.4247488023
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4277540292
Short name T181
Test name
Test status
Simulation time 12893943646 ps
CPU time 28.64 seconds
Started Jun 10 07:41:22 PM PDT 24
Finished Jun 10 07:41:53 PM PDT 24
Peak memory 217272 kb
Host smart-65a4a75f-68bd-4c56-9a51-1a2d59cdaba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277540292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4277540292
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.4264829829
Short name T326
Test name
Test status
Simulation time 72663669934 ps
CPU time 674.98 seconds
Started Jun 10 07:41:14 PM PDT 24
Finished Jun 10 07:52:32 PM PDT 24
Peak memory 218500 kb
Host smart-5b2d99df-aae4-4c61-a1e5-9cc36c3a9d83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264829829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.4264829829
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.375615169
Short name T47
Test name
Test status
Simulation time 806241818 ps
CPU time 18.98 seconds
Started Jun 10 07:41:15 PM PDT 24
Finished Jun 10 07:41:37 PM PDT 24
Peak memory 219076 kb
Host smart-fa7cd042-4615-4297-89fd-d430d5b04a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375615169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.375615169
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3575108429
Short name T239
Test name
Test status
Simulation time 682632607 ps
CPU time 14.73 seconds
Started Jun 10 07:41:13 PM PDT 24
Finished Jun 10 07:41:30 PM PDT 24
Peak memory 218144 kb
Host smart-e4cc8094-ac4b-45d3-b818-99fe68c8de2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3575108429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3575108429
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3630497756
Short name T268
Test name
Test status
Simulation time 47365631793 ps
CPU time 49.11 seconds
Started Jun 10 07:41:15 PM PDT 24
Finished Jun 10 07:42:07 PM PDT 24
Peak memory 216116 kb
Host smart-1c98240b-0557-4551-96d7-d66525b28d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630497756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3630497756
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1758168890
Short name T137
Test name
Test status
Simulation time 766922537 ps
CPU time 21.06 seconds
Started Jun 10 07:41:14 PM PDT 24
Finished Jun 10 07:41:38 PM PDT 24
Peak memory 215928 kb
Host smart-48e37a0f-dba3-485a-8071-fd30736fb0e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758168890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1758168890
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.368014424
Short name T319
Test name
Test status
Simulation time 7021695608 ps
CPU time 28.99 seconds
Started Jun 10 07:41:15 PM PDT 24
Finished Jun 10 07:41:47 PM PDT 24
Peak memory 217188 kb
Host smart-81475f62-e279-4dfe-8cb3-868e63f55fae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368014424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.368014424
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3316179621
Short name T164
Test name
Test status
Simulation time 17918797102 ps
CPU time 443.22 seconds
Started Jun 10 07:41:15 PM PDT 24
Finished Jun 10 07:48:41 PM PDT 24
Peak memory 236068 kb
Host smart-44865b90-faaa-43e5-b364-3179340b6aa7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316179621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3316179621
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1743754049
Short name T298
Test name
Test status
Simulation time 332160819 ps
CPU time 19.59 seconds
Started Jun 10 07:41:21 PM PDT 24
Finished Jun 10 07:41:43 PM PDT 24
Peak memory 218988 kb
Host smart-a2f29912-529d-4ed6-8108-d75737b3b454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743754049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1743754049
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.526110821
Short name T321
Test name
Test status
Simulation time 11708426249 ps
CPU time 27.12 seconds
Started Jun 10 07:41:20 PM PDT 24
Finished Jun 10 07:41:50 PM PDT 24
Peak memory 219164 kb
Host smart-44fa563b-39f1-4c30-b775-e61978cf5199
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=526110821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.526110821
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1497662658
Short name T295
Test name
Test status
Simulation time 681905993 ps
CPU time 26.71 seconds
Started Jun 10 07:41:27 PM PDT 24
Finished Jun 10 07:41:57 PM PDT 24
Peak memory 217196 kb
Host smart-294edd7d-cb82-4ae7-9cc6-c5ec2d2350fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497662658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1497662658
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3760368597
Short name T77
Test name
Test status
Simulation time 30536955401 ps
CPU time 99.99 seconds
Started Jun 10 07:41:13 PM PDT 24
Finished Jun 10 07:42:55 PM PDT 24
Peak memory 221360 kb
Host smart-c46ac9bd-5985-4425-a8fb-3ed4bac2903d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760368597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3760368597
Directory /workspace/9.rom_ctrl_stress_all/latest
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