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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.22 96.89 91.99 97.72 100.00 98.28 97.30 98.37


Total test records in report: 457
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T301 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3361954475 Jun 11 03:19:51 PM PDT 24 Jun 11 03:20:23 PM PDT 24 3555082839 ps
T302 /workspace/coverage/default/33.rom_ctrl_smoke.3570934137 Jun 11 03:19:42 PM PDT 24 Jun 11 03:20:03 PM PDT 24 1561729306 ps
T303 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.598950919 Jun 11 03:19:34 PM PDT 24 Jun 11 03:19:55 PM PDT 24 346069105 ps
T304 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.448913963 Jun 11 03:19:24 PM PDT 24 Jun 11 03:19:47 PM PDT 24 332492855 ps
T305 /workspace/coverage/default/32.rom_ctrl_smoke.4028147105 Jun 11 03:19:46 PM PDT 24 Jun 11 03:20:48 PM PDT 24 13976003043 ps
T306 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3315372587 Jun 11 03:19:40 PM PDT 24 Jun 11 03:25:03 PM PDT 24 19869867711 ps
T307 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3157458808 Jun 11 03:20:19 PM PDT 24 Jun 11 03:21:05 PM PDT 24 7884244468 ps
T308 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.892351387 Jun 11 03:19:53 PM PDT 24 Jun 11 03:20:31 PM PDT 24 32688469141 ps
T309 /workspace/coverage/default/17.rom_ctrl_stress_all.2891346499 Jun 11 03:19:33 PM PDT 24 Jun 11 03:19:58 PM PDT 24 1390247389 ps
T310 /workspace/coverage/default/14.rom_ctrl_alert_test.3997885283 Jun 11 03:19:24 PM PDT 24 Jun 11 03:19:51 PM PDT 24 38110542602 ps
T311 /workspace/coverage/default/31.rom_ctrl_smoke.2683757920 Jun 11 03:19:48 PM PDT 24 Jun 11 03:20:56 PM PDT 24 8329617615 ps
T312 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.412799974 Jun 11 03:20:19 PM PDT 24 Jun 11 03:35:22 PM PDT 24 94684271745 ps
T313 /workspace/coverage/default/22.rom_ctrl_alert_test.2849726210 Jun 11 03:19:35 PM PDT 24 Jun 11 03:19:46 PM PDT 24 169204164 ps
T314 /workspace/coverage/default/25.rom_ctrl_stress_all.3879959537 Jun 11 03:19:40 PM PDT 24 Jun 11 03:21:59 PM PDT 24 68593916561 ps
T315 /workspace/coverage/default/29.rom_ctrl_alert_test.2060832434 Jun 11 03:19:42 PM PDT 24 Jun 11 03:20:11 PM PDT 24 3170041844 ps
T316 /workspace/coverage/default/38.rom_ctrl_smoke.3085606980 Jun 11 03:19:59 PM PDT 24 Jun 11 03:21:08 PM PDT 24 32021565935 ps
T317 /workspace/coverage/default/31.rom_ctrl_stress_all.1606954213 Jun 11 03:19:45 PM PDT 24 Jun 11 03:22:24 PM PDT 24 34295006316 ps
T318 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2026180233 Jun 11 03:20:10 PM PDT 24 Jun 11 03:20:35 PM PDT 24 2637036267 ps
T319 /workspace/coverage/default/48.rom_ctrl_alert_test.1610910053 Jun 11 03:20:30 PM PDT 24 Jun 11 03:21:02 PM PDT 24 3629063754 ps
T320 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3783199331 Jun 11 03:19:23 PM PDT 24 Jun 11 03:24:29 PM PDT 24 118156279843 ps
T321 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2133360292 Jun 11 03:19:17 PM PDT 24 Jun 11 03:19:40 PM PDT 24 332309579 ps
T55 /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2000695296 Jun 11 03:20:29 PM PDT 24 Jun 11 04:04:41 PM PDT 24 272466447445 ps
T322 /workspace/coverage/default/15.rom_ctrl_stress_all.634150667 Jun 11 03:19:33 PM PDT 24 Jun 11 03:22:33 PM PDT 24 65782934024 ps
T323 /workspace/coverage/default/29.rom_ctrl_smoke.3965056659 Jun 11 03:19:43 PM PDT 24 Jun 11 03:20:36 PM PDT 24 11696881560 ps
T324 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.932131694 Jun 11 03:20:20 PM PDT 24 Jun 11 03:20:54 PM PDT 24 44213332785 ps
T325 /workspace/coverage/default/5.rom_ctrl_alert_test.3894919728 Jun 11 03:19:14 PM PDT 24 Jun 11 03:19:26 PM PDT 24 1948363720 ps
T56 /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3646224871 Jun 11 03:19:40 PM PDT 24 Jun 11 03:44:27 PM PDT 24 36830639437 ps
T326 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.764707860 Jun 11 03:19:51 PM PDT 24 Jun 11 03:20:19 PM PDT 24 6375048105 ps
T327 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2255848201 Jun 11 03:19:36 PM PDT 24 Jun 11 03:24:12 PM PDT 24 6553580047 ps
T328 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1954353498 Jun 11 03:19:14 PM PDT 24 Jun 11 03:19:50 PM PDT 24 8840525298 ps
T329 /workspace/coverage/default/23.rom_ctrl_alert_test.3992759169 Jun 11 03:19:37 PM PDT 24 Jun 11 03:20:00 PM PDT 24 4503778166 ps
T330 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.35311854 Jun 11 03:19:35 PM PDT 24 Jun 11 03:19:47 PM PDT 24 179371174 ps
T331 /workspace/coverage/default/42.rom_ctrl_smoke.1565727193 Jun 11 03:20:02 PM PDT 24 Jun 11 03:20:24 PM PDT 24 343359203 ps
T332 /workspace/coverage/default/14.rom_ctrl_smoke.346707352 Jun 11 03:19:23 PM PDT 24 Jun 11 03:20:24 PM PDT 24 24621580995 ps
T333 /workspace/coverage/default/21.rom_ctrl_stress_all.3838354773 Jun 11 03:19:35 PM PDT 24 Jun 11 03:20:01 PM PDT 24 8374578128 ps
T334 /workspace/coverage/default/26.rom_ctrl_smoke.2416376579 Jun 11 03:19:43 PM PDT 24 Jun 11 03:20:43 PM PDT 24 22200985766 ps
T335 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2015151022 Jun 11 03:19:43 PM PDT 24 Jun 11 03:20:11 PM PDT 24 1200113716 ps
T336 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2166873487 Jun 11 03:19:42 PM PDT 24 Jun 11 03:25:12 PM PDT 24 47826513913 ps
T337 /workspace/coverage/default/25.rom_ctrl_alert_test.2310569259 Jun 11 03:19:40 PM PDT 24 Jun 11 03:19:55 PM PDT 24 4400169519 ps
T338 /workspace/coverage/default/0.rom_ctrl_smoke.3988672734 Jun 11 03:19:16 PM PDT 24 Jun 11 03:20:24 PM PDT 24 15702021079 ps
T339 /workspace/coverage/default/37.rom_ctrl_alert_test.532824023 Jun 11 03:19:54 PM PDT 24 Jun 11 03:20:31 PM PDT 24 19296259011 ps
T340 /workspace/coverage/default/45.rom_ctrl_smoke.2830363361 Jun 11 03:20:09 PM PDT 24 Jun 11 03:20:58 PM PDT 24 4456851076 ps
T341 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1128845613 Jun 11 03:20:27 PM PDT 24 Jun 11 03:21:40 PM PDT 24 16077148565 ps
T342 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1536217649 Jun 11 03:19:35 PM PDT 24 Jun 11 03:20:06 PM PDT 24 3116250015 ps
T343 /workspace/coverage/default/27.rom_ctrl_stress_all.2737111532 Jun 11 03:19:42 PM PDT 24 Jun 11 03:20:14 PM PDT 24 8221391796 ps
T344 /workspace/coverage/default/46.rom_ctrl_stress_all.11634090 Jun 11 03:20:19 PM PDT 24 Jun 11 03:20:44 PM PDT 24 6057442628 ps
T345 /workspace/coverage/default/14.rom_ctrl_stress_all.3646408114 Jun 11 03:19:29 PM PDT 24 Jun 11 03:20:32 PM PDT 24 4472408412 ps
T346 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2609405781 Jun 11 03:19:51 PM PDT 24 Jun 11 03:28:19 PM PDT 24 199629717558 ps
T347 /workspace/coverage/default/39.rom_ctrl_stress_all.4243411843 Jun 11 03:19:53 PM PDT 24 Jun 11 03:21:00 PM PDT 24 16597478153 ps
T17 /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.4058971672 Jun 11 03:19:15 PM PDT 24 Jun 11 03:47:36 PM PDT 24 56450781250 ps
T348 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2906525265 Jun 11 03:20:08 PM PDT 24 Jun 11 03:20:38 PM PDT 24 13148951259 ps
T349 /workspace/coverage/default/2.rom_ctrl_alert_test.295921796 Jun 11 03:19:17 PM PDT 24 Jun 11 03:19:28 PM PDT 24 717810454 ps
T350 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.322926505 Jun 11 03:19:39 PM PDT 24 Jun 11 03:20:13 PM PDT 24 2054609420 ps
T351 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3190158110 Jun 11 03:19:36 PM PDT 24 Jun 11 03:27:59 PM PDT 24 46109661593 ps
T352 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.509299957 Jun 11 03:20:19 PM PDT 24 Jun 11 03:22:41 PM PDT 24 4146879379 ps
T353 /workspace/coverage/default/40.rom_ctrl_stress_all.634988808 Jun 11 03:19:56 PM PDT 24 Jun 11 03:20:30 PM PDT 24 1167756339 ps
T354 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1494103308 Jun 11 03:19:26 PM PDT 24 Jun 11 03:19:48 PM PDT 24 332452156 ps
T355 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.209108746 Jun 11 03:19:13 PM PDT 24 Jun 11 03:20:27 PM PDT 24 35529630635 ps
T356 /workspace/coverage/default/1.rom_ctrl_alert_test.2335030850 Jun 11 03:19:17 PM PDT 24 Jun 11 03:19:32 PM PDT 24 2159018515 ps
T357 /workspace/coverage/default/42.rom_ctrl_stress_all.2943241882 Jun 11 03:19:59 PM PDT 24 Jun 11 03:20:54 PM PDT 24 2449617902 ps
T358 /workspace/coverage/default/19.rom_ctrl_stress_all.1215226945 Jun 11 03:19:35 PM PDT 24 Jun 11 03:21:43 PM PDT 24 14439160289 ps
T359 /workspace/coverage/default/1.rom_ctrl_stress_all.2111052299 Jun 11 03:19:17 PM PDT 24 Jun 11 03:20:46 PM PDT 24 10528521341 ps
T57 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3142581154 Jun 11 02:24:07 PM PDT 24 Jun 11 02:24:28 PM PDT 24 1051633578 ps
T67 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2212010220 Jun 11 02:24:22 PM PDT 24 Jun 11 02:24:52 PM PDT 24 3345185292 ps
T68 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2825993068 Jun 11 02:23:50 PM PDT 24 Jun 11 02:24:10 PM PDT 24 6594368311 ps
T69 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1563875679 Jun 11 02:24:24 PM PDT 24 Jun 11 02:26:48 PM PDT 24 59465206746 ps
T61 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3409022219 Jun 11 02:23:35 PM PDT 24 Jun 11 02:25:07 PM PDT 24 1634004354 ps
T109 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.716623028 Jun 11 02:23:48 PM PDT 24 Jun 11 02:24:14 PM PDT 24 2892544379 ps
T360 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.187666101 Jun 11 02:23:42 PM PDT 24 Jun 11 02:24:05 PM PDT 24 8484860560 ps
T75 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.837770171 Jun 11 02:24:11 PM PDT 24 Jun 11 02:24:40 PM PDT 24 13154905908 ps
T105 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1514249089 Jun 11 02:24:21 PM PDT 24 Jun 11 02:24:40 PM PDT 24 1687816309 ps
T76 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2823634678 Jun 11 02:24:09 PM PDT 24 Jun 11 02:24:35 PM PDT 24 5977584329 ps
T361 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2203584914 Jun 11 02:23:32 PM PDT 24 Jun 11 02:24:04 PM PDT 24 8066620097 ps
T106 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2303248625 Jun 11 02:24:25 PM PDT 24 Jun 11 02:24:45 PM PDT 24 3261969085 ps
T62 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3835279296 Jun 11 02:24:23 PM PDT 24 Jun 11 02:27:17 PM PDT 24 3662244312 ps
T77 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1664321556 Jun 11 02:23:34 PM PDT 24 Jun 11 02:23:43 PM PDT 24 172546257 ps
T362 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1715103788 Jun 11 02:23:45 PM PDT 24 Jun 11 02:23:55 PM PDT 24 743616413 ps
T110 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.842986217 Jun 11 02:24:10 PM PDT 24 Jun 11 02:24:19 PM PDT 24 174292856 ps
T63 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3955364246 Jun 11 02:24:20 PM PDT 24 Jun 11 02:27:04 PM PDT 24 1443003391 ps
T363 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2698101573 Jun 11 02:24:22 PM PDT 24 Jun 11 02:24:55 PM PDT 24 3252932726 ps
T111 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.161549833 Jun 11 02:23:55 PM PDT 24 Jun 11 02:26:45 PM PDT 24 2611429657 ps
T78 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1411739117 Jun 11 02:24:09 PM PDT 24 Jun 11 02:25:01 PM PDT 24 6688617546 ps
T79 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1633946413 Jun 11 02:24:09 PM PDT 24 Jun 11 02:24:38 PM PDT 24 31098954621 ps
T80 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.273005027 Jun 11 02:23:42 PM PDT 24 Jun 11 02:24:00 PM PDT 24 4124301408 ps
T81 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3049327351 Jun 11 02:23:33 PM PDT 24 Jun 11 02:23:43 PM PDT 24 338915922 ps
T364 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.108906086 Jun 11 02:24:10 PM PDT 24 Jun 11 02:25:41 PM PDT 24 2269736246 ps
T82 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.713611627 Jun 11 02:24:10 PM PDT 24 Jun 11 02:24:40 PM PDT 24 3752605362 ps
T365 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3322174776 Jun 11 02:23:33 PM PDT 24 Jun 11 02:24:03 PM PDT 24 3733923324 ps
T366 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3687221439 Jun 11 02:24:20 PM PDT 24 Jun 11 02:24:56 PM PDT 24 10851788061 ps
T107 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3932223588 Jun 11 02:24:09 PM PDT 24 Jun 11 02:24:36 PM PDT 24 3187377770 ps
T90 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2909966830 Jun 11 02:23:44 PM PDT 24 Jun 11 02:25:14 PM PDT 24 10140040178 ps
T367 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3086054835 Jun 11 02:23:56 PM PDT 24 Jun 11 02:24:33 PM PDT 24 18638895004 ps
T91 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.158686486 Jun 11 02:24:23 PM PDT 24 Jun 11 02:24:53 PM PDT 24 4308742951 ps
T368 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.17861842 Jun 11 02:24:20 PM PDT 24 Jun 11 02:24:33 PM PDT 24 345448972 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1617191612 Jun 11 02:23:34 PM PDT 24 Jun 11 02:24:07 PM PDT 24 16039220693 ps
T370 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2770778932 Jun 11 02:23:49 PM PDT 24 Jun 11 02:26:11 PM PDT 24 57625554949 ps
T119 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3302469981 Jun 11 02:24:23 PM PDT 24 Jun 11 02:27:04 PM PDT 24 738541426 ps
T371 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.695933285 Jun 11 02:23:44 PM PDT 24 Jun 11 02:24:07 PM PDT 24 2557493819 ps
T117 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1127888050 Jun 11 02:23:35 PM PDT 24 Jun 11 02:26:28 PM PDT 24 3194885439 ps
T92 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1437189753 Jun 11 02:23:32 PM PDT 24 Jun 11 02:23:50 PM PDT 24 4795614597 ps
T108 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3790490086 Jun 11 02:24:11 PM PDT 24 Jun 11 02:24:20 PM PDT 24 689204025 ps
T372 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3267045485 Jun 11 02:24:21 PM PDT 24 Jun 11 02:24:49 PM PDT 24 5902336935 ps
T93 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1582551675 Jun 11 02:24:21 PM PDT 24 Jun 11 02:27:08 PM PDT 24 38368464407 ps
T94 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.126186849 Jun 11 02:23:54 PM PDT 24 Jun 11 02:24:03 PM PDT 24 167697407 ps
T373 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2996759708 Jun 11 02:23:51 PM PDT 24 Jun 11 02:24:11 PM PDT 24 1508822124 ps
T374 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1623987115 Jun 11 02:24:09 PM PDT 24 Jun 11 02:25:06 PM PDT 24 11062252479 ps
T375 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1613903465 Jun 11 02:24:22 PM PDT 24 Jun 11 02:24:38 PM PDT 24 336005944 ps
T376 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3866686958 Jun 11 02:24:07 PM PDT 24 Jun 11 02:24:33 PM PDT 24 11241966392 ps
T377 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3047088202 Jun 11 02:23:53 PM PDT 24 Jun 11 02:24:17 PM PDT 24 3543149754 ps
T378 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4247180945 Jun 11 02:23:56 PM PDT 24 Jun 11 02:24:26 PM PDT 24 21965913312 ps
T379 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1912046195 Jun 11 02:23:55 PM PDT 24 Jun 11 02:24:34 PM PDT 24 4287480239 ps
T380 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.924676949 Jun 11 02:24:21 PM PDT 24 Jun 11 02:24:53 PM PDT 24 4116286388 ps
T381 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2736433763 Jun 11 02:23:41 PM PDT 24 Jun 11 02:24:10 PM PDT 24 9097078015 ps
T382 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.526171917 Jun 11 02:23:56 PM PDT 24 Jun 11 02:24:06 PM PDT 24 331626919 ps
T383 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4270475964 Jun 11 02:23:35 PM PDT 24 Jun 11 02:23:49 PM PDT 24 688961105 ps
T95 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.33687914 Jun 11 02:24:20 PM PDT 24 Jun 11 02:26:44 PM PDT 24 34069231896 ps
T384 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3252574836 Jun 11 02:24:11 PM PDT 24 Jun 11 02:24:29 PM PDT 24 2729268415 ps
T385 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.922710619 Jun 11 02:23:54 PM PDT 24 Jun 11 02:24:15 PM PDT 24 1990374762 ps
T386 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1212709451 Jun 11 02:24:19 PM PDT 24 Jun 11 02:24:40 PM PDT 24 1904571137 ps
T115 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2409650070 Jun 11 02:23:50 PM PDT 24 Jun 11 02:26:43 PM PDT 24 7940756329 ps
T387 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4151740437 Jun 11 02:23:52 PM PDT 24 Jun 11 02:24:27 PM PDT 24 8496123804 ps
T101 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.954476030 Jun 11 02:23:55 PM PDT 24 Jun 11 02:24:09 PM PDT 24 2852055568 ps
T388 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1795562877 Jun 11 02:23:33 PM PDT 24 Jun 11 02:24:04 PM PDT 24 3267796590 ps
T389 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3363488377 Jun 11 02:23:33 PM PDT 24 Jun 11 02:23:46 PM PDT 24 503104983 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1583882054 Jun 11 02:23:51 PM PDT 24 Jun 11 02:24:11 PM PDT 24 1776716808 ps
T102 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1129927056 Jun 11 02:24:22 PM PDT 24 Jun 11 02:26:17 PM PDT 24 55927306331 ps
T391 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.828266092 Jun 11 02:24:22 PM PDT 24 Jun 11 02:24:54 PM PDT 24 12260687179 ps
T392 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3425140274 Jun 11 02:23:33 PM PDT 24 Jun 11 02:23:53 PM PDT 24 6062987113 ps
T393 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.505691381 Jun 11 02:24:09 PM PDT 24 Jun 11 02:24:43 PM PDT 24 3522138736 ps
T97 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3940596760 Jun 11 02:24:08 PM PDT 24 Jun 11 02:26:38 PM PDT 24 15414506768 ps
T98 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1719961525 Jun 11 02:23:42 PM PDT 24 Jun 11 02:23:55 PM PDT 24 2501042122 ps
T99 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.819419988 Jun 11 02:23:31 PM PDT 24 Jun 11 02:26:48 PM PDT 24 23599433511 ps
T394 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1895750457 Jun 11 02:24:11 PM PDT 24 Jun 11 02:26:50 PM PDT 24 995501772 ps
T395 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1485044522 Jun 11 02:24:23 PM PDT 24 Jun 11 02:24:54 PM PDT 24 14865622828 ps
T112 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.966478798 Jun 11 02:24:25 PM PDT 24 Jun 11 02:25:53 PM PDT 24 13072016199 ps
T396 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.346615270 Jun 11 02:24:08 PM PDT 24 Jun 11 02:24:27 PM PDT 24 1967777430 ps
T397 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2937960340 Jun 11 02:23:50 PM PDT 24 Jun 11 02:24:10 PM PDT 24 16501923349 ps
T398 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.891760155 Jun 11 02:24:07 PM PDT 24 Jun 11 02:24:40 PM PDT 24 3649444773 ps
T399 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3746750421 Jun 11 02:23:56 PM PDT 24 Jun 11 02:24:14 PM PDT 24 21894945964 ps
T400 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3615556233 Jun 11 02:23:35 PM PDT 24 Jun 11 02:23:57 PM PDT 24 6501762845 ps
T401 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.829773226 Jun 11 02:24:21 PM PDT 24 Jun 11 02:24:45 PM PDT 24 9020290928 ps
T402 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.871230079 Jun 11 02:23:56 PM PDT 24 Jun 11 02:24:22 PM PDT 24 24618209228 ps
T118 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4288285777 Jun 11 02:23:55 PM PDT 24 Jun 11 02:26:42 PM PDT 24 1858289938 ps
T116 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1393955341 Jun 11 02:23:44 PM PDT 24 Jun 11 02:26:39 PM PDT 24 7796108806 ps
T403 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3262509772 Jun 11 02:24:10 PM PDT 24 Jun 11 02:24:31 PM PDT 24 2054833683 ps
T404 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1112667816 Jun 11 02:24:25 PM PDT 24 Jun 11 02:24:49 PM PDT 24 10758423734 ps
T103 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2379255414 Jun 11 02:24:23 PM PDT 24 Jun 11 02:25:53 PM PDT 24 4722930034 ps
T405 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2003113381 Jun 11 02:23:54 PM PDT 24 Jun 11 02:24:16 PM PDT 24 2126407852 ps
T406 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3708514282 Jun 11 02:24:09 PM PDT 24 Jun 11 02:24:44 PM PDT 24 3875875426 ps
T407 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3691327942 Jun 11 02:23:43 PM PDT 24 Jun 11 02:24:17 PM PDT 24 8818601355 ps
T408 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3364298221 Jun 11 02:24:21 PM PDT 24 Jun 11 02:24:30 PM PDT 24 1828707137 ps
T409 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2922771084 Jun 11 02:24:23 PM PDT 24 Jun 11 02:24:54 PM PDT 24 18678348774 ps
T410 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1554969910 Jun 11 02:24:23 PM PDT 24 Jun 11 02:24:58 PM PDT 24 12566449207 ps
T411 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3819281393 Jun 11 02:24:11 PM PDT 24 Jun 11 02:25:53 PM PDT 24 17625480637 ps
T412 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3557437063 Jun 11 02:24:23 PM PDT 24 Jun 11 02:24:37 PM PDT 24 636259959 ps
T413 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.25646995 Jun 11 02:24:10 PM PDT 24 Jun 11 02:26:16 PM PDT 24 41451833233 ps
T414 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.169320901 Jun 11 02:24:09 PM PDT 24 Jun 11 02:24:47 PM PDT 24 17351938786 ps
T415 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1286196943 Jun 11 02:24:24 PM PDT 24 Jun 11 02:26:12 PM PDT 24 11890247417 ps
T416 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3859698192 Jun 11 02:24:11 PM PDT 24 Jun 11 02:24:36 PM PDT 24 7690677770 ps
T417 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1565865572 Jun 11 02:23:49 PM PDT 24 Jun 11 02:23:58 PM PDT 24 688374897 ps
T418 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1772931723 Jun 11 02:24:11 PM PDT 24 Jun 11 02:24:31 PM PDT 24 2151409895 ps
T419 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1596155591 Jun 11 02:24:21 PM PDT 24 Jun 11 02:24:42 PM PDT 24 4163580500 ps
T420 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2588371527 Jun 11 02:24:23 PM PDT 24 Jun 11 02:24:48 PM PDT 24 10000069989 ps
T421 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1412068088 Jun 11 02:24:09 PM PDT 24 Jun 11 02:24:29 PM PDT 24 1873416796 ps
T422 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.4114224276 Jun 11 02:23:52 PM PDT 24 Jun 11 02:25:38 PM PDT 24 11310742481 ps
T423 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1088590721 Jun 11 02:23:52 PM PDT 24 Jun 11 02:24:06 PM PDT 24 2087248190 ps
T424 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.580369057 Jun 11 02:24:23 PM PDT 24 Jun 11 02:24:36 PM PDT 24 1451267336 ps
T425 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3711380330 Jun 11 02:24:08 PM PDT 24 Jun 11 02:24:41 PM PDT 24 18206364220 ps
T426 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4197279234 Jun 11 02:24:07 PM PDT 24 Jun 11 02:24:41 PM PDT 24 17510020768 ps
T113 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4009664053 Jun 11 02:24:08 PM PDT 24 Jun 11 02:26:58 PM PDT 24 13468048515 ps
T427 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.369091515 Jun 11 02:23:53 PM PDT 24 Jun 11 02:24:05 PM PDT 24 661087428 ps
T428 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3343928085 Jun 11 02:23:50 PM PDT 24 Jun 11 02:24:22 PM PDT 24 4214861406 ps
T429 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2065922696 Jun 11 02:23:45 PM PDT 24 Jun 11 02:24:12 PM PDT 24 4719998109 ps
T430 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.950491392 Jun 11 02:24:20 PM PDT 24 Jun 11 02:24:48 PM PDT 24 26152831305 ps
T120 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1194567503 Jun 11 02:24:08 PM PDT 24 Jun 11 02:25:34 PM PDT 24 2955050766 ps
T431 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.211361541 Jun 11 02:23:53 PM PDT 24 Jun 11 02:24:05 PM PDT 24 426142811 ps
T432 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.544913952 Jun 11 02:23:43 PM PDT 24 Jun 11 02:23:55 PM PDT 24 688666725 ps
T433 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2065530261 Jun 11 02:24:22 PM PDT 24 Jun 11 02:27:16 PM PDT 24 20629312714 ps
T434 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.857122901 Jun 11 02:24:07 PM PDT 24 Jun 11 02:24:36 PM PDT 24 12434677589 ps
T435 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3149292315 Jun 11 02:24:11 PM PDT 24 Jun 11 02:24:23 PM PDT 24 341215247 ps
T436 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.352866893 Jun 11 02:23:56 PM PDT 24 Jun 11 02:24:14 PM PDT 24 1336822319 ps
T437 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2675219872 Jun 11 02:24:24 PM PDT 24 Jun 11 02:24:59 PM PDT 24 4869467201 ps
T438 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3981813305 Jun 11 02:24:21 PM PDT 24 Jun 11 02:26:23 PM PDT 24 20171051511 ps
T114 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1971313322 Jun 11 02:24:24 PM PDT 24 Jun 11 02:27:03 PM PDT 24 5174653632 ps
T439 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2397043407 Jun 11 02:24:25 PM PDT 24 Jun 11 02:24:52 PM PDT 24 2950327944 ps
T440 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3557062141 Jun 11 02:23:51 PM PDT 24 Jun 11 02:24:21 PM PDT 24 14300175395 ps
T441 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.727258288 Jun 11 02:23:52 PM PDT 24 Jun 11 02:24:01 PM PDT 24 689688648 ps
T104 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4279666292 Jun 11 02:24:08 PM PDT 24 Jun 11 02:25:36 PM PDT 24 29784553496 ps
T442 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2992818363 Jun 11 02:23:32 PM PDT 24 Jun 11 02:23:41 PM PDT 24 331625896 ps
T443 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1220077582 Jun 11 02:24:18 PM PDT 24 Jun 11 02:24:42 PM PDT 24 2641605483 ps
T444 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2378677486 Jun 11 02:23:51 PM PDT 24 Jun 11 02:24:00 PM PDT 24 171085662 ps
T445 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2576800975 Jun 11 02:24:21 PM PDT 24 Jun 11 02:24:36 PM PDT 24 1617009043 ps
T446 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.442800760 Jun 11 02:24:09 PM PDT 24 Jun 11 02:24:39 PM PDT 24 3129895303 ps
T100 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3582542856 Jun 11 02:23:37 PM PDT 24 Jun 11 02:25:14 PM PDT 24 12109814260 ps
T447 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2413824465 Jun 11 02:24:09 PM PDT 24 Jun 11 02:25:31 PM PDT 24 234217528 ps
T448 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.758524086 Jun 11 02:24:24 PM PDT 24 Jun 11 02:25:04 PM PDT 24 724786288 ps
T449 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1085430076 Jun 11 02:23:41 PM PDT 24 Jun 11 02:24:12 PM PDT 24 3595427428 ps
T450 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2035515944 Jun 11 02:23:51 PM PDT 24 Jun 11 02:24:15 PM PDT 24 10850452509 ps
T451 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.779505628 Jun 11 02:23:55 PM PDT 24 Jun 11 02:24:04 PM PDT 24 660644956 ps
T452 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.547499853 Jun 11 02:23:52 PM PDT 24 Jun 11 02:24:11 PM PDT 24 2948263675 ps
T121 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2999581058 Jun 11 02:23:56 PM PDT 24 Jun 11 02:26:40 PM PDT 24 9081292010 ps
T453 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1342426861 Jun 11 02:23:55 PM PDT 24 Jun 11 02:24:31 PM PDT 24 3924888670 ps
T454 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2445243028 Jun 11 02:24:20 PM PDT 24 Jun 11 02:24:39 PM PDT 24 6175191074 ps
T455 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3672880739 Jun 11 02:23:56 PM PDT 24 Jun 11 02:26:29 PM PDT 24 65210848562 ps
T456 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.815549351 Jun 11 02:24:08 PM PDT 24 Jun 11 02:24:26 PM PDT 24 11611031476 ps
T96 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2203687526 Jun 11 02:23:56 PM PDT 24 Jun 11 02:24:28 PM PDT 24 3327346135 ps
T457 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.4043443909 Jun 11 02:24:09 PM PDT 24 Jun 11 02:26:43 PM PDT 24 67631981749 ps

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3479281688
Short name T8
Test name
Test status
Simulation time 234147028833 ps
CPU time 635.32 seconds
Started Jun 11 03:19:20 PM PDT 24
Finished Jun 11 03:30:00 PM PDT 24
Peak memory 233412 kb
Host smart-912137f0-79fc-4da6-aba0-56a73bce1a4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479281688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3479281688
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.711839673
Short name T11
Test name
Test status
Simulation time 113748989600 ps
CPU time 1113.72 seconds
Started Jun 11 03:19:52 PM PDT 24
Finished Jun 11 03:38:28 PM PDT 24
Peak memory 233636 kb
Host smart-658ebc48-3d68-439f-bbe8-7b54fe9d37db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711839673 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.711839673
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3409022219
Short name T61
Test name
Test status
Simulation time 1634004354 ps
CPU time 91.6 seconds
Started Jun 11 02:23:35 PM PDT 24
Finished Jun 11 02:25:07 PM PDT 24
Peak memory 212524 kb
Host smart-2eac49a0-b20d-4587-9b24-fb16e85acce7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409022219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3409022219
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1275552291
Short name T50
Test name
Test status
Simulation time 15695999200 ps
CPU time 48.34 seconds
Started Jun 11 03:19:24 PM PDT 24
Finished Jun 11 03:20:16 PM PDT 24
Peak memory 216792 kb
Host smart-8453d446-1f07-438b-9f0c-201a459ad8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275552291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1275552291
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3032800637
Short name T184
Test name
Test status
Simulation time 182122298496 ps
CPU time 517.32 seconds
Started Jun 11 03:19:36 PM PDT 24
Finished Jun 11 03:28:15 PM PDT 24
Peak memory 239488 kb
Host smart-33635f1f-0681-4e4d-838e-4d341c6ae589
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032800637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3032800637
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.375392932
Short name T21
Test name
Test status
Simulation time 2523343162 ps
CPU time 130.83 seconds
Started Jun 11 03:19:14 PM PDT 24
Finished Jun 11 03:21:26 PM PDT 24
Peak memory 237164 kb
Host smart-be4695f3-5240-4f8c-b72e-9d663bc7ec2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375392932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.375392932
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3835279296
Short name T62
Test name
Test status
Simulation time 3662244312 ps
CPU time 172.11 seconds
Started Jun 11 02:24:23 PM PDT 24
Finished Jun 11 02:27:17 PM PDT 24
Peak memory 214172 kb
Host smart-159f9a93-8a72-484e-9391-a674b7f69151
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835279296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3835279296
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1563875679
Short name T69
Test name
Test status
Simulation time 59465206746 ps
CPU time 142.9 seconds
Started Jun 11 02:24:24 PM PDT 24
Finished Jun 11 02:26:48 PM PDT 24
Peak memory 212408 kb
Host smart-4b3b7d6a-19cb-4a77-93b2-3713c398805e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563875679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1563875679
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1320718938
Short name T71
Test name
Test status
Simulation time 1348138525 ps
CPU time 17.39 seconds
Started Jun 11 03:19:24 PM PDT 24
Finished Jun 11 03:19:45 PM PDT 24
Peak memory 216860 kb
Host smart-7cd7aeb2-5ea2-4d12-9f54-1164aa43b200
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320718938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1320718938
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2880225636
Short name T131
Test name
Test status
Simulation time 5755446036 ps
CPU time 55.4 seconds
Started Jun 11 03:19:14 PM PDT 24
Finished Jun 11 03:20:11 PM PDT 24
Peak memory 219096 kb
Host smart-19ca4ac0-d1d1-418c-9a7f-c90446d02991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880225636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2880225636
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.598950919
Short name T303
Test name
Test status
Simulation time 346069105 ps
CPU time 19.12 seconds
Started Jun 11 03:19:34 PM PDT 24
Finished Jun 11 03:19:55 PM PDT 24
Peak memory 218984 kb
Host smart-ac0fed76-6fb6-4d64-b875-506b6144cc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598950919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.598950919
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1020632842
Short name T60
Test name
Test status
Simulation time 6898329972 ps
CPU time 30.3 seconds
Started Jun 11 03:19:13 PM PDT 24
Finished Jun 11 03:19:45 PM PDT 24
Peak memory 211488 kb
Host smart-4104a080-1291-4f28-b02f-d48cb97af294
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1020632842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1020632842
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1719961525
Short name T98
Test name
Test status
Simulation time 2501042122 ps
CPU time 12.11 seconds
Started Jun 11 02:23:42 PM PDT 24
Finished Jun 11 02:23:55 PM PDT 24
Peak memory 211108 kb
Host smart-d1d5e245-bc10-415c-a37c-99fc8062a3da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719961525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1719961525
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4009664053
Short name T113
Test name
Test status
Simulation time 13468048515 ps
CPU time 170.13 seconds
Started Jun 11 02:24:08 PM PDT 24
Finished Jun 11 02:26:58 PM PDT 24
Peak memory 219272 kb
Host smart-a4b90dde-4b1a-47a5-8a0d-f726502aa482
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009664053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.4009664053
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1194567503
Short name T120
Test name
Test status
Simulation time 2955050766 ps
CPU time 84.95 seconds
Started Jun 11 02:24:08 PM PDT 24
Finished Jun 11 02:25:34 PM PDT 24
Peak memory 212928 kb
Host smart-8c57a176-b1e8-4356-b2e8-855722ceebef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194567503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1194567503
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3049327351
Short name T81
Test name
Test status
Simulation time 338915922 ps
CPU time 8.45 seconds
Started Jun 11 02:23:33 PM PDT 24
Finished Jun 11 02:23:43 PM PDT 24
Peak memory 211372 kb
Host smart-69e34265-8734-4b30-ad7f-66c2ac2a0a08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049327351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3049327351
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1737149091
Short name T15
Test name
Test status
Simulation time 1371410154 ps
CPU time 19.79 seconds
Started Jun 11 03:19:15 PM PDT 24
Finished Jun 11 03:19:37 PM PDT 24
Peak memory 216108 kb
Host smart-41b267a6-79cb-4aa6-b27f-1d6cb580fc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737149091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1737149091
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.4058971672
Short name T17
Test name
Test status
Simulation time 56450781250 ps
CPU time 1699.03 seconds
Started Jun 11 03:19:15 PM PDT 24
Finished Jun 11 03:47:36 PM PDT 24
Peak memory 237020 kb
Host smart-fd79f645-3d18-409c-9f84-d5971e1066fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058971672 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.4058971672
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1664321556
Short name T77
Test name
Test status
Simulation time 172546257 ps
CPU time 8.15 seconds
Started Jun 11 02:23:34 PM PDT 24
Finished Jun 11 02:23:43 PM PDT 24
Peak memory 211024 kb
Host smart-9cf29c80-f7cc-41f4-a394-84ec91c2dcae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664321556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1664321556
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1617191612
Short name T369
Test name
Test status
Simulation time 16039220693 ps
CPU time 32.19 seconds
Started Jun 11 02:23:34 PM PDT 24
Finished Jun 11 02:24:07 PM PDT 24
Peak memory 211940 kb
Host smart-28fc64ae-b358-45e4-9b56-d829f624efa7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617191612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1617191612
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1795562877
Short name T388
Test name
Test status
Simulation time 3267796590 ps
CPU time 30.67 seconds
Started Jun 11 02:23:33 PM PDT 24
Finished Jun 11 02:24:04 PM PDT 24
Peak memory 211588 kb
Host smart-4576dcf5-ff64-490e-95cc-c7fcede5deee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795562877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1795562877
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3363488377
Short name T389
Test name
Test status
Simulation time 503104983 ps
CPU time 12.04 seconds
Started Jun 11 02:23:33 PM PDT 24
Finished Jun 11 02:23:46 PM PDT 24
Peak memory 219204 kb
Host smart-e03298dc-7410-4fb3-b557-1e80442906b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363488377 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3363488377
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1437189753
Short name T92
Test name
Test status
Simulation time 4795614597 ps
CPU time 16.38 seconds
Started Jun 11 02:23:32 PM PDT 24
Finished Jun 11 02:23:50 PM PDT 24
Peak memory 211468 kb
Host smart-c52b1567-8785-49c7-8742-47ca41944a0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437189753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1437189753
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2992818363
Short name T442
Test name
Test status
Simulation time 331625896 ps
CPU time 8.13 seconds
Started Jun 11 02:23:32 PM PDT 24
Finished Jun 11 02:23:41 PM PDT 24
Peak memory 210760 kb
Host smart-1911d81e-f888-4f66-948b-3b76f6b770d0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992818363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2992818363
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3425140274
Short name T392
Test name
Test status
Simulation time 6062987113 ps
CPU time 19.12 seconds
Started Jun 11 02:23:33 PM PDT 24
Finished Jun 11 02:23:53 PM PDT 24
Peak memory 211084 kb
Host smart-178bb14c-3bf3-4abf-8780-a16995aa9c3c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425140274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3425140274
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3582542856
Short name T100
Test name
Test status
Simulation time 12109814260 ps
CPU time 95.59 seconds
Started Jun 11 02:23:37 PM PDT 24
Finished Jun 11 02:25:14 PM PDT 24
Peak memory 217220 kb
Host smart-c992f802-c317-4405-842e-239f11b3d946
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582542856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3582542856
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.4270475964
Short name T383
Test name
Test status
Simulation time 688961105 ps
CPU time 13.07 seconds
Started Jun 11 02:23:35 PM PDT 24
Finished Jun 11 02:23:49 PM PDT 24
Peak memory 217512 kb
Host smart-221ed624-a0c8-4ac0-a50c-cdd05c98ace5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270475964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.4270475964
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3557062141
Short name T440
Test name
Test status
Simulation time 14300175395 ps
CPU time 29.26 seconds
Started Jun 11 02:23:51 PM PDT 24
Finished Jun 11 02:24:21 PM PDT 24
Peak memory 212600 kb
Host smart-16f2dbbc-093b-4845-8aa5-a2e0e9a1d05b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557062141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3557062141
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.716623028
Short name T109
Test name
Test status
Simulation time 2892544379 ps
CPU time 25.49 seconds
Started Jun 11 02:23:48 PM PDT 24
Finished Jun 11 02:24:14 PM PDT 24
Peak memory 211616 kb
Host smart-8ed363be-47c9-4237-9873-7a2f11ace6a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716623028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.716623028
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.273005027
Short name T80
Test name
Test status
Simulation time 4124301408 ps
CPU time 17.15 seconds
Started Jun 11 02:23:42 PM PDT 24
Finished Jun 11 02:24:00 PM PDT 24
Peak memory 211604 kb
Host smart-eadf7bba-37b8-4409-b422-aed5eed401fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273005027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.273005027
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2736433763
Short name T381
Test name
Test status
Simulation time 9097078015 ps
CPU time 27.76 seconds
Started Jun 11 02:23:41 PM PDT 24
Finished Jun 11 02:24:10 PM PDT 24
Peak memory 219340 kb
Host smart-769fd22f-1208-478f-a03e-c0b89a3acd8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736433763 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2736433763
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3322174776
Short name T365
Test name
Test status
Simulation time 3733923324 ps
CPU time 29.01 seconds
Started Jun 11 02:23:33 PM PDT 24
Finished Jun 11 02:24:03 PM PDT 24
Peak memory 210888 kb
Host smart-2c8faaad-78c6-40a7-a7ea-cedb861d272f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322174776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3322174776
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2203584914
Short name T361
Test name
Test status
Simulation time 8066620097 ps
CPU time 31.15 seconds
Started Jun 11 02:23:32 PM PDT 24
Finished Jun 11 02:24:04 PM PDT 24
Peak memory 211060 kb
Host smart-7c90f716-9b20-4e20-bbec-dcd298d7d226
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203584914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2203584914
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.819419988
Short name T99
Test name
Test status
Simulation time 23599433511 ps
CPU time 195.32 seconds
Started Jun 11 02:23:31 PM PDT 24
Finished Jun 11 02:26:48 PM PDT 24
Peak memory 215308 kb
Host smart-8f006965-2910-474e-aa54-7fa4fc6ca6f1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819419988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.819419988
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1565865572
Short name T417
Test name
Test status
Simulation time 688374897 ps
CPU time 8.56 seconds
Started Jun 11 02:23:49 PM PDT 24
Finished Jun 11 02:23:58 PM PDT 24
Peak memory 211240 kb
Host smart-b5822336-c763-4af8-ae58-7049b638ba15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565865572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1565865572
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3615556233
Short name T400
Test name
Test status
Simulation time 6501762845 ps
CPU time 21.86 seconds
Started Jun 11 02:23:35 PM PDT 24
Finished Jun 11 02:23:57 PM PDT 24
Peak memory 218920 kb
Host smart-96811e40-1b4d-4ceb-88a2-c4d7562490a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615556233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3615556233
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1127888050
Short name T117
Test name
Test status
Simulation time 3194885439 ps
CPU time 172.4 seconds
Started Jun 11 02:23:35 PM PDT 24
Finished Jun 11 02:26:28 PM PDT 24
Peak memory 219208 kb
Host smart-04f57873-10f9-4e8b-8c3f-8ec92313efaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127888050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1127888050
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.857122901
Short name T434
Test name
Test status
Simulation time 12434677589 ps
CPU time 28.19 seconds
Started Jun 11 02:24:07 PM PDT 24
Finished Jun 11 02:24:36 PM PDT 24
Peak memory 217192 kb
Host smart-3609044f-295d-4cef-80fb-b5da56dfba6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857122901 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.857122901
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.842986217
Short name T110
Test name
Test status
Simulation time 174292856 ps
CPU time 8.22 seconds
Started Jun 11 02:24:10 PM PDT 24
Finished Jun 11 02:24:19 PM PDT 24
Peak memory 211280 kb
Host smart-e334a36d-67e8-4307-8b74-72cd12142e5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842986217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.842986217
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.4279666292
Short name T104
Test name
Test status
Simulation time 29784553496 ps
CPU time 87.22 seconds
Started Jun 11 02:24:08 PM PDT 24
Finished Jun 11 02:25:36 PM PDT 24
Peak memory 212076 kb
Host smart-657a31e7-1aa1-480b-9065-28f7c8c6b2db
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279666292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.4279666292
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.169320901
Short name T414
Test name
Test status
Simulation time 17351938786 ps
CPU time 37.69 seconds
Started Jun 11 02:24:09 PM PDT 24
Finished Jun 11 02:24:47 PM PDT 24
Peak memory 212892 kb
Host smart-f5a0e9bf-134f-444e-b717-ac6f39c82ed9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169320901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.169320901
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.346615270
Short name T396
Test name
Test status
Simulation time 1967777430 ps
CPU time 17.25 seconds
Started Jun 11 02:24:08 PM PDT 24
Finished Jun 11 02:24:27 PM PDT 24
Peak memory 217412 kb
Host smart-27317d1c-a85c-43f2-8cb3-11b845db4c8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346615270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.346615270
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3711380330
Short name T425
Test name
Test status
Simulation time 18206364220 ps
CPU time 33.06 seconds
Started Jun 11 02:24:08 PM PDT 24
Finished Jun 11 02:24:41 PM PDT 24
Peak memory 214940 kb
Host smart-9948fb1b-8db2-483f-ac42-5434f8b3224b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711380330 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3711380330
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3262509772
Short name T403
Test name
Test status
Simulation time 2054833683 ps
CPU time 19.7 seconds
Started Jun 11 02:24:10 PM PDT 24
Finished Jun 11 02:24:31 PM PDT 24
Peak memory 212088 kb
Host smart-0056a5f8-9349-470f-88b6-b24e4c62ab93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262509772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3262509772
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.25646995
Short name T413
Test name
Test status
Simulation time 41451833233 ps
CPU time 125.6 seconds
Started Jun 11 02:24:10 PM PDT 24
Finished Jun 11 02:26:16 PM PDT 24
Peak memory 215416 kb
Host smart-2dda16ff-6d29-4008-bd27-b2a7957a6d60
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25646995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pas
sthru_mem_tl_intg_err.25646995
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3790490086
Short name T108
Test name
Test status
Simulation time 689204025 ps
CPU time 8.49 seconds
Started Jun 11 02:24:11 PM PDT 24
Finished Jun 11 02:24:20 PM PDT 24
Peak memory 211600 kb
Host smart-0650ecfc-23ee-4ac6-a40e-9e16d753c4a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790490086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3790490086
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3708514282
Short name T406
Test name
Test status
Simulation time 3875875426 ps
CPU time 34.7 seconds
Started Jun 11 02:24:09 PM PDT 24
Finished Jun 11 02:24:44 PM PDT 24
Peak memory 219140 kb
Host smart-54c652e6-52bc-455e-9989-df204a70e414
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708514282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3708514282
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.108906086
Short name T364
Test name
Test status
Simulation time 2269736246 ps
CPU time 89.99 seconds
Started Jun 11 02:24:10 PM PDT 24
Finished Jun 11 02:25:41 PM PDT 24
Peak memory 213992 kb
Host smart-0ed58711-e0ce-4199-baa6-61c1f89c7392
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108906086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.108906086
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1412068088
Short name T421
Test name
Test status
Simulation time 1873416796 ps
CPU time 18.97 seconds
Started Jun 11 02:24:09 PM PDT 24
Finished Jun 11 02:24:29 PM PDT 24
Peak memory 216872 kb
Host smart-389c63e3-c4c8-4cd7-875d-bcb6f9a0a7c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412068088 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1412068088
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.713611627
Short name T82
Test name
Test status
Simulation time 3752605362 ps
CPU time 29.06 seconds
Started Jun 11 02:24:10 PM PDT 24
Finished Jun 11 02:24:40 PM PDT 24
Peak memory 211884 kb
Host smart-14a28dfa-c64a-4ef9-9714-3cf1ce0bd620
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713611627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.713611627
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1411739117
Short name T78
Test name
Test status
Simulation time 6688617546 ps
CPU time 51.38 seconds
Started Jun 11 02:24:09 PM PDT 24
Finished Jun 11 02:25:01 PM PDT 24
Peak memory 215124 kb
Host smart-766550de-47be-45fb-b59c-ba8a4ebc3cf3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411739117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1411739117
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4197279234
Short name T426
Test name
Test status
Simulation time 17510020768 ps
CPU time 32.88 seconds
Started Jun 11 02:24:07 PM PDT 24
Finished Jun 11 02:24:41 PM PDT 24
Peak memory 213008 kb
Host smart-2fc6efd9-360a-4c98-a2ff-94984777977d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197279234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.4197279234
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.891760155
Short name T398
Test name
Test status
Simulation time 3649444773 ps
CPU time 32.42 seconds
Started Jun 11 02:24:07 PM PDT 24
Finished Jun 11 02:24:40 PM PDT 24
Peak memory 217148 kb
Host smart-74d4993b-84d9-4931-a8bc-2daac51f969a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891760155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.891760155
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.580369057
Short name T424
Test name
Test status
Simulation time 1451267336 ps
CPU time 12.17 seconds
Started Jun 11 02:24:23 PM PDT 24
Finished Jun 11 02:24:36 PM PDT 24
Peak memory 217300 kb
Host smart-05cc2e15-db23-44e5-aa43-dbf639f104ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580369057 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.580369057
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1554969910
Short name T410
Test name
Test status
Simulation time 12566449207 ps
CPU time 33.65 seconds
Started Jun 11 02:24:23 PM PDT 24
Finished Jun 11 02:24:58 PM PDT 24
Peak memory 212448 kb
Host smart-e8084734-a7c8-4255-bf88-7f9083b7f0de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554969910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1554969910
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1514249089
Short name T105
Test name
Test status
Simulation time 1687816309 ps
CPU time 17.58 seconds
Started Jun 11 02:24:21 PM PDT 24
Finished Jun 11 02:24:40 PM PDT 24
Peak memory 211240 kb
Host smart-87f87d24-f584-407d-9b25-02085c9da009
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514249089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1514249089
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3687221439
Short name T366
Test name
Test status
Simulation time 10851788061 ps
CPU time 35.47 seconds
Started Jun 11 02:24:20 PM PDT 24
Finished Jun 11 02:24:56 PM PDT 24
Peak memory 217384 kb
Host smart-42176f0f-8eed-444c-b7aa-d03d1f01cc17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687221439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3687221439
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.2065530261
Short name T433
Test name
Test status
Simulation time 20629312714 ps
CPU time 172.77 seconds
Started Jun 11 02:24:22 PM PDT 24
Finished Jun 11 02:27:16 PM PDT 24
Peak memory 214548 kb
Host smart-1a0de812-0c7b-4a1f-b01a-7992379a0d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065530261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.2065530261
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2212010220
Short name T67
Test name
Test status
Simulation time 3345185292 ps
CPU time 29.19 seconds
Started Jun 11 02:24:22 PM PDT 24
Finished Jun 11 02:24:52 PM PDT 24
Peak memory 214996 kb
Host smart-f49c4e75-d62f-4fea-ac05-2227f11cc01d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212010220 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2212010220
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2397043407
Short name T439
Test name
Test status
Simulation time 2950327944 ps
CPU time 25.18 seconds
Started Jun 11 02:24:25 PM PDT 24
Finished Jun 11 02:24:52 PM PDT 24
Peak memory 211992 kb
Host smart-6d4333ee-2797-486f-a2d3-2b230bf5a9d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397043407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2397043407
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.33687914
Short name T95
Test name
Test status
Simulation time 34069231896 ps
CPU time 142.24 seconds
Started Jun 11 02:24:20 PM PDT 24
Finished Jun 11 02:26:44 PM PDT 24
Peak memory 212400 kb
Host smart-36adb735-8d14-4181-9319-b22cceb66fbf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33687914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pas
sthru_mem_tl_intg_err.33687914
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2445243028
Short name T454
Test name
Test status
Simulation time 6175191074 ps
CPU time 17.43 seconds
Started Jun 11 02:24:20 PM PDT 24
Finished Jun 11 02:24:39 PM PDT 24
Peak memory 212304 kb
Host smart-e497989d-366f-4800-a198-f952e03ac229
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445243028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2445243028
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.17861842
Short name T368
Test name
Test status
Simulation time 345448972 ps
CPU time 11.26 seconds
Started Jun 11 02:24:20 PM PDT 24
Finished Jun 11 02:24:33 PM PDT 24
Peak memory 217136 kb
Host smart-c8702ad1-90c2-48c2-ba4d-5669efe7e1b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17861842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.17861842
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2588371527
Short name T420
Test name
Test status
Simulation time 10000069989 ps
CPU time 23.82 seconds
Started Jun 11 02:24:23 PM PDT 24
Finished Jun 11 02:24:48 PM PDT 24
Peak memory 218724 kb
Host smart-f782d9d5-32a8-4737-9a44-2904a9875cab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588371527 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2588371527
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2675219872
Short name T437
Test name
Test status
Simulation time 4869467201 ps
CPU time 32.55 seconds
Started Jun 11 02:24:24 PM PDT 24
Finished Jun 11 02:24:59 PM PDT 24
Peak memory 212676 kb
Host smart-9a1e68a4-30c7-4229-8ee2-b132d2da78fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675219872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2675219872
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2379255414
Short name T103
Test name
Test status
Simulation time 4722930034 ps
CPU time 88.64 seconds
Started Jun 11 02:24:23 PM PDT 24
Finished Jun 11 02:25:53 PM PDT 24
Peak memory 219276 kb
Host smart-0032a2db-45a3-455f-a335-229b5eab75f0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379255414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2379255414
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1596155591
Short name T419
Test name
Test status
Simulation time 4163580500 ps
CPU time 20.55 seconds
Started Jun 11 02:24:21 PM PDT 24
Finished Jun 11 02:24:42 PM PDT 24
Peak memory 212560 kb
Host smart-ea794059-364c-4094-81c6-16dc34d5203a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596155591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1596155591
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2698101573
Short name T363
Test name
Test status
Simulation time 3252932726 ps
CPU time 31.26 seconds
Started Jun 11 02:24:22 PM PDT 24
Finished Jun 11 02:24:55 PM PDT 24
Peak memory 218660 kb
Host smart-069d14a2-a2cd-48f2-9fc6-f55faf4dae72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698101573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2698101573
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3955364246
Short name T63
Test name
Test status
Simulation time 1443003391 ps
CPU time 162.27 seconds
Started Jun 11 02:24:20 PM PDT 24
Finished Jun 11 02:27:04 PM PDT 24
Peak memory 214012 kb
Host smart-351f453f-2d31-4394-bfd9-1ffea2c7946e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955364246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3955364246
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.950491392
Short name T430
Test name
Test status
Simulation time 26152831305 ps
CPU time 26.64 seconds
Started Jun 11 02:24:20 PM PDT 24
Finished Jun 11 02:24:48 PM PDT 24
Peak memory 216736 kb
Host smart-2f2db774-e510-4831-b470-dc0bf56cf217
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950491392 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.950491392
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3267045485
Short name T372
Test name
Test status
Simulation time 5902336935 ps
CPU time 27.1 seconds
Started Jun 11 02:24:21 PM PDT 24
Finished Jun 11 02:24:49 PM PDT 24
Peak memory 212172 kb
Host smart-1c71c761-fd29-4bc1-a62a-38bbb6798d51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267045485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3267045485
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1582551675
Short name T93
Test name
Test status
Simulation time 38368464407 ps
CPU time 165.8 seconds
Started Jun 11 02:24:21 PM PDT 24
Finished Jun 11 02:27:08 PM PDT 24
Peak memory 215504 kb
Host smart-113082bf-bf89-43b7-8bf3-75a87cfbf261
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582551675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1582551675
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3364298221
Short name T408
Test name
Test status
Simulation time 1828707137 ps
CPU time 8.41 seconds
Started Jun 11 02:24:21 PM PDT 24
Finished Jun 11 02:24:30 PM PDT 24
Peak memory 211500 kb
Host smart-e2377453-afc7-4b9f-85f1-6cf029dcd804
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364298221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3364298221
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.828266092
Short name T391
Test name
Test status
Simulation time 12260687179 ps
CPU time 30.87 seconds
Started Jun 11 02:24:22 PM PDT 24
Finished Jun 11 02:24:54 PM PDT 24
Peak memory 218804 kb
Host smart-43c7ce4c-3d86-4e7c-bf80-6416b6352dca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828266092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.828266092
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.966478798
Short name T112
Test name
Test status
Simulation time 13072016199 ps
CPU time 86.59 seconds
Started Jun 11 02:24:25 PM PDT 24
Finished Jun 11 02:25:53 PM PDT 24
Peak memory 219244 kb
Host smart-d2fdafc3-3080-4b18-be8e-a2d8d53a7aed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966478798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.966478798
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1485044522
Short name T395
Test name
Test status
Simulation time 14865622828 ps
CPU time 29.92 seconds
Started Jun 11 02:24:23 PM PDT 24
Finished Jun 11 02:24:54 PM PDT 24
Peak memory 215440 kb
Host smart-ed38c640-8e48-44e1-b2af-53f96af191cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485044522 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1485044522
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2922771084
Short name T409
Test name
Test status
Simulation time 18678348774 ps
CPU time 30.07 seconds
Started Jun 11 02:24:23 PM PDT 24
Finished Jun 11 02:24:54 PM PDT 24
Peak memory 212328 kb
Host smart-73855cad-8266-40e1-b834-9544f186762b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922771084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2922771084
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.758524086
Short name T448
Test name
Test status
Simulation time 724786288 ps
CPU time 38.05 seconds
Started Jun 11 02:24:24 PM PDT 24
Finished Jun 11 02:25:04 PM PDT 24
Peak memory 218736 kb
Host smart-5eaf6efe-95fc-4f99-a52a-d50ecd3a6994
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758524086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.758524086
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2576800975
Short name T445
Test name
Test status
Simulation time 1617009043 ps
CPU time 14.04 seconds
Started Jun 11 02:24:21 PM PDT 24
Finished Jun 11 02:24:36 PM PDT 24
Peak memory 211344 kb
Host smart-aba9ae56-5cd3-49e6-9945-223b2048a694
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576800975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2576800975
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1112667816
Short name T404
Test name
Test status
Simulation time 10758423734 ps
CPU time 23.41 seconds
Started Jun 11 02:24:25 PM PDT 24
Finished Jun 11 02:24:49 PM PDT 24
Peak memory 217740 kb
Host smart-f98f2888-8f94-4415-b6dc-bed4046d46f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112667816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1112667816
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1971313322
Short name T114
Test name
Test status
Simulation time 5174653632 ps
CPU time 157.42 seconds
Started Jun 11 02:24:24 PM PDT 24
Finished Jun 11 02:27:03 PM PDT 24
Peak memory 219264 kb
Host smart-e62f4b69-2d32-446c-81b8-7b59409d7b0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971313322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1971313322
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1212709451
Short name T386
Test name
Test status
Simulation time 1904571137 ps
CPU time 20.36 seconds
Started Jun 11 02:24:19 PM PDT 24
Finished Jun 11 02:24:40 PM PDT 24
Peak memory 216836 kb
Host smart-38086a17-5464-438f-9026-0fd6e3ca60ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212709451 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1212709451
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1220077582
Short name T443
Test name
Test status
Simulation time 2641605483 ps
CPU time 22.4 seconds
Started Jun 11 02:24:18 PM PDT 24
Finished Jun 11 02:24:42 PM PDT 24
Peak memory 211772 kb
Host smart-47c242df-1f48-4edb-b4d2-bbaa7e3a3319
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220077582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1220077582
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1129927056
Short name T102
Test name
Test status
Simulation time 55927306331 ps
CPU time 112.49 seconds
Started Jun 11 02:24:22 PM PDT 24
Finished Jun 11 02:26:17 PM PDT 24
Peak memory 214268 kb
Host smart-9999cfdd-f24f-4095-9476-0bb6ad0981e4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129927056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1129927056
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.924676949
Short name T380
Test name
Test status
Simulation time 4116286388 ps
CPU time 31.36 seconds
Started Jun 11 02:24:21 PM PDT 24
Finished Jun 11 02:24:53 PM PDT 24
Peak memory 212556 kb
Host smart-4abd1cfc-4b41-468e-9e9b-0a8f7a42cf8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924676949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.924676949
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3557437063
Short name T412
Test name
Test status
Simulation time 636259959 ps
CPU time 13 seconds
Started Jun 11 02:24:23 PM PDT 24
Finished Jun 11 02:24:37 PM PDT 24
Peak memory 216372 kb
Host smart-6f269911-e9bd-411b-95cd-4707d7c785c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557437063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3557437063
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3302469981
Short name T119
Test name
Test status
Simulation time 738541426 ps
CPU time 159.72 seconds
Started Jun 11 02:24:23 PM PDT 24
Finished Jun 11 02:27:04 PM PDT 24
Peak memory 219188 kb
Host smart-952fab25-90ca-4834-98e5-26c0cd769bac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302469981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3302469981
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.829773226
Short name T401
Test name
Test status
Simulation time 9020290928 ps
CPU time 22.61 seconds
Started Jun 11 02:24:21 PM PDT 24
Finished Jun 11 02:24:45 PM PDT 24
Peak memory 218372 kb
Host smart-d29dd9e5-82c8-40af-ae09-687079ed631b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829773226 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.829773226
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.158686486
Short name T91
Test name
Test status
Simulation time 4308742951 ps
CPU time 27.7 seconds
Started Jun 11 02:24:23 PM PDT 24
Finished Jun 11 02:24:53 PM PDT 24
Peak memory 211932 kb
Host smart-073ddb24-80c1-4721-a9dc-2a16f61d4e8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158686486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.158686486
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3981813305
Short name T438
Test name
Test status
Simulation time 20171051511 ps
CPU time 121.45 seconds
Started Jun 11 02:24:21 PM PDT 24
Finished Jun 11 02:26:23 PM PDT 24
Peak memory 215164 kb
Host smart-046a8c5a-af6f-4034-89b3-65a77cbdb2d5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981813305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3981813305
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2303248625
Short name T106
Test name
Test status
Simulation time 3261969085 ps
CPU time 17.84 seconds
Started Jun 11 02:24:25 PM PDT 24
Finished Jun 11 02:24:45 PM PDT 24
Peak memory 212576 kb
Host smart-ac1c7ef7-878e-4368-bec3-04412ce5aaca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303248625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2303248625
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1613903465
Short name T375
Test name
Test status
Simulation time 336005944 ps
CPU time 14.1 seconds
Started Jun 11 02:24:22 PM PDT 24
Finished Jun 11 02:24:38 PM PDT 24
Peak memory 218436 kb
Host smart-18ee2cd4-8143-42d5-8a15-e2146661223c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613903465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1613903465
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1286196943
Short name T415
Test name
Test status
Simulation time 11890247417 ps
CPU time 106.73 seconds
Started Jun 11 02:24:24 PM PDT 24
Finished Jun 11 02:26:12 PM PDT 24
Peak memory 219252 kb
Host smart-e2691861-8c54-4e7b-ab7e-92861f9f8988
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286196943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1286196943
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.695933285
Short name T371
Test name
Test status
Simulation time 2557493819 ps
CPU time 22.67 seconds
Started Jun 11 02:23:44 PM PDT 24
Finished Jun 11 02:24:07 PM PDT 24
Peak memory 211520 kb
Host smart-b7d5a68b-4dbd-4a91-8359-5c2792895ee9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695933285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.695933285
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1085430076
Short name T449
Test name
Test status
Simulation time 3595427428 ps
CPU time 30.04 seconds
Started Jun 11 02:23:41 PM PDT 24
Finished Jun 11 02:24:12 PM PDT 24
Peak memory 211940 kb
Host smart-1e3d1212-d7c4-448e-a8df-267b0de6ab42
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085430076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1085430076
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3343928085
Short name T428
Test name
Test status
Simulation time 4214861406 ps
CPU time 30.61 seconds
Started Jun 11 02:23:50 PM PDT 24
Finished Jun 11 02:24:22 PM PDT 24
Peak memory 211980 kb
Host smart-858d9ce1-2ac5-4b92-8438-686f3b17fc78
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343928085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3343928085
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1715103788
Short name T362
Test name
Test status
Simulation time 743616413 ps
CPU time 9.75 seconds
Started Jun 11 02:23:45 PM PDT 24
Finished Jun 11 02:23:55 PM PDT 24
Peak memory 217444 kb
Host smart-14042502-39b5-4f9f-8645-03f07ea93df6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715103788 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1715103788
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3691327942
Short name T407
Test name
Test status
Simulation time 8818601355 ps
CPU time 33.6 seconds
Started Jun 11 02:23:43 PM PDT 24
Finished Jun 11 02:24:17 PM PDT 24
Peak memory 212176 kb
Host smart-0680a7d3-63bf-4361-a751-25a71c12d845
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691327942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3691327942
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2035515944
Short name T450
Test name
Test status
Simulation time 10850452509 ps
CPU time 24.02 seconds
Started Jun 11 02:23:51 PM PDT 24
Finished Jun 11 02:24:15 PM PDT 24
Peak memory 210992 kb
Host smart-9f38ee05-04b0-4947-bd44-7fe83ecc39c3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035515944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2035515944
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.187666101
Short name T360
Test name
Test status
Simulation time 8484860560 ps
CPU time 22.35 seconds
Started Jun 11 02:23:42 PM PDT 24
Finished Jun 11 02:24:05 PM PDT 24
Peak memory 210816 kb
Host smart-d9def381-2724-44b6-bac5-478e6eff583f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187666101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
187666101
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2770778932
Short name T370
Test name
Test status
Simulation time 57625554949 ps
CPU time 140.55 seconds
Started Jun 11 02:23:49 PM PDT 24
Finished Jun 11 02:26:11 PM PDT 24
Peak memory 215284 kb
Host smart-8036f9b2-a3e0-4c11-8f25-0843e53974ae
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770778932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2770778932
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2065922696
Short name T429
Test name
Test status
Simulation time 4719998109 ps
CPU time 26.32 seconds
Started Jun 11 02:23:45 PM PDT 24
Finished Jun 11 02:24:12 PM PDT 24
Peak memory 212916 kb
Host smart-fd223b22-fbaa-4bc3-b623-4e86f8ed5d6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065922696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2065922696
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.544913952
Short name T432
Test name
Test status
Simulation time 688666725 ps
CPU time 11.46 seconds
Started Jun 11 02:23:43 PM PDT 24
Finished Jun 11 02:23:55 PM PDT 24
Peak memory 217308 kb
Host smart-0d15f0ef-3f34-4f63-a55f-9c9b0895c925
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544913952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.544913952
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2409650070
Short name T115
Test name
Test status
Simulation time 7940756329 ps
CPU time 172.3 seconds
Started Jun 11 02:23:50 PM PDT 24
Finished Jun 11 02:26:43 PM PDT 24
Peak memory 214592 kb
Host smart-9a775bdc-3edd-4f04-b141-762840768b35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409650070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2409650070
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.352866893
Short name T436
Test name
Test status
Simulation time 1336822319 ps
CPU time 17.23 seconds
Started Jun 11 02:23:56 PM PDT 24
Finished Jun 11 02:24:14 PM PDT 24
Peak memory 211448 kb
Host smart-f32f4796-8c03-4868-b466-e4d3b493dcdb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352866893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.352866893
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.547499853
Short name T452
Test name
Test status
Simulation time 2948263675 ps
CPU time 17.98 seconds
Started Jun 11 02:23:52 PM PDT 24
Finished Jun 11 02:24:11 PM PDT 24
Peak memory 211092 kb
Host smart-8c812bac-dfd2-4102-ae44-e69c2df6865a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547499853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.547499853
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2203687526
Short name T96
Test name
Test status
Simulation time 3327346135 ps
CPU time 30.85 seconds
Started Jun 11 02:23:56 PM PDT 24
Finished Jun 11 02:24:28 PM PDT 24
Peak memory 212204 kb
Host smart-9157ee45-0a4e-4faa-bd95-42eeabc44c93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203687526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2203687526
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2996759708
Short name T373
Test name
Test status
Simulation time 1508822124 ps
CPU time 18.98 seconds
Started Jun 11 02:23:51 PM PDT 24
Finished Jun 11 02:24:11 PM PDT 24
Peak memory 217196 kb
Host smart-cb37eb4f-e720-4852-a67b-bd910b1d43b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996759708 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2996759708
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.211361541
Short name T431
Test name
Test status
Simulation time 426142811 ps
CPU time 11.19 seconds
Started Jun 11 02:23:53 PM PDT 24
Finished Jun 11 02:24:05 PM PDT 24
Peak memory 211060 kb
Host smart-05376673-1498-4d69-9960-64d9540a0a55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211361541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.211361541
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4151740437
Short name T387
Test name
Test status
Simulation time 8496123804 ps
CPU time 33.77 seconds
Started Jun 11 02:23:52 PM PDT 24
Finished Jun 11 02:24:27 PM PDT 24
Peak memory 211008 kb
Host smart-310625c6-6642-41f6-8f20-1ac1a17ab249
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151740437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.4151740437
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.727258288
Short name T441
Test name
Test status
Simulation time 689688648 ps
CPU time 8.19 seconds
Started Jun 11 02:23:52 PM PDT 24
Finished Jun 11 02:24:01 PM PDT 24
Peak memory 210692 kb
Host smart-f24b8cd8-fdc6-48b5-9293-aebf2eea913a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727258288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
727258288
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2909966830
Short name T90
Test name
Test status
Simulation time 10140040178 ps
CPU time 89.47 seconds
Started Jun 11 02:23:44 PM PDT 24
Finished Jun 11 02:25:14 PM PDT 24
Peak memory 214544 kb
Host smart-1dd0399c-9047-4a5b-96ad-9143713780b0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909966830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2909966830
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4247180945
Short name T378
Test name
Test status
Simulation time 21965913312 ps
CPU time 29.64 seconds
Started Jun 11 02:23:56 PM PDT 24
Finished Jun 11 02:24:26 PM PDT 24
Peak memory 212928 kb
Host smart-3ae65b84-bddc-4f06-a4b1-ec59c46c9ffe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247180945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.4247180945
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2937960340
Short name T397
Test name
Test status
Simulation time 16501923349 ps
CPU time 20.17 seconds
Started Jun 11 02:23:50 PM PDT 24
Finished Jun 11 02:24:10 PM PDT 24
Peak memory 218088 kb
Host smart-7efa5331-0276-4296-ab78-ab32f4293508
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937960340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2937960340
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1393955341
Short name T116
Test name
Test status
Simulation time 7796108806 ps
CPU time 175.2 seconds
Started Jun 11 02:23:44 PM PDT 24
Finished Jun 11 02:26:39 PM PDT 24
Peak memory 214576 kb
Host smart-c2e15c1b-0020-48b4-81bd-7b8deb6f7ad4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393955341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1393955341
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.922710619
Short name T385
Test name
Test status
Simulation time 1990374762 ps
CPU time 20.5 seconds
Started Jun 11 02:23:54 PM PDT 24
Finished Jun 11 02:24:15 PM PDT 24
Peak memory 212032 kb
Host smart-fb29b862-ccd3-4498-912b-997255e36803
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922710619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.922710619
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.526171917
Short name T382
Test name
Test status
Simulation time 331626919 ps
CPU time 8.51 seconds
Started Jun 11 02:23:56 PM PDT 24
Finished Jun 11 02:24:06 PM PDT 24
Peak memory 211104 kb
Host smart-abe78525-58b5-4ddf-8b22-4f35560b1476
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526171917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.526171917
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3047088202
Short name T377
Test name
Test status
Simulation time 3543149754 ps
CPU time 23.14 seconds
Started Jun 11 02:23:53 PM PDT 24
Finished Jun 11 02:24:17 PM PDT 24
Peak memory 211944 kb
Host smart-86e8ffd7-1606-4f54-bf67-ae1e9351a9c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047088202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3047088202
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1583882054
Short name T390
Test name
Test status
Simulation time 1776716808 ps
CPU time 19.61 seconds
Started Jun 11 02:23:51 PM PDT 24
Finished Jun 11 02:24:11 PM PDT 24
Peak memory 219220 kb
Host smart-17ae4764-eed6-403b-9a31-c01e1aba54a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583882054 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1583882054
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.954476030
Short name T101
Test name
Test status
Simulation time 2852055568 ps
CPU time 13.16 seconds
Started Jun 11 02:23:55 PM PDT 24
Finished Jun 11 02:24:09 PM PDT 24
Peak memory 211220 kb
Host smart-95471ff4-74e7-4200-bb48-380ff151be84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954476030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.954476030
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.871230079
Short name T402
Test name
Test status
Simulation time 24618209228 ps
CPU time 25.42 seconds
Started Jun 11 02:23:56 PM PDT 24
Finished Jun 11 02:24:22 PM PDT 24
Peak memory 210988 kb
Host smart-f968bd17-ac64-475b-80d2-65c14da43a11
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871230079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.871230079
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.779505628
Short name T451
Test name
Test status
Simulation time 660644956 ps
CPU time 8.07 seconds
Started Jun 11 02:23:55 PM PDT 24
Finished Jun 11 02:24:04 PM PDT 24
Peak memory 210772 kb
Host smart-b55a2ff1-adfb-4d6e-81fa-6ee3eff67910
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779505628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
779505628
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1912046195
Short name T379
Test name
Test status
Simulation time 4287480239 ps
CPU time 38.15 seconds
Started Jun 11 02:23:55 PM PDT 24
Finished Jun 11 02:24:34 PM PDT 24
Peak memory 218764 kb
Host smart-9605aa66-b188-4c3c-86e8-86b817b10dfe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912046195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1912046195
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2825993068
Short name T68
Test name
Test status
Simulation time 6594368311 ps
CPU time 19.4 seconds
Started Jun 11 02:23:50 PM PDT 24
Finished Jun 11 02:24:10 PM PDT 24
Peak memory 212888 kb
Host smart-d6591665-8fa0-4603-bfb5-001a18f6aa12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825993068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2825993068
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3086054835
Short name T367
Test name
Test status
Simulation time 18638895004 ps
CPU time 36.02 seconds
Started Jun 11 02:23:56 PM PDT 24
Finished Jun 11 02:24:33 PM PDT 24
Peak memory 219120 kb
Host smart-1df021fd-f4ea-47fc-8241-bd6d604ece20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086054835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3086054835
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4288285777
Short name T118
Test name
Test status
Simulation time 1858289938 ps
CPU time 166.25 seconds
Started Jun 11 02:23:55 PM PDT 24
Finished Jun 11 02:26:42 PM PDT 24
Peak memory 214260 kb
Host smart-9235df1b-33a5-46fc-9d9f-2757f557973a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288285777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.4288285777
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1088590721
Short name T423
Test name
Test status
Simulation time 2087248190 ps
CPU time 12.78 seconds
Started Jun 11 02:23:52 PM PDT 24
Finished Jun 11 02:24:06 PM PDT 24
Peak memory 217564 kb
Host smart-e142e14f-c087-419e-9c2a-807e65180934
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088590721 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1088590721
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.126186849
Short name T94
Test name
Test status
Simulation time 167697407 ps
CPU time 8.19 seconds
Started Jun 11 02:23:54 PM PDT 24
Finished Jun 11 02:24:03 PM PDT 24
Peak memory 210940 kb
Host smart-0163676d-9bc6-49d8-a44f-e4924845d9f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126186849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.126186849
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3672880739
Short name T455
Test name
Test status
Simulation time 65210848562 ps
CPU time 151.94 seconds
Started Jun 11 02:23:56 PM PDT 24
Finished Jun 11 02:26:29 PM PDT 24
Peak memory 215568 kb
Host smart-51f66ea1-6490-4985-8542-a975439ed886
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672880739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3672880739
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2378677486
Short name T444
Test name
Test status
Simulation time 171085662 ps
CPU time 8.44 seconds
Started Jun 11 02:23:51 PM PDT 24
Finished Jun 11 02:24:00 PM PDT 24
Peak memory 211412 kb
Host smart-9507f416-1e81-4aa0-a21b-b8fc3635f168
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378677486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2378677486
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1342426861
Short name T453
Test name
Test status
Simulation time 3924888670 ps
CPU time 35.36 seconds
Started Jun 11 02:23:55 PM PDT 24
Finished Jun 11 02:24:31 PM PDT 24
Peak memory 218044 kb
Host smart-b04c44bd-21f4-44c8-a788-daf5091aa73e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342426861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1342426861
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.161549833
Short name T111
Test name
Test status
Simulation time 2611429657 ps
CPU time 168.99 seconds
Started Jun 11 02:23:55 PM PDT 24
Finished Jun 11 02:26:45 PM PDT 24
Peak memory 219260 kb
Host smart-a27fe23a-c956-4276-a11c-aa6576d7841d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161549833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.161549833
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3859698192
Short name T416
Test name
Test status
Simulation time 7690677770 ps
CPU time 23.76 seconds
Started Jun 11 02:24:11 PM PDT 24
Finished Jun 11 02:24:36 PM PDT 24
Peak memory 216404 kb
Host smart-a81aa5fe-d595-43ff-94e2-479592d923c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859698192 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3859698192
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3746750421
Short name T399
Test name
Test status
Simulation time 21894945964 ps
CPU time 17.16 seconds
Started Jun 11 02:23:56 PM PDT 24
Finished Jun 11 02:24:14 PM PDT 24
Peak memory 212372 kb
Host smart-f7adde84-79f9-42c6-9cbc-40b78b2543f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746750421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3746750421
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.4114224276
Short name T422
Test name
Test status
Simulation time 11310742481 ps
CPU time 106.12 seconds
Started Jun 11 02:23:52 PM PDT 24
Finished Jun 11 02:25:38 PM PDT 24
Peak memory 214160 kb
Host smart-f8194e07-a4aa-4316-a22a-6a247a06673e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114224276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.4114224276
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2003113381
Short name T405
Test name
Test status
Simulation time 2126407852 ps
CPU time 20.71 seconds
Started Jun 11 02:23:54 PM PDT 24
Finished Jun 11 02:24:16 PM PDT 24
Peak memory 212632 kb
Host smart-1fea933d-9de1-46f0-8fd6-3e590702be8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003113381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2003113381
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.369091515
Short name T427
Test name
Test status
Simulation time 661087428 ps
CPU time 12.03 seconds
Started Jun 11 02:23:53 PM PDT 24
Finished Jun 11 02:24:05 PM PDT 24
Peak memory 217468 kb
Host smart-c7eb46f2-8ac3-43ac-b1ad-456cf775edb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369091515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.369091515
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2999581058
Short name T121
Test name
Test status
Simulation time 9081292010 ps
CPU time 162.5 seconds
Started Jun 11 02:23:56 PM PDT 24
Finished Jun 11 02:26:40 PM PDT 24
Peak memory 214408 kb
Host smart-8f2fa7c6-fafe-47e7-9e70-f5b38bde5b07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999581058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2999581058
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.442800760
Short name T446
Test name
Test status
Simulation time 3129895303 ps
CPU time 28.76 seconds
Started Jun 11 02:24:09 PM PDT 24
Finished Jun 11 02:24:39 PM PDT 24
Peak memory 217052 kb
Host smart-751f78af-41e9-44cf-9b1a-871e05e1d2ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442800760 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.442800760
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1772931723
Short name T418
Test name
Test status
Simulation time 2151409895 ps
CPU time 19.24 seconds
Started Jun 11 02:24:11 PM PDT 24
Finished Jun 11 02:24:31 PM PDT 24
Peak memory 212160 kb
Host smart-ac0535be-c05f-4d0c-a203-37c6a0b1d3d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772931723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1772931723
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.4043443909
Short name T457
Test name
Test status
Simulation time 67631981749 ps
CPU time 152.98 seconds
Started Jun 11 02:24:09 PM PDT 24
Finished Jun 11 02:26:43 PM PDT 24
Peak memory 215436 kb
Host smart-0db7b743-c2fe-45c4-b919-872906c01b95
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043443909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.4043443909
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.837770171
Short name T75
Test name
Test status
Simulation time 13154905908 ps
CPU time 28.59 seconds
Started Jun 11 02:24:11 PM PDT 24
Finished Jun 11 02:24:40 PM PDT 24
Peak memory 213060 kb
Host smart-a7ff3582-c317-4cf9-95d2-a830956ff169
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837770171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.837770171
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3252574836
Short name T384
Test name
Test status
Simulation time 2729268415 ps
CPU time 17.25 seconds
Started Jun 11 02:24:11 PM PDT 24
Finished Jun 11 02:24:29 PM PDT 24
Peak memory 217408 kb
Host smart-c93727e5-3f3a-4f18-a377-8a781901302a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252574836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3252574836
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3819281393
Short name T411
Test name
Test status
Simulation time 17625480637 ps
CPU time 100.77 seconds
Started Jun 11 02:24:11 PM PDT 24
Finished Jun 11 02:25:53 PM PDT 24
Peak memory 213224 kb
Host smart-e32261d7-06be-4919-ae1a-81dcb61fa89a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819281393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3819281393
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3866686958
Short name T376
Test name
Test status
Simulation time 11241966392 ps
CPU time 25.31 seconds
Started Jun 11 02:24:07 PM PDT 24
Finished Jun 11 02:24:33 PM PDT 24
Peak memory 217012 kb
Host smart-8ce17006-2b93-4496-9a49-4482bc8fb179
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866686958 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3866686958
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1633946413
Short name T79
Test name
Test status
Simulation time 31098954621 ps
CPU time 27.57 seconds
Started Jun 11 02:24:09 PM PDT 24
Finished Jun 11 02:24:38 PM PDT 24
Peak memory 212584 kb
Host smart-5817874b-eff0-41ec-a977-1c9a4697955c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633946413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1633946413
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3940596760
Short name T97
Test name
Test status
Simulation time 15414506768 ps
CPU time 148.48 seconds
Started Jun 11 02:24:08 PM PDT 24
Finished Jun 11 02:26:38 PM PDT 24
Peak memory 218848 kb
Host smart-acb2cab6-95b4-41e4-b412-148b0fb23f02
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940596760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3940596760
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3932223588
Short name T107
Test name
Test status
Simulation time 3187377770 ps
CPU time 26.45 seconds
Started Jun 11 02:24:09 PM PDT 24
Finished Jun 11 02:24:36 PM PDT 24
Peak memory 212696 kb
Host smart-f3392ea2-c6d0-433f-8f45-8e352be6a6a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932223588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3932223588
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.505691381
Short name T393
Test name
Test status
Simulation time 3522138736 ps
CPU time 33.06 seconds
Started Jun 11 02:24:09 PM PDT 24
Finished Jun 11 02:24:43 PM PDT 24
Peak memory 218560 kb
Host smart-7db802b7-ad23-44b0-8c1f-6ea6bf168fbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505691381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.505691381
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1895750457
Short name T394
Test name
Test status
Simulation time 995501772 ps
CPU time 158.35 seconds
Started Jun 11 02:24:11 PM PDT 24
Finished Jun 11 02:26:50 PM PDT 24
Peak memory 219212 kb
Host smart-e67a8161-a02f-4549-aa30-c8619fb68003
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895750457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1895750457
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3149292315
Short name T435
Test name
Test status
Simulation time 341215247 ps
CPU time 11.52 seconds
Started Jun 11 02:24:11 PM PDT 24
Finished Jun 11 02:24:23 PM PDT 24
Peak memory 215448 kb
Host smart-1c984eef-46c2-466b-96be-0406b694df9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149292315 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3149292315
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2823634678
Short name T76
Test name
Test status
Simulation time 5977584329 ps
CPU time 24.81 seconds
Started Jun 11 02:24:09 PM PDT 24
Finished Jun 11 02:24:35 PM PDT 24
Peak memory 212432 kb
Host smart-47d630d5-bcbf-40b6-bf5f-36ecef6d4dbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823634678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2823634678
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1623987115
Short name T374
Test name
Test status
Simulation time 11062252479 ps
CPU time 56.01 seconds
Started Jun 11 02:24:09 PM PDT 24
Finished Jun 11 02:25:06 PM PDT 24
Peak memory 215184 kb
Host smart-0e97b668-fdfc-4c3f-8c24-c2b8766baaa2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623987115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1623987115
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.815549351
Short name T456
Test name
Test status
Simulation time 11611031476 ps
CPU time 16.95 seconds
Started Jun 11 02:24:08 PM PDT 24
Finished Jun 11 02:24:26 PM PDT 24
Peak memory 212464 kb
Host smart-96200fd8-b498-4d26-b54a-11b6418045a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815549351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.815549351
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3142581154
Short name T57
Test name
Test status
Simulation time 1051633578 ps
CPU time 20.47 seconds
Started Jun 11 02:24:07 PM PDT 24
Finished Jun 11 02:24:28 PM PDT 24
Peak memory 218496 kb
Host smart-a114c6b6-1ae4-4d35-b297-4ef862322f59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142581154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3142581154
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2413824465
Short name T447
Test name
Test status
Simulation time 234217528 ps
CPU time 81.06 seconds
Started Jun 11 02:24:09 PM PDT 24
Finished Jun 11 02:25:31 PM PDT 24
Peak memory 212904 kb
Host smart-efb8eb17-4ee9-4689-a45a-5402c9939a89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413824465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2413824465
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3073739714
Short name T212
Test name
Test status
Simulation time 1716227757 ps
CPU time 18.97 seconds
Started Jun 11 03:19:15 PM PDT 24
Finished Jun 11 03:19:35 PM PDT 24
Peak memory 216904 kb
Host smart-b625cc3e-6f4e-47d7-85f8-47bdcc32a407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073739714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3073739714
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2990343005
Short name T183
Test name
Test status
Simulation time 45767244790 ps
CPU time 358.03 seconds
Started Jun 11 03:19:19 PM PDT 24
Finished Jun 11 03:25:21 PM PDT 24
Peak memory 235608 kb
Host smart-a756252e-e9f4-445d-be38-fb4c1bb8e578
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990343005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2990343005
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1954353498
Short name T328
Test name
Test status
Simulation time 8840525298 ps
CPU time 34.48 seconds
Started Jun 11 03:19:14 PM PDT 24
Finished Jun 11 03:19:50 PM PDT 24
Peak memory 219116 kb
Host smart-5ec4a78f-bd0f-4030-aca4-b8e8d2fe2f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954353498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1954353498
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1592396615
Short name T145
Test name
Test status
Simulation time 3130709083 ps
CPU time 25.46 seconds
Started Jun 11 03:19:16 PM PDT 24
Finished Jun 11 03:19:44 PM PDT 24
Peak memory 211176 kb
Host smart-5ec055ed-f0e9-479f-b9f6-06a0f3e40d47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1592396615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1592396615
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.631580688
Short name T29
Test name
Test status
Simulation time 17668495991 ps
CPU time 249.52 seconds
Started Jun 11 03:19:12 PM PDT 24
Finished Jun 11 03:23:24 PM PDT 24
Peak memory 235912 kb
Host smart-ded027c1-5aee-448c-a603-33fd215df9ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631580688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.631580688
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3988672734
Short name T338
Test name
Test status
Simulation time 15702021079 ps
CPU time 66.51 seconds
Started Jun 11 03:19:16 PM PDT 24
Finished Jun 11 03:20:24 PM PDT 24
Peak memory 216676 kb
Host smart-3daced30-e6b5-4456-9b01-94d2e70d8cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988672734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3988672734
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.547552325
Short name T275
Test name
Test status
Simulation time 46619176286 ps
CPU time 105.04 seconds
Started Jun 11 03:19:14 PM PDT 24
Finished Jun 11 03:21:00 PM PDT 24
Peak memory 220448 kb
Host smart-8c462f0a-d44f-472e-a31d-8d12184a5b82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547552325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.547552325
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2335030850
Short name T356
Test name
Test status
Simulation time 2159018515 ps
CPU time 11.72 seconds
Started Jun 11 03:19:17 PM PDT 24
Finished Jun 11 03:19:32 PM PDT 24
Peak memory 216896 kb
Host smart-c36944a3-bd3f-4cf3-bf07-8065ec6f8845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335030850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2335030850
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.642077540
Short name T253
Test name
Test status
Simulation time 193683845639 ps
CPU time 628.35 seconds
Started Jun 11 03:19:21 PM PDT 24
Finished Jun 11 03:29:54 PM PDT 24
Peak memory 236112 kb
Host smart-3ce23c36-dc21-4d2a-836b-fdc0847c0718
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642077540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.642077540
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2111052299
Short name T359
Test name
Test status
Simulation time 10528521341 ps
CPU time 85.2 seconds
Started Jun 11 03:19:17 PM PDT 24
Finished Jun 11 03:20:46 PM PDT 24
Peak memory 219152 kb
Host smart-d2b9d027-ff1f-41aa-9ade-a8bc4f02d2d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111052299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2111052299
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3783199331
Short name T320
Test name
Test status
Simulation time 118156279843 ps
CPU time 301.67 seconds
Started Jun 11 03:19:23 PM PDT 24
Finished Jun 11 03:24:29 PM PDT 24
Peak memory 237660 kb
Host smart-e9a10d4e-e7bb-4bdb-b88f-4255300b7f7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783199331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3783199331
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3134321744
Short name T202
Test name
Test status
Simulation time 67429033912 ps
CPU time 54.45 seconds
Started Jun 11 03:19:23 PM PDT 24
Finished Jun 11 03:20:22 PM PDT 24
Peak memory 219140 kb
Host smart-cd12eeee-4730-4b50-8050-9659773be420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134321744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3134321744
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1096527266
Short name T7
Test name
Test status
Simulation time 11564643102 ps
CPU time 26.15 seconds
Started Jun 11 03:19:21 PM PDT 24
Finished Jun 11 03:19:52 PM PDT 24
Peak memory 217540 kb
Host smart-bacc33d6-fd2b-450d-a8f4-a461704c341d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1096527266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1096527266
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2464837713
Short name T204
Test name
Test status
Simulation time 5450131851 ps
CPU time 57.84 seconds
Started Jun 11 03:19:25 PM PDT 24
Finished Jun 11 03:20:26 PM PDT 24
Peak memory 216064 kb
Host smart-407d456e-1484-42de-9eb6-43b031ef7853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464837713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2464837713
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.425233310
Short name T267
Test name
Test status
Simulation time 542270560 ps
CPU time 35.35 seconds
Started Jun 11 03:19:21 PM PDT 24
Finished Jun 11 03:20:01 PM PDT 24
Peak memory 218968 kb
Host smart-f16b1590-514c-4d80-8881-87ae31f72880
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425233310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.425233310
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.892890577
Short name T37
Test name
Test status
Simulation time 8552086073 ps
CPU time 33.77 seconds
Started Jun 11 03:19:21 PM PDT 24
Finished Jun 11 03:20:00 PM PDT 24
Peak memory 217044 kb
Host smart-791d1974-2243-4ff4-a0ab-3d35b8e7ea4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892890577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.892890577
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2264440360
Short name T43
Test name
Test status
Simulation time 9040303990 ps
CPU time 298.54 seconds
Started Jun 11 03:19:22 PM PDT 24
Finished Jun 11 03:24:25 PM PDT 24
Peak memory 235304 kb
Host smart-69fe0b26-c050-4468-bef0-a56833178215
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264440360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2264440360
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1278667768
Short name T264
Test name
Test status
Simulation time 9750926380 ps
CPU time 49.16 seconds
Started Jun 11 03:19:25 PM PDT 24
Finished Jun 11 03:20:18 PM PDT 24
Peak memory 218944 kb
Host smart-f9fb6740-295f-4e23-953f-5757b83ce71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278667768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1278667768
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2854857440
Short name T277
Test name
Test status
Simulation time 8722304381 ps
CPU time 19.15 seconds
Started Jun 11 03:19:22 PM PDT 24
Finished Jun 11 03:19:46 PM PDT 24
Peak memory 217464 kb
Host smart-55665b31-4b98-4f2c-99ec-faaa930dc66a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2854857440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2854857440
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3593950804
Short name T231
Test name
Test status
Simulation time 6863273041 ps
CPU time 31.37 seconds
Started Jun 11 03:19:23 PM PDT 24
Finished Jun 11 03:19:59 PM PDT 24
Peak memory 216256 kb
Host smart-9fe2cf2f-27c8-4ce1-a29f-901a349b2cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593950804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3593950804
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1365040742
Short name T89
Test name
Test status
Simulation time 3772279730 ps
CPU time 40.21 seconds
Started Jun 11 03:19:23 PM PDT 24
Finished Jun 11 03:20:08 PM PDT 24
Peak memory 216508 kb
Host smart-23d70445-c76a-4dac-958b-b0d8f3d57c63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365040742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1365040742
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1289864267
Short name T207
Test name
Test status
Simulation time 416449885 ps
CPU time 12.07 seconds
Started Jun 11 03:19:25 PM PDT 24
Finished Jun 11 03:19:41 PM PDT 24
Peak memory 216680 kb
Host smart-8736488d-216b-4699-aefd-b62b8c0dc188
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289864267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1289864267
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2375575159
Short name T234
Test name
Test status
Simulation time 120985711592 ps
CPU time 629.52 seconds
Started Jun 11 03:19:25 PM PDT 24
Finished Jun 11 03:29:58 PM PDT 24
Peak memory 234892 kb
Host smart-0be2bdd2-38c4-4e71-9edb-c5686d4ee7b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375575159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2375575159
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.390639474
Short name T161
Test name
Test status
Simulation time 3133163319 ps
CPU time 24.51 seconds
Started Jun 11 03:19:23 PM PDT 24
Finished Jun 11 03:19:52 PM PDT 24
Peak memory 219036 kb
Host smart-4589dc45-f48c-4543-a1aa-51d4157b6524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390639474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.390639474
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.4272873759
Short name T224
Test name
Test status
Simulation time 2209634557 ps
CPU time 22.83 seconds
Started Jun 11 03:19:24 PM PDT 24
Finished Jun 11 03:19:51 PM PDT 24
Peak memory 219116 kb
Host smart-735e28d9-2fd9-4ce8-b273-772d1565e161
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4272873759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.4272873759
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3448222643
Short name T18
Test name
Test status
Simulation time 14460321523 ps
CPU time 73.91 seconds
Started Jun 11 03:19:23 PM PDT 24
Finished Jun 11 03:20:41 PM PDT 24
Peak memory 219528 kb
Host smart-51023aa9-332f-40c2-abb4-4e528a84e6e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448222643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3448222643
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1381497153
Short name T172
Test name
Test status
Simulation time 21997449625 ps
CPU time 17.34 seconds
Started Jun 11 03:19:25 PM PDT 24
Finished Jun 11 03:19:46 PM PDT 24
Peak memory 217180 kb
Host smart-5170af30-3f66-4706-9d6a-b073f7f11dbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381497153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1381497153
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3897415658
Short name T230
Test name
Test status
Simulation time 14580303028 ps
CPU time 252.56 seconds
Started Jun 11 03:19:24 PM PDT 24
Finished Jun 11 03:23:40 PM PDT 24
Peak memory 239120 kb
Host smart-a5541b1a-7a86-4c7e-82a3-51d8bc75be99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897415658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3897415658
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.448913963
Short name T304
Test name
Test status
Simulation time 332492855 ps
CPU time 19.07 seconds
Started Jun 11 03:19:24 PM PDT 24
Finished Jun 11 03:19:47 PM PDT 24
Peak memory 218980 kb
Host smart-928dc2ba-327c-4805-aa3b-c42830fe0ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448913963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.448913963
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2728417645
Short name T246
Test name
Test status
Simulation time 9397032184 ps
CPU time 22.52 seconds
Started Jun 11 03:19:24 PM PDT 24
Finished Jun 11 03:19:50 PM PDT 24
Peak memory 219192 kb
Host smart-888f222d-0d34-473a-87a5-0cbd0701a381
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2728417645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2728417645
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3849407532
Short name T88
Test name
Test status
Simulation time 2625390550 ps
CPU time 20.69 seconds
Started Jun 11 03:19:23 PM PDT 24
Finished Jun 11 03:19:48 PM PDT 24
Peak memory 215924 kb
Host smart-296eb115-01cb-478e-91e5-4043915c15aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849407532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3849407532
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3756762132
Short name T220
Test name
Test status
Simulation time 1909926463 ps
CPU time 24.64 seconds
Started Jun 11 03:19:25 PM PDT 24
Finished Jun 11 03:19:53 PM PDT 24
Peak memory 218940 kb
Host smart-a8d0f528-cadb-4584-9f42-a279e1c04f6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756762132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3756762132
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3997885283
Short name T310
Test name
Test status
Simulation time 38110542602 ps
CPU time 22.67 seconds
Started Jun 11 03:19:24 PM PDT 24
Finished Jun 11 03:19:51 PM PDT 24
Peak memory 217280 kb
Host smart-8140d850-3c4c-4153-852b-8951bf141b35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997885283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3997885283
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.799322326
Short name T124
Test name
Test status
Simulation time 81564858362 ps
CPU time 223.98 seconds
Started Jun 11 03:19:24 PM PDT 24
Finished Jun 11 03:23:12 PM PDT 24
Peak memory 216588 kb
Host smart-8ffad843-48be-4bfb-8194-517bc7aea772
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799322326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.799322326
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1494103308
Short name T354
Test name
Test status
Simulation time 332452156 ps
CPU time 18.87 seconds
Started Jun 11 03:19:26 PM PDT 24
Finished Jun 11 03:19:48 PM PDT 24
Peak memory 219016 kb
Host smart-663eff01-022b-421c-bd72-1fda3823d125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494103308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1494103308
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2031457357
Short name T125
Test name
Test status
Simulation time 5186362496 ps
CPU time 25.05 seconds
Started Jun 11 03:19:22 PM PDT 24
Finished Jun 11 03:19:52 PM PDT 24
Peak memory 211528 kb
Host smart-1a34d149-c396-45c3-9c4d-9d6f3383be0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2031457357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2031457357
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.346707352
Short name T332
Test name
Test status
Simulation time 24621580995 ps
CPU time 56.41 seconds
Started Jun 11 03:19:23 PM PDT 24
Finished Jun 11 03:20:24 PM PDT 24
Peak memory 215540 kb
Host smart-a6732f16-9393-4642-b65c-a6c8761e2d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346707352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.346707352
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3646408114
Short name T345
Test name
Test status
Simulation time 4472408412 ps
CPU time 61.24 seconds
Started Jun 11 03:19:29 PM PDT 24
Finished Jun 11 03:20:32 PM PDT 24
Peak memory 219100 kb
Host smart-daa9132d-d4a9-4a6e-8501-0f8e29f1da3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646408114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3646408114
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2207638930
Short name T191
Test name
Test status
Simulation time 331996420 ps
CPU time 8.46 seconds
Started Jun 11 03:19:32 PM PDT 24
Finished Jun 11 03:19:42 PM PDT 24
Peak memory 216720 kb
Host smart-208813af-fcd0-482f-ad39-e5c477affe62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207638930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2207638930
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.924362896
Short name T206
Test name
Test status
Simulation time 17837988678 ps
CPU time 274.65 seconds
Started Jun 11 03:19:33 PM PDT 24
Finished Jun 11 03:24:09 PM PDT 24
Peak memory 237444 kb
Host smart-21c5eb33-d371-46fa-ac97-786bb5eedf50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924362896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.924362896
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4194352438
Short name T133
Test name
Test status
Simulation time 107941895943 ps
CPU time 67.42 seconds
Started Jun 11 03:19:34 PM PDT 24
Finished Jun 11 03:20:44 PM PDT 24
Peak memory 219028 kb
Host smart-7113d06c-72b4-43f5-b726-5f81e2d23ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194352438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.4194352438
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1673091053
Short name T5
Test name
Test status
Simulation time 27945195666 ps
CPU time 27.66 seconds
Started Jun 11 03:19:32 PM PDT 24
Finished Jun 11 03:20:01 PM PDT 24
Peak memory 217448 kb
Host smart-7d316af1-f2d3-4aec-add5-e7529be4eaff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1673091053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1673091053
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3807367673
Short name T141
Test name
Test status
Simulation time 15050629817 ps
CPU time 61.42 seconds
Started Jun 11 03:19:25 PM PDT 24
Finished Jun 11 03:20:31 PM PDT 24
Peak memory 217444 kb
Host smart-3fb93e32-9baf-4300-ab63-f89379042d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807367673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3807367673
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.634150667
Short name T322
Test name
Test status
Simulation time 65782934024 ps
CPU time 178.66 seconds
Started Jun 11 03:19:33 PM PDT 24
Finished Jun 11 03:22:33 PM PDT 24
Peak memory 221004 kb
Host smart-ad9d61db-b368-4d40-93e9-4162af819b7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634150667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.634150667
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2328350395
Short name T190
Test name
Test status
Simulation time 937644437 ps
CPU time 14.7 seconds
Started Jun 11 03:19:37 PM PDT 24
Finished Jun 11 03:19:54 PM PDT 24
Peak memory 216696 kb
Host smart-8600b22a-b2e6-4b87-a710-77ec72031023
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328350395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2328350395
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.648994510
Short name T176
Test name
Test status
Simulation time 320596933609 ps
CPU time 944.72 seconds
Started Jun 11 03:19:37 PM PDT 24
Finished Jun 11 03:35:24 PM PDT 24
Peak memory 237580 kb
Host smart-a39f5a81-02da-458f-b820-bf044985ad6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648994510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.648994510
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.4238932410
Short name T4
Test name
Test status
Simulation time 10258448531 ps
CPU time 24.6 seconds
Started Jun 11 03:19:32 PM PDT 24
Finished Jun 11 03:19:58 PM PDT 24
Peak memory 217552 kb
Host smart-ea991c2b-fa5a-4094-ba83-eff8b9678fe9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4238932410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.4238932410
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2356976982
Short name T32
Test name
Test status
Simulation time 1653709617 ps
CPU time 33.66 seconds
Started Jun 11 03:19:31 PM PDT 24
Finished Jun 11 03:20:06 PM PDT 24
Peak memory 215440 kb
Host smart-a700276e-e3e7-4c59-bb3a-f371dcc097bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356976982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2356976982
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1032657528
Short name T135
Test name
Test status
Simulation time 5110103583 ps
CPU time 35.29 seconds
Started Jun 11 03:19:34 PM PDT 24
Finished Jun 11 03:20:11 PM PDT 24
Peak memory 217548 kb
Host smart-2f242653-5193-4010-97ea-4b5a54b61fa7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032657528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1032657528
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.352089962
Short name T23
Test name
Test status
Simulation time 16444019730 ps
CPU time 27.84 seconds
Started Jun 11 03:19:32 PM PDT 24
Finished Jun 11 03:20:02 PM PDT 24
Peak memory 217268 kb
Host smart-4b549696-c7ab-4357-bf65-bfb42c9f1740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352089962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.352089962
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3132614685
Short name T123
Test name
Test status
Simulation time 151616879766 ps
CPU time 349.27 seconds
Started Jun 11 03:19:31 PM PDT 24
Finished Jun 11 03:25:21 PM PDT 24
Peak memory 227972 kb
Host smart-a394b910-6efc-4074-a301-4500cf963618
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132614685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3132614685
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1708433647
Short name T27
Test name
Test status
Simulation time 9794554157 ps
CPU time 50.11 seconds
Started Jun 11 03:19:34 PM PDT 24
Finished Jun 11 03:20:26 PM PDT 24
Peak memory 219144 kb
Host smart-d91b6efd-0af8-427d-8ddc-37447b8c50a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708433647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1708433647
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1171404888
Short name T214
Test name
Test status
Simulation time 260104664 ps
CPU time 11.85 seconds
Started Jun 11 03:19:32 PM PDT 24
Finished Jun 11 03:19:46 PM PDT 24
Peak memory 219072 kb
Host smart-0333a49a-753b-4db3-9da1-6a42dfafcfb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1171404888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1171404888
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3327731284
Short name T165
Test name
Test status
Simulation time 4672241081 ps
CPU time 55.32 seconds
Started Jun 11 03:19:35 PM PDT 24
Finished Jun 11 03:20:32 PM PDT 24
Peak memory 216264 kb
Host smart-2856c145-926b-4e5b-abe2-294e9ac19c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327731284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3327731284
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2891346499
Short name T309
Test name
Test status
Simulation time 1390247389 ps
CPU time 23.08 seconds
Started Jun 11 03:19:33 PM PDT 24
Finished Jun 11 03:19:58 PM PDT 24
Peak memory 218456 kb
Host smart-b88b1fde-0694-4836-ad7c-9a5e32642538
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891346499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2891346499
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1291347992
Short name T143
Test name
Test status
Simulation time 689640456 ps
CPU time 8.3 seconds
Started Jun 11 03:19:31 PM PDT 24
Finished Jun 11 03:19:40 PM PDT 24
Peak memory 216864 kb
Host smart-83b2b0f8-1f3b-4e01-9635-ded9f8efef0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291347992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1291347992
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3190158110
Short name T351
Test name
Test status
Simulation time 46109661593 ps
CPU time 501.01 seconds
Started Jun 11 03:19:36 PM PDT 24
Finished Jun 11 03:27:59 PM PDT 24
Peak memory 238960 kb
Host smart-f5c10bbe-acfb-4b1e-bd35-27b3232193e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190158110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3190158110
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2866263863
Short name T129
Test name
Test status
Simulation time 2015918236 ps
CPU time 26.58 seconds
Started Jun 11 03:19:32 PM PDT 24
Finished Jun 11 03:20:00 PM PDT 24
Peak memory 219016 kb
Host smart-02e290ad-ef5e-415d-8625-bf49409f63c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866263863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2866263863
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1856899775
Short name T147
Test name
Test status
Simulation time 2141415908 ps
CPU time 22.9 seconds
Started Jun 11 03:19:34 PM PDT 24
Finished Jun 11 03:19:58 PM PDT 24
Peak memory 218972 kb
Host smart-c247981a-a010-4e9b-b617-2de3d565f1c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1856899775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1856899775
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.3545649108
Short name T297
Test name
Test status
Simulation time 12701114634 ps
CPU time 57.03 seconds
Started Jun 11 03:19:32 PM PDT 24
Finished Jun 11 03:20:30 PM PDT 24
Peak memory 216968 kb
Host smart-c580dcc0-29d5-4853-9382-d3fa468e84cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545649108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.3545649108
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.705741537
Short name T65
Test name
Test status
Simulation time 8792226347 ps
CPU time 85.83 seconds
Started Jun 11 03:19:31 PM PDT 24
Finished Jun 11 03:20:58 PM PDT 24
Peak memory 219092 kb
Host smart-3f11e8a5-2a31-402b-b908-78f880d65051
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705741537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.705741537
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1743383218
Short name T271
Test name
Test status
Simulation time 12343929245 ps
CPU time 24.37 seconds
Started Jun 11 03:19:31 PM PDT 24
Finished Jun 11 03:19:56 PM PDT 24
Peak memory 217156 kb
Host smart-cf90ec90-bfc9-452d-9f6a-9618df8b50a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743383218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1743383218
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1536733860
Short name T188
Test name
Test status
Simulation time 77258698599 ps
CPU time 417.56 seconds
Started Jun 11 03:19:35 PM PDT 24
Finished Jun 11 03:26:34 PM PDT 24
Peak memory 224632 kb
Host smart-b5781c41-fbf4-49aa-bfb9-5975ab3467eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536733860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1536733860
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.256335616
Short name T46
Test name
Test status
Simulation time 674752145 ps
CPU time 19.43 seconds
Started Jun 11 03:19:30 PM PDT 24
Finished Jun 11 03:19:50 PM PDT 24
Peak memory 219128 kb
Host smart-3ba1354a-9ebe-44a4-b263-19dd41375f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256335616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.256335616
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.789736315
Short name T217
Test name
Test status
Simulation time 4517578385 ps
CPU time 34.27 seconds
Started Jun 11 03:19:34 PM PDT 24
Finished Jun 11 03:20:10 PM PDT 24
Peak memory 219192 kb
Host smart-3ca99d78-234d-4a7b-83ad-1b0b9abb414b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=789736315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.789736315
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1398732117
Short name T31
Test name
Test status
Simulation time 8661188409 ps
CPU time 90.98 seconds
Started Jun 11 03:19:33 PM PDT 24
Finished Jun 11 03:21:06 PM PDT 24
Peak memory 217076 kb
Host smart-14cd440e-f5c6-4cbd-b859-6c7a62eb5d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398732117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1398732117
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1215226945
Short name T358
Test name
Test status
Simulation time 14439160289 ps
CPU time 125.56 seconds
Started Jun 11 03:19:35 PM PDT 24
Finished Jun 11 03:21:43 PM PDT 24
Peak memory 219088 kb
Host smart-5fdf41e2-1423-4b6a-af07-a9a25a9ef929
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215226945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1215226945
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.295921796
Short name T349
Test name
Test status
Simulation time 717810454 ps
CPU time 8.26 seconds
Started Jun 11 03:19:17 PM PDT 24
Finished Jun 11 03:19:28 PM PDT 24
Peak memory 216720 kb
Host smart-a50ca339-37ba-4ff0-b007-0afd3a6c9f8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295921796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.295921796
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3863353953
Short name T223
Test name
Test status
Simulation time 88774505997 ps
CPU time 525.43 seconds
Started Jun 11 03:19:18 PM PDT 24
Finished Jun 11 03:28:07 PM PDT 24
Peak memory 237760 kb
Host smart-c46a0d6d-060d-467e-8661-1a47a2c77f77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863353953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3863353953
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3688729334
Short name T256
Test name
Test status
Simulation time 3128718288 ps
CPU time 39.14 seconds
Started Jun 11 03:19:17 PM PDT 24
Finished Jun 11 03:19:59 PM PDT 24
Peak memory 219052 kb
Host smart-40abc356-2060-4c0b-a678-e6b1d004d6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688729334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3688729334
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3277764734
Short name T12
Test name
Test status
Simulation time 1290290244 ps
CPU time 18.63 seconds
Started Jun 11 03:19:15 PM PDT 24
Finished Jun 11 03:19:36 PM PDT 24
Peak memory 219064 kb
Host smart-59ea8f6a-b53d-4b0a-85b9-19fffc6d4edb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3277764734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3277764734
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2337439499
Short name T20
Test name
Test status
Simulation time 4913453887 ps
CPU time 130.68 seconds
Started Jun 11 03:19:15 PM PDT 24
Finished Jun 11 03:21:28 PM PDT 24
Peak memory 235216 kb
Host smart-1aa2912b-7b98-4ee2-85d6-d5b076b719bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337439499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2337439499
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.525179537
Short name T254
Test name
Test status
Simulation time 361221787 ps
CPU time 20.44 seconds
Started Jun 11 03:19:12 PM PDT 24
Finished Jun 11 03:19:34 PM PDT 24
Peak memory 216096 kb
Host smart-c747ed0f-befa-41f5-9b9a-3237c742125a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525179537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.525179537
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3477847621
Short name T245
Test name
Test status
Simulation time 34559546994 ps
CPU time 170.56 seconds
Started Jun 11 03:19:11 PM PDT 24
Finished Jun 11 03:22:02 PM PDT 24
Peak memory 227364 kb
Host smart-14b2fae2-c15f-4e76-be13-a1314580be48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477847621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3477847621
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1704527568
Short name T13
Test name
Test status
Simulation time 26810523696 ps
CPU time 545.84 seconds
Started Jun 11 03:19:14 PM PDT 24
Finished Jun 11 03:28:22 PM PDT 24
Peak memory 230468 kb
Host smart-7db8c004-7920-48a1-b104-8aae43e3e26e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704527568 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1704527568
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2838961491
Short name T153
Test name
Test status
Simulation time 13417627731 ps
CPU time 26.52 seconds
Started Jun 11 03:19:35 PM PDT 24
Finished Jun 11 03:20:03 PM PDT 24
Peak memory 217136 kb
Host smart-35efc159-2934-4a51-8ab4-23fb0be12a72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838961491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2838961491
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3952057956
Short name T51
Test name
Test status
Simulation time 85385446467 ps
CPU time 228.11 seconds
Started Jun 11 03:19:34 PM PDT 24
Finished Jun 11 03:23:24 PM PDT 24
Peak memory 235604 kb
Host smart-003e2940-ca90-4f68-b4c0-43a1495874bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952057956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3952057956
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.668634118
Short name T242
Test name
Test status
Simulation time 1375487040 ps
CPU time 19.55 seconds
Started Jun 11 03:19:38 PM PDT 24
Finished Jun 11 03:19:59 PM PDT 24
Peak memory 219004 kb
Host smart-1c969b47-beca-4633-bda2-f957e56e7bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668634118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.668634118
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1241160489
Short name T178
Test name
Test status
Simulation time 491841213 ps
CPU time 12.07 seconds
Started Jun 11 03:19:33 PM PDT 24
Finished Jun 11 03:19:47 PM PDT 24
Peak memory 219060 kb
Host smart-6469abca-92ae-4df0-bb3d-11233e702758
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1241160489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1241160489
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.4086672493
Short name T177
Test name
Test status
Simulation time 17394097112 ps
CPU time 60.61 seconds
Started Jun 11 03:19:31 PM PDT 24
Finished Jun 11 03:20:32 PM PDT 24
Peak memory 216928 kb
Host smart-41541531-2cd6-4a5f-8c32-c68be19db947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086672493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.4086672493
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1609154920
Short name T137
Test name
Test status
Simulation time 1236678497 ps
CPU time 25.69 seconds
Started Jun 11 03:19:33 PM PDT 24
Finished Jun 11 03:20:00 PM PDT 24
Peak memory 211692 kb
Host smart-64644a80-3b23-47d5-ad02-1d558392d94b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609154920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1609154920
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.699513183
Short name T54
Test name
Test status
Simulation time 26427925865 ps
CPU time 6104.4 seconds
Started Jun 11 03:19:35 PM PDT 24
Finished Jun 11 05:01:21 PM PDT 24
Peak memory 230572 kb
Host smart-2e912f88-8b58-4923-a733-4c4edaf14e31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699513183 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.699513183
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2998667462
Short name T211
Test name
Test status
Simulation time 47429708114 ps
CPU time 22.92 seconds
Started Jun 11 03:19:37 PM PDT 24
Finished Jun 11 03:20:01 PM PDT 24
Peak memory 217208 kb
Host smart-71264d60-4eab-40e5-8115-4b995abcc2bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998667462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2998667462
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.522073316
Short name T44
Test name
Test status
Simulation time 11105071564 ps
CPU time 228.21 seconds
Started Jun 11 03:19:39 PM PDT 24
Finished Jun 11 03:23:28 PM PDT 24
Peak memory 225476 kb
Host smart-1e133d2c-b097-48ef-b4fd-0f2ec3909bc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522073316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.522073316
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4022077748
Short name T49
Test name
Test status
Simulation time 6576953590 ps
CPU time 56.35 seconds
Started Jun 11 03:19:36 PM PDT 24
Finished Jun 11 03:20:34 PM PDT 24
Peak memory 219112 kb
Host smart-623e9481-ae48-4ee2-a12f-e2c8f23b0042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022077748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4022077748
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.35311854
Short name T330
Test name
Test status
Simulation time 179371174 ps
CPU time 10.46 seconds
Started Jun 11 03:19:35 PM PDT 24
Finished Jun 11 03:19:47 PM PDT 24
Peak memory 218992 kb
Host smart-8fde6184-9b74-4b7c-86e4-d49876184c57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=35311854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.35311854
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.864854758
Short name T16
Test name
Test status
Simulation time 1794035207 ps
CPU time 23.71 seconds
Started Jun 11 03:19:37 PM PDT 24
Finished Jun 11 03:20:03 PM PDT 24
Peak memory 216064 kb
Host smart-2b50289d-d682-4a00-bc4e-87c7ed7687a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864854758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.864854758
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3838354773
Short name T333
Test name
Test status
Simulation time 8374578128 ps
CPU time 23.93 seconds
Started Jun 11 03:19:35 PM PDT 24
Finished Jun 11 03:20:01 PM PDT 24
Peak memory 214548 kb
Host smart-378f301f-0236-499a-8034-949f96b94346
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838354773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3838354773
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2849726210
Short name T313
Test name
Test status
Simulation time 169204164 ps
CPU time 8.31 seconds
Started Jun 11 03:19:35 PM PDT 24
Finished Jun 11 03:19:46 PM PDT 24
Peak memory 216788 kb
Host smart-b5f14c2c-81f7-4bf8-9d6d-abdb50ea5979
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849726210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2849726210
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2255848201
Short name T327
Test name
Test status
Simulation time 6553580047 ps
CPU time 274.5 seconds
Started Jun 11 03:19:36 PM PDT 24
Finished Jun 11 03:24:12 PM PDT 24
Peak memory 239344 kb
Host smart-5263f2e8-1cab-4764-883a-239d4379b6bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255848201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2255848201
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.446269844
Short name T210
Test name
Test status
Simulation time 3662488294 ps
CPU time 18.9 seconds
Started Jun 11 03:19:34 PM PDT 24
Finished Jun 11 03:19:54 PM PDT 24
Peak memory 219064 kb
Host smart-0350f4c5-f30f-449c-bc1d-41e3a3803258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446269844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.446269844
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1536217649
Short name T342
Test name
Test status
Simulation time 3116250015 ps
CPU time 28.94 seconds
Started Jun 11 03:19:35 PM PDT 24
Finished Jun 11 03:20:06 PM PDT 24
Peak memory 219212 kb
Host smart-f2492963-b6da-4932-ac79-5347e19ad382
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1536217649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1536217649
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.3914833864
Short name T159
Test name
Test status
Simulation time 6254738436 ps
CPU time 58.73 seconds
Started Jun 11 03:19:34 PM PDT 24
Finished Jun 11 03:20:35 PM PDT 24
Peak memory 217096 kb
Host smart-99e3f2f2-32c7-40a8-b6ba-a4c23bba3a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914833864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3914833864
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1978565754
Short name T226
Test name
Test status
Simulation time 72893293033 ps
CPU time 109.38 seconds
Started Jun 11 03:19:35 PM PDT 24
Finished Jun 11 03:21:27 PM PDT 24
Peak memory 220888 kb
Host smart-aeff5ded-c901-4606-b7fc-5554772a91ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978565754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1978565754
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3992759169
Short name T329
Test name
Test status
Simulation time 4503778166 ps
CPU time 21.44 seconds
Started Jun 11 03:19:37 PM PDT 24
Finished Jun 11 03:20:00 PM PDT 24
Peak memory 217272 kb
Host smart-631e10bc-037d-41ee-bf7f-414cb52ab378
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992759169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3992759169
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1375300175
Short name T40
Test name
Test status
Simulation time 5748973301 ps
CPU time 200.56 seconds
Started Jun 11 03:19:40 PM PDT 24
Finished Jun 11 03:23:02 PM PDT 24
Peak memory 229476 kb
Host smart-a09c4486-f105-4f2d-a777-3308ce581753
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375300175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1375300175
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.322926505
Short name T350
Test name
Test status
Simulation time 2054609420 ps
CPU time 33.46 seconds
Started Jun 11 03:19:39 PM PDT 24
Finished Jun 11 03:20:13 PM PDT 24
Peak memory 218988 kb
Host smart-00a3889d-38cb-4f94-b6f4-34bb8fffdedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322926505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.322926505
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2266479873
Short name T213
Test name
Test status
Simulation time 12982069016 ps
CPU time 23.92 seconds
Started Jun 11 03:19:38 PM PDT 24
Finished Jun 11 03:20:03 PM PDT 24
Peak memory 219152 kb
Host smart-fb37a659-998d-4844-ab72-c1673e46d4f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2266479873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2266479873
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3026722709
Short name T257
Test name
Test status
Simulation time 675496023 ps
CPU time 26.35 seconds
Started Jun 11 03:19:41 PM PDT 24
Finished Jun 11 03:20:09 PM PDT 24
Peak memory 215836 kb
Host smart-10bfa092-7f35-4e32-92a8-3d6f7b8de922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026722709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3026722709
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2449887771
Short name T272
Test name
Test status
Simulation time 5032505001 ps
CPU time 35.57 seconds
Started Jun 11 03:19:34 PM PDT 24
Finished Jun 11 03:20:11 PM PDT 24
Peak memory 218988 kb
Host smart-b350a293-8530-4269-8916-fbe4d538a91c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449887771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2449887771
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2021069228
Short name T59
Test name
Test status
Simulation time 3289763982 ps
CPU time 11.91 seconds
Started Jun 11 03:19:37 PM PDT 24
Finished Jun 11 03:19:50 PM PDT 24
Peak memory 216764 kb
Host smart-b2f936ce-d5dc-4868-8c04-6a2072802759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021069228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2021069228
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1039668069
Short name T151
Test name
Test status
Simulation time 20057539693 ps
CPU time 43.01 seconds
Started Jun 11 03:21:08 PM PDT 24
Finished Jun 11 03:21:52 PM PDT 24
Peak memory 219048 kb
Host smart-19757b8f-4535-4a97-b714-907d488e3c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039668069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1039668069
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.763007926
Short name T227
Test name
Test status
Simulation time 10447181105 ps
CPU time 25.92 seconds
Started Jun 11 03:19:40 PM PDT 24
Finished Jun 11 03:20:07 PM PDT 24
Peak memory 219180 kb
Host smart-09436b2f-c4fd-4518-9cd2-00d6205b477a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=763007926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.763007926
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3461404366
Short name T142
Test name
Test status
Simulation time 25326147866 ps
CPU time 57.28 seconds
Started Jun 11 03:19:37 PM PDT 24
Finished Jun 11 03:20:36 PM PDT 24
Peak memory 217160 kb
Host smart-a9979845-b99b-47d6-9bf4-eebcee641d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461404366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3461404366
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2947787824
Short name T209
Test name
Test status
Simulation time 7862204107 ps
CPU time 25.82 seconds
Started Jun 11 03:19:35 PM PDT 24
Finished Jun 11 03:20:02 PM PDT 24
Peak memory 219052 kb
Host smart-de262cc6-e486-438a-8b96-5934fd0c7daf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947787824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2947787824
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2310569259
Short name T337
Test name
Test status
Simulation time 4400169519 ps
CPU time 13.15 seconds
Started Jun 11 03:19:40 PM PDT 24
Finished Jun 11 03:19:55 PM PDT 24
Peak memory 217184 kb
Host smart-8b368029-75cc-42ec-9cec-b452426d6e50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310569259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2310569259
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3318720822
Short name T173
Test name
Test status
Simulation time 518028637830 ps
CPU time 1187.9 seconds
Started Jun 11 03:21:22 PM PDT 24
Finished Jun 11 03:41:12 PM PDT 24
Peak memory 225272 kb
Host smart-5332fd49-880c-4dd5-9b2b-4e1fd93df328
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318720822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3318720822
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.4009378036
Short name T189
Test name
Test status
Simulation time 16315877600 ps
CPU time 70.12 seconds
Started Jun 11 03:19:40 PM PDT 24
Finished Jun 11 03:20:52 PM PDT 24
Peak memory 219000 kb
Host smart-fb2e7be2-689d-4d04-a7e0-79eb49483262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009378036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.4009378036
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.223166199
Short name T228
Test name
Test status
Simulation time 1391611379 ps
CPU time 12.52 seconds
Started Jun 11 03:19:41 PM PDT 24
Finished Jun 11 03:19:55 PM PDT 24
Peak memory 218496 kb
Host smart-11111697-ef5a-43c0-8957-dbc26682442a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=223166199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.223166199
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1097023299
Short name T150
Test name
Test status
Simulation time 29508640602 ps
CPU time 65.77 seconds
Started Jun 11 03:19:41 PM PDT 24
Finished Jun 11 03:20:49 PM PDT 24
Peak memory 215724 kb
Host smart-a639ce7d-164c-4aa4-a86d-da7e3724d273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097023299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1097023299
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3879959537
Short name T314
Test name
Test status
Simulation time 68593916561 ps
CPU time 137.34 seconds
Started Jun 11 03:19:40 PM PDT 24
Finished Jun 11 03:21:59 PM PDT 24
Peak memory 219828 kb
Host smart-50115e3e-7d1d-40fb-9483-d7be0911b40e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879959537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3879959537
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3176157146
Short name T128
Test name
Test status
Simulation time 235130316 ps
CPU time 8.53 seconds
Started Jun 11 03:19:40 PM PDT 24
Finished Jun 11 03:19:50 PM PDT 24
Peak memory 216776 kb
Host smart-44a03bcb-de79-4e3b-80c9-1041d9d6bdfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176157146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3176157146
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2916197389
Short name T180
Test name
Test status
Simulation time 27548381036 ps
CPU time 416 seconds
Started Jun 11 03:19:42 PM PDT 24
Finished Jun 11 03:26:40 PM PDT 24
Peak memory 236384 kb
Host smart-5cc47ea1-480a-4701-9d1e-3bc08bcbb0b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916197389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2916197389
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2775514764
Short name T222
Test name
Test status
Simulation time 2052364072 ps
CPU time 32.48 seconds
Started Jun 11 03:19:39 PM PDT 24
Finished Jun 11 03:20:13 PM PDT 24
Peak memory 218972 kb
Host smart-4aadbc02-6171-43d1-bbb3-b3d7100b3554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775514764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2775514764
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3765374558
Short name T136
Test name
Test status
Simulation time 1827918014 ps
CPU time 21.46 seconds
Started Jun 11 03:19:42 PM PDT 24
Finished Jun 11 03:20:06 PM PDT 24
Peak memory 217332 kb
Host smart-769b0610-b441-4a3f-8da2-763d63b39002
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3765374558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3765374558
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2416376579
Short name T334
Test name
Test status
Simulation time 22200985766 ps
CPU time 58.81 seconds
Started Jun 11 03:19:43 PM PDT 24
Finished Jun 11 03:20:43 PM PDT 24
Peak memory 216684 kb
Host smart-a647ac15-23ad-49a6-b24e-90e8517aac6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416376579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2416376579
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.658461755
Short name T48
Test name
Test status
Simulation time 9206250912 ps
CPU time 43.77 seconds
Started Jun 11 03:19:47 PM PDT 24
Finished Jun 11 03:20:32 PM PDT 24
Peak memory 219164 kb
Host smart-124c284e-1eaf-4080-8c20-3a74b875b2ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658461755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.658461755
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3356138135
Short name T73
Test name
Test status
Simulation time 6179973827 ps
CPU time 12.06 seconds
Started Jun 11 03:19:48 PM PDT 24
Finished Jun 11 03:20:01 PM PDT 24
Peak memory 217048 kb
Host smart-65f1b40e-fcf9-4ee5-bfaf-845beedc01a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356138135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3356138135
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2496743397
Short name T232
Test name
Test status
Simulation time 25744930915 ps
CPU time 313.56 seconds
Started Jun 11 03:19:41 PM PDT 24
Finished Jun 11 03:24:56 PM PDT 24
Peak memory 219336 kb
Host smart-967ff6ff-f335-4c60-a38e-59a7cd11661c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496743397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2496743397
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3189176188
Short name T233
Test name
Test status
Simulation time 1992846034 ps
CPU time 33.17 seconds
Started Jun 11 03:19:43 PM PDT 24
Finished Jun 11 03:20:18 PM PDT 24
Peak memory 218992 kb
Host smart-0424ef1e-9ea4-48fd-a5b5-10a144cca859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189176188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3189176188
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2625157768
Short name T260
Test name
Test status
Simulation time 3739955416 ps
CPU time 31.32 seconds
Started Jun 11 03:19:46 PM PDT 24
Finished Jun 11 03:20:19 PM PDT 24
Peak memory 211240 kb
Host smart-9306d562-5df0-45e3-9332-28499407b48d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2625157768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2625157768
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3733431923
Short name T66
Test name
Test status
Simulation time 27901611519 ps
CPU time 58.02 seconds
Started Jun 11 03:19:42 PM PDT 24
Finished Jun 11 03:20:42 PM PDT 24
Peak memory 216288 kb
Host smart-60d5f8a5-1fb3-49d5-ae84-47f879431492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733431923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3733431923
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2737111532
Short name T343
Test name
Test status
Simulation time 8221391796 ps
CPU time 29.9 seconds
Started Jun 11 03:19:42 PM PDT 24
Finished Jun 11 03:20:14 PM PDT 24
Peak memory 214404 kb
Host smart-43b085e7-d07a-4066-a7c8-f26eb4f209dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737111532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2737111532
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3646224871
Short name T56
Test name
Test status
Simulation time 36830639437 ps
CPU time 1485.06 seconds
Started Jun 11 03:19:40 PM PDT 24
Finished Jun 11 03:44:27 PM PDT 24
Peak memory 233040 kb
Host smart-1ee1402e-ae12-4b16-9bd2-ac1649400c19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646224871 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.3646224871
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2448014327
Short name T181
Test name
Test status
Simulation time 6178357177 ps
CPU time 16.41 seconds
Started Jun 11 03:19:42 PM PDT 24
Finished Jun 11 03:20:00 PM PDT 24
Peak memory 217336 kb
Host smart-99c39599-2760-40c0-ab52-acca21b8ea00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448014327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2448014327
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2166873487
Short name T336
Test name
Test status
Simulation time 47826513913 ps
CPU time 328.21 seconds
Started Jun 11 03:19:42 PM PDT 24
Finished Jun 11 03:25:12 PM PDT 24
Peak memory 239456 kb
Host smart-193de7c4-170b-451b-8ce7-9bb18d1d617a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166873487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2166873487
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2554258979
Short name T149
Test name
Test status
Simulation time 19907034701 ps
CPU time 38.97 seconds
Started Jun 11 03:19:42 PM PDT 24
Finished Jun 11 03:20:23 PM PDT 24
Peak memory 218928 kb
Host smart-0f00bd46-60d0-45a2-9df6-b5ed81cc2595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554258979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2554258979
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2436785507
Short name T198
Test name
Test status
Simulation time 182706952 ps
CPU time 10.37 seconds
Started Jun 11 03:19:43 PM PDT 24
Finished Jun 11 03:19:55 PM PDT 24
Peak memory 219060 kb
Host smart-fe68b806-30aa-495f-b2c1-a56c6b1b65f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2436785507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2436785507
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1943450527
Short name T169
Test name
Test status
Simulation time 9065465545 ps
CPU time 51.62 seconds
Started Jun 11 03:19:42 PM PDT 24
Finished Jun 11 03:20:35 PM PDT 24
Peak memory 216452 kb
Host smart-8c946160-f201-4459-838e-af26c0dc02fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943450527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1943450527
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3960976475
Short name T262
Test name
Test status
Simulation time 23705869282 ps
CPU time 111.84 seconds
Started Jun 11 03:19:42 PM PDT 24
Finished Jun 11 03:21:36 PM PDT 24
Peak memory 216908 kb
Host smart-3477856e-0447-4063-b4c9-61bd35a34180
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960976475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3960976475
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2060832434
Short name T315
Test name
Test status
Simulation time 3170041844 ps
CPU time 26.92 seconds
Started Jun 11 03:19:42 PM PDT 24
Finished Jun 11 03:20:11 PM PDT 24
Peak memory 216784 kb
Host smart-821b78a6-8775-4f50-a472-300217b24bcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060832434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2060832434
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3315372587
Short name T306
Test name
Test status
Simulation time 19869867711 ps
CPU time 321.94 seconds
Started Jun 11 03:19:40 PM PDT 24
Finished Jun 11 03:25:03 PM PDT 24
Peak memory 239872 kb
Host smart-451d6e4f-24ea-4a6e-a9a7-158b8f907961
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315372587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3315372587
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2015151022
Short name T335
Test name
Test status
Simulation time 1200113716 ps
CPU time 26.91 seconds
Started Jun 11 03:19:43 PM PDT 24
Finished Jun 11 03:20:11 PM PDT 24
Peak memory 219000 kb
Host smart-1d5bc4f0-8556-47c2-8a0a-74891d69177e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015151022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2015151022
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1809963488
Short name T250
Test name
Test status
Simulation time 9818149025 ps
CPU time 25.42 seconds
Started Jun 11 03:19:45 PM PDT 24
Finished Jun 11 03:20:12 PM PDT 24
Peak memory 219176 kb
Host smart-f6efc44d-304e-485e-9fcb-a7a6c85658e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1809963488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1809963488
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3965056659
Short name T323
Test name
Test status
Simulation time 11696881560 ps
CPU time 51.19 seconds
Started Jun 11 03:19:43 PM PDT 24
Finished Jun 11 03:20:36 PM PDT 24
Peak memory 216912 kb
Host smart-b3c1dbeb-7628-4163-a899-97f48fd9c48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965056659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3965056659
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3330062340
Short name T30
Test name
Test status
Simulation time 17343745063 ps
CPU time 144.8 seconds
Started Jun 11 03:19:40 PM PDT 24
Finished Jun 11 03:22:07 PM PDT 24
Peak memory 219512 kb
Host smart-52380f86-acfc-4421-90e6-80abe872d76c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330062340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3330062340
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1839954227
Short name T255
Test name
Test status
Simulation time 2513909473 ps
CPU time 16.85 seconds
Started Jun 11 03:19:17 PM PDT 24
Finished Jun 11 03:19:37 PM PDT 24
Peak memory 216836 kb
Host smart-33441986-06e7-493a-9376-739ea8e3959b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839954227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1839954227
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.939493043
Short name T39
Test name
Test status
Simulation time 60958633045 ps
CPU time 669.32 seconds
Started Jun 11 03:19:13 PM PDT 24
Finished Jun 11 03:30:24 PM PDT 24
Peak memory 217696 kb
Host smart-56feba5d-44a6-4207-ad5b-1709ee8d09a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939493043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_co
rrupt_sig_fatal_chk.939493043
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.209108746
Short name T355
Test name
Test status
Simulation time 35529630635 ps
CPU time 72.89 seconds
Started Jun 11 03:19:13 PM PDT 24
Finished Jun 11 03:20:27 PM PDT 24
Peak memory 218932 kb
Host smart-3897c120-b5c8-42b6-a983-6029f82e4a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209108746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.209108746
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1547956149
Short name T132
Test name
Test status
Simulation time 4550516857 ps
CPU time 24.17 seconds
Started Jun 11 03:19:15 PM PDT 24
Finished Jun 11 03:19:41 PM PDT 24
Peak memory 217484 kb
Host smart-d007b160-7117-44cb-9650-b58e0fc21d3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1547956149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1547956149
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1584965937
Short name T22
Test name
Test status
Simulation time 671402854 ps
CPU time 115.97 seconds
Started Jun 11 03:19:19 PM PDT 24
Finished Jun 11 03:21:20 PM PDT 24
Peak memory 237404 kb
Host smart-c24aa4f8-ec19-4de1-b0a5-aa1f2bf74679
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584965937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1584965937
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3849548337
Short name T283
Test name
Test status
Simulation time 13678022569 ps
CPU time 58.31 seconds
Started Jun 11 03:19:13 PM PDT 24
Finished Jun 11 03:20:13 PM PDT 24
Peak memory 217960 kb
Host smart-9f86225e-7f64-48ba-ae19-9f43a17129f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849548337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3849548337
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2663652420
Short name T25
Test name
Test status
Simulation time 431782457 ps
CPU time 11.18 seconds
Started Jun 11 03:19:45 PM PDT 24
Finished Jun 11 03:19:58 PM PDT 24
Peak memory 216736 kb
Host smart-25079ef7-f36d-4fd6-a965-10baac8c532a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663652420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2663652420
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.4127806002
Short name T122
Test name
Test status
Simulation time 40754044141 ps
CPU time 373.33 seconds
Started Jun 11 03:19:48 PM PDT 24
Finished Jun 11 03:26:02 PM PDT 24
Peak memory 237160 kb
Host smart-6abda664-f60b-4e46-8475-f34442f07a3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127806002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.4127806002
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3248870452
Short name T268
Test name
Test status
Simulation time 33235398382 ps
CPU time 70.07 seconds
Started Jun 11 03:19:43 PM PDT 24
Finished Jun 11 03:20:55 PM PDT 24
Peak memory 218940 kb
Host smart-20b61094-01ec-4160-bb4b-07f7306a10a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248870452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3248870452
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2644221539
Short name T138
Test name
Test status
Simulation time 187340233 ps
CPU time 10.43 seconds
Started Jun 11 03:19:48 PM PDT 24
Finished Jun 11 03:20:00 PM PDT 24
Peak memory 219060 kb
Host smart-297d45a7-6403-4601-b4f3-b2633b99471a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644221539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2644221539
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1939193330
Short name T140
Test name
Test status
Simulation time 6106368968 ps
CPU time 60.87 seconds
Started Jun 11 03:19:46 PM PDT 24
Finished Jun 11 03:20:48 PM PDT 24
Peak memory 216380 kb
Host smart-53accf99-7427-46dc-8ade-cccb2eb05667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939193330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1939193330
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.341563483
Short name T218
Test name
Test status
Simulation time 71186618166 ps
CPU time 67.44 seconds
Started Jun 11 03:19:45 PM PDT 24
Finished Jun 11 03:20:54 PM PDT 24
Peak memory 219124 kb
Host smart-d2b68af2-93d6-4f85-a856-d558e512df97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341563483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.341563483
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1563248905
Short name T296
Test name
Test status
Simulation time 170662903 ps
CPU time 8.2 seconds
Started Jun 11 03:19:47 PM PDT 24
Finished Jun 11 03:19:57 PM PDT 24
Peak memory 216736 kb
Host smart-ce740995-d7c6-4a50-9e30-69934930f27c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563248905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1563248905
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1650233669
Short name T241
Test name
Test status
Simulation time 5906290418 ps
CPU time 258.68 seconds
Started Jun 11 03:19:47 PM PDT 24
Finished Jun 11 03:24:07 PM PDT 24
Peak memory 242352 kb
Host smart-be802edb-65e3-49b5-b137-e9dfed719c49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650233669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1650233669
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2742756217
Short name T279
Test name
Test status
Simulation time 12444379361 ps
CPU time 62.15 seconds
Started Jun 11 03:19:41 PM PDT 24
Finished Jun 11 03:20:45 PM PDT 24
Peak memory 219028 kb
Host smart-6a4277ba-500f-4fbe-86a3-310f89e66979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742756217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2742756217
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.661351039
Short name T197
Test name
Test status
Simulation time 8535382025 ps
CPU time 23.11 seconds
Started Jun 11 03:19:43 PM PDT 24
Finished Jun 11 03:20:08 PM PDT 24
Peak memory 217460 kb
Host smart-2cf4af03-c3d1-4640-94bf-6ee19765e697
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=661351039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.661351039
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2683757920
Short name T311
Test name
Test status
Simulation time 8329617615 ps
CPU time 67.27 seconds
Started Jun 11 03:19:48 PM PDT 24
Finished Jun 11 03:20:56 PM PDT 24
Peak memory 217040 kb
Host smart-3b76105d-6adf-4c91-9ad1-94f5c736df8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683757920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2683757920
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1606954213
Short name T317
Test name
Test status
Simulation time 34295006316 ps
CPU time 157.39 seconds
Started Jun 11 03:19:45 PM PDT 24
Finished Jun 11 03:22:24 PM PDT 24
Peak memory 219096 kb
Host smart-2db6666f-dc9d-4fcb-8c83-0b308ddcdafc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606954213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1606954213
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.504460278
Short name T167
Test name
Test status
Simulation time 3382290505 ps
CPU time 27.31 seconds
Started Jun 11 03:19:43 PM PDT 24
Finished Jun 11 03:20:12 PM PDT 24
Peak memory 216948 kb
Host smart-9f1abe76-1271-4f5b-b1b1-fc10ae79f62c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504460278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.504460278
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3958483562
Short name T215
Test name
Test status
Simulation time 39064631551 ps
CPU time 399.22 seconds
Started Jun 11 03:19:44 PM PDT 24
Finished Jun 11 03:26:25 PM PDT 24
Peak memory 233500 kb
Host smart-f10ed08b-cafb-4a57-971e-e3a7f482db12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958483562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3958483562
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2818497708
Short name T130
Test name
Test status
Simulation time 9817862357 ps
CPU time 49.39 seconds
Started Jun 11 03:19:44 PM PDT 24
Finished Jun 11 03:20:35 PM PDT 24
Peak memory 219048 kb
Host smart-43a801d5-d948-40f0-87c5-883b75a68b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818497708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2818497708
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2914144000
Short name T237
Test name
Test status
Simulation time 177359823 ps
CPU time 10.61 seconds
Started Jun 11 03:19:44 PM PDT 24
Finished Jun 11 03:19:56 PM PDT 24
Peak memory 219052 kb
Host smart-5960f9a5-b68b-44d5-8c0f-19276ae4762d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2914144000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2914144000
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.4028147105
Short name T305
Test name
Test status
Simulation time 13976003043 ps
CPU time 60.33 seconds
Started Jun 11 03:19:46 PM PDT 24
Finished Jun 11 03:20:48 PM PDT 24
Peak memory 216848 kb
Host smart-da5b0046-5076-4ac1-b848-42a415c041d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028147105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.4028147105
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3036450069
Short name T164
Test name
Test status
Simulation time 2962637403 ps
CPU time 30 seconds
Started Jun 11 03:19:44 PM PDT 24
Finished Jun 11 03:20:16 PM PDT 24
Peak memory 217300 kb
Host smart-a3911946-a9d9-4acb-a871-0a6165338cb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036450069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3036450069
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.169124075
Short name T53
Test name
Test status
Simulation time 159991518349 ps
CPU time 3240.54 seconds
Started Jun 11 03:19:44 PM PDT 24
Finished Jun 11 04:13:47 PM PDT 24
Peak memory 251912 kb
Host smart-b73e8eac-89f9-48bb-bf74-be63c6951e7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169124075 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.169124075
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3095588548
Short name T208
Test name
Test status
Simulation time 6896362190 ps
CPU time 28.32 seconds
Started Jun 11 03:21:21 PM PDT 24
Finished Jun 11 03:21:51 PM PDT 24
Peak memory 217276 kb
Host smart-99ca431d-61f6-4d3a-9a5f-e9119c17c878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095588548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3095588548
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.168023853
Short name T286
Test name
Test status
Simulation time 90519610697 ps
CPU time 495 seconds
Started Jun 11 03:21:21 PM PDT 24
Finished Jun 11 03:29:38 PM PDT 24
Peak memory 233628 kb
Host smart-3eb940ec-5980-4e35-bad4-f011343fab38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168023853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.168023853
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.844927548
Short name T3
Test name
Test status
Simulation time 16428716123 ps
CPU time 64.43 seconds
Started Jun 11 03:19:53 PM PDT 24
Finished Jun 11 03:20:59 PM PDT 24
Peak memory 218868 kb
Host smart-534db586-1ce0-414d-b3d2-929eb882981d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844927548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.844927548
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2937639634
Short name T288
Test name
Test status
Simulation time 1537952667 ps
CPU time 19.77 seconds
Started Jun 11 03:19:45 PM PDT 24
Finished Jun 11 03:20:06 PM PDT 24
Peak memory 219060 kb
Host smart-ffe3dee7-b2cd-4060-a379-06241df595ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2937639634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2937639634
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3570934137
Short name T302
Test name
Test status
Simulation time 1561729306 ps
CPU time 19.49 seconds
Started Jun 11 03:19:42 PM PDT 24
Finished Jun 11 03:20:03 PM PDT 24
Peak memory 216116 kb
Host smart-d46dcd84-0d3a-4767-911c-101b36a1c7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570934137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3570934137
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2776138521
Short name T83
Test name
Test status
Simulation time 1112512405 ps
CPU time 31.74 seconds
Started Jun 11 03:19:44 PM PDT 24
Finished Jun 11 03:20:18 PM PDT 24
Peak memory 218968 kb
Host smart-e0622698-8ff1-4eee-9c00-4c6a14aa9ea1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776138521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2776138521
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2171961838
Short name T240
Test name
Test status
Simulation time 5668118914 ps
CPU time 24.89 seconds
Started Jun 11 03:19:51 PM PDT 24
Finished Jun 11 03:20:17 PM PDT 24
Peak memory 217552 kb
Host smart-b782d695-87ec-41f1-8806-dc5109507bf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171961838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2171961838
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.4049236725
Short name T239
Test name
Test status
Simulation time 50984903416 ps
CPU time 532.22 seconds
Started Jun 11 03:19:53 PM PDT 24
Finished Jun 11 03:28:47 PM PDT 24
Peak memory 237740 kb
Host smart-2365e59b-e046-49e4-93ea-0f53c92b87bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049236725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.4049236725
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.892351387
Short name T308
Test name
Test status
Simulation time 32688469141 ps
CPU time 36.28 seconds
Started Jun 11 03:19:53 PM PDT 24
Finished Jun 11 03:20:31 PM PDT 24
Peak memory 219076 kb
Host smart-21c456de-941b-4175-9f40-996ece6060d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892351387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.892351387
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3361954475
Short name T301
Test name
Test status
Simulation time 3555082839 ps
CPU time 29.93 seconds
Started Jun 11 03:19:51 PM PDT 24
Finished Jun 11 03:20:23 PM PDT 24
Peak memory 211092 kb
Host smart-b6efb662-f883-483c-b204-3bc1ef347d44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3361954475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3361954475
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3511546284
Short name T244
Test name
Test status
Simulation time 839997291 ps
CPU time 27.51 seconds
Started Jun 11 03:19:52 PM PDT 24
Finished Jun 11 03:20:22 PM PDT 24
Peak memory 215632 kb
Host smart-bb78f2ab-2cbc-4f78-8b4a-d7a8ed6789a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511546284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3511546284
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2369969702
Short name T276
Test name
Test status
Simulation time 709762040 ps
CPU time 44.89 seconds
Started Jun 11 03:19:51 PM PDT 24
Finished Jun 11 03:20:38 PM PDT 24
Peak memory 218980 kb
Host smart-c26b7d13-5688-4354-879e-6dad71c74f49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369969702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2369969702
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1628561881
Short name T278
Test name
Test status
Simulation time 2948660476 ps
CPU time 13.41 seconds
Started Jun 11 03:19:50 PM PDT 24
Finished Jun 11 03:20:06 PM PDT 24
Peak memory 216744 kb
Host smart-6dd8247c-fa02-4c3c-aadc-4cb6b69a6212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628561881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1628561881
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.4209934558
Short name T274
Test name
Test status
Simulation time 274220114719 ps
CPU time 669.75 seconds
Started Jun 11 03:19:52 PM PDT 24
Finished Jun 11 03:31:05 PM PDT 24
Peak memory 223628 kb
Host smart-4ce535b5-e00b-42cc-ada4-446a256ca53e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209934558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.4209934558
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1826782147
Short name T273
Test name
Test status
Simulation time 17070499214 ps
CPU time 48.19 seconds
Started Jun 11 03:19:53 PM PDT 24
Finished Jun 11 03:20:43 PM PDT 24
Peak memory 219000 kb
Host smart-1dfd65c6-d4e3-4943-b583-673cc0fc60de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826782147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1826782147
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.764707860
Short name T326
Test name
Test status
Simulation time 6375048105 ps
CPU time 25.62 seconds
Started Jun 11 03:19:51 PM PDT 24
Finished Jun 11 03:20:19 PM PDT 24
Peak memory 211712 kb
Host smart-e7f20cc6-c43e-4778-966d-ece2c4ac70c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=764707860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.764707860
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.894523951
Short name T259
Test name
Test status
Simulation time 14950998619 ps
CPU time 79.16 seconds
Started Jun 11 03:19:52 PM PDT 24
Finished Jun 11 03:21:14 PM PDT 24
Peak memory 219256 kb
Host smart-95c332c9-225a-4eed-8c4f-8a3eddcbfc20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894523951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.894523951
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.4063531803
Short name T70
Test name
Test status
Simulation time 238279838 ps
CPU time 8.28 seconds
Started Jun 11 03:19:51 PM PDT 24
Finished Jun 11 03:20:01 PM PDT 24
Peak memory 217776 kb
Host smart-3fc02024-aeb2-4e57-84e8-94fe7b348f46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063531803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.4063531803
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2609405781
Short name T346
Test name
Test status
Simulation time 199629717558 ps
CPU time 506.74 seconds
Started Jun 11 03:19:51 PM PDT 24
Finished Jun 11 03:28:19 PM PDT 24
Peak memory 233360 kb
Host smart-b9ac5c9f-5b2c-4b50-bb87-18c40b5a1e46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609405781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2609405781
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1929583610
Short name T179
Test name
Test status
Simulation time 4648118053 ps
CPU time 33.15 seconds
Started Jun 11 03:19:51 PM PDT 24
Finished Jun 11 03:20:26 PM PDT 24
Peak memory 219096 kb
Host smart-8b40e2e8-7f12-4d48-b4ec-c067d81e345a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929583610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1929583610
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.933216015
Short name T290
Test name
Test status
Simulation time 2868240494 ps
CPU time 27.59 seconds
Started Jun 11 03:19:52 PM PDT 24
Finished Jun 11 03:20:21 PM PDT 24
Peak memory 219288 kb
Host smart-b60fc113-3602-459c-8f43-fe9c425c0d08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=933216015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.933216015
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.559135551
Short name T174
Test name
Test status
Simulation time 863385963 ps
CPU time 26.63 seconds
Started Jun 11 03:19:53 PM PDT 24
Finished Jun 11 03:20:22 PM PDT 24
Peak memory 216260 kb
Host smart-df3ca6b6-7ee0-4441-9964-5d804c50854a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559135551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.559135551
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.943358072
Short name T84
Test name
Test status
Simulation time 22435731833 ps
CPU time 70.93 seconds
Started Jun 11 03:19:53 PM PDT 24
Finished Jun 11 03:21:07 PM PDT 24
Peak memory 219092 kb
Host smart-1e3002e0-29bc-49e6-acc9-775a4d2da71b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943358072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.943358072
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.532824023
Short name T339
Test name
Test status
Simulation time 19296259011 ps
CPU time 34.94 seconds
Started Jun 11 03:19:54 PM PDT 24
Finished Jun 11 03:20:31 PM PDT 24
Peak memory 217248 kb
Host smart-70494987-861d-4aa3-ad24-b70d0c28960a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532824023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.532824023
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3796445687
Short name T42
Test name
Test status
Simulation time 90896109731 ps
CPU time 613.01 seconds
Started Jun 11 03:19:54 PM PDT 24
Finished Jun 11 03:30:09 PM PDT 24
Peak memory 234504 kb
Host smart-ac09f77c-a3aa-4c95-831e-2e198bbec01b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796445687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3796445687
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3036072418
Short name T293
Test name
Test status
Simulation time 662237672 ps
CPU time 19.3 seconds
Started Jun 11 03:19:52 PM PDT 24
Finished Jun 11 03:20:14 PM PDT 24
Peak memory 219004 kb
Host smart-826dda0f-c98f-4e48-8ab5-cdf35f2ecaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036072418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3036072418
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1202438153
Short name T281
Test name
Test status
Simulation time 4179989676 ps
CPU time 34.26 seconds
Started Jun 11 03:19:54 PM PDT 24
Finished Jun 11 03:20:31 PM PDT 24
Peak memory 219112 kb
Host smart-e73775b8-1921-4776-80d7-34558714baff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1202438153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1202438153
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.233474652
Short name T163
Test name
Test status
Simulation time 1440226635 ps
CPU time 19.94 seconds
Started Jun 11 03:19:52 PM PDT 24
Finished Jun 11 03:20:14 PM PDT 24
Peak memory 216044 kb
Host smart-1d87cb3c-f641-4c59-9066-658a30e483a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233474652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.233474652
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1901204348
Short name T235
Test name
Test status
Simulation time 8363475042 ps
CPU time 45.09 seconds
Started Jun 11 03:19:52 PM PDT 24
Finished Jun 11 03:20:39 PM PDT 24
Peak memory 218976 kb
Host smart-d662ae13-7d98-422f-afdc-e518fee1146e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901204348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1901204348
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3950571186
Short name T225
Test name
Test status
Simulation time 15304153880 ps
CPU time 31.44 seconds
Started Jun 11 03:19:54 PM PDT 24
Finished Jun 11 03:20:27 PM PDT 24
Peak memory 217212 kb
Host smart-0b480507-45ef-4f94-8d9d-7d6aa961d2ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950571186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3950571186
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.998403962
Short name T157
Test name
Test status
Simulation time 167839889107 ps
CPU time 861.81 seconds
Started Jun 11 03:19:54 PM PDT 24
Finished Jun 11 03:34:18 PM PDT 24
Peak memory 217540 kb
Host smart-72931c10-d6c3-403d-9dc9-b5534bd7ce48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998403962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.998403962
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1452455727
Short name T261
Test name
Test status
Simulation time 3810369485 ps
CPU time 41.09 seconds
Started Jun 11 03:19:54 PM PDT 24
Finished Jun 11 03:20:37 PM PDT 24
Peak memory 219040 kb
Host smart-faaef327-a98b-48e1-8033-36fb90667702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452455727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1452455727
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.465272686
Short name T295
Test name
Test status
Simulation time 2703068158 ps
CPU time 26.07 seconds
Started Jun 11 03:19:53 PM PDT 24
Finished Jun 11 03:20:21 PM PDT 24
Peak memory 219140 kb
Host smart-72bda6b2-6a47-410e-83f2-6e998fcad76d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=465272686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.465272686
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3085606980
Short name T316
Test name
Test status
Simulation time 32021565935 ps
CPU time 66.93 seconds
Started Jun 11 03:19:59 PM PDT 24
Finished Jun 11 03:21:08 PM PDT 24
Peak memory 216748 kb
Host smart-fff3046b-41d2-44d8-9679-fcc323779c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085606980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3085606980
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.4075278254
Short name T266
Test name
Test status
Simulation time 34340301193 ps
CPU time 79.04 seconds
Started Jun 11 03:19:52 PM PDT 24
Finished Jun 11 03:21:13 PM PDT 24
Peak memory 218896 kb
Host smart-6b6497c0-4a14-4357-b140-acc59d70a4de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075278254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.4075278254
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.284000497
Short name T229
Test name
Test status
Simulation time 660625736 ps
CPU time 8.21 seconds
Started Jun 11 03:19:55 PM PDT 24
Finished Jun 11 03:20:06 PM PDT 24
Peak memory 216716 kb
Host smart-d5771039-669b-4959-825e-08489bdf58ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284000497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.284000497
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1432151858
Short name T196
Test name
Test status
Simulation time 10047472957 ps
CPU time 177.05 seconds
Started Jun 11 03:19:57 PM PDT 24
Finished Jun 11 03:22:55 PM PDT 24
Peak memory 228240 kb
Host smart-efaee444-5c88-490c-b4b1-eb507f70855f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432151858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1432151858
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3718602118
Short name T193
Test name
Test status
Simulation time 22609231950 ps
CPU time 49.91 seconds
Started Jun 11 03:19:55 PM PDT 24
Finished Jun 11 03:20:47 PM PDT 24
Peak memory 218964 kb
Host smart-30c53d56-4bcd-4d38-93ae-b1a1e1c59c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718602118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3718602118
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3079897158
Short name T200
Test name
Test status
Simulation time 2453614745 ps
CPU time 10.23 seconds
Started Jun 11 03:19:52 PM PDT 24
Finished Jun 11 03:20:05 PM PDT 24
Peak memory 219116 kb
Host smart-52c7c4ca-4c67-40fc-b92e-fe26e763461c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3079897158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3079897158
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.4006318203
Short name T280
Test name
Test status
Simulation time 7512629299 ps
CPU time 30.26 seconds
Started Jun 11 03:19:54 PM PDT 24
Finished Jun 11 03:20:27 PM PDT 24
Peak memory 216052 kb
Host smart-a7d5facf-0474-4e15-a184-def5547a5ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006318203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.4006318203
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.4243411843
Short name T347
Test name
Test status
Simulation time 16597478153 ps
CPU time 64.98 seconds
Started Jun 11 03:19:53 PM PDT 24
Finished Jun 11 03:21:00 PM PDT 24
Peak memory 219116 kb
Host smart-8db47016-1731-403d-8f5d-7c373042bab4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243411843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.4243411843
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.4241697986
Short name T221
Test name
Test status
Simulation time 1199221208 ps
CPU time 14.86 seconds
Started Jun 11 03:19:15 PM PDT 24
Finished Jun 11 03:19:32 PM PDT 24
Peak memory 216912 kb
Host smart-9bed60e7-2f97-4be1-b7e9-ed2c19077466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241697986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.4241697986
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2227851938
Short name T2
Test name
Test status
Simulation time 71847552693 ps
CPU time 382.1 seconds
Started Jun 11 03:19:14 PM PDT 24
Finished Jun 11 03:25:38 PM PDT 24
Peak memory 236596 kb
Host smart-4eda481f-12fc-4eae-bf54-d4ccb76a30e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227851938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2227851938
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1116177873
Short name T146
Test name
Test status
Simulation time 2129573944 ps
CPU time 32.81 seconds
Started Jun 11 03:19:18 PM PDT 24
Finished Jun 11 03:19:54 PM PDT 24
Peak memory 218980 kb
Host smart-24189399-bee7-457d-bab0-634cc1a4cfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116177873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1116177873
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3185863739
Short name T1
Test name
Test status
Simulation time 178630021 ps
CPU time 10.6 seconds
Started Jun 11 03:19:17 PM PDT 24
Finished Jun 11 03:19:31 PM PDT 24
Peak memory 219040 kb
Host smart-3ed858c8-571c-4e13-8b68-fb7449faa35e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3185863739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3185863739
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3562564825
Short name T28
Test name
Test status
Simulation time 353443252 ps
CPU time 222.98 seconds
Started Jun 11 03:19:19 PM PDT 24
Finished Jun 11 03:23:07 PM PDT 24
Peak memory 236540 kb
Host smart-88fa65f5-9025-48be-b8fe-0add608ec790
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562564825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3562564825
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3694720932
Short name T64
Test name
Test status
Simulation time 6120441453 ps
CPU time 62.02 seconds
Started Jun 11 03:19:14 PM PDT 24
Finished Jun 11 03:20:18 PM PDT 24
Peak memory 216384 kb
Host smart-35fa958d-71af-4441-8c6c-ed5d75f6bc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694720932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3694720932
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.560578329
Short name T282
Test name
Test status
Simulation time 1442241999 ps
CPU time 24.46 seconds
Started Jun 11 03:19:16 PM PDT 24
Finished Jun 11 03:19:43 PM PDT 24
Peak memory 219008 kb
Host smart-1314e19a-863c-4b90-b722-a7ef4d197d70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560578329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.560578329
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1672089848
Short name T24
Test name
Test status
Simulation time 15083133859 ps
CPU time 31.57 seconds
Started Jun 11 03:19:58 PM PDT 24
Finished Jun 11 03:20:31 PM PDT 24
Peak memory 217112 kb
Host smart-8d36bed6-6b1e-479e-baa3-380975e74a76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672089848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1672089848
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.104012922
Short name T33
Test name
Test status
Simulation time 19638261907 ps
CPU time 176.57 seconds
Started Jun 11 03:19:55 PM PDT 24
Finished Jun 11 03:22:54 PM PDT 24
Peak memory 238380 kb
Host smart-7a4e68af-839c-4d51-9a90-30eb870dc834
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104012922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.104012922
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.958318661
Short name T270
Test name
Test status
Simulation time 1374486048 ps
CPU time 18.87 seconds
Started Jun 11 03:19:54 PM PDT 24
Finished Jun 11 03:20:15 PM PDT 24
Peak memory 218956 kb
Host smart-f2dd919e-88c7-402d-8cbc-f23b11473be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958318661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.958318661
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2199101840
Short name T168
Test name
Test status
Simulation time 15416703852 ps
CPU time 34.2 seconds
Started Jun 11 03:19:53 PM PDT 24
Finished Jun 11 03:20:29 PM PDT 24
Peak memory 219140 kb
Host smart-fc6832d9-19df-4588-850c-977d6d0d1b7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2199101840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2199101840
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3915899598
Short name T294
Test name
Test status
Simulation time 17072084924 ps
CPU time 69.51 seconds
Started Jun 11 03:19:55 PM PDT 24
Finished Jun 11 03:21:06 PM PDT 24
Peak memory 217320 kb
Host smart-1c5126c7-c528-435e-9dc4-a42c2d9e9ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915899598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3915899598
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.634988808
Short name T353
Test name
Test status
Simulation time 1167756339 ps
CPU time 32.6 seconds
Started Jun 11 03:19:56 PM PDT 24
Finished Jun 11 03:20:30 PM PDT 24
Peak memory 217356 kb
Host smart-23abbc12-244a-400e-bc03-81604a5a1b7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634988808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.634988808
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1701143683
Short name T238
Test name
Test status
Simulation time 3084668240 ps
CPU time 13.09 seconds
Started Jun 11 03:20:00 PM PDT 24
Finished Jun 11 03:20:14 PM PDT 24
Peak memory 216588 kb
Host smart-ecd3346a-9f58-4751-bb52-fe331db8701d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701143683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1701143683
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.459200934
Short name T187
Test name
Test status
Simulation time 19222135951 ps
CPU time 135.73 seconds
Started Jun 11 03:19:57 PM PDT 24
Finished Jun 11 03:22:14 PM PDT 24
Peak memory 236916 kb
Host smart-a9ecc04f-9e6d-4053-8f26-6c992c7d4f20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459200934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.459200934
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.920087768
Short name T299
Test name
Test status
Simulation time 3938035752 ps
CPU time 44.76 seconds
Started Jun 11 03:20:00 PM PDT 24
Finished Jun 11 03:20:46 PM PDT 24
Peak memory 218572 kb
Host smart-9aa621c7-d701-48ff-80f8-a625fa64cf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920087768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.920087768
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1197899530
Short name T171
Test name
Test status
Simulation time 691353682 ps
CPU time 10.39 seconds
Started Jun 11 03:19:55 PM PDT 24
Finished Jun 11 03:20:08 PM PDT 24
Peak memory 219016 kb
Host smart-121c8594-a7d0-4866-9a8e-ad3574e7ceed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1197899530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1197899530
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1694406753
Short name T156
Test name
Test status
Simulation time 1440298126 ps
CPU time 20.12 seconds
Started Jun 11 03:19:58 PM PDT 24
Finished Jun 11 03:20:20 PM PDT 24
Peak memory 216672 kb
Host smart-5cd2db8f-6d27-4746-b489-21b33951dcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694406753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1694406753
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3102353162
Short name T243
Test name
Test status
Simulation time 71843989538 ps
CPU time 123.43 seconds
Started Jun 11 03:19:58 PM PDT 24
Finished Jun 11 03:22:03 PM PDT 24
Peak memory 220080 kb
Host smart-bef66698-105a-4d9e-990e-8ac136a8b2ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102353162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3102353162
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3539497355
Short name T287
Test name
Test status
Simulation time 6459271765 ps
CPU time 17.36 seconds
Started Jun 11 03:19:58 PM PDT 24
Finished Jun 11 03:20:17 PM PDT 24
Peak memory 217184 kb
Host smart-aa9a148c-00bc-4a5f-aeef-8eb13a489b3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539497355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3539497355
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.4249303954
Short name T45
Test name
Test status
Simulation time 2457813636 ps
CPU time 175.19 seconds
Started Jun 11 03:20:03 PM PDT 24
Finished Jun 11 03:23:00 PM PDT 24
Peak memory 240516 kb
Host smart-e93f5d2e-2a01-41ac-a47b-f3263032312f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249303954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.4249303954
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.326164878
Short name T6
Test name
Test status
Simulation time 25623521823 ps
CPU time 59.99 seconds
Started Jun 11 03:19:59 PM PDT 24
Finished Jun 11 03:21:01 PM PDT 24
Peak memory 219108 kb
Host smart-5e59bef9-a3b5-4938-9b50-fd2a8fc4d9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326164878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.326164878
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1918415476
Short name T58
Test name
Test status
Simulation time 361191878 ps
CPU time 10.2 seconds
Started Jun 11 03:19:58 PM PDT 24
Finished Jun 11 03:20:10 PM PDT 24
Peak memory 219060 kb
Host smart-781f37a4-edb7-4c4d-beff-9aefe764588b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1918415476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1918415476
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1565727193
Short name T331
Test name
Test status
Simulation time 343359203 ps
CPU time 20.65 seconds
Started Jun 11 03:20:02 PM PDT 24
Finished Jun 11 03:20:24 PM PDT 24
Peak memory 215920 kb
Host smart-650cdc1e-f51b-47cf-9d91-5ba098531f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565727193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1565727193
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2943241882
Short name T357
Test name
Test status
Simulation time 2449617902 ps
CPU time 53.28 seconds
Started Jun 11 03:19:59 PM PDT 24
Finished Jun 11 03:20:54 PM PDT 24
Peak memory 219148 kb
Host smart-d9438843-9a93-433c-8bf6-3b52b386eff9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943241882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2943241882
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2018701028
Short name T292
Test name
Test status
Simulation time 5731335546 ps
CPU time 26.61 seconds
Started Jun 11 03:20:09 PM PDT 24
Finished Jun 11 03:20:37 PM PDT 24
Peak memory 217104 kb
Host smart-39d2f047-d808-4957-8d10-736362a10cd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018701028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2018701028
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2687836653
Short name T185
Test name
Test status
Simulation time 34949066521 ps
CPU time 576.2 seconds
Started Jun 11 03:20:09 PM PDT 24
Finished Jun 11 03:29:47 PM PDT 24
Peak memory 234020 kb
Host smart-d75345c6-5b2f-4adc-abd7-00a4a00620da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687836653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2687836653
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2026180233
Short name T318
Test name
Test status
Simulation time 2637036267 ps
CPU time 24.02 seconds
Started Jun 11 03:20:10 PM PDT 24
Finished Jun 11 03:20:35 PM PDT 24
Peak memory 219056 kb
Host smart-e9a5eee2-31fd-46cb-a6bb-a1a3dedf266b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026180233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2026180233
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.198029961
Short name T170
Test name
Test status
Simulation time 5292906163 ps
CPU time 25.33 seconds
Started Jun 11 03:20:10 PM PDT 24
Finished Jun 11 03:20:36 PM PDT 24
Peak memory 211452 kb
Host smart-246b722c-b1cf-4de5-8507-afd3c2cda93c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=198029961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.198029961
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.775849896
Short name T201
Test name
Test status
Simulation time 3736794088 ps
CPU time 41.95 seconds
Started Jun 11 03:20:02 PM PDT 24
Finished Jun 11 03:20:45 PM PDT 24
Peak memory 215056 kb
Host smart-f775c058-de00-42ca-b97b-31ee3e8d1375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775849896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.775849896
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.736191112
Short name T285
Test name
Test status
Simulation time 4525706873 ps
CPU time 63.02 seconds
Started Jun 11 03:20:00 PM PDT 24
Finished Jun 11 03:21:05 PM PDT 24
Peak memory 219076 kb
Host smart-a3386e88-3d58-43be-9e9c-af962d3007be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736191112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.736191112
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.4020367258
Short name T72
Test name
Test status
Simulation time 14111174525 ps
CPU time 30.13 seconds
Started Jun 11 03:20:10 PM PDT 24
Finished Jun 11 03:20:42 PM PDT 24
Peak memory 217112 kb
Host smart-2b326b16-291c-4ce7-880d-79becd423ef4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020367258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.4020367258
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2071635575
Short name T41
Test name
Test status
Simulation time 6731456609 ps
CPU time 195.05 seconds
Started Jun 11 03:20:12 PM PDT 24
Finished Jun 11 03:23:28 PM PDT 24
Peak memory 238352 kb
Host smart-e49fceba-bb8c-4e22-a64e-42b10d340cde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071635575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2071635575
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3791717230
Short name T249
Test name
Test status
Simulation time 2779725089 ps
CPU time 36.05 seconds
Started Jun 11 03:21:21 PM PDT 24
Finished Jun 11 03:21:58 PM PDT 24
Peak memory 219056 kb
Host smart-e44094e6-a7d2-432c-b0cc-338a78423814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791717230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3791717230
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2906525265
Short name T348
Test name
Test status
Simulation time 13148951259 ps
CPU time 29.57 seconds
Started Jun 11 03:20:08 PM PDT 24
Finished Jun 11 03:20:38 PM PDT 24
Peak memory 219164 kb
Host smart-507604ae-182e-4ac5-a1e6-931ffdd85f4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2906525265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2906525265
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2636822261
Short name T86
Test name
Test status
Simulation time 688486220 ps
CPU time 20.45 seconds
Started Jun 11 03:20:09 PM PDT 24
Finished Jun 11 03:20:31 PM PDT 24
Peak memory 216196 kb
Host smart-1da8cc60-ba05-427f-8600-29f28884f51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636822261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2636822261
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2168509135
Short name T34
Test name
Test status
Simulation time 46671077707 ps
CPU time 103.07 seconds
Started Jun 11 03:20:08 PM PDT 24
Finished Jun 11 03:21:52 PM PDT 24
Peak memory 219064 kb
Host smart-f89bc9b6-4e7d-4a54-85d3-ce27cc51f8cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168509135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2168509135
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.761305968
Short name T284
Test name
Test status
Simulation time 3205122492 ps
CPU time 28.35 seconds
Started Jun 11 03:20:20 PM PDT 24
Finished Jun 11 03:20:50 PM PDT 24
Peak memory 216744 kb
Host smart-f91ac01a-2b28-4617-b75c-f30d40c5010b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761305968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.761305968
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2171458560
Short name T263
Test name
Test status
Simulation time 8665061994 ps
CPU time 251.39 seconds
Started Jun 11 03:20:20 PM PDT 24
Finished Jun 11 03:24:34 PM PDT 24
Peak memory 234468 kb
Host smart-78eddfd7-354d-4f94-8adb-fce236527bb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171458560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2171458560
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3157458808
Short name T307
Test name
Test status
Simulation time 7884244468 ps
CPU time 45.02 seconds
Started Jun 11 03:20:19 PM PDT 24
Finished Jun 11 03:21:05 PM PDT 24
Peak memory 219016 kb
Host smart-caa419c7-0f74-428c-9273-0deb4d6b63eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157458808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3157458808
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2194483464
Short name T175
Test name
Test status
Simulation time 1448968690 ps
CPU time 14.91 seconds
Started Jun 11 03:20:19 PM PDT 24
Finished Jun 11 03:20:35 PM PDT 24
Peak memory 218664 kb
Host smart-de6907a9-bbc2-4d8e-b52e-d1b8a1ed916b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2194483464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2194483464
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2830363361
Short name T340
Test name
Test status
Simulation time 4456851076 ps
CPU time 47.19 seconds
Started Jun 11 03:20:09 PM PDT 24
Finished Jun 11 03:20:58 PM PDT 24
Peak memory 216632 kb
Host smart-1678a500-c5a8-466b-a746-d104a1628e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830363361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2830363361
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3529204970
Short name T258
Test name
Test status
Simulation time 213715333214 ps
CPU time 180.48 seconds
Started Jun 11 03:20:18 PM PDT 24
Finished Jun 11 03:23:20 PM PDT 24
Peak memory 220792 kb
Host smart-d15b0e4e-16d9-46b7-a6ba-f36ad0b922d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529204970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3529204970
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1839128467
Short name T154
Test name
Test status
Simulation time 8059606948 ps
CPU time 33.76 seconds
Started Jun 11 03:20:21 PM PDT 24
Finished Jun 11 03:20:57 PM PDT 24
Peak memory 217260 kb
Host smart-ad838933-1e12-4516-b82d-29700b73ebbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839128467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1839128467
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.412799974
Short name T312
Test name
Test status
Simulation time 94684271745 ps
CPU time 901.99 seconds
Started Jun 11 03:20:19 PM PDT 24
Finished Jun 11 03:35:22 PM PDT 24
Peak memory 224972 kb
Host smart-97d74a00-d5f2-442e-b6c3-f625503b07a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412799974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.412799974
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4253307736
Short name T38
Test name
Test status
Simulation time 734838793 ps
CPU time 19.69 seconds
Started Jun 11 03:20:19 PM PDT 24
Finished Jun 11 03:20:39 PM PDT 24
Peak memory 218972 kb
Host smart-9453f81f-0718-4253-9ea3-e0a0101f2aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253307736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4253307736
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2772955532
Short name T247
Test name
Test status
Simulation time 4171091990 ps
CPU time 34.55 seconds
Started Jun 11 03:20:20 PM PDT 24
Finished Jun 11 03:20:56 PM PDT 24
Peak memory 211152 kb
Host smart-ce95eafe-406c-421d-b4cd-e6f6d8d8fca6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2772955532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2772955532
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1424016766
Short name T300
Test name
Test status
Simulation time 688827070 ps
CPU time 20.23 seconds
Started Jun 11 03:20:20 PM PDT 24
Finished Jun 11 03:20:42 PM PDT 24
Peak memory 216100 kb
Host smart-e0ecef14-3ecb-46c3-a179-4f7c18d6657e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424016766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1424016766
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.11634090
Short name T344
Test name
Test status
Simulation time 6057442628 ps
CPU time 24.24 seconds
Started Jun 11 03:20:19 PM PDT 24
Finished Jun 11 03:20:44 PM PDT 24
Peak memory 214348 kb
Host smart-55dd7760-2dc1-4446-acf5-ec57efc47997
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11634090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 46.rom_ctrl_stress_all.11634090
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.182631397
Short name T127
Test name
Test status
Simulation time 595468925 ps
CPU time 12.36 seconds
Started Jun 11 03:20:19 PM PDT 24
Finished Jun 11 03:20:32 PM PDT 24
Peak memory 216836 kb
Host smart-417700ed-28cf-4606-b081-5f9243f951ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182631397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.182631397
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.509299957
Short name T352
Test name
Test status
Simulation time 4146879379 ps
CPU time 140.47 seconds
Started Jun 11 03:20:19 PM PDT 24
Finished Jun 11 03:22:41 PM PDT 24
Peak memory 229452 kb
Host smart-e85f94d0-5f3f-4f2c-96ed-61954307fca8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509299957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.509299957
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1649451632
Short name T216
Test name
Test status
Simulation time 1321031924 ps
CPU time 18.81 seconds
Started Jun 11 03:20:19 PM PDT 24
Finished Jun 11 03:20:39 PM PDT 24
Peak memory 218960 kb
Host smart-811e0c7a-b85f-45ff-86ea-8ac81eb850b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649451632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1649451632
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.932131694
Short name T324
Test name
Test status
Simulation time 44213332785 ps
CPU time 32.99 seconds
Started Jun 11 03:20:20 PM PDT 24
Finished Jun 11 03:20:54 PM PDT 24
Peak memory 211740 kb
Host smart-2e00e016-17c2-4541-8c40-07fcb8776b09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=932131694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.932131694
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1815206339
Short name T87
Test name
Test status
Simulation time 702375409 ps
CPU time 20.64 seconds
Started Jun 11 03:20:20 PM PDT 24
Finished Jun 11 03:20:42 PM PDT 24
Peak memory 216696 kb
Host smart-d1553705-cef1-4736-ab69-097ce1d0b2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815206339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1815206339
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1610411655
Short name T289
Test name
Test status
Simulation time 7155806157 ps
CPU time 53.92 seconds
Started Jun 11 03:20:20 PM PDT 24
Finished Jun 11 03:21:16 PM PDT 24
Peak memory 219136 kb
Host smart-93717103-0425-4c5e-adb5-498881badec7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610411655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1610411655
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2085755211
Short name T14
Test name
Test status
Simulation time 42579544112 ps
CPU time 1735.03 seconds
Started Jun 11 03:20:20 PM PDT 24
Finished Jun 11 03:49:18 PM PDT 24
Peak memory 236320 kb
Host smart-9e2d3859-35be-4bc0-b66b-c46336a31573
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085755211 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2085755211
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1610910053
Short name T319
Test name
Test status
Simulation time 3629063754 ps
CPU time 29.33 seconds
Started Jun 11 03:20:30 PM PDT 24
Finished Jun 11 03:21:02 PM PDT 24
Peak memory 216936 kb
Host smart-fb1bf759-e708-480e-8300-2033c855167c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610910053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1610910053
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3253164818
Short name T252
Test name
Test status
Simulation time 3971026452 ps
CPU time 146.12 seconds
Started Jun 11 03:20:27 PM PDT 24
Finished Jun 11 03:22:56 PM PDT 24
Peak memory 224212 kb
Host smart-1bb8ddb5-5648-4d8c-abcf-2f1f01ef8149
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253164818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3253164818
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1128845613
Short name T341
Test name
Test status
Simulation time 16077148565 ps
CPU time 70.61 seconds
Started Jun 11 03:20:27 PM PDT 24
Finished Jun 11 03:21:40 PM PDT 24
Peak memory 219100 kb
Host smart-191e95c0-699c-480c-beca-b821d5d1a994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128845613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1128845613
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3256288152
Short name T74
Test name
Test status
Simulation time 1844230315 ps
CPU time 21.41 seconds
Started Jun 11 03:20:30 PM PDT 24
Finished Jun 11 03:20:54 PM PDT 24
Peak memory 219068 kb
Host smart-6a8ff485-b417-4db7-9141-a78a0ad8fdc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3256288152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3256288152
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1331898301
Short name T251
Test name
Test status
Simulation time 3071515499 ps
CPU time 43.55 seconds
Started Jun 11 03:20:29 PM PDT 24
Finished Jun 11 03:21:16 PM PDT 24
Peak memory 215900 kb
Host smart-8658f626-083c-41af-bf9d-ac2e10759778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331898301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1331898301
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3235759137
Short name T265
Test name
Test status
Simulation time 102978739649 ps
CPU time 257 seconds
Started Jun 11 03:20:27 PM PDT 24
Finished Jun 11 03:24:47 PM PDT 24
Peak memory 219132 kb
Host smart-1e7d7944-66b4-46c7-8b39-869130e41afa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235759137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3235759137
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2000695296
Short name T55
Test name
Test status
Simulation time 272466447445 ps
CPU time 2647.82 seconds
Started Jun 11 03:20:29 PM PDT 24
Finished Jun 11 04:04:41 PM PDT 24
Peak memory 251936 kb
Host smart-0ccd978b-438e-4231-bcc3-6d2ec4ffaeaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000695296 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2000695296
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1758849685
Short name T186
Test name
Test status
Simulation time 5206536348 ps
CPU time 29.32 seconds
Started Jun 11 03:20:29 PM PDT 24
Finished Jun 11 03:21:02 PM PDT 24
Peak memory 217264 kb
Host smart-055b86a8-937b-4c0a-9e58-2b762ccdb703
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758849685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1758849685
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2745399730
Short name T158
Test name
Test status
Simulation time 3751554065 ps
CPU time 261.79 seconds
Started Jun 11 03:20:27 PM PDT 24
Finished Jun 11 03:24:51 PM PDT 24
Peak memory 225240 kb
Host smart-1be55130-4e52-40aa-a344-e4d2341e3301
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745399730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2745399730
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.4019847639
Short name T148
Test name
Test status
Simulation time 14963612174 ps
CPU time 62.51 seconds
Started Jun 11 03:20:28 PM PDT 24
Finished Jun 11 03:21:33 PM PDT 24
Peak memory 219108 kb
Host smart-c865327e-149e-4a60-969c-2e070f777ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019847639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.4019847639
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1991099995
Short name T134
Test name
Test status
Simulation time 2427224162 ps
CPU time 24.65 seconds
Started Jun 11 03:20:31 PM PDT 24
Finished Jun 11 03:20:58 PM PDT 24
Peak memory 219108 kb
Host smart-1f215117-4ad2-407c-8236-3e3af20c39dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1991099995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1991099995
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3572441499
Short name T195
Test name
Test status
Simulation time 1729645985 ps
CPU time 33.46 seconds
Started Jun 11 03:20:29 PM PDT 24
Finished Jun 11 03:21:06 PM PDT 24
Peak memory 216164 kb
Host smart-6eb2c56c-9de5-44d1-9601-2d71e68a3f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572441499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3572441499
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1316748884
Short name T182
Test name
Test status
Simulation time 8371096343 ps
CPU time 79.75 seconds
Started Jun 11 03:20:29 PM PDT 24
Finished Jun 11 03:21:52 PM PDT 24
Peak memory 219096 kb
Host smart-2fb6f2cd-4963-4000-8ea5-8887b832429c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316748884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1316748884
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3894919728
Short name T325
Test name
Test status
Simulation time 1948363720 ps
CPU time 11.28 seconds
Started Jun 11 03:19:14 PM PDT 24
Finished Jun 11 03:19:26 PM PDT 24
Peak memory 216652 kb
Host smart-cdd1bff4-2ecc-4d03-a485-d2ea48606414
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894919728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3894919728
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2450971296
Short name T35
Test name
Test status
Simulation time 243940337759 ps
CPU time 602.45 seconds
Started Jun 11 03:19:19 PM PDT 24
Finished Jun 11 03:29:26 PM PDT 24
Peak memory 215580 kb
Host smart-462b46e2-6aac-44ab-be57-61952825566c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450971296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2450971296
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.684261059
Short name T166
Test name
Test status
Simulation time 806058112 ps
CPU time 19.43 seconds
Started Jun 11 03:19:16 PM PDT 24
Finished Jun 11 03:19:37 PM PDT 24
Peak memory 218996 kb
Host smart-7ec51add-855e-4a47-a8d2-c6e69324b460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684261059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.684261059
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2048898500
Short name T10
Test name
Test status
Simulation time 12730560658 ps
CPU time 28.41 seconds
Started Jun 11 03:19:16 PM PDT 24
Finished Jun 11 03:19:46 PM PDT 24
Peak memory 211832 kb
Host smart-9fb13f42-f94b-4c48-9efc-eb75a962aedb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2048898500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2048898500
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3547807212
Short name T298
Test name
Test status
Simulation time 15780479542 ps
CPU time 51.8 seconds
Started Jun 11 03:19:17 PM PDT 24
Finished Jun 11 03:20:12 PM PDT 24
Peak memory 216516 kb
Host smart-ad4e0ce8-4095-4821-b40e-e0901e483dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547807212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3547807212
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1250891554
Short name T192
Test name
Test status
Simulation time 32633194603 ps
CPU time 81.67 seconds
Started Jun 11 03:19:13 PM PDT 24
Finished Jun 11 03:20:36 PM PDT 24
Peak memory 219096 kb
Host smart-59fdd990-78c6-412b-b605-7a57dbc42da9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250891554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1250891554
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1772972173
Short name T36
Test name
Test status
Simulation time 2312968656 ps
CPU time 15.07 seconds
Started Jun 11 03:19:14 PM PDT 24
Finished Jun 11 03:19:30 PM PDT 24
Peak memory 216740 kb
Host smart-f74551dc-843c-464e-b001-66576f372f32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772972173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1772972173
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4030283643
Short name T144
Test name
Test status
Simulation time 1361876267 ps
CPU time 101.77 seconds
Started Jun 11 03:19:12 PM PDT 24
Finished Jun 11 03:20:55 PM PDT 24
Peak memory 242212 kb
Host smart-68747785-ad16-445b-bdb2-a4a66a248cca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030283643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.4030283643
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2378873271
Short name T194
Test name
Test status
Simulation time 14741302862 ps
CPU time 37.6 seconds
Started Jun 11 03:19:15 PM PDT 24
Finished Jun 11 03:19:54 PM PDT 24
Peak memory 218576 kb
Host smart-71e57e2f-6819-4e64-9fad-8cef4b4ce355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378873271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2378873271
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1449382136
Short name T139
Test name
Test status
Simulation time 2541018630 ps
CPU time 25.11 seconds
Started Jun 11 03:19:16 PM PDT 24
Finished Jun 11 03:19:43 PM PDT 24
Peak memory 211488 kb
Host smart-adb717da-ef33-412f-a18a-48751331ddff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1449382136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1449382136
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1275090550
Short name T248
Test name
Test status
Simulation time 12952628966 ps
CPU time 73.7 seconds
Started Jun 11 03:19:14 PM PDT 24
Finished Jun 11 03:20:29 PM PDT 24
Peak memory 215932 kb
Host smart-666b079d-ebe7-442b-be5c-4914bbf54836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275090550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1275090550
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3901620010
Short name T291
Test name
Test status
Simulation time 19327909333 ps
CPU time 213.83 seconds
Started Jun 11 03:19:18 PM PDT 24
Finished Jun 11 03:22:55 PM PDT 24
Peak memory 228112 kb
Host smart-8f492f65-3e79-4b3a-a781-fe4ae6b44dd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901620010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3901620010
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.527513980
Short name T160
Test name
Test status
Simulation time 822017185 ps
CPU time 13.75 seconds
Started Jun 11 03:19:20 PM PDT 24
Finished Jun 11 03:19:39 PM PDT 24
Peak memory 216700 kb
Host smart-d2ef1b20-e718-49de-a2b1-fc40037908b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527513980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.527513980
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2133360292
Short name T321
Test name
Test status
Simulation time 332309579 ps
CPU time 19.77 seconds
Started Jun 11 03:19:17 PM PDT 24
Finished Jun 11 03:19:40 PM PDT 24
Peak memory 218988 kb
Host smart-8c3f1334-9b9a-40dd-a742-a82d09c78a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133360292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2133360292
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3336076774
Short name T155
Test name
Test status
Simulation time 4193000801 ps
CPU time 33.15 seconds
Started Jun 11 03:19:22 PM PDT 24
Finished Jun 11 03:20:00 PM PDT 24
Peak memory 217492 kb
Host smart-c51bb667-f3ef-4103-b794-35d23c69fb07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3336076774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3336076774
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3057452766
Short name T126
Test name
Test status
Simulation time 1379413445 ps
CPU time 19.89 seconds
Started Jun 11 03:19:22 PM PDT 24
Finished Jun 11 03:19:46 PM PDT 24
Peak memory 216444 kb
Host smart-17a721cf-b021-4c80-a294-dc9e5a894884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057452766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3057452766
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2186213470
Short name T162
Test name
Test status
Simulation time 1442317497 ps
CPU time 24.8 seconds
Started Jun 11 03:19:13 PM PDT 24
Finished Jun 11 03:19:40 PM PDT 24
Peak memory 218848 kb
Host smart-43c7b444-7332-44df-93d3-a36f899ee0c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186213470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2186213470
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3940559691
Short name T236
Test name
Test status
Simulation time 3091162496 ps
CPU time 10.17 seconds
Started Jun 11 03:19:22 PM PDT 24
Finished Jun 11 03:19:37 PM PDT 24
Peak memory 216916 kb
Host smart-a0d0ffc7-3f9d-4525-b7af-69132046653a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940559691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3940559691
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.843300977
Short name T205
Test name
Test status
Simulation time 5414915499 ps
CPU time 176.46 seconds
Started Jun 11 03:19:24 PM PDT 24
Finished Jun 11 03:22:24 PM PDT 24
Peak memory 229680 kb
Host smart-d83eac0e-d9a8-4982-9f69-c8e0ee2c0c26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843300977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.843300977
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2596740825
Short name T26
Test name
Test status
Simulation time 12323655314 ps
CPU time 58.21 seconds
Started Jun 11 03:19:23 PM PDT 24
Finished Jun 11 03:20:25 PM PDT 24
Peak memory 219076 kb
Host smart-fc3e50cf-b555-4e74-a447-c64e728d96a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596740825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2596740825
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.873164551
Short name T9
Test name
Test status
Simulation time 215369392 ps
CPU time 10.41 seconds
Started Jun 11 03:19:19 PM PDT 24
Finished Jun 11 03:19:34 PM PDT 24
Peak memory 219040 kb
Host smart-c436bbc2-275b-4bbe-bc38-1e4007335d09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=873164551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.873164551
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3209451250
Short name T199
Test name
Test status
Simulation time 348790145 ps
CPU time 19.81 seconds
Started Jun 11 03:19:21 PM PDT 24
Finished Jun 11 03:19:46 PM PDT 24
Peak memory 215880 kb
Host smart-d8afc83f-b8c7-4879-85f1-f48deb56b6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209451250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3209451250
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2283198769
Short name T152
Test name
Test status
Simulation time 3383183337 ps
CPU time 65.65 seconds
Started Jun 11 03:19:20 PM PDT 24
Finished Jun 11 03:20:30 PM PDT 24
Peak memory 218892 kb
Host smart-50654a7f-fd84-4485-bac5-f8cdac7870bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283198769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2283198769
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2964073710
Short name T219
Test name
Test status
Simulation time 66963116819 ps
CPU time 35.04 seconds
Started Jun 11 03:19:25 PM PDT 24
Finished Jun 11 03:20:03 PM PDT 24
Peak memory 217148 kb
Host smart-72a5ce6d-1937-4f25-922b-83cd57ca3f97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964073710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2964073710
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.454926304
Short name T19
Test name
Test status
Simulation time 14268786526 ps
CPU time 284.88 seconds
Started Jun 11 03:19:24 PM PDT 24
Finished Jun 11 03:24:13 PM PDT 24
Peak memory 239024 kb
Host smart-1a765aa0-26bd-4c88-b882-df22e9e814d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454926304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.454926304
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2173080098
Short name T47
Test name
Test status
Simulation time 1320241277 ps
CPU time 19.35 seconds
Started Jun 11 03:19:24 PM PDT 24
Finished Jun 11 03:19:47 PM PDT 24
Peak memory 218912 kb
Host smart-87a5552f-baf3-4b57-ac7c-9f08989c9939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173080098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2173080098
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1606639953
Short name T203
Test name
Test status
Simulation time 3847125387 ps
CPU time 21.24 seconds
Started Jun 11 03:19:23 PM PDT 24
Finished Jun 11 03:19:49 PM PDT 24
Peak memory 217492 kb
Host smart-d6e9e293-0980-4310-b114-a64190c0a48b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1606639953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1606639953
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.973528425
Short name T85
Test name
Test status
Simulation time 345953687 ps
CPU time 19.94 seconds
Started Jun 11 03:19:24 PM PDT 24
Finished Jun 11 03:19:48 PM PDT 24
Peak memory 216380 kb
Host smart-d8d6dbc1-37f1-47d7-a1a1-285dc7a8564f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973528425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.973528425
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3557134293
Short name T269
Test name
Test status
Simulation time 5142228671 ps
CPU time 53.47 seconds
Started Jun 11 03:19:24 PM PDT 24
Finished Jun 11 03:20:21 PM PDT 24
Peak memory 217288 kb
Host smart-f42f2654-4542-4b3b-b2a5-6147e6a80d83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557134293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3557134293
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1730869451
Short name T52
Test name
Test status
Simulation time 141290758923 ps
CPU time 592.39 seconds
Started Jun 11 03:19:25 PM PDT 24
Finished Jun 11 03:29:21 PM PDT 24
Peak memory 235572 kb
Host smart-34e3189b-4947-4e53-9d36-87c0a81886d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730869451 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.1730869451
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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