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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.18 96.89 91.99 97.68 100.00 98.28 97.30 98.14


Total test records in report: 457
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T291 /workspace/coverage/default/4.rom_ctrl_smoke.3385288879 Jun 21 04:43:26 PM PDT 24 Jun 21 04:43:52 PM PDT 24 346602587 ps
T292 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1034642856 Jun 21 04:43:55 PM PDT 24 Jun 21 04:44:16 PM PDT 24 1321195697 ps
T293 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.256277097 Jun 21 04:44:12 PM PDT 24 Jun 21 04:47:46 PM PDT 24 2975970815 ps
T294 /workspace/coverage/default/22.rom_ctrl_stress_all.2507506229 Jun 21 04:43:24 PM PDT 24 Jun 21 04:43:48 PM PDT 24 229632681 ps
T295 /workspace/coverage/default/8.rom_ctrl_alert_test.1248231203 Jun 21 04:43:21 PM PDT 24 Jun 21 04:43:37 PM PDT 24 174317902 ps
T296 /workspace/coverage/default/18.rom_ctrl_smoke.39911094 Jun 21 04:43:23 PM PDT 24 Jun 21 04:44:21 PM PDT 24 26596756155 ps
T297 /workspace/coverage/default/24.rom_ctrl_smoke.3714744416 Jun 21 04:43:32 PM PDT 24 Jun 21 04:44:12 PM PDT 24 6957006626 ps
T298 /workspace/coverage/default/46.rom_ctrl_smoke.1718162574 Jun 21 04:44:06 PM PDT 24 Jun 21 04:45:09 PM PDT 24 26796840313 ps
T299 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.969140300 Jun 21 04:43:12 PM PDT 24 Jun 21 04:48:22 PM PDT 24 60609137205 ps
T46 /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.570217181 Jun 21 04:44:10 PM PDT 24 Jun 21 05:21:59 PM PDT 24 59579993907 ps
T300 /workspace/coverage/default/14.rom_ctrl_stress_all.2371479071 Jun 21 04:43:31 PM PDT 24 Jun 21 04:45:07 PM PDT 24 8620581843 ps
T301 /workspace/coverage/default/20.rom_ctrl_stress_all.3093156911 Jun 21 04:43:23 PM PDT 24 Jun 21 04:44:07 PM PDT 24 7945444047 ps
T302 /workspace/coverage/default/3.rom_ctrl_alert_test.2173026563 Jun 21 04:43:29 PM PDT 24 Jun 21 04:43:59 PM PDT 24 11115791214 ps
T303 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2814019503 Jun 21 04:43:57 PM PDT 24 Jun 21 04:44:10 PM PDT 24 180402600 ps
T304 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3617139043 Jun 21 04:44:06 PM PDT 24 Jun 21 04:44:19 PM PDT 24 182975624 ps
T305 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2360412663 Jun 21 04:43:25 PM PDT 24 Jun 21 04:57:40 PM PDT 24 96564586437 ps
T306 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3644686359 Jun 21 04:43:25 PM PDT 24 Jun 21 04:43:55 PM PDT 24 2611944522 ps
T307 /workspace/coverage/default/40.rom_ctrl_alert_test.3620926615 Jun 21 04:44:08 PM PDT 24 Jun 21 04:44:35 PM PDT 24 5696988781 ps
T308 /workspace/coverage/default/38.rom_ctrl_smoke.2058556036 Jun 21 04:43:57 PM PDT 24 Jun 21 04:44:38 PM PDT 24 2492948092 ps
T309 /workspace/coverage/default/15.rom_ctrl_stress_all.3957940307 Jun 21 04:43:33 PM PDT 24 Jun 21 04:45:32 PM PDT 24 11561067781 ps
T310 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3137557595 Jun 21 04:43:34 PM PDT 24 Jun 21 04:43:58 PM PDT 24 1974101546 ps
T311 /workspace/coverage/default/17.rom_ctrl_alert_test.1565851872 Jun 21 04:43:36 PM PDT 24 Jun 21 04:43:54 PM PDT 24 2576917179 ps
T312 /workspace/coverage/default/2.rom_ctrl_stress_all.2140214944 Jun 21 04:43:08 PM PDT 24 Jun 21 04:43:48 PM PDT 24 2130567774 ps
T313 /workspace/coverage/default/48.rom_ctrl_stress_all.653644797 Jun 21 04:44:05 PM PDT 24 Jun 21 04:45:22 PM PDT 24 6630260934 ps
T314 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2319927290 Jun 21 04:43:59 PM PDT 24 Jun 21 04:44:26 PM PDT 24 10386916571 ps
T315 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4258888446 Jun 21 04:43:58 PM PDT 24 Jun 21 04:44:19 PM PDT 24 349694675 ps
T316 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1117991922 Jun 21 04:43:26 PM PDT 24 Jun 21 04:44:26 PM PDT 24 5979819683 ps
T317 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2074883860 Jun 21 04:43:58 PM PDT 24 Jun 21 04:48:02 PM PDT 24 16034079313 ps
T318 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.842745953 Jun 21 04:43:26 PM PDT 24 Jun 21 04:43:42 PM PDT 24 707492172 ps
T319 /workspace/coverage/default/37.rom_ctrl_stress_all.1272221760 Jun 21 04:43:55 PM PDT 24 Jun 21 04:45:31 PM PDT 24 10017254225 ps
T320 /workspace/coverage/default/6.rom_ctrl_stress_all.1965406859 Jun 21 04:43:28 PM PDT 24 Jun 21 04:44:49 PM PDT 24 7981846587 ps
T321 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1570951399 Jun 21 04:43:22 PM PDT 24 Jun 21 04:53:25 PM PDT 24 521833945600 ps
T322 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1451036646 Jun 21 04:43:48 PM PDT 24 Jun 21 05:00:43 PM PDT 24 231373664436 ps
T323 /workspace/coverage/default/37.rom_ctrl_smoke.377819480 Jun 21 04:43:58 PM PDT 24 Jun 21 04:44:21 PM PDT 24 347849264 ps
T324 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3799909909 Jun 21 04:43:27 PM PDT 24 Jun 21 04:49:57 PM PDT 24 9943976341 ps
T325 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2513880119 Jun 21 04:43:37 PM PDT 24 Jun 21 04:44:00 PM PDT 24 18856144551 ps
T326 /workspace/coverage/default/19.rom_ctrl_stress_all.3361528107 Jun 21 04:43:41 PM PDT 24 Jun 21 04:44:03 PM PDT 24 1190208276 ps
T327 /workspace/coverage/default/47.rom_ctrl_stress_all.1614678738 Jun 21 04:44:07 PM PDT 24 Jun 21 04:44:47 PM PDT 24 2257284940 ps
T328 /workspace/coverage/default/3.rom_ctrl_stress_all.2809510669 Jun 21 04:43:25 PM PDT 24 Jun 21 04:44:33 PM PDT 24 30237144847 ps
T329 /workspace/coverage/default/29.rom_ctrl_smoke.2910478755 Jun 21 04:43:40 PM PDT 24 Jun 21 04:44:32 PM PDT 24 7194362051 ps
T330 /workspace/coverage/default/12.rom_ctrl_smoke.2990839354 Jun 21 04:43:38 PM PDT 24 Jun 21 04:44:09 PM PDT 24 1215164334 ps
T331 /workspace/coverage/default/19.rom_ctrl_alert_test.2221827468 Jun 21 04:43:32 PM PDT 24 Jun 21 04:44:00 PM PDT 24 5382911410 ps
T332 /workspace/coverage/default/42.rom_ctrl_stress_all.389725058 Jun 21 04:43:58 PM PDT 24 Jun 21 04:44:43 PM PDT 24 3603961483 ps
T333 /workspace/coverage/default/26.rom_ctrl_stress_all.2775270377 Jun 21 04:43:26 PM PDT 24 Jun 21 04:44:27 PM PDT 24 3554028614 ps
T334 /workspace/coverage/default/34.rom_ctrl_smoke.2894777826 Jun 21 04:43:46 PM PDT 24 Jun 21 04:44:12 PM PDT 24 706998042 ps
T335 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3182991523 Jun 21 04:43:21 PM PDT 24 Jun 21 04:43:46 PM PDT 24 1885976730 ps
T336 /workspace/coverage/default/28.rom_ctrl_stress_all.89060510 Jun 21 04:43:35 PM PDT 24 Jun 21 04:44:11 PM PDT 24 7561530505 ps
T337 /workspace/coverage/default/20.rom_ctrl_smoke.1479937478 Jun 21 04:43:22 PM PDT 24 Jun 21 04:44:24 PM PDT 24 43433447898 ps
T338 /workspace/coverage/default/8.rom_ctrl_stress_all.879810860 Jun 21 04:43:26 PM PDT 24 Jun 21 04:44:38 PM PDT 24 14998044272 ps
T339 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.686701407 Jun 21 04:43:37 PM PDT 24 Jun 21 04:44:00 PM PDT 24 2245600987 ps
T340 /workspace/coverage/default/14.rom_ctrl_smoke.2264767415 Jun 21 04:43:25 PM PDT 24 Jun 21 04:43:51 PM PDT 24 366201351 ps
T28 /workspace/coverage/default/2.rom_ctrl_sec_cm.3462936277 Jun 21 04:43:27 PM PDT 24 Jun 21 04:47:21 PM PDT 24 4878330180 ps
T341 /workspace/coverage/default/4.rom_ctrl_alert_test.1354192647 Jun 21 04:43:28 PM PDT 24 Jun 21 04:43:42 PM PDT 24 172434105 ps
T342 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2667053196 Jun 21 04:43:22 PM PDT 24 Jun 21 04:43:47 PM PDT 24 1375121400 ps
T343 /workspace/coverage/default/21.rom_ctrl_smoke.1920449681 Jun 21 04:43:29 PM PDT 24 Jun 21 04:44:56 PM PDT 24 16689681523 ps
T344 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3755703190 Jun 21 04:43:26 PM PDT 24 Jun 21 04:47:34 PM PDT 24 18863511279 ps
T345 /workspace/coverage/default/5.rom_ctrl_stress_all.3426539608 Jun 21 04:43:14 PM PDT 24 Jun 21 04:44:00 PM PDT 24 1873309432 ps
T346 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2029460855 Jun 21 04:43:19 PM PDT 24 Jun 21 04:51:36 PM PDT 24 64689702915 ps
T347 /workspace/coverage/default/45.rom_ctrl_alert_test.1896531539 Jun 21 04:44:04 PM PDT 24 Jun 21 04:44:28 PM PDT 24 8159404913 ps
T348 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.619653302 Jun 21 04:44:00 PM PDT 24 Jun 21 04:48:31 PM PDT 24 41992094062 ps
T349 /workspace/coverage/default/12.rom_ctrl_stress_all.4106974878 Jun 21 04:43:27 PM PDT 24 Jun 21 04:45:34 PM PDT 24 51083783532 ps
T350 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2216292220 Jun 21 04:43:34 PM PDT 24 Jun 21 04:51:48 PM PDT 24 138491390161 ps
T351 /workspace/coverage/default/27.rom_ctrl_smoke.3468929392 Jun 21 04:43:25 PM PDT 24 Jun 21 04:44:11 PM PDT 24 12493846685 ps
T54 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1002911151 Jun 21 04:44:05 PM PDT 24 Jun 21 04:44:52 PM PDT 24 1052469395 ps
T55 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3282754692 Jun 21 04:44:29 PM PDT 24 Jun 21 04:44:54 PM PDT 24 4818070518 ps
T56 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.384700406 Jun 21 04:44:16 PM PDT 24 Jun 21 04:44:42 PM PDT 24 2542850573 ps
T352 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4045360872 Jun 21 04:44:15 PM PDT 24 Jun 21 04:44:51 PM PDT 24 3501090890 ps
T353 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3220017312 Jun 21 04:44:10 PM PDT 24 Jun 21 04:44:33 PM PDT 24 1644785146 ps
T354 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3663769098 Jun 21 04:44:16 PM PDT 24 Jun 21 04:44:49 PM PDT 24 3727063087 ps
T64 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1514693246 Jun 21 04:44:21 PM PDT 24 Jun 21 04:44:56 PM PDT 24 11803027553 ps
T65 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.677120500 Jun 21 04:44:07 PM PDT 24 Jun 21 04:44:21 PM PDT 24 856901545 ps
T355 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2027052578 Jun 21 04:44:13 PM PDT 24 Jun 21 04:44:41 PM PDT 24 15990249414 ps
T51 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2764396451 Jun 21 04:44:17 PM PDT 24 Jun 21 04:45:58 PM PDT 24 2899445477 ps
T356 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1377843135 Jun 21 04:44:12 PM PDT 24 Jun 21 04:44:32 PM PDT 24 1359285317 ps
T357 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3561737471 Jun 21 04:44:14 PM PDT 24 Jun 21 04:44:52 PM PDT 24 4024125185 ps
T97 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.707288138 Jun 21 04:44:13 PM PDT 24 Jun 21 04:46:55 PM PDT 24 19230034738 ps
T66 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3805529149 Jun 21 04:44:17 PM PDT 24 Jun 21 04:45:54 PM PDT 24 38060541604 ps
T358 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1606084855 Jun 21 04:44:17 PM PDT 24 Jun 21 04:44:38 PM PDT 24 3020365755 ps
T359 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.277072524 Jun 21 04:44:20 PM PDT 24 Jun 21 04:45:02 PM PDT 24 16797489873 ps
T360 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.748886817 Jun 21 04:44:13 PM PDT 24 Jun 21 04:44:38 PM PDT 24 19069398717 ps
T361 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1109703695 Jun 21 04:44:16 PM PDT 24 Jun 21 04:44:44 PM PDT 24 8005934488 ps
T67 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.672602183 Jun 21 04:44:09 PM PDT 24 Jun 21 04:45:43 PM PDT 24 5511466297 ps
T68 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2603224650 Jun 21 04:44:16 PM PDT 24 Jun 21 04:44:39 PM PDT 24 4630026379 ps
T69 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.570781522 Jun 21 04:44:21 PM PDT 24 Jun 21 04:44:41 PM PDT 24 5329472045 ps
T70 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3764811884 Jun 21 04:44:14 PM PDT 24 Jun 21 04:45:55 PM PDT 24 23313437927 ps
T71 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4124087079 Jun 21 04:44:21 PM PDT 24 Jun 21 04:47:29 PM PDT 24 50184967611 ps
T362 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.287413133 Jun 21 04:44:16 PM PDT 24 Jun 21 04:44:52 PM PDT 24 8811237843 ps
T363 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1840569467 Jun 21 04:44:16 PM PDT 24 Jun 21 04:44:42 PM PDT 24 2225159151 ps
T364 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1591342445 Jun 21 04:44:14 PM PDT 24 Jun 21 04:44:33 PM PDT 24 1169148717 ps
T365 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3376867695 Jun 21 04:44:17 PM PDT 24 Jun 21 04:44:50 PM PDT 24 15390607541 ps
T366 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3691240550 Jun 21 04:44:16 PM PDT 24 Jun 21 04:44:28 PM PDT 24 185652876 ps
T88 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3345255171 Jun 21 04:44:29 PM PDT 24 Jun 21 04:44:39 PM PDT 24 216925861 ps
T367 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1943499358 Jun 21 04:44:17 PM PDT 24 Jun 21 04:44:33 PM PDT 24 1125624991 ps
T368 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1640928706 Jun 21 04:44:26 PM PDT 24 Jun 21 04:45:01 PM PDT 24 4303908629 ps
T52 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2709844292 Jun 21 04:44:07 PM PDT 24 Jun 21 04:45:35 PM PDT 24 3127234648 ps
T369 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.609125374 Jun 21 04:44:16 PM PDT 24 Jun 21 04:44:57 PM PDT 24 7917513803 ps
T370 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2170475643 Jun 21 04:44:14 PM PDT 24 Jun 21 04:44:45 PM PDT 24 13510372941 ps
T371 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3725061733 Jun 21 04:44:17 PM PDT 24 Jun 21 04:45:17 PM PDT 24 1038083375 ps
T53 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2674122469 Jun 21 04:44:21 PM PDT 24 Jun 21 04:45:59 PM PDT 24 9476231472 ps
T372 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1154805608 Jun 21 04:44:15 PM PDT 24 Jun 21 04:44:31 PM PDT 24 1079411579 ps
T373 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.910951559 Jun 21 04:44:13 PM PDT 24 Jun 21 04:44:34 PM PDT 24 1612012862 ps
T374 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1238735018 Jun 21 04:44:21 PM PDT 24 Jun 21 04:44:46 PM PDT 24 1524400303 ps
T375 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1008907933 Jun 21 04:44:03 PM PDT 24 Jun 21 04:44:13 PM PDT 24 174493032 ps
T376 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3606030790 Jun 21 04:44:15 PM PDT 24 Jun 21 04:44:34 PM PDT 24 1200991786 ps
T377 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2303690861 Jun 21 04:44:21 PM PDT 24 Jun 21 04:44:45 PM PDT 24 30071473744 ps
T378 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1469027584 Jun 21 04:44:09 PM PDT 24 Jun 21 04:44:21 PM PDT 24 352356835 ps
T379 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4203900750 Jun 21 04:44:03 PM PDT 24 Jun 21 04:44:28 PM PDT 24 2242577283 ps
T380 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1250596004 Jun 21 04:44:09 PM PDT 24 Jun 21 04:44:27 PM PDT 24 1287382390 ps
T98 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2627246546 Jun 21 04:44:18 PM PDT 24 Jun 21 04:47:07 PM PDT 24 2301499375 ps
T381 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.727285674 Jun 21 04:44:21 PM PDT 24 Jun 21 04:45:00 PM PDT 24 44728262959 ps
T382 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2993399599 Jun 21 04:44:09 PM PDT 24 Jun 21 04:44:22 PM PDT 24 2350677537 ps
T383 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1819732652 Jun 21 04:44:17 PM PDT 24 Jun 21 04:44:49 PM PDT 24 3400224187 ps
T384 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1679074168 Jun 21 04:44:10 PM PDT 24 Jun 21 04:44:44 PM PDT 24 4328776385 ps
T385 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.814601522 Jun 21 04:44:18 PM PDT 24 Jun 21 04:44:46 PM PDT 24 5236711147 ps
T386 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2156624566 Jun 21 04:44:12 PM PDT 24 Jun 21 04:44:26 PM PDT 24 1029159305 ps
T76 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3257677484 Jun 21 04:44:11 PM PDT 24 Jun 21 04:45:11 PM PDT 24 1087302314 ps
T387 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1248283882 Jun 21 04:44:09 PM PDT 24 Jun 21 04:44:37 PM PDT 24 10603541707 ps
T388 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.436371903 Jun 21 04:44:07 PM PDT 24 Jun 21 04:44:19 PM PDT 24 4935410846 ps
T389 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1160001813 Jun 21 04:44:21 PM PDT 24 Jun 21 04:44:37 PM PDT 24 175983802 ps
T390 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.87152934 Jun 21 04:44:09 PM PDT 24 Jun 21 04:44:44 PM PDT 24 31508010325 ps
T391 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1875376000 Jun 21 04:44:17 PM PDT 24 Jun 21 04:44:46 PM PDT 24 12169655014 ps
T392 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.507627477 Jun 21 04:44:14 PM PDT 24 Jun 21 04:44:28 PM PDT 24 5122903866 ps
T393 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.181370606 Jun 21 04:44:09 PM PDT 24 Jun 21 04:44:20 PM PDT 24 167353496 ps
T394 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.360401385 Jun 21 04:44:10 PM PDT 24 Jun 21 04:44:35 PM PDT 24 5342933919 ps
T395 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.517493519 Jun 21 04:44:09 PM PDT 24 Jun 21 04:44:22 PM PDT 24 696893480 ps
T396 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3980802273 Jun 21 04:44:16 PM PDT 24 Jun 21 04:44:54 PM PDT 24 7664113158 ps
T397 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1891101078 Jun 21 04:44:08 PM PDT 24 Jun 21 04:44:35 PM PDT 24 5935995138 ps
T77 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1833123905 Jun 21 04:44:40 PM PDT 24 Jun 21 04:45:59 PM PDT 24 26370616749 ps
T99 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2664108105 Jun 21 04:44:17 PM PDT 24 Jun 21 04:46:00 PM PDT 24 11354602645 ps
T398 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4208439140 Jun 21 04:44:07 PM PDT 24 Jun 21 04:44:18 PM PDT 24 2749579113 ps
T106 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3237923481 Jun 21 04:44:20 PM PDT 24 Jun 21 04:47:13 PM PDT 24 3398052057 ps
T78 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4229560310 Jun 21 04:44:13 PM PDT 24 Jun 21 04:44:44 PM PDT 24 8822472895 ps
T79 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2183732755 Jun 21 04:44:23 PM PDT 24 Jun 21 04:44:48 PM PDT 24 2154486746 ps
T80 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2610638087 Jun 21 04:44:17 PM PDT 24 Jun 21 04:44:29 PM PDT 24 332338310 ps
T399 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2317697159 Jun 21 04:44:16 PM PDT 24 Jun 21 04:46:07 PM PDT 24 8090060811 ps
T400 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3602848391 Jun 21 04:44:16 PM PDT 24 Jun 21 04:44:39 PM PDT 24 905674815 ps
T401 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1736695273 Jun 21 04:44:05 PM PDT 24 Jun 21 04:44:29 PM PDT 24 5624128454 ps
T402 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1989215947 Jun 21 04:44:15 PM PDT 24 Jun 21 04:44:41 PM PDT 24 2380062395 ps
T100 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1009131380 Jun 21 04:44:17 PM PDT 24 Jun 21 04:45:55 PM PDT 24 4123020760 ps
T403 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2533722707 Jun 21 04:44:21 PM PDT 24 Jun 21 04:44:37 PM PDT 24 206159162 ps
T81 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1888896042 Jun 21 04:44:17 PM PDT 24 Jun 21 04:44:35 PM PDT 24 3302774523 ps
T101 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1922577384 Jun 21 04:44:25 PM PDT 24 Jun 21 04:47:20 PM PDT 24 3900114008 ps
T404 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.909130966 Jun 21 04:44:12 PM PDT 24 Jun 21 04:44:23 PM PDT 24 826216827 ps
T82 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3084608601 Jun 21 04:44:16 PM PDT 24 Jun 21 04:44:28 PM PDT 24 211476431 ps
T405 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.779697720 Jun 21 04:44:18 PM PDT 24 Jun 21 04:44:52 PM PDT 24 12421102573 ps
T406 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3488590849 Jun 21 04:44:21 PM PDT 24 Jun 21 04:44:53 PM PDT 24 6234274243 ps
T407 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.211148911 Jun 21 04:44:09 PM PDT 24 Jun 21 04:44:29 PM PDT 24 5812550314 ps
T408 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1137727219 Jun 21 04:44:18 PM PDT 24 Jun 21 04:44:52 PM PDT 24 15700224525 ps
T409 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3351720380 Jun 21 04:44:15 PM PDT 24 Jun 21 04:44:53 PM PDT 24 34100472750 ps
T410 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1454678611 Jun 21 04:44:18 PM PDT 24 Jun 21 04:45:47 PM PDT 24 718289061 ps
T86 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4195086833 Jun 21 04:44:12 PM PDT 24 Jun 21 04:44:53 PM PDT 24 9229148343 ps
T411 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3975877785 Jun 21 04:44:13 PM PDT 24 Jun 21 04:44:24 PM PDT 24 3291350646 ps
T412 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3099721874 Jun 21 04:44:23 PM PDT 24 Jun 21 04:44:58 PM PDT 24 13325878343 ps
T102 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3307545150 Jun 21 04:44:14 PM PDT 24 Jun 21 04:47:02 PM PDT 24 3818658628 ps
T413 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1412654196 Jun 21 04:44:21 PM PDT 24 Jun 21 04:44:49 PM PDT 24 2309863309 ps
T83 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.437492006 Jun 21 04:44:07 PM PDT 24 Jun 21 04:45:01 PM PDT 24 8001308619 ps
T414 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3741221493 Jun 21 04:44:19 PM PDT 24 Jun 21 04:44:51 PM PDT 24 12412354681 ps
T415 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.21750980 Jun 21 04:44:17 PM PDT 24 Jun 21 04:44:31 PM PDT 24 189863146 ps
T416 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2692517074 Jun 21 04:44:21 PM PDT 24 Jun 21 04:44:40 PM PDT 24 1030262619 ps
T417 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3881949032 Jun 21 04:44:09 PM PDT 24 Jun 21 04:44:40 PM PDT 24 6993399004 ps
T418 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3194993864 Jun 21 04:44:17 PM PDT 24 Jun 21 04:44:54 PM PDT 24 3674786159 ps
T419 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2253060019 Jun 21 04:44:23 PM PDT 24 Jun 21 04:47:41 PM PDT 24 24129361887 ps
T420 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2902347609 Jun 21 04:44:05 PM PDT 24 Jun 21 04:44:40 PM PDT 24 11428242125 ps
T421 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.585517349 Jun 21 04:44:17 PM PDT 24 Jun 21 04:44:44 PM PDT 24 11632230753 ps
T422 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3168404227 Jun 21 04:44:22 PM PDT 24 Jun 21 04:45:24 PM PDT 24 3117499549 ps
T423 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3436693749 Jun 21 04:44:10 PM PDT 24 Jun 21 04:46:51 PM PDT 24 2820308881 ps
T424 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4130436846 Jun 21 04:44:18 PM PDT 24 Jun 21 04:44:39 PM PDT 24 2619817836 ps
T84 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2513560633 Jun 21 04:44:15 PM PDT 24 Jun 21 04:46:29 PM PDT 24 75947792678 ps
T85 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1405311945 Jun 21 04:44:07 PM PDT 24 Jun 21 04:47:02 PM PDT 24 19972343344 ps
T425 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3512972508 Jun 21 04:44:41 PM PDT 24 Jun 21 04:46:20 PM PDT 24 3190817419 ps
T426 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1801310111 Jun 21 04:44:15 PM PDT 24 Jun 21 04:44:48 PM PDT 24 25816491983 ps
T427 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3967201306 Jun 21 04:44:22 PM PDT 24 Jun 21 04:45:48 PM PDT 24 3719575345 ps
T428 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1686103561 Jun 21 04:44:10 PM PDT 24 Jun 21 04:44:28 PM PDT 24 826581442 ps
T429 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3416136684 Jun 21 04:44:16 PM PDT 24 Jun 21 04:44:40 PM PDT 24 2514820209 ps
T430 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.792779082 Jun 21 04:44:10 PM PDT 24 Jun 21 04:44:43 PM PDT 24 7414225096 ps
T431 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.986883107 Jun 21 04:44:16 PM PDT 24 Jun 21 04:44:28 PM PDT 24 870057975 ps
T432 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2072682261 Jun 21 04:44:21 PM PDT 24 Jun 21 04:44:47 PM PDT 24 4642815836 ps
T433 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1580123529 Jun 21 04:44:21 PM PDT 24 Jun 21 04:44:38 PM PDT 24 602577966 ps
T87 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.358840210 Jun 21 04:44:15 PM PDT 24 Jun 21 04:45:56 PM PDT 24 26776160475 ps
T434 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1660906471 Jun 21 04:44:21 PM PDT 24 Jun 21 04:44:34 PM PDT 24 751477859 ps
T435 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1433396678 Jun 21 04:44:08 PM PDT 24 Jun 21 04:44:35 PM PDT 24 6039820105 ps
T436 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4149292940 Jun 21 04:44:15 PM PDT 24 Jun 21 04:44:39 PM PDT 24 14095519202 ps
T437 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4209144476 Jun 21 04:44:10 PM PDT 24 Jun 21 04:44:25 PM PDT 24 1202226807 ps
T438 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.357158933 Jun 21 04:44:20 PM PDT 24 Jun 21 04:44:37 PM PDT 24 169245513 ps
T439 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3458707724 Jun 21 04:44:15 PM PDT 24 Jun 21 04:46:51 PM PDT 24 1203217146 ps
T440 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4092164872 Jun 21 04:44:24 PM PDT 24 Jun 21 04:44:59 PM PDT 24 16040036801 ps
T441 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.904518143 Jun 21 04:44:06 PM PDT 24 Jun 21 04:44:21 PM PDT 24 1377024638 ps
T442 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3137271003 Jun 21 04:44:34 PM PDT 24 Jun 21 04:45:08 PM PDT 24 4073171084 ps
T443 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2422098322 Jun 21 04:44:13 PM PDT 24 Jun 21 04:44:36 PM PDT 24 10390769967 ps
T444 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4224296272 Jun 21 04:44:21 PM PDT 24 Jun 21 04:44:51 PM PDT 24 5961808546 ps
T445 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2592798667 Jun 21 04:44:11 PM PDT 24 Jun 21 04:45:43 PM PDT 24 21530407256 ps
T446 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4070379454 Jun 21 04:44:09 PM PDT 24 Jun 21 04:44:47 PM PDT 24 4006766055 ps
T447 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2864867182 Jun 21 04:44:16 PM PDT 24 Jun 21 04:44:53 PM PDT 24 16701811366 ps
T107 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4073893441 Jun 21 04:44:14 PM PDT 24 Jun 21 04:47:16 PM PDT 24 4627682467 ps
T103 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.591599851 Jun 21 04:44:16 PM PDT 24 Jun 21 04:47:11 PM PDT 24 4134513707 ps
T448 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1388694820 Jun 21 04:44:09 PM PDT 24 Jun 21 04:44:29 PM PDT 24 3015517527 ps
T449 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.43364467 Jun 21 04:44:12 PM PDT 24 Jun 21 04:44:47 PM PDT 24 8216264866 ps
T450 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1163044896 Jun 21 04:44:15 PM PDT 24 Jun 21 04:44:47 PM PDT 24 4494999025 ps
T451 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1704567533 Jun 21 04:44:18 PM PDT 24 Jun 21 04:45:41 PM PDT 24 276719384 ps
T452 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1042481262 Jun 21 04:44:13 PM PDT 24 Jun 21 04:45:45 PM PDT 24 8913527137 ps
T453 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2197262099 Jun 21 04:44:16 PM PDT 24 Jun 21 04:45:56 PM PDT 24 10792468413 ps
T454 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3257784156 Jun 21 04:44:17 PM PDT 24 Jun 21 04:44:53 PM PDT 24 3491469514 ps
T455 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2640770251 Jun 21 04:44:16 PM PDT 24 Jun 21 04:44:38 PM PDT 24 1497485842 ps
T456 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.4130266468 Jun 21 04:44:16 PM PDT 24 Jun 21 04:45:44 PM PDT 24 8134053176 ps
T457 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1296995113 Jun 21 04:44:22 PM PDT 24 Jun 21 04:44:48 PM PDT 24 17878335974 ps
T104 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2919080634 Jun 21 04:44:15 PM PDT 24 Jun 21 04:46:51 PM PDT 24 665795933 ps
T105 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3541124971 Jun 21 04:44:11 PM PDT 24 Jun 21 04:45:37 PM PDT 24 1738583294 ps

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.660157953
Short name T2
Test name
Test status
Simulation time 26566852964 ps
CPU time 351.46 seconds
Started Jun 21 04:43:34 PM PDT 24
Finished Jun 21 04:49:27 PM PDT 24
Peak memory 241432 kb
Host smart-caa990eb-df11-4477-b6a1-5a95b1373887
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660157953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.660157953
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.43085204
Short name T12
Test name
Test status
Simulation time 317640148781 ps
CPU time 2458.09 seconds
Started Jun 21 04:43:44 PM PDT 24
Finished Jun 21 05:24:44 PM PDT 24
Peak memory 252008 kb
Host smart-bc60350a-ff53-43fa-bc02-c8ecea1a3152
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43085204 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.43085204
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.918850801
Short name T4
Test name
Test status
Simulation time 1717651545 ps
CPU time 25.11 seconds
Started Jun 21 04:44:09 PM PDT 24
Finished Jun 21 04:44:36 PM PDT 24
Peak memory 218340 kb
Host smart-780b67d2-8a37-4d59-ac74-451c30262224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918850801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.918850801
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2627246546
Short name T98
Test name
Test status
Simulation time 2301499375 ps
CPU time 164.45 seconds
Started Jun 21 04:44:18 PM PDT 24
Finished Jun 21 04:47:07 PM PDT 24
Peak memory 214524 kb
Host smart-3151bd72-9261-4900-88f0-a1effe180f1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627246546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2627246546
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2515536424
Short name T38
Test name
Test status
Simulation time 73432197889 ps
CPU time 737.75 seconds
Started Jun 21 04:43:59 PM PDT 24
Finished Jun 21 04:56:19 PM PDT 24
Peak memory 239392 kb
Host smart-121ac849-0baa-42d6-83e9-6026cef55a25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515536424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2515536424
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1009498849
Short name T15
Test name
Test status
Simulation time 14296319457 ps
CPU time 142.86 seconds
Started Jun 21 04:43:21 PM PDT 24
Finished Jun 21 04:45:47 PM PDT 24
Peak memory 219556 kb
Host smart-b013843b-1af5-4229-9ee7-f9a3de777117
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009498849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1009498849
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3921118382
Short name T6
Test name
Test status
Simulation time 26973072357 ps
CPU time 244.74 seconds
Started Jun 21 04:43:23 PM PDT 24
Finished Jun 21 04:47:32 PM PDT 24
Peak memory 235796 kb
Host smart-e7bbad65-efad-4659-8f25-90ff7772da1e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921118382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3921118382
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3805529149
Short name T66
Test name
Test status
Simulation time 38060541604 ps
CPU time 93.24 seconds
Started Jun 21 04:44:17 PM PDT 24
Finished Jun 21 04:45:54 PM PDT 24
Peak memory 219648 kb
Host smart-0840dd39-39e6-4247-a0ff-e3296b36f864
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805529149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3805529149
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3307545150
Short name T102
Test name
Test status
Simulation time 3818658628 ps
CPU time 165.94 seconds
Started Jun 21 04:44:14 PM PDT 24
Finished Jun 21 04:47:02 PM PDT 24
Peak memory 214388 kb
Host smart-df1b1b29-9824-4515-98d5-3f97a4563787
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307545150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3307545150
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.262516472
Short name T24
Test name
Test status
Simulation time 4435703248 ps
CPU time 21.93 seconds
Started Jun 21 04:43:21 PM PDT 24
Finished Jun 21 04:43:48 PM PDT 24
Peak memory 217312 kb
Host smart-7bda82f8-a7eb-4cd5-ba91-f374d0054014
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262516472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.262516472
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3640897028
Short name T124
Test name
Test status
Simulation time 342836419 ps
CPU time 19.34 seconds
Started Jun 21 04:43:39 PM PDT 24
Finished Jun 21 04:43:59 PM PDT 24
Peak memory 219072 kb
Host smart-fbf3d2ca-a088-4ac5-8bb5-a7589d7eacc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640897028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3640897028
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.484796923
Short name T74
Test name
Test status
Simulation time 1320634339 ps
CPU time 20.82 seconds
Started Jun 21 04:43:35 PM PDT 24
Finished Jun 21 04:43:58 PM PDT 24
Peak memory 216192 kb
Host smart-b3f95c97-0b80-4a09-ae64-065ca1626fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484796923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.484796923
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1002911151
Short name T54
Test name
Test status
Simulation time 1052469395 ps
CPU time 44.47 seconds
Started Jun 21 04:44:05 PM PDT 24
Finished Jun 21 04:44:52 PM PDT 24
Peak memory 211372 kb
Host smart-b272c84b-da25-4f62-9f20-1cc152750782
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002911151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1002911151
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3237923481
Short name T106
Test name
Test status
Simulation time 3398052057 ps
CPU time 168.18 seconds
Started Jun 21 04:44:20 PM PDT 24
Finished Jun 21 04:47:13 PM PDT 24
Peak memory 214584 kb
Host smart-108c6e10-6ff9-49eb-80d6-8a5899da15ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237923481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3237923481
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2674122469
Short name T53
Test name
Test status
Simulation time 9476231472 ps
CPU time 93.16 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:45:59 PM PDT 24
Peak memory 219444 kb
Host smart-65c0f410-77c5-4155-a845-d292265f11b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674122469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2674122469
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2919080634
Short name T104
Test name
Test status
Simulation time 665795933 ps
CPU time 154.2 seconds
Started Jun 21 04:44:15 PM PDT 24
Finished Jun 21 04:46:51 PM PDT 24
Peak memory 214680 kb
Host smart-0ad98d19-6783-4f2d-b58b-33739e7a3e82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919080634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2919080634
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3905804221
Short name T21
Test name
Test status
Simulation time 295756071 ps
CPU time 227.11 seconds
Started Jun 21 04:43:22 PM PDT 24
Finished Jun 21 04:47:13 PM PDT 24
Peak memory 235480 kb
Host smart-d6368359-5df4-41fe-b822-9051aeb6ed28
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905804221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3905804221
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.677120500
Short name T65
Test name
Test status
Simulation time 856901545 ps
CPU time 11.6 seconds
Started Jun 21 04:44:07 PM PDT 24
Finished Jun 21 04:44:21 PM PDT 24
Peak memory 211240 kb
Host smart-18c9054c-23cc-4ddb-b914-f21cb4f7a5b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677120500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.677120500
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4208439140
Short name T398
Test name
Test status
Simulation time 2749579113 ps
CPU time 8.72 seconds
Started Jun 21 04:44:07 PM PDT 24
Finished Jun 21 04:44:18 PM PDT 24
Peak memory 211464 kb
Host smart-fbd377ba-3ad4-4bf2-a1ad-28f8d34e4c70
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208439140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.4208439140
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4203900750
Short name T379
Test name
Test status
Simulation time 2242577283 ps
CPU time 22.89 seconds
Started Jun 21 04:44:03 PM PDT 24
Finished Jun 21 04:44:28 PM PDT 24
Peak memory 212580 kb
Host smart-9f07f3b1-289d-4e62-b8dc-960ceb1bae0f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203900750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.4203900750
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.904518143
Short name T441
Test name
Test status
Simulation time 1377024638 ps
CPU time 12.98 seconds
Started Jun 21 04:44:06 PM PDT 24
Finished Jun 21 04:44:21 PM PDT 24
Peak memory 215140 kb
Host smart-33aa9e2e-c077-404b-b8b8-3dd51a4e40dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904518143 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.904518143
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1008907933
Short name T375
Test name
Test status
Simulation time 174493032 ps
CPU time 8.29 seconds
Started Jun 21 04:44:03 PM PDT 24
Finished Jun 21 04:44:13 PM PDT 24
Peak memory 211224 kb
Host smart-1f9c2a6e-01aa-4c11-94da-b884d38b200d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008907933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1008907933
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1137727219
Short name T408
Test name
Test status
Simulation time 15700224525 ps
CPU time 30.19 seconds
Started Jun 21 04:44:18 PM PDT 24
Finished Jun 21 04:44:52 PM PDT 24
Peak memory 211524 kb
Host smart-89238d78-3b01-449a-a4ef-b4a0b8426e2d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137727219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1137727219
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.181370606
Short name T393
Test name
Test status
Simulation time 167353496 ps
CPU time 8.22 seconds
Started Jun 21 04:44:09 PM PDT 24
Finished Jun 21 04:44:20 PM PDT 24
Peak memory 211116 kb
Host smart-42611717-f59d-4770-917d-a663e6df62ff
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181370606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
181370606
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1405311945
Short name T85
Test name
Test status
Simulation time 19972343344 ps
CPU time 172.64 seconds
Started Jun 21 04:44:07 PM PDT 24
Finished Jun 21 04:47:02 PM PDT 24
Peak memory 215844 kb
Host smart-ab19aa33-02b6-4387-8e69-1ee47e65c621
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405311945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1405311945
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1679074168
Short name T384
Test name
Test status
Simulation time 4328776385 ps
CPU time 31.45 seconds
Started Jun 21 04:44:10 PM PDT 24
Finished Jun 21 04:44:44 PM PDT 24
Peak memory 213140 kb
Host smart-33405aad-727c-480f-84ce-622008d59144
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679074168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1679074168
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3220017312
Short name T353
Test name
Test status
Simulation time 1644785146 ps
CPU time 21.05 seconds
Started Jun 21 04:44:10 PM PDT 24
Finished Jun 21 04:44:33 PM PDT 24
Peak memory 217720 kb
Host smart-51c6479b-31b1-493e-bf04-1c9698e94b0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220017312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3220017312
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1704567533
Short name T451
Test name
Test status
Simulation time 276719384 ps
CPU time 78.89 seconds
Started Jun 21 04:44:18 PM PDT 24
Finished Jun 21 04:45:41 PM PDT 24
Peak memory 212872 kb
Host smart-b443e526-ed2d-40a7-b7b6-04947911dbe1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704567533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1704567533
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.909130966
Short name T404
Test name
Test status
Simulation time 826216827 ps
CPU time 8.02 seconds
Started Jun 21 04:44:12 PM PDT 24
Finished Jun 21 04:44:23 PM PDT 24
Peak memory 211240 kb
Host smart-1908ebd1-84a0-40aa-ad3e-e0febd477c01
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909130966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.909130966
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1891101078
Short name T397
Test name
Test status
Simulation time 5935995138 ps
CPU time 24.24 seconds
Started Jun 21 04:44:08 PM PDT 24
Finished Jun 21 04:44:35 PM PDT 24
Peak memory 212344 kb
Host smart-d960b9f8-ca2d-4e84-9ab6-335ca1a8336a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891101078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1891101078
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1686103561
Short name T428
Test name
Test status
Simulation time 826581442 ps
CPU time 14.79 seconds
Started Jun 21 04:44:10 PM PDT 24
Finished Jun 21 04:44:28 PM PDT 24
Peak memory 212196 kb
Host smart-f95c4d04-f6b5-4f95-96d8-cc1447156333
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686103561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1686103561
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.517493519
Short name T395
Test name
Test status
Simulation time 696893480 ps
CPU time 10.71 seconds
Started Jun 21 04:44:09 PM PDT 24
Finished Jun 21 04:44:22 PM PDT 24
Peak memory 219536 kb
Host smart-4f0edaab-9e48-463f-8f50-17ee7876e853
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517493519 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.517493519
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.211148911
Short name T407
Test name
Test status
Simulation time 5812550314 ps
CPU time 17.7 seconds
Started Jun 21 04:44:09 PM PDT 24
Finished Jun 21 04:44:29 PM PDT 24
Peak memory 212932 kb
Host smart-6905dc14-73eb-4d16-b5ce-802f5ae05678
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211148911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.211148911
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3881949032
Short name T417
Test name
Test status
Simulation time 6993399004 ps
CPU time 28 seconds
Started Jun 21 04:44:09 PM PDT 24
Finished Jun 21 04:44:40 PM PDT 24
Peak memory 211628 kb
Host smart-915281d5-85f9-4a01-8bba-29f36c9f970e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881949032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3881949032
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.748886817
Short name T360
Test name
Test status
Simulation time 19069398717 ps
CPU time 22.2 seconds
Started Jun 21 04:44:13 PM PDT 24
Finished Jun 21 04:44:38 PM PDT 24
Peak memory 211264 kb
Host smart-ed5c0016-af3f-4f87-866d-92946abafb3b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748886817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
748886817
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.672602183
Short name T67
Test name
Test status
Simulation time 5511466297 ps
CPU time 91.1 seconds
Started Jun 21 04:44:09 PM PDT 24
Finished Jun 21 04:45:43 PM PDT 24
Peak memory 215992 kb
Host smart-d47de33b-d48f-4dd2-9924-2003377cb4ab
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672602183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.672602183
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1250596004
Short name T380
Test name
Test status
Simulation time 1287382390 ps
CPU time 16.46 seconds
Started Jun 21 04:44:09 PM PDT 24
Finished Jun 21 04:44:27 PM PDT 24
Peak memory 211604 kb
Host smart-0d55a988-7b61-4bf2-8f47-0a9cef88d879
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250596004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1250596004
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.609125374
Short name T369
Test name
Test status
Simulation time 7917513803 ps
CPU time 36.58 seconds
Started Jun 21 04:44:16 PM PDT 24
Finished Jun 21 04:44:57 PM PDT 24
Peak memory 219212 kb
Host smart-592df8a0-7603-4ff7-85f2-ba00f063547f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609125374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.609125374
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2709844292
Short name T52
Test name
Test status
Simulation time 3127234648 ps
CPU time 86.27 seconds
Started Jun 21 04:44:07 PM PDT 24
Finished Jun 21 04:45:35 PM PDT 24
Peak memory 214328 kb
Host smart-4440095e-2841-466c-8552-10fd1e7371ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709844292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2709844292
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.21750980
Short name T415
Test name
Test status
Simulation time 189863146 ps
CPU time 9.12 seconds
Started Jun 21 04:44:17 PM PDT 24
Finished Jun 21 04:44:31 PM PDT 24
Peak memory 219556 kb
Host smart-de205354-bc61-4116-8dcf-7f0ac43f0f52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21750980 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.21750980
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3137271003
Short name T442
Test name
Test status
Simulation time 4073171084 ps
CPU time 32.83 seconds
Started Jun 21 04:44:34 PM PDT 24
Finished Jun 21 04:45:08 PM PDT 24
Peak memory 212552 kb
Host smart-a1deb73b-93a0-468f-b492-77c76b9dfcff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137271003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3137271003
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.570781522
Short name T69
Test name
Test status
Simulation time 5329472045 ps
CPU time 15.7 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:44:41 PM PDT 24
Peak memory 212152 kb
Host smart-7c27b30b-5fcc-4203-8373-460dcb6585c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570781522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.570781522
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2533722707
Short name T403
Test name
Test status
Simulation time 206159162 ps
CPU time 11.57 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:44:37 PM PDT 24
Peak memory 217764 kb
Host smart-9220985a-7835-4be1-857a-485567c6d572
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533722707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2533722707
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2197262099
Short name T453
Test name
Test status
Simulation time 10792468413 ps
CPU time 96.48 seconds
Started Jun 21 04:44:16 PM PDT 24
Finished Jun 21 04:45:56 PM PDT 24
Peak memory 214636 kb
Host smart-5671e05f-e74a-4abb-a3e1-69454308e2f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197262099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2197262099
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1296995113
Short name T457
Test name
Test status
Simulation time 17878335974 ps
CPU time 21.51 seconds
Started Jun 21 04:44:22 PM PDT 24
Finished Jun 21 04:44:48 PM PDT 24
Peak memory 216076 kb
Host smart-57f196e4-94fb-40d6-a6a1-185f69f7dfcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296995113 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1296995113
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.986883107
Short name T431
Test name
Test status
Simulation time 870057975 ps
CPU time 7.85 seconds
Started Jun 21 04:44:16 PM PDT 24
Finished Jun 21 04:44:28 PM PDT 24
Peak memory 211516 kb
Host smart-12819b4e-3527-4903-a8b7-341c59551505
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986883107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.986883107
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.358840210
Short name T87
Test name
Test status
Simulation time 26776160475 ps
CPU time 98.11 seconds
Started Jun 21 04:44:15 PM PDT 24
Finished Jun 21 04:45:56 PM PDT 24
Peak memory 212680 kb
Host smart-ea3396de-b44e-4f17-b2be-aed0f2dca68d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358840210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.358840210
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3488590849
Short name T406
Test name
Test status
Simulation time 6234274243 ps
CPU time 26.24 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:44:53 PM PDT 24
Peak memory 213060 kb
Host smart-8a7aeb72-d9a5-405b-9870-93a57b3dc641
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488590849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3488590849
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3561737471
Short name T357
Test name
Test status
Simulation time 4024125185 ps
CPU time 35.13 seconds
Started Jun 21 04:44:14 PM PDT 24
Finished Jun 21 04:44:52 PM PDT 24
Peak memory 218992 kb
Host smart-bbcad1d5-c2cc-4c0c-97b9-d15e07b91b10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561737471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3561737471
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2640770251
Short name T455
Test name
Test status
Simulation time 1497485842 ps
CPU time 17.9 seconds
Started Jun 21 04:44:16 PM PDT 24
Finished Jun 21 04:44:38 PM PDT 24
Peak memory 218104 kb
Host smart-a08a8aa2-5ae3-4bce-baf1-a48bcb73ab54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640770251 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2640770251
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1888896042
Short name T81
Test name
Test status
Simulation time 3302774523 ps
CPU time 13.54 seconds
Started Jun 21 04:44:17 PM PDT 24
Finished Jun 21 04:44:35 PM PDT 24
Peak memory 210068 kb
Host smart-390d1adf-1a32-48ea-bdc6-a119c57419e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888896042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1888896042
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.43364467
Short name T449
Test name
Test status
Simulation time 8216264866 ps
CPU time 32.12 seconds
Started Jun 21 04:44:12 PM PDT 24
Finished Jun 21 04:44:47 PM PDT 24
Peak memory 211420 kb
Host smart-93d36b40-904b-42fe-bee3-c62bcc57ddfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43364467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ct
rl_same_csr_outstanding.43364467
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.357158933
Short name T438
Test name
Test status
Simulation time 169245513 ps
CPU time 11.65 seconds
Started Jun 21 04:44:20 PM PDT 24
Finished Jun 21 04:44:37 PM PDT 24
Peak memory 219436 kb
Host smart-a1139c3a-5db8-4d04-b6d5-a1ed1f5d520d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357158933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.357158933
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3282754692
Short name T55
Test name
Test status
Simulation time 4818070518 ps
CPU time 22.78 seconds
Started Jun 21 04:44:29 PM PDT 24
Finished Jun 21 04:44:54 PM PDT 24
Peak memory 219772 kb
Host smart-4e29fab1-5569-4bf9-bd43-5bb61bb0cf51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282754692 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3282754692
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2170475643
Short name T370
Test name
Test status
Simulation time 13510372941 ps
CPU time 28.16 seconds
Started Jun 21 04:44:14 PM PDT 24
Finished Jun 21 04:44:45 PM PDT 24
Peak memory 212860 kb
Host smart-106bec24-3d44-453a-a3f5-fd50542e9246
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170475643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2170475643
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1833123905
Short name T77
Test name
Test status
Simulation time 26370616749 ps
CPU time 76.78 seconds
Started Jun 21 04:44:40 PM PDT 24
Finished Jun 21 04:45:59 PM PDT 24
Peak memory 219632 kb
Host smart-3dd9be12-bb2a-4748-933d-eac0ebbe0006
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833123905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1833123905
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3345255171
Short name T88
Test name
Test status
Simulation time 216925861 ps
CPU time 8.1 seconds
Started Jun 21 04:44:29 PM PDT 24
Finished Jun 21 04:44:39 PM PDT 24
Peak memory 211784 kb
Host smart-0696648f-53af-465c-bd94-44981b1eb26f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345255171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3345255171
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2902347609
Short name T420
Test name
Test status
Simulation time 11428242125 ps
CPU time 32.61 seconds
Started Jun 21 04:44:05 PM PDT 24
Finished Jun 21 04:44:40 PM PDT 24
Peak memory 218264 kb
Host smart-ee4209a4-1034-444b-9a74-b265907c6ee3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902347609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2902347609
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1009131380
Short name T100
Test name
Test status
Simulation time 4123020760 ps
CPU time 93.65 seconds
Started Jun 21 04:44:17 PM PDT 24
Finished Jun 21 04:45:55 PM PDT 24
Peak memory 212636 kb
Host smart-593bb9c3-d42f-4eb7-964e-485b0b0035f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009131380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1009131380
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1640928706
Short name T368
Test name
Test status
Simulation time 4303908629 ps
CPU time 32.14 seconds
Started Jun 21 04:44:26 PM PDT 24
Finished Jun 21 04:45:01 PM PDT 24
Peak memory 219204 kb
Host smart-fdc16396-027b-4f20-9980-0b621680cf9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640928706 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1640928706
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2183732755
Short name T79
Test name
Test status
Simulation time 2154486746 ps
CPU time 20.34 seconds
Started Jun 21 04:44:23 PM PDT 24
Finished Jun 21 04:44:48 PM PDT 24
Peak memory 212620 kb
Host smart-fca9dc62-9b6f-4b7e-822b-99709002dc20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183732755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2183732755
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2253060019
Short name T419
Test name
Test status
Simulation time 24129361887 ps
CPU time 193.94 seconds
Started Jun 21 04:44:23 PM PDT 24
Finished Jun 21 04:47:41 PM PDT 24
Peak memory 215552 kb
Host smart-0169333c-0727-4545-8500-cf8a97832ae4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253060019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2253060019
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4092164872
Short name T440
Test name
Test status
Simulation time 16040036801 ps
CPU time 30.36 seconds
Started Jun 21 04:44:24 PM PDT 24
Finished Jun 21 04:44:59 PM PDT 24
Peak memory 211248 kb
Host smart-e2230ae0-8831-4347-841e-92310ca635a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092164872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.4092164872
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3099721874
Short name T412
Test name
Test status
Simulation time 13325878343 ps
CPU time 31.3 seconds
Started Jun 21 04:44:23 PM PDT 24
Finished Jun 21 04:44:58 PM PDT 24
Peak memory 219324 kb
Host smart-f9580bcb-c5c0-41f1-9e21-041f1a36e677
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099721874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3099721874
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3512972508
Short name T425
Test name
Test status
Simulation time 3190817419 ps
CPU time 97.01 seconds
Started Jun 21 04:44:41 PM PDT 24
Finished Jun 21 04:46:20 PM PDT 24
Peak memory 213960 kb
Host smart-40adb69c-a887-4592-b58b-c7533ee1e366
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512972508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3512972508
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2422098322
Short name T443
Test name
Test status
Simulation time 10390769967 ps
CPU time 20.68 seconds
Started Jun 21 04:44:13 PM PDT 24
Finished Jun 21 04:44:36 PM PDT 24
Peak memory 217876 kb
Host smart-7d76caaf-dd44-4ad1-bb34-39148897620d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422098322 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2422098322
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3975877785
Short name T411
Test name
Test status
Simulation time 3291350646 ps
CPU time 8.58 seconds
Started Jun 21 04:44:13 PM PDT 24
Finished Jun 21 04:44:24 PM PDT 24
Peak memory 211864 kb
Host smart-53a99b9e-d28b-4a4e-aed0-87f797daf1b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975877785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3975877785
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3416136684
Short name T429
Test name
Test status
Simulation time 2514820209 ps
CPU time 19.62 seconds
Started Jun 21 04:44:16 PM PDT 24
Finished Jun 21 04:44:40 PM PDT 24
Peak memory 213044 kb
Host smart-c8acb356-0887-4fe4-a1f4-b0f39309f87b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416136684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3416136684
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.277072524
Short name T359
Test name
Test status
Simulation time 16797489873 ps
CPU time 36.55 seconds
Started Jun 21 04:44:20 PM PDT 24
Finished Jun 21 04:45:02 PM PDT 24
Peak memory 218508 kb
Host smart-1f04c534-1500-4221-9645-c185c1853419
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277072524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.277072524
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4073893441
Short name T107
Test name
Test status
Simulation time 4627682467 ps
CPU time 179.87 seconds
Started Jun 21 04:44:14 PM PDT 24
Finished Jun 21 04:47:16 PM PDT 24
Peak memory 214948 kb
Host smart-ba76a9a1-bcb3-44fb-ba92-5b30a789bebc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073893441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.4073893441
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1840569467
Short name T363
Test name
Test status
Simulation time 2225159151 ps
CPU time 22.07 seconds
Started Jun 21 04:44:16 PM PDT 24
Finished Jun 21 04:44:42 PM PDT 24
Peak memory 219624 kb
Host smart-2878b05d-5436-4b68-a727-9b42053d3f32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840569467 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1840569467
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1875376000
Short name T391
Test name
Test status
Simulation time 12169655014 ps
CPU time 24.62 seconds
Started Jun 21 04:44:17 PM PDT 24
Finished Jun 21 04:44:46 PM PDT 24
Peak memory 212884 kb
Host smart-0cca3746-7cf7-4b3e-8703-1c608509d44a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875376000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1875376000
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3257677484
Short name T76
Test name
Test status
Simulation time 1087302314 ps
CPU time 56.95 seconds
Started Jun 21 04:44:11 PM PDT 24
Finished Jun 21 04:45:11 PM PDT 24
Peak memory 215820 kb
Host smart-b6c493e1-9456-4943-a0d7-e07939852196
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257677484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3257677484
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.360401385
Short name T394
Test name
Test status
Simulation time 5342933919 ps
CPU time 22.53 seconds
Started Jun 21 04:44:10 PM PDT 24
Finished Jun 21 04:44:35 PM PDT 24
Peak memory 212996 kb
Host smart-7bf9f63f-8190-4e2c-ada4-61d3b8b16473
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360401385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.360401385
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3602848391
Short name T400
Test name
Test status
Simulation time 905674815 ps
CPU time 18.82 seconds
Started Jun 21 04:44:16 PM PDT 24
Finished Jun 21 04:44:39 PM PDT 24
Peak memory 217828 kb
Host smart-f75808f5-7477-42c8-885c-8dc0ad2f40b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602848391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3602848391
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3376867695
Short name T365
Test name
Test status
Simulation time 15390607541 ps
CPU time 27.43 seconds
Started Jun 21 04:44:17 PM PDT 24
Finished Jun 21 04:44:50 PM PDT 24
Peak memory 219652 kb
Host smart-c6acc258-4105-4d59-ac79-13ba6f7527f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376867695 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3376867695
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1660906471
Short name T434
Test name
Test status
Simulation time 751477859 ps
CPU time 8.35 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:44:34 PM PDT 24
Peak memory 211620 kb
Host smart-0b0bc012-0fdd-496e-b985-14b3d57e5c17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660906471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1660906471
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.707288138
Short name T97
Test name
Test status
Simulation time 19230034738 ps
CPU time 159.15 seconds
Started Jun 21 04:44:13 PM PDT 24
Finished Jun 21 04:46:55 PM PDT 24
Peak memory 215672 kb
Host smart-08da030b-287d-4a5f-bc00-0091df57db51
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707288138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.707288138
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2603224650
Short name T68
Test name
Test status
Simulation time 4630026379 ps
CPU time 19.41 seconds
Started Jun 21 04:44:16 PM PDT 24
Finished Jun 21 04:44:39 PM PDT 24
Peak memory 213356 kb
Host smart-6d962c59-d088-4b5e-9c5f-146aac96d5d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603224650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2603224650
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2692517074
Short name T416
Test name
Test status
Simulation time 1030262619 ps
CPU time 14.48 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:44:40 PM PDT 24
Peak memory 219032 kb
Host smart-25f150a4-5899-489b-b8e0-e67dabc16c83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692517074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2692517074
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1922577384
Short name T101
Test name
Test status
Simulation time 3900114008 ps
CPU time 171.41 seconds
Started Jun 21 04:44:25 PM PDT 24
Finished Jun 21 04:47:20 PM PDT 24
Peak memory 214512 kb
Host smart-ee3719aa-075d-4696-a66e-52b15e814cb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922577384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1922577384
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2027052578
Short name T355
Test name
Test status
Simulation time 15990249414 ps
CPU time 25.13 seconds
Started Jun 21 04:44:13 PM PDT 24
Finished Jun 21 04:44:41 PM PDT 24
Peak memory 217900 kb
Host smart-1f909d39-e26c-4e7c-a523-1e96a5196806
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027052578 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2027052578
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.910951559
Short name T373
Test name
Test status
Simulation time 1612012862 ps
CPU time 18.08 seconds
Started Jun 21 04:44:13 PM PDT 24
Finished Jun 21 04:44:34 PM PDT 24
Peak memory 212084 kb
Host smart-1286fa71-aed6-4a5d-a94f-cdc5eab825ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910951559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.910951559
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3725061733
Short name T371
Test name
Test status
Simulation time 1038083375 ps
CPU time 56.52 seconds
Started Jun 21 04:44:17 PM PDT 24
Finished Jun 21 04:45:17 PM PDT 24
Peak memory 214408 kb
Host smart-ab5c415f-bfa0-4d33-b068-826a4416488b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725061733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3725061733
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3980802273
Short name T396
Test name
Test status
Simulation time 7664113158 ps
CPU time 33.95 seconds
Started Jun 21 04:44:16 PM PDT 24
Finished Jun 21 04:44:54 PM PDT 24
Peak memory 213324 kb
Host smart-cf67372b-4041-4f52-99f1-31c76d7ea80f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980802273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3980802273
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4045360872
Short name T352
Test name
Test status
Simulation time 3501090890 ps
CPU time 32.69 seconds
Started Jun 21 04:44:15 PM PDT 24
Finished Jun 21 04:44:51 PM PDT 24
Peak memory 219644 kb
Host smart-01d6c6c3-2b40-4680-8dc5-d93d70a460bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045360872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.4045360872
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2592798667
Short name T445
Test name
Test status
Simulation time 21530407256 ps
CPU time 88.51 seconds
Started Jun 21 04:44:11 PM PDT 24
Finished Jun 21 04:45:43 PM PDT 24
Peak memory 214732 kb
Host smart-e89d1b12-aa2b-4458-acb0-5afa1d25623a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592798667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2592798667
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1412654196
Short name T413
Test name
Test status
Simulation time 2309863309 ps
CPU time 22.29 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:44:49 PM PDT 24
Peak memory 218284 kb
Host smart-7fb6d8ab-213b-4d14-ac25-b073b6bc2927
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412654196 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1412654196
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.287413133
Short name T362
Test name
Test status
Simulation time 8811237843 ps
CPU time 31.92 seconds
Started Jun 21 04:44:16 PM PDT 24
Finished Jun 21 04:44:52 PM PDT 24
Peak memory 212848 kb
Host smart-4ff16634-9932-4937-9e81-eb7369a40ab6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287413133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.287413133
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3967201306
Short name T427
Test name
Test status
Simulation time 3719575345 ps
CPU time 81.37 seconds
Started Jun 21 04:44:22 PM PDT 24
Finished Jun 21 04:45:48 PM PDT 24
Peak memory 216588 kb
Host smart-f35cf082-5745-4eef-b0c3-615870fb031c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967201306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3967201306
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.727285674
Short name T381
Test name
Test status
Simulation time 44728262959 ps
CPU time 34.15 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:45:00 PM PDT 24
Peak memory 213316 kb
Host smart-534ffe76-befd-474e-a197-3ee2aa8605d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727285674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.727285674
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3257784156
Short name T454
Test name
Test status
Simulation time 3491469514 ps
CPU time 32.12 seconds
Started Jun 21 04:44:17 PM PDT 24
Finished Jun 21 04:44:53 PM PDT 24
Peak memory 218964 kb
Host smart-712288ee-bebb-40db-8f5e-edca7e077bb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257784156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3257784156
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1388694820
Short name T448
Test name
Test status
Simulation time 3015517527 ps
CPU time 17.27 seconds
Started Jun 21 04:44:09 PM PDT 24
Finished Jun 21 04:44:29 PM PDT 24
Peak memory 212076 kb
Host smart-e2d949ca-13b2-45ae-a5d3-efc9f3a939e8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388694820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1388694820
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1377843135
Short name T356
Test name
Test status
Simulation time 1359285317 ps
CPU time 16.82 seconds
Started Jun 21 04:44:12 PM PDT 24
Finished Jun 21 04:44:32 PM PDT 24
Peak memory 211344 kb
Host smart-687d5007-bb56-4265-9701-1271b198e16d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377843135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1377843135
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4195086833
Short name T86
Test name
Test status
Simulation time 9229148343 ps
CPU time 38.27 seconds
Started Jun 21 04:44:12 PM PDT 24
Finished Jun 21 04:44:53 PM PDT 24
Peak memory 212588 kb
Host smart-6d33f8d9-3fcf-4061-9894-5da5bc64c291
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195086833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.4195086833
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1469027584
Short name T378
Test name
Test status
Simulation time 352356835 ps
CPU time 8.89 seconds
Started Jun 21 04:44:09 PM PDT 24
Finished Jun 21 04:44:21 PM PDT 24
Peak memory 215540 kb
Host smart-25aa55bd-4959-417d-b8b6-aef796d4603f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469027584 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1469027584
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2993399599
Short name T382
Test name
Test status
Simulation time 2350677537 ps
CPU time 10.67 seconds
Started Jun 21 04:44:09 PM PDT 24
Finished Jun 21 04:44:22 PM PDT 24
Peak memory 211532 kb
Host smart-8a5cb555-26fe-43ff-98f5-59e0d9e4df48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993399599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2993399599
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3606030790
Short name T376
Test name
Test status
Simulation time 1200991786 ps
CPU time 15.32 seconds
Started Jun 21 04:44:15 PM PDT 24
Finished Jun 21 04:44:34 PM PDT 24
Peak memory 211108 kb
Host smart-dc9e011c-8350-4a0e-b6f1-c492c8c06eeb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606030790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3606030790
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.87152934
Short name T390
Test name
Test status
Simulation time 31508010325 ps
CPU time 32.09 seconds
Started Jun 21 04:44:09 PM PDT 24
Finished Jun 21 04:44:44 PM PDT 24
Peak memory 211512 kb
Host smart-c15319a2-d873-4cf7-8849-120f0ca83bad
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87152934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.87152934
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.437492006
Short name T83
Test name
Test status
Simulation time 8001308619 ps
CPU time 52.2 seconds
Started Jun 21 04:44:07 PM PDT 24
Finished Jun 21 04:45:01 PM PDT 24
Peak memory 219596 kb
Host smart-66fb75d4-811f-48f0-966d-5b7f19bac3c1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437492006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.437492006
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1154805608
Short name T372
Test name
Test status
Simulation time 1079411579 ps
CPU time 13.56 seconds
Started Jun 21 04:44:15 PM PDT 24
Finished Jun 21 04:44:31 PM PDT 24
Peak memory 212920 kb
Host smart-3df4736a-4293-4bc7-96ab-4411444a2f48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154805608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1154805608
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1248283882
Short name T387
Test name
Test status
Simulation time 10603541707 ps
CPU time 24.93 seconds
Started Jun 21 04:44:09 PM PDT 24
Finished Jun 21 04:44:37 PM PDT 24
Peak memory 219540 kb
Host smart-33a45912-ce93-4c1d-a323-dec92374ed2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248283882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1248283882
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3436693749
Short name T423
Test name
Test status
Simulation time 2820308881 ps
CPU time 158.01 seconds
Started Jun 21 04:44:10 PM PDT 24
Finished Jun 21 04:46:51 PM PDT 24
Peak memory 213616 kb
Host smart-adbe00a6-809d-42e3-beb2-235b378a2dfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436693749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3436693749
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3084608601
Short name T82
Test name
Test status
Simulation time 211476431 ps
CPU time 8.23 seconds
Started Jun 21 04:44:16 PM PDT 24
Finished Jun 21 04:44:28 PM PDT 24
Peak memory 211304 kb
Host smart-e5609876-bcf8-43db-b99c-d0a6a134e110
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084608601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3084608601
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.436371903
Short name T388
Test name
Test status
Simulation time 4935410846 ps
CPU time 10.21 seconds
Started Jun 21 04:44:07 PM PDT 24
Finished Jun 21 04:44:19 PM PDT 24
Peak memory 211464 kb
Host smart-5da3aeb8-d6a4-4535-9f03-6e3f36d3156d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436371903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.436371903
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1989215947
Short name T402
Test name
Test status
Simulation time 2380062395 ps
CPU time 22.8 seconds
Started Jun 21 04:44:15 PM PDT 24
Finished Jun 21 04:44:41 PM PDT 24
Peak memory 212560 kb
Host smart-6073c5e8-24f7-43a7-9337-1666bb9f7689
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989215947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1989215947
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.792779082
Short name T430
Test name
Test status
Simulation time 7414225096 ps
CPU time 30.01 seconds
Started Jun 21 04:44:10 PM PDT 24
Finished Jun 21 04:44:43 PM PDT 24
Peak memory 218352 kb
Host smart-29cd27a5-6e75-46ef-8b6e-12a99c96792c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792779082 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.792779082
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4130436846
Short name T424
Test name
Test status
Simulation time 2619817836 ps
CPU time 16.69 seconds
Started Jun 21 04:44:18 PM PDT 24
Finished Jun 21 04:44:39 PM PDT 24
Peak memory 211476 kb
Host smart-9db62aa3-2fc9-494c-8bd7-70b4170fa6b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130436846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.4130436846
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2156624566
Short name T386
Test name
Test status
Simulation time 1029159305 ps
CPU time 11.09 seconds
Started Jun 21 04:44:12 PM PDT 24
Finished Jun 21 04:44:26 PM PDT 24
Peak memory 211152 kb
Host smart-56f756a5-70c4-4c5b-ab50-2b89e8657714
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156624566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2156624566
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4209144476
Short name T437
Test name
Test status
Simulation time 1202226807 ps
CPU time 11.8 seconds
Started Jun 21 04:44:10 PM PDT 24
Finished Jun 21 04:44:25 PM PDT 24
Peak memory 211144 kb
Host smart-3992b61d-0f61-45a6-8a29-ae0a3cafa4ad
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209144476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.4209144476
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1042481262
Short name T452
Test name
Test status
Simulation time 8913527137 ps
CPU time 89.18 seconds
Started Jun 21 04:44:13 PM PDT 24
Finished Jun 21 04:45:45 PM PDT 24
Peak memory 214044 kb
Host smart-d20fbac5-e0ad-479f-8de7-b907c7e4507b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042481262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1042481262
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.814601522
Short name T385
Test name
Test status
Simulation time 5236711147 ps
CPU time 23.24 seconds
Started Jun 21 04:44:18 PM PDT 24
Finished Jun 21 04:44:46 PM PDT 24
Peak memory 213396 kb
Host smart-74e56cd7-61d1-45d9-8df7-017213f077a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814601522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.814601522
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4070379454
Short name T446
Test name
Test status
Simulation time 4006766055 ps
CPU time 35.04 seconds
Started Jun 21 04:44:09 PM PDT 24
Finished Jun 21 04:44:47 PM PDT 24
Peak memory 217972 kb
Host smart-75aacfdd-3fad-444b-ab7f-82667a279162
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070379454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4070379454
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1454678611
Short name T410
Test name
Test status
Simulation time 718289061 ps
CPU time 84.5 seconds
Started Jun 21 04:44:18 PM PDT 24
Finished Jun 21 04:45:47 PM PDT 24
Peak memory 213844 kb
Host smart-ee0959d9-60fe-4c76-84ee-c16c0975701a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454678611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1454678611
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1238735018
Short name T374
Test name
Test status
Simulation time 1524400303 ps
CPU time 16.99 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:44:46 PM PDT 24
Peak memory 212416 kb
Host smart-8dd77ef7-d987-4a63-92a9-41f7f47e8d3d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238735018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1238735018
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3691240550
Short name T366
Test name
Test status
Simulation time 185652876 ps
CPU time 8.47 seconds
Started Jun 21 04:44:16 PM PDT 24
Finished Jun 21 04:44:28 PM PDT 24
Peak memory 211332 kb
Host smart-90e4b647-0d2c-4633-bc98-763a029708b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691240550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3691240550
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4229560310
Short name T78
Test name
Test status
Simulation time 8822472895 ps
CPU time 28.17 seconds
Started Jun 21 04:44:13 PM PDT 24
Finished Jun 21 04:44:44 PM PDT 24
Peak memory 212916 kb
Host smart-4070fbbb-34c8-4010-ae00-80733ea5ef03
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229560310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4229560310
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2303690861
Short name T377
Test name
Test status
Simulation time 30071473744 ps
CPU time 18.78 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:44:45 PM PDT 24
Peak memory 219612 kb
Host smart-0edbe21f-d453-489a-96c5-ebca6d6abdfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303690861 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2303690861
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3741221493
Short name T414
Test name
Test status
Simulation time 12412354681 ps
CPU time 26.56 seconds
Started Jun 21 04:44:19 PM PDT 24
Finished Jun 21 04:44:51 PM PDT 24
Peak memory 212736 kb
Host smart-1da77075-1598-49d9-8fc9-dc8938223d49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741221493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3741221493
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1606084855
Short name T358
Test name
Test status
Simulation time 3020365755 ps
CPU time 16.92 seconds
Started Jun 21 04:44:17 PM PDT 24
Finished Jun 21 04:44:38 PM PDT 24
Peak memory 210960 kb
Host smart-74558dd6-9b35-41df-ac5d-484123fe7b8e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606084855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1606084855
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1580123529
Short name T433
Test name
Test status
Simulation time 602577966 ps
CPU time 12.07 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:44:38 PM PDT 24
Peak memory 211136 kb
Host smart-bb9fa9d6-b11b-4b92-b1cd-8090ffe41d14
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580123529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1580123529
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.4130266468
Short name T456
Test name
Test status
Simulation time 8134053176 ps
CPU time 84.34 seconds
Started Jun 21 04:44:16 PM PDT 24
Finished Jun 21 04:45:44 PM PDT 24
Peak memory 216596 kb
Host smart-fa9ed268-f4bf-4200-838d-2da4545b3b20
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130266468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.4130266468
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.585517349
Short name T421
Test name
Test status
Simulation time 11632230753 ps
CPU time 22.7 seconds
Started Jun 21 04:44:17 PM PDT 24
Finished Jun 21 04:44:44 PM PDT 24
Peak memory 213336 kb
Host smart-49977752-8086-46e6-83cc-33fcaefc2557
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585517349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.585517349
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1160001813
Short name T389
Test name
Test status
Simulation time 175983802 ps
CPU time 11.02 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:44:37 PM PDT 24
Peak memory 219440 kb
Host smart-1ef70e29-bd3f-48a5-8390-b8547fd66f00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160001813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1160001813
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3458707724
Short name T439
Test name
Test status
Simulation time 1203217146 ps
CPU time 153.09 seconds
Started Jun 21 04:44:15 PM PDT 24
Finished Jun 21 04:46:51 PM PDT 24
Peak memory 219472 kb
Host smart-acaded04-b667-4672-8a15-1537da33a161
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458707724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3458707724
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1591342445
Short name T364
Test name
Test status
Simulation time 1169148717 ps
CPU time 16.39 seconds
Started Jun 21 04:44:14 PM PDT 24
Finished Jun 21 04:44:33 PM PDT 24
Peak memory 217768 kb
Host smart-42756f7d-9a15-4994-b76b-2c7050984c7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591342445 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1591342445
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2610638087
Short name T80
Test name
Test status
Simulation time 332338310 ps
CPU time 8.13 seconds
Started Jun 21 04:44:17 PM PDT 24
Finished Jun 21 04:44:29 PM PDT 24
Peak memory 211460 kb
Host smart-2fada5ad-4d1e-45be-a870-22703ddd1f9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610638087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2610638087
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4124087079
Short name T71
Test name
Test status
Simulation time 50184967611 ps
CPU time 183.61 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:47:29 PM PDT 24
Peak memory 215572 kb
Host smart-e7c0a843-8c3a-4824-99b0-5ed3b305500f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124087079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4124087079
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.507627477
Short name T392
Test name
Test status
Simulation time 5122903866 ps
CPU time 11.47 seconds
Started Jun 21 04:44:14 PM PDT 24
Finished Jun 21 04:44:28 PM PDT 24
Peak memory 212116 kb
Host smart-b64534d0-3977-4325-89dd-d3c938ae89b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507627477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.507627477
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3351720380
Short name T409
Test name
Test status
Simulation time 34100472750 ps
CPU time 34.91 seconds
Started Jun 21 04:44:15 PM PDT 24
Finished Jun 21 04:44:53 PM PDT 24
Peak memory 218876 kb
Host smart-f4ecada8-8a25-45ce-b631-4443034ddd6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351720380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3351720380
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3663769098
Short name T354
Test name
Test status
Simulation time 3727063087 ps
CPU time 29.43 seconds
Started Jun 21 04:44:16 PM PDT 24
Finished Jun 21 04:44:49 PM PDT 24
Peak memory 215076 kb
Host smart-8d0d92dc-c10a-4ff5-8bf1-69458b411dc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663769098 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3663769098
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4224296272
Short name T444
Test name
Test status
Simulation time 5961808546 ps
CPU time 25.28 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:44:51 PM PDT 24
Peak memory 212412 kb
Host smart-5a89c40e-13cf-4133-845f-99f9522e781a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224296272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.4224296272
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2513560633
Short name T84
Test name
Test status
Simulation time 75947792678 ps
CPU time 131.54 seconds
Started Jun 21 04:44:15 PM PDT 24
Finished Jun 21 04:46:29 PM PDT 24
Peak memory 219716 kb
Host smart-f504aec9-929c-4671-a6ec-565ec40b6c92
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513560633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2513560633
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1163044896
Short name T450
Test name
Test status
Simulation time 4494999025 ps
CPU time 28.31 seconds
Started Jun 21 04:44:15 PM PDT 24
Finished Jun 21 04:44:47 PM PDT 24
Peak memory 213424 kb
Host smart-54353142-6451-4fce-a6c3-c630d4bd9902
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163044896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1163044896
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3194993864
Short name T418
Test name
Test status
Simulation time 3674786159 ps
CPU time 32.64 seconds
Started Jun 21 04:44:17 PM PDT 24
Finished Jun 21 04:44:54 PM PDT 24
Peak memory 219096 kb
Host smart-aa889f46-7f14-4dc4-850f-af81a1649145
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194993864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3194993864
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3541124971
Short name T105
Test name
Test status
Simulation time 1738583294 ps
CPU time 82.81 seconds
Started Jun 21 04:44:11 PM PDT 24
Finished Jun 21 04:45:37 PM PDT 24
Peak memory 214280 kb
Host smart-cc3208fc-8f89-4178-adad-417ad7dae844
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541124971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3541124971
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1109703695
Short name T361
Test name
Test status
Simulation time 8005934488 ps
CPU time 25.39 seconds
Started Jun 21 04:44:16 PM PDT 24
Finished Jun 21 04:44:44 PM PDT 24
Peak memory 218172 kb
Host smart-f5990c9e-2769-4617-a8b6-8d6984db2528
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109703695 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1109703695
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2072682261
Short name T432
Test name
Test status
Simulation time 4642815836 ps
CPU time 20.53 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:44:47 PM PDT 24
Peak memory 212988 kb
Host smart-5c700bcf-c6a2-4c72-ac5e-9f96d9123468
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072682261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2072682261
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3764811884
Short name T70
Test name
Test status
Simulation time 23313437927 ps
CPU time 98.24 seconds
Started Jun 21 04:44:14 PM PDT 24
Finished Jun 21 04:45:55 PM PDT 24
Peak memory 219248 kb
Host smart-65e7918f-ba30-4788-a8c8-62c1aac32c48
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764811884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3764811884
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1514693246
Short name T64
Test name
Test status
Simulation time 11803027553 ps
CPU time 29.25 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:44:56 PM PDT 24
Peak memory 213212 kb
Host smart-28e5e886-17ef-4b6a-b396-0a3efc4eb58f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514693246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1514693246
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2864867182
Short name T447
Test name
Test status
Simulation time 16701811366 ps
CPU time 33.25 seconds
Started Jun 21 04:44:16 PM PDT 24
Finished Jun 21 04:44:53 PM PDT 24
Peak memory 219572 kb
Host smart-b0d817eb-ca0a-4f18-990f-a401b697c5a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864867182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2864867182
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2664108105
Short name T99
Test name
Test status
Simulation time 11354602645 ps
CPU time 98.33 seconds
Started Jun 21 04:44:17 PM PDT 24
Finished Jun 21 04:46:00 PM PDT 24
Peak memory 214600 kb
Host smart-1c4a7b1e-379a-458d-a159-453f37b1d303
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664108105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2664108105
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1801310111
Short name T426
Test name
Test status
Simulation time 25816491983 ps
CPU time 28.98 seconds
Started Jun 21 04:44:15 PM PDT 24
Finished Jun 21 04:44:48 PM PDT 24
Peak memory 216076 kb
Host smart-a024469f-bc5a-43ad-aaf3-76779ce90b6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801310111 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1801310111
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1433396678
Short name T435
Test name
Test status
Simulation time 6039820105 ps
CPU time 24.84 seconds
Started Jun 21 04:44:08 PM PDT 24
Finished Jun 21 04:44:35 PM PDT 24
Peak memory 212124 kb
Host smart-d3824dae-ecb2-46a7-9dec-49d9a21a3b2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433396678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1433396678
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2317697159
Short name T399
Test name
Test status
Simulation time 8090060811 ps
CPU time 106.97 seconds
Started Jun 21 04:44:16 PM PDT 24
Finished Jun 21 04:46:07 PM PDT 24
Peak memory 215956 kb
Host smart-79b4485d-703a-4361-89dd-cc1a4f005a58
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317697159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2317697159
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.384700406
Short name T56
Test name
Test status
Simulation time 2542850573 ps
CPU time 22.8 seconds
Started Jun 21 04:44:16 PM PDT 24
Finished Jun 21 04:44:42 PM PDT 24
Peak memory 213008 kb
Host smart-fc1a08e6-2cea-4cd4-b090-63382324ef17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384700406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.384700406
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.779697720
Short name T405
Test name
Test status
Simulation time 12421102573 ps
CPU time 29.71 seconds
Started Jun 21 04:44:18 PM PDT 24
Finished Jun 21 04:44:52 PM PDT 24
Peak memory 219564 kb
Host smart-c1753ade-e482-46c8-8fcf-7ff9aeb54c89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779697720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.779697720
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2764396451
Short name T51
Test name
Test status
Simulation time 2899445477 ps
CPU time 97.48 seconds
Started Jun 21 04:44:17 PM PDT 24
Finished Jun 21 04:45:58 PM PDT 24
Peak memory 214424 kb
Host smart-7cdc2d87-242e-47cb-b58b-94665d44e1cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764396451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2764396451
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4149292940
Short name T436
Test name
Test status
Simulation time 14095519202 ps
CPU time 20.44 seconds
Started Jun 21 04:44:15 PM PDT 24
Finished Jun 21 04:44:39 PM PDT 24
Peak memory 218048 kb
Host smart-a7cc521b-8773-4de8-951d-9898510deac9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149292940 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.4149292940
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1819732652
Short name T383
Test name
Test status
Simulation time 3400224187 ps
CPU time 27.87 seconds
Started Jun 21 04:44:17 PM PDT 24
Finished Jun 21 04:44:49 PM PDT 24
Peak memory 211996 kb
Host smart-93632982-33e4-45bb-ad34-daa9b581a673
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819732652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1819732652
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3168404227
Short name T422
Test name
Test status
Simulation time 3117499549 ps
CPU time 57.59 seconds
Started Jun 21 04:44:22 PM PDT 24
Finished Jun 21 04:45:24 PM PDT 24
Peak memory 214620 kb
Host smart-5ba7f612-b9a1-4dc0-9352-7c6b28dd6370
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168404227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3168404227
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1943499358
Short name T367
Test name
Test status
Simulation time 1125624991 ps
CPU time 11.6 seconds
Started Jun 21 04:44:17 PM PDT 24
Finished Jun 21 04:44:33 PM PDT 24
Peak memory 213064 kb
Host smart-0e00f45b-3ee9-42ab-84d7-aab8d2547532
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943499358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1943499358
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1736695273
Short name T401
Test name
Test status
Simulation time 5624128454 ps
CPU time 22.1 seconds
Started Jun 21 04:44:05 PM PDT 24
Finished Jun 21 04:44:29 PM PDT 24
Peak memory 218160 kb
Host smart-aabeb944-28dd-48c0-a7d7-70a3fbec5488
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736695273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1736695273
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.591599851
Short name T103
Test name
Test status
Simulation time 4134513707 ps
CPU time 171.3 seconds
Started Jun 21 04:44:16 PM PDT 24
Finished Jun 21 04:47:11 PM PDT 24
Peak memory 219632 kb
Host smart-5b89115b-0637-4ad5-8d84-feade1cf9ec4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591599851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.591599851
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3856915440
Short name T184
Test name
Test status
Simulation time 9052195685 ps
CPU time 19.7 seconds
Started Jun 21 04:43:27 PM PDT 24
Finished Jun 21 04:43:52 PM PDT 24
Peak memory 217084 kb
Host smart-a32ae22c-be10-40a0-816b-5233fcacac4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856915440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3856915440
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1570951399
Short name T321
Test name
Test status
Simulation time 521833945600 ps
CPU time 598.51 seconds
Started Jun 21 04:43:22 PM PDT 24
Finished Jun 21 04:53:25 PM PDT 24
Peak memory 226056 kb
Host smart-d177f684-f5c9-41ec-8100-72cfb968d083
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570951399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1570951399
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.931891959
Short name T161
Test name
Test status
Simulation time 1223968046 ps
CPU time 19.38 seconds
Started Jun 21 04:43:05 PM PDT 24
Finished Jun 21 04:43:27 PM PDT 24
Peak memory 219056 kb
Host smart-2dc3dd63-09c2-43af-9644-cdc235c00bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931891959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.931891959
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.4137185909
Short name T155
Test name
Test status
Simulation time 3675580435 ps
CPU time 31.01 seconds
Started Jun 21 04:43:24 PM PDT 24
Finished Jun 21 04:44:00 PM PDT 24
Peak memory 219156 kb
Host smart-40d4235a-cd64-44d6-bd1e-d00a564aab5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4137185909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.4137185909
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1700858738
Short name T139
Test name
Test status
Simulation time 8472479716 ps
CPU time 67.49 seconds
Started Jun 21 04:43:26 PM PDT 24
Finished Jun 21 04:44:39 PM PDT 24
Peak memory 216544 kb
Host smart-a9b7591e-30c3-498d-84a7-61a996de5308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700858738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1700858738
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1917908307
Short name T16
Test name
Test status
Simulation time 19951527278 ps
CPU time 66.96 seconds
Started Jun 21 04:43:05 PM PDT 24
Finished Jun 21 04:44:15 PM PDT 24
Peak memory 219032 kb
Host smart-183e48a3-3256-44c5-8e52-ee7bbdf7bea2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917908307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1917908307
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1897676547
Short name T153
Test name
Test status
Simulation time 12901811945 ps
CPU time 25.12 seconds
Started Jun 21 04:43:22 PM PDT 24
Finished Jun 21 04:43:51 PM PDT 24
Peak memory 217308 kb
Host smart-ec8879e6-a0c2-4828-91d6-1083177aa923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897676547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1897676547
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.45523894
Short name T127
Test name
Test status
Simulation time 117784235888 ps
CPU time 326.32 seconds
Started Jun 21 04:43:42 PM PDT 24
Finished Jun 21 04:49:09 PM PDT 24
Peak memory 219324 kb
Host smart-858a02a3-169a-4c44-9dfe-01f67dc55caa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45523894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_cor
rupt_sig_fatal_chk.45523894
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1117991922
Short name T316
Test name
Test status
Simulation time 5979819683 ps
CPU time 54.41 seconds
Started Jun 21 04:43:26 PM PDT 24
Finished Jun 21 04:44:26 PM PDT 24
Peak memory 219104 kb
Host smart-c68424e2-6a74-4a9a-83e4-34f992783169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117991922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1117991922
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1244413906
Short name T264
Test name
Test status
Simulation time 616089548 ps
CPU time 14.24 seconds
Started Jun 21 04:43:25 PM PDT 24
Finished Jun 21 04:43:48 PM PDT 24
Peak memory 217172 kb
Host smart-2354f611-2988-4afd-ab32-8f0478fd58e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1244413906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1244413906
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.546402123
Short name T75
Test name
Test status
Simulation time 1430835762 ps
CPU time 20.65 seconds
Started Jun 21 04:43:24 PM PDT 24
Finished Jun 21 04:43:50 PM PDT 24
Peak memory 215696 kb
Host smart-3ec13d9f-8ee5-4f22-99b3-822029b4f6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546402123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.546402123
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3463719897
Short name T194
Test name
Test status
Simulation time 753169728 ps
CPU time 41.59 seconds
Started Jun 21 04:43:14 PM PDT 24
Finished Jun 21 04:44:00 PM PDT 24
Peak memory 219080 kb
Host smart-5b2be00b-e95e-4d87-ade9-19c306208749
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463719897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3463719897
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.187043462
Short name T226
Test name
Test status
Simulation time 3862591195 ps
CPU time 29.85 seconds
Started Jun 21 04:43:21 PM PDT 24
Finished Jun 21 04:43:55 PM PDT 24
Peak memory 216968 kb
Host smart-cd2d8454-f484-4cfe-b4f4-65d301ded526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187043462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.187043462
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2365376179
Short name T32
Test name
Test status
Simulation time 13788004873 ps
CPU time 261.88 seconds
Started Jun 21 04:43:23 PM PDT 24
Finished Jun 21 04:47:49 PM PDT 24
Peak memory 240340 kb
Host smart-8eac7d55-ee1c-4994-a727-40010e7826fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365376179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2365376179
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2859723399
Short name T91
Test name
Test status
Simulation time 77813731397 ps
CPU time 69.07 seconds
Started Jun 21 04:43:27 PM PDT 24
Finished Jun 21 04:44:41 PM PDT 24
Peak memory 219120 kb
Host smart-02cd3e35-4c73-4798-bc29-04525ded9d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859723399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2859723399
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3928899336
Short name T268
Test name
Test status
Simulation time 10661394681 ps
CPU time 25.54 seconds
Started Jun 21 04:43:23 PM PDT 24
Finished Jun 21 04:43:53 PM PDT 24
Peak memory 219196 kb
Host smart-9a89763d-c033-4b2b-a351-3a5c6cbddcc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3928899336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3928899336
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.79333675
Short name T5
Test name
Test status
Simulation time 16499698962 ps
CPU time 44.76 seconds
Started Jun 21 04:43:39 PM PDT 24
Finished Jun 21 04:44:25 PM PDT 24
Peak memory 216516 kb
Host smart-906d5bdf-b4a6-486f-9cee-5a4a15c4e651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79333675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.79333675
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.313404109
Short name T130
Test name
Test status
Simulation time 7320226868 ps
CPU time 44.96 seconds
Started Jun 21 04:43:22 PM PDT 24
Finished Jun 21 04:44:11 PM PDT 24
Peak memory 219104 kb
Host smart-0681bb06-d94e-441e-aa4c-3b957cd334aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313404109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.313404109
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1787854779
Short name T271
Test name
Test status
Simulation time 10805980435 ps
CPU time 155.23 seconds
Started Jun 21 04:43:25 PM PDT 24
Finished Jun 21 04:46:06 PM PDT 24
Peak memory 239316 kb
Host smart-40d18689-c278-4b57-86a4-9ccc932938df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787854779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1787854779
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.293640139
Short name T276
Test name
Test status
Simulation time 346307850 ps
CPU time 19.19 seconds
Started Jun 21 04:43:21 PM PDT 24
Finished Jun 21 04:43:44 PM PDT 24
Peak memory 219064 kb
Host smart-12ef0308-cdbb-4312-8518-d5a65c808ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293640139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.293640139
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.382217385
Short name T61
Test name
Test status
Simulation time 2010893976 ps
CPU time 22.09 seconds
Started Jun 21 04:43:19 PM PDT 24
Finished Jun 21 04:43:45 PM PDT 24
Peak memory 218148 kb
Host smart-beee6599-08fd-4faf-9901-1396c422bc25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=382217385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.382217385
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.169236644
Short name T48
Test name
Test status
Simulation time 1372361800 ps
CPU time 20.46 seconds
Started Jun 21 04:43:20 PM PDT 24
Finished Jun 21 04:43:44 PM PDT 24
Peak memory 216144 kb
Host smart-46197e63-829e-4dce-b09a-d2c05618a39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169236644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.169236644
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1348299023
Short name T158
Test name
Test status
Simulation time 11479629169 ps
CPU time 27.13 seconds
Started Jun 21 04:43:40 PM PDT 24
Finished Jun 21 04:44:08 PM PDT 24
Peak memory 217272 kb
Host smart-14b29e30-7c95-46c9-a114-a837045a3dad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348299023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1348299023
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1104412614
Short name T241
Test name
Test status
Simulation time 3388839124 ps
CPU time 233.51 seconds
Started Jun 21 04:43:23 PM PDT 24
Finished Jun 21 04:47:22 PM PDT 24
Peak memory 229336 kb
Host smart-7320a8de-92fe-4d52-8d1a-86070464bda2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104412614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1104412614
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2757749789
Short name T39
Test name
Test status
Simulation time 7245813061 ps
CPU time 64.17 seconds
Started Jun 21 04:43:25 PM PDT 24
Finished Jun 21 04:44:35 PM PDT 24
Peak memory 219080 kb
Host smart-f785eecf-14d5-4df6-ae1b-643379092ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757749789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2757749789
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1449631318
Short name T273
Test name
Test status
Simulation time 4814095135 ps
CPU time 23.49 seconds
Started Jun 21 04:43:25 PM PDT 24
Finished Jun 21 04:43:54 PM PDT 24
Peak memory 218900 kb
Host smart-14ee63d2-a670-488b-a926-73c2ab1cf5cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1449631318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1449631318
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2990839354
Short name T330
Test name
Test status
Simulation time 1215164334 ps
CPU time 29.01 seconds
Started Jun 21 04:43:38 PM PDT 24
Finished Jun 21 04:44:09 PM PDT 24
Peak memory 215520 kb
Host smart-5c7263f4-b9b2-4e6a-bd51-98042b697367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990839354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2990839354
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.4106974878
Short name T349
Test name
Test status
Simulation time 51083783532 ps
CPU time 121.64 seconds
Started Jun 21 04:43:27 PM PDT 24
Finished Jun 21 04:45:34 PM PDT 24
Peak memory 219140 kb
Host smart-654a7d77-d219-4287-bead-c705d0dd1585
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106974878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.4106974878
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2260832451
Short name T90
Test name
Test status
Simulation time 1032572402 ps
CPU time 8.15 seconds
Started Jun 21 04:43:24 PM PDT 24
Finished Jun 21 04:43:38 PM PDT 24
Peak memory 216792 kb
Host smart-f65d52bd-407c-487b-9d35-5b20ac21ebd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260832451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2260832451
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2464577192
Short name T192
Test name
Test status
Simulation time 10422016429 ps
CPU time 181.46 seconds
Started Jun 21 04:43:26 PM PDT 24
Finished Jun 21 04:46:33 PM PDT 24
Peak memory 239884 kb
Host smart-bc3a8fdf-81bf-419b-bdcd-10504a24aafe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464577192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2464577192
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.386342360
Short name T170
Test name
Test status
Simulation time 8555706050 ps
CPU time 34.03 seconds
Started Jun 21 04:43:29 PM PDT 24
Finished Jun 21 04:44:08 PM PDT 24
Peak memory 219124 kb
Host smart-b9be10e2-5fa0-42d0-a924-ec2335457a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386342360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.386342360
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2007787258
Short name T163
Test name
Test status
Simulation time 179281713 ps
CPU time 10.73 seconds
Started Jun 21 04:43:19 PM PDT 24
Finished Jun 21 04:43:33 PM PDT 24
Peak memory 219132 kb
Host smart-6b5a55e5-b3c1-4f90-9a1c-531d0483d01b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2007787258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2007787258
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.895460728
Short name T8
Test name
Test status
Simulation time 4294468552 ps
CPU time 21.25 seconds
Started Jun 21 04:43:26 PM PDT 24
Finished Jun 21 04:43:53 PM PDT 24
Peak memory 216116 kb
Host smart-0c923b4f-5e1a-4d4f-950b-58eb9b2a773c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895460728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.895460728
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2307164440
Short name T281
Test name
Test status
Simulation time 8090718038 ps
CPU time 67.27 seconds
Started Jun 21 04:43:32 PM PDT 24
Finished Jun 21 04:44:43 PM PDT 24
Peak memory 219124 kb
Host smart-926631fb-e5e3-440f-a1b1-de6923ea0869
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307164440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2307164440
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3118729639
Short name T249
Test name
Test status
Simulation time 9571821461 ps
CPU time 13.05 seconds
Started Jun 21 04:43:26 PM PDT 24
Finished Jun 21 04:43:45 PM PDT 24
Peak memory 216916 kb
Host smart-40c4bbc2-73f6-44a2-87bb-cdf324b5524a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118729639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3118729639
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1963511198
Short name T33
Test name
Test status
Simulation time 63722686560 ps
CPU time 256.72 seconds
Started Jun 21 04:43:23 PM PDT 24
Finished Jun 21 04:47:44 PM PDT 24
Peak memory 233144 kb
Host smart-6b1a61f9-053e-49ae-8574-dd6573705919
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963511198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1963511198
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1614406973
Short name T113
Test name
Test status
Simulation time 2741927460 ps
CPU time 26.38 seconds
Started Jun 21 04:43:25 PM PDT 24
Finished Jun 21 04:43:57 PM PDT 24
Peak memory 219176 kb
Host smart-ad539935-0633-4bf2-ae79-ecb9a7c0f55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614406973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1614406973
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1452509279
Short name T129
Test name
Test status
Simulation time 16345266234 ps
CPU time 32.05 seconds
Started Jun 21 04:43:23 PM PDT 24
Finished Jun 21 04:43:59 PM PDT 24
Peak memory 211788 kb
Host smart-a3e65b6d-e9c5-40b2-9e54-ed8e9911148e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1452509279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1452509279
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2264767415
Short name T340
Test name
Test status
Simulation time 366201351 ps
CPU time 20.54 seconds
Started Jun 21 04:43:25 PM PDT 24
Finished Jun 21 04:43:51 PM PDT 24
Peak memory 216784 kb
Host smart-108ca33e-9fc1-4693-a0d0-118b84d370d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264767415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2264767415
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2371479071
Short name T300
Test name
Test status
Simulation time 8620581843 ps
CPU time 92.53 seconds
Started Jun 21 04:43:31 PM PDT 24
Finished Jun 21 04:45:07 PM PDT 24
Peak memory 219400 kb
Host smart-e28fcd87-9adf-4e05-92c9-804d2e7ed7bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371479071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2371479071
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.255847671
Short name T179
Test name
Test status
Simulation time 688028339 ps
CPU time 8.37 seconds
Started Jun 21 04:43:25 PM PDT 24
Finished Jun 21 04:43:39 PM PDT 24
Peak memory 216876 kb
Host smart-f2e7216a-418f-4769-a9a4-a31ebdeaf0c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255847671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.255847671
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2029460855
Short name T346
Test name
Test status
Simulation time 64689702915 ps
CPU time 486.63 seconds
Started Jun 21 04:43:19 PM PDT 24
Finished Jun 21 04:51:36 PM PDT 24
Peak memory 219372 kb
Host smart-24b3ac31-6a34-4937-bb3b-58b613a2ecbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029460855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2029460855
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.446727504
Short name T147
Test name
Test status
Simulation time 17826258532 ps
CPU time 45.61 seconds
Started Jun 21 04:43:31 PM PDT 24
Finished Jun 21 04:44:20 PM PDT 24
Peak memory 219056 kb
Host smart-979fe534-abb1-4cc4-8f97-6a738f399b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446727504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.446727504
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1662828179
Short name T143
Test name
Test status
Simulation time 827192131 ps
CPU time 15.25 seconds
Started Jun 21 04:43:33 PM PDT 24
Finished Jun 21 04:43:51 PM PDT 24
Peak memory 219148 kb
Host smart-26f1e355-f28b-4413-bbc5-5a6c3d0647e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1662828179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1662828179
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3770051311
Short name T121
Test name
Test status
Simulation time 4588727858 ps
CPU time 52.19 seconds
Started Jun 21 04:43:33 PM PDT 24
Finished Jun 21 04:44:28 PM PDT 24
Peak memory 216400 kb
Host smart-61e3b8b7-4b82-4a55-925a-b650c06d6352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770051311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3770051311
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3957940307
Short name T309
Test name
Test status
Simulation time 11561067781 ps
CPU time 116.03 seconds
Started Jun 21 04:43:33 PM PDT 24
Finished Jun 21 04:45:32 PM PDT 24
Peak memory 220440 kb
Host smart-e60f982d-691e-4d96-a4b1-bf1a55903d71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957940307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3957940307
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3000534964
Short name T42
Test name
Test status
Simulation time 194744943259 ps
CPU time 1158.68 seconds
Started Jun 21 04:43:21 PM PDT 24
Finished Jun 21 05:02:44 PM PDT 24
Peak memory 235648 kb
Host smart-92e65407-3dc8-48f1-9e75-7791c580850c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000534964 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.3000534964
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3812604926
Short name T193
Test name
Test status
Simulation time 12356014460 ps
CPU time 26.76 seconds
Started Jun 21 04:43:24 PM PDT 24
Finished Jun 21 04:43:56 PM PDT 24
Peak memory 217304 kb
Host smart-2bf24045-b9ae-4978-a05d-a3930b4cf6cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812604926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3812604926
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3319062057
Short name T31
Test name
Test status
Simulation time 19389530100 ps
CPU time 287.51 seconds
Started Jun 21 04:43:37 PM PDT 24
Finished Jun 21 04:48:25 PM PDT 24
Peak memory 219348 kb
Host smart-e7831810-c67c-49e3-b652-7d217cbc3851
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319062057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3319062057
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2564165439
Short name T112
Test name
Test status
Simulation time 15223278029 ps
CPU time 44.75 seconds
Started Jun 21 04:43:42 PM PDT 24
Finished Jun 21 04:44:28 PM PDT 24
Peak memory 219100 kb
Host smart-292b1df0-d2a3-4463-9fa0-394ce7462ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564165439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2564165439
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3463338995
Short name T201
Test name
Test status
Simulation time 8183254660 ps
CPU time 22.06 seconds
Started Jun 21 04:43:31 PM PDT 24
Finished Jun 21 04:43:57 PM PDT 24
Peak memory 211520 kb
Host smart-14174b9f-56cd-4f5b-aad4-175714693601
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3463338995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3463338995
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1479010310
Short name T246
Test name
Test status
Simulation time 17132438216 ps
CPU time 78.4 seconds
Started Jun 21 04:43:28 PM PDT 24
Finished Jun 21 04:44:51 PM PDT 24
Peak memory 216400 kb
Host smart-6144a674-3b9f-485b-b203-ff06dd7fcae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479010310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1479010310
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.67198269
Short name T282
Test name
Test status
Simulation time 6756303942 ps
CPU time 36.01 seconds
Started Jun 21 04:43:25 PM PDT 24
Finished Jun 21 04:44:06 PM PDT 24
Peak memory 218984 kb
Host smart-bf3ecf74-918c-4058-b444-f6cfe241cc88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67198269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 16.rom_ctrl_stress_all.67198269
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1565851872
Short name T311
Test name
Test status
Simulation time 2576917179 ps
CPU time 17.35 seconds
Started Jun 21 04:43:36 PM PDT 24
Finished Jun 21 04:43:54 PM PDT 24
Peak memory 216860 kb
Host smart-1088cc05-33c2-4a96-b829-f17a82d6adfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565851872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1565851872
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2667658854
Short name T272
Test name
Test status
Simulation time 413275464713 ps
CPU time 415.39 seconds
Started Jun 21 04:43:24 PM PDT 24
Finished Jun 21 04:50:24 PM PDT 24
Peak memory 233612 kb
Host smart-35bfb472-4836-4791-b438-625e9aab0b3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667658854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2667658854
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1537415673
Short name T214
Test name
Test status
Simulation time 2538757180 ps
CPU time 19.74 seconds
Started Jun 21 04:43:25 PM PDT 24
Finished Jun 21 04:43:51 PM PDT 24
Peak memory 219112 kb
Host smart-a9afd73a-e822-4fea-b6ac-6d2a62b39196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537415673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1537415673
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.526712519
Short name T279
Test name
Test status
Simulation time 1720803613 ps
CPU time 15.74 seconds
Started Jun 21 04:43:43 PM PDT 24
Finished Jun 21 04:44:00 PM PDT 24
Peak memory 211476 kb
Host smart-6406c2f4-429d-4b49-8d78-68415132f362
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=526712519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.526712519
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.528991980
Short name T47
Test name
Test status
Simulation time 28791676867 ps
CPU time 68.03 seconds
Started Jun 21 04:43:25 PM PDT 24
Finished Jun 21 04:44:38 PM PDT 24
Peak memory 216360 kb
Host smart-a1c2a360-0f64-4ccc-bd87-eaff9a8390a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528991980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.528991980
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1769399138
Short name T131
Test name
Test status
Simulation time 7901184313 ps
CPU time 85.73 seconds
Started Jun 21 04:43:35 PM PDT 24
Finished Jun 21 04:45:02 PM PDT 24
Peak memory 219124 kb
Host smart-9101801c-a141-4740-b43a-4e7915daf7e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769399138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1769399138
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.4267039802
Short name T225
Test name
Test status
Simulation time 2010728144 ps
CPU time 15.27 seconds
Started Jun 21 04:43:22 PM PDT 24
Finished Jun 21 04:43:42 PM PDT 24
Peak memory 216824 kb
Host smart-92a4834a-da2e-47e9-b1cc-4e3de2877645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267039802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.4267039802
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1766977538
Short name T20
Test name
Test status
Simulation time 8037096454 ps
CPU time 150.32 seconds
Started Jun 21 04:43:23 PM PDT 24
Finished Jun 21 04:45:58 PM PDT 24
Peak memory 233580 kb
Host smart-e4c782bb-448a-44e6-8d0a-a6bd61dce990
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766977538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1766977538
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3800580684
Short name T144
Test name
Test status
Simulation time 53920091911 ps
CPU time 68.55 seconds
Started Jun 21 04:43:38 PM PDT 24
Finished Jun 21 04:44:48 PM PDT 24
Peak memory 218988 kb
Host smart-1d9781dc-db7c-4337-944f-025662e230a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800580684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3800580684
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2076375767
Short name T108
Test name
Test status
Simulation time 2705304112 ps
CPU time 25.08 seconds
Started Jun 21 04:43:31 PM PDT 24
Finished Jun 21 04:44:00 PM PDT 24
Peak memory 219200 kb
Host smart-4c64d17b-7cbe-4d37-9d18-e71f08f4d0f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2076375767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2076375767
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.39911094
Short name T296
Test name
Test status
Simulation time 26596756155 ps
CPU time 53.54 seconds
Started Jun 21 04:43:23 PM PDT 24
Finished Jun 21 04:44:21 PM PDT 24
Peak memory 216332 kb
Host smart-ceb4f5cf-bb98-49fe-86a4-30d202a4fb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39911094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.39911094
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2221827468
Short name T331
Test name
Test status
Simulation time 5382911410 ps
CPU time 25.14 seconds
Started Jun 21 04:43:32 PM PDT 24
Finished Jun 21 04:44:00 PM PDT 24
Peak memory 217268 kb
Host smart-70c0fe86-64e7-459c-90a2-cce86626db38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221827468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2221827468
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3628023810
Short name T208
Test name
Test status
Simulation time 40007492429 ps
CPU time 411.18 seconds
Started Jun 21 04:43:40 PM PDT 24
Finished Jun 21 04:50:32 PM PDT 24
Peak memory 238140 kb
Host smart-9f4fa2b8-c9d0-4700-a46f-2aa8428508a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628023810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3628023810
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1225825147
Short name T242
Test name
Test status
Simulation time 7028716270 ps
CPU time 58.44 seconds
Started Jun 21 04:43:37 PM PDT 24
Finished Jun 21 04:44:36 PM PDT 24
Peak memory 219124 kb
Host smart-d842a8e4-541a-4b86-8d8d-21bf4ce59f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225825147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1225825147
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3327638574
Short name T176
Test name
Test status
Simulation time 16930207109 ps
CPU time 25.92 seconds
Started Jun 21 04:43:33 PM PDT 24
Finished Jun 21 04:44:02 PM PDT 24
Peak memory 217520 kb
Host smart-160d2065-17cd-4724-bb36-2352a983acd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3327638574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3327638574
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3670658528
Short name T278
Test name
Test status
Simulation time 348178821 ps
CPU time 19.92 seconds
Started Jun 21 04:43:21 PM PDT 24
Finished Jun 21 04:43:49 PM PDT 24
Peak memory 216188 kb
Host smart-8d6fa785-2e8a-4b88-8b02-a13dfd267b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670658528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3670658528
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3361528107
Short name T326
Test name
Test status
Simulation time 1190208276 ps
CPU time 21.03 seconds
Started Jun 21 04:43:41 PM PDT 24
Finished Jun 21 04:44:03 PM PDT 24
Peak memory 218880 kb
Host smart-f1f9344f-96b9-46e9-9a12-9ab82cf5252d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361528107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3361528107
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1617754060
Short name T118
Test name
Test status
Simulation time 5060239843 ps
CPU time 12.97 seconds
Started Jun 21 04:43:38 PM PDT 24
Finished Jun 21 04:43:52 PM PDT 24
Peak memory 217028 kb
Host smart-952b77c9-a49e-4fca-b770-a2826980b47d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617754060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1617754060
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3533251401
Short name T140
Test name
Test status
Simulation time 18441030993 ps
CPU time 390.44 seconds
Started Jun 21 04:43:18 PM PDT 24
Finished Jun 21 04:49:52 PM PDT 24
Peak memory 238324 kb
Host smart-7c08753b-a446-4f18-a751-023fdff60afa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533251401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3533251401
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1546398031
Short name T157
Test name
Test status
Simulation time 3946743841 ps
CPU time 26.42 seconds
Started Jun 21 04:43:06 PM PDT 24
Finished Jun 21 04:43:35 PM PDT 24
Peak memory 219088 kb
Host smart-6c702033-3286-4598-9479-d007752a7ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546398031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1546398031
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1266660521
Short name T197
Test name
Test status
Simulation time 183125183 ps
CPU time 10.37 seconds
Started Jun 21 04:43:12 PM PDT 24
Finished Jun 21 04:43:27 PM PDT 24
Peak memory 219072 kb
Host smart-9d79f1b0-b0cf-4a6d-ade7-3641b8d012f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1266660521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1266660521
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3462936277
Short name T28
Test name
Test status
Simulation time 4878330180 ps
CPU time 228.56 seconds
Started Jun 21 04:43:27 PM PDT 24
Finished Jun 21 04:47:21 PM PDT 24
Peak memory 235404 kb
Host smart-fcd6e7ca-64aa-41ad-9878-a357d1a5aa1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462936277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3462936277
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1213272689
Short name T205
Test name
Test status
Simulation time 77239857793 ps
CPU time 58.27 seconds
Started Jun 21 04:43:16 PM PDT 24
Finished Jun 21 04:44:19 PM PDT 24
Peak memory 216192 kb
Host smart-8a0e3dd0-114a-4389-8974-a4bce13a9aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213272689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1213272689
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2140214944
Short name T312
Test name
Test status
Simulation time 2130567774 ps
CPU time 37.29 seconds
Started Jun 21 04:43:08 PM PDT 24
Finished Jun 21 04:43:48 PM PDT 24
Peak memory 219076 kb
Host smart-f3738da1-badd-4544-869b-9ab0ab891fe0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140214944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2140214944
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3768431660
Short name T229
Test name
Test status
Simulation time 16107075831 ps
CPU time 31.68 seconds
Started Jun 21 04:43:32 PM PDT 24
Finished Jun 21 04:44:07 PM PDT 24
Peak memory 217200 kb
Host smart-b8084e82-b42b-4110-84d0-d2030614e0dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768431660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3768431660
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2160223301
Short name T132
Test name
Test status
Simulation time 30135910711 ps
CPU time 374.08 seconds
Started Jun 21 04:43:20 PM PDT 24
Finished Jun 21 04:49:44 PM PDT 24
Peak memory 237736 kb
Host smart-acfecf90-9499-47b2-a07a-7d24cfb18d50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160223301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2160223301
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1747737907
Short name T128
Test name
Test status
Simulation time 16351705058 ps
CPU time 67.55 seconds
Started Jun 21 04:43:25 PM PDT 24
Finished Jun 21 04:44:38 PM PDT 24
Peak memory 219008 kb
Host smart-ccd81a56-f1a2-4512-9ad4-666f352b027e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747737907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1747737907
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3848132338
Short name T11
Test name
Test status
Simulation time 2005195863 ps
CPU time 13.64 seconds
Started Jun 21 04:43:39 PM PDT 24
Finished Jun 21 04:43:54 PM PDT 24
Peak memory 218572 kb
Host smart-3e6cff0d-c075-4e1f-8fc7-33e7a5679385
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3848132338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3848132338
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1479937478
Short name T337
Test name
Test status
Simulation time 43433447898 ps
CPU time 57.88 seconds
Started Jun 21 04:43:22 PM PDT 24
Finished Jun 21 04:44:24 PM PDT 24
Peak memory 216508 kb
Host smart-ed9928d5-2369-4bb3-987e-87d73698323b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479937478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1479937478
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3093156911
Short name T301
Test name
Test status
Simulation time 7945444047 ps
CPU time 38.83 seconds
Started Jun 21 04:43:23 PM PDT 24
Finished Jun 21 04:44:07 PM PDT 24
Peak memory 219136 kb
Host smart-33edcceb-57e8-42bb-8e6f-e7e5b31b187b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093156911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3093156911
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1035522081
Short name T92
Test name
Test status
Simulation time 14944465360 ps
CPU time 31.27 seconds
Started Jun 21 04:43:38 PM PDT 24
Finished Jun 21 04:44:11 PM PDT 24
Peak memory 217060 kb
Host smart-72828124-820a-48d1-9789-3db59bde8056
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035522081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1035522081
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3755703190
Short name T344
Test name
Test status
Simulation time 18863511279 ps
CPU time 242.19 seconds
Started Jun 21 04:43:26 PM PDT 24
Finished Jun 21 04:47:34 PM PDT 24
Peak memory 217748 kb
Host smart-079211a0-b00e-4947-b89e-2d5da52ab275
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755703190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3755703190
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4193565038
Short name T265
Test name
Test status
Simulation time 8036556540 ps
CPU time 68.17 seconds
Started Jun 21 04:43:39 PM PDT 24
Finished Jun 21 04:44:48 PM PDT 24
Peak memory 219112 kb
Host smart-737dbb6a-4bd3-4b2a-af20-bb34f4a6d498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193565038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4193565038
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2405107027
Short name T259
Test name
Test status
Simulation time 3422883390 ps
CPU time 30.12 seconds
Started Jun 21 04:43:33 PM PDT 24
Finished Jun 21 04:44:06 PM PDT 24
Peak memory 211244 kb
Host smart-f4ef8b67-8331-4c97-92e4-e1f9fca08db8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2405107027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2405107027
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1920449681
Short name T343
Test name
Test status
Simulation time 16689681523 ps
CPU time 82.65 seconds
Started Jun 21 04:43:29 PM PDT 24
Finished Jun 21 04:44:56 PM PDT 24
Peak memory 216908 kb
Host smart-19374902-3591-487e-89fd-457908de2b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920449681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1920449681
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.484934158
Short name T251
Test name
Test status
Simulation time 30257290568 ps
CPU time 71.11 seconds
Started Jun 21 04:43:24 PM PDT 24
Finished Jun 21 04:44:40 PM PDT 24
Peak memory 217612 kb
Host smart-c8e731a2-0d70-4a9a-9967-7503dfdbf802
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484934158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.484934158
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.4223617935
Short name T183
Test name
Test status
Simulation time 172682331 ps
CPU time 8.87 seconds
Started Jun 21 04:43:38 PM PDT 24
Finished Jun 21 04:43:49 PM PDT 24
Peak memory 216904 kb
Host smart-9c294b42-10e7-4c40-9d6b-045a4e7b7beb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223617935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.4223617935
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2432161069
Short name T211
Test name
Test status
Simulation time 293535387125 ps
CPU time 697.93 seconds
Started Jun 21 04:43:40 PM PDT 24
Finished Jun 21 04:55:19 PM PDT 24
Peak memory 233724 kb
Host smart-fce9535e-68aa-4326-88f5-35b8be4dfb88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432161069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2432161069
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.791954820
Short name T263
Test name
Test status
Simulation time 9825582239 ps
CPU time 35.73 seconds
Started Jun 21 04:43:26 PM PDT 24
Finished Jun 21 04:44:07 PM PDT 24
Peak memory 219156 kb
Host smart-db85d1da-b1c7-4965-a04c-22eeb3214493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791954820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.791954820
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.4073444435
Short name T142
Test name
Test status
Simulation time 5847456008 ps
CPU time 20.79 seconds
Started Jun 21 04:43:43 PM PDT 24
Finished Jun 21 04:44:04 PM PDT 24
Peak memory 219304 kb
Host smart-fcef6054-9756-4db1-9baf-a3303731fdd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4073444435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.4073444435
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.464768686
Short name T287
Test name
Test status
Simulation time 7550925677 ps
CPU time 64.88 seconds
Started Jun 21 04:43:40 PM PDT 24
Finished Jun 21 04:44:46 PM PDT 24
Peak memory 216592 kb
Host smart-c3643832-7fa7-477f-b3fe-a7a37aa34aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464768686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.464768686
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2507506229
Short name T294
Test name
Test status
Simulation time 229632681 ps
CPU time 18.48 seconds
Started Jun 21 04:43:24 PM PDT 24
Finished Jun 21 04:43:48 PM PDT 24
Peak memory 219164 kb
Host smart-00cd18d8-7480-4df0-8326-21189ff4add2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507506229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2507506229
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3474907313
Short name T284
Test name
Test status
Simulation time 167314273 ps
CPU time 8.43 seconds
Started Jun 21 04:43:33 PM PDT 24
Finished Jun 21 04:43:44 PM PDT 24
Peak memory 216884 kb
Host smart-7d07c329-20cc-4ada-877e-e533aa87fc96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474907313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3474907313
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3799909909
Short name T324
Test name
Test status
Simulation time 9943976341 ps
CPU time 384.55 seconds
Started Jun 21 04:43:27 PM PDT 24
Finished Jun 21 04:49:57 PM PDT 24
Peak memory 238920 kb
Host smart-657ed11d-5f83-4094-bbc1-e4ef96ab8561
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799909909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3799909909
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.913166767
Short name T133
Test name
Test status
Simulation time 10464223215 ps
CPU time 57.95 seconds
Started Jun 21 04:43:46 PM PDT 24
Finished Jun 21 04:44:45 PM PDT 24
Peak memory 219080 kb
Host smart-eeb5d676-faff-4ef6-a989-32c485e31987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913166767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.913166767
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1923343396
Short name T167
Test name
Test status
Simulation time 2920683186 ps
CPU time 26.38 seconds
Started Jun 21 04:43:47 PM PDT 24
Finished Jun 21 04:44:14 PM PDT 24
Peak memory 219160 kb
Host smart-8e87353d-6227-4460-b1f6-8ff5e22fef5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1923343396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1923343396
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.362585306
Short name T245
Test name
Test status
Simulation time 712212262 ps
CPU time 19.84 seconds
Started Jun 21 04:43:34 PM PDT 24
Finished Jun 21 04:43:56 PM PDT 24
Peak memory 216380 kb
Host smart-b8614131-bd3f-4d8f-969f-fc018368dc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362585306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.362585306
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3649379082
Short name T280
Test name
Test status
Simulation time 377520275 ps
CPU time 25.05 seconds
Started Jun 21 04:43:32 PM PDT 24
Finished Jun 21 04:44:00 PM PDT 24
Peak memory 219072 kb
Host smart-82c86ebe-ad6c-4b2f-b4a6-bff6c7133282
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649379082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3649379082
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.4210174827
Short name T275
Test name
Test status
Simulation time 6098926035 ps
CPU time 25.46 seconds
Started Jun 21 04:43:28 PM PDT 24
Finished Jun 21 04:43:59 PM PDT 24
Peak memory 216720 kb
Host smart-41707350-2463-443d-9b4a-0f89cf7c4d0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210174827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.4210174827
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1301805163
Short name T221
Test name
Test status
Simulation time 14816320086 ps
CPU time 64.91 seconds
Started Jun 21 04:43:35 PM PDT 24
Finished Jun 21 04:44:42 PM PDT 24
Peak memory 219080 kb
Host smart-2dab76f5-429a-4239-96f8-0705e7d8c588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301805163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1301805163
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3493936797
Short name T134
Test name
Test status
Simulation time 8178503353 ps
CPU time 33.52 seconds
Started Jun 21 04:43:44 PM PDT 24
Finished Jun 21 04:44:18 PM PDT 24
Peak memory 219160 kb
Host smart-609c64f0-7c1b-4a41-a81b-ebd3f85fa900
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3493936797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3493936797
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3714744416
Short name T297
Test name
Test status
Simulation time 6957006626 ps
CPU time 37.08 seconds
Started Jun 21 04:43:32 PM PDT 24
Finished Jun 21 04:44:12 PM PDT 24
Peak memory 217164 kb
Host smart-a4033b2c-6fc1-45c1-a426-fce7d8fc9e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714744416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3714744416
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1701765496
Short name T195
Test name
Test status
Simulation time 715813101 ps
CPU time 38.99 seconds
Started Jun 21 04:43:38 PM PDT 24
Finished Jun 21 04:44:19 PM PDT 24
Peak memory 219080 kb
Host smart-7ea7e448-c788-46e6-89ff-08403bd7c4d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701765496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1701765496
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1673739264
Short name T260
Test name
Test status
Simulation time 14622365481 ps
CPU time 28.28 seconds
Started Jun 21 04:43:26 PM PDT 24
Finished Jun 21 04:44:00 PM PDT 24
Peak memory 217380 kb
Host smart-2ea8a2d1-fcbb-43fd-8d60-eafa5a9c6623
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673739264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1673739264
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1045210243
Short name T290
Test name
Test status
Simulation time 17114325787 ps
CPU time 290.89 seconds
Started Jun 21 04:43:49 PM PDT 24
Finished Jun 21 04:48:46 PM PDT 24
Peak memory 242460 kb
Host smart-47fa7dea-aa92-409f-bbfa-56a9623932a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045210243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1045210243
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1161039750
Short name T26
Test name
Test status
Simulation time 6653980248 ps
CPU time 58.05 seconds
Started Jun 21 04:43:48 PM PDT 24
Finished Jun 21 04:44:47 PM PDT 24
Peak memory 219100 kb
Host smart-37f9c11e-4ab5-492e-b65d-5d71ae1b30c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161039750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1161039750
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1340993430
Short name T220
Test name
Test status
Simulation time 2369467700 ps
CPU time 24.27 seconds
Started Jun 21 04:43:27 PM PDT 24
Finished Jun 21 04:43:57 PM PDT 24
Peak memory 211092 kb
Host smart-99bd454e-6f83-49e1-a7cb-870bddaad6c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1340993430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1340993430
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.428876092
Short name T136
Test name
Test status
Simulation time 6505264707 ps
CPU time 54.21 seconds
Started Jun 21 04:43:47 PM PDT 24
Finished Jun 21 04:44:42 PM PDT 24
Peak memory 217428 kb
Host smart-4b6dec11-bfdd-4592-a67c-1e336ea4a6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428876092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.428876092
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2190357240
Short name T62
Test name
Test status
Simulation time 23104947023 ps
CPU time 123.56 seconds
Started Jun 21 04:43:41 PM PDT 24
Finished Jun 21 04:45:46 PM PDT 24
Peak memory 219124 kb
Host smart-2a2bf930-9448-4622-af21-846d0ff3632c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190357240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2190357240
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2551008530
Short name T182
Test name
Test status
Simulation time 4665445908 ps
CPU time 22.99 seconds
Started Jun 21 04:43:28 PM PDT 24
Finished Jun 21 04:43:56 PM PDT 24
Peak memory 217208 kb
Host smart-d96c41ff-dc75-4d49-9d42-47c4bf784ba0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551008530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2551008530
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.359010060
Short name T285
Test name
Test status
Simulation time 33970958054 ps
CPU time 484.59 seconds
Started Jun 21 04:43:36 PM PDT 24
Finished Jun 21 04:51:42 PM PDT 24
Peak memory 238824 kb
Host smart-2e1d8be5-6f5c-415e-ace0-85b894aea27c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359010060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.359010060
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3585189599
Short name T270
Test name
Test status
Simulation time 1548947981 ps
CPU time 29.78 seconds
Started Jun 21 04:43:44 PM PDT 24
Finished Jun 21 04:44:15 PM PDT 24
Peak memory 219176 kb
Host smart-ed5bb953-a86a-451c-8de3-7569d58a595c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585189599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3585189599
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.4048056683
Short name T117
Test name
Test status
Simulation time 14994874411 ps
CPU time 30.47 seconds
Started Jun 21 04:43:47 PM PDT 24
Finished Jun 21 04:44:18 PM PDT 24
Peak memory 219208 kb
Host smart-5eee484d-7447-499b-91bf-542d3e1e7764
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4048056683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.4048056683
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3895852091
Short name T19
Test name
Test status
Simulation time 8570560886 ps
CPU time 39.38 seconds
Started Jun 21 04:43:31 PM PDT 24
Finished Jun 21 04:44:14 PM PDT 24
Peak memory 216488 kb
Host smart-dc6d10b3-4064-4fb8-afd8-65d77429258d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895852091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3895852091
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2775270377
Short name T333
Test name
Test status
Simulation time 3554028614 ps
CPU time 54.89 seconds
Started Jun 21 04:43:26 PM PDT 24
Finished Jun 21 04:44:27 PM PDT 24
Peak memory 220520 kb
Host smart-98a5ccee-8028-414a-bd19-d101b30b783e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775270377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2775270377
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3870392111
Short name T169
Test name
Test status
Simulation time 3342887961 ps
CPU time 13.99 seconds
Started Jun 21 04:43:41 PM PDT 24
Finished Jun 21 04:43:56 PM PDT 24
Peak memory 216836 kb
Host smart-1e852a7b-95b4-49cd-81f7-bb8de26a7d0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870392111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3870392111
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3825653842
Short name T148
Test name
Test status
Simulation time 12931797847 ps
CPU time 110.12 seconds
Started Jun 21 04:43:26 PM PDT 24
Finished Jun 21 04:45:22 PM PDT 24
Peak memory 239144 kb
Host smart-cd78814d-733e-421e-9ec4-3668124a0cbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825653842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3825653842
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2257422766
Short name T123
Test name
Test status
Simulation time 39413663254 ps
CPU time 55.17 seconds
Started Jun 21 04:43:51 PM PDT 24
Finished Jun 21 04:44:47 PM PDT 24
Peak memory 219116 kb
Host smart-53a72b5a-8ebc-41b6-9b2f-4d4506ba77c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257422766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2257422766
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3137557595
Short name T310
Test name
Test status
Simulation time 1974101546 ps
CPU time 21.76 seconds
Started Jun 21 04:43:34 PM PDT 24
Finished Jun 21 04:43:58 PM PDT 24
Peak memory 219140 kb
Host smart-806730e7-0f57-497f-901f-9044dde06f9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3137557595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3137557595
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3468929392
Short name T351
Test name
Test status
Simulation time 12493846685 ps
CPU time 39.96 seconds
Started Jun 21 04:43:25 PM PDT 24
Finished Jun 21 04:44:11 PM PDT 24
Peak memory 216624 kb
Host smart-5f5451eb-8823-443e-ae0d-e091bddb9948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468929392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3468929392
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1543542182
Short name T159
Test name
Test status
Simulation time 8622768296 ps
CPU time 28.55 seconds
Started Jun 21 04:43:32 PM PDT 24
Finished Jun 21 04:44:03 PM PDT 24
Peak memory 216344 kb
Host smart-4ee4ecd8-3f0f-4680-9828-ed4075f859b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543542182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1543542182
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1710501719
Short name T14
Test name
Test status
Simulation time 16362621845 ps
CPU time 164.2 seconds
Started Jun 21 04:43:31 PM PDT 24
Finished Jun 21 04:46:19 PM PDT 24
Peak memory 231448 kb
Host smart-c97f6130-9acc-4fd7-a990-18056d12a42b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710501719 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.1710501719
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3907877685
Short name T255
Test name
Test status
Simulation time 10846114461 ps
CPU time 25.46 seconds
Started Jun 21 04:43:30 PM PDT 24
Finished Jun 21 04:44:00 PM PDT 24
Peak memory 217172 kb
Host smart-d91ee3da-1df1-4dc5-aa8a-3c2c9c0f18b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907877685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3907877685
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.639444673
Short name T166
Test name
Test status
Simulation time 70739612346 ps
CPU time 367.79 seconds
Started Jun 21 04:43:40 PM PDT 24
Finished Jun 21 04:49:49 PM PDT 24
Peak memory 225556 kb
Host smart-30efb9d6-3087-412e-bae9-f388e0d6fef4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639444673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.639444673
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1764606215
Short name T267
Test name
Test status
Simulation time 35450849734 ps
CPU time 66.34 seconds
Started Jun 21 04:43:50 PM PDT 24
Finished Jun 21 04:44:57 PM PDT 24
Peak memory 219132 kb
Host smart-de5fa49c-0719-4e87-9c1e-b2374a69384e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764606215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1764606215
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.4024940910
Short name T238
Test name
Test status
Simulation time 2163307409 ps
CPU time 10.65 seconds
Started Jun 21 04:43:40 PM PDT 24
Finished Jun 21 04:43:52 PM PDT 24
Peak memory 219196 kb
Host smart-30f29a74-3fee-4e05-85b3-954a40126086
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4024940910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.4024940910
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1104915951
Short name T141
Test name
Test status
Simulation time 15459852917 ps
CPU time 55.38 seconds
Started Jun 21 04:43:46 PM PDT 24
Finished Jun 21 04:44:43 PM PDT 24
Peak memory 216572 kb
Host smart-28dac8fd-eacf-4391-94d6-403550ece510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104915951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1104915951
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.89060510
Short name T336
Test name
Test status
Simulation time 7561530505 ps
CPU time 34.72 seconds
Started Jun 21 04:43:35 PM PDT 24
Finished Jun 21 04:44:11 PM PDT 24
Peak memory 219164 kb
Host smart-4062205d-4f67-492d-95e3-f7ac22434f9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89060510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 28.rom_ctrl_stress_all.89060510
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2067015526
Short name T126
Test name
Test status
Simulation time 575394373 ps
CPU time 13.23 seconds
Started Jun 21 04:43:36 PM PDT 24
Finished Jun 21 04:43:50 PM PDT 24
Peak memory 216896 kb
Host smart-c3c3898a-66db-4057-a50b-92e705022809
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067015526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2067015526
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3250502186
Short name T165
Test name
Test status
Simulation time 115029079532 ps
CPU time 340.3 seconds
Started Jun 21 04:43:34 PM PDT 24
Finished Jun 21 04:49:17 PM PDT 24
Peak memory 236576 kb
Host smart-275281dc-0ae6-4d76-b2f8-2a273d3b8ab8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250502186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3250502186
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2099721988
Short name T175
Test name
Test status
Simulation time 1502314256 ps
CPU time 19.33 seconds
Started Jun 21 04:43:57 PM PDT 24
Finished Jun 21 04:44:18 PM PDT 24
Peak memory 219048 kb
Host smart-8f89c3de-2b12-4bc8-afc5-0879957058b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099721988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2099721988
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.686701407
Short name T339
Test name
Test status
Simulation time 2245600987 ps
CPU time 22.87 seconds
Started Jun 21 04:43:37 PM PDT 24
Finished Jun 21 04:44:00 PM PDT 24
Peak memory 211176 kb
Host smart-549b6dce-eacc-454f-8f06-d14c467a27c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=686701407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.686701407
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2910478755
Short name T329
Test name
Test status
Simulation time 7194362051 ps
CPU time 51.23 seconds
Started Jun 21 04:43:40 PM PDT 24
Finished Jun 21 04:44:32 PM PDT 24
Peak memory 216472 kb
Host smart-5aabec60-dabf-4adf-b51a-5a7e4aae1833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910478755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2910478755
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.552405165
Short name T188
Test name
Test status
Simulation time 2176469615 ps
CPU time 34.09 seconds
Started Jun 21 04:43:43 PM PDT 24
Finished Jun 21 04:44:18 PM PDT 24
Peak memory 219136 kb
Host smart-e4441a61-2843-412c-b52e-1a7f2ac2b25e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552405165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.552405165
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2434002605
Short name T41
Test name
Test status
Simulation time 19929935496 ps
CPU time 774.98 seconds
Started Jun 21 04:43:43 PM PDT 24
Finished Jun 21 04:56:39 PM PDT 24
Peak memory 228724 kb
Host smart-fff206e3-13d1-4d0e-8756-5370ef943086
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434002605 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.2434002605
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2173026563
Short name T302
Test name
Test status
Simulation time 11115791214 ps
CPU time 25.17 seconds
Started Jun 21 04:43:29 PM PDT 24
Finished Jun 21 04:43:59 PM PDT 24
Peak memory 216992 kb
Host smart-3413e3b1-cb23-4ded-ad66-1c5bda615f35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173026563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2173026563
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1075591808
Short name T164
Test name
Test status
Simulation time 323145417126 ps
CPU time 813.36 seconds
Started Jun 21 04:43:25 PM PDT 24
Finished Jun 21 04:57:04 PM PDT 24
Peak memory 234780 kb
Host smart-4145034e-6b39-4153-a229-c09edcf9a69b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075591808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1075591808
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2667053196
Short name T342
Test name
Test status
Simulation time 1375121400 ps
CPU time 19.88 seconds
Started Jun 21 04:43:22 PM PDT 24
Finished Jun 21 04:43:47 PM PDT 24
Peak memory 219044 kb
Host smart-83b05b59-1d37-4814-90f0-0206793aec19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667053196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2667053196
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2475510836
Short name T217
Test name
Test status
Simulation time 1017275994 ps
CPU time 17.31 seconds
Started Jun 21 04:43:32 PM PDT 24
Finished Jun 21 04:43:52 PM PDT 24
Peak memory 218496 kb
Host smart-aa5cfe07-d8ab-4f22-87e1-95d5594329f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2475510836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2475510836
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3976246997
Short name T27
Test name
Test status
Simulation time 4463148883 ps
CPU time 131.36 seconds
Started Jun 21 04:43:46 PM PDT 24
Finished Jun 21 04:45:58 PM PDT 24
Peak memory 235224 kb
Host smart-72c65ac1-cc5a-4ff0-8bd1-439eefc225c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976246997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3976246997
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.68409592
Short name T109
Test name
Test status
Simulation time 15461410510 ps
CPU time 50.5 seconds
Started Jun 21 04:43:27 PM PDT 24
Finished Jun 21 04:44:23 PM PDT 24
Peak memory 215640 kb
Host smart-50bf2e61-158e-49f8-a733-a1b9557a2408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68409592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.68409592
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2809510669
Short name T328
Test name
Test status
Simulation time 30237144847 ps
CPU time 61.85 seconds
Started Jun 21 04:43:25 PM PDT 24
Finished Jun 21 04:44:33 PM PDT 24
Peak memory 217900 kb
Host smart-cbbb4a5f-4e52-4522-857b-b094c27c1fec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809510669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2809510669
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.4262141299
Short name T13
Test name
Test status
Simulation time 15265487885 ps
CPU time 602.41 seconds
Started Jun 21 04:43:40 PM PDT 24
Finished Jun 21 04:53:43 PM PDT 24
Peak memory 230296 kb
Host smart-2fc1b58f-34de-4580-9cef-7b58d892aa65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262141299 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.4262141299
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.308403089
Short name T207
Test name
Test status
Simulation time 2555111634 ps
CPU time 23.94 seconds
Started Jun 21 04:43:39 PM PDT 24
Finished Jun 21 04:44:04 PM PDT 24
Peak memory 216920 kb
Host smart-0bd1fa96-4719-404c-9a4f-07f1763c6572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308403089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.308403089
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3153606586
Short name T29
Test name
Test status
Simulation time 450781266781 ps
CPU time 1054.41 seconds
Started Jun 21 04:43:35 PM PDT 24
Finished Jun 21 05:01:11 PM PDT 24
Peak memory 219352 kb
Host smart-fe1a87a9-82a7-448a-bbdd-3905220e1776
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153606586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3153606586
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.913220707
Short name T35
Test name
Test status
Simulation time 4105639171 ps
CPU time 26.91 seconds
Started Jun 21 04:43:46 PM PDT 24
Finished Jun 21 04:44:14 PM PDT 24
Peak memory 219120 kb
Host smart-3d2796ca-6d2b-4269-a605-6aa2d936d6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913220707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.913220707
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2513880119
Short name T325
Test name
Test status
Simulation time 18856144551 ps
CPU time 22.07 seconds
Started Jun 21 04:43:37 PM PDT 24
Finished Jun 21 04:44:00 PM PDT 24
Peak memory 219184 kb
Host smart-148a8eec-f3de-4105-9bed-8f47318aebf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2513880119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2513880119
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.703137609
Short name T111
Test name
Test status
Simulation time 6781515621 ps
CPU time 55.3 seconds
Started Jun 21 04:43:39 PM PDT 24
Finished Jun 21 04:44:35 PM PDT 24
Peak memory 216584 kb
Host smart-d7649fe8-7657-47fc-b995-59d14fbc1c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703137609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.703137609
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1593531440
Short name T146
Test name
Test status
Simulation time 8059949164 ps
CPU time 107.71 seconds
Started Jun 21 04:43:27 PM PDT 24
Finished Jun 21 04:45:20 PM PDT 24
Peak memory 220732 kb
Host smart-fa50ecca-c22f-439f-b087-2af9130c6dc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593531440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1593531440
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2840425638
Short name T235
Test name
Test status
Simulation time 167715422 ps
CPU time 8.62 seconds
Started Jun 21 04:43:51 PM PDT 24
Finished Jun 21 04:44:01 PM PDT 24
Peak memory 216928 kb
Host smart-204dc90c-eb1d-411f-a5c8-2bba27e9ae7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840425638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2840425638
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2642200821
Short name T253
Test name
Test status
Simulation time 14293848631 ps
CPU time 316.23 seconds
Started Jun 21 04:43:29 PM PDT 24
Finished Jun 21 04:48:50 PM PDT 24
Peak memory 217348 kb
Host smart-7b50a08b-9b8a-438c-bbe7-e3349deb09c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642200821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2642200821
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1816064613
Short name T239
Test name
Test status
Simulation time 1376119967 ps
CPU time 19.12 seconds
Started Jun 21 04:43:25 PM PDT 24
Finished Jun 21 04:43:50 PM PDT 24
Peak memory 219112 kb
Host smart-7e26f0e4-33e6-46b3-b605-a4710b08a57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816064613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1816064613
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.842745953
Short name T318
Test name
Test status
Simulation time 707492172 ps
CPU time 10.56 seconds
Started Jun 21 04:43:26 PM PDT 24
Finished Jun 21 04:43:42 PM PDT 24
Peak memory 218780 kb
Host smart-8285d690-e101-4b42-9057-77344c41515d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=842745953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.842745953
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1734445600
Short name T49
Test name
Test status
Simulation time 343936085 ps
CPU time 19.9 seconds
Started Jun 21 04:43:27 PM PDT 24
Finished Jun 21 04:43:52 PM PDT 24
Peak memory 216464 kb
Host smart-b4b5517e-9a22-44a9-b1cd-9cb322380bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734445600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1734445600
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.591482196
Short name T115
Test name
Test status
Simulation time 34807992137 ps
CPU time 78.57 seconds
Started Jun 21 04:43:45 PM PDT 24
Finished Jun 21 04:45:04 PM PDT 24
Peak memory 219156 kb
Host smart-40dac51d-6461-4b17-bc11-83f48e72acf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591482196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.591482196
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2265043463
Short name T172
Test name
Test status
Simulation time 15050720472 ps
CPU time 31.14 seconds
Started Jun 21 04:43:33 PM PDT 24
Finished Jun 21 04:44:07 PM PDT 24
Peak memory 217284 kb
Host smart-8b4e24c6-4c54-40b6-8810-da2779176a0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265043463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2265043463
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.396168892
Short name T219
Test name
Test status
Simulation time 123745810719 ps
CPU time 460.85 seconds
Started Jun 21 04:43:43 PM PDT 24
Finished Jun 21 04:51:25 PM PDT 24
Peak memory 216916 kb
Host smart-b4cb5629-7e62-4377-96bd-f010846fc151
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396168892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.396168892
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3359365405
Short name T151
Test name
Test status
Simulation time 7896753797 ps
CPU time 22.97 seconds
Started Jun 21 04:43:41 PM PDT 24
Finished Jun 21 04:44:05 PM PDT 24
Peak memory 211744 kb
Host smart-f5103cbf-1371-430f-92c1-855eb1fa5295
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3359365405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3359365405
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3372823907
Short name T227
Test name
Test status
Simulation time 10451699925 ps
CPU time 52.8 seconds
Started Jun 21 04:43:45 PM PDT 24
Finished Jun 21 04:44:39 PM PDT 24
Peak memory 216576 kb
Host smart-a11fd0b9-2a7f-4d08-a694-f249bbfe6e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372823907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3372823907
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3318825791
Short name T247
Test name
Test status
Simulation time 159517396704 ps
CPU time 152.36 seconds
Started Jun 21 04:43:48 PM PDT 24
Finished Jun 21 04:46:21 PM PDT 24
Peak memory 219848 kb
Host smart-0e5edc68-a901-450f-a483-bef527de11a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318825791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3318825791
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1574857785
Short name T45
Test name
Test status
Simulation time 39008452082 ps
CPU time 1180.73 seconds
Started Jun 21 04:43:41 PM PDT 24
Finished Jun 21 05:03:23 PM PDT 24
Peak memory 231332 kb
Host smart-b39c5930-dd16-4ce7-8b98-33eb85074c31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574857785 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.1574857785
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.4105341455
Short name T180
Test name
Test status
Simulation time 916537777 ps
CPU time 8.61 seconds
Started Jun 21 04:43:26 PM PDT 24
Finished Jun 21 04:43:40 PM PDT 24
Peak memory 216916 kb
Host smart-d9ac8681-9991-47ea-a748-800d64f6387e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105341455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.4105341455
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1451036646
Short name T322
Test name
Test status
Simulation time 231373664436 ps
CPU time 1013.7 seconds
Started Jun 21 04:43:48 PM PDT 24
Finished Jun 21 05:00:43 PM PDT 24
Peak memory 217648 kb
Host smart-cb892b53-91aa-44ba-9c0d-7881c840959d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451036646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1451036646
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1683300672
Short name T222
Test name
Test status
Simulation time 7866473494 ps
CPU time 32.53 seconds
Started Jun 21 04:43:27 PM PDT 24
Finished Jun 21 04:44:05 PM PDT 24
Peak memory 219156 kb
Host smart-879948c8-d753-493b-99df-793a5dc269b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683300672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1683300672
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3411119341
Short name T149
Test name
Test status
Simulation time 1687620080 ps
CPU time 12.88 seconds
Started Jun 21 04:43:47 PM PDT 24
Finished Jun 21 04:44:01 PM PDT 24
Peak memory 218536 kb
Host smart-18bc2c8b-b677-4a9c-97f1-386b8ab1f182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3411119341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3411119341
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3481288090
Short name T262
Test name
Test status
Simulation time 903694859 ps
CPU time 33.25 seconds
Started Jun 21 04:43:48 PM PDT 24
Finished Jun 21 04:44:22 PM PDT 24
Peak memory 219096 kb
Host smart-03fec5ed-831a-4d94-96b3-7040b1aa1b3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481288090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3481288090
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.650488221
Short name T135
Test name
Test status
Simulation time 1353650916 ps
CPU time 16.91 seconds
Started Jun 21 04:43:27 PM PDT 24
Finished Jun 21 04:43:49 PM PDT 24
Peak memory 216880 kb
Host smart-aa9907a6-92e5-4880-a014-1970540395bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650488221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.650488221
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2216292220
Short name T350
Test name
Test status
Simulation time 138491390161 ps
CPU time 492.45 seconds
Started Jun 21 04:43:34 PM PDT 24
Finished Jun 21 04:51:48 PM PDT 24
Peak memory 244684 kb
Host smart-e6a54e35-c897-45db-b022-64aa5c72ffdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216292220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2216292220
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.527963991
Short name T202
Test name
Test status
Simulation time 90551839419 ps
CPU time 64.17 seconds
Started Jun 21 04:43:44 PM PDT 24
Finished Jun 21 04:44:49 PM PDT 24
Peak memory 219136 kb
Host smart-0815f776-0476-40fa-9279-8537723dabb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527963991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.527963991
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2159515110
Short name T178
Test name
Test status
Simulation time 4350788680 ps
CPU time 34.9 seconds
Started Jun 21 04:43:28 PM PDT 24
Finished Jun 21 04:44:08 PM PDT 24
Peak memory 211560 kb
Host smart-1b615a1e-6195-4f88-ae91-eb9ad2e08578
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2159515110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2159515110
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2894777826
Short name T334
Test name
Test status
Simulation time 706998042 ps
CPU time 25.42 seconds
Started Jun 21 04:43:46 PM PDT 24
Finished Jun 21 04:44:12 PM PDT 24
Peak memory 216744 kb
Host smart-7805dea3-8339-4b3e-be1c-efadb150e09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894777826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2894777826
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2481491930
Short name T177
Test name
Test status
Simulation time 6056513566 ps
CPU time 76.26 seconds
Started Jun 21 04:43:41 PM PDT 24
Finished Jun 21 04:44:59 PM PDT 24
Peak memory 219072 kb
Host smart-5d6aac37-4a46-4b8b-9e7e-5b31aeb2d606
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481491930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2481491930
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1318521589
Short name T40
Test name
Test status
Simulation time 38184347421 ps
CPU time 723.89 seconds
Started Jun 21 04:43:48 PM PDT 24
Finished Jun 21 04:55:53 PM PDT 24
Peak memory 235676 kb
Host smart-c6bbb32e-3531-4358-a46e-a8ac222c1453
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318521589 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.1318521589
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2098165076
Short name T198
Test name
Test status
Simulation time 40868919461 ps
CPU time 21.47 seconds
Started Jun 21 04:43:50 PM PDT 24
Finished Jun 21 04:44:12 PM PDT 24
Peak memory 217304 kb
Host smart-ef2c856f-ef53-446f-9609-fe8b9d910d50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098165076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2098165076
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1041714448
Short name T252
Test name
Test status
Simulation time 123135506761 ps
CPU time 303.17 seconds
Started Jun 21 04:43:34 PM PDT 24
Finished Jun 21 04:48:40 PM PDT 24
Peak memory 233324 kb
Host smart-e0adacd6-f71f-4e43-bf54-dcd8b97cf633
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041714448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1041714448
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3038896314
Short name T269
Test name
Test status
Simulation time 4097596680 ps
CPU time 45.47 seconds
Started Jun 21 04:44:03 PM PDT 24
Finished Jun 21 04:44:50 PM PDT 24
Peak memory 219088 kb
Host smart-a734411e-f25e-49e0-ac5e-c46e07b9d9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038896314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3038896314
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2944057333
Short name T231
Test name
Test status
Simulation time 4097726592 ps
CPU time 33.53 seconds
Started Jun 21 04:43:39 PM PDT 24
Finished Jun 21 04:44:14 PM PDT 24
Peak memory 219192 kb
Host smart-fa43e5fb-0041-4731-adcc-fce378cb1a36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2944057333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2944057333
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.273989258
Short name T1
Test name
Test status
Simulation time 8359135098 ps
CPU time 43.6 seconds
Started Jun 21 04:43:47 PM PDT 24
Finished Jun 21 04:44:32 PM PDT 24
Peak memory 217176 kb
Host smart-3a1d21c5-3a86-4282-ab81-016ae7db6cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273989258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.273989258
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3896158838
Short name T110
Test name
Test status
Simulation time 36097502415 ps
CPU time 151.44 seconds
Started Jun 21 04:43:44 PM PDT 24
Finished Jun 21 04:46:17 PM PDT 24
Peak memory 221672 kb
Host smart-b074ea94-60be-4c4e-b9bf-d9e3aafd7631
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896158838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3896158838
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3794481782
Short name T25
Test name
Test status
Simulation time 5691074248 ps
CPU time 24.36 seconds
Started Jun 21 04:43:58 PM PDT 24
Finished Jun 21 04:44:24 PM PDT 24
Peak memory 217196 kb
Host smart-368d22e1-bafa-4986-a460-8994fafc9317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794481782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3794481782
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.836347039
Short name T160
Test name
Test status
Simulation time 58134196107 ps
CPU time 586.81 seconds
Started Jun 21 04:43:56 PM PDT 24
Finished Jun 21 04:53:44 PM PDT 24
Peak memory 225348 kb
Host smart-b513a3df-3571-413e-8ffb-67d3a0dbf568
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836347039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.836347039
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4258888446
Short name T315
Test name
Test status
Simulation time 349694675 ps
CPU time 19.22 seconds
Started Jun 21 04:43:58 PM PDT 24
Finished Jun 21 04:44:19 PM PDT 24
Peak memory 219048 kb
Host smart-c6930880-02f3-43b2-92a3-714f5e4a2320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258888446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4258888446
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3617139043
Short name T304
Test name
Test status
Simulation time 182975624 ps
CPU time 10.7 seconds
Started Jun 21 04:44:06 PM PDT 24
Finished Jun 21 04:44:19 PM PDT 24
Peak memory 219080 kb
Host smart-c8b3156c-db29-4766-9a17-02f15c2896ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3617139043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3617139043
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1695281076
Short name T274
Test name
Test status
Simulation time 9611885678 ps
CPU time 36.08 seconds
Started Jun 21 04:43:56 PM PDT 24
Finished Jun 21 04:44:33 PM PDT 24
Peak memory 217492 kb
Host smart-07d1bffb-1235-4a57-ade2-f3f1d4479725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695281076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1695281076
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1423876058
Short name T152
Test name
Test status
Simulation time 3996376231 ps
CPU time 29.21 seconds
Started Jun 21 04:44:02 PM PDT 24
Finished Jun 21 04:44:33 PM PDT 24
Peak memory 214380 kb
Host smart-c0665c34-3ebc-4da6-b033-53533c67e11d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423876058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1423876058
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3158469247
Short name T138
Test name
Test status
Simulation time 4667876106 ps
CPU time 28.01 seconds
Started Jun 21 04:43:56 PM PDT 24
Finished Jun 21 04:44:25 PM PDT 24
Peak memory 217176 kb
Host smart-7d333f9d-ab0c-4154-8d58-9ba1b725029f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158469247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3158469247
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3129497887
Short name T37
Test name
Test status
Simulation time 395243777032 ps
CPU time 420.78 seconds
Started Jun 21 04:44:08 PM PDT 24
Finished Jun 21 04:51:11 PM PDT 24
Peak memory 234280 kb
Host smart-8fb55d76-aeef-425d-b90f-d3a4c276b626
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129497887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3129497887
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3220695972
Short name T34
Test name
Test status
Simulation time 45749258772 ps
CPU time 66.11 seconds
Started Jun 21 04:43:59 PM PDT 24
Finished Jun 21 04:45:07 PM PDT 24
Peak memory 219088 kb
Host smart-021918e1-4989-4b8c-b41e-0defa57c3555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220695972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3220695972
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3810580381
Short name T50
Test name
Test status
Simulation time 2713805266 ps
CPU time 26.45 seconds
Started Jun 21 04:43:58 PM PDT 24
Finished Jun 21 04:44:27 PM PDT 24
Peak memory 219288 kb
Host smart-ee7892f9-1e9c-4b66-ae0c-0fcb3da25fd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3810580381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3810580381
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.377819480
Short name T323
Test name
Test status
Simulation time 347849264 ps
CPU time 20.59 seconds
Started Jun 21 04:43:58 PM PDT 24
Finished Jun 21 04:44:21 PM PDT 24
Peak memory 216304 kb
Host smart-6b9d8bc3-410e-4a66-a8ee-8763f580674a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377819480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.377819480
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1272221760
Short name T319
Test name
Test status
Simulation time 10017254225 ps
CPU time 94.22 seconds
Started Jun 21 04:43:55 PM PDT 24
Finished Jun 21 04:45:31 PM PDT 24
Peak memory 219556 kb
Host smart-683d5367-123f-462c-bf09-dd36c2aced9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272221760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1272221760
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2220603186
Short name T59
Test name
Test status
Simulation time 27437031932 ps
CPU time 32.16 seconds
Started Jun 21 04:43:53 PM PDT 24
Finished Jun 21 04:44:26 PM PDT 24
Peak memory 217236 kb
Host smart-c0f72ef2-9ef3-4036-8275-8320c2189b2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220603186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2220603186
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3500237765
Short name T189
Test name
Test status
Simulation time 27976940223 ps
CPU time 378.46 seconds
Started Jun 21 04:44:01 PM PDT 24
Finished Jun 21 04:50:22 PM PDT 24
Peak memory 238852 kb
Host smart-2f14b31b-b6b4-4fc6-8605-80326e020512
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500237765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3500237765
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3420926507
Short name T213
Test name
Test status
Simulation time 44404516283 ps
CPU time 69.8 seconds
Started Jun 21 04:43:52 PM PDT 24
Finished Jun 21 04:45:03 PM PDT 24
Peak memory 219040 kb
Host smart-76cb63e9-ef16-44b1-ae14-5bf1d644f30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420926507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3420926507
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2975144104
Short name T156
Test name
Test status
Simulation time 2472980429 ps
CPU time 24.87 seconds
Started Jun 21 04:43:51 PM PDT 24
Finished Jun 21 04:44:17 PM PDT 24
Peak memory 219256 kb
Host smart-eb50e75f-e893-4967-b2c0-23c3fbf9ea1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2975144104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2975144104
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2058556036
Short name T308
Test name
Test status
Simulation time 2492948092 ps
CPU time 38.55 seconds
Started Jun 21 04:43:57 PM PDT 24
Finished Jun 21 04:44:38 PM PDT 24
Peak memory 216684 kb
Host smart-14d0b086-bb75-468b-b9e6-dc3a60aa027b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058556036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2058556036
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2398681164
Short name T277
Test name
Test status
Simulation time 63279191321 ps
CPU time 157.25 seconds
Started Jun 21 04:43:58 PM PDT 24
Finished Jun 21 04:46:37 PM PDT 24
Peak memory 220336 kb
Host smart-0b446844-3b54-44dc-8c35-cd46444881ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398681164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2398681164
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.4258796649
Short name T57
Test name
Test status
Simulation time 8810601430 ps
CPU time 21.73 seconds
Started Jun 21 04:43:55 PM PDT 24
Finished Jun 21 04:44:18 PM PDT 24
Peak memory 217424 kb
Host smart-3d71bd46-723f-4ac8-923b-490e6a347edc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258796649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.4258796649
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.982705314
Short name T30
Test name
Test status
Simulation time 125981280934 ps
CPU time 493.95 seconds
Started Jun 21 04:43:56 PM PDT 24
Finished Jun 21 04:52:12 PM PDT 24
Peak memory 233648 kb
Host smart-3d636f47-b7f2-4809-bfe0-be484995aef3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982705314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.982705314
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.4064572239
Short name T114
Test name
Test status
Simulation time 17726512964 ps
CPU time 71.32 seconds
Started Jun 21 04:43:56 PM PDT 24
Finished Jun 21 04:45:09 PM PDT 24
Peak memory 219020 kb
Host smart-2fcbd65e-2a17-4ca6-a54e-e17cc638edce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064572239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.4064572239
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3530542905
Short name T60
Test name
Test status
Simulation time 4512262287 ps
CPU time 17.45 seconds
Started Jun 21 04:43:56 PM PDT 24
Finished Jun 21 04:44:16 PM PDT 24
Peak memory 219084 kb
Host smart-d76d6674-d0a8-490a-8aaf-feaa535e1f25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3530542905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3530542905
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2833815182
Short name T73
Test name
Test status
Simulation time 1558403382 ps
CPU time 20.14 seconds
Started Jun 21 04:43:57 PM PDT 24
Finished Jun 21 04:44:19 PM PDT 24
Peak memory 215408 kb
Host smart-5febd599-91ff-4ae3-9447-4a2b3af84194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833815182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2833815182
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1196839719
Short name T250
Test name
Test status
Simulation time 375492149 ps
CPU time 27.61 seconds
Started Jun 21 04:43:56 PM PDT 24
Finished Jun 21 04:44:26 PM PDT 24
Peak memory 217236 kb
Host smart-ac2907a3-5b6a-4ec1-971a-0d651d1e30b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196839719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1196839719
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1354192647
Short name T341
Test name
Test status
Simulation time 172434105 ps
CPU time 8.56 seconds
Started Jun 21 04:43:28 PM PDT 24
Finished Jun 21 04:43:42 PM PDT 24
Peak memory 216760 kb
Host smart-0045e511-1718-41f7-943a-b85993f080ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354192647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1354192647
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2360412663
Short name T305
Test name
Test status
Simulation time 96564586437 ps
CPU time 844.93 seconds
Started Jun 21 04:43:25 PM PDT 24
Finished Jun 21 04:57:40 PM PDT 24
Peak memory 239364 kb
Host smart-7d39cb76-9354-43b5-bb97-cb50d17fc85a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360412663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2360412663
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1715011751
Short name T230
Test name
Test status
Simulation time 7871341154 ps
CPU time 41.39 seconds
Started Jun 21 04:43:49 PM PDT 24
Finished Jun 21 04:44:32 PM PDT 24
Peak memory 219088 kb
Host smart-81497860-6b7c-49a5-a1a0-03779b025e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715011751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1715011751
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3979133919
Short name T199
Test name
Test status
Simulation time 2299130773 ps
CPU time 23.85 seconds
Started Jun 21 04:43:22 PM PDT 24
Finished Jun 21 04:43:50 PM PDT 24
Peak memory 219184 kb
Host smart-717a247d-3c1a-4324-a571-89745aa160df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3979133919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3979133919
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1430180794
Short name T7
Test name
Test status
Simulation time 6500147544 ps
CPU time 128.19 seconds
Started Jun 21 04:43:16 PM PDT 24
Finished Jun 21 04:45:28 PM PDT 24
Peak memory 235852 kb
Host smart-1fa09025-d78d-4b3e-91ca-a381385f6786
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430180794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1430180794
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3385288879
Short name T291
Test name
Test status
Simulation time 346602587 ps
CPU time 20.24 seconds
Started Jun 21 04:43:26 PM PDT 24
Finished Jun 21 04:43:52 PM PDT 24
Peak memory 215672 kb
Host smart-1862a3e4-74a9-4231-8f1a-566bc0408db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385288879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3385288879
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1587525931
Short name T243
Test name
Test status
Simulation time 6468792424 ps
CPU time 23.78 seconds
Started Jun 21 04:43:16 PM PDT 24
Finished Jun 21 04:43:44 PM PDT 24
Peak memory 214484 kb
Host smart-747cda8e-55cd-4380-a5b0-3e2746d62a60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587525931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1587525931
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3620926615
Short name T307
Test name
Test status
Simulation time 5696988781 ps
CPU time 25.45 seconds
Started Jun 21 04:44:08 PM PDT 24
Finished Jun 21 04:44:35 PM PDT 24
Peak memory 217756 kb
Host smart-cbe9d3c1-89f5-4ead-a99e-d454feea5e06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620926615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3620926615
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2074883860
Short name T317
Test name
Test status
Simulation time 16034079313 ps
CPU time 241.99 seconds
Started Jun 21 04:43:58 PM PDT 24
Finished Jun 21 04:48:02 PM PDT 24
Peak memory 238004 kb
Host smart-9e1d3a50-78fb-40ec-aee1-dc3bb200e46c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074883860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2074883860
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.4282754236
Short name T228
Test name
Test status
Simulation time 11479752876 ps
CPU time 48.27 seconds
Started Jun 21 04:44:04 PM PDT 24
Finished Jun 21 04:44:54 PM PDT 24
Peak memory 219136 kb
Host smart-050d444a-c71c-4f79-8c10-cd51f37335ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282754236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.4282754236
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2823764338
Short name T95
Test name
Test status
Simulation time 635939976 ps
CPU time 10.54 seconds
Started Jun 21 04:44:00 PM PDT 24
Finished Jun 21 04:44:13 PM PDT 24
Peak memory 219108 kb
Host smart-b500cbbd-2988-4849-9a59-5c644767a5b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2823764338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2823764338
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1216299761
Short name T216
Test name
Test status
Simulation time 2139260533 ps
CPU time 20.49 seconds
Started Jun 21 04:43:59 PM PDT 24
Finished Jun 21 04:44:22 PM PDT 24
Peak memory 215304 kb
Host smart-7260059a-7540-4d5b-95d8-407f0aaa2375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216299761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1216299761
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2299427030
Short name T154
Test name
Test status
Simulation time 55623031050 ps
CPU time 238.06 seconds
Started Jun 21 04:43:54 PM PDT 24
Finished Jun 21 04:47:53 PM PDT 24
Peak memory 222036 kb
Host smart-b2f3d11e-704d-47a4-a3f8-50b5bedb8fdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299427030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2299427030
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1356905397
Short name T210
Test name
Test status
Simulation time 176216194 ps
CPU time 8.37 seconds
Started Jun 21 04:44:03 PM PDT 24
Finished Jun 21 04:44:13 PM PDT 24
Peak memory 216860 kb
Host smart-06c45579-3995-4162-a7dd-b37cc9647ae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356905397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1356905397
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3247681338
Short name T248
Test name
Test status
Simulation time 223772010144 ps
CPU time 525.86 seconds
Started Jun 21 04:44:02 PM PDT 24
Finished Jun 21 04:52:50 PM PDT 24
Peak memory 235424 kb
Host smart-948a51ae-8059-42c2-8314-a61a5f255d76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247681338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3247681338
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1034642856
Short name T292
Test name
Test status
Simulation time 1321195697 ps
CPU time 19.39 seconds
Started Jun 21 04:43:55 PM PDT 24
Finished Jun 21 04:44:16 PM PDT 24
Peak memory 219024 kb
Host smart-e8536327-8ad5-4fdf-b5e5-8fd8caadddf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034642856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1034642856
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1776924441
Short name T10
Test name
Test status
Simulation time 1572455753 ps
CPU time 20.55 seconds
Started Jun 21 04:44:01 PM PDT 24
Finished Jun 21 04:44:23 PM PDT 24
Peak memory 219216 kb
Host smart-0fc33566-5781-42dd-8048-dadebaf931dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1776924441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1776924441
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.496277011
Short name T283
Test name
Test status
Simulation time 7264200303 ps
CPU time 60.58 seconds
Started Jun 21 04:43:57 PM PDT 24
Finished Jun 21 04:45:00 PM PDT 24
Peak memory 216964 kb
Host smart-3265817d-e83c-402b-b863-1df3a15272ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496277011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.496277011
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1636871189
Short name T191
Test name
Test status
Simulation time 22595625926 ps
CPU time 78.34 seconds
Started Jun 21 04:43:53 PM PDT 24
Finished Jun 21 04:45:12 PM PDT 24
Peak memory 219140 kb
Host smart-f9ca2797-11d9-4c5e-9198-f6bd2eb36345
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636871189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1636871189
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3295710955
Short name T137
Test name
Test status
Simulation time 5570800163 ps
CPU time 25.55 seconds
Started Jun 21 04:43:57 PM PDT 24
Finished Jun 21 04:44:25 PM PDT 24
Peak memory 217220 kb
Host smart-321e75b9-8852-49cc-879e-152f8a4cfbee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295710955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3295710955
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1258032502
Short name T120
Test name
Test status
Simulation time 664614899 ps
CPU time 19.04 seconds
Started Jun 21 04:44:02 PM PDT 24
Finished Jun 21 04:44:23 PM PDT 24
Peak memory 219144 kb
Host smart-0d470b87-83c0-45d9-85a8-d50e9e6f4647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258032502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1258032502
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.4122328305
Short name T18
Test name
Test status
Simulation time 3434668920 ps
CPU time 15.23 seconds
Started Jun 21 04:44:02 PM PDT 24
Finished Jun 21 04:44:19 PM PDT 24
Peak memory 219184 kb
Host smart-e65ee4aa-dd7b-465a-a5a0-564a720ca5d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4122328305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.4122328305
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2774113525
Short name T200
Test name
Test status
Simulation time 26547658933 ps
CPU time 74.57 seconds
Started Jun 21 04:44:01 PM PDT 24
Finished Jun 21 04:45:18 PM PDT 24
Peak memory 216044 kb
Host smart-052eb49b-6d67-471b-8559-df1a648eab21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774113525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2774113525
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.389725058
Short name T332
Test name
Test status
Simulation time 3603961483 ps
CPU time 43.96 seconds
Started Jun 21 04:43:58 PM PDT 24
Finished Jun 21 04:44:43 PM PDT 24
Peak memory 219164 kb
Host smart-76ee1f2c-565d-4ade-b0d3-71be3f414ab3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389725058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.389725058
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.75398807
Short name T240
Test name
Test status
Simulation time 12558517427 ps
CPU time 27.49 seconds
Started Jun 21 04:44:02 PM PDT 24
Finished Jun 21 04:44:32 PM PDT 24
Peak memory 217188 kb
Host smart-b82f47b0-ccd9-495f-86fa-87183c05770f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75398807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.75398807
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.655835826
Short name T9
Test name
Test status
Simulation time 359307993565 ps
CPU time 843.51 seconds
Started Jun 21 04:44:04 PM PDT 24
Finished Jun 21 04:58:10 PM PDT 24
Peak memory 234324 kb
Host smart-408bb330-f45e-45ff-a361-52bb0442269b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655835826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.655835826
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3365458789
Short name T206
Test name
Test status
Simulation time 86466049672 ps
CPU time 55.06 seconds
Started Jun 21 04:43:52 PM PDT 24
Finished Jun 21 04:44:48 PM PDT 24
Peak memory 219112 kb
Host smart-9f4b97ba-6f6b-4107-a0e0-3a8a5496f7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365458789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3365458789
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2814019503
Short name T303
Test name
Test status
Simulation time 180402600 ps
CPU time 11.12 seconds
Started Jun 21 04:43:57 PM PDT 24
Finished Jun 21 04:44:10 PM PDT 24
Peak memory 219064 kb
Host smart-e003fe70-2fe8-43cc-b3ae-2448020b78b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2814019503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2814019503
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1730243432
Short name T215
Test name
Test status
Simulation time 49156277015 ps
CPU time 68.65 seconds
Started Jun 21 04:44:06 PM PDT 24
Finished Jun 21 04:45:17 PM PDT 24
Peak memory 217140 kb
Host smart-7f85c3a4-700d-48cf-9270-91508639a9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730243432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1730243432
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.304770365
Short name T209
Test name
Test status
Simulation time 7474695816 ps
CPU time 73.64 seconds
Started Jun 21 04:44:07 PM PDT 24
Finished Jun 21 04:45:23 PM PDT 24
Peak memory 215436 kb
Host smart-90bfb319-2d71-47c9-9adc-aac58c36a923
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304770365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.304770365
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1969359892
Short name T168
Test name
Test status
Simulation time 6678543541 ps
CPU time 27.95 seconds
Started Jun 21 04:44:01 PM PDT 24
Finished Jun 21 04:44:31 PM PDT 24
Peak memory 217196 kb
Host smart-003a0c38-1812-4676-a02a-89ad89001618
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969359892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1969359892
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.863696353
Short name T162
Test name
Test status
Simulation time 32406875844 ps
CPU time 241.27 seconds
Started Jun 21 04:43:59 PM PDT 24
Finished Jun 21 04:48:02 PM PDT 24
Peak memory 232472 kb
Host smart-7747d36b-f976-4ee8-821b-a58f1b41e83e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863696353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.863696353
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3963841147
Short name T196
Test name
Test status
Simulation time 1028157161 ps
CPU time 26.83 seconds
Started Jun 21 04:44:05 PM PDT 24
Finished Jun 21 04:44:34 PM PDT 24
Peak memory 218316 kb
Host smart-d2afb799-3868-4022-a9d6-7c2b7cd4e90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963841147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3963841147
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2319927290
Short name T314
Test name
Test status
Simulation time 10386916571 ps
CPU time 24.3 seconds
Started Jun 21 04:43:59 PM PDT 24
Finished Jun 21 04:44:26 PM PDT 24
Peak memory 219172 kb
Host smart-917d8a9d-7b12-4180-975b-457ce5558efe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2319927290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2319927290
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2303705985
Short name T234
Test name
Test status
Simulation time 11141769850 ps
CPU time 41.53 seconds
Started Jun 21 04:44:04 PM PDT 24
Finished Jun 21 04:44:47 PM PDT 24
Peak memory 216068 kb
Host smart-c0f2f808-fb58-4bf0-b622-a57c0cb8fd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303705985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2303705985
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1883363644
Short name T185
Test name
Test status
Simulation time 5075739680 ps
CPU time 28.99 seconds
Started Jun 21 04:44:06 PM PDT 24
Finished Jun 21 04:44:36 PM PDT 24
Peak memory 219004 kb
Host smart-615078aa-feab-49cd-893b-af6e9a84e048
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883363644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1883363644
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2819988922
Short name T44
Test name
Test status
Simulation time 36633579473 ps
CPU time 1604.45 seconds
Started Jun 21 04:44:01 PM PDT 24
Finished Jun 21 05:10:48 PM PDT 24
Peak memory 244272 kb
Host smart-ddb461d4-4dae-4f13-be08-6215f50b2865
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819988922 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2819988922
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1896531539
Short name T347
Test name
Test status
Simulation time 8159404913 ps
CPU time 21.27 seconds
Started Jun 21 04:44:04 PM PDT 24
Finished Jun 21 04:44:28 PM PDT 24
Peak memory 217256 kb
Host smart-35fb9526-ddac-47be-8dff-76dc3975e4df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896531539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1896531539
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.619653302
Short name T348
Test name
Test status
Simulation time 41992094062 ps
CPU time 269.02 seconds
Started Jun 21 04:44:00 PM PDT 24
Finished Jun 21 04:48:31 PM PDT 24
Peak memory 241488 kb
Host smart-ec9eeb4d-0a3f-460f-883c-6b55085cf2cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619653302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.619653302
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2491327280
Short name T257
Test name
Test status
Simulation time 3186858507 ps
CPU time 34.51 seconds
Started Jun 21 04:44:03 PM PDT 24
Finished Jun 21 04:44:40 PM PDT 24
Peak memory 219100 kb
Host smart-32df5c39-373d-4b70-984f-48484c3926ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491327280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2491327280
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2213170391
Short name T261
Test name
Test status
Simulation time 4271246421 ps
CPU time 34.36 seconds
Started Jun 21 04:43:57 PM PDT 24
Finished Jun 21 04:44:33 PM PDT 24
Peak memory 211180 kb
Host smart-1d913eb5-b275-44b3-b105-322b24c7811f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2213170391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2213170391
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2242280372
Short name T174
Test name
Test status
Simulation time 1447955637 ps
CPU time 20.49 seconds
Started Jun 21 04:44:05 PM PDT 24
Finished Jun 21 04:44:27 PM PDT 24
Peak memory 215832 kb
Host smart-9e9f234c-610f-4e42-afb4-73e845ac4b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242280372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2242280372
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.138763094
Short name T145
Test name
Test status
Simulation time 1800676833 ps
CPU time 56.84 seconds
Started Jun 21 04:43:55 PM PDT 24
Finished Jun 21 04:44:53 PM PDT 24
Peak memory 219076 kb
Host smart-dd28ccf1-a115-413b-9f3d-a1dc51cdade6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138763094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.138763094
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.703338297
Short name T23
Test name
Test status
Simulation time 2606518167 ps
CPU time 23.97 seconds
Started Jun 21 04:44:04 PM PDT 24
Finished Jun 21 04:44:30 PM PDT 24
Peak memory 216964 kb
Host smart-017f525d-98e9-4d9b-a1aa-3cf4292cb68f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703338297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.703338297
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1731855631
Short name T254
Test name
Test status
Simulation time 45103087882 ps
CPU time 298.34 seconds
Started Jun 21 04:44:04 PM PDT 24
Finished Jun 21 04:49:05 PM PDT 24
Peak memory 240488 kb
Host smart-3d523b0d-c045-4627-88d8-2d2216fef7a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731855631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1731855631
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.247878213
Short name T3
Test name
Test status
Simulation time 339144720 ps
CPU time 19.15 seconds
Started Jun 21 04:44:03 PM PDT 24
Finished Jun 21 04:44:25 PM PDT 24
Peak memory 219044 kb
Host smart-2d1a819d-05ea-44ed-a666-c6de515f01c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247878213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.247878213
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3459446167
Short name T181
Test name
Test status
Simulation time 7173424915 ps
CPU time 31.15 seconds
Started Jun 21 04:43:57 PM PDT 24
Finished Jun 21 04:44:30 PM PDT 24
Peak memory 219100 kb
Host smart-d6de48c8-21eb-4919-b6e5-72a27304b9c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3459446167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3459446167
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1718162574
Short name T298
Test name
Test status
Simulation time 26796840313 ps
CPU time 60.43 seconds
Started Jun 21 04:44:06 PM PDT 24
Finished Jun 21 04:45:09 PM PDT 24
Peak memory 217148 kb
Host smart-ab8e56bf-90ce-457e-84be-40c994dae116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718162574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1718162574
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2302242686
Short name T223
Test name
Test status
Simulation time 7062817044 ps
CPU time 70 seconds
Started Jun 21 04:43:57 PM PDT 24
Finished Jun 21 04:45:08 PM PDT 24
Peak memory 219052 kb
Host smart-c1695aa0-f9f3-4117-bbf0-0e9230aed82e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302242686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2302242686
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.377062053
Short name T93
Test name
Test status
Simulation time 7514501168 ps
CPU time 20.25 seconds
Started Jun 21 04:44:02 PM PDT 24
Finished Jun 21 04:44:25 PM PDT 24
Peak memory 216784 kb
Host smart-31ae21b1-466c-4b3c-8c5f-9db06fb17cf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377062053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.377062053
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2765782517
Short name T286
Test name
Test status
Simulation time 2780124024 ps
CPU time 36.86 seconds
Started Jun 21 04:44:10 PM PDT 24
Finished Jun 21 04:44:49 PM PDT 24
Peak memory 218872 kb
Host smart-fbe92676-0f45-4d15-a233-a2af0a2d0efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765782517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2765782517
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2350269261
Short name T266
Test name
Test status
Simulation time 2655160860 ps
CPU time 15.53 seconds
Started Jun 21 04:44:13 PM PDT 24
Finished Jun 21 04:44:31 PM PDT 24
Peak memory 219208 kb
Host smart-6ad55379-bdd3-40a7-b0b8-90739f510b7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2350269261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2350269261
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2145581523
Short name T233
Test name
Test status
Simulation time 4495675057 ps
CPU time 34.43 seconds
Started Jun 21 04:44:06 PM PDT 24
Finished Jun 21 04:44:43 PM PDT 24
Peak memory 216056 kb
Host smart-ae26f2bc-003e-4aca-8919-591ee6a8eb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145581523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2145581523
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1614678738
Short name T327
Test name
Test status
Simulation time 2257284940 ps
CPU time 38.04 seconds
Started Jun 21 04:44:07 PM PDT 24
Finished Jun 21 04:44:47 PM PDT 24
Peak memory 219848 kb
Host smart-61bdacff-5cbe-4143-8abd-bad98156109d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614678738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1614678738
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.662829926
Short name T119
Test name
Test status
Simulation time 1369056123 ps
CPU time 16.67 seconds
Started Jun 21 04:44:10 PM PDT 24
Finished Jun 21 04:44:29 PM PDT 24
Peak memory 216428 kb
Host smart-afc9d398-66e5-48a3-9c6d-19f3b1ffa4de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662829926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.662829926
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.256277097
Short name T293
Test name
Test status
Simulation time 2975970815 ps
CPU time 211.21 seconds
Started Jun 21 04:44:12 PM PDT 24
Finished Jun 21 04:47:46 PM PDT 24
Peak memory 237588 kb
Host smart-8931ccfa-09ac-4d7a-84d6-c6831e972d59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256277097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.256277097
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2567473745
Short name T224
Test name
Test status
Simulation time 14904950632 ps
CPU time 24.87 seconds
Started Jun 21 04:44:06 PM PDT 24
Finished Jun 21 04:44:33 PM PDT 24
Peak memory 217568 kb
Host smart-7abe94eb-fbc6-4897-9c99-3f54d522a272
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2567473745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2567473745
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3396508660
Short name T173
Test name
Test status
Simulation time 13216411496 ps
CPU time 37.33 seconds
Started Jun 21 04:44:22 PM PDT 24
Finished Jun 21 04:45:04 PM PDT 24
Peak memory 216596 kb
Host smart-5bd49ca4-6260-4282-bbf9-6ebe06070b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396508660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3396508660
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.653644797
Short name T313
Test name
Test status
Simulation time 6630260934 ps
CPU time 74.84 seconds
Started Jun 21 04:44:05 PM PDT 24
Finished Jun 21 04:45:22 PM PDT 24
Peak memory 219132 kb
Host smart-dd5d392c-a785-472e-92a7-7f9b1c336d19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653644797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.653644797
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1874782640
Short name T22
Test name
Test status
Simulation time 16840322519 ps
CPU time 31.83 seconds
Started Jun 21 04:44:09 PM PDT 24
Finished Jun 21 04:44:44 PM PDT 24
Peak memory 217208 kb
Host smart-34c431c2-d31c-43ee-8d78-a73dd164e21f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874782640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1874782640
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3169670000
Short name T212
Test name
Test status
Simulation time 17253002856 ps
CPU time 120.52 seconds
Started Jun 21 04:44:09 PM PDT 24
Finished Jun 21 04:46:12 PM PDT 24
Peak memory 224956 kb
Host smart-94b97f12-492b-4535-b501-502cd381cb55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169670000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3169670000
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3981979955
Short name T94
Test name
Test status
Simulation time 18492050945 ps
CPU time 46.88 seconds
Started Jun 21 04:44:07 PM PDT 24
Finished Jun 21 04:44:56 PM PDT 24
Peak memory 218920 kb
Host smart-e56781c7-854d-49c9-ba2b-9b33ec0faa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981979955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3981979955
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1985695457
Short name T236
Test name
Test status
Simulation time 1746058043 ps
CPU time 13.13 seconds
Started Jun 21 04:44:08 PM PDT 24
Finished Jun 21 04:44:23 PM PDT 24
Peak memory 218408 kb
Host smart-1be68dd9-b82d-4223-946a-8c1a7dbc0b11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1985695457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1985695457
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1851049831
Short name T72
Test name
Test status
Simulation time 8131944122 ps
CPU time 74.3 seconds
Started Jun 21 04:44:13 PM PDT 24
Finished Jun 21 04:45:30 PM PDT 24
Peak memory 216372 kb
Host smart-54fd13e5-5149-4a72-9eb4-6c4eb691a5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851049831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1851049831
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2966286838
Short name T36
Test name
Test status
Simulation time 80047339870 ps
CPU time 200.89 seconds
Started Jun 21 04:44:10 PM PDT 24
Finished Jun 21 04:47:34 PM PDT 24
Peak memory 220228 kb
Host smart-c26f2303-eba6-42a5-ab40-64834ec15967
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966286838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2966286838
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.570217181
Short name T46
Test name
Test status
Simulation time 59579993907 ps
CPU time 2261.08 seconds
Started Jun 21 04:44:10 PM PDT 24
Finished Jun 21 05:21:59 PM PDT 24
Peak memory 243808 kb
Host smart-d5f43e98-dc66-4667-bdec-0f2739b1681a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570217181 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.570217181
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1237254670
Short name T58
Test name
Test status
Simulation time 5070951566 ps
CPU time 17.98 seconds
Started Jun 21 04:43:23 PM PDT 24
Finished Jun 21 04:43:47 PM PDT 24
Peak memory 216676 kb
Host smart-45bcaf73-cef5-42a4-b51c-90c7eeb0dd35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237254670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1237254670
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.864223977
Short name T256
Test name
Test status
Simulation time 544932007952 ps
CPU time 1028.23 seconds
Started Jun 21 04:43:21 PM PDT 24
Finished Jun 21 05:00:34 PM PDT 24
Peak memory 225408 kb
Host smart-0ae4c7e9-22f4-4c31-aa28-1656a93f0d62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864223977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.864223977
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2996796825
Short name T89
Test name
Test status
Simulation time 2067682363 ps
CPU time 22.39 seconds
Started Jun 21 04:43:23 PM PDT 24
Finished Jun 21 04:43:50 PM PDT 24
Peak memory 214544 kb
Host smart-32ab5f00-4c29-4900-a4f5-58d641e331a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996796825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2996796825
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3182991523
Short name T335
Test name
Test status
Simulation time 1885976730 ps
CPU time 21.52 seconds
Started Jun 21 04:43:21 PM PDT 24
Finished Jun 21 04:43:46 PM PDT 24
Peak memory 211112 kb
Host smart-4e9b197f-ea03-4687-80d6-c99068f2acb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3182991523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3182991523
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.4103461227
Short name T186
Test name
Test status
Simulation time 6854891943 ps
CPU time 72.53 seconds
Started Jun 21 04:43:14 PM PDT 24
Finished Jun 21 04:44:31 PM PDT 24
Peak memory 216316 kb
Host smart-ab0d56c2-73fb-4811-a624-2cb79c942765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103461227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.4103461227
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3426539608
Short name T345
Test name
Test status
Simulation time 1873309432 ps
CPU time 41.02 seconds
Started Jun 21 04:43:14 PM PDT 24
Finished Jun 21 04:44:00 PM PDT 24
Peak memory 219064 kb
Host smart-b22a8461-6a44-4f88-9072-954095f1b266
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426539608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3426539608
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2169122366
Short name T43
Test name
Test status
Simulation time 40753408623 ps
CPU time 1563.31 seconds
Started Jun 21 04:43:21 PM PDT 24
Finished Jun 21 05:09:29 PM PDT 24
Peak memory 235652 kb
Host smart-a12ef344-28b5-4df4-9a27-66f3edeaebae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169122366 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2169122366
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3512743477
Short name T288
Test name
Test status
Simulation time 9422453870 ps
CPU time 19.77 seconds
Started Jun 21 04:43:21 PM PDT 24
Finished Jun 21 04:43:45 PM PDT 24
Peak memory 217148 kb
Host smart-f8c018be-f0fa-4769-bf0f-fbb64c3b2149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512743477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3512743477
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1392183811
Short name T232
Test name
Test status
Simulation time 73112322027 ps
CPU time 719.66 seconds
Started Jun 21 04:43:21 PM PDT 24
Finished Jun 21 04:55:24 PM PDT 24
Peak memory 234528 kb
Host smart-7d21e7ad-7347-4427-8339-f9209d9c5f4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392183811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1392183811
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3766569334
Short name T116
Test name
Test status
Simulation time 4181601017 ps
CPU time 45.53 seconds
Started Jun 21 04:43:24 PM PDT 24
Finished Jun 21 04:44:15 PM PDT 24
Peak memory 219136 kb
Host smart-eaf24213-0e3f-4c67-b8b9-25c55182e7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766569334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3766569334
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2342511552
Short name T218
Test name
Test status
Simulation time 3043348296 ps
CPU time 28.94 seconds
Started Jun 21 04:43:28 PM PDT 24
Finished Jun 21 04:44:02 PM PDT 24
Peak memory 217536 kb
Host smart-35fca278-4285-4718-b8d6-54f83e193fe2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2342511552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2342511552
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1342814527
Short name T190
Test name
Test status
Simulation time 351626355 ps
CPU time 20.61 seconds
Started Jun 21 04:43:35 PM PDT 24
Finished Jun 21 04:43:57 PM PDT 24
Peak memory 215596 kb
Host smart-b1892432-cd41-46e5-886a-93ec08cfed23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342814527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1342814527
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1965406859
Short name T320
Test name
Test status
Simulation time 7981846587 ps
CPU time 75.81 seconds
Started Jun 21 04:43:28 PM PDT 24
Finished Jun 21 04:44:49 PM PDT 24
Peak memory 220132 kb
Host smart-3ce52e8f-0950-45c4-a9ff-9350ea81228c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965406859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1965406859
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2002105990
Short name T125
Test name
Test status
Simulation time 3042742785 ps
CPU time 25.8 seconds
Started Jun 21 04:43:10 PM PDT 24
Finished Jun 21 04:43:39 PM PDT 24
Peak memory 216900 kb
Host smart-1e357dd5-8e2d-4121-9ed7-7b5f6504c519
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002105990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2002105990
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.969140300
Short name T299
Test name
Test status
Simulation time 60609137205 ps
CPU time 305.2 seconds
Started Jun 21 04:43:12 PM PDT 24
Finished Jun 21 04:48:22 PM PDT 24
Peak memory 234804 kb
Host smart-6dc18495-472a-4899-8330-b94196361a3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969140300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.969140300
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3361155174
Short name T96
Test name
Test status
Simulation time 689557250 ps
CPU time 19.26 seconds
Started Jun 21 04:43:49 PM PDT 24
Finished Jun 21 04:44:09 PM PDT 24
Peak memory 219048 kb
Host smart-76a64c1f-bbaf-403c-934f-cc42336825b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361155174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3361155174
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.857742914
Short name T17
Test name
Test status
Simulation time 4290631564 ps
CPU time 33.68 seconds
Started Jun 21 04:43:21 PM PDT 24
Finished Jun 21 04:43:59 PM PDT 24
Peak memory 219192 kb
Host smart-5bd16fea-1f70-4325-8214-c0422ccb3e0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=857742914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.857742914
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1113577890
Short name T237
Test name
Test status
Simulation time 31802560829 ps
CPU time 51.51 seconds
Started Jun 21 04:43:19 PM PDT 24
Finished Jun 21 04:44:14 PM PDT 24
Peak memory 214528 kb
Host smart-34a12c33-9559-4383-917b-0506bbe96b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113577890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1113577890
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1671747276
Short name T122
Test name
Test status
Simulation time 913293291 ps
CPU time 53.68 seconds
Started Jun 21 04:43:18 PM PDT 24
Finished Jun 21 04:44:15 PM PDT 24
Peak memory 219060 kb
Host smart-534875f7-d897-415e-85f2-12b7d2e7e1f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671747276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1671747276
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1248231203
Short name T295
Test name
Test status
Simulation time 174317902 ps
CPU time 8.5 seconds
Started Jun 21 04:43:21 PM PDT 24
Finished Jun 21 04:43:37 PM PDT 24
Peak memory 216804 kb
Host smart-986d95e3-6de1-4689-b7d8-6ae164e4fe3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248231203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1248231203
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.617177335
Short name T203
Test name
Test status
Simulation time 131364536482 ps
CPU time 371.69 seconds
Started Jun 21 04:43:08 PM PDT 24
Finished Jun 21 04:49:22 PM PDT 24
Peak memory 239212 kb
Host smart-173c2583-71dc-42c2-95ae-2f2d3f41db02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617177335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.617177335
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2439025602
Short name T150
Test name
Test status
Simulation time 9557892517 ps
CPU time 34.17 seconds
Started Jun 21 04:43:26 PM PDT 24
Finished Jun 21 04:44:06 PM PDT 24
Peak memory 218616 kb
Host smart-3eac0414-c533-46ba-ad79-295d7a47f9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439025602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2439025602
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3644686359
Short name T306
Test name
Test status
Simulation time 2611944522 ps
CPU time 24.37 seconds
Started Jun 21 04:43:25 PM PDT 24
Finished Jun 21 04:43:55 PM PDT 24
Peak memory 210824 kb
Host smart-c78f78c9-e1ee-4040-be14-50d5dd9ddb23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3644686359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3644686359
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2356898050
Short name T171
Test name
Test status
Simulation time 32212858746 ps
CPU time 63.71 seconds
Started Jun 21 04:43:28 PM PDT 24
Finished Jun 21 04:44:37 PM PDT 24
Peak memory 215752 kb
Host smart-ba54181e-1a4a-4eb3-957e-8ebd2b52bc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356898050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2356898050
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.879810860
Short name T338
Test name
Test status
Simulation time 14998044272 ps
CPU time 66.87 seconds
Started Jun 21 04:43:26 PM PDT 24
Finished Jun 21 04:44:38 PM PDT 24
Peak memory 222016 kb
Host smart-2ab634e9-15a7-4dfb-bb88-bb92a831bd88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879810860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.879810860
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3294417778
Short name T187
Test name
Test status
Simulation time 687959464 ps
CPU time 8.61 seconds
Started Jun 21 04:43:22 PM PDT 24
Finished Jun 21 04:43:35 PM PDT 24
Peak memory 216904 kb
Host smart-d056682d-c41a-4e5a-824d-3fbcb55f3a56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294417778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3294417778
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1904196240
Short name T204
Test name
Test status
Simulation time 230515213911 ps
CPU time 657.04 seconds
Started Jun 21 04:43:23 PM PDT 24
Finished Jun 21 04:54:25 PM PDT 24
Peak memory 232508 kb
Host smart-291eb503-4b07-4dcb-870d-c0f97f1c8177
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904196240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1904196240
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3941186650
Short name T289
Test name
Test status
Simulation time 13674295961 ps
CPU time 62.52 seconds
Started Jun 21 04:43:21 PM PDT 24
Finished Jun 21 04:44:28 PM PDT 24
Peak memory 218600 kb
Host smart-57b138b2-6ccd-4b92-93de-0259a1110c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941186650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3941186650
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1916284746
Short name T63
Test name
Test status
Simulation time 2836960190 ps
CPU time 26.04 seconds
Started Jun 21 04:43:24 PM PDT 24
Finished Jun 21 04:43:55 PM PDT 24
Peak memory 219016 kb
Host smart-e8649d83-0336-4bc7-931b-f591f158b697
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1916284746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1916284746
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.652187266
Short name T244
Test name
Test status
Simulation time 32754367815 ps
CPU time 68.43 seconds
Started Jun 21 04:43:25 PM PDT 24
Finished Jun 21 04:44:39 PM PDT 24
Peak memory 216448 kb
Host smart-b477a95c-2d7e-46f5-bb59-0d522bee8880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652187266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.652187266
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3133613329
Short name T258
Test name
Test status
Simulation time 1554601686 ps
CPU time 25.1 seconds
Started Jun 21 04:43:25 PM PDT 24
Finished Jun 21 04:43:56 PM PDT 24
Peak memory 219100 kb
Host smart-e4a7d97f-c4b8-4210-baac-d44afb0e3080
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133613329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3133613329
Directory /workspace/9.rom_ctrl_stress_all/latest
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