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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.26 96.89 91.99 97.68 100.00 98.62 97.30 98.37


Total test records in report: 453
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T299 /workspace/coverage/default/15.rom_ctrl_smoke.3704457174 Jun 22 04:36:09 PM PDT 24 Jun 22 04:37:14 PM PDT 24 25708068441 ps
T300 /workspace/coverage/default/40.rom_ctrl_stress_all.2684791203 Jun 22 04:36:53 PM PDT 24 Jun 22 04:38:06 PM PDT 24 8532960962 ps
T29 /workspace/coverage/default/0.rom_ctrl_sec_cm.2742300967 Jun 22 04:36:06 PM PDT 24 Jun 22 04:38:14 PM PDT 24 2125024426 ps
T301 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3091364624 Jun 22 04:36:45 PM PDT 24 Jun 22 04:44:01 PM PDT 24 97309018199 ps
T302 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3325959858 Jun 22 04:36:12 PM PDT 24 Jun 22 04:36:43 PM PDT 24 3643173416 ps
T303 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2901698789 Jun 22 04:36:38 PM PDT 24 Jun 22 04:41:34 PM PDT 24 8052981640 ps
T304 /workspace/coverage/default/46.rom_ctrl_stress_all.2591388995 Jun 22 04:36:47 PM PDT 24 Jun 22 04:40:43 PM PDT 24 24136692891 ps
T305 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.4157538160 Jun 22 04:36:31 PM PDT 24 Jun 22 04:48:17 PM PDT 24 289299864808 ps
T306 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3964793351 Jun 22 04:36:29 PM PDT 24 Jun 22 04:37:32 PM PDT 24 6986438634 ps
T307 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1236484025 Jun 22 04:36:30 PM PDT 24 Jun 22 04:43:34 PM PDT 24 172660022421 ps
T308 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1149145987 Jun 22 04:36:26 PM PDT 24 Jun 22 04:36:43 PM PDT 24 3422185476 ps
T309 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.750487538 Jun 22 04:36:27 PM PDT 24 Jun 22 04:36:58 PM PDT 24 15326161430 ps
T310 /workspace/coverage/default/4.rom_ctrl_alert_test.1954633624 Jun 22 04:35:55 PM PDT 24 Jun 22 04:36:14 PM PDT 24 2917845393 ps
T311 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3776437730 Jun 22 04:36:46 PM PDT 24 Jun 22 04:37:37 PM PDT 24 4736442938 ps
T312 /workspace/coverage/default/43.rom_ctrl_alert_test.1859761924 Jun 22 04:36:50 PM PDT 24 Jun 22 04:37:17 PM PDT 24 2721166751 ps
T313 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1054899679 Jun 22 04:35:58 PM PDT 24 Jun 22 04:39:41 PM PDT 24 85160900927 ps
T314 /workspace/coverage/default/48.rom_ctrl_alert_test.94442368 Jun 22 04:37:01 PM PDT 24 Jun 22 04:37:30 PM PDT 24 6653092084 ps
T315 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.367830503 Jun 22 04:36:31 PM PDT 24 Jun 22 04:37:26 PM PDT 24 6012960059 ps
T316 /workspace/coverage/default/1.rom_ctrl_alert_test.699778914 Jun 22 04:36:06 PM PDT 24 Jun 22 04:36:40 PM PDT 24 8734613090 ps
T49 /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3146863964 Jun 22 04:36:30 PM PDT 24 Jun 22 05:16:33 PM PDT 24 38085608775 ps
T317 /workspace/coverage/default/8.rom_ctrl_alert_test.4092008148 Jun 22 04:36:14 PM PDT 24 Jun 22 04:36:33 PM PDT 24 3187395083 ps
T318 /workspace/coverage/default/37.rom_ctrl_alert_test.1149933610 Jun 22 04:36:49 PM PDT 24 Jun 22 04:37:12 PM PDT 24 8226041262 ps
T319 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.338046803 Jun 22 04:36:39 PM PDT 24 Jun 22 04:37:09 PM PDT 24 15041689207 ps
T320 /workspace/coverage/default/40.rom_ctrl_smoke.3205885418 Jun 22 04:36:47 PM PDT 24 Jun 22 04:37:26 PM PDT 24 10045966675 ps
T321 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1171254897 Jun 22 04:36:52 PM PDT 24 Jun 22 04:37:06 PM PDT 24 731635993 ps
T322 /workspace/coverage/default/12.rom_ctrl_alert_test.1518316044 Jun 22 04:36:30 PM PDT 24 Jun 22 04:36:49 PM PDT 24 1488907402 ps
T323 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4224873908 Jun 22 04:35:56 PM PDT 24 Jun 22 04:40:46 PM PDT 24 34778828253 ps
T324 /workspace/coverage/default/4.rom_ctrl_smoke.1428265399 Jun 22 04:35:52 PM PDT 24 Jun 22 04:36:49 PM PDT 24 21036568091 ps
T325 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.317540538 Jun 22 04:36:56 PM PDT 24 Jun 22 04:37:30 PM PDT 24 4119580121 ps
T50 /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3467276016 Jun 22 04:36:40 PM PDT 24 Jun 22 05:36:07 PM PDT 24 42821555346 ps
T46 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3189239095 Jun 22 04:36:37 PM PDT 24 Jun 22 04:37:21 PM PDT 24 53695519870 ps
T326 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3556088295 Jun 22 04:36:36 PM PDT 24 Jun 22 04:36:57 PM PDT 24 661340482 ps
T327 /workspace/coverage/default/32.rom_ctrl_alert_test.3410158822 Jun 22 04:36:51 PM PDT 24 Jun 22 04:37:28 PM PDT 24 34996477524 ps
T328 /workspace/coverage/default/3.rom_ctrl_stress_all.3153903185 Jun 22 04:36:20 PM PDT 24 Jun 22 04:37:27 PM PDT 24 14913082687 ps
T329 /workspace/coverage/default/29.rom_ctrl_stress_all.3162851007 Jun 22 04:36:47 PM PDT 24 Jun 22 04:40:09 PM PDT 24 23729316250 ps
T330 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2162800012 Jun 22 04:36:07 PM PDT 24 Jun 22 04:36:36 PM PDT 24 2234762817 ps
T331 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.838108840 Jun 22 04:36:50 PM PDT 24 Jun 22 04:37:43 PM PDT 24 9114718429 ps
T332 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3957969410 Jun 22 04:36:41 PM PDT 24 Jun 22 04:40:33 PM PDT 24 116469360354 ps
T333 /workspace/coverage/default/4.rom_ctrl_stress_all.3426221807 Jun 22 04:36:15 PM PDT 24 Jun 22 04:37:15 PM PDT 24 73044818602 ps
T334 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.427294778 Jun 22 04:36:04 PM PDT 24 Jun 22 04:37:03 PM PDT 24 6333715576 ps
T335 /workspace/coverage/default/0.rom_ctrl_stress_all.2364959970 Jun 22 04:36:13 PM PDT 24 Jun 22 04:36:24 PM PDT 24 751325360 ps
T336 /workspace/coverage/default/38.rom_ctrl_stress_all.803715693 Jun 22 04:36:46 PM PDT 24 Jun 22 04:39:07 PM PDT 24 33590822534 ps
T337 /workspace/coverage/default/33.rom_ctrl_alert_test.3770060008 Jun 22 04:36:48 PM PDT 24 Jun 22 04:36:59 PM PDT 24 187785682 ps
T338 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3198615445 Jun 22 04:36:42 PM PDT 24 Jun 22 04:37:11 PM PDT 24 3119776548 ps
T339 /workspace/coverage/default/9.rom_ctrl_smoke.3301427524 Jun 22 04:36:27 PM PDT 24 Jun 22 04:37:03 PM PDT 24 4387217699 ps
T340 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1793005873 Jun 22 04:36:35 PM PDT 24 Jun 22 04:37:17 PM PDT 24 14462524463 ps
T341 /workspace/coverage/default/17.rom_ctrl_stress_all.2806249029 Jun 22 04:37:03 PM PDT 24 Jun 22 04:38:08 PM PDT 24 30179428390 ps
T342 /workspace/coverage/default/36.rom_ctrl_stress_all.569287075 Jun 22 04:36:49 PM PDT 24 Jun 22 04:39:26 PM PDT 24 15289005050 ps
T343 /workspace/coverage/default/45.rom_ctrl_alert_test.3822116882 Jun 22 04:36:52 PM PDT 24 Jun 22 04:37:23 PM PDT 24 12987624598 ps
T344 /workspace/coverage/default/41.rom_ctrl_stress_all.1091559867 Jun 22 04:36:51 PM PDT 24 Jun 22 04:38:29 PM PDT 24 34481507316 ps
T345 /workspace/coverage/default/3.rom_ctrl_alert_test.631528989 Jun 22 04:36:29 PM PDT 24 Jun 22 04:36:58 PM PDT 24 15198810022 ps
T346 /workspace/coverage/default/9.rom_ctrl_alert_test.1553990961 Jun 22 04:36:32 PM PDT 24 Jun 22 04:36:50 PM PDT 24 7281539806 ps
T347 /workspace/coverage/default/19.rom_ctrl_alert_test.38640661 Jun 22 04:36:31 PM PDT 24 Jun 22 04:36:52 PM PDT 24 3913555512 ps
T348 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3301094722 Jun 22 04:36:19 PM PDT 24 Jun 22 04:36:39 PM PDT 24 1320667373 ps
T51 /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.274729001 Jun 22 04:36:22 PM PDT 24 Jun 22 04:47:20 PM PDT 24 31041666640 ps
T349 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2307596986 Jun 22 04:36:52 PM PDT 24 Jun 22 04:41:36 PM PDT 24 27923070238 ps
T350 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.4220494054 Jun 22 04:36:53 PM PDT 24 Jun 22 04:37:51 PM PDT 24 35787978435 ps
T351 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2155543717 Jun 22 04:36:26 PM PDT 24 Jun 22 04:36:47 PM PDT 24 5531724918 ps
T68 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2492922534 Jun 22 04:31:42 PM PDT 24 Jun 22 04:31:57 PM PDT 24 1933839448 ps
T69 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.223954826 Jun 22 04:30:58 PM PDT 24 Jun 22 04:31:11 PM PDT 24 2519772353 ps
T70 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1173371054 Jun 22 04:31:34 PM PDT 24 Jun 22 04:32:06 PM PDT 24 33493792520 ps
T75 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2613379183 Jun 22 04:31:30 PM PDT 24 Jun 22 04:32:27 PM PDT 24 2110589759 ps
T76 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.4166874858 Jun 22 04:31:20 PM PDT 24 Jun 22 04:33:05 PM PDT 24 11638950243 ps
T77 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2642615373 Jun 22 04:31:26 PM PDT 24 Jun 22 04:32:24 PM PDT 24 3103921267 ps
T101 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.487271543 Jun 22 04:31:08 PM PDT 24 Jun 22 04:31:30 PM PDT 24 4723219293 ps
T52 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3634654975 Jun 22 04:31:26 PM PDT 24 Jun 22 04:32:49 PM PDT 24 912909045 ps
T78 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.907021107 Jun 22 04:31:20 PM PDT 24 Jun 22 04:31:29 PM PDT 24 1497243650 ps
T79 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3968098303 Jun 22 04:31:19 PM PDT 24 Jun 22 04:31:47 PM PDT 24 6228876203 ps
T80 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1457688776 Jun 22 04:31:36 PM PDT 24 Jun 22 04:32:06 PM PDT 24 3698479769 ps
T352 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3848991866 Jun 22 04:31:28 PM PDT 24 Jun 22 04:31:55 PM PDT 24 5833439910 ps
T353 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3600170727 Jun 22 04:31:00 PM PDT 24 Jun 22 04:31:23 PM PDT 24 6028942623 ps
T53 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4130235747 Jun 22 04:31:41 PM PDT 24 Jun 22 04:31:53 PM PDT 24 1898053433 ps
T54 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3163815676 Jun 22 04:31:26 PM PDT 24 Jun 22 04:31:49 PM PDT 24 1920533840 ps
T102 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1975699063 Jun 22 04:31:35 PM PDT 24 Jun 22 04:32:25 PM PDT 24 6976438789 ps
T74 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2554667450 Jun 22 04:31:25 PM PDT 24 Jun 22 04:31:42 PM PDT 24 1119437428 ps
T354 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2114931503 Jun 22 04:30:59 PM PDT 24 Jun 22 04:31:08 PM PDT 24 1501160370 ps
T64 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1351711827 Jun 22 04:31:26 PM PDT 24 Jun 22 04:34:07 PM PDT 24 1563101980 ps
T355 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3782025258 Jun 22 04:31:26 PM PDT 24 Jun 22 04:33:10 PM PDT 24 42149381062 ps
T65 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1706392736 Jun 22 04:31:27 PM PDT 24 Jun 22 04:34:09 PM PDT 24 4298162383 ps
T356 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2628777049 Jun 22 04:31:15 PM PDT 24 Jun 22 04:31:45 PM PDT 24 8046132845 ps
T81 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3244418910 Jun 22 04:31:25 PM PDT 24 Jun 22 04:31:44 PM PDT 24 1755447295 ps
T99 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3089250984 Jun 22 04:31:26 PM PDT 24 Jun 22 04:31:49 PM PDT 24 4817058210 ps
T82 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2396152019 Jun 22 04:30:59 PM PDT 24 Jun 22 04:31:21 PM PDT 24 1029186097 ps
T357 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4206633873 Jun 22 04:31:08 PM PDT 24 Jun 22 04:31:23 PM PDT 24 520092989 ps
T104 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3179798845 Jun 22 04:30:58 PM PDT 24 Jun 22 04:33:44 PM PDT 24 2633913349 ps
T358 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.18523830 Jun 22 04:31:27 PM PDT 24 Jun 22 04:32:02 PM PDT 24 3669951910 ps
T359 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.955310865 Jun 22 04:30:59 PM PDT 24 Jun 22 04:31:08 PM PDT 24 167580257 ps
T360 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2563947655 Jun 22 04:31:25 PM PDT 24 Jun 22 04:32:03 PM PDT 24 46108484819 ps
T100 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2180140787 Jun 22 04:31:29 PM PDT 24 Jun 22 04:31:41 PM PDT 24 362890249 ps
T361 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2630195308 Jun 22 04:31:17 PM PDT 24 Jun 22 04:31:32 PM PDT 24 2052350343 ps
T83 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2573335620 Jun 22 04:31:33 PM PDT 24 Jun 22 04:31:48 PM PDT 24 3753185526 ps
T362 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3979487277 Jun 22 04:31:26 PM PDT 24 Jun 22 04:31:51 PM PDT 24 3030964963 ps
T363 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.801171189 Jun 22 04:31:19 PM PDT 24 Jun 22 04:31:40 PM PDT 24 3910950248 ps
T364 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1119328310 Jun 22 04:31:07 PM PDT 24 Jun 22 04:31:35 PM PDT 24 3221735430 ps
T365 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2983730407 Jun 22 04:31:28 PM PDT 24 Jun 22 04:31:38 PM PDT 24 1721785450 ps
T105 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.246084711 Jun 22 04:31:18 PM PDT 24 Jun 22 04:34:10 PM PDT 24 14799167333 ps
T108 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3590219508 Jun 22 04:31:18 PM PDT 24 Jun 22 04:33:50 PM PDT 24 284441311 ps
T366 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1806863605 Jun 22 04:31:00 PM PDT 24 Jun 22 04:31:55 PM PDT 24 1033202436 ps
T103 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4144679554 Jun 22 04:31:10 PM PDT 24 Jun 22 04:31:48 PM PDT 24 2860342702 ps
T367 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1254375200 Jun 22 04:31:18 PM PDT 24 Jun 22 04:31:33 PM PDT 24 859835988 ps
T368 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2462098517 Jun 22 04:31:08 PM PDT 24 Jun 22 04:31:17 PM PDT 24 1650531019 ps
T369 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4124254796 Jun 22 04:31:19 PM PDT 24 Jun 22 04:31:36 PM PDT 24 907042397 ps
T370 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3174610896 Jun 22 04:31:19 PM PDT 24 Jun 22 04:32:15 PM PDT 24 5718260086 ps
T88 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.629318533 Jun 22 04:31:07 PM PDT 24 Jun 22 04:32:02 PM PDT 24 10214859163 ps
T371 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.941545344 Jun 22 04:31:01 PM PDT 24 Jun 22 04:31:27 PM PDT 24 5868968646 ps
T372 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.715130327 Jun 22 04:31:41 PM PDT 24 Jun 22 04:32:12 PM PDT 24 3301065112 ps
T373 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2620160576 Jun 22 04:31:20 PM PDT 24 Jun 22 04:31:51 PM PDT 24 5563878516 ps
T374 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3650803390 Jun 22 04:31:45 PM PDT 24 Jun 22 04:32:08 PM PDT 24 2239189932 ps
T89 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.28472711 Jun 22 04:31:18 PM PDT 24 Jun 22 04:31:45 PM PDT 24 6392500103 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3531102720 Jun 22 04:31:17 PM PDT 24 Jun 22 04:31:27 PM PDT 24 672068562 ps
T376 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2520796934 Jun 22 04:31:40 PM PDT 24 Jun 22 04:31:52 PM PDT 24 688579321 ps
T377 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.614051830 Jun 22 04:31:34 PM PDT 24 Jun 22 04:32:59 PM PDT 24 7967874816 ps
T378 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1434174081 Jun 22 04:30:59 PM PDT 24 Jun 22 04:31:35 PM PDT 24 16695907503 ps
T379 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2645463666 Jun 22 04:31:17 PM PDT 24 Jun 22 04:31:40 PM PDT 24 3838295479 ps
T380 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.567316597 Jun 22 04:30:58 PM PDT 24 Jun 22 04:31:11 PM PDT 24 1146329311 ps
T106 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.971768254 Jun 22 04:31:20 PM PDT 24 Jun 22 04:34:15 PM PDT 24 16091658008 ps
T90 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1016611327 Jun 22 04:31:07 PM PDT 24 Jun 22 04:31:34 PM PDT 24 62085538158 ps
T381 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.517341799 Jun 22 04:31:01 PM PDT 24 Jun 22 04:31:16 PM PDT 24 831449870 ps
T382 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1875877357 Jun 22 04:30:59 PM PDT 24 Jun 22 04:31:12 PM PDT 24 2869286769 ps
T383 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2203862409 Jun 22 04:31:19 PM PDT 24 Jun 22 04:31:48 PM PDT 24 2547104918 ps
T384 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2737798552 Jun 22 04:31:01 PM PDT 24 Jun 22 04:31:16 PM PDT 24 8269863416 ps
T385 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1683635310 Jun 22 04:31:36 PM PDT 24 Jun 22 04:31:48 PM PDT 24 172627276 ps
T111 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3465032037 Jun 22 04:31:39 PM PDT 24 Jun 22 04:34:25 PM PDT 24 3182890331 ps
T91 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3385103309 Jun 22 04:31:19 PM PDT 24 Jun 22 04:31:35 PM PDT 24 5118590699 ps
T386 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4079042130 Jun 22 04:31:34 PM PDT 24 Jun 22 04:31:48 PM PDT 24 171079774 ps
T387 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2043107519 Jun 22 04:31:19 PM PDT 24 Jun 22 04:33:56 PM PDT 24 3121874390 ps
T388 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.768380351 Jun 22 04:31:08 PM PDT 24 Jun 22 04:31:22 PM PDT 24 1730007831 ps
T389 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2291027735 Jun 22 04:31:06 PM PDT 24 Jun 22 04:31:23 PM PDT 24 5591664796 ps
T92 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.351446723 Jun 22 04:31:01 PM PDT 24 Jun 22 04:31:39 PM PDT 24 7943120399 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4227036403 Jun 22 04:31:06 PM PDT 24 Jun 22 04:31:31 PM PDT 24 2792016905 ps
T391 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1228904402 Jun 22 04:31:00 PM PDT 24 Jun 22 04:31:16 PM PDT 24 1088987363 ps
T392 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1303596531 Jun 22 04:31:21 PM PDT 24 Jun 22 04:31:51 PM PDT 24 3778259274 ps
T393 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.284414831 Jun 22 04:31:26 PM PDT 24 Jun 22 04:31:56 PM PDT 24 10310977994 ps
T394 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3620493785 Jun 22 04:31:08 PM PDT 24 Jun 22 04:32:51 PM PDT 24 11640413499 ps
T93 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1871512277 Jun 22 04:31:19 PM PDT 24 Jun 22 04:33:57 PM PDT 24 180712966377 ps
T98 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4051365920 Jun 22 04:31:48 PM PDT 24 Jun 22 04:32:15 PM PDT 24 6469797185 ps
T395 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.502773959 Jun 22 04:31:46 PM PDT 24 Jun 22 04:34:21 PM PDT 24 581884228 ps
T396 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2948663412 Jun 22 04:31:01 PM PDT 24 Jun 22 04:31:28 PM PDT 24 2175637193 ps
T94 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3227896275 Jun 22 04:31:31 PM PDT 24 Jun 22 04:31:50 PM PDT 24 1648383697 ps
T397 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.456749922 Jun 22 04:31:47 PM PDT 24 Jun 22 04:32:26 PM PDT 24 16897058387 ps
T398 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3713537027 Jun 22 04:30:59 PM PDT 24 Jun 22 04:31:07 PM PDT 24 660332807 ps
T399 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1504855491 Jun 22 04:31:36 PM PDT 24 Jun 22 04:31:55 PM PDT 24 1802092564 ps
T400 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.82880541 Jun 22 04:31:08 PM PDT 24 Jun 22 04:31:46 PM PDT 24 7549620585 ps
T401 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2223084733 Jun 22 04:31:35 PM PDT 24 Jun 22 04:31:59 PM PDT 24 9846771075 ps
T402 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4188789883 Jun 22 04:30:59 PM PDT 24 Jun 22 04:31:07 PM PDT 24 660582612 ps
T403 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.917951156 Jun 22 04:31:38 PM PDT 24 Jun 22 04:32:12 PM PDT 24 39459250854 ps
T404 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.732545398 Jun 22 04:31:25 PM PDT 24 Jun 22 04:31:42 PM PDT 24 5126771453 ps
T405 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1736542977 Jun 22 04:31:46 PM PDT 24 Jun 22 04:34:22 PM PDT 24 1154199587 ps
T406 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3606084193 Jun 22 04:31:27 PM PDT 24 Jun 22 04:32:00 PM PDT 24 10061553309 ps
T407 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1246736150 Jun 22 04:31:07 PM PDT 24 Jun 22 04:31:17 PM PDT 24 1362420366 ps
T408 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4079225907 Jun 22 04:31:32 PM PDT 24 Jun 22 04:32:05 PM PDT 24 17945300581 ps
T409 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3490486453 Jun 22 04:31:09 PM PDT 24 Jun 22 04:32:48 PM PDT 24 14762644528 ps
T95 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1135074443 Jun 22 04:31:35 PM PDT 24 Jun 22 04:32:14 PM PDT 24 1440812302 ps
T112 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3558849262 Jun 22 04:31:50 PM PDT 24 Jun 22 04:33:12 PM PDT 24 289219084 ps
T96 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3801348454 Jun 22 04:31:18 PM PDT 24 Jun 22 04:32:36 PM PDT 24 12757268222 ps
T410 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3517362993 Jun 22 04:31:10 PM PDT 24 Jun 22 04:31:36 PM PDT 24 3101726467 ps
T411 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.123651704 Jun 22 04:31:01 PM PDT 24 Jun 22 04:31:21 PM PDT 24 3549280487 ps
T412 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4025215284 Jun 22 04:31:08 PM PDT 24 Jun 22 04:31:24 PM PDT 24 1106608649 ps
T413 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.19078599 Jun 22 04:31:38 PM PDT 24 Jun 22 04:31:59 PM PDT 24 2115869341 ps
T414 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2779213495 Jun 22 04:31:18 PM PDT 24 Jun 22 04:31:39 PM PDT 24 22584388068 ps
T415 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.757860985 Jun 22 04:31:07 PM PDT 24 Jun 22 04:33:59 PM PDT 24 17862857368 ps
T416 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1499359385 Jun 22 04:31:08 PM PDT 24 Jun 22 04:31:25 PM PDT 24 1428286839 ps
T417 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1811812508 Jun 22 04:31:27 PM PDT 24 Jun 22 04:32:05 PM PDT 24 713041150 ps
T418 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2179606491 Jun 22 04:31:08 PM PDT 24 Jun 22 04:31:30 PM PDT 24 8919298677 ps
T419 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1717377276 Jun 22 04:31:46 PM PDT 24 Jun 22 04:33:32 PM PDT 24 8015545299 ps
T97 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.375026514 Jun 22 04:30:58 PM PDT 24 Jun 22 04:31:07 PM PDT 24 234829659 ps
T420 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2480878988 Jun 22 04:31:03 PM PDT 24 Jun 22 04:33:09 PM PDT 24 140658905930 ps
T421 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4242496432 Jun 22 04:31:08 PM PDT 24 Jun 22 04:31:20 PM PDT 24 1646209966 ps
T422 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1439020636 Jun 22 04:31:07 PM PDT 24 Jun 22 04:31:41 PM PDT 24 8198682560 ps
T423 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3865002363 Jun 22 04:31:35 PM PDT 24 Jun 22 04:31:54 PM PDT 24 1721430308 ps
T424 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1302843808 Jun 22 04:31:20 PM PDT 24 Jun 22 04:31:29 PM PDT 24 167614965 ps
T425 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.662291999 Jun 22 04:31:34 PM PDT 24 Jun 22 04:31:58 PM PDT 24 2467590443 ps
T426 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4088154826 Jun 22 04:31:07 PM PDT 24 Jun 22 04:31:27 PM PDT 24 2044910874 ps
T109 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3429887644 Jun 22 04:31:20 PM PDT 24 Jun 22 04:34:07 PM PDT 24 11130603326 ps
T110 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.426820149 Jun 22 04:31:44 PM PDT 24 Jun 22 04:34:35 PM PDT 24 11800460150 ps
T427 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3730062949 Jun 22 04:31:00 PM PDT 24 Jun 22 04:31:19 PM PDT 24 2647353135 ps
T428 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2707411923 Jun 22 04:31:35 PM PDT 24 Jun 22 04:34:19 PM PDT 24 4411109622 ps
T429 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2434683616 Jun 22 04:31:46 PM PDT 24 Jun 22 04:32:14 PM PDT 24 12241140910 ps
T430 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.832338504 Jun 22 04:31:27 PM PDT 24 Jun 22 04:31:50 PM PDT 24 2391793867 ps
T431 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2664176176 Jun 22 04:31:02 PM PDT 24 Jun 22 04:31:57 PM PDT 24 5527627870 ps
T432 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2266401359 Jun 22 04:31:17 PM PDT 24 Jun 22 04:31:46 PM PDT 24 3333646035 ps
T433 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1076897523 Jun 22 04:31:46 PM PDT 24 Jun 22 04:33:36 PM PDT 24 8795047522 ps
T434 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4102099898 Jun 22 04:31:06 PM PDT 24 Jun 22 04:31:21 PM PDT 24 2343003335 ps
T435 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2023335634 Jun 22 04:31:27 PM PDT 24 Jun 22 04:32:00 PM PDT 24 5708311571 ps
T436 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3939577773 Jun 22 04:31:30 PM PDT 24 Jun 22 04:34:19 PM PDT 24 13201858273 ps
T437 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1208595059 Jun 22 04:31:35 PM PDT 24 Jun 22 04:31:47 PM PDT 24 1001737927 ps
T438 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4098308067 Jun 22 04:31:09 PM PDT 24 Jun 22 04:31:36 PM PDT 24 6924197576 ps
T439 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.332814919 Jun 22 04:31:21 PM PDT 24 Jun 22 04:31:51 PM PDT 24 34663227383 ps
T440 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4152632689 Jun 22 04:31:18 PM PDT 24 Jun 22 04:31:28 PM PDT 24 739711860 ps
T441 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1026644632 Jun 22 04:31:34 PM PDT 24 Jun 22 04:32:04 PM PDT 24 20453532686 ps
T442 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.240973148 Jun 22 04:31:34 PM PDT 24 Jun 22 04:32:02 PM PDT 24 20771259216 ps
T443 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4261408252 Jun 22 04:31:48 PM PDT 24 Jun 22 04:32:14 PM PDT 24 12119052288 ps
T444 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2007329853 Jun 22 04:31:00 PM PDT 24 Jun 22 04:31:13 PM PDT 24 1338350173 ps
T445 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.410020617 Jun 22 04:31:34 PM PDT 24 Jun 22 04:31:54 PM PDT 24 1965324408 ps
T446 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3007011936 Jun 22 04:31:36 PM PDT 24 Jun 22 04:32:13 PM PDT 24 4814110594 ps
T447 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3677118613 Jun 22 04:31:25 PM PDT 24 Jun 22 04:31:53 PM PDT 24 3371559936 ps
T448 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2448087350 Jun 22 04:31:39 PM PDT 24 Jun 22 04:32:06 PM PDT 24 2933465085 ps
T107 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2956581191 Jun 22 04:30:59 PM PDT 24 Jun 22 04:32:18 PM PDT 24 1352437901 ps
T449 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3329449036 Jun 22 04:31:46 PM PDT 24 Jun 22 04:34:06 PM PDT 24 17270020718 ps
T450 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.567163995 Jun 22 04:30:59 PM PDT 24 Jun 22 04:31:32 PM PDT 24 3084272820 ps
T451 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1131698641 Jun 22 04:31:46 PM PDT 24 Jun 22 04:35:01 PM PDT 24 102699862005 ps
T452 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1988868939 Jun 22 04:31:06 PM PDT 24 Jun 22 04:31:16 PM PDT 24 182251705 ps
T453 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3868907999 Jun 22 04:31:34 PM PDT 24 Jun 22 04:31:59 PM PDT 24 2945119958 ps

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.39812220
Short name T10
Test name
Test status
Simulation time 273958739115 ps
CPU time 713.87 seconds
Started Jun 22 04:36:48 PM PDT 24
Finished Jun 22 04:48:45 PM PDT 24
Peak memory 238528 kb
Host smart-583b49c4-f57e-4a27-8981-a1cedfe32747
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39812220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_co
rrupt_sig_fatal_chk.39812220
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1323466917
Short name T14
Test name
Test status
Simulation time 127628533400 ps
CPU time 2396.55 seconds
Started Jun 22 04:36:51 PM PDT 24
Finished Jun 22 05:16:51 PM PDT 24
Peak memory 243860 kb
Host smart-06205fab-80f7-44d1-a79c-59a8d4f304a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323466917 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.1323466917
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.700633076
Short name T13
Test name
Test status
Simulation time 26403455833 ps
CPU time 42.96 seconds
Started Jun 22 04:36:49 PM PDT 24
Finished Jun 22 04:37:35 PM PDT 24
Peak memory 216972 kb
Host smart-792ff403-761d-45d6-bb47-79c01a01511e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700633076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.700633076
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3179798845
Short name T104
Test name
Test status
Simulation time 2633913349 ps
CPU time 164.96 seconds
Started Jun 22 04:30:58 PM PDT 24
Finished Jun 22 04:33:44 PM PDT 24
Peak memory 213672 kb
Host smart-04442b56-6d96-454b-8320-99e955eea638
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179798845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3179798845
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3149811787
Short name T36
Test name
Test status
Simulation time 40592014402 ps
CPU time 340.14 seconds
Started Jun 22 04:36:39 PM PDT 24
Finished Jun 22 04:42:20 PM PDT 24
Peak memory 240416 kb
Host smart-f57c3b00-e63d-4cd3-b965-c8c826cd45eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149811787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3149811787
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.4011320200
Short name T22
Test name
Test status
Simulation time 1899126873 ps
CPU time 224.1 seconds
Started Jun 22 04:36:26 PM PDT 24
Finished Jun 22 04:40:11 PM PDT 24
Peak memory 237500 kb
Host smart-f7b7585b-33eb-4cb5-89dc-8839d804c518
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011320200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.4011320200
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.4166874858
Short name T76
Test name
Test status
Simulation time 11638950243 ps
CPU time 104.63 seconds
Started Jun 22 04:31:20 PM PDT 24
Finished Jun 22 04:33:05 PM PDT 24
Peak memory 214576 kb
Host smart-a6134c01-707a-46c8-b637-4bf68671a3ef
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166874858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.4166874858
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.4080366535
Short name T11
Test name
Test status
Simulation time 51872218456 ps
CPU time 159.17 seconds
Started Jun 22 04:36:49 PM PDT 24
Finished Jun 22 04:39:31 PM PDT 24
Peak memory 227356 kb
Host smart-282e2800-f843-446a-9b08-5aa706dafec4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080366535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.4080366535
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.426820149
Short name T110
Test name
Test status
Simulation time 11800460150 ps
CPU time 169.32 seconds
Started Jun 22 04:31:44 PM PDT 24
Finished Jun 22 04:34:35 PM PDT 24
Peak memory 214816 kb
Host smart-497e6d22-68be-4d24-99a4-87665b344b7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426820149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.426820149
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.587121268
Short name T125
Test name
Test status
Simulation time 62431707334 ps
CPU time 30.08 seconds
Started Jun 22 04:36:36 PM PDT 24
Finished Jun 22 04:37:08 PM PDT 24
Peak memory 217288 kb
Host smart-cda0c6d4-f3e4-445d-9cdb-64e8b260acf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587121268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.587121268
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3015007497
Short name T25
Test name
Test status
Simulation time 6381554589 ps
CPU time 53.85 seconds
Started Jun 22 04:36:52 PM PDT 24
Finished Jun 22 04:37:50 PM PDT 24
Peak memory 219092 kb
Host smart-613e7f37-56d8-4795-acfd-3da8f0bb2e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015007497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3015007497
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2616389149
Short name T45
Test name
Test status
Simulation time 2334554593 ps
CPU time 33.68 seconds
Started Jun 22 04:36:26 PM PDT 24
Finished Jun 22 04:37:02 PM PDT 24
Peak memory 218288 kb
Host smart-966db1b7-b9ec-4ed9-ae0a-c7826e35183c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616389149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2616389149
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.534087496
Short name T177
Test name
Test status
Simulation time 1434984262 ps
CPU time 18.17 seconds
Started Jun 22 04:37:26 PM PDT 24
Finished Jun 22 04:37:44 PM PDT 24
Peak memory 218856 kb
Host smart-50335c50-56a6-4937-be8d-6b6d7ade192c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534087496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.534087496
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3634654975
Short name T52
Test name
Test status
Simulation time 912909045 ps
CPU time 82.09 seconds
Started Jun 22 04:31:26 PM PDT 24
Finished Jun 22 04:32:49 PM PDT 24
Peak memory 213852 kb
Host smart-8802f27c-16ca-4ca1-8bb4-2d4f10a32038
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634654975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3634654975
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.4144679554
Short name T103
Test name
Test status
Simulation time 2860342702 ps
CPU time 37.62 seconds
Started Jun 22 04:31:10 PM PDT 24
Finished Jun 22 04:31:48 PM PDT 24
Peak memory 212128 kb
Host smart-0f3cceb1-462f-47e6-920e-b9d6ee447aa2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144679554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.4144679554
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.94237258
Short name T163
Test name
Test status
Simulation time 2973299646 ps
CPU time 52.85 seconds
Started Jun 22 04:36:36 PM PDT 24
Finished Jun 22 04:37:30 PM PDT 24
Peak memory 219164 kb
Host smart-c6503513-37c3-40d2-9605-c4c656fa1296
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94237258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 14.rom_ctrl_stress_all.94237258
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3227896275
Short name T94
Test name
Test status
Simulation time 1648383697 ps
CPU time 18.33 seconds
Started Jun 22 04:31:31 PM PDT 24
Finished Jun 22 04:31:50 PM PDT 24
Peak memory 212108 kb
Host smart-cb92ac89-3469-4f67-bc9e-f77323737898
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227896275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3227896275
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3244418910
Short name T81
Test name
Test status
Simulation time 1755447295 ps
CPU time 18.46 seconds
Started Jun 22 04:31:25 PM PDT 24
Finished Jun 22 04:31:44 PM PDT 24
Peak memory 212260 kb
Host smart-86205925-07ec-4a7a-9375-b667b36fba8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244418910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3244418910
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3242173604
Short name T269
Test name
Test status
Simulation time 20257453875 ps
CPU time 61.48 seconds
Started Jun 22 04:36:31 PM PDT 24
Finished Jun 22 04:37:34 PM PDT 24
Peak memory 216112 kb
Host smart-f2ca805e-1d1f-407d-9ea3-3a27e95f6121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242173604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3242173604
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.4188789883
Short name T402
Test name
Test status
Simulation time 660582612 ps
CPU time 8.07 seconds
Started Jun 22 04:30:59 PM PDT 24
Finished Jun 22 04:31:07 PM PDT 24
Peak memory 211296 kb
Host smart-04fe6048-9611-403d-a1c4-40d31213e47f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188789883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.4188789883
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1228904402
Short name T391
Test name
Test status
Simulation time 1088987363 ps
CPU time 15.43 seconds
Started Jun 22 04:31:00 PM PDT 24
Finished Jun 22 04:31:16 PM PDT 24
Peak memory 211280 kb
Host smart-2170a914-99f1-427b-a19b-e574aa9c9b31
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228904402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1228904402
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.567163995
Short name T450
Test name
Test status
Simulation time 3084272820 ps
CPU time 32.71 seconds
Started Jun 22 04:30:59 PM PDT 24
Finished Jun 22 04:31:32 PM PDT 24
Peak memory 212056 kb
Host smart-efb8c917-4e00-4ce7-830f-cd7ac4a39a57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567163995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.567163995
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.517341799
Short name T381
Test name
Test status
Simulation time 831449870 ps
CPU time 14.01 seconds
Started Jun 22 04:31:01 PM PDT 24
Finished Jun 22 04:31:16 PM PDT 24
Peak memory 215152 kb
Host smart-e9724185-a4a6-4dc4-b162-51c71649ad26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517341799 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.517341799
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.567316597
Short name T380
Test name
Test status
Simulation time 1146329311 ps
CPU time 11.95 seconds
Started Jun 22 04:30:58 PM PDT 24
Finished Jun 22 04:31:11 PM PDT 24
Peak memory 211240 kb
Host smart-0442c2a5-e170-4289-b135-ed1314c435bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567316597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.567316597
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3713537027
Short name T398
Test name
Test status
Simulation time 660332807 ps
CPU time 7.72 seconds
Started Jun 22 04:30:59 PM PDT 24
Finished Jun 22 04:31:07 PM PDT 24
Peak memory 211108 kb
Host smart-0e04d081-7890-4ba7-88ce-378aa14ef85c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713537027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3713537027
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.955310865
Short name T359
Test name
Test status
Simulation time 167580257 ps
CPU time 8 seconds
Started Jun 22 04:30:59 PM PDT 24
Finished Jun 22 04:31:08 PM PDT 24
Peak memory 211108 kb
Host smart-921efe47-f345-4002-bad3-fcd5e166e940
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955310865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
955310865
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1806863605
Short name T366
Test name
Test status
Simulation time 1033202436 ps
CPU time 54.45 seconds
Started Jun 22 04:31:00 PM PDT 24
Finished Jun 22 04:31:55 PM PDT 24
Peak memory 219500 kb
Host smart-bdff7f33-abd0-4136-b00c-f6740b968852
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806863605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1806863605
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2007329853
Short name T444
Test name
Test status
Simulation time 1338350173 ps
CPU time 12.54 seconds
Started Jun 22 04:31:00 PM PDT 24
Finished Jun 22 04:31:13 PM PDT 24
Peak memory 211716 kb
Host smart-12d617bf-04f3-4e60-8830-8cf831d8dd9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007329853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2007329853
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2948663412
Short name T396
Test name
Test status
Simulation time 2175637193 ps
CPU time 26.75 seconds
Started Jun 22 04:31:01 PM PDT 24
Finished Jun 22 04:31:28 PM PDT 24
Peak memory 219032 kb
Host smart-9d643c54-71ad-4989-b088-f75d50e47486
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948663412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2948663412
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2114931503
Short name T354
Test name
Test status
Simulation time 1501160370 ps
CPU time 8.46 seconds
Started Jun 22 04:30:59 PM PDT 24
Finished Jun 22 04:31:08 PM PDT 24
Peak memory 211304 kb
Host smart-b2b1fa6e-7e76-4461-9e68-39d5874f8132
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114931503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2114931503
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2396152019
Short name T82
Test name
Test status
Simulation time 1029186097 ps
CPU time 21.81 seconds
Started Jun 22 04:30:59 PM PDT 24
Finished Jun 22 04:31:21 PM PDT 24
Peak memory 211224 kb
Host smart-8e4532e9-47c2-4a95-9a3e-4b8f8ceaa8d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396152019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2396152019
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3531102720
Short name T375
Test name
Test status
Simulation time 672068562 ps
CPU time 9.22 seconds
Started Jun 22 04:31:17 PM PDT 24
Finished Jun 22 04:31:27 PM PDT 24
Peak memory 218000 kb
Host smart-35df1072-7f96-4d32-8dc8-dca7bb6aec9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531102720 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3531102720
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3600170727
Short name T353
Test name
Test status
Simulation time 6028942623 ps
CPU time 22.8 seconds
Started Jun 22 04:31:00 PM PDT 24
Finished Jun 22 04:31:23 PM PDT 24
Peak memory 211232 kb
Host smart-9d98d525-d202-4d97-9b2c-f5b130ee8ce3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600170727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3600170727
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.941545344
Short name T371
Test name
Test status
Simulation time 5868968646 ps
CPU time 25.31 seconds
Started Jun 22 04:31:01 PM PDT 24
Finished Jun 22 04:31:27 PM PDT 24
Peak memory 211232 kb
Host smart-6f466401-4650-4f01-bb71-79b67770edb1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941545344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
941545344
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2664176176
Short name T431
Test name
Test status
Simulation time 5527627870 ps
CPU time 54.26 seconds
Started Jun 22 04:31:02 PM PDT 24
Finished Jun 22 04:31:57 PM PDT 24
Peak memory 211452 kb
Host smart-f5259ad9-1d25-4183-9b37-c2cba7a1c89c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664176176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2664176176
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.223954826
Short name T69
Test name
Test status
Simulation time 2519772353 ps
CPU time 12.11 seconds
Started Jun 22 04:30:58 PM PDT 24
Finished Jun 22 04:31:11 PM PDT 24
Peak memory 213044 kb
Host smart-95e6a3e8-fccd-4e6c-a185-7ce966e8fc93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223954826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.223954826
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3730062949
Short name T427
Test name
Test status
Simulation time 2647353135 ps
CPU time 18.57 seconds
Started Jun 22 04:31:00 PM PDT 24
Finished Jun 22 04:31:19 PM PDT 24
Peak memory 219036 kb
Host smart-9e403648-5690-4542-9db5-b1906566046e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730062949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3730062949
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2956581191
Short name T107
Test name
Test status
Simulation time 1352437901 ps
CPU time 78.7 seconds
Started Jun 22 04:30:59 PM PDT 24
Finished Jun 22 04:32:18 PM PDT 24
Peak memory 214356 kb
Host smart-f8767363-e9f5-408a-8fc2-5a8a1407f0f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956581191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2956581191
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3979487277
Short name T362
Test name
Test status
Simulation time 3030964963 ps
CPU time 25.03 seconds
Started Jun 22 04:31:26 PM PDT 24
Finished Jun 22 04:31:51 PM PDT 24
Peak memory 215664 kb
Host smart-57b98ab3-7cc1-44a8-99f9-f0794618567c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979487277 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3979487277
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.284414831
Short name T393
Test name
Test status
Simulation time 10310977994 ps
CPU time 29.31 seconds
Started Jun 22 04:31:26 PM PDT 24
Finished Jun 22 04:31:56 PM PDT 24
Peak memory 212788 kb
Host smart-b8fe224b-1eb4-4452-ad50-3b9d6c38f4d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284414831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.284414831
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3782025258
Short name T355
Test name
Test status
Simulation time 42149381062 ps
CPU time 102.55 seconds
Started Jun 22 04:31:26 PM PDT 24
Finished Jun 22 04:33:10 PM PDT 24
Peak memory 219556 kb
Host smart-27c87f2e-5474-4c20-b4a3-fedf77027514
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782025258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3782025258
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3606084193
Short name T406
Test name
Test status
Simulation time 10061553309 ps
CPU time 32.8 seconds
Started Jun 22 04:31:27 PM PDT 24
Finished Jun 22 04:32:00 PM PDT 24
Peak memory 213192 kb
Host smart-6f57f379-b2e9-4ec8-b850-fdf866a7fb35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606084193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3606084193
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4079225907
Short name T408
Test name
Test status
Simulation time 17945300581 ps
CPU time 32.45 seconds
Started Jun 22 04:31:32 PM PDT 24
Finished Jun 22 04:32:05 PM PDT 24
Peak memory 219532 kb
Host smart-8c08eb22-0932-4905-a7f7-0d0b3728ca15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079225907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.4079225907
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2554667450
Short name T74
Test name
Test status
Simulation time 1119437428 ps
CPU time 15.9 seconds
Started Jun 22 04:31:25 PM PDT 24
Finished Jun 22 04:31:42 PM PDT 24
Peak memory 216664 kb
Host smart-d3ea016e-5189-4a45-bbaa-d5043ffa9597
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554667450 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2554667450
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.832338504
Short name T430
Test name
Test status
Simulation time 2391793867 ps
CPU time 22.45 seconds
Started Jun 22 04:31:27 PM PDT 24
Finished Jun 22 04:31:50 PM PDT 24
Peak memory 212520 kb
Host smart-2ce34042-1a1d-4b07-b97b-4f3d0b73bc23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832338504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.832338504
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2642615373
Short name T77
Test name
Test status
Simulation time 3103921267 ps
CPU time 56.63 seconds
Started Jun 22 04:31:26 PM PDT 24
Finished Jun 22 04:32:24 PM PDT 24
Peak memory 219712 kb
Host smart-62f5beb6-5dda-42e4-8003-7214b392e461
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642615373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2642615373
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2180140787
Short name T100
Test name
Test status
Simulation time 362890249 ps
CPU time 12.13 seconds
Started Jun 22 04:31:29 PM PDT 24
Finished Jun 22 04:31:41 PM PDT 24
Peak memory 213100 kb
Host smart-a8fe4a74-e41d-4bb0-b11b-be1ccd9fb989
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180140787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2180140787
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3163815676
Short name T54
Test name
Test status
Simulation time 1920533840 ps
CPU time 22.62 seconds
Started Jun 22 04:31:26 PM PDT 24
Finished Jun 22 04:31:49 PM PDT 24
Peak memory 219416 kb
Host smart-95e51d56-5e31-43bc-b8b9-ea28a880b722
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163815676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3163815676
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1706392736
Short name T65
Test name
Test status
Simulation time 4298162383 ps
CPU time 160.48 seconds
Started Jun 22 04:31:27 PM PDT 24
Finished Jun 22 04:34:09 PM PDT 24
Peak memory 214500 kb
Host smart-d6bb4d93-0bd7-46c6-be2c-dde61088fae1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706392736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1706392736
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2983730407
Short name T365
Test name
Test status
Simulation time 1721785450 ps
CPU time 8.91 seconds
Started Jun 22 04:31:28 PM PDT 24
Finished Jun 22 04:31:38 PM PDT 24
Peak memory 217780 kb
Host smart-99ed089d-249f-4dcd-98ae-08a54883a9d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983730407 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2983730407
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2023335634
Short name T435
Test name
Test status
Simulation time 5708311571 ps
CPU time 32.21 seconds
Started Jun 22 04:31:27 PM PDT 24
Finished Jun 22 04:32:00 PM PDT 24
Peak memory 213008 kb
Host smart-a3fc0944-51e5-44a7-acc8-fc669b19ed3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023335634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2023335634
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1811812508
Short name T417
Test name
Test status
Simulation time 713041150 ps
CPU time 37.48 seconds
Started Jun 22 04:31:27 PM PDT 24
Finished Jun 22 04:32:05 PM PDT 24
Peak memory 214396 kb
Host smart-b0ff440a-c48d-4173-b162-770cee076fd4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811812508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1811812508
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3089250984
Short name T99
Test name
Test status
Simulation time 4817058210 ps
CPU time 22.51 seconds
Started Jun 22 04:31:26 PM PDT 24
Finished Jun 22 04:31:49 PM PDT 24
Peak memory 213140 kb
Host smart-26d0c4d2-d6fd-4e81-af40-1905232248b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089250984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3089250984
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2563947655
Short name T360
Test name
Test status
Simulation time 46108484819 ps
CPU time 37.06 seconds
Started Jun 22 04:31:25 PM PDT 24
Finished Jun 22 04:32:03 PM PDT 24
Peak memory 219368 kb
Host smart-d9acbaca-68fa-43e8-998e-25b47bcdb456
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563947655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2563947655
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3939577773
Short name T436
Test name
Test status
Simulation time 13201858273 ps
CPU time 168.37 seconds
Started Jun 22 04:31:30 PM PDT 24
Finished Jun 22 04:34:19 PM PDT 24
Peak memory 214824 kb
Host smart-2214938e-1e86-4a23-b586-85ed06eb6291
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939577773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3939577773
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3677118613
Short name T447
Test name
Test status
Simulation time 3371559936 ps
CPU time 27.84 seconds
Started Jun 22 04:31:25 PM PDT 24
Finished Jun 22 04:31:53 PM PDT 24
Peak memory 217348 kb
Host smart-db3cfc4a-c0e8-40d3-9185-cfe0551802d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677118613 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3677118613
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3848991866
Short name T352
Test name
Test status
Simulation time 5833439910 ps
CPU time 26.7 seconds
Started Jun 22 04:31:28 PM PDT 24
Finished Jun 22 04:31:55 PM PDT 24
Peak memory 212552 kb
Host smart-ec554c08-1242-4724-a510-3d7aaf1dc079
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848991866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3848991866
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2613379183
Short name T75
Test name
Test status
Simulation time 2110589759 ps
CPU time 56.8 seconds
Started Jun 22 04:31:30 PM PDT 24
Finished Jun 22 04:32:27 PM PDT 24
Peak memory 219476 kb
Host smart-cacac4a0-5726-467e-a15a-ecfa139099b2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613379183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2613379183
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.732545398
Short name T404
Test name
Test status
Simulation time 5126771453 ps
CPU time 16.03 seconds
Started Jun 22 04:31:25 PM PDT 24
Finished Jun 22 04:31:42 PM PDT 24
Peak memory 212120 kb
Host smart-851a037e-d41e-4fb1-acb6-f2d0df381fd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732545398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.732545398
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.18523830
Short name T358
Test name
Test status
Simulation time 3669951910 ps
CPU time 33.84 seconds
Started Jun 22 04:31:27 PM PDT 24
Finished Jun 22 04:32:02 PM PDT 24
Peak memory 219448 kb
Host smart-14da5abe-0544-4484-8fb7-0f0af74f380c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18523830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.18523830
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1351711827
Short name T64
Test name
Test status
Simulation time 1563101980 ps
CPU time 160 seconds
Started Jun 22 04:31:26 PM PDT 24
Finished Jun 22 04:34:07 PM PDT 24
Peak memory 214312 kb
Host smart-abbd6625-64d9-4601-a60a-a038bbcfe5d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351711827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1351711827
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1026644632
Short name T441
Test name
Test status
Simulation time 20453532686 ps
CPU time 29.45 seconds
Started Jun 22 04:31:34 PM PDT 24
Finished Jun 22 04:32:04 PM PDT 24
Peak memory 218732 kb
Host smart-41ceca69-3141-4cd7-84f1-e52e53563702
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026644632 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1026644632
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3868907999
Short name T453
Test name
Test status
Simulation time 2945119958 ps
CPU time 25.03 seconds
Started Jun 22 04:31:34 PM PDT 24
Finished Jun 22 04:31:59 PM PDT 24
Peak memory 211420 kb
Host smart-cdcf15ae-5ce9-44f2-beb3-e6dd3cdbee55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868907999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3868907999
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1975699063
Short name T102
Test name
Test status
Simulation time 6976438789 ps
CPU time 49.13 seconds
Started Jun 22 04:31:35 PM PDT 24
Finished Jun 22 04:32:25 PM PDT 24
Peak memory 214516 kb
Host smart-9a4b2c54-211d-4b24-8621-c7fff6ccdb2f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975699063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1975699063
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.410020617
Short name T445
Test name
Test status
Simulation time 1965324408 ps
CPU time 19.25 seconds
Started Jun 22 04:31:34 PM PDT 24
Finished Jun 22 04:31:54 PM PDT 24
Peak memory 212136 kb
Host smart-cb041f0c-39fa-4496-808e-25c6c66b209d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410020617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.410020617
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.456749922
Short name T397
Test name
Test status
Simulation time 16897058387 ps
CPU time 37.47 seconds
Started Jun 22 04:31:47 PM PDT 24
Finished Jun 22 04:32:26 PM PDT 24
Peak memory 219524 kb
Host smart-d62ac1a9-e6e8-47ab-877f-e53816fe8aa5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456749922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.456749922
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2707411923
Short name T428
Test name
Test status
Simulation time 4411109622 ps
CPU time 163.64 seconds
Started Jun 22 04:31:35 PM PDT 24
Finished Jun 22 04:34:19 PM PDT 24
Peak memory 214940 kb
Host smart-2a718d45-d24e-4af1-aa42-7737b3b379a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707411923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2707411923
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.662291999
Short name T425
Test name
Test status
Simulation time 2467590443 ps
CPU time 23.15 seconds
Started Jun 22 04:31:34 PM PDT 24
Finished Jun 22 04:31:58 PM PDT 24
Peak memory 218804 kb
Host smart-2dd87225-338a-4d8f-b6c7-d7bd97b006ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662291999 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.662291999
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2448087350
Short name T448
Test name
Test status
Simulation time 2933465085 ps
CPU time 25.65 seconds
Started Jun 22 04:31:39 PM PDT 24
Finished Jun 22 04:32:06 PM PDT 24
Peak memory 211428 kb
Host smart-f19332df-4bfd-489b-82ad-2bfb291c8bc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448087350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2448087350
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3329449036
Short name T449
Test name
Test status
Simulation time 17270020718 ps
CPU time 137.77 seconds
Started Jun 22 04:31:46 PM PDT 24
Finished Jun 22 04:34:06 PM PDT 24
Peak memory 214432 kb
Host smart-a687fadc-9d5d-45f2-9381-da4d0a0ab5a3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329449036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3329449036
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3865002363
Short name T423
Test name
Test status
Simulation time 1721430308 ps
CPU time 18.61 seconds
Started Jun 22 04:31:35 PM PDT 24
Finished Jun 22 04:31:54 PM PDT 24
Peak memory 212756 kb
Host smart-cd6e69af-296b-4f81-990a-255ca3655198
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865002363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3865002363
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.4079042130
Short name T386
Test name
Test status
Simulation time 171079774 ps
CPU time 13.26 seconds
Started Jun 22 04:31:34 PM PDT 24
Finished Jun 22 04:31:48 PM PDT 24
Peak memory 217912 kb
Host smart-fe65b717-7306-430f-8d03-e08d4850d1e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079042130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.4079042130
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1717377276
Short name T419
Test name
Test status
Simulation time 8015545299 ps
CPU time 103.72 seconds
Started Jun 22 04:31:46 PM PDT 24
Finished Jun 22 04:33:32 PM PDT 24
Peak memory 213968 kb
Host smart-0f94d083-528c-4960-8454-73a4f074082f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717377276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1717377276
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1504855491
Short name T399
Test name
Test status
Simulation time 1802092564 ps
CPU time 18.57 seconds
Started Jun 22 04:31:36 PM PDT 24
Finished Jun 22 04:31:55 PM PDT 24
Peak memory 219808 kb
Host smart-f97d6430-a8e3-47ca-b532-bc9e913b2946
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504855491 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1504855491
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1173371054
Short name T70
Test name
Test status
Simulation time 33493792520 ps
CPU time 31.46 seconds
Started Jun 22 04:31:34 PM PDT 24
Finished Jun 22 04:32:06 PM PDT 24
Peak memory 212600 kb
Host smart-e3442534-d042-41eb-a966-06846183a78a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173371054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1173371054
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1135074443
Short name T95
Test name
Test status
Simulation time 1440812302 ps
CPU time 38.94 seconds
Started Jun 22 04:31:35 PM PDT 24
Finished Jun 22 04:32:14 PM PDT 24
Peak memory 214332 kb
Host smart-d2a72893-e22d-4e11-a8bf-768f56a4ee9a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135074443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1135074443
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2434683616
Short name T429
Test name
Test status
Simulation time 12241140910 ps
CPU time 26.4 seconds
Started Jun 22 04:31:46 PM PDT 24
Finished Jun 22 04:32:14 PM PDT 24
Peak memory 213048 kb
Host smart-358ff2d4-cf9d-4d8b-8bfc-a2d4825ab77a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434683616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2434683616
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1683635310
Short name T385
Test name
Test status
Simulation time 172627276 ps
CPU time 11.16 seconds
Started Jun 22 04:31:36 PM PDT 24
Finished Jun 22 04:31:48 PM PDT 24
Peak memory 219420 kb
Host smart-eda2c9c3-c294-4261-b3f1-e989326e46e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683635310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1683635310
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.502773959
Short name T395
Test name
Test status
Simulation time 581884228 ps
CPU time 152.96 seconds
Started Jun 22 04:31:46 PM PDT 24
Finished Jun 22 04:34:21 PM PDT 24
Peak memory 219312 kb
Host smart-004dc667-adf7-4655-aa9a-7a5a0c97e6b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502773959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.502773959
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4130235747
Short name T53
Test name
Test status
Simulation time 1898053433 ps
CPU time 11.37 seconds
Started Jun 22 04:31:41 PM PDT 24
Finished Jun 22 04:31:53 PM PDT 24
Peak memory 214392 kb
Host smart-a95f3de8-6b1b-4d9e-b1f7-2cbdb284f8df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130235747 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.4130235747
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1208595059
Short name T437
Test name
Test status
Simulation time 1001737927 ps
CPU time 11.76 seconds
Started Jun 22 04:31:35 PM PDT 24
Finished Jun 22 04:31:47 PM PDT 24
Peak memory 211484 kb
Host smart-f70d8466-8372-4cb5-b53b-1db32f1d2a49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208595059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1208595059
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.614051830
Short name T377
Test name
Test status
Simulation time 7967874816 ps
CPU time 84.47 seconds
Started Jun 22 04:31:34 PM PDT 24
Finished Jun 22 04:32:59 PM PDT 24
Peak memory 212104 kb
Host smart-4af5af11-17a4-4809-90ef-8979f3c07e43
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614051830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.614051830
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2223084733
Short name T401
Test name
Test status
Simulation time 9846771075 ps
CPU time 23.32 seconds
Started Jun 22 04:31:35 PM PDT 24
Finished Jun 22 04:31:59 PM PDT 24
Peak memory 212980 kb
Host smart-79f249d4-bccc-4e30-b217-4e7d6ebca5d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223084733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2223084733
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2520796934
Short name T376
Test name
Test status
Simulation time 688579321 ps
CPU time 11.04 seconds
Started Jun 22 04:31:40 PM PDT 24
Finished Jun 22 04:31:52 PM PDT 24
Peak memory 217700 kb
Host smart-45ec65e6-7fb4-4f80-866b-b79e8acac32b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520796934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2520796934
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3465032037
Short name T111
Test name
Test status
Simulation time 3182890331 ps
CPU time 165.08 seconds
Started Jun 22 04:31:39 PM PDT 24
Finished Jun 22 04:34:25 PM PDT 24
Peak memory 215576 kb
Host smart-6ed6829a-e0ce-4434-bf87-5cf863b6c4a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465032037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3465032037
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.19078599
Short name T413
Test name
Test status
Simulation time 2115869341 ps
CPU time 20.38 seconds
Started Jun 22 04:31:38 PM PDT 24
Finished Jun 22 04:31:59 PM PDT 24
Peak memory 216336 kb
Host smart-7170f056-61e2-426a-8e48-d8beb466417e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19078599 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.19078599
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.240973148
Short name T442
Test name
Test status
Simulation time 20771259216 ps
CPU time 26.55 seconds
Started Jun 22 04:31:34 PM PDT 24
Finished Jun 22 04:32:02 PM PDT 24
Peak memory 213052 kb
Host smart-6624e43c-bfd9-4c99-bb40-0e7c67d0ac98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240973148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.240973148
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1076897523
Short name T433
Test name
Test status
Simulation time 8795047522 ps
CPU time 108.25 seconds
Started Jun 22 04:31:46 PM PDT 24
Finished Jun 22 04:33:36 PM PDT 24
Peak memory 216112 kb
Host smart-519e0850-4320-4a48-a74b-365085b381ba
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076897523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1076897523
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1457688776
Short name T80
Test name
Test status
Simulation time 3698479769 ps
CPU time 29.02 seconds
Started Jun 22 04:31:36 PM PDT 24
Finished Jun 22 04:32:06 PM PDT 24
Peak memory 212808 kb
Host smart-adce6b53-03a6-460b-b8e0-14df5b03b704
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457688776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1457688776
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3007011936
Short name T446
Test name
Test status
Simulation time 4814110594 ps
CPU time 36.66 seconds
Started Jun 22 04:31:36 PM PDT 24
Finished Jun 22 04:32:13 PM PDT 24
Peak memory 219532 kb
Host smart-b18300d1-d87c-45e6-80e7-38b7855f25c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007011936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.3007011936
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1736542977
Short name T405
Test name
Test status
Simulation time 1154199587 ps
CPU time 154.63 seconds
Started Jun 22 04:31:46 PM PDT 24
Finished Jun 22 04:34:22 PM PDT 24
Peak memory 214560 kb
Host smart-2ab9ecac-d8e5-4427-a73f-71490db5374d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736542977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.1736542977
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4261408252
Short name T443
Test name
Test status
Simulation time 12119052288 ps
CPU time 24.45 seconds
Started Jun 22 04:31:48 PM PDT 24
Finished Jun 22 04:32:14 PM PDT 24
Peak memory 217984 kb
Host smart-08908ca4-759d-40f4-b319-8ab0411e5a96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261408252 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.4261408252
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2492922534
Short name T68
Test name
Test status
Simulation time 1933839448 ps
CPU time 14.12 seconds
Started Jun 22 04:31:42 PM PDT 24
Finished Jun 22 04:31:57 PM PDT 24
Peak memory 211244 kb
Host smart-d9bf58c9-3a4f-46bf-be7a-07a3ea5e85ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492922534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2492922534
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1131698641
Short name T451
Test name
Test status
Simulation time 102699862005 ps
CPU time 193.35 seconds
Started Jun 22 04:31:46 PM PDT 24
Finished Jun 22 04:35:01 PM PDT 24
Peak memory 215604 kb
Host smart-a2cd060f-aa75-4896-bc0b-13938e787fb3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131698641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1131698641
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3650803390
Short name T374
Test name
Test status
Simulation time 2239189932 ps
CPU time 20.75 seconds
Started Jun 22 04:31:45 PM PDT 24
Finished Jun 22 04:32:08 PM PDT 24
Peak memory 212764 kb
Host smart-21431e08-3b32-42d5-bd82-746271b4675d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650803390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3650803390
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.715130327
Short name T372
Test name
Test status
Simulation time 3301065112 ps
CPU time 30.39 seconds
Started Jun 22 04:31:41 PM PDT 24
Finished Jun 22 04:32:12 PM PDT 24
Peak memory 219508 kb
Host smart-7d7ae45a-8453-40e9-8ab8-d06e62a1d9fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715130327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.715130327
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3558849262
Short name T112
Test name
Test status
Simulation time 289219084 ps
CPU time 81.27 seconds
Started Jun 22 04:31:50 PM PDT 24
Finished Jun 22 04:33:12 PM PDT 24
Peak memory 214412 kb
Host smart-d467144f-ba0d-430b-ab33-c6bc05a2331e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558849262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3558849262
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2573335620
Short name T83
Test name
Test status
Simulation time 3753185526 ps
CPU time 14.58 seconds
Started Jun 22 04:31:33 PM PDT 24
Finished Jun 22 04:31:48 PM PDT 24
Peak memory 211476 kb
Host smart-5548fb53-0e54-4af5-a599-b8ef1de4e7de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573335620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2573335620
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.375026514
Short name T97
Test name
Test status
Simulation time 234829659 ps
CPU time 8.09 seconds
Started Jun 22 04:30:58 PM PDT 24
Finished Jun 22 04:31:07 PM PDT 24
Peak memory 211240 kb
Host smart-2ab865fc-ee6f-4004-bac4-1b0657ba38d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375026514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.375026514
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.351446723
Short name T92
Test name
Test status
Simulation time 7943120399 ps
CPU time 37.23 seconds
Started Jun 22 04:31:01 PM PDT 24
Finished Jun 22 04:31:39 PM PDT 24
Peak memory 212888 kb
Host smart-73901fa1-0815-4619-aa82-c21d4797052e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351446723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.351446723
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1988868939
Short name T452
Test name
Test status
Simulation time 182251705 ps
CPU time 8.78 seconds
Started Jun 22 04:31:06 PM PDT 24
Finished Jun 22 04:31:16 PM PDT 24
Peak memory 217428 kb
Host smart-0fd23406-4dbb-4537-927f-9b63ebd3e9fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988868939 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1988868939
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.123651704
Short name T411
Test name
Test status
Simulation time 3549280487 ps
CPU time 19.08 seconds
Started Jun 22 04:31:01 PM PDT 24
Finished Jun 22 04:31:21 PM PDT 24
Peak memory 212540 kb
Host smart-419dbbe5-638b-4679-9acf-5bea1750dbaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123651704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.123651704
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2737798552
Short name T384
Test name
Test status
Simulation time 8269863416 ps
CPU time 14.26 seconds
Started Jun 22 04:31:01 PM PDT 24
Finished Jun 22 04:31:16 PM PDT 24
Peak memory 211236 kb
Host smart-f3fd09a1-4ba4-4cc8-abb4-f280be734e5d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737798552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2737798552
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1875877357
Short name T382
Test name
Test status
Simulation time 2869286769 ps
CPU time 12.11 seconds
Started Jun 22 04:30:59 PM PDT 24
Finished Jun 22 04:31:12 PM PDT 24
Peak memory 211228 kb
Host smart-0833da44-d6e9-4066-b52a-b986d8e19e33
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875877357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1875877357
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2480878988
Short name T420
Test name
Test status
Simulation time 140658905930 ps
CPU time 126.34 seconds
Started Jun 22 04:31:03 PM PDT 24
Finished Jun 22 04:33:09 PM PDT 24
Peak memory 219620 kb
Host smart-4d681fb0-4a20-48d8-8bd0-33362008aaf3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480878988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2480878988
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.768380351
Short name T388
Test name
Test status
Simulation time 1730007831 ps
CPU time 12.44 seconds
Started Jun 22 04:31:08 PM PDT 24
Finished Jun 22 04:31:22 PM PDT 24
Peak memory 212040 kb
Host smart-69ecd82a-eeea-467c-b1e5-e3ac44c65737
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768380351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.768380351
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1434174081
Short name T378
Test name
Test status
Simulation time 16695907503 ps
CPU time 35.54 seconds
Started Jun 22 04:30:59 PM PDT 24
Finished Jun 22 04:31:35 PM PDT 24
Peak memory 219448 kb
Host smart-58f90e1c-837a-472d-9dd8-7e95061b69ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434174081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1434174081
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4102099898
Short name T434
Test name
Test status
Simulation time 2343003335 ps
CPU time 15.06 seconds
Started Jun 22 04:31:06 PM PDT 24
Finished Jun 22 04:31:21 PM PDT 24
Peak memory 212296 kb
Host smart-65828f39-48b3-400d-b080-05d93cf21524
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102099898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.4102099898
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2179606491
Short name T418
Test name
Test status
Simulation time 8919298677 ps
CPU time 21.34 seconds
Started Jun 22 04:31:08 PM PDT 24
Finished Jun 22 04:31:30 PM PDT 24
Peak memory 212476 kb
Host smart-4333d32a-6ff7-44e6-b76f-0107dccb10dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179606491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2179606491
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4206633873
Short name T357
Test name
Test status
Simulation time 520092989 ps
CPU time 13.71 seconds
Started Jun 22 04:31:08 PM PDT 24
Finished Jun 22 04:31:23 PM PDT 24
Peak memory 211304 kb
Host smart-2e69f224-8c83-4a50-a171-1c13b5b5271e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206633873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.4206633873
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1246736150
Short name T407
Test name
Test status
Simulation time 1362420366 ps
CPU time 9.14 seconds
Started Jun 22 04:31:07 PM PDT 24
Finished Jun 22 04:31:17 PM PDT 24
Peak memory 217816 kb
Host smart-0f472124-34bd-4728-af66-b1c7c4a4a5e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246736150 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1246736150
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3517362993
Short name T410
Test name
Test status
Simulation time 3101726467 ps
CPU time 25.86 seconds
Started Jun 22 04:31:10 PM PDT 24
Finished Jun 22 04:31:36 PM PDT 24
Peak memory 212360 kb
Host smart-2b945e15-94aa-4ae4-8fad-fcb69ad2f7e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517362993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3517362993
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2462098517
Short name T368
Test name
Test status
Simulation time 1650531019 ps
CPU time 8.35 seconds
Started Jun 22 04:31:08 PM PDT 24
Finished Jun 22 04:31:17 PM PDT 24
Peak memory 211112 kb
Host smart-6efe44fb-4799-432d-ae50-18d76f93181d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462098517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2462098517
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1499359385
Short name T416
Test name
Test status
Simulation time 1428286839 ps
CPU time 16.68 seconds
Started Jun 22 04:31:08 PM PDT 24
Finished Jun 22 04:31:25 PM PDT 24
Peak memory 211108 kb
Host smart-1325e69a-018f-4449-b4ad-be13b2ac135b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499359385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1499359385
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4242496432
Short name T421
Test name
Test status
Simulation time 1646209966 ps
CPU time 11.04 seconds
Started Jun 22 04:31:08 PM PDT 24
Finished Jun 22 04:31:20 PM PDT 24
Peak memory 211784 kb
Host smart-404bab96-9537-4a90-97a6-fcec29f9cc8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242496432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.4242496432
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4088154826
Short name T426
Test name
Test status
Simulation time 2044910874 ps
CPU time 18.44 seconds
Started Jun 22 04:31:07 PM PDT 24
Finished Jun 22 04:31:27 PM PDT 24
Peak memory 219024 kb
Host smart-6f041bcd-80e3-4c57-a384-15ce476cc70d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088154826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4088154826
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3490486453
Short name T409
Test name
Test status
Simulation time 14762644528 ps
CPU time 98.44 seconds
Started Jun 22 04:31:09 PM PDT 24
Finished Jun 22 04:32:48 PM PDT 24
Peak memory 215204 kb
Host smart-b646c995-6516-4b35-9375-ed73b8126fe1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490486453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3490486453
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1016611327
Short name T90
Test name
Test status
Simulation time 62085538158 ps
CPU time 26.11 seconds
Started Jun 22 04:31:07 PM PDT 24
Finished Jun 22 04:31:34 PM PDT 24
Peak memory 212764 kb
Host smart-98a413bb-d2bb-4629-acae-f023ffda8ebb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016611327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1016611327
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.487271543
Short name T101
Test name
Test status
Simulation time 4723219293 ps
CPU time 21.33 seconds
Started Jun 22 04:31:08 PM PDT 24
Finished Jun 22 04:31:30 PM PDT 24
Peak memory 212520 kb
Host smart-5f37d3fb-37af-499a-86e7-3c26228f94c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487271543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.487271543
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.82880541
Short name T400
Test name
Test status
Simulation time 7549620585 ps
CPU time 37.24 seconds
Started Jun 22 04:31:08 PM PDT 24
Finished Jun 22 04:31:46 PM PDT 24
Peak memory 212820 kb
Host smart-b66f9c91-0800-4289-a8c9-91bb32c3465a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82880541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_res
et.82880541
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.4227036403
Short name T390
Test name
Test status
Simulation time 2792016905 ps
CPU time 23.74 seconds
Started Jun 22 04:31:06 PM PDT 24
Finished Jun 22 04:31:31 PM PDT 24
Peak memory 218356 kb
Host smart-bcad1a4b-dbb8-493e-b842-98fddc49aaa5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227036403 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.4227036403
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1119328310
Short name T364
Test name
Test status
Simulation time 3221735430 ps
CPU time 26.64 seconds
Started Jun 22 04:31:07 PM PDT 24
Finished Jun 22 04:31:35 PM PDT 24
Peak memory 212436 kb
Host smart-d9adde7a-d21e-4d70-80a9-53aed2e2e6d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119328310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1119328310
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2291027735
Short name T389
Test name
Test status
Simulation time 5591664796 ps
CPU time 16.75 seconds
Started Jun 22 04:31:06 PM PDT 24
Finished Jun 22 04:31:23 PM PDT 24
Peak memory 211528 kb
Host smart-ca62f5de-5e2a-40a7-907f-ec6e65942cbd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291027735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2291027735
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4025215284
Short name T412
Test name
Test status
Simulation time 1106608649 ps
CPU time 14.87 seconds
Started Jun 22 04:31:08 PM PDT 24
Finished Jun 22 04:31:24 PM PDT 24
Peak memory 211108 kb
Host smart-651ec3af-01f8-4610-a2fc-01d9eb1b5f75
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025215284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.4025215284
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3620493785
Short name T394
Test name
Test status
Simulation time 11640413499 ps
CPU time 102.48 seconds
Started Jun 22 04:31:08 PM PDT 24
Finished Jun 22 04:32:51 PM PDT 24
Peak memory 219600 kb
Host smart-d9630ff9-7971-4897-ab6a-25ed41a1f650
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620493785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3620493785
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4098308067
Short name T438
Test name
Test status
Simulation time 6924197576 ps
CPU time 26.04 seconds
Started Jun 22 04:31:09 PM PDT 24
Finished Jun 22 04:31:36 PM PDT 24
Peak memory 212968 kb
Host smart-12454315-7aa7-4b74-bfea-66864deae24b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098308067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.4098308067
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1439020636
Short name T422
Test name
Test status
Simulation time 8198682560 ps
CPU time 33.78 seconds
Started Jun 22 04:31:07 PM PDT 24
Finished Jun 22 04:31:41 PM PDT 24
Peak memory 218080 kb
Host smart-d91513df-7d74-4926-9aed-e0a7b3fc7a81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439020636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1439020636
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.757860985
Short name T415
Test name
Test status
Simulation time 17862857368 ps
CPU time 171.14 seconds
Started Jun 22 04:31:07 PM PDT 24
Finished Jun 22 04:33:59 PM PDT 24
Peak memory 214620 kb
Host smart-94539a34-74d9-46fc-a351-9694aaf78f20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757860985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.757860985
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1254375200
Short name T367
Test name
Test status
Simulation time 859835988 ps
CPU time 14.18 seconds
Started Jun 22 04:31:18 PM PDT 24
Finished Jun 22 04:31:33 PM PDT 24
Peak memory 216652 kb
Host smart-69c70317-950d-4f8d-ac81-96027502d3c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254375200 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1254375200
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.28472711
Short name T89
Test name
Test status
Simulation time 6392500103 ps
CPU time 26.33 seconds
Started Jun 22 04:31:18 PM PDT 24
Finished Jun 22 04:31:45 PM PDT 24
Peak memory 212708 kb
Host smart-6a03f7fc-8cd7-4e70-b485-7007303ad3d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28472711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.28472711
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.629318533
Short name T88
Test name
Test status
Simulation time 10214859163 ps
CPU time 54.38 seconds
Started Jun 22 04:31:07 PM PDT 24
Finished Jun 22 04:32:02 PM PDT 24
Peak memory 214396 kb
Host smart-77c96aaa-2c77-4987-a7ec-25c3b517116a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629318533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.629318533
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1302843808
Short name T424
Test name
Test status
Simulation time 167614965 ps
CPU time 8.4 seconds
Started Jun 22 04:31:20 PM PDT 24
Finished Jun 22 04:31:29 PM PDT 24
Peak memory 211632 kb
Host smart-e781e79f-63dd-47e1-95f2-d2174c28f01f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302843808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1302843808
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2620160576
Short name T373
Test name
Test status
Simulation time 5563878516 ps
CPU time 30.25 seconds
Started Jun 22 04:31:20 PM PDT 24
Finished Jun 22 04:31:51 PM PDT 24
Peak memory 219412 kb
Host smart-a8aa75a1-3c54-48cd-bdd9-d926b227f921
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620160576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2620160576
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3590219508
Short name T108
Test name
Test status
Simulation time 284441311 ps
CPU time 151.3 seconds
Started Jun 22 04:31:18 PM PDT 24
Finished Jun 22 04:33:50 PM PDT 24
Peak memory 213636 kb
Host smart-b080ae3b-5955-4891-803c-471a22fe3a50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590219508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3590219508
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2266401359
Short name T432
Test name
Test status
Simulation time 3333646035 ps
CPU time 28.02 seconds
Started Jun 22 04:31:17 PM PDT 24
Finished Jun 22 04:31:46 PM PDT 24
Peak memory 219680 kb
Host smart-0c75fec9-5da0-47b1-8bed-b4dd0827487c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266401359 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2266401359
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.801171189
Short name T363
Test name
Test status
Simulation time 3910950248 ps
CPU time 20.12 seconds
Started Jun 22 04:31:19 PM PDT 24
Finished Jun 22 04:31:40 PM PDT 24
Peak memory 212696 kb
Host smart-6a876de0-6cf3-47d0-8ae8-3178f2897abd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801171189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.801171189
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1871512277
Short name T93
Test name
Test status
Simulation time 180712966377 ps
CPU time 156.46 seconds
Started Jun 22 04:31:19 PM PDT 24
Finished Jun 22 04:33:57 PM PDT 24
Peak memory 219436 kb
Host smart-30eea8d9-fc09-4d5f-87c9-49c40c099641
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871512277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1871512277
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2779213495
Short name T414
Test name
Test status
Simulation time 22584388068 ps
CPU time 20.35 seconds
Started Jun 22 04:31:18 PM PDT 24
Finished Jun 22 04:31:39 PM PDT 24
Peak memory 213156 kb
Host smart-df7f7dd2-3123-4f3e-8fb0-e446f9facf5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779213495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2779213495
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2203862409
Short name T383
Test name
Test status
Simulation time 2547104918 ps
CPU time 29.23 seconds
Started Jun 22 04:31:19 PM PDT 24
Finished Jun 22 04:31:48 PM PDT 24
Peak memory 218112 kb
Host smart-dfd9b6ff-ee6d-4728-8116-1afa4df04cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203862409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2203862409
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3429887644
Short name T109
Test name
Test status
Simulation time 11130603326 ps
CPU time 167.16 seconds
Started Jun 22 04:31:20 PM PDT 24
Finished Jun 22 04:34:07 PM PDT 24
Peak memory 219596 kb
Host smart-8cc7c042-7885-4347-aeb4-3bb02fbf9581
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429887644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3429887644
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2628777049
Short name T356
Test name
Test status
Simulation time 8046132845 ps
CPU time 30.35 seconds
Started Jun 22 04:31:15 PM PDT 24
Finished Jun 22 04:31:45 PM PDT 24
Peak memory 218476 kb
Host smart-a4ff216c-ab7a-4bab-9d59-8a763c4538a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628777049 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2628777049
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.332814919
Short name T439
Test name
Test status
Simulation time 34663227383 ps
CPU time 30.01 seconds
Started Jun 22 04:31:21 PM PDT 24
Finished Jun 22 04:31:51 PM PDT 24
Peak memory 213036 kb
Host smart-fb6ebced-fbe3-4d76-95f8-3f1e20d7ca88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332814919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.332814919
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.917951156
Short name T403
Test name
Test status
Simulation time 39459250854 ps
CPU time 34.24 seconds
Started Jun 22 04:31:38 PM PDT 24
Finished Jun 22 04:32:12 PM PDT 24
Peak memory 213032 kb
Host smart-c3299509-f7c6-48c5-afab-35da1a029b3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917951156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.917951156
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4124254796
Short name T369
Test name
Test status
Simulation time 907042397 ps
CPU time 16.81 seconds
Started Jun 22 04:31:19 PM PDT 24
Finished Jun 22 04:31:36 PM PDT 24
Peak memory 219412 kb
Host smart-7ccadf0f-288f-4912-9d11-b56b2c41c68b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124254796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.4124254796
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2043107519
Short name T387
Test name
Test status
Simulation time 3121874390 ps
CPU time 155.53 seconds
Started Jun 22 04:31:19 PM PDT 24
Finished Jun 22 04:33:56 PM PDT 24
Peak memory 214424 kb
Host smart-e1939e0b-8cda-495f-9358-1cb854596868
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043107519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2043107519
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4152632689
Short name T440
Test name
Test status
Simulation time 739711860 ps
CPU time 9.5 seconds
Started Jun 22 04:31:18 PM PDT 24
Finished Jun 22 04:31:28 PM PDT 24
Peak memory 217972 kb
Host smart-93b9408d-4146-42fc-8f1a-6f2ad470ac9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152632689 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.4152632689
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4051365920
Short name T98
Test name
Test status
Simulation time 6469797185 ps
CPU time 26.05 seconds
Started Jun 22 04:31:48 PM PDT 24
Finished Jun 22 04:32:15 PM PDT 24
Peak memory 212752 kb
Host smart-8c96d31d-2cea-4a90-a6df-9f260918397c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051365920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.4051365920
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3801348454
Short name T96
Test name
Test status
Simulation time 12757268222 ps
CPU time 76.55 seconds
Started Jun 22 04:31:18 PM PDT 24
Finished Jun 22 04:32:36 PM PDT 24
Peak memory 212128 kb
Host smart-e8395285-6a77-44f8-86bc-f39363dad5e5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801348454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3801348454
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.907021107
Short name T78
Test name
Test status
Simulation time 1497243650 ps
CPU time 8.31 seconds
Started Jun 22 04:31:20 PM PDT 24
Finished Jun 22 04:31:29 PM PDT 24
Peak memory 211652 kb
Host smart-ceac83d0-9d0c-4b9a-85cb-dc80451fb028
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907021107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.907021107
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2630195308
Short name T361
Test name
Test status
Simulation time 2052350343 ps
CPU time 13.85 seconds
Started Jun 22 04:31:17 PM PDT 24
Finished Jun 22 04:31:32 PM PDT 24
Peak memory 217788 kb
Host smart-f7f4fa0e-fe99-4e33-b420-99d1449cf638
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630195308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2630195308
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.971768254
Short name T106
Test name
Test status
Simulation time 16091658008 ps
CPU time 174.01 seconds
Started Jun 22 04:31:20 PM PDT 24
Finished Jun 22 04:34:15 PM PDT 24
Peak memory 214804 kb
Host smart-938c9716-9cff-4798-a90f-62917b6ad9df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971768254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.971768254
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1303596531
Short name T392
Test name
Test status
Simulation time 3778259274 ps
CPU time 29.86 seconds
Started Jun 22 04:31:21 PM PDT 24
Finished Jun 22 04:31:51 PM PDT 24
Peak memory 218484 kb
Host smart-7771874d-778c-40d9-b1db-0e1596f5e39d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303596531 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1303596531
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3385103309
Short name T91
Test name
Test status
Simulation time 5118590699 ps
CPU time 15.66 seconds
Started Jun 22 04:31:19 PM PDT 24
Finished Jun 22 04:31:35 PM PDT 24
Peak memory 212380 kb
Host smart-82e529be-370c-4904-b0c9-1a48f39947b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385103309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3385103309
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3174610896
Short name T370
Test name
Test status
Simulation time 5718260086 ps
CPU time 55.43 seconds
Started Jun 22 04:31:19 PM PDT 24
Finished Jun 22 04:32:15 PM PDT 24
Peak memory 219560 kb
Host smart-a2594759-f60a-424a-afc5-a128686a7897
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174610896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3174610896
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3968098303
Short name T79
Test name
Test status
Simulation time 6228876203 ps
CPU time 26.74 seconds
Started Jun 22 04:31:19 PM PDT 24
Finished Jun 22 04:31:47 PM PDT 24
Peak memory 213400 kb
Host smart-4a4ec2bc-1d85-47e3-8ac3-16b6b16d6dac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968098303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3968098303
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2645463666
Short name T379
Test name
Test status
Simulation time 3838295479 ps
CPU time 22.08 seconds
Started Jun 22 04:31:17 PM PDT 24
Finished Jun 22 04:31:40 PM PDT 24
Peak memory 218832 kb
Host smart-f108e2f4-4241-4185-a5f3-c96a3d6a48ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645463666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2645463666
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.246084711
Short name T105
Test name
Test status
Simulation time 14799167333 ps
CPU time 171.1 seconds
Started Jun 22 04:31:18 PM PDT 24
Finished Jun 22 04:34:10 PM PDT 24
Peak memory 213604 kb
Host smart-767c031a-32b6-4160-9e2c-d4b565693dee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246084711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.246084711
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1188184477
Short name T240
Test name
Test status
Simulation time 3356175218 ps
CPU time 27.99 seconds
Started Jun 22 04:36:07 PM PDT 24
Finished Jun 22 04:36:36 PM PDT 24
Peak memory 217032 kb
Host smart-366db018-315c-444b-a28a-06d66b5089d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188184477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1188184477
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1091541263
Short name T127
Test name
Test status
Simulation time 129726438792 ps
CPU time 458.23 seconds
Started Jun 22 04:36:28 PM PDT 24
Finished Jun 22 04:44:07 PM PDT 24
Peak memory 233932 kb
Host smart-2d9c18a1-edc6-417f-b233-fcdbeac849bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091541263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1091541263
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3964793351
Short name T306
Test name
Test status
Simulation time 6986438634 ps
CPU time 61.65 seconds
Started Jun 22 04:36:29 PM PDT 24
Finished Jun 22 04:37:32 PM PDT 24
Peak memory 219136 kb
Host smart-04ea6213-1582-47d5-9825-7e63ca170f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964793351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3964793351
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1731666277
Short name T44
Test name
Test status
Simulation time 3131336049 ps
CPU time 26.67 seconds
Started Jun 22 04:36:05 PM PDT 24
Finished Jun 22 04:36:32 PM PDT 24
Peak memory 219204 kb
Host smart-9382c439-4b38-4330-bbf9-d0fb16b93c19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1731666277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1731666277
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2742300967
Short name T29
Test name
Test status
Simulation time 2125024426 ps
CPU time 127.23 seconds
Started Jun 22 04:36:06 PM PDT 24
Finished Jun 22 04:38:14 PM PDT 24
Peak memory 237104 kb
Host smart-b7e787de-4002-401d-a9c4-a2211cb7beec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742300967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2742300967
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.4044371685
Short name T86
Test name
Test status
Simulation time 13982533719 ps
CPU time 34.71 seconds
Started Jun 22 04:36:06 PM PDT 24
Finished Jun 22 04:36:47 PM PDT 24
Peak memory 217304 kb
Host smart-1a6f9013-1f00-4437-b02f-18b4add506d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044371685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.4044371685
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2364959970
Short name T335
Test name
Test status
Simulation time 751325360 ps
CPU time 10 seconds
Started Jun 22 04:36:13 PM PDT 24
Finished Jun 22 04:36:24 PM PDT 24
Peak memory 218936 kb
Host smart-7e1843c0-91f8-43e5-acb7-6526e673d5b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364959970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2364959970
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.699778914
Short name T316
Test name
Test status
Simulation time 8734613090 ps
CPU time 32.93 seconds
Started Jun 22 04:36:06 PM PDT 24
Finished Jun 22 04:36:40 PM PDT 24
Peak memory 217160 kb
Host smart-44da3711-b923-4512-b2ba-3623adf72f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699778914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.699778914
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2052546891
Short name T152
Test name
Test status
Simulation time 8310538292 ps
CPU time 132.64 seconds
Started Jun 22 04:36:33 PM PDT 24
Finished Jun 22 04:38:47 PM PDT 24
Peak memory 239144 kb
Host smart-77c3bac9-40f3-41b1-8293-305a09a947d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052546891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2052546891
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1694088316
Short name T252
Test name
Test status
Simulation time 4200439168 ps
CPU time 32.32 seconds
Started Jun 22 04:35:58 PM PDT 24
Finished Jun 22 04:36:32 PM PDT 24
Peak memory 218452 kb
Host smart-cb3b20a1-f9e8-419b-8820-4777bcd76127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694088316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1694088316
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3802902436
Short name T30
Test name
Test status
Simulation time 7065292643 ps
CPU time 29.11 seconds
Started Jun 22 04:36:21 PM PDT 24
Finished Jun 22 04:36:51 PM PDT 24
Peak memory 219204 kb
Host smart-be54de9b-25da-4040-a69c-3616ceeeb54d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3802902436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3802902436
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1852229439
Short name T21
Test name
Test status
Simulation time 1028320151 ps
CPU time 117.06 seconds
Started Jun 22 04:36:12 PM PDT 24
Finished Jun 22 04:38:10 PM PDT 24
Peak memory 237160 kb
Host smart-cd3ad314-8590-498f-9eb4-3a16e91c4f62
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852229439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1852229439
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2157658076
Short name T254
Test name
Test status
Simulation time 3738763183 ps
CPU time 42.19 seconds
Started Jun 22 04:36:30 PM PDT 24
Finished Jun 22 04:37:13 PM PDT 24
Peak memory 216520 kb
Host smart-319b975f-0d93-4c48-8e54-433054a049b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157658076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2157658076
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.4088012097
Short name T115
Test name
Test status
Simulation time 1077543702 ps
CPU time 63.37 seconds
Started Jun 22 04:36:36 PM PDT 24
Finished Jun 22 04:37:41 PM PDT 24
Peak memory 219172 kb
Host smart-761bb779-3532-4345-bbf6-a537e911fa98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088012097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.4088012097
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.4034611776
Short name T71
Test name
Test status
Simulation time 2731802222 ps
CPU time 24.71 seconds
Started Jun 22 04:36:27 PM PDT 24
Finished Jun 22 04:36:53 PM PDT 24
Peak memory 216920 kb
Host smart-f3736a03-b5e4-41eb-8689-5a06d03c765c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034611776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.4034611776
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1236484025
Short name T307
Test name
Test status
Simulation time 172660022421 ps
CPU time 423.12 seconds
Started Jun 22 04:36:30 PM PDT 24
Finished Jun 22 04:43:34 PM PDT 24
Peak memory 233444 kb
Host smart-bea465d1-5336-462c-897d-09883edd192f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236484025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1236484025
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1737337778
Short name T159
Test name
Test status
Simulation time 20522429521 ps
CPU time 28.78 seconds
Started Jun 22 04:36:06 PM PDT 24
Finished Jun 22 04:36:36 PM PDT 24
Peak memory 217452 kb
Host smart-f2c1e52f-9495-45a2-998c-eae428484799
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1737337778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1737337778
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3927717384
Short name T191
Test name
Test status
Simulation time 3417615815 ps
CPU time 39.35 seconds
Started Jun 22 04:36:28 PM PDT 24
Finished Jun 22 04:37:08 PM PDT 24
Peak memory 218532 kb
Host smart-304765ad-896e-49ae-a6a8-edc5b8c49003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927717384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3927717384
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2923773223
Short name T123
Test name
Test status
Simulation time 82437406854 ps
CPU time 160.05 seconds
Started Jun 22 04:36:28 PM PDT 24
Finished Jun 22 04:39:10 PM PDT 24
Peak memory 219040 kb
Host smart-b59785a3-8964-4797-a4f3-acd7835545e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923773223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2923773223
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2346191565
Short name T193
Test name
Test status
Simulation time 297078806 ps
CPU time 8.46 seconds
Started Jun 22 04:36:28 PM PDT 24
Finished Jun 22 04:36:38 PM PDT 24
Peak memory 216920 kb
Host smart-70ca41e8-b4be-4031-9955-138ac4666b6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346191565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2346191565
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2797521651
Short name T268
Test name
Test status
Simulation time 14372845405 ps
CPU time 257.01 seconds
Started Jun 22 04:36:41 PM PDT 24
Finished Jun 22 04:40:58 PM PDT 24
Peak memory 219420 kb
Host smart-71e82507-fb36-4ee5-ad3e-e603cfbb212f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797521651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2797521651
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2387677087
Short name T7
Test name
Test status
Simulation time 29231353863 ps
CPU time 66.23 seconds
Started Jun 22 04:36:21 PM PDT 24
Finished Jun 22 04:37:27 PM PDT 24
Peak memory 219108 kb
Host smart-3214669f-9b49-4e5a-b74d-8df40043fdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387677087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2387677087
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3849318592
Short name T26
Test name
Test status
Simulation time 10495153514 ps
CPU time 23.88 seconds
Started Jun 22 04:36:29 PM PDT 24
Finished Jun 22 04:36:54 PM PDT 24
Peak memory 211800 kb
Host smart-661b8ac9-1242-41cc-b9bb-d0179871fc43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3849318592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3849318592
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2770904639
Short name T190
Test name
Test status
Simulation time 2312533591 ps
CPU time 36.47 seconds
Started Jun 22 04:37:25 PM PDT 24
Finished Jun 22 04:38:01 PM PDT 24
Peak memory 216052 kb
Host smart-31c4b263-5b9d-4f09-895e-c4d1c0166117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770904639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2770904639
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2237854037
Short name T117
Test name
Test status
Simulation time 114297176034 ps
CPU time 144.67 seconds
Started Jun 22 04:36:34 PM PDT 24
Finished Jun 22 04:39:00 PM PDT 24
Peak memory 220464 kb
Host smart-b29e46cc-c9d3-4dda-8810-6b4a0cf710c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237854037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2237854037
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1518316044
Short name T322
Test name
Test status
Simulation time 1488907402 ps
CPU time 18.03 seconds
Started Jun 22 04:36:30 PM PDT 24
Finished Jun 22 04:36:49 PM PDT 24
Peak memory 216960 kb
Host smart-bb255615-92be-4bd4-8d94-63d250829502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518316044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1518316044
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.470928121
Short name T32
Test name
Test status
Simulation time 29363550258 ps
CPU time 307.87 seconds
Started Jun 22 04:37:23 PM PDT 24
Finished Jun 22 04:42:31 PM PDT 24
Peak memory 234560 kb
Host smart-4fc5b163-43ed-4758-beef-2625a3011a95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470928121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.470928121
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.4268478487
Short name T170
Test name
Test status
Simulation time 11411177983 ps
CPU time 54.09 seconds
Started Jun 22 04:36:33 PM PDT 24
Finished Jun 22 04:37:28 PM PDT 24
Peak memory 219136 kb
Host smart-fc5b6d0e-addd-4b33-a188-c7b64ee90ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268478487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.4268478487
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3659195991
Short name T250
Test name
Test status
Simulation time 35454949776 ps
CPU time 25.19 seconds
Started Jun 22 04:36:22 PM PDT 24
Finished Jun 22 04:36:47 PM PDT 24
Peak memory 211848 kb
Host smart-b1671dfb-1d7d-49a5-9103-18618602a31a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3659195991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3659195991
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.428918893
Short name T278
Test name
Test status
Simulation time 9256664493 ps
CPU time 45.51 seconds
Started Jun 22 04:36:31 PM PDT 24
Finished Jun 22 04:37:18 PM PDT 24
Peak memory 217024 kb
Host smart-16367d54-77a7-46de-bd30-88817b9b9b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428918893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.428918893
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.4073981905
Short name T136
Test name
Test status
Simulation time 272865632 ps
CPU time 8.27 seconds
Started Jun 22 04:36:35 PM PDT 24
Finished Jun 22 04:36:44 PM PDT 24
Peak memory 216856 kb
Host smart-a79cbcaa-5065-476d-a72f-fecb91aed6f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073981905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.4073981905
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1412003532
Short name T272
Test name
Test status
Simulation time 294404118286 ps
CPU time 757.87 seconds
Started Jun 22 04:36:30 PM PDT 24
Finished Jun 22 04:49:09 PM PDT 24
Peak memory 236176 kb
Host smart-e3458aae-4b84-4e17-b96e-314ac4dd7138
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412003532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1412003532
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.558328731
Short name T298
Test name
Test status
Simulation time 7027453828 ps
CPU time 59.15 seconds
Started Jun 22 04:36:23 PM PDT 24
Finished Jun 22 04:37:23 PM PDT 24
Peak memory 219168 kb
Host smart-967ba8d4-cfb7-4072-8f8b-4170ce999159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558328731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.558328731
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2733462347
Short name T181
Test name
Test status
Simulation time 2366677226 ps
CPU time 17.93 seconds
Started Jun 22 04:36:17 PM PDT 24
Finished Jun 22 04:36:37 PM PDT 24
Peak memory 219176 kb
Host smart-eec89bf3-2823-493a-9ae3-dc8f16d3b5a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2733462347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2733462347
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.637954192
Short name T58
Test name
Test status
Simulation time 350244627 ps
CPU time 20.49 seconds
Started Jun 22 04:36:09 PM PDT 24
Finished Jun 22 04:36:35 PM PDT 24
Peak memory 216180 kb
Host smart-73c4d520-05d2-428f-a7cc-ea632dc8bd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637954192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.637954192
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1335675058
Short name T262
Test name
Test status
Simulation time 3034386881 ps
CPU time 27.32 seconds
Started Jun 22 04:35:58 PM PDT 24
Finished Jun 22 04:36:28 PM PDT 24
Peak memory 214432 kb
Host smart-c36b5961-d81c-4f5a-8e0e-3b14a8bbcd2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335675058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1335675058
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1048297185
Short name T264
Test name
Test status
Simulation time 7013943197 ps
CPU time 20.1 seconds
Started Jun 22 04:36:33 PM PDT 24
Finished Jun 22 04:36:54 PM PDT 24
Peak memory 217116 kb
Host smart-19c0a559-7fc5-4f22-8ab5-5a579b6a8040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048297185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1048297185
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.55280996
Short name T227
Test name
Test status
Simulation time 43186739497 ps
CPU time 596.78 seconds
Started Jun 22 04:37:24 PM PDT 24
Finished Jun 22 04:47:21 PM PDT 24
Peak memory 233232 kb
Host smart-fac93cae-b77d-4a1d-a584-94f67e5dc293
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55280996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_co
rrupt_sig_fatal_chk.55280996
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1493748384
Short name T160
Test name
Test status
Simulation time 13640982332 ps
CPU time 54.82 seconds
Started Jun 22 04:36:27 PM PDT 24
Finished Jun 22 04:37:27 PM PDT 24
Peak memory 219112 kb
Host smart-39d96601-994d-4bc8-bda6-71cbd2716653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493748384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1493748384
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1108642564
Short name T205
Test name
Test status
Simulation time 1114962031 ps
CPU time 13 seconds
Started Jun 22 04:37:24 PM PDT 24
Finished Jun 22 04:37:38 PM PDT 24
Peak memory 217604 kb
Host smart-301c49bd-9053-4d13-ae88-0ff26f9c0709
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1108642564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1108642564
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1550416505
Short name T17
Test name
Test status
Simulation time 355542742 ps
CPU time 20.01 seconds
Started Jun 22 04:36:19 PM PDT 24
Finished Jun 22 04:36:40 PM PDT 24
Peak memory 216100 kb
Host smart-7c47b6ec-8099-4f74-beff-69fa9204f14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550416505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1550416505
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1219377708
Short name T258
Test name
Test status
Simulation time 1289549949 ps
CPU time 16.21 seconds
Started Jun 22 04:36:48 PM PDT 24
Finished Jun 22 04:37:06 PM PDT 24
Peak memory 216744 kb
Host smart-16bffa95-1520-44c8-a4bf-b80a042b7306
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219377708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1219377708
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3058494637
Short name T38
Test name
Test status
Simulation time 5441515167 ps
CPU time 373.82 seconds
Started Jun 22 04:36:38 PM PDT 24
Finished Jun 22 04:42:53 PM PDT 24
Peak memory 234476 kb
Host smart-ade64c34-e4db-46d9-ac4b-db56e5c72276
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058494637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3058494637
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2883657810
Short name T248
Test name
Test status
Simulation time 346306777 ps
CPU time 19.21 seconds
Started Jun 22 04:36:39 PM PDT 24
Finished Jun 22 04:36:59 PM PDT 24
Peak memory 219176 kb
Host smart-431920c7-268f-4202-9d47-b036457256f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883657810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2883657810
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2916423116
Short name T155
Test name
Test status
Simulation time 8666027596 ps
CPU time 21.94 seconds
Started Jun 22 04:36:33 PM PDT 24
Finished Jun 22 04:36:55 PM PDT 24
Peak memory 219176 kb
Host smart-343dfd7b-7ca5-4b46-99e4-3afbfda8a0ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2916423116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2916423116
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3704457174
Short name T299
Test name
Test status
Simulation time 25708068441 ps
CPU time 64.63 seconds
Started Jun 22 04:36:09 PM PDT 24
Finished Jun 22 04:37:14 PM PDT 24
Peak memory 215688 kb
Host smart-4f97bc6b-a2ac-4f59-a0d2-357dba4be2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704457174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3704457174
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1774979978
Short name T265
Test name
Test status
Simulation time 24616745724 ps
CPU time 75.38 seconds
Started Jun 22 04:36:06 PM PDT 24
Finished Jun 22 04:37:23 PM PDT 24
Peak memory 219248 kb
Host smart-7fdee078-31f6-4411-bbc7-df1f5e869e73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774979978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1774979978
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2254921563
Short name T172
Test name
Test status
Simulation time 7007261811 ps
CPU time 29.08 seconds
Started Jun 22 04:36:06 PM PDT 24
Finished Jun 22 04:36:40 PM PDT 24
Peak memory 217292 kb
Host smart-9a725ae9-255f-4b02-a29a-66bd8ce88aa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254921563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2254921563
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3800484850
Short name T296
Test name
Test status
Simulation time 21075156300 ps
CPU time 325.1 seconds
Started Jun 22 04:36:24 PM PDT 24
Finished Jun 22 04:41:50 PM PDT 24
Peak memory 233428 kb
Host smart-b8d86101-8773-44c2-9d23-14eec12ab835
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800484850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3800484850
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.768026677
Short name T173
Test name
Test status
Simulation time 7388719724 ps
CPU time 37.14 seconds
Started Jun 22 04:37:26 PM PDT 24
Finished Jun 22 04:38:03 PM PDT 24
Peak memory 218896 kb
Host smart-316fcd79-f27b-44bd-a205-a733452ab33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768026677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.768026677
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3325959858
Short name T302
Test name
Test status
Simulation time 3643173416 ps
CPU time 29.73 seconds
Started Jun 22 04:36:12 PM PDT 24
Finished Jun 22 04:36:43 PM PDT 24
Peak memory 219288 kb
Host smart-e627678b-2a50-4e7a-b981-9e0dda1aabc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3325959858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3325959858
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.571223873
Short name T192
Test name
Test status
Simulation time 3320139706 ps
CPU time 27.01 seconds
Started Jun 22 04:36:10 PM PDT 24
Finished Jun 22 04:36:37 PM PDT 24
Peak memory 216488 kb
Host smart-94667685-38a4-4275-8f18-0102eefb02c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571223873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.571223873
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2401538617
Short name T198
Test name
Test status
Simulation time 20893195636 ps
CPU time 175.93 seconds
Started Jun 22 04:36:20 PM PDT 24
Finished Jun 22 04:39:16 PM PDT 24
Peak memory 219696 kb
Host smart-ee755967-fa3a-469d-8534-23823bbc8eb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401538617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2401538617
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2920600780
Short name T289
Test name
Test status
Simulation time 1508039895 ps
CPU time 17.68 seconds
Started Jun 22 04:36:31 PM PDT 24
Finished Jun 22 04:36:50 PM PDT 24
Peak memory 216928 kb
Host smart-45016680-ce10-4578-9251-1bd86bfaddfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920600780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2920600780
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1556072342
Short name T47
Test name
Test status
Simulation time 75672055220 ps
CPU time 396.8 seconds
Started Jun 22 04:36:16 PM PDT 24
Finished Jun 22 04:42:54 PM PDT 24
Peak memory 235652 kb
Host smart-40e56a0d-0693-4f7a-bce6-fa99d6a1e4fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556072342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1556072342
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2864654400
Short name T241
Test name
Test status
Simulation time 284321336 ps
CPU time 10.02 seconds
Started Jun 22 04:37:24 PM PDT 24
Finished Jun 22 04:37:35 PM PDT 24
Peak memory 218308 kb
Host smart-2ce6f977-1bf7-46ef-bbf4-cd289dbd72b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2864654400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2864654400
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1324673715
Short name T129
Test name
Test status
Simulation time 2968864947 ps
CPU time 30.45 seconds
Started Jun 22 04:36:30 PM PDT 24
Finished Jun 22 04:37:01 PM PDT 24
Peak memory 216964 kb
Host smart-d6ddc827-7974-4813-a274-f29ec0c35b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324673715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1324673715
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2806249029
Short name T341
Test name
Test status
Simulation time 30179428390 ps
CPU time 63.5 seconds
Started Jun 22 04:37:03 PM PDT 24
Finished Jun 22 04:38:08 PM PDT 24
Peak memory 217720 kb
Host smart-41cd1df1-3f2a-4e48-8c9d-4c42b2b709a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806249029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2806249029
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.941033074
Short name T175
Test name
Test status
Simulation time 3745345476 ps
CPU time 30.47 seconds
Started Jun 22 04:36:28 PM PDT 24
Finished Jun 22 04:37:00 PM PDT 24
Peak memory 217008 kb
Host smart-c86277af-c3ca-4c7f-b686-b38c1f300693
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941033074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.941033074
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3446991517
Short name T277
Test name
Test status
Simulation time 16299638154 ps
CPU time 231.07 seconds
Started Jun 22 04:36:31 PM PDT 24
Finished Jun 22 04:40:23 PM PDT 24
Peak memory 238332 kb
Host smart-a596815d-a260-4533-963a-879abfae44ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446991517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3446991517
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1618388509
Short name T297
Test name
Test status
Simulation time 15108481957 ps
CPU time 64.9 seconds
Started Jun 22 04:36:19 PM PDT 24
Finished Jun 22 04:37:25 PM PDT 24
Peak memory 219228 kb
Host smart-344b99b4-87c5-400b-9694-41c6ced8aef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618388509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1618388509
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2980453746
Short name T179
Test name
Test status
Simulation time 7679326600 ps
CPU time 17.58 seconds
Started Jun 22 04:36:32 PM PDT 24
Finished Jun 22 04:36:51 PM PDT 24
Peak memory 219208 kb
Host smart-d2afdc0e-6e2f-4683-bdba-9f185d32e7e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2980453746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2980453746
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.727560756
Short name T84
Test name
Test status
Simulation time 5665254774 ps
CPU time 19.65 seconds
Started Jun 22 04:36:19 PM PDT 24
Finished Jun 22 04:36:40 PM PDT 24
Peak memory 216552 kb
Host smart-0168b5bb-38f4-40de-8d85-7df535bd35e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727560756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.727560756
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1912405167
Short name T61
Test name
Test status
Simulation time 2119302874 ps
CPU time 39.89 seconds
Started Jun 22 04:36:37 PM PDT 24
Finished Jun 22 04:37:18 PM PDT 24
Peak memory 218676 kb
Host smart-66982271-4690-4f0c-81c7-1b0f514c1802
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912405167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1912405167
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.38640661
Short name T347
Test name
Test status
Simulation time 3913555512 ps
CPU time 20.37 seconds
Started Jun 22 04:36:31 PM PDT 24
Finished Jun 22 04:36:52 PM PDT 24
Peak memory 216928 kb
Host smart-d793455a-1ade-4052-8429-2d318d9db8ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38640661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.38640661
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4210393148
Short name T164
Test name
Test status
Simulation time 164560278431 ps
CPU time 705.66 seconds
Started Jun 22 04:36:37 PM PDT 24
Finished Jun 22 04:48:24 PM PDT 24
Peak memory 233448 kb
Host smart-7ed69c29-225c-4152-bef7-eaef87de6910
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210393148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.4210393148
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.4107711865
Short name T130
Test name
Test status
Simulation time 9277902267 ps
CPU time 61.41 seconds
Started Jun 22 04:36:26 PM PDT 24
Finished Jun 22 04:37:29 PM PDT 24
Peak memory 219132 kb
Host smart-c5b575d5-1dc9-4d69-9845-2bbedc47974c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107711865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.4107711865
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2155543717
Short name T351
Test name
Test status
Simulation time 5531724918 ps
CPU time 18.8 seconds
Started Jun 22 04:36:26 PM PDT 24
Finished Jun 22 04:36:47 PM PDT 24
Peak memory 219180 kb
Host smart-66bb4434-1dc2-40de-8122-3c834516c4d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2155543717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2155543717
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3683950384
Short name T122
Test name
Test status
Simulation time 45988769236 ps
CPU time 131.99 seconds
Started Jun 22 04:36:30 PM PDT 24
Finished Jun 22 04:38:43 PM PDT 24
Peak memory 219768 kb
Host smart-9b2fd00c-a02a-4ef2-8310-8ba1b364dbb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683950384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3683950384
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3248071084
Short name T270
Test name
Test status
Simulation time 688857183 ps
CPU time 8.06 seconds
Started Jun 22 04:36:07 PM PDT 24
Finished Jun 22 04:36:16 PM PDT 24
Peak memory 216828 kb
Host smart-55a44452-5c15-497d-af63-f0404aef9e5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248071084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3248071084
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4207904902
Short name T283
Test name
Test status
Simulation time 43958340751 ps
CPU time 432.83 seconds
Started Jun 22 04:36:22 PM PDT 24
Finished Jun 22 04:43:35 PM PDT 24
Peak memory 237472 kb
Host smart-c4f7672f-6bc2-4568-9bb5-21d278078aba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207904902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.4207904902
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2214839025
Short name T244
Test name
Test status
Simulation time 332580025 ps
CPU time 19.37 seconds
Started Jun 22 04:36:26 PM PDT 24
Finished Jun 22 04:36:46 PM PDT 24
Peak memory 219092 kb
Host smart-c9d05720-61d5-4dc5-9923-bf57974a1207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214839025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2214839025
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3608622504
Short name T224
Test name
Test status
Simulation time 1756004822 ps
CPU time 10.49 seconds
Started Jun 22 04:36:24 PM PDT 24
Finished Jun 22 04:36:36 PM PDT 24
Peak memory 219100 kb
Host smart-62873562-0b4d-4a9a-afd2-740c125e9769
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3608622504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3608622504
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3731945838
Short name T28
Test name
Test status
Simulation time 4339102598 ps
CPU time 141.01 seconds
Started Jun 22 04:35:55 PM PDT 24
Finished Jun 22 04:38:19 PM PDT 24
Peak memory 236080 kb
Host smart-731b9d14-ed40-4fc0-85f4-12888bf89034
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731945838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3731945838
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3712084042
Short name T85
Test name
Test status
Simulation time 29467529871 ps
CPU time 72.58 seconds
Started Jun 22 04:36:11 PM PDT 24
Finished Jun 22 04:37:25 PM PDT 24
Peak memory 217240 kb
Host smart-f3949871-bb26-4623-ae31-4152fabb9085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712084042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3712084042
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2798202600
Short name T56
Test name
Test status
Simulation time 748138862 ps
CPU time 46.24 seconds
Started Jun 22 04:36:26 PM PDT 24
Finished Jun 22 04:37:14 PM PDT 24
Peak memory 220004 kb
Host smart-0bba91eb-722f-415c-a1e0-07dd0dc17401
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798202600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2798202600
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.712977204
Short name T15
Test name
Test status
Simulation time 136774868955 ps
CPU time 1144.15 seconds
Started Jun 22 04:36:27 PM PDT 24
Finished Jun 22 04:55:32 PM PDT 24
Peak memory 235636 kb
Host smart-40b5d487-5e80-4bd2-91f6-920f22bc70f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712977204 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.712977204
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.753730029
Short name T276
Test name
Test status
Simulation time 74210855991 ps
CPU time 416.76 seconds
Started Jun 22 04:36:22 PM PDT 24
Finished Jun 22 04:43:20 PM PDT 24
Peak memory 225728 kb
Host smart-34cb3071-8059-4743-b16f-4005b6fe9a96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753730029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.753730029
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2527350831
Short name T59
Test name
Test status
Simulation time 3751714716 ps
CPU time 42.68 seconds
Started Jun 22 04:36:38 PM PDT 24
Finished Jun 22 04:37:22 PM PDT 24
Peak memory 219052 kb
Host smart-34b4c3b6-54af-49f8-bd25-70cb211c90c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527350831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2527350831
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.338046803
Short name T319
Test name
Test status
Simulation time 15041689207 ps
CPU time 29.77 seconds
Started Jun 22 04:36:39 PM PDT 24
Finished Jun 22 04:37:09 PM PDT 24
Peak memory 211736 kb
Host smart-ba4e8dfd-173c-4e09-8781-fd90d3875485
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=338046803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.338046803
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3653893540
Short name T116
Test name
Test status
Simulation time 3958520306 ps
CPU time 44.03 seconds
Started Jun 22 04:36:31 PM PDT 24
Finished Jun 22 04:37:16 PM PDT 24
Peak memory 216336 kb
Host smart-168eae61-dc62-4d86-898c-7363664c5f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653893540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3653893540
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3976653697
Short name T187
Test name
Test status
Simulation time 17941680096 ps
CPU time 44.85 seconds
Started Jun 22 04:36:26 PM PDT 24
Finished Jun 22 04:37:13 PM PDT 24
Peak memory 217588 kb
Host smart-0e1cd450-1092-4251-8bbe-82b17732e450
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976653697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3976653697
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1612863861
Short name T162
Test name
Test status
Simulation time 661033716 ps
CPU time 8.18 seconds
Started Jun 22 04:36:41 PM PDT 24
Finished Jun 22 04:36:49 PM PDT 24
Peak memory 216928 kb
Host smart-a8d25e2b-ab68-46c7-823e-9b341ffa6a22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612863861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1612863861
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1635664173
Short name T249
Test name
Test status
Simulation time 57555940590 ps
CPU time 435.52 seconds
Started Jun 22 04:36:26 PM PDT 24
Finished Jun 22 04:43:43 PM PDT 24
Peak memory 229160 kb
Host smart-3de78e9f-aa6e-4a7f-b66f-67c99b752019
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635664173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1635664173
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3556088295
Short name T326
Test name
Test status
Simulation time 661340482 ps
CPU time 19.61 seconds
Started Jun 22 04:36:36 PM PDT 24
Finished Jun 22 04:36:57 PM PDT 24
Peak memory 219044 kb
Host smart-778a26a6-1f7b-4e53-878e-6ff4bc0ae3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556088295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3556088295
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1983863093
Short name T139
Test name
Test status
Simulation time 6937815492 ps
CPU time 20.37 seconds
Started Jun 22 04:36:33 PM PDT 24
Finished Jun 22 04:36:54 PM PDT 24
Peak memory 211468 kb
Host smart-d4113066-8df0-45e0-8c30-348d0873cba1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1983863093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1983863093
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2127912152
Short name T134
Test name
Test status
Simulation time 13271473396 ps
CPU time 64.47 seconds
Started Jun 22 04:36:34 PM PDT 24
Finished Jun 22 04:37:39 PM PDT 24
Peak memory 215772 kb
Host smart-350acc58-0290-4a8c-926a-596ee988841b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127912152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2127912152
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2579316387
Short name T178
Test name
Test status
Simulation time 25311515571 ps
CPU time 248.25 seconds
Started Jun 22 04:36:27 PM PDT 24
Finished Jun 22 04:40:37 PM PDT 24
Peak memory 222440 kb
Host smart-8eeed7d5-6c0a-4c36-a1f7-989ff5385eef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579316387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2579316387
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.383867838
Short name T243
Test name
Test status
Simulation time 8600740288 ps
CPU time 34.29 seconds
Started Jun 22 04:36:28 PM PDT 24
Finished Jun 22 04:37:04 PM PDT 24
Peak memory 217176 kb
Host smart-bd03653c-0082-4728-bd93-ca4b4b0d497c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383867838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.383867838
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3065340275
Short name T280
Test name
Test status
Simulation time 3379615372 ps
CPU time 151.73 seconds
Started Jun 22 04:36:41 PM PDT 24
Finished Jun 22 04:39:14 PM PDT 24
Peak memory 238224 kb
Host smart-e336f229-ac00-4aaf-995a-507526f32c8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065340275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3065340275
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1793005873
Short name T340
Test name
Test status
Simulation time 14462524463 ps
CPU time 40.13 seconds
Started Jun 22 04:36:35 PM PDT 24
Finished Jun 22 04:37:17 PM PDT 24
Peak memory 219112 kb
Host smart-6f948742-2d00-4c0f-ac15-28356b463cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793005873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1793005873
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1149145987
Short name T308
Test name
Test status
Simulation time 3422185476 ps
CPU time 16.6 seconds
Started Jun 22 04:36:26 PM PDT 24
Finished Jun 22 04:36:43 PM PDT 24
Peak memory 218740 kb
Host smart-203ca540-e4f2-4826-aa2f-7441183367e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1149145987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1149145987
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.959780230
Short name T219
Test name
Test status
Simulation time 349255347 ps
CPU time 19.58 seconds
Started Jun 22 04:36:36 PM PDT 24
Finished Jun 22 04:36:57 PM PDT 24
Peak memory 218496 kb
Host smart-21f399be-6126-4020-9750-50e5d57ade26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959780230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.959780230
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.564090354
Short name T286
Test name
Test status
Simulation time 611486583 ps
CPU time 45.63 seconds
Started Jun 22 04:36:42 PM PDT 24
Finished Jun 22 04:37:29 PM PDT 24
Peak memory 219096 kb
Host smart-84e0d9dd-2faa-42d7-963a-3ebbce3dbcd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564090354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.564090354
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2005060012
Short name T63
Test name
Test status
Simulation time 3538815606 ps
CPU time 29.92 seconds
Started Jun 22 04:36:28 PM PDT 24
Finished Jun 22 04:36:59 PM PDT 24
Peak memory 216940 kb
Host smart-aef6764c-3f07-490e-a979-14d178dba7d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005060012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2005060012
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2038957509
Short name T149
Test name
Test status
Simulation time 43234890641 ps
CPU time 278.42 seconds
Started Jun 22 04:36:34 PM PDT 24
Finished Jun 22 04:41:13 PM PDT 24
Peak memory 224884 kb
Host smart-e2398d7b-ff15-4362-9b94-bc79a3be90c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038957509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2038957509
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.367830503
Short name T315
Test name
Test status
Simulation time 6012960059 ps
CPU time 54.47 seconds
Started Jun 22 04:36:31 PM PDT 24
Finished Jun 22 04:37:26 PM PDT 24
Peak memory 219160 kb
Host smart-2e590b60-bb07-4645-b8d1-522441b72737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367830503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.367830503
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2552361427
Short name T212
Test name
Test status
Simulation time 25506199994 ps
CPU time 30.64 seconds
Started Jun 22 04:36:27 PM PDT 24
Finished Jun 22 04:37:00 PM PDT 24
Peak memory 217560 kb
Host smart-85436c58-d6ef-4abe-9308-ef1bce801459
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2552361427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2552361427
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.638212856
Short name T257
Test name
Test status
Simulation time 14371037683 ps
CPU time 46.14 seconds
Started Jun 22 04:36:30 PM PDT 24
Finished Jun 22 04:37:17 PM PDT 24
Peak memory 216212 kb
Host smart-fb8d43a9-4905-491a-83f3-19f81a5f5b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638212856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.638212856
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2483721116
Short name T284
Test name
Test status
Simulation time 2033212127 ps
CPU time 86.19 seconds
Started Jun 22 04:36:35 PM PDT 24
Finished Jun 22 04:38:01 PM PDT 24
Peak memory 227304 kb
Host smart-6f982a2f-563e-48c3-ba68-38d7090d57a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483721116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2483721116
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3517317678
Short name T119
Test name
Test status
Simulation time 167639946 ps
CPU time 8.5 seconds
Started Jun 22 04:36:29 PM PDT 24
Finished Jun 22 04:36:39 PM PDT 24
Peak memory 216832 kb
Host smart-508987dc-90c0-44b7-81d8-6ad5ed168b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517317678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3517317678
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3699685764
Short name T231
Test name
Test status
Simulation time 69027346123 ps
CPU time 700.05 seconds
Started Jun 22 04:36:18 PM PDT 24
Finished Jun 22 04:47:59 PM PDT 24
Peak memory 239524 kb
Host smart-85dfe1fe-0c03-45bb-8cd6-98c6a6b9d24f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699685764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3699685764
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3892594027
Short name T41
Test name
Test status
Simulation time 9042374038 ps
CPU time 45.36 seconds
Started Jun 22 04:36:31 PM PDT 24
Finished Jun 22 04:37:18 PM PDT 24
Peak memory 219052 kb
Host smart-f67c5733-41fc-44b2-b863-dd3da24ce2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892594027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3892594027
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2460199252
Short name T235
Test name
Test status
Simulation time 2619199071 ps
CPU time 23.64 seconds
Started Jun 22 04:36:33 PM PDT 24
Finished Jun 22 04:36:57 PM PDT 24
Peak memory 219200 kb
Host smart-e0a900e7-5f20-442f-a4c2-92c4a0bc17c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2460199252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2460199252
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.668597047
Short name T150
Test name
Test status
Simulation time 2163055578 ps
CPU time 32.03 seconds
Started Jun 22 04:36:20 PM PDT 24
Finished Jun 22 04:36:53 PM PDT 24
Peak memory 215972 kb
Host smart-e2d9b9f9-b1a4-48a9-8e84-67104d2daf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668597047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.668597047
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2632118115
Short name T34
Test name
Test status
Simulation time 4247432806 ps
CPU time 35.66 seconds
Started Jun 22 04:36:29 PM PDT 24
Finished Jun 22 04:37:06 PM PDT 24
Peak memory 218964 kb
Host smart-52811417-ebaa-4576-a82c-7ada83a0ac6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632118115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2632118115
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1764184429
Short name T161
Test name
Test status
Simulation time 3658221386 ps
CPU time 18.82 seconds
Started Jun 22 04:36:32 PM PDT 24
Finished Jun 22 04:36:52 PM PDT 24
Peak memory 217024 kb
Host smart-cb0c513d-00d8-4a36-b1e9-00ff9e71d851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764184429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1764184429
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.340782010
Short name T208
Test name
Test status
Simulation time 1321182256 ps
CPU time 18.99 seconds
Started Jun 22 04:36:37 PM PDT 24
Finished Jun 22 04:36:57 PM PDT 24
Peak memory 219156 kb
Host smart-ef3b6e29-a4eb-4b80-a8a5-99bde84db01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340782010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.340782010
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1350588106
Short name T236
Test name
Test status
Simulation time 1887818190 ps
CPU time 20.88 seconds
Started Jun 22 04:36:33 PM PDT 24
Finished Jun 22 04:36:55 PM PDT 24
Peak memory 211192 kb
Host smart-64aafa57-b1c0-498d-937f-6134b920a322
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1350588106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1350588106
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.4091411622
Short name T229
Test name
Test status
Simulation time 3035467221 ps
CPU time 37.68 seconds
Started Jun 22 04:36:29 PM PDT 24
Finished Jun 22 04:37:08 PM PDT 24
Peak memory 215552 kb
Host smart-f38a0933-fc3d-44b8-83e5-6bf7a04ac27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091411622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.4091411622
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.388928030
Short name T267
Test name
Test status
Simulation time 43801749003 ps
CPU time 87.18 seconds
Started Jun 22 04:36:21 PM PDT 24
Finished Jun 22 04:37:48 PM PDT 24
Peak memory 219160 kb
Host smart-602971e0-3a8a-416a-85cb-98e997bd77c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388928030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.388928030
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.73994480
Short name T43
Test name
Test status
Simulation time 22232337790 ps
CPU time 17.68 seconds
Started Jun 22 04:36:34 PM PDT 24
Finished Jun 22 04:36:53 PM PDT 24
Peak memory 217692 kb
Host smart-083c7fcc-f28f-4dfc-9035-01e55ec88a7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73994480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.73994480
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.4157538160
Short name T305
Test name
Test status
Simulation time 289299864808 ps
CPU time 704.87 seconds
Started Jun 22 04:36:31 PM PDT 24
Finished Jun 22 04:48:17 PM PDT 24
Peak memory 236032 kb
Host smart-d9f7bf3f-8b28-4b35-bbe2-69188116f9cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157538160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.4157538160
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4223319667
Short name T209
Test name
Test status
Simulation time 31844310660 ps
CPU time 54.49 seconds
Started Jun 22 04:36:50 PM PDT 24
Finished Jun 22 04:37:48 PM PDT 24
Peak memory 218980 kb
Host smart-66fbf70d-020e-4293-955b-2b69c5de499c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223319667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4223319667
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1220342060
Short name T182
Test name
Test status
Simulation time 689730114 ps
CPU time 10.16 seconds
Started Jun 22 04:36:40 PM PDT 24
Finished Jun 22 04:36:50 PM PDT 24
Peak memory 219144 kb
Host smart-fdd352c1-04c6-42ff-9ed8-25e4fdf526cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1220342060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1220342060
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.951191591
Short name T197
Test name
Test status
Simulation time 350632890 ps
CPU time 19.76 seconds
Started Jun 22 04:36:42 PM PDT 24
Finished Jun 22 04:37:02 PM PDT 24
Peak memory 216172 kb
Host smart-fd6a19f8-aade-4b94-a291-84c2147c2427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951191591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.951191591
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.269626799
Short name T128
Test name
Test status
Simulation time 47556421625 ps
CPU time 130.18 seconds
Started Jun 22 04:36:37 PM PDT 24
Finished Jun 22 04:38:49 PM PDT 24
Peak memory 219364 kb
Host smart-c8f6548f-831f-43a3-b9e7-fbb1e2a1ac53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269626799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.269626799
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1045202166
Short name T279
Test name
Test status
Simulation time 14986178024 ps
CPU time 28.67 seconds
Started Jun 22 04:36:42 PM PDT 24
Finished Jun 22 04:37:12 PM PDT 24
Peak memory 216904 kb
Host smart-e45cc579-f6c9-4cab-857a-93e9d3d5762e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045202166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1045202166
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3091364624
Short name T301
Test name
Test status
Simulation time 97309018199 ps
CPU time 435.87 seconds
Started Jun 22 04:36:45 PM PDT 24
Finished Jun 22 04:44:01 PM PDT 24
Peak memory 216884 kb
Host smart-e8069a67-fd38-4d9a-ba23-9aa5cfd68ee9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091364624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3091364624
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2447767374
Short name T144
Test name
Test status
Simulation time 1374745353 ps
CPU time 19.06 seconds
Started Jun 22 04:36:37 PM PDT 24
Finished Jun 22 04:36:58 PM PDT 24
Peak memory 219068 kb
Host smart-da5f96c2-35bb-4a40-b19b-324786725a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447767374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2447767374
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3264261392
Short name T273
Test name
Test status
Simulation time 353656957 ps
CPU time 10.6 seconds
Started Jun 22 04:36:25 PM PDT 24
Finished Jun 22 04:36:36 PM PDT 24
Peak memory 219516 kb
Host smart-76085f55-a1ce-41e1-a19b-52901bcc3f64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3264261392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3264261392
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2047767121
Short name T245
Test name
Test status
Simulation time 13497502628 ps
CPU time 42.47 seconds
Started Jun 22 04:36:44 PM PDT 24
Finished Jun 22 04:37:26 PM PDT 24
Peak memory 215508 kb
Host smart-66ff4bc6-ba01-4185-a2b7-c809e27b0f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047767121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2047767121
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1973251776
Short name T67
Test name
Test status
Simulation time 1356314888 ps
CPU time 62.3 seconds
Started Jun 22 04:36:31 PM PDT 24
Finished Jun 22 04:37:35 PM PDT 24
Peak memory 219912 kb
Host smart-161e3b85-a6fb-4eb5-ad5a-e5c0ccfe6326
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973251776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1973251776
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1448597309
Short name T215
Test name
Test status
Simulation time 174476647 ps
CPU time 8.45 seconds
Started Jun 22 04:36:30 PM PDT 24
Finished Jun 22 04:36:39 PM PDT 24
Peak memory 216936 kb
Host smart-e2a068ba-e420-4bdf-b610-cf0d84c28c7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448597309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1448597309
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.4076190339
Short name T189
Test name
Test status
Simulation time 151177584119 ps
CPU time 370.86 seconds
Started Jun 22 04:36:33 PM PDT 24
Finished Jun 22 04:42:45 PM PDT 24
Peak memory 233424 kb
Host smart-10c9d38c-b630-49b1-9376-4238bcffe640
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076190339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.4076190339
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.697556319
Short name T218
Test name
Test status
Simulation time 104463627296 ps
CPU time 67.85 seconds
Started Jun 22 04:36:41 PM PDT 24
Finished Jun 22 04:37:50 PM PDT 24
Peak memory 219252 kb
Host smart-a051ead1-12b2-4de3-a6c6-53f25194fd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697556319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.697556319
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3489673101
Short name T9
Test name
Test status
Simulation time 722054170 ps
CPU time 9.91 seconds
Started Jun 22 04:36:42 PM PDT 24
Finished Jun 22 04:36:53 PM PDT 24
Peak memory 219136 kb
Host smart-15dde7d4-7f93-4043-8a3b-b06f43e15a7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3489673101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3489673101
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3917685917
Short name T87
Test name
Test status
Simulation time 749654422 ps
CPU time 19.83 seconds
Started Jun 22 04:36:34 PM PDT 24
Finished Jun 22 04:36:54 PM PDT 24
Peak memory 216852 kb
Host smart-22680e33-76f4-48f3-8efd-735df430ff81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917685917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3917685917
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1075096569
Short name T6
Test name
Test status
Simulation time 12407189856 ps
CPU time 45.56 seconds
Started Jun 22 04:36:27 PM PDT 24
Finished Jun 22 04:37:14 PM PDT 24
Peak memory 215316 kb
Host smart-ca9da12c-df17-4d12-9e16-fd3f539f82f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075096569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1075096569
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2772025057
Short name T31
Test name
Test status
Simulation time 662136522 ps
CPU time 8.38 seconds
Started Jun 22 04:36:42 PM PDT 24
Finished Jun 22 04:36:52 PM PDT 24
Peak memory 216784 kb
Host smart-759fb001-e877-4550-ad60-325f0f8737bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772025057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2772025057
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4199891129
Short name T120
Test name
Test status
Simulation time 98288845772 ps
CPU time 494.78 seconds
Started Jun 22 04:36:37 PM PDT 24
Finished Jun 22 04:44:53 PM PDT 24
Peak memory 239708 kb
Host smart-cae23fab-8a25-4b49-ad8a-082baff8150a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199891129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.4199891129
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.449537434
Short name T188
Test name
Test status
Simulation time 4817930434 ps
CPU time 35.74 seconds
Started Jun 22 04:36:42 PM PDT 24
Finished Jun 22 04:37:18 PM PDT 24
Peak memory 219148 kb
Host smart-74a5b587-4cc1-48be-9336-7284a56bc704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449537434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.449537434
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3608820643
Short name T274
Test name
Test status
Simulation time 7922972885 ps
CPU time 32.07 seconds
Started Jun 22 04:36:47 PM PDT 24
Finished Jun 22 04:37:20 PM PDT 24
Peak memory 219172 kb
Host smart-a752c27c-dfb5-4a8a-9804-c57ffdb85055
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3608820643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3608820643
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.275109712
Short name T207
Test name
Test status
Simulation time 347788031 ps
CPU time 19.91 seconds
Started Jun 22 04:36:44 PM PDT 24
Finished Jun 22 04:37:05 PM PDT 24
Peak memory 215808 kb
Host smart-231d87ef-f361-4e0e-a1c8-296dc5fd70da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275109712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.275109712
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3162851007
Short name T329
Test name
Test status
Simulation time 23729316250 ps
CPU time 200.24 seconds
Started Jun 22 04:36:47 PM PDT 24
Finished Jun 22 04:40:09 PM PDT 24
Peak memory 220768 kb
Host smart-96886da0-9162-46fd-b8fa-75d793320be9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162851007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3162851007
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.631528989
Short name T345
Test name
Test status
Simulation time 15198810022 ps
CPU time 27.16 seconds
Started Jun 22 04:36:29 PM PDT 24
Finished Jun 22 04:36:58 PM PDT 24
Peak memory 217296 kb
Host smart-831f92ee-7da2-453e-9bd1-ef93bcbf0bdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631528989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.631528989
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2961977658
Short name T1
Test name
Test status
Simulation time 315886003103 ps
CPU time 716.31 seconds
Started Jun 22 04:36:23 PM PDT 24
Finished Jun 22 04:48:20 PM PDT 24
Peak memory 219324 kb
Host smart-d47b558c-eed0-481b-aa39-f4bc12e258b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961977658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2961977658
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2646105319
Short name T256
Test name
Test status
Simulation time 5855831458 ps
CPU time 55.26 seconds
Started Jun 22 04:36:25 PM PDT 24
Finished Jun 22 04:37:22 PM PDT 24
Peak memory 219156 kb
Host smart-79502054-680f-4666-b90a-df8cdd25837e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646105319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2646105319
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.219869025
Short name T185
Test name
Test status
Simulation time 1653689589 ps
CPU time 20.29 seconds
Started Jun 22 04:36:31 PM PDT 24
Finished Jun 22 04:36:52 PM PDT 24
Peak memory 217384 kb
Host smart-10c92449-e80b-4353-bea9-9f4b150e28e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=219869025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.219869025
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.692493511
Short name T184
Test name
Test status
Simulation time 75163721329 ps
CPU time 82.1 seconds
Started Jun 22 04:36:15 PM PDT 24
Finished Jun 22 04:37:39 PM PDT 24
Peak memory 216908 kb
Host smart-3f036c41-080d-4d5c-8e0b-f8a8e726cd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692493511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.692493511
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3153903185
Short name T328
Test name
Test status
Simulation time 14913082687 ps
CPU time 66.51 seconds
Started Jun 22 04:36:20 PM PDT 24
Finished Jun 22 04:37:27 PM PDT 24
Peak memory 217220 kb
Host smart-b88e188c-9215-4f50-beb5-3c5316de4285
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153903185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3153903185
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3146863964
Short name T49
Test name
Test status
Simulation time 38085608775 ps
CPU time 2401.41 seconds
Started Jun 22 04:36:30 PM PDT 24
Finished Jun 22 05:16:33 PM PDT 24
Peak memory 233572 kb
Host smart-29623e7c-f382-41d1-8623-3b130122a7f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146863964 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.3146863964
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.438582308
Short name T143
Test name
Test status
Simulation time 3670974188 ps
CPU time 23.3 seconds
Started Jun 22 04:36:38 PM PDT 24
Finished Jun 22 04:37:03 PM PDT 24
Peak memory 217408 kb
Host smart-d059c87f-288d-4424-878f-ad5c2dcdf1b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438582308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.438582308
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2541921739
Short name T131
Test name
Test status
Simulation time 8227096680 ps
CPU time 144.86 seconds
Started Jun 22 04:36:41 PM PDT 24
Finished Jun 22 04:39:07 PM PDT 24
Peak memory 235052 kb
Host smart-e07a85cb-6a65-4260-86a4-5e8903b278eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541921739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2541921739
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.838108840
Short name T331
Test name
Test status
Simulation time 9114718429 ps
CPU time 49.04 seconds
Started Jun 22 04:36:50 PM PDT 24
Finished Jun 22 04:37:43 PM PDT 24
Peak memory 219220 kb
Host smart-baed07a8-e99a-4e37-8c66-15e1cf990586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838108840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.838108840
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.723621964
Short name T210
Test name
Test status
Simulation time 4962048803 ps
CPU time 32.72 seconds
Started Jun 22 04:36:43 PM PDT 24
Finished Jun 22 04:37:16 PM PDT 24
Peak memory 219208 kb
Host smart-c0e9ed29-f731-479b-b205-34e428f6e5d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=723621964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.723621964
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.919976641
Short name T147
Test name
Test status
Simulation time 8993353911 ps
CPU time 48.09 seconds
Started Jun 22 04:36:46 PM PDT 24
Finished Jun 22 04:37:35 PM PDT 24
Peak memory 215920 kb
Host smart-2a96eff5-bebd-4a79-ae7d-496c761f3e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919976641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.919976641
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2227303566
Short name T168
Test name
Test status
Simulation time 7051348916 ps
CPU time 21.21 seconds
Started Jun 22 04:36:49 PM PDT 24
Finished Jun 22 04:37:14 PM PDT 24
Peak memory 217296 kb
Host smart-bd348c8d-30b9-4c61-9132-c412469aad42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227303566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2227303566
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.4106569556
Short name T118
Test name
Test status
Simulation time 14955881284 ps
CPU time 24.5 seconds
Started Jun 22 04:36:31 PM PDT 24
Finished Jun 22 04:36:56 PM PDT 24
Peak memory 217216 kb
Host smart-937d5fab-5c80-4db1-969b-59e5cf03f4a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106569556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.4106569556
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1127162377
Short name T271
Test name
Test status
Simulation time 5549907373 ps
CPU time 364.8 seconds
Started Jun 22 04:36:42 PM PDT 24
Finished Jun 22 04:42:48 PM PDT 24
Peak memory 234804 kb
Host smart-440edefc-911e-4626-98cb-ff6f06a11ce5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127162377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1127162377
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1891109043
Short name T153
Test name
Test status
Simulation time 5839240622 ps
CPU time 53.27 seconds
Started Jun 22 04:36:47 PM PDT 24
Finished Jun 22 04:37:42 PM PDT 24
Peak memory 219136 kb
Host smart-faf57f2c-0a19-4fe9-9e95-395cec7593a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891109043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1891109043
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2161657264
Short name T295
Test name
Test status
Simulation time 5409110946 ps
CPU time 25.28 seconds
Started Jun 22 04:36:42 PM PDT 24
Finished Jun 22 04:37:08 PM PDT 24
Peak memory 219208 kb
Host smart-15bb1943-f342-44e8-ab31-0c7876346290
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2161657264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2161657264
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2051414046
Short name T156
Test name
Test status
Simulation time 13020216757 ps
CPU time 29.34 seconds
Started Jun 22 04:36:56 PM PDT 24
Finished Jun 22 04:37:28 PM PDT 24
Peak memory 216908 kb
Host smart-9db86f52-d982-42ee-8125-89437c158644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051414046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2051414046
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1689779833
Short name T35
Test name
Test status
Simulation time 5659408721 ps
CPU time 67.03 seconds
Started Jun 22 04:36:41 PM PDT 24
Finished Jun 22 04:37:48 PM PDT 24
Peak memory 219136 kb
Host smart-879c597b-108a-490b-b864-f306c23c9d7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689779833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1689779833
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3467276016
Short name T50
Test name
Test status
Simulation time 42821555346 ps
CPU time 3566.05 seconds
Started Jun 22 04:36:40 PM PDT 24
Finished Jun 22 05:36:07 PM PDT 24
Peak memory 230720 kb
Host smart-67bf0454-5e2e-465f-b724-0a46cf26fe9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467276016 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.3467276016
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3410158822
Short name T327
Test name
Test status
Simulation time 34996477524 ps
CPU time 33.91 seconds
Started Jun 22 04:36:51 PM PDT 24
Finished Jun 22 04:37:28 PM PDT 24
Peak memory 217296 kb
Host smart-d9fb951d-b470-44de-9b03-fd10c1cd856f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410158822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3410158822
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.4269377928
Short name T113
Test name
Test status
Simulation time 5862684947 ps
CPU time 196.2 seconds
Started Jun 22 04:36:43 PM PDT 24
Finished Jun 22 04:40:00 PM PDT 24
Peak memory 236528 kb
Host smart-a9c64e29-1ead-4c4a-8afd-d8e12967eff2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269377928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.4269377928
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3776437730
Short name T311
Test name
Test status
Simulation time 4736442938 ps
CPU time 49.18 seconds
Started Jun 22 04:36:46 PM PDT 24
Finished Jun 22 04:37:37 PM PDT 24
Peak memory 219028 kb
Host smart-c851e2b0-71c9-42f8-92e6-28b4194cc214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776437730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3776437730
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1014233461
Short name T138
Test name
Test status
Simulation time 2996985966 ps
CPU time 26.65 seconds
Started Jun 22 04:36:40 PM PDT 24
Finished Jun 22 04:37:08 PM PDT 24
Peak memory 219208 kb
Host smart-9e90a512-ef4c-4722-8f55-e1e8c85eb1ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1014233461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1014233461
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3357116186
Short name T141
Test name
Test status
Simulation time 52592136825 ps
CPU time 55.3 seconds
Started Jun 22 04:36:41 PM PDT 24
Finished Jun 22 04:37:37 PM PDT 24
Peak memory 217700 kb
Host smart-40a30089-4eb5-4af4-980a-f14b2f5f2eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357116186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3357116186
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.352552476
Short name T3
Test name
Test status
Simulation time 1819442284 ps
CPU time 28.38 seconds
Started Jun 22 04:36:47 PM PDT 24
Finished Jun 22 04:37:17 PM PDT 24
Peak memory 219348 kb
Host smart-3df59fee-9f8b-437a-9090-3dcea8afd066
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352552476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.352552476
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3770060008
Short name T337
Test name
Test status
Simulation time 187785682 ps
CPU time 8.53 seconds
Started Jun 22 04:36:48 PM PDT 24
Finished Jun 22 04:36:59 PM PDT 24
Peak memory 216904 kb
Host smart-a8e96504-b70b-4d2f-9d0b-a4923211cb3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770060008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3770060008
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2665041383
Short name T220
Test name
Test status
Simulation time 91547832602 ps
CPU time 416.53 seconds
Started Jun 22 04:36:48 PM PDT 24
Finished Jun 22 04:43:47 PM PDT 24
Peak memory 224504 kb
Host smart-237578e1-0c25-4857-a630-99dec8dd5a1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665041383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2665041383
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2453741698
Short name T154
Test name
Test status
Simulation time 5993555376 ps
CPU time 52.85 seconds
Started Jun 22 04:36:46 PM PDT 24
Finished Jun 22 04:37:40 PM PDT 24
Peak memory 219132 kb
Host smart-0bca576d-eb31-45bc-8131-0d364f6b2f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453741698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2453741698
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3648099641
Short name T246
Test name
Test status
Simulation time 12700541830 ps
CPU time 28.05 seconds
Started Jun 22 04:36:44 PM PDT 24
Finished Jun 22 04:37:12 PM PDT 24
Peak memory 211660 kb
Host smart-aad06f7b-fe2a-409c-9b43-0ce577ff3407
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3648099641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3648099641
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2551774280
Short name T288
Test name
Test status
Simulation time 700384353 ps
CPU time 19.93 seconds
Started Jun 22 04:36:48 PM PDT 24
Finished Jun 22 04:37:11 PM PDT 24
Peak memory 215632 kb
Host smart-b737ad6d-d4da-4464-9afc-51dd7d22984c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551774280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2551774280
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.673401000
Short name T196
Test name
Test status
Simulation time 69985676821 ps
CPU time 169.67 seconds
Started Jun 22 04:36:45 PM PDT 24
Finished Jun 22 04:39:36 PM PDT 24
Peak memory 220592 kb
Host smart-5be68336-d737-4e04-b9ab-6f12967bd587
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673401000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.673401000
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2612482310
Short name T5
Test name
Test status
Simulation time 14360729580 ps
CPU time 29.33 seconds
Started Jun 22 04:36:45 PM PDT 24
Finished Jun 22 04:37:14 PM PDT 24
Peak memory 217288 kb
Host smart-4b53eef3-c1b8-421d-a490-2fc82c2e783b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612482310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2612482310
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3005693
Short name T225
Test name
Test status
Simulation time 212122362274 ps
CPU time 482.58 seconds
Started Jun 22 04:36:47 PM PDT 24
Finished Jun 22 04:44:51 PM PDT 24
Peak memory 216600 kb
Host smart-90e64a4f-1126-49fb-a85a-9bf33981dacb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_s
ig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_cor
rupt_sig_fatal_chk.3005693
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2353625919
Short name T42
Test name
Test status
Simulation time 689062524 ps
CPU time 19.34 seconds
Started Jun 22 04:36:46 PM PDT 24
Finished Jun 22 04:37:07 PM PDT 24
Peak memory 219064 kb
Host smart-9b804cb0-3493-4464-90cf-c5bf39c51bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353625919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2353625919
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1770251129
Short name T171
Test name
Test status
Simulation time 3955846884 ps
CPU time 15.96 seconds
Started Jun 22 04:36:46 PM PDT 24
Finished Jun 22 04:37:03 PM PDT 24
Peak memory 219288 kb
Host smart-f1084d43-4b01-4810-b780-36c529d80ce6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1770251129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1770251129
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2010287140
Short name T18
Test name
Test status
Simulation time 2951440161 ps
CPU time 37.12 seconds
Started Jun 22 04:36:46 PM PDT 24
Finished Jun 22 04:37:25 PM PDT 24
Peak memory 215960 kb
Host smart-9017801f-54e5-4880-9336-9595fa2579d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010287140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2010287140
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3794588230
Short name T137
Test name
Test status
Simulation time 1799340383 ps
CPU time 11.27 seconds
Started Jun 22 04:36:46 PM PDT 24
Finished Jun 22 04:36:58 PM PDT 24
Peak memory 216776 kb
Host smart-c0465b9f-2c85-4428-be71-ee13711b2a77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794588230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3794588230
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3040626696
Short name T148
Test name
Test status
Simulation time 67333622489 ps
CPU time 272.39 seconds
Started Jun 22 04:36:37 PM PDT 24
Finished Jun 22 04:41:11 PM PDT 24
Peak memory 215772 kb
Host smart-41945ca9-0f1a-4e7d-8fe5-1e2c94acb287
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040626696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3040626696
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2537749874
Short name T239
Test name
Test status
Simulation time 15379996688 ps
CPU time 64.1 seconds
Started Jun 22 04:36:40 PM PDT 24
Finished Jun 22 04:37:44 PM PDT 24
Peak memory 219132 kb
Host smart-471d575d-a523-435a-bf87-5a2b3a788607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537749874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2537749874
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1547309600
Short name T281
Test name
Test status
Simulation time 383445257 ps
CPU time 12.09 seconds
Started Jun 22 04:36:42 PM PDT 24
Finished Jun 22 04:36:55 PM PDT 24
Peak memory 218648 kb
Host smart-84e536a6-abdd-4f42-af2f-2c995db02646
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1547309600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1547309600
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3710346674
Short name T201
Test name
Test status
Simulation time 10072455019 ps
CPU time 62.84 seconds
Started Jun 22 04:36:47 PM PDT 24
Finished Jun 22 04:37:51 PM PDT 24
Peak memory 216660 kb
Host smart-e7326c2a-603c-4bcd-b0fe-0493706cfab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710346674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3710346674
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.843514513
Short name T142
Test name
Test status
Simulation time 8846150119 ps
CPU time 47.55 seconds
Started Jun 22 04:36:47 PM PDT 24
Finished Jun 22 04:37:36 PM PDT 24
Peak memory 219052 kb
Host smart-24cd5683-0c0d-4fa5-b357-6085097c6289
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843514513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.843514513
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3778845494
Short name T222
Test name
Test status
Simulation time 5135654677 ps
CPU time 13.98 seconds
Started Jun 22 04:36:48 PM PDT 24
Finished Jun 22 04:37:09 PM PDT 24
Peak memory 217144 kb
Host smart-b60d5062-62aa-49b5-9e3a-7016ae59b6e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778845494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3778845494
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3996729888
Short name T266
Test name
Test status
Simulation time 6255841115 ps
CPU time 193.42 seconds
Started Jun 22 04:36:48 PM PDT 24
Finished Jun 22 04:40:10 PM PDT 24
Peak memory 236532 kb
Host smart-dd33bfd7-b36e-4916-b5af-191d38faf644
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996729888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3996729888
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3189239095
Short name T46
Test name
Test status
Simulation time 53695519870 ps
CPU time 42.38 seconds
Started Jun 22 04:36:37 PM PDT 24
Finished Jun 22 04:37:21 PM PDT 24
Peak memory 219160 kb
Host smart-bdd19307-7085-4327-8372-e0c1dbc585e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189239095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3189239095
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2138134431
Short name T292
Test name
Test status
Simulation time 9574892463 ps
CPU time 24.14 seconds
Started Jun 22 04:36:57 PM PDT 24
Finished Jun 22 04:37:23 PM PDT 24
Peak memory 219316 kb
Host smart-d2145d44-9fb1-4648-a4a2-cae02e83cf5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2138134431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2138134431
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.126669469
Short name T294
Test name
Test status
Simulation time 10321438486 ps
CPU time 55.76 seconds
Started Jun 22 04:36:46 PM PDT 24
Finished Jun 22 04:37:43 PM PDT 24
Peak memory 216756 kb
Host smart-ac7c9063-dda9-4c41-a01c-24a90adb4bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126669469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.126669469
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.569287075
Short name T342
Test name
Test status
Simulation time 15289005050 ps
CPU time 154.04 seconds
Started Jun 22 04:36:49 PM PDT 24
Finished Jun 22 04:39:26 PM PDT 24
Peak memory 219144 kb
Host smart-e831feb4-3c21-4eaa-97ac-9b1a9791219c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569287075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.569287075
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1048322754
Short name T48
Test name
Test status
Simulation time 85952564828 ps
CPU time 3144.2 seconds
Started Jun 22 04:36:39 PM PDT 24
Finished Jun 22 05:29:04 PM PDT 24
Peak memory 252016 kb
Host smart-27ffb820-a91a-46b5-addf-f0ff7cdee0c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048322754 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.1048322754
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1149933610
Short name T318
Test name
Test status
Simulation time 8226041262 ps
CPU time 19.96 seconds
Started Jun 22 04:36:49 PM PDT 24
Finished Jun 22 04:37:12 PM PDT 24
Peak memory 217412 kb
Host smart-4d4a1a7a-5bfe-4198-a526-636e809ec1e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149933610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1149933610
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2947391402
Short name T221
Test name
Test status
Simulation time 78218139472 ps
CPU time 865.81 seconds
Started Jun 22 04:36:47 PM PDT 24
Finished Jun 22 04:51:14 PM PDT 24
Peak memory 236828 kb
Host smart-73c88dec-6e71-4933-83cb-fd53e70383a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947391402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2947391402
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1235665238
Short name T166
Test name
Test status
Simulation time 714085712 ps
CPU time 9.92 seconds
Started Jun 22 04:36:46 PM PDT 24
Finished Jun 22 04:36:58 PM PDT 24
Peak memory 219116 kb
Host smart-c5b75934-0e80-446e-b2d6-854e6f2fdd1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1235665238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1235665238
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1434588360
Short name T199
Test name
Test status
Simulation time 23880981401 ps
CPU time 57.91 seconds
Started Jun 22 04:36:48 PM PDT 24
Finished Jun 22 04:37:54 PM PDT 24
Peak memory 215712 kb
Host smart-753a9f4f-67d3-4ccd-ad66-b12c69b57802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434588360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1434588360
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2497071243
Short name T124
Test name
Test status
Simulation time 31109805015 ps
CPU time 73.67 seconds
Started Jun 22 04:36:36 PM PDT 24
Finished Jun 22 04:37:52 PM PDT 24
Peak memory 219160 kb
Host smart-a464db02-d784-4a05-968d-68854f1025aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497071243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2497071243
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1883284085
Short name T146
Test name
Test status
Simulation time 14222149894 ps
CPU time 30.5 seconds
Started Jun 22 04:37:01 PM PDT 24
Finished Jun 22 04:37:32 PM PDT 24
Peak memory 217296 kb
Host smart-bf472987-d574-49e8-9922-67de91bd87cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883284085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1883284085
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3911852556
Short name T223
Test name
Test status
Simulation time 37350748315 ps
CPU time 410.89 seconds
Started Jun 22 04:36:53 PM PDT 24
Finished Jun 22 04:43:47 PM PDT 24
Peak memory 226656 kb
Host smart-eb3d1817-d673-4b0d-b971-abca4f40ade6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911852556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3911852556
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3605239763
Short name T195
Test name
Test status
Simulation time 9843871328 ps
CPU time 35.96 seconds
Started Jun 22 04:36:48 PM PDT 24
Finished Jun 22 04:37:27 PM PDT 24
Peak memory 219004 kb
Host smart-317fbc4b-a729-4f2f-beec-7939036a3f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605239763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3605239763
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.937152902
Short name T253
Test name
Test status
Simulation time 853082707 ps
CPU time 12.94 seconds
Started Jun 22 04:36:49 PM PDT 24
Finished Jun 22 04:37:05 PM PDT 24
Peak memory 218304 kb
Host smart-9d0d69de-2c82-4a71-9c18-5f3842427afd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=937152902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.937152902
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.803715693
Short name T336
Test name
Test status
Simulation time 33590822534 ps
CPU time 139.22 seconds
Started Jun 22 04:36:46 PM PDT 24
Finished Jun 22 04:39:07 PM PDT 24
Peak memory 219156 kb
Host smart-1c879bb0-c6d9-4bbe-9069-aae655b3fb06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803715693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.803715693
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1751201003
Short name T259
Test name
Test status
Simulation time 6805772156 ps
CPU time 16.26 seconds
Started Jun 22 04:36:48 PM PDT 24
Finished Jun 22 04:37:07 PM PDT 24
Peak memory 217228 kb
Host smart-120ebea1-9764-4a81-936d-5df86ab4cf7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751201003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1751201003
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1636646649
Short name T287
Test name
Test status
Simulation time 73892969930 ps
CPU time 845.05 seconds
Started Jun 22 04:36:50 PM PDT 24
Finished Jun 22 04:50:58 PM PDT 24
Peak memory 239424 kb
Host smart-d04be2dd-912f-4c21-a4c4-92d6220fb4d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636646649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1636646649
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2744100891
Short name T186
Test name
Test status
Simulation time 5810222975 ps
CPU time 36.78 seconds
Started Jun 22 04:36:50 PM PDT 24
Finished Jun 22 04:37:29 PM PDT 24
Peak memory 219080 kb
Host smart-aee911a6-ca59-4ffe-ae50-8049e4ca8bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744100891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2744100891
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3198615445
Short name T338
Test name
Test status
Simulation time 3119776548 ps
CPU time 27.39 seconds
Started Jun 22 04:36:42 PM PDT 24
Finished Jun 22 04:37:11 PM PDT 24
Peak memory 219580 kb
Host smart-bcb0dbd1-3171-420f-af57-b5421942c29c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3198615445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3198615445
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1949535731
Short name T165
Test name
Test status
Simulation time 3237393262 ps
CPU time 37.44 seconds
Started Jun 22 04:36:46 PM PDT 24
Finished Jun 22 04:37:25 PM PDT 24
Peak memory 216820 kb
Host smart-a5b64a6c-dcfe-4c37-860f-d586c8216235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949535731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1949535731
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.386673446
Short name T145
Test name
Test status
Simulation time 3463217241 ps
CPU time 43.2 seconds
Started Jun 22 04:36:50 PM PDT 24
Finished Jun 22 04:37:37 PM PDT 24
Peak memory 219004 kb
Host smart-1a8b4aef-5118-4271-bf41-5af28b5de09b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386673446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.386673446
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1954633624
Short name T310
Test name
Test status
Simulation time 2917845393 ps
CPU time 16.5 seconds
Started Jun 22 04:35:55 PM PDT 24
Finished Jun 22 04:36:14 PM PDT 24
Peak memory 216984 kb
Host smart-64efecc1-7ae6-4ac1-82bb-ba57e441b43f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954633624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1954633624
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2901698789
Short name T303
Test name
Test status
Simulation time 8052981640 ps
CPU time 294.52 seconds
Started Jun 22 04:36:38 PM PDT 24
Finished Jun 22 04:41:34 PM PDT 24
Peak memory 239792 kb
Host smart-4b2c28d0-f5fe-488e-8974-738219c8ae76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901698789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2901698789
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3609032939
Short name T204
Test name
Test status
Simulation time 10259403869 ps
CPU time 47.4 seconds
Started Jun 22 04:36:17 PM PDT 24
Finished Jun 22 04:37:06 PM PDT 24
Peak memory 219136 kb
Host smart-6daf7b1d-ad07-496c-8588-3358a83c313f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609032939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3609032939
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2080584929
Short name T263
Test name
Test status
Simulation time 4944549178 ps
CPU time 16.37 seconds
Started Jun 22 04:36:20 PM PDT 24
Finished Jun 22 04:36:37 PM PDT 24
Peak memory 217456 kb
Host smart-9b1c31df-1362-4c80-884e-09c10138432b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2080584929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2080584929
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3660754077
Short name T23
Test name
Test status
Simulation time 4001492053 ps
CPU time 128.03 seconds
Started Jun 22 04:36:17 PM PDT 24
Finished Jun 22 04:38:26 PM PDT 24
Peak memory 236220 kb
Host smart-35dd9516-49c4-4540-b1d0-064cf62b63b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660754077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3660754077
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1428265399
Short name T324
Test name
Test status
Simulation time 21036568091 ps
CPU time 56.63 seconds
Started Jun 22 04:35:52 PM PDT 24
Finished Jun 22 04:36:49 PM PDT 24
Peak memory 217040 kb
Host smart-02cda09f-727b-406e-af8a-cc68988d59f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428265399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1428265399
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3426221807
Short name T333
Test name
Test status
Simulation time 73044818602 ps
CPU time 59.64 seconds
Started Jun 22 04:36:15 PM PDT 24
Finished Jun 22 04:37:15 PM PDT 24
Peak memory 218036 kb
Host smart-7eede64b-a302-40fc-8ca3-6abb55a6cf93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426221807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3426221807
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3526583221
Short name T24
Test name
Test status
Simulation time 2926128272 ps
CPU time 25.75 seconds
Started Jun 22 04:36:54 PM PDT 24
Finished Jun 22 04:37:23 PM PDT 24
Peak memory 216852 kb
Host smart-08e866c1-68e0-41d6-9cf4-bb02bdf57d47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526583221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3526583221
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1856843585
Short name T214
Test name
Test status
Simulation time 5762854661 ps
CPU time 52.3 seconds
Started Jun 22 04:36:49 PM PDT 24
Finished Jun 22 04:37:44 PM PDT 24
Peak memory 219240 kb
Host smart-48662a0d-3e0b-49b2-a01a-6821baf954f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856843585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1856843585
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.329171228
Short name T194
Test name
Test status
Simulation time 3609942025 ps
CPU time 30.07 seconds
Started Jun 22 04:36:47 PM PDT 24
Finished Jun 22 04:37:20 PM PDT 24
Peak memory 211340 kb
Host smart-c0d0c205-79e1-464a-adb7-4b1b10c52d99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=329171228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.329171228
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3205885418
Short name T320
Test name
Test status
Simulation time 10045966675 ps
CPU time 36.23 seconds
Started Jun 22 04:36:47 PM PDT 24
Finished Jun 22 04:37:26 PM PDT 24
Peak memory 215916 kb
Host smart-c134f65b-9d57-4503-988f-e5186f7d8a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205885418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3205885418
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2684791203
Short name T300
Test name
Test status
Simulation time 8532960962 ps
CPU time 69.41 seconds
Started Jun 22 04:36:53 PM PDT 24
Finished Jun 22 04:38:06 PM PDT 24
Peak memory 216880 kb
Host smart-f3225f75-279c-4b3e-94dc-3d63810dc7cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684791203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2684791203
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3172116695
Short name T73
Test name
Test status
Simulation time 26526616932 ps
CPU time 27.68 seconds
Started Jun 22 04:36:53 PM PDT 24
Finished Jun 22 04:37:24 PM PDT 24
Peak memory 217200 kb
Host smart-23586f79-57ff-4756-89f2-420b62b32ece
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172116695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3172116695
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2343972270
Short name T180
Test name
Test status
Simulation time 144464592166 ps
CPU time 492.78 seconds
Started Jun 22 04:36:44 PM PDT 24
Finished Jun 22 04:44:58 PM PDT 24
Peak memory 237060 kb
Host smart-5804494d-2356-4987-af58-65c25b283fe5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343972270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2343972270
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3568103765
Short name T151
Test name
Test status
Simulation time 18322864062 ps
CPU time 46.68 seconds
Started Jun 22 04:36:51 PM PDT 24
Finished Jun 22 04:37:41 PM PDT 24
Peak memory 218952 kb
Host smart-7f9c2787-662d-444b-baf1-7701465a79d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568103765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3568103765
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1171254897
Short name T321
Test name
Test status
Simulation time 731635993 ps
CPU time 10.28 seconds
Started Jun 22 04:36:52 PM PDT 24
Finished Jun 22 04:37:06 PM PDT 24
Peak memory 219144 kb
Host smart-4249c5be-e478-48e7-9d3f-a0e37f229878
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1171254897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1171254897
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3259420894
Short name T202
Test name
Test status
Simulation time 1202734639 ps
CPU time 18.71 seconds
Started Jun 22 04:36:51 PM PDT 24
Finished Jun 22 04:37:13 PM PDT 24
Peak memory 216008 kb
Host smart-2190451c-d947-4f4d-a87d-4687f02f6b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259420894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3259420894
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1091559867
Short name T344
Test name
Test status
Simulation time 34481507316 ps
CPU time 95.22 seconds
Started Jun 22 04:36:51 PM PDT 24
Finished Jun 22 04:38:29 PM PDT 24
Peak memory 221972 kb
Host smart-f48e2129-8585-478e-bf74-5601362569f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091559867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1091559867
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1162209380
Short name T237
Test name
Test status
Simulation time 991794256 ps
CPU time 13.96 seconds
Started Jun 22 04:36:52 PM PDT 24
Finished Jun 22 04:37:09 PM PDT 24
Peak memory 216828 kb
Host smart-c13d337d-ff41-4a21-80b1-7b468c074890
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162209380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1162209380
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1078076252
Short name T39
Test name
Test status
Simulation time 55371502762 ps
CPU time 697.93 seconds
Started Jun 22 04:36:51 PM PDT 24
Finished Jun 22 04:48:33 PM PDT 24
Peak memory 234412 kb
Host smart-4a19fd66-0b51-4036-a9f0-343614b0deaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078076252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1078076252
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2611684744
Short name T57
Test name
Test status
Simulation time 3410379683 ps
CPU time 24.84 seconds
Started Jun 22 04:36:45 PM PDT 24
Finished Jun 22 04:37:11 PM PDT 24
Peak memory 218196 kb
Host smart-471febd9-c1e3-47b0-8b20-8248d65819d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611684744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2611684744
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2700666710
Short name T213
Test name
Test status
Simulation time 16322148983 ps
CPU time 32.11 seconds
Started Jun 22 04:36:52 PM PDT 24
Finished Jun 22 04:37:28 PM PDT 24
Peak memory 219208 kb
Host smart-d5a132e7-bc35-44a3-b4c9-97876fbe0edd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2700666710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2700666710
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.330101722
Short name T261
Test name
Test status
Simulation time 7693805278 ps
CPU time 63.9 seconds
Started Jun 22 04:36:49 PM PDT 24
Finished Jun 22 04:37:56 PM PDT 24
Peak memory 216964 kb
Host smart-3a7c2b2b-d4a6-46d9-b72b-581c6086c078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330101722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.330101722
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1933013876
Short name T4
Test name
Test status
Simulation time 5321391629 ps
CPU time 42.26 seconds
Started Jun 22 04:36:54 PM PDT 24
Finished Jun 22 04:37:39 PM PDT 24
Peak memory 219024 kb
Host smart-eabd9c53-27c4-400c-bcf2-722bc40c1cf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933013876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1933013876
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1859761924
Short name T312
Test name
Test status
Simulation time 2721166751 ps
CPU time 24.36 seconds
Started Jun 22 04:36:50 PM PDT 24
Finished Jun 22 04:37:17 PM PDT 24
Peak memory 217032 kb
Host smart-dbbf589d-33bf-48f0-b87c-1a1f198e38ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859761924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1859761924
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2783231259
Short name T20
Test name
Test status
Simulation time 91825951861 ps
CPU time 529.67 seconds
Started Jun 22 04:36:48 PM PDT 24
Finished Jun 22 04:45:40 PM PDT 24
Peak memory 239616 kb
Host smart-6f67b118-d491-44e2-8f3f-a47d9756a0d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783231259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2783231259
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3033254307
Short name T251
Test name
Test status
Simulation time 3212167997 ps
CPU time 40.19 seconds
Started Jun 22 04:36:53 PM PDT 24
Finished Jun 22 04:37:37 PM PDT 24
Peak memory 219220 kb
Host smart-5ff496fc-5586-41bd-8571-05b3c152ccf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033254307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3033254307
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3500551559
Short name T290
Test name
Test status
Simulation time 1129639402 ps
CPU time 17.16 seconds
Started Jun 22 04:36:45 PM PDT 24
Finished Jun 22 04:37:03 PM PDT 24
Peak memory 211284 kb
Host smart-22265e29-3105-4cdc-a99c-caa483b69324
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3500551559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3500551559
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3255736421
Short name T121
Test name
Test status
Simulation time 8705341493 ps
CPU time 65.38 seconds
Started Jun 22 04:36:48 PM PDT 24
Finished Jun 22 04:37:57 PM PDT 24
Peak memory 216404 kb
Host smart-193e0883-2ce3-4b40-9e22-c1cf69241c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255736421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3255736421
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.4095199697
Short name T233
Test name
Test status
Simulation time 15144138602 ps
CPU time 84.2 seconds
Started Jun 22 04:36:52 PM PDT 24
Finished Jun 22 04:38:19 PM PDT 24
Peak memory 219164 kb
Host smart-bc0e55b7-20a2-4d28-889d-5176862f68b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095199697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.4095199697
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2261312202
Short name T8
Test name
Test status
Simulation time 2385989272 ps
CPU time 22.25 seconds
Started Jun 22 04:36:51 PM PDT 24
Finished Jun 22 04:37:17 PM PDT 24
Peak memory 217012 kb
Host smart-ce412be4-1203-4a3d-9aa3-331cbbf44930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261312202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2261312202
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1798150338
Short name T126
Test name
Test status
Simulation time 59043562743 ps
CPU time 613.57 seconds
Started Jun 22 04:36:44 PM PDT 24
Finished Jun 22 04:46:58 PM PDT 24
Peak memory 239400 kb
Host smart-7604f929-6fc7-4495-ac3f-ae023941b50f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798150338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1798150338
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.402952694
Short name T135
Test name
Test status
Simulation time 1375490112 ps
CPU time 18.39 seconds
Started Jun 22 04:36:52 PM PDT 24
Finished Jun 22 04:37:14 PM PDT 24
Peak memory 219044 kb
Host smart-87ca5add-93f9-4565-8f34-0c1d7f8570fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402952694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.402952694
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1418340359
Short name T114
Test name
Test status
Simulation time 1389018753 ps
CPU time 18.94 seconds
Started Jun 22 04:36:51 PM PDT 24
Finished Jun 22 04:37:13 PM PDT 24
Peak memory 219136 kb
Host smart-8a7ac956-f6b8-4014-a48c-43dd4fd1e890
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1418340359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1418340359
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1715536888
Short name T55
Test name
Test status
Simulation time 1539186037 ps
CPU time 31.13 seconds
Started Jun 22 04:36:48 PM PDT 24
Finished Jun 22 04:37:22 PM PDT 24
Peak memory 216744 kb
Host smart-8d4cfc75-6a21-4976-bfa2-3879c7c253a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715536888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1715536888
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1938967555
Short name T291
Test name
Test status
Simulation time 6726282463 ps
CPU time 72.01 seconds
Started Jun 22 04:36:53 PM PDT 24
Finished Jun 22 04:38:08 PM PDT 24
Peak memory 222192 kb
Host smart-70de5f3e-5332-4290-9021-fbec970ae57d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938967555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1938967555
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3822116882
Short name T343
Test name
Test status
Simulation time 12987624598 ps
CPU time 27.23 seconds
Started Jun 22 04:36:52 PM PDT 24
Finished Jun 22 04:37:23 PM PDT 24
Peak memory 217288 kb
Host smart-d0a1228a-57f8-488f-95d3-1fc8b3c3429b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822116882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3822116882
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.962203703
Short name T247
Test name
Test status
Simulation time 18582050100 ps
CPU time 174.17 seconds
Started Jun 22 04:36:47 PM PDT 24
Finished Jun 22 04:39:44 PM PDT 24
Peak memory 234004 kb
Host smart-de12ae4e-2503-48a1-864f-b7c1a70bdad0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962203703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.962203703
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1195075485
Short name T133
Test name
Test status
Simulation time 8700119937 ps
CPU time 46.33 seconds
Started Jun 22 04:36:57 PM PDT 24
Finished Jun 22 04:37:45 PM PDT 24
Peak memory 219112 kb
Host smart-cfdb8b90-2771-47e7-afb3-ef85b58dd7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195075485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1195075485
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4136700971
Short name T132
Test name
Test status
Simulation time 650330567 ps
CPU time 10.34 seconds
Started Jun 22 04:36:55 PM PDT 24
Finished Jun 22 04:37:08 PM PDT 24
Peak memory 219144 kb
Host smart-16cce4a6-b276-41f5-ada2-0a9ba382cee8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4136700971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4136700971
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3222657204
Short name T238
Test name
Test status
Simulation time 11366382822 ps
CPU time 35.92 seconds
Started Jun 22 04:36:45 PM PDT 24
Finished Jun 22 04:37:22 PM PDT 24
Peak memory 214344 kb
Host smart-cc69524b-63b6-471b-8a8d-e178db945dcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222657204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3222657204
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2024757399
Short name T60
Test name
Test status
Simulation time 5530132940 ps
CPU time 23.18 seconds
Started Jun 22 04:36:52 PM PDT 24
Finished Jun 22 04:37:19 PM PDT 24
Peak memory 216712 kb
Host smart-db1944ff-0fa6-4a4d-aa3c-e1ca393d3f6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024757399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2024757399
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.588513261
Short name T228
Test name
Test status
Simulation time 155170830900 ps
CPU time 490.82 seconds
Started Jun 22 04:36:54 PM PDT 24
Finished Jun 22 04:45:08 PM PDT 24
Peak memory 238372 kb
Host smart-c07b4c4c-e5a8-4219-a2fa-f60a5538d63c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588513261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.588513261
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2417523640
Short name T158
Test name
Test status
Simulation time 4758257368 ps
CPU time 48.47 seconds
Started Jun 22 04:36:53 PM PDT 24
Finished Jun 22 04:37:45 PM PDT 24
Peak memory 219112 kb
Host smart-e609e949-f58c-4158-90c3-74b23b9d1a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417523640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2417523640
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2266776231
Short name T33
Test name
Test status
Simulation time 722266456 ps
CPU time 10.08 seconds
Started Jun 22 04:36:52 PM PDT 24
Finished Jun 22 04:37:05 PM PDT 24
Peak memory 219104 kb
Host smart-edeaa9eb-0d1f-4678-9d33-a5704e0462e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2266776231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2266776231
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3905565842
Short name T217
Test name
Test status
Simulation time 518388897 ps
CPU time 23.82 seconds
Started Jun 22 04:36:48 PM PDT 24
Finished Jun 22 04:37:15 PM PDT 24
Peak memory 216160 kb
Host smart-fd13e039-b74b-4dfa-a5fc-30b57439e707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905565842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3905565842
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2591388995
Short name T304
Test name
Test status
Simulation time 24136692891 ps
CPU time 233.54 seconds
Started Jun 22 04:36:47 PM PDT 24
Finished Jun 22 04:40:43 PM PDT 24
Peak memory 221684 kb
Host smart-8333c981-549d-4e60-9ef0-dabc3345484f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591388995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2591388995
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3017992631
Short name T200
Test name
Test status
Simulation time 3191496831 ps
CPU time 27.43 seconds
Started Jun 22 04:36:54 PM PDT 24
Finished Jun 22 04:37:24 PM PDT 24
Peak memory 216936 kb
Host smart-0ce99b77-8107-4dd6-843a-1b48dd71a2b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017992631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3017992631
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.587731043
Short name T37
Test name
Test status
Simulation time 13171355864 ps
CPU time 479.96 seconds
Started Jun 22 04:37:19 PM PDT 24
Finished Jun 22 04:45:19 PM PDT 24
Peak memory 225284 kb
Host smart-902ae647-1bca-4905-b3ba-461aba7612d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587731043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.587731043
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.4220494054
Short name T350
Test name
Test status
Simulation time 35787978435 ps
CPU time 54.77 seconds
Started Jun 22 04:36:53 PM PDT 24
Finished Jun 22 04:37:51 PM PDT 24
Peak memory 219076 kb
Host smart-59777f99-97a9-4d57-8194-16ede182766f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220494054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.4220494054
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.317540538
Short name T325
Test name
Test status
Simulation time 4119580121 ps
CPU time 32.59 seconds
Started Jun 22 04:36:56 PM PDT 24
Finished Jun 22 04:37:30 PM PDT 24
Peak memory 219208 kb
Host smart-8cf8b12c-bbae-4951-a359-082f61b311b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=317540538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.317540538
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3401702682
Short name T183
Test name
Test status
Simulation time 22553034624 ps
CPU time 52.44 seconds
Started Jun 22 04:36:50 PM PDT 24
Finished Jun 22 04:37:46 PM PDT 24
Peak memory 216788 kb
Host smart-892bd160-7933-4e2d-88e1-4a33a0afca73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401702682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3401702682
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.93329251
Short name T282
Test name
Test status
Simulation time 1948334906 ps
CPU time 14.57 seconds
Started Jun 22 04:36:56 PM PDT 24
Finished Jun 22 04:37:13 PM PDT 24
Peak memory 219016 kb
Host smart-4e98dec5-bf3d-4b6f-8940-84be0a0d66db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93329251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 47.rom_ctrl_stress_all.93329251
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.94442368
Short name T314
Test name
Test status
Simulation time 6653092084 ps
CPU time 28.38 seconds
Started Jun 22 04:37:01 PM PDT 24
Finished Jun 22 04:37:30 PM PDT 24
Peak memory 217296 kb
Host smart-a8ac7d4c-f5ce-4e04-af90-279d4114891e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94442368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.94442368
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2307596986
Short name T349
Test name
Test status
Simulation time 27923070238 ps
CPU time 280.59 seconds
Started Jun 22 04:36:52 PM PDT 24
Finished Jun 22 04:41:36 PM PDT 24
Peak memory 228104 kb
Host smart-450d05b8-5a80-49cb-8ddc-f90b87ed447a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307596986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2307596986
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3806980460
Short name T27
Test name
Test status
Simulation time 517496733 ps
CPU time 22.67 seconds
Started Jun 22 04:37:00 PM PDT 24
Finished Jun 22 04:37:23 PM PDT 24
Peak memory 219032 kb
Host smart-142fb0e1-9492-46a9-8665-4acd967a2468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806980460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3806980460
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.154759744
Short name T62
Test name
Test status
Simulation time 11521364559 ps
CPU time 31.36 seconds
Started Jun 22 04:36:48 PM PDT 24
Finished Jun 22 04:37:22 PM PDT 24
Peak memory 219176 kb
Host smart-1ddba253-bb32-48d4-af07-1c42511f5532
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=154759744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.154759744
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1841733683
Short name T232
Test name
Test status
Simulation time 14203696947 ps
CPU time 46.19 seconds
Started Jun 22 04:36:58 PM PDT 24
Finished Jun 22 04:37:45 PM PDT 24
Peak memory 219112 kb
Host smart-47f4a772-2265-443b-9360-a435f2eefc37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841733683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1841733683
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3465606743
Short name T72
Test name
Test status
Simulation time 11242904006 ps
CPU time 24.89 seconds
Started Jun 22 04:36:49 PM PDT 24
Finished Jun 22 04:37:17 PM PDT 24
Peak memory 217388 kb
Host smart-c1080b20-665e-4269-800d-558718fe5aab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465606743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3465606743
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1323479472
Short name T66
Test name
Test status
Simulation time 59203204500 ps
CPU time 620.15 seconds
Started Jun 22 04:37:05 PM PDT 24
Finished Jun 22 04:47:26 PM PDT 24
Peak memory 217724 kb
Host smart-0d4a2e40-8912-47eb-bc94-01cafb1c2ec6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323479472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1323479472
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2311912411
Short name T226
Test name
Test status
Simulation time 342624916 ps
CPU time 19.5 seconds
Started Jun 22 04:37:00 PM PDT 24
Finished Jun 22 04:37:20 PM PDT 24
Peak memory 219044 kb
Host smart-cc2c16b6-9394-4c8f-ab7a-d359806ce7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311912411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2311912411
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1918430289
Short name T157
Test name
Test status
Simulation time 2971057636 ps
CPU time 27 seconds
Started Jun 22 04:36:50 PM PDT 24
Finished Jun 22 04:37:20 PM PDT 24
Peak memory 219168 kb
Host smart-27214904-7884-4932-9dd5-4cac69c1d89f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1918430289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1918430289
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.909810534
Short name T19
Test name
Test status
Simulation time 5875666057 ps
CPU time 53.32 seconds
Started Jun 22 04:37:10 PM PDT 24
Finished Jun 22 04:38:04 PM PDT 24
Peak memory 216320 kb
Host smart-d1847abe-eda0-4aba-829a-1ec2acfed558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909810534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.909810534
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.142787045
Short name T293
Test name
Test status
Simulation time 10446568917 ps
CPU time 68.02 seconds
Started Jun 22 04:36:55 PM PDT 24
Finished Jun 22 04:38:06 PM PDT 24
Peak memory 219160 kb
Host smart-47cad6e6-71e6-41cc-bfe8-119bf577b3bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142787045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.142787045
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.1869996163
Short name T16
Test name
Test status
Simulation time 199338064608 ps
CPU time 2090.48 seconds
Started Jun 22 04:36:54 PM PDT 24
Finished Jun 22 05:11:48 PM PDT 24
Peak memory 250480 kb
Host smart-0022f7df-cffb-4f6c-a053-20804de8842a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869996163 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.1869996163
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1144889827
Short name T140
Test name
Test status
Simulation time 12175446567 ps
CPU time 25.51 seconds
Started Jun 22 04:36:02 PM PDT 24
Finished Jun 22 04:36:29 PM PDT 24
Peak memory 217328 kb
Host smart-d11265d4-99a8-4f2e-9362-88ad67218575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144889827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1144889827
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3957969410
Short name T332
Test name
Test status
Simulation time 116469360354 ps
CPU time 231.88 seconds
Started Jun 22 04:36:41 PM PDT 24
Finished Jun 22 04:40:33 PM PDT 24
Peak memory 235964 kb
Host smart-53ed5e99-c9bd-4130-bdfe-8a89e6fe93e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957969410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3957969410
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3301094722
Short name T348
Test name
Test status
Simulation time 1320667373 ps
CPU time 19.26 seconds
Started Jun 22 04:36:19 PM PDT 24
Finished Jun 22 04:36:39 PM PDT 24
Peak memory 219176 kb
Host smart-8c78d729-8a49-4d46-8645-9645e8a5d02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301094722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3301094722
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3963422540
Short name T203
Test name
Test status
Simulation time 1690456214 ps
CPU time 15.81 seconds
Started Jun 22 04:36:10 PM PDT 24
Finished Jun 22 04:36:26 PM PDT 24
Peak memory 219200 kb
Host smart-aadda366-30dc-4857-b0e3-fd705b552270
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3963422540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3963422540
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1164646502
Short name T285
Test name
Test status
Simulation time 4477575608 ps
CPU time 46.75 seconds
Started Jun 22 04:36:02 PM PDT 24
Finished Jun 22 04:36:49 PM PDT 24
Peak memory 216584 kb
Host smart-e90259ca-bdbc-4d2f-b41f-c4d969eaae79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164646502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1164646502
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.339897125
Short name T206
Test name
Test status
Simulation time 18318297564 ps
CPU time 126.72 seconds
Started Jun 22 04:36:11 PM PDT 24
Finished Jun 22 04:38:19 PM PDT 24
Peak memory 227340 kb
Host smart-e3e0343a-3b16-4020-8244-6a2e33f96dc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339897125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.339897125
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1218451825
Short name T255
Test name
Test status
Simulation time 167480755 ps
CPU time 8.37 seconds
Started Jun 22 04:36:14 PM PDT 24
Finished Jun 22 04:36:24 PM PDT 24
Peak memory 216936 kb
Host smart-9d28d752-6270-4a5b-8a3e-556f042b4fe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218451825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1218451825
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4224873908
Short name T323
Test name
Test status
Simulation time 34778828253 ps
CPU time 287.34 seconds
Started Jun 22 04:35:56 PM PDT 24
Finished Jun 22 04:40:46 PM PDT 24
Peak memory 219424 kb
Host smart-d507a9a7-fb31-44a0-b7f6-c5b5f1b04cd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224873908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.4224873908
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.427294778
Short name T334
Test name
Test status
Simulation time 6333715576 ps
CPU time 58.36 seconds
Started Jun 22 04:36:04 PM PDT 24
Finished Jun 22 04:37:03 PM PDT 24
Peak memory 219248 kb
Host smart-64db74d4-6399-44ff-9654-38a6b45adf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427294778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.427294778
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2162800012
Short name T330
Test name
Test status
Simulation time 2234762817 ps
CPU time 24.01 seconds
Started Jun 22 04:36:07 PM PDT 24
Finished Jun 22 04:36:36 PM PDT 24
Peak memory 211312 kb
Host smart-0f66a5b9-1db9-4b9f-b264-833929719a87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2162800012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2162800012
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3006308604
Short name T174
Test name
Test status
Simulation time 1353150853 ps
CPU time 20.76 seconds
Started Jun 22 04:36:33 PM PDT 24
Finished Jun 22 04:36:55 PM PDT 24
Peak memory 216764 kb
Host smart-d8675c7c-78cc-4fbf-8900-d130634e5c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006308604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3006308604
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.75848875
Short name T242
Test name
Test status
Simulation time 10279518705 ps
CPU time 102.37 seconds
Started Jun 22 04:36:06 PM PDT 24
Finished Jun 22 04:37:49 PM PDT 24
Peak memory 219968 kb
Host smart-b9f1ebdd-5f1a-42b9-93ca-a7caafdbc082
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75848875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 6.rom_ctrl_stress_all.75848875
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3333044395
Short name T234
Test name
Test status
Simulation time 2816877509 ps
CPU time 25.62 seconds
Started Jun 22 04:36:33 PM PDT 24
Finished Jun 22 04:36:59 PM PDT 24
Peak memory 216880 kb
Host smart-7fd52fa6-f570-4096-a1da-2febc1c83e86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333044395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3333044395
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1054899679
Short name T313
Test name
Test status
Simulation time 85160900927 ps
CPU time 217.31 seconds
Started Jun 22 04:35:58 PM PDT 24
Finished Jun 22 04:39:41 PM PDT 24
Peak memory 215432 kb
Host smart-80dbcd94-9c28-4644-84f0-2865efa21294
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054899679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1054899679
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.523115748
Short name T40
Test name
Test status
Simulation time 1375754664 ps
CPU time 19.18 seconds
Started Jun 22 04:36:34 PM PDT 24
Finished Jun 22 04:36:54 PM PDT 24
Peak memory 219160 kb
Host smart-5cfdaf0b-398d-4291-94eb-99a598f19512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523115748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.523115748
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.750487538
Short name T309
Test name
Test status
Simulation time 15326161430 ps
CPU time 30.07 seconds
Started Jun 22 04:36:27 PM PDT 24
Finished Jun 22 04:36:58 PM PDT 24
Peak memory 217456 kb
Host smart-f87c8893-d783-42b8-a97f-234d9a7bf17d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=750487538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.750487538
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.184343978
Short name T176
Test name
Test status
Simulation time 4261889457 ps
CPU time 50.4 seconds
Started Jun 22 04:36:00 PM PDT 24
Finished Jun 22 04:36:52 PM PDT 24
Peak memory 215508 kb
Host smart-d89cd44c-6a65-4a3e-b0ff-73f9e304f879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184343978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.184343978
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.4231129179
Short name T260
Test name
Test status
Simulation time 7744913946 ps
CPU time 41.9 seconds
Started Jun 22 04:36:26 PM PDT 24
Finished Jun 22 04:37:09 PM PDT 24
Peak memory 219024 kb
Host smart-508c0a34-cbd2-4679-9821-6b91aa40fd07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231129179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.4231129179
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4092008148
Short name T317
Test name
Test status
Simulation time 3187395083 ps
CPU time 18.39 seconds
Started Jun 22 04:36:14 PM PDT 24
Finished Jun 22 04:36:33 PM PDT 24
Peak memory 217124 kb
Host smart-8e1b4196-e8d3-4b41-b537-737bc0862e86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092008148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4092008148
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3919032085
Short name T275
Test name
Test status
Simulation time 2472433565 ps
CPU time 34.37 seconds
Started Jun 22 04:36:18 PM PDT 24
Finished Jun 22 04:36:54 PM PDT 24
Peak memory 219156 kb
Host smart-5b5bad38-2196-4f00-8f40-eef38f8b6b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919032085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3919032085
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.952319354
Short name T12
Test name
Test status
Simulation time 2613235419 ps
CPU time 16.82 seconds
Started Jun 22 04:36:21 PM PDT 24
Finished Jun 22 04:36:39 PM PDT 24
Peak memory 217568 kb
Host smart-6bad123f-50ce-43e4-b486-4fb0eb52914e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=952319354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.952319354
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1583810363
Short name T167
Test name
Test status
Simulation time 2157188804 ps
CPU time 20.49 seconds
Started Jun 22 04:36:08 PM PDT 24
Finished Jun 22 04:36:29 PM PDT 24
Peak memory 215468 kb
Host smart-217858fe-bd2f-46d1-b752-9eb1415ccb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583810363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1583810363
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3010710780
Short name T2
Test name
Test status
Simulation time 6666610898 ps
CPU time 64.58 seconds
Started Jun 22 04:36:28 PM PDT 24
Finished Jun 22 04:37:34 PM PDT 24
Peak memory 219132 kb
Host smart-91d1337c-b988-40b8-9ee5-6835cdbacdd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010710780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3010710780
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.274729001
Short name T51
Test name
Test status
Simulation time 31041666640 ps
CPU time 657.11 seconds
Started Jun 22 04:36:22 PM PDT 24
Finished Jun 22 04:47:20 PM PDT 24
Peak memory 235656 kb
Host smart-9657e814-06f2-414f-8a25-11c155a6ed6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274729001 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.274729001
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1553990961
Short name T346
Test name
Test status
Simulation time 7281539806 ps
CPU time 17.06 seconds
Started Jun 22 04:36:32 PM PDT 24
Finished Jun 22 04:36:50 PM PDT 24
Peak memory 217440 kb
Host smart-f613b5c0-c792-4c51-a6e4-06f28f764222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553990961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1553990961
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2648906176
Short name T169
Test name
Test status
Simulation time 6897748499 ps
CPU time 103.77 seconds
Started Jun 22 04:36:30 PM PDT 24
Finished Jun 22 04:38:15 PM PDT 24
Peak memory 219412 kb
Host smart-2b4dd8bd-65f6-4c84-acb1-6c59ef67c58f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648906176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2648906176
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.585830527
Short name T211
Test name
Test status
Simulation time 28621646383 ps
CPU time 56.88 seconds
Started Jun 22 04:36:31 PM PDT 24
Finished Jun 22 04:37:29 PM PDT 24
Peak memory 219136 kb
Host smart-c6e9f734-9463-491a-8a7f-6435a285c606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585830527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.585830527
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1995860422
Short name T216
Test name
Test status
Simulation time 689778008 ps
CPU time 10.2 seconds
Started Jun 22 04:36:19 PM PDT 24
Finished Jun 22 04:36:30 PM PDT 24
Peak memory 219140 kb
Host smart-667dbc51-476c-49b7-973f-2cf87acf664f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1995860422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1995860422
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3301427524
Short name T339
Test name
Test status
Simulation time 4387217699 ps
CPU time 33.96 seconds
Started Jun 22 04:36:27 PM PDT 24
Finished Jun 22 04:37:03 PM PDT 24
Peak memory 216836 kb
Host smart-15331ed1-7db0-4567-90fa-18fc9621f06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301427524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3301427524
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3692919919
Short name T230
Test name
Test status
Simulation time 1423987721 ps
CPU time 55.23 seconds
Started Jun 22 04:36:00 PM PDT 24
Finished Jun 22 04:36:57 PM PDT 24
Peak memory 219044 kb
Host smart-bcefa15a-87c4-4152-af9b-84c509b0ff1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692919919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3692919919
Directory /workspace/9.rom_ctrl_stress_all/latest
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