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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.24 96.89 91.99 97.68 100.00 98.28 97.45 98.37


Total test records in report: 455
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T312 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3687570019 Jun 23 05:37:17 PM PDT 24 Jun 23 05:44:41 PM PDT 24 23927967654 ps
T313 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3102650428 Jun 23 05:38:21 PM PDT 24 Jun 23 05:38:37 PM PDT 24 783196998 ps
T314 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3928407806 Jun 23 05:37:24 PM PDT 24 Jun 23 05:37:43 PM PDT 24 5288697513 ps
T315 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1417481342 Jun 23 05:38:52 PM PDT 24 Jun 23 05:39:11 PM PDT 24 662278429 ps
T316 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.849731998 Jun 23 05:38:30 PM PDT 24 Jun 23 05:39:15 PM PDT 24 74915938131 ps
T317 /workspace/coverage/default/36.rom_ctrl_smoke.124289066 Jun 23 05:38:14 PM PDT 24 Jun 23 05:39:19 PM PDT 24 28824279905 ps
T318 /workspace/coverage/default/6.rom_ctrl_stress_all.1220159132 Jun 23 05:37:24 PM PDT 24 Jun 23 05:39:24 PM PDT 24 11080753000 ps
T319 /workspace/coverage/default/37.rom_ctrl_alert_test.2997767414 Jun 23 05:38:26 PM PDT 24 Jun 23 05:38:34 PM PDT 24 167572736 ps
T320 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.903993784 Jun 23 05:37:23 PM PDT 24 Jun 23 05:44:52 PM PDT 24 51354961135 ps
T321 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1254937206 Jun 23 05:37:36 PM PDT 24 Jun 23 05:38:06 PM PDT 24 13690729786 ps
T322 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1512961292 Jun 23 05:38:44 PM PDT 24 Jun 23 05:46:00 PM PDT 24 32370558487 ps
T323 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.885248898 Jun 23 05:37:54 PM PDT 24 Jun 23 05:38:23 PM PDT 24 37946857713 ps
T324 /workspace/coverage/default/40.rom_ctrl_smoke.1885572474 Jun 23 05:38:29 PM PDT 24 Jun 23 05:39:06 PM PDT 24 2149881884 ps
T325 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3073547039 Jun 23 05:37:54 PM PDT 24 Jun 23 05:38:10 PM PDT 24 614275541 ps
T326 /workspace/coverage/default/2.rom_ctrl_alert_test.3605130695 Jun 23 05:37:20 PM PDT 24 Jun 23 05:37:41 PM PDT 24 7579465395 ps
T93 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3894891980 Jun 23 05:37:55 PM PDT 24 Jun 23 05:38:26 PM PDT 24 24154585214 ps
T94 /workspace/coverage/default/41.rom_ctrl_alert_test.4026871704 Jun 23 05:38:34 PM PDT 24 Jun 23 05:38:43 PM PDT 24 167583642 ps
T95 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3268953848 Jun 23 05:37:19 PM PDT 24 Jun 23 05:37:50 PM PDT 24 13787741495 ps
T96 /workspace/coverage/default/13.rom_ctrl_smoke.3904376204 Jun 23 05:37:33 PM PDT 24 Jun 23 05:38:42 PM PDT 24 7542354573 ps
T97 /workspace/coverage/default/1.rom_ctrl_smoke.2611444949 Jun 23 05:37:17 PM PDT 24 Jun 23 05:38:22 PM PDT 24 55025621681 ps
T98 /workspace/coverage/default/31.rom_ctrl_stress_all.3189979546 Jun 23 05:37:54 PM PDT 24 Jun 23 05:39:12 PM PDT 24 35574950972 ps
T99 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2675930925 Jun 23 05:37:41 PM PDT 24 Jun 23 05:37:58 PM PDT 24 3833487077 ps
T100 /workspace/coverage/default/39.rom_ctrl_alert_test.2054370248 Jun 23 05:38:31 PM PDT 24 Jun 23 05:38:48 PM PDT 24 4795154179 ps
T101 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.294062893 Jun 23 05:38:38 PM PDT 24 Jun 23 05:43:33 PM PDT 24 11885907002 ps
T102 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2823581925 Jun 23 05:38:35 PM PDT 24 Jun 23 05:39:22 PM PDT 24 20144503744 ps
T327 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1157615503 Jun 23 05:37:31 PM PDT 24 Jun 23 05:37:43 PM PDT 24 179900889 ps
T328 /workspace/coverage/default/4.rom_ctrl_alert_test.531418886 Jun 23 05:37:26 PM PDT 24 Jun 23 05:37:37 PM PDT 24 917802233 ps
T329 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2653535868 Jun 23 05:37:58 PM PDT 24 Jun 23 05:38:20 PM PDT 24 1812408204 ps
T330 /workspace/coverage/default/38.rom_ctrl_stress_all.3505186829 Jun 23 05:38:24 PM PDT 24 Jun 23 05:39:01 PM PDT 24 548970178 ps
T331 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1309156080 Jun 23 05:37:40 PM PDT 24 Jun 23 05:38:00 PM PDT 24 345914239 ps
T332 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.530691202 Jun 23 05:37:54 PM PDT 24 Jun 23 05:38:15 PM PDT 24 6828635881 ps
T333 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2811617405 Jun 23 05:37:44 PM PDT 24 Jun 23 05:38:06 PM PDT 24 1968055432 ps
T334 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.739483711 Jun 23 05:37:38 PM PDT 24 Jun 23 05:37:48 PM PDT 24 366588149 ps
T335 /workspace/coverage/default/31.rom_ctrl_smoke.1057761458 Jun 23 05:37:58 PM PDT 24 Jun 23 05:38:54 PM PDT 24 5323448456 ps
T336 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2473007311 Jun 23 05:37:55 PM PDT 24 Jun 23 05:38:07 PM PDT 24 178692283 ps
T337 /workspace/coverage/default/3.rom_ctrl_alert_test.1802673538 Jun 23 05:37:20 PM PDT 24 Jun 23 05:37:54 PM PDT 24 17805474164 ps
T338 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1532966870 Jun 23 05:38:39 PM PDT 24 Jun 23 05:39:07 PM PDT 24 14752441433 ps
T339 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.355204996 Jun 23 05:37:31 PM PDT 24 Jun 23 05:38:34 PM PDT 24 48026869592 ps
T340 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2748948546 Jun 23 05:38:35 PM PDT 24 Jun 23 05:38:55 PM PDT 24 768706093 ps
T341 /workspace/coverage/default/43.rom_ctrl_stress_all.504303909 Jun 23 05:38:38 PM PDT 24 Jun 23 05:39:42 PM PDT 24 8802270553 ps
T342 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3556537765 Jun 23 05:37:54 PM PDT 24 Jun 23 05:40:53 PM PDT 24 24384846567 ps
T343 /workspace/coverage/default/45.rom_ctrl_stress_all.1017249512 Jun 23 05:38:38 PM PDT 24 Jun 23 05:39:42 PM PDT 24 6617329846 ps
T344 /workspace/coverage/default/39.rom_ctrl_smoke.921804322 Jun 23 05:38:26 PM PDT 24 Jun 23 05:39:06 PM PDT 24 3282230109 ps
T345 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1326608721 Jun 23 05:37:53 PM PDT 24 Jun 23 05:39:31 PM PDT 24 1427881318 ps
T346 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.395747858 Jun 23 05:37:25 PM PDT 24 Jun 23 05:45:16 PM PDT 24 147401744814 ps
T347 /workspace/coverage/default/22.rom_ctrl_alert_test.1592085900 Jun 23 05:37:46 PM PDT 24 Jun 23 05:37:59 PM PDT 24 665836655 ps
T348 /workspace/coverage/default/47.rom_ctrl_alert_test.3527897173 Jun 23 05:38:46 PM PDT 24 Jun 23 05:39:13 PM PDT 24 39780565972 ps
T349 /workspace/coverage/default/2.rom_ctrl_stress_all.2087159426 Jun 23 05:37:20 PM PDT 24 Jun 23 05:37:50 PM PDT 24 1100407100 ps
T350 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2846275575 Jun 23 05:38:13 PM PDT 24 Jun 23 05:39:09 PM PDT 24 24724953212 ps
T351 /workspace/coverage/default/0.rom_ctrl_stress_all.2211075310 Jun 23 05:37:15 PM PDT 24 Jun 23 05:38:15 PM PDT 24 14438949031 ps
T352 /workspace/coverage/default/19.rom_ctrl_alert_test.518067973 Jun 23 05:37:41 PM PDT 24 Jun 23 05:38:13 PM PDT 24 3993624220 ps
T24 /workspace/coverage/default/0.rom_ctrl_sec_cm.2169009644 Jun 23 05:37:17 PM PDT 24 Jun 23 05:41:05 PM PDT 24 328437330 ps
T353 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.58466637 Jun 23 05:37:13 PM PDT 24 Jun 23 05:37:29 PM PDT 24 774514282 ps
T354 /workspace/coverage/default/2.rom_ctrl_smoke.926888562 Jun 23 05:37:17 PM PDT 24 Jun 23 05:37:51 PM PDT 24 6740627551 ps
T355 /workspace/coverage/default/7.rom_ctrl_smoke.4094124720 Jun 23 05:37:22 PM PDT 24 Jun 23 05:38:19 PM PDT 24 11688297468 ps
T356 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2647723234 Jun 23 05:37:36 PM PDT 24 Jun 23 05:37:58 PM PDT 24 6361432186 ps
T357 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2974807781 Jun 23 05:38:53 PM PDT 24 Jun 23 05:39:03 PM PDT 24 242721461 ps
T358 /workspace/coverage/default/18.rom_ctrl_smoke.550879511 Jun 23 05:37:38 PM PDT 24 Jun 23 05:38:53 PM PDT 24 76993352673 ps
T359 /workspace/coverage/default/18.rom_ctrl_stress_all.4242738930 Jun 23 05:37:39 PM PDT 24 Jun 23 05:38:55 PM PDT 24 10366375561 ps
T360 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2738329165 Jun 23 05:37:53 PM PDT 24 Jun 23 05:41:00 PM PDT 24 3131193517 ps
T361 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1383393658 Jun 23 05:38:20 PM PDT 24 Jun 23 05:39:14 PM PDT 24 8465490913 ps
T61 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2752714273 Jun 23 04:44:56 PM PDT 24 Jun 23 04:45:05 PM PDT 24 332197774 ps
T62 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4076741672 Jun 23 04:44:32 PM PDT 24 Jun 23 04:45:06 PM PDT 24 4237916291 ps
T57 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.991359083 Jun 23 04:45:10 PM PDT 24 Jun 23 04:46:55 PM PDT 24 6729960239 ps
T66 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4287214677 Jun 23 04:44:39 PM PDT 24 Jun 23 04:45:19 PM PDT 24 6258604175 ps
T58 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2437915508 Jun 23 04:45:02 PM PDT 24 Jun 23 04:45:35 PM PDT 24 3856191712 ps
T64 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.506572363 Jun 23 04:44:47 PM PDT 24 Jun 23 04:45:07 PM PDT 24 5458171404 ps
T362 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4112972962 Jun 23 04:44:37 PM PDT 24 Jun 23 04:45:12 PM PDT 24 3958063498 ps
T59 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.990866027 Jun 23 04:45:03 PM PDT 24 Jun 23 04:47:44 PM PDT 24 2494528872 ps
T67 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.322185860 Jun 23 04:44:44 PM PDT 24 Jun 23 04:47:01 PM PDT 24 17110397770 ps
T363 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3598590576 Jun 23 04:44:20 PM PDT 24 Jun 23 04:44:32 PM PDT 24 868511231 ps
T364 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.37357739 Jun 23 04:44:46 PM PDT 24 Jun 23 04:45:11 PM PDT 24 8189178994 ps
T110 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3354037156 Jun 23 04:44:39 PM PDT 24 Jun 23 04:44:50 PM PDT 24 3650509346 ps
T111 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2860495959 Jun 23 04:44:28 PM PDT 24 Jun 23 04:44:40 PM PDT 24 728556240 ps
T365 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3460778706 Jun 23 04:44:36 PM PDT 24 Jun 23 04:44:45 PM PDT 24 174391352 ps
T366 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2807651269 Jun 23 04:44:52 PM PDT 24 Jun 23 04:45:14 PM PDT 24 2298460413 ps
T367 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3198813016 Jun 23 04:44:42 PM PDT 24 Jun 23 04:44:53 PM PDT 24 176153689 ps
T112 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4038299577 Jun 23 04:44:26 PM PDT 24 Jun 23 04:44:34 PM PDT 24 1832394468 ps
T368 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1595580478 Jun 23 04:44:39 PM PDT 24 Jun 23 04:45:11 PM PDT 24 8204945087 ps
T60 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4079575542 Jun 23 04:44:47 PM PDT 24 Jun 23 04:47:20 PM PDT 24 1161213611 ps
T116 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.172182987 Jun 23 04:44:59 PM PDT 24 Jun 23 04:46:41 PM PDT 24 3119792047 ps
T369 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.196926601 Jun 23 04:44:47 PM PDT 24 Jun 23 04:45:15 PM PDT 24 2659816086 ps
T68 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4232990524 Jun 23 04:44:58 PM PDT 24 Jun 23 04:45:18 PM PDT 24 2741063063 ps
T370 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3479951494 Jun 23 04:44:34 PM PDT 24 Jun 23 04:45:05 PM PDT 24 13188073734 ps
T120 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1089501578 Jun 23 04:44:32 PM PDT 24 Jun 23 04:45:52 PM PDT 24 258226848 ps
T371 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2372298856 Jun 23 04:44:39 PM PDT 24 Jun 23 04:45:11 PM PDT 24 4022960594 ps
T372 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2107811777 Jun 23 04:44:28 PM PDT 24 Jun 23 04:44:37 PM PDT 24 179355178 ps
T373 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4131146760 Jun 23 04:44:49 PM PDT 24 Jun 23 04:45:23 PM PDT 24 12881372520 ps
T69 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3603051103 Jun 23 04:44:39 PM PDT 24 Jun 23 04:45:07 PM PDT 24 3501117983 ps
T70 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2133293519 Jun 23 04:44:37 PM PDT 24 Jun 23 04:44:59 PM PDT 24 9259550175 ps
T71 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3382312867 Jun 23 04:44:26 PM PDT 24 Jun 23 04:44:52 PM PDT 24 3021208380 ps
T374 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1536329670 Jun 23 04:44:29 PM PDT 24 Jun 23 04:46:33 PM PDT 24 11096096326 ps
T375 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2476115309 Jun 23 04:44:36 PM PDT 24 Jun 23 04:44:59 PM PDT 24 7155081867 ps
T376 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3338846819 Jun 23 04:44:35 PM PDT 24 Jun 23 04:44:46 PM PDT 24 348649621 ps
T377 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4123878717 Jun 23 04:44:30 PM PDT 24 Jun 23 04:44:38 PM PDT 24 661696509 ps
T121 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1917136435 Jun 23 04:44:45 PM PDT 24 Jun 23 04:47:35 PM PDT 24 13670099431 ps
T378 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.114106783 Jun 23 04:44:44 PM PDT 24 Jun 23 04:45:11 PM PDT 24 3214476554 ps
T72 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4074053486 Jun 23 04:44:56 PM PDT 24 Jun 23 04:45:24 PM PDT 24 3681627549 ps
T122 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2571806147 Jun 23 04:44:48 PM PDT 24 Jun 23 04:46:32 PM PDT 24 4467135629 ps
T103 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2511751832 Jun 23 04:44:47 PM PDT 24 Jun 23 04:44:56 PM PDT 24 460271923 ps
T379 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2284272108 Jun 23 04:44:35 PM PDT 24 Jun 23 04:45:05 PM PDT 24 15071003911 ps
T380 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4146550452 Jun 23 04:45:01 PM PDT 24 Jun 23 04:46:22 PM PDT 24 848227053 ps
T381 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.580413728 Jun 23 04:45:07 PM PDT 24 Jun 23 04:45:35 PM PDT 24 10254253931 ps
T104 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1373397564 Jun 23 04:44:40 PM PDT 24 Jun 23 04:45:10 PM PDT 24 3199489494 ps
T105 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2541931858 Jun 23 04:44:34 PM PDT 24 Jun 23 04:45:10 PM PDT 24 31441212497 ps
T106 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.65928699 Jun 23 04:44:28 PM PDT 24 Jun 23 04:44:56 PM PDT 24 16428488132 ps
T382 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2872109158 Jun 23 04:44:39 PM PDT 24 Jun 23 04:45:05 PM PDT 24 5965038968 ps
T383 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3056082823 Jun 23 04:44:31 PM PDT 24 Jun 23 04:45:00 PM PDT 24 12524253710 ps
T73 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2301234312 Jun 23 04:44:42 PM PDT 24 Jun 23 04:45:02 PM PDT 24 2051781977 ps
T384 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.91872007 Jun 23 04:44:32 PM PDT 24 Jun 23 04:44:45 PM PDT 24 1686182966 ps
T74 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1078962393 Jun 23 04:44:46 PM PDT 24 Jun 23 04:44:55 PM PDT 24 172897096 ps
T385 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.314681807 Jun 23 04:44:28 PM PDT 24 Jun 23 04:44:58 PM PDT 24 5869263680 ps
T107 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.252948667 Jun 23 04:44:35 PM PDT 24 Jun 23 04:44:44 PM PDT 24 332033615 ps
T83 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4257677446 Jun 23 04:44:50 PM PDT 24 Jun 23 04:45:58 PM PDT 24 9236796858 ps
T386 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3032492631 Jun 23 04:44:37 PM PDT 24 Jun 23 04:45:09 PM PDT 24 4598739991 ps
T387 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3709787507 Jun 23 04:44:51 PM PDT 24 Jun 23 04:46:13 PM PDT 24 481802397 ps
T115 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1622746682 Jun 23 04:44:36 PM PDT 24 Jun 23 04:46:46 PM PDT 24 35803972318 ps
T388 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2163822664 Jun 23 04:44:53 PM PDT 24 Jun 23 04:45:15 PM PDT 24 2382490138 ps
T108 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4222642710 Jun 23 04:44:44 PM PDT 24 Jun 23 04:45:17 PM PDT 24 4511905798 ps
T125 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2326276050 Jun 23 04:45:07 PM PDT 24 Jun 23 04:48:00 PM PDT 24 7761750191 ps
T109 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2815071590 Jun 23 04:44:50 PM PDT 24 Jun 23 04:44:59 PM PDT 24 345899999 ps
T389 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1110192281 Jun 23 04:44:46 PM PDT 24 Jun 23 04:44:54 PM PDT 24 338506704 ps
T84 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2253498079 Jun 23 04:44:27 PM PDT 24 Jun 23 04:45:23 PM PDT 24 1035913289 ps
T390 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1756307113 Jun 23 04:44:40 PM PDT 24 Jun 23 04:46:13 PM PDT 24 6408960682 ps
T391 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.143712141 Jun 23 04:44:35 PM PDT 24 Jun 23 04:45:44 PM PDT 24 21006856343 ps
T128 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1552761766 Jun 23 04:44:49 PM PDT 24 Jun 23 04:46:26 PM PDT 24 5489762862 ps
T392 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.643989348 Jun 23 04:44:35 PM PDT 24 Jun 23 04:44:55 PM PDT 24 3774888128 ps
T393 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1316128531 Jun 23 04:44:49 PM PDT 24 Jun 23 04:45:12 PM PDT 24 1717760818 ps
T394 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.4159611748 Jun 23 04:44:33 PM PDT 24 Jun 23 04:45:11 PM PDT 24 2999052064 ps
T395 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2992469689 Jun 23 04:44:41 PM PDT 24 Jun 23 04:44:49 PM PDT 24 174677790 ps
T396 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2610822068 Jun 23 04:44:27 PM PDT 24 Jun 23 04:44:55 PM PDT 24 2886390732 ps
T397 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4268925301 Jun 23 04:44:41 PM PDT 24 Jun 23 04:44:58 PM PDT 24 3514934661 ps
T398 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2286791831 Jun 23 04:44:39 PM PDT 24 Jun 23 04:44:51 PM PDT 24 861332303 ps
T399 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3253751436 Jun 23 04:44:29 PM PDT 24 Jun 23 04:45:02 PM PDT 24 3929387198 ps
T400 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1584881262 Jun 23 04:44:36 PM PDT 24 Jun 23 04:45:06 PM PDT 24 16803196664 ps
T401 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2794625787 Jun 23 04:45:00 PM PDT 24 Jun 23 04:45:36 PM PDT 24 8634536496 ps
T117 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1173385139 Jun 23 04:44:29 PM PDT 24 Jun 23 04:46:03 PM PDT 24 2309193687 ps
T402 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3346973884 Jun 23 04:44:46 PM PDT 24 Jun 23 04:45:18 PM PDT 24 57331954170 ps
T124 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.8362487 Jun 23 04:44:24 PM PDT 24 Jun 23 04:47:01 PM PDT 24 482548692 ps
T403 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1779389451 Jun 23 04:44:54 PM PDT 24 Jun 23 04:45:50 PM PDT 24 9321930472 ps
T85 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.224368318 Jun 23 04:44:45 PM PDT 24 Jun 23 04:45:12 PM PDT 24 3306270469 ps
T404 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3554207134 Jun 23 04:44:40 PM PDT 24 Jun 23 04:44:57 PM PDT 24 2835248949 ps
T405 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.167069998 Jun 23 04:44:46 PM PDT 24 Jun 23 04:46:43 PM PDT 24 55116582451 ps
T406 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3940949826 Jun 23 04:44:31 PM PDT 24 Jun 23 04:44:56 PM PDT 24 2648569635 ps
T407 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2430353028 Jun 23 04:44:42 PM PDT 24 Jun 23 04:45:15 PM PDT 24 3361900849 ps
T408 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3420228547 Jun 23 04:44:40 PM PDT 24 Jun 23 04:45:05 PM PDT 24 2940538583 ps
T409 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4043297702 Jun 23 04:44:53 PM PDT 24 Jun 23 04:45:02 PM PDT 24 819385973 ps
T410 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3329139284 Jun 23 04:44:43 PM PDT 24 Jun 23 04:45:04 PM PDT 24 5780583897 ps
T411 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2900950389 Jun 23 04:44:51 PM PDT 24 Jun 23 04:45:29 PM PDT 24 2851208978 ps
T412 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3773469258 Jun 23 04:44:34 PM PDT 24 Jun 23 04:44:48 PM PDT 24 319039120 ps
T413 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2091594956 Jun 23 04:44:51 PM PDT 24 Jun 23 04:45:10 PM PDT 24 7797916090 ps
T414 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1034100240 Jun 23 04:44:51 PM PDT 24 Jun 23 04:47:32 PM PDT 24 80468835425 ps
T86 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2172020582 Jun 23 04:44:42 PM PDT 24 Jun 23 04:45:08 PM PDT 24 3276204140 ps
T87 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2222092300 Jun 23 04:44:48 PM PDT 24 Jun 23 04:46:22 PM PDT 24 40002781876 ps
T415 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.278694959 Jun 23 04:44:33 PM PDT 24 Jun 23 04:45:02 PM PDT 24 4184858224 ps
T416 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.779177080 Jun 23 04:44:49 PM PDT 24 Jun 23 04:46:28 PM PDT 24 13984966824 ps
T417 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1749662200 Jun 23 04:44:25 PM PDT 24 Jun 23 04:44:34 PM PDT 24 1029919631 ps
T418 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2685649162 Jun 23 04:44:30 PM PDT 24 Jun 23 04:44:54 PM PDT 24 2838557929 ps
T419 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1857883691 Jun 23 04:44:41 PM PDT 24 Jun 23 04:44:55 PM PDT 24 1253938443 ps
T420 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.788425999 Jun 23 04:44:43 PM PDT 24 Jun 23 04:45:14 PM PDT 24 22156783983 ps
T421 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4156675705 Jun 23 04:44:43 PM PDT 24 Jun 23 04:45:11 PM PDT 24 3426969349 ps
T422 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4196503199 Jun 23 04:44:49 PM PDT 24 Jun 23 04:45:19 PM PDT 24 3424776973 ps
T123 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.178009986 Jun 23 04:44:27 PM PDT 24 Jun 23 04:47:03 PM PDT 24 465060984 ps
T423 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2051629441 Jun 23 04:44:51 PM PDT 24 Jun 23 04:45:14 PM PDT 24 2752015472 ps
T424 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.217963648 Jun 23 04:44:58 PM PDT 24 Jun 23 04:45:21 PM PDT 24 5165317925 ps
T425 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1287227917 Jun 23 04:44:28 PM PDT 24 Jun 23 04:44:44 PM PDT 24 215583433 ps
T426 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3115624661 Jun 23 04:44:34 PM PDT 24 Jun 23 04:45:06 PM PDT 24 8364396965 ps
T427 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3681432261 Jun 23 04:44:56 PM PDT 24 Jun 23 04:45:29 PM PDT 24 4112573229 ps
T88 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2993112892 Jun 23 04:44:38 PM PDT 24 Jun 23 04:46:25 PM PDT 24 34415220445 ps
T118 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.997140492 Jun 23 04:44:42 PM PDT 24 Jun 23 04:47:18 PM PDT 24 1172724482 ps
T89 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1141662551 Jun 23 04:44:37 PM PDT 24 Jun 23 04:44:52 PM PDT 24 6168203137 ps
T428 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4175263741 Jun 23 04:45:02 PM PDT 24 Jun 23 04:45:36 PM PDT 24 70348925304 ps
T126 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2352839549 Jun 23 04:44:48 PM PDT 24 Jun 23 04:46:09 PM PDT 24 452265053 ps
T429 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3720029763 Jun 23 04:44:36 PM PDT 24 Jun 23 04:44:51 PM PDT 24 194503351 ps
T430 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1426801909 Jun 23 04:44:29 PM PDT 24 Jun 23 04:44:41 PM PDT 24 590996218 ps
T127 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.705849223 Jun 23 04:44:36 PM PDT 24 Jun 23 04:45:57 PM PDT 24 757755536 ps
T431 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2187839560 Jun 23 04:44:57 PM PDT 24 Jun 23 04:45:26 PM PDT 24 53337175172 ps
T432 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.955153076 Jun 23 04:44:43 PM PDT 24 Jun 23 04:45:18 PM PDT 24 19721049684 ps
T433 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.689576858 Jun 23 04:44:37 PM PDT 24 Jun 23 04:45:08 PM PDT 24 2908932231 ps
T434 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1338798433 Jun 23 04:44:46 PM PDT 24 Jun 23 04:45:20 PM PDT 24 3919257340 ps
T435 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.466665865 Jun 23 04:44:54 PM PDT 24 Jun 23 04:46:03 PM PDT 24 10273845875 ps
T436 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3755712640 Jun 23 04:44:37 PM PDT 24 Jun 23 04:44:57 PM PDT 24 4899149233 ps
T437 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1856617039 Jun 23 04:44:43 PM PDT 24 Jun 23 04:44:52 PM PDT 24 683566983 ps
T438 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4084111377 Jun 23 04:44:32 PM PDT 24 Jun 23 04:44:55 PM PDT 24 4924329877 ps
T439 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3459407130 Jun 23 04:44:47 PM PDT 24 Jun 23 04:45:14 PM PDT 24 6450144777 ps
T440 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1049096274 Jun 23 04:44:28 PM PDT 24 Jun 23 04:45:01 PM PDT 24 47468607415 ps
T441 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2107218694 Jun 23 04:44:49 PM PDT 24 Jun 23 04:45:22 PM PDT 24 24517300723 ps
T442 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1691311472 Jun 23 04:44:58 PM PDT 24 Jun 23 04:45:25 PM PDT 24 11779932936 ps
T443 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4094062736 Jun 23 04:44:58 PM PDT 24 Jun 23 04:45:27 PM PDT 24 3562332153 ps
T444 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2931300920 Jun 23 04:45:07 PM PDT 24 Jun 23 04:45:20 PM PDT 24 423779626 ps
T445 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4157983519 Jun 23 04:44:55 PM PDT 24 Jun 23 04:46:32 PM PDT 24 13229173714 ps
T446 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2471899207 Jun 23 04:44:44 PM PDT 24 Jun 23 04:45:08 PM PDT 24 3855409596 ps
T447 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1288888854 Jun 23 04:44:35 PM PDT 24 Jun 23 04:47:10 PM PDT 24 36965724484 ps
T90 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.141888046 Jun 23 04:44:46 PM PDT 24 Jun 23 04:46:47 PM PDT 24 33513885178 ps
T448 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3472692372 Jun 23 04:44:30 PM PDT 24 Jun 23 04:44:58 PM PDT 24 3363475969 ps
T449 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3600315123 Jun 23 04:44:54 PM PDT 24 Jun 23 04:45:23 PM PDT 24 2622091466 ps
T450 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3339323410 Jun 23 04:45:02 PM PDT 24 Jun 23 04:45:29 PM PDT 24 2637011547 ps
T451 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1889541417 Jun 23 04:44:23 PM PDT 24 Jun 23 04:44:32 PM PDT 24 174187591 ps
T119 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2921231269 Jun 23 04:44:27 PM PDT 24 Jun 23 04:47:17 PM PDT 24 61215316837 ps
T452 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2730217234 Jun 23 04:44:49 PM PDT 24 Jun 23 04:44:57 PM PDT 24 689350600 ps
T453 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.806036434 Jun 23 04:44:32 PM PDT 24 Jun 23 04:44:47 PM PDT 24 989310484 ps
T454 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4018079214 Jun 23 04:44:52 PM PDT 24 Jun 23 04:45:01 PM PDT 24 636747119 ps
T91 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.80090813 Jun 23 04:44:29 PM PDT 24 Jun 23 04:45:02 PM PDT 24 8702880787 ps
T92 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3487761806 Jun 23 04:44:51 PM PDT 24 Jun 23 04:46:53 PM PDT 24 14592429713 ps
T455 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.814747670 Jun 23 04:44:15 PM PDT 24 Jun 23 04:44:38 PM PDT 24 1968170746 ps

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.4077665917
Short name T4
Test name
Test status
Simulation time 68150762550 ps
CPU time 1333.89 seconds
Started Jun 23 05:38:30 PM PDT 24
Finished Jun 23 06:00:44 PM PDT 24
Peak memory 237388 kb
Host smart-7848fcd4-bef9-4558-b336-d662ddd255d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077665917 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.4077665917
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.4006796091
Short name T34
Test name
Test status
Simulation time 56686627687 ps
CPU time 558.9 seconds
Started Jun 23 05:38:35 PM PDT 24
Finished Jun 23 05:47:55 PM PDT 24
Peak memory 230816 kb
Host smart-907b0974-e863-45a0-bb2b-6893fe2de770
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006796091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.4006796091
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3813758205
Short name T1
Test name
Test status
Simulation time 4194986087 ps
CPU time 185.19 seconds
Started Jun 23 05:38:20 PM PDT 24
Finished Jun 23 05:41:26 PM PDT 24
Peak memory 235184 kb
Host smart-76a98c70-0392-400c-91ea-cee7aaa2a61f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813758205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3813758205
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.990866027
Short name T59
Test name
Test status
Simulation time 2494528872 ps
CPU time 159.85 seconds
Started Jun 23 04:45:03 PM PDT 24
Finished Jun 23 04:47:44 PM PDT 24
Peak memory 213424 kb
Host smart-73fc242c-e94d-4720-ae91-1beb336fd7c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990866027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.990866027
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2208735204
Short name T50
Test name
Test status
Simulation time 29823129794 ps
CPU time 196.4 seconds
Started Jun 23 05:37:52 PM PDT 24
Finished Jun 23 05:41:09 PM PDT 24
Peak memory 240700 kb
Host smart-6c7a7e7a-891e-4d79-a6dd-331977300656
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208735204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2208735204
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1095466795
Short name T173
Test name
Test status
Simulation time 2842979058 ps
CPU time 187.23 seconds
Started Jun 23 05:37:40 PM PDT 24
Finished Jun 23 05:40:48 PM PDT 24
Peak memory 219600 kb
Host smart-e3e408e3-63a1-4f35-8ebf-94d962d72a65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095466795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1095466795
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.322185860
Short name T67
Test name
Test status
Simulation time 17110397770 ps
CPU time 131.93 seconds
Started Jun 23 04:44:44 PM PDT 24
Finished Jun 23 04:47:01 PM PDT 24
Peak memory 215872 kb
Host smart-38137b24-1d33-4d4d-88b8-35c598ba5a7e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322185860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.322185860
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2169009644
Short name T24
Test name
Test status
Simulation time 328437330 ps
CPU time 227.53 seconds
Started Jun 23 05:37:17 PM PDT 24
Finished Jun 23 05:41:05 PM PDT 24
Peak memory 238008 kb
Host smart-fdcb8d50-1ba6-4c84-bfd6-079cc42febed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169009644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2169009644
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.997140492
Short name T118
Test name
Test status
Simulation time 1172724482 ps
CPU time 154.79 seconds
Started Jun 23 04:44:42 PM PDT 24
Finished Jun 23 04:47:18 PM PDT 24
Peak memory 214640 kb
Host smart-058ac722-a59d-4dec-b863-0444bc47f211
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997140492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.997140492
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3917409890
Short name T63
Test name
Test status
Simulation time 3068079109 ps
CPU time 25.8 seconds
Started Jun 23 05:37:35 PM PDT 24
Finished Jun 23 05:38:01 PM PDT 24
Peak memory 217160 kb
Host smart-1f3d8198-3891-4438-8d4a-927f927e56b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917409890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3917409890
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2384028950
Short name T65
Test name
Test status
Simulation time 7816443596 ps
CPU time 60.35 seconds
Started Jun 23 05:37:29 PM PDT 24
Finished Jun 23 05:38:29 PM PDT 24
Peak memory 219304 kb
Host smart-39ee19d8-b3ea-4d7c-b326-37f1c7085800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384028950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2384028950
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.716883113
Short name T47
Test name
Test status
Simulation time 2357382211 ps
CPU time 19.29 seconds
Started Jun 23 05:37:31 PM PDT 24
Finished Jun 23 05:37:50 PM PDT 24
Peak memory 219304 kb
Host smart-cc03f24b-3c4b-4ba9-b8ee-3140f7d48760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716883113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.716883113
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.8362487
Short name T124
Test name
Test status
Simulation time 482548692 ps
CPU time 156.25 seconds
Started Jun 23 04:44:24 PM PDT 24
Finished Jun 23 04:47:01 PM PDT 24
Peak memory 213868 kb
Host smart-4efad0f2-1d3d-403c-b759-18038a020ba8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8362487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_
err.8362487
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2111829420
Short name T43
Test name
Test status
Simulation time 3331898267 ps
CPU time 28.41 seconds
Started Jun 23 05:37:18 PM PDT 24
Finished Jun 23 05:37:47 PM PDT 24
Peak memory 216316 kb
Host smart-520149eb-d13d-40a0-b109-36a667d90a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111829420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2111829420
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.178009986
Short name T123
Test name
Test status
Simulation time 465060984 ps
CPU time 156.5 seconds
Started Jun 23 04:44:27 PM PDT 24
Finished Jun 23 04:47:03 PM PDT 24
Peak memory 214648 kb
Host smart-86ed45a4-3d1a-4347-bff0-22b469fe1cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178009986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.178009986
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4257677446
Short name T83
Test name
Test status
Simulation time 9236796858 ps
CPU time 67.61 seconds
Started Jun 23 04:44:50 PM PDT 24
Finished Jun 23 04:45:58 PM PDT 24
Peak memory 214540 kb
Host smart-64b08404-5ba8-4fd3-ab52-ca5dd9429f5e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257677446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.4257677446
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3382312867
Short name T71
Test name
Test status
Simulation time 3021208380 ps
CPU time 25.63 seconds
Started Jun 23 04:44:26 PM PDT 24
Finished Jun 23 04:44:52 PM PDT 24
Peak memory 212288 kb
Host smart-bf31d72e-39c4-4a4b-84fa-282afe74f26a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382312867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3382312867
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3894891980
Short name T93
Test name
Test status
Simulation time 24154585214 ps
CPU time 30.58 seconds
Started Jun 23 05:37:55 PM PDT 24
Finished Jun 23 05:38:26 PM PDT 24
Peak memory 211924 kb
Host smart-b8968a79-8a99-4cd7-9396-fe4ab6de3f10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3894891980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3894891980
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3554207134
Short name T404
Test name
Test status
Simulation time 2835248949 ps
CPU time 17.21 seconds
Started Jun 23 04:44:40 PM PDT 24
Finished Jun 23 04:44:57 PM PDT 24
Peak memory 212412 kb
Host smart-c33f79ea-1838-4883-9e7a-ffa956c2cd8a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554207134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3554207134
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.91872007
Short name T384
Test name
Test status
Simulation time 1686182966 ps
CPU time 12.67 seconds
Started Jun 23 04:44:32 PM PDT 24
Finished Jun 23 04:44:45 PM PDT 24
Peak memory 211484 kb
Host smart-46d9313f-a6b5-4f2c-b053-65cdb03481f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91872007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_ba
sh.91872007
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2685649162
Short name T418
Test name
Test status
Simulation time 2838557929 ps
CPU time 24.15 seconds
Started Jun 23 04:44:30 PM PDT 24
Finished Jun 23 04:44:54 PM PDT 24
Peak memory 212380 kb
Host smart-61388593-3788-4379-9972-a91516259cad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685649162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2685649162
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3253751436
Short name T399
Test name
Test status
Simulation time 3929387198 ps
CPU time 31.64 seconds
Started Jun 23 04:44:29 PM PDT 24
Finished Jun 23 04:45:02 PM PDT 24
Peak memory 218024 kb
Host smart-a6e76201-5fae-4df5-aaff-b33b5b63ae9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253751436 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3253751436
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1110192281
Short name T389
Test name
Test status
Simulation time 338506704 ps
CPU time 8.08 seconds
Started Jun 23 04:44:46 PM PDT 24
Finished Jun 23 04:44:54 PM PDT 24
Peak memory 211324 kb
Host smart-a1e3c068-74e4-4d0d-9bfc-fee39668e811
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110192281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1110192281
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1595580478
Short name T368
Test name
Test status
Simulation time 8204945087 ps
CPU time 31.27 seconds
Started Jun 23 04:44:39 PM PDT 24
Finished Jun 23 04:45:11 PM PDT 24
Peak memory 211420 kb
Host smart-22113dc0-86df-43fd-bb7f-be17c3d87b6a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595580478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1595580478
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.806036434
Short name T453
Test name
Test status
Simulation time 989310484 ps
CPU time 14.78 seconds
Started Jun 23 04:44:32 PM PDT 24
Finished Jun 23 04:44:47 PM PDT 24
Peak memory 211124 kb
Host smart-0ce57c95-41a4-43d3-a413-4ad75bddd628
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806036434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
806036434
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1536329670
Short name T374
Test name
Test status
Simulation time 11096096326 ps
CPU time 124.03 seconds
Started Jun 23 04:44:29 PM PDT 24
Finished Jun 23 04:46:33 PM PDT 24
Peak memory 215944 kb
Host smart-a0eeb74c-3ea7-4e4d-bcf3-4bfd25dc4665
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536329670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1536329670
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4018079214
Short name T454
Test name
Test status
Simulation time 636747119 ps
CPU time 8.31 seconds
Started Jun 23 04:44:52 PM PDT 24
Finished Jun 23 04:45:01 PM PDT 24
Peak memory 211724 kb
Host smart-bbb84884-9721-4121-820e-dc0f0a221d3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018079214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.4018079214
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.814747670
Short name T455
Test name
Test status
Simulation time 1968170746 ps
CPU time 23.36 seconds
Started Jun 23 04:44:15 PM PDT 24
Finished Jun 23 04:44:38 PM PDT 24
Peak memory 218592 kb
Host smart-f1bc2283-45e5-4927-8523-6fbdf352ce4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814747670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.814747670
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4038299577
Short name T112
Test name
Test status
Simulation time 1832394468 ps
CPU time 8.06 seconds
Started Jun 23 04:44:26 PM PDT 24
Finished Jun 23 04:44:34 PM PDT 24
Peak memory 211264 kb
Host smart-47853c3f-f744-4095-b819-4426c3fd9fc1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038299577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.4038299577
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2872109158
Short name T382
Test name
Test status
Simulation time 5965038968 ps
CPU time 25.16 seconds
Started Jun 23 04:44:39 PM PDT 24
Finished Jun 23 04:45:05 PM PDT 24
Peak memory 212220 kb
Host smart-a5a767ae-c7ba-4f18-8afd-f6354c432d26
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872109158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2872109158
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4268925301
Short name T397
Test name
Test status
Simulation time 3514934661 ps
CPU time 16.17 seconds
Started Jun 23 04:44:41 PM PDT 24
Finished Jun 23 04:44:58 PM PDT 24
Peak memory 211268 kb
Host smart-f02cba75-947d-43ac-8dcf-44cc4babcae6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268925301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.4268925301
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1749662200
Short name T417
Test name
Test status
Simulation time 1029919631 ps
CPU time 8.88 seconds
Started Jun 23 04:44:25 PM PDT 24
Finished Jun 23 04:44:34 PM PDT 24
Peak memory 215952 kb
Host smart-9b6f5ee6-3bd7-4545-9155-25d7cf997c19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749662200 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1749662200
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2133293519
Short name T70
Test name
Test status
Simulation time 9259550175 ps
CPU time 21.89 seconds
Started Jun 23 04:44:37 PM PDT 24
Finished Jun 23 04:44:59 PM PDT 24
Peak memory 212688 kb
Host smart-e7a9d4a0-7a31-4869-a720-28a034b72009
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133293519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2133293519
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3346973884
Short name T402
Test name
Test status
Simulation time 57331954170 ps
CPU time 31.87 seconds
Started Jun 23 04:44:46 PM PDT 24
Finished Jun 23 04:45:18 PM PDT 24
Peak memory 211456 kb
Host smart-39e46443-e58e-45f1-bab9-dcc2af7b2ac2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346973884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3346973884
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2476115309
Short name T375
Test name
Test status
Simulation time 7155081867 ps
CPU time 17.66 seconds
Started Jun 23 04:44:36 PM PDT 24
Finished Jun 23 04:44:59 PM PDT 24
Peak memory 211228 kb
Host smart-0578e323-ebaa-45ef-9fc9-a0a6f6eeef1b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476115309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2476115309
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2253498079
Short name T84
Test name
Test status
Simulation time 1035913289 ps
CPU time 55.58 seconds
Started Jun 23 04:44:27 PM PDT 24
Finished Jun 23 04:45:23 PM PDT 24
Peak memory 215120 kb
Host smart-433660b7-37e4-4d2f-8bc1-c1bfa99a68c7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253498079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2253498079
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3598590576
Short name T363
Test name
Test status
Simulation time 868511231 ps
CPU time 11.66 seconds
Started Jun 23 04:44:20 PM PDT 24
Finished Jun 23 04:44:32 PM PDT 24
Peak memory 217968 kb
Host smart-ad9dcb3e-7035-4cb5-9189-07bf4cd729c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598590576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3598590576
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1584881262
Short name T400
Test name
Test status
Simulation time 16803196664 ps
CPU time 29.75 seconds
Started Jun 23 04:44:36 PM PDT 24
Finished Jun 23 04:45:06 PM PDT 24
Peak memory 218320 kb
Host smart-96c39a40-b55f-4a8f-a765-f8a45f3f0ece
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584881262 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1584881262
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1141662551
Short name T89
Test name
Test status
Simulation time 6168203137 ps
CPU time 15.09 seconds
Started Jun 23 04:44:37 PM PDT 24
Finished Jun 23 04:44:52 PM PDT 24
Peak memory 212004 kb
Host smart-52b77d29-a275-4bfa-be49-c2edc6284463
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141662551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1141662551
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.779177080
Short name T416
Test name
Test status
Simulation time 13984966824 ps
CPU time 97.3 seconds
Started Jun 23 04:44:49 PM PDT 24
Finished Jun 23 04:46:28 PM PDT 24
Peak memory 219112 kb
Host smart-b22a0282-3112-4a32-a61f-1344e8b55493
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779177080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.779177080
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1078962393
Short name T74
Test name
Test status
Simulation time 172897096 ps
CPU time 8.27 seconds
Started Jun 23 04:44:46 PM PDT 24
Finished Jun 23 04:44:55 PM PDT 24
Peak memory 211612 kb
Host smart-e6f7d192-9c73-4c3d-985d-c4cd64810983
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078962393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1078962393
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1338798433
Short name T434
Test name
Test status
Simulation time 3919257340 ps
CPU time 33.21 seconds
Started Jun 23 04:44:46 PM PDT 24
Finished Jun 23 04:45:20 PM PDT 24
Peak memory 218820 kb
Host smart-44507e8e-3c1f-474d-b93a-841aaf2cb254
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338798433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1338798433
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1756307113
Short name T390
Test name
Test status
Simulation time 6408960682 ps
CPU time 92.69 seconds
Started Jun 23 04:44:40 PM PDT 24
Finished Jun 23 04:46:13 PM PDT 24
Peak memory 214256 kb
Host smart-5d3d26fc-53d2-443e-a157-6048cb7311d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756307113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1756307113
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2430353028
Short name T407
Test name
Test status
Simulation time 3361900849 ps
CPU time 27.33 seconds
Started Jun 23 04:44:42 PM PDT 24
Finished Jun 23 04:45:15 PM PDT 24
Peak memory 217692 kb
Host smart-2f00de0a-ccd3-4af0-b93d-4a3fe69a58b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430353028 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2430353028
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3354037156
Short name T110
Test name
Test status
Simulation time 3650509346 ps
CPU time 10.7 seconds
Started Jun 23 04:44:39 PM PDT 24
Finished Jun 23 04:44:50 PM PDT 24
Peak memory 211696 kb
Host smart-1c1ac267-4eae-4b16-8ff8-433de13250b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354037156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3354037156
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3459407130
Short name T439
Test name
Test status
Simulation time 6450144777 ps
CPU time 25.57 seconds
Started Jun 23 04:44:47 PM PDT 24
Finished Jun 23 04:45:14 PM PDT 24
Peak memory 213236 kb
Host smart-d1483ccc-a9af-4158-a160-8c4fae507931
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459407130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3459407130
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1426801909
Short name T430
Test name
Test status
Simulation time 590996218 ps
CPU time 11.87 seconds
Started Jun 23 04:44:29 PM PDT 24
Finished Jun 23 04:44:41 PM PDT 24
Peak memory 217948 kb
Host smart-4554cf7a-8f05-4616-8d6e-de299a5f22a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426801909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1426801909
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3940949826
Short name T406
Test name
Test status
Simulation time 2648569635 ps
CPU time 24.65 seconds
Started Jun 23 04:44:31 PM PDT 24
Finished Jun 23 04:44:56 PM PDT 24
Peak memory 219608 kb
Host smart-47cb8db4-0ee1-4d43-b3c0-3b15ac8634b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940949826 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3940949826
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2172020582
Short name T86
Test name
Test status
Simulation time 3276204140 ps
CPU time 26.29 seconds
Started Jun 23 04:44:42 PM PDT 24
Finished Jun 23 04:45:08 PM PDT 24
Peak memory 212404 kb
Host smart-d98be1f8-196b-4726-8025-7db163c897f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172020582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2172020582
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.4287214677
Short name T66
Test name
Test status
Simulation time 6258604175 ps
CPU time 39.05 seconds
Started Jun 23 04:44:39 PM PDT 24
Finished Jun 23 04:45:19 PM PDT 24
Peak memory 214072 kb
Host smart-10661ee7-4491-4de7-a6ef-6a5f0a35ccb7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287214677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.4287214677
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.955153076
Short name T432
Test name
Test status
Simulation time 19721049684 ps
CPU time 34.9 seconds
Started Jun 23 04:44:43 PM PDT 24
Finished Jun 23 04:45:18 PM PDT 24
Peak memory 213136 kb
Host smart-89272b58-24ab-4ff7-af52-c32274809ff8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955153076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.955153076
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3198813016
Short name T367
Test name
Test status
Simulation time 176153689 ps
CPU time 11.33 seconds
Started Jun 23 04:44:42 PM PDT 24
Finished Jun 23 04:44:53 PM PDT 24
Peak memory 219736 kb
Host smart-63ab8229-c530-40df-a7a7-059e2a240252
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198813016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3198813016
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.4079575542
Short name T60
Test name
Test status
Simulation time 1161213611 ps
CPU time 153.14 seconds
Started Jun 23 04:44:47 PM PDT 24
Finished Jun 23 04:47:20 PM PDT 24
Peak memory 214596 kb
Host smart-cccba7ae-7278-4392-9fea-678e19bbe2b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079575542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.4079575542
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2107811777
Short name T372
Test name
Test status
Simulation time 179355178 ps
CPU time 8.72 seconds
Started Jun 23 04:44:28 PM PDT 24
Finished Jun 23 04:44:37 PM PDT 24
Peak memory 217400 kb
Host smart-ae0a0fb9-f3b3-496b-9e02-819a686f0624
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107811777 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2107811777
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2301234312
Short name T73
Test name
Test status
Simulation time 2051781977 ps
CPU time 19.8 seconds
Started Jun 23 04:44:42 PM PDT 24
Finished Jun 23 04:45:02 PM PDT 24
Peak memory 211880 kb
Host smart-b0a30816-f718-4a66-a152-e8c9b0f1860c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301234312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2301234312
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.141888046
Short name T90
Test name
Test status
Simulation time 33513885178 ps
CPU time 120.55 seconds
Started Jun 23 04:44:46 PM PDT 24
Finished Jun 23 04:46:47 PM PDT 24
Peak memory 214540 kb
Host smart-f4166e3d-5ff7-4bd3-b906-7802d8b3d7b5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141888046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.141888046
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1889541417
Short name T451
Test name
Test status
Simulation time 174187591 ps
CPU time 8.31 seconds
Started Jun 23 04:44:23 PM PDT 24
Finished Jun 23 04:44:32 PM PDT 24
Peak memory 211784 kb
Host smart-02d909a7-d219-48b3-9273-eb972f846419
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889541417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1889541417
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.314681807
Short name T385
Test name
Test status
Simulation time 5869263680 ps
CPU time 29.25 seconds
Started Jun 23 04:44:28 PM PDT 24
Finished Jun 23 04:44:58 PM PDT 24
Peak memory 217808 kb
Host smart-591b9be7-01a5-404b-a4e8-a133a1b9bcbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314681807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.314681807
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.705849223
Short name T127
Test name
Test status
Simulation time 757755536 ps
CPU time 81.3 seconds
Started Jun 23 04:44:36 PM PDT 24
Finished Jun 23 04:45:57 PM PDT 24
Peak memory 212976 kb
Host smart-cac0c4c7-01d8-48f7-87f1-57cf47d6a433
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705849223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.705849223
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4156675705
Short name T421
Test name
Test status
Simulation time 3426969349 ps
CPU time 27.39 seconds
Started Jun 23 04:44:43 PM PDT 24
Finished Jun 23 04:45:11 PM PDT 24
Peak memory 217064 kb
Host smart-10ea6e53-f452-40bd-bfac-6ddd0d8c686f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156675705 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4156675705
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.224368318
Short name T85
Test name
Test status
Simulation time 3306270469 ps
CPU time 27.17 seconds
Started Jun 23 04:44:45 PM PDT 24
Finished Jun 23 04:45:12 PM PDT 24
Peak memory 212400 kb
Host smart-653718a1-0521-4a98-b974-7a6008c06b96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224368318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.224368318
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.167069998
Short name T405
Test name
Test status
Simulation time 55116582451 ps
CPU time 116.98 seconds
Started Jun 23 04:44:46 PM PDT 24
Finished Jun 23 04:46:43 PM PDT 24
Peak memory 212296 kb
Host smart-dec88b39-71a9-4bd4-91d9-4326005fbf9b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167069998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.167069998
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2931300920
Short name T444
Test name
Test status
Simulation time 423779626 ps
CPU time 11.71 seconds
Started Jun 23 04:45:07 PM PDT 24
Finished Jun 23 04:45:20 PM PDT 24
Peak memory 213172 kb
Host smart-80f08757-bd0d-4825-b912-ab8267f9317e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931300920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2931300920
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.689576858
Short name T433
Test name
Test status
Simulation time 2908932231 ps
CPU time 29.98 seconds
Started Jun 23 04:44:37 PM PDT 24
Finished Jun 23 04:45:08 PM PDT 24
Peak memory 219568 kb
Host smart-04d39454-4dff-4ae7-88d9-586a7f359c18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689576858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.689576858
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2571806147
Short name T122
Test name
Test status
Simulation time 4467135629 ps
CPU time 104.12 seconds
Started Jun 23 04:44:48 PM PDT 24
Finished Jun 23 04:46:32 PM PDT 24
Peak memory 214360 kb
Host smart-a661ce2b-78e7-4d1f-8782-5131e1cfc372
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571806147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2571806147
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3720029763
Short name T429
Test name
Test status
Simulation time 194503351 ps
CPU time 9.48 seconds
Started Jun 23 04:44:36 PM PDT 24
Finished Jun 23 04:44:51 PM PDT 24
Peak memory 216500 kb
Host smart-62297bce-4e2c-4d1d-8a3d-b82f2d1d7baf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720029763 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3720029763
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2051629441
Short name T423
Test name
Test status
Simulation time 2752015472 ps
CPU time 22.11 seconds
Started Jun 23 04:44:51 PM PDT 24
Finished Jun 23 04:45:14 PM PDT 24
Peak memory 212624 kb
Host smart-f38ae5d4-0bc5-4ac2-b7ed-db1c9f52227a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051629441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2051629441
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2222092300
Short name T87
Test name
Test status
Simulation time 40002781876 ps
CPU time 93.68 seconds
Started Jun 23 04:44:48 PM PDT 24
Finished Jun 23 04:46:22 PM PDT 24
Peak memory 214756 kb
Host smart-1e5d09f0-8535-47c7-b31a-5768da243445
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222092300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2222092300
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4094062736
Short name T443
Test name
Test status
Simulation time 3562332153 ps
CPU time 28.85 seconds
Started Jun 23 04:44:58 PM PDT 24
Finished Jun 23 04:45:27 PM PDT 24
Peak memory 212516 kb
Host smart-6de046f8-0975-49ad-adac-38e81ca4dc9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094062736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.4094062736
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.506572363
Short name T64
Test name
Test status
Simulation time 5458171404 ps
CPU time 20.1 seconds
Started Jun 23 04:44:47 PM PDT 24
Finished Jun 23 04:45:07 PM PDT 24
Peak memory 219552 kb
Host smart-1e836a2f-e1f5-46b2-a52f-8323742f637f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506572363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.506572363
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1552761766
Short name T128
Test name
Test status
Simulation time 5489762862 ps
CPU time 96.67 seconds
Started Jun 23 04:44:49 PM PDT 24
Finished Jun 23 04:46:26 PM PDT 24
Peak memory 214244 kb
Host smart-d0f5dbb0-7cf9-4bf8-bbcf-a6f066833305
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552761766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1552761766
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.217963648
Short name T424
Test name
Test status
Simulation time 5165317925 ps
CPU time 22.74 seconds
Started Jun 23 04:44:58 PM PDT 24
Finished Jun 23 04:45:21 PM PDT 24
Peak memory 219584 kb
Host smart-b38f5378-4c04-4360-be30-5cb298a608ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217963648 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.217963648
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4123878717
Short name T377
Test name
Test status
Simulation time 661696509 ps
CPU time 8.13 seconds
Started Jun 23 04:44:30 PM PDT 24
Finished Jun 23 04:44:38 PM PDT 24
Peak memory 211168 kb
Host smart-a72126b4-ac56-43c4-b8e1-8589aa421eb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123878717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.4123878717
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.466665865
Short name T435
Test name
Test status
Simulation time 10273845875 ps
CPU time 68.49 seconds
Started Jun 23 04:44:54 PM PDT 24
Finished Jun 23 04:46:03 PM PDT 24
Peak memory 214288 kb
Host smart-c94314ac-b777-4e2b-87cc-e2bf3383d92f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466665865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.466665865
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4074053486
Short name T72
Test name
Test status
Simulation time 3681627549 ps
CPU time 27.65 seconds
Started Jun 23 04:44:56 PM PDT 24
Finished Jun 23 04:45:24 PM PDT 24
Peak memory 212788 kb
Host smart-0a3a512f-99c9-4b10-8625-a3a14ed9c313
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074053486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.4074053486
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2437915508
Short name T58
Test name
Test status
Simulation time 3856191712 ps
CPU time 31.76 seconds
Started Jun 23 04:45:02 PM PDT 24
Finished Jun 23 04:45:35 PM PDT 24
Peak memory 217548 kb
Host smart-5130b601-ba3f-44d0-8044-038d3728d707
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437915508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2437915508
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4157983519
Short name T445
Test name
Test status
Simulation time 13229173714 ps
CPU time 96.24 seconds
Started Jun 23 04:44:55 PM PDT 24
Finished Jun 23 04:46:32 PM PDT 24
Peak memory 214532 kb
Host smart-0c2e0c8d-3f6a-4e97-b6e1-ff5013b8e00a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157983519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.4157983519
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4196503199
Short name T422
Test name
Test status
Simulation time 3424776973 ps
CPU time 28.66 seconds
Started Jun 23 04:44:49 PM PDT 24
Finished Jun 23 04:45:19 PM PDT 24
Peak memory 218000 kb
Host smart-33e1a28c-1583-4013-8429-79d1bd2669ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196503199 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.4196503199
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2992469689
Short name T395
Test name
Test status
Simulation time 174677790 ps
CPU time 8.19 seconds
Started Jun 23 04:44:41 PM PDT 24
Finished Jun 23 04:44:49 PM PDT 24
Peak memory 211332 kb
Host smart-75c26b6d-bf1c-40ad-8ffe-776ea3768007
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992469689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2992469689
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2993112892
Short name T88
Test name
Test status
Simulation time 34415220445 ps
CPU time 106.59 seconds
Started Jun 23 04:44:38 PM PDT 24
Finished Jun 23 04:46:25 PM PDT 24
Peak memory 219636 kb
Host smart-5bb667df-254d-4a56-8185-25817d957aba
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993112892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2993112892
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2815071590
Short name T109
Test name
Test status
Simulation time 345899999 ps
CPU time 8.57 seconds
Started Jun 23 04:44:50 PM PDT 24
Finished Jun 23 04:44:59 PM PDT 24
Peak memory 211340 kb
Host smart-6318e1b6-5a32-4fdd-bb1a-45454ba82516
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815071590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2815071590
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1316128531
Short name T393
Test name
Test status
Simulation time 1717760818 ps
CPU time 20.96 seconds
Started Jun 23 04:44:49 PM PDT 24
Finished Jun 23 04:45:12 PM PDT 24
Peak memory 219432 kb
Host smart-9fb2f3c9-059e-458b-abe7-dd3180cb5902
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316128531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1316128531
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.172182987
Short name T116
Test name
Test status
Simulation time 3119792047 ps
CPU time 101.73 seconds
Started Jun 23 04:44:59 PM PDT 24
Finished Jun 23 04:46:41 PM PDT 24
Peak memory 214416 kb
Host smart-085483ea-6519-493a-b1a1-0c5e284a723d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172182987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.172182987
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4043297702
Short name T409
Test name
Test status
Simulation time 819385973 ps
CPU time 8.97 seconds
Started Jun 23 04:44:53 PM PDT 24
Finished Jun 23 04:45:02 PM PDT 24
Peak memory 217400 kb
Host smart-2e74fe0e-04bf-4e73-b6f4-46af0b669d5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043297702 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.4043297702
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.643989348
Short name T392
Test name
Test status
Simulation time 3774888128 ps
CPU time 14.51 seconds
Started Jun 23 04:44:35 PM PDT 24
Finished Jun 23 04:44:55 PM PDT 24
Peak memory 212468 kb
Host smart-7fa84bab-8b7d-468c-b64d-d6e6a96aeb42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643989348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.643989348
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2900950389
Short name T411
Test name
Test status
Simulation time 2851208978 ps
CPU time 37.63 seconds
Started Jun 23 04:44:51 PM PDT 24
Finished Jun 23 04:45:29 PM PDT 24
Peak memory 215376 kb
Host smart-54e9f904-99bb-4c54-95c4-c8568d044b40
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900950389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2900950389
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2794625787
Short name T401
Test name
Test status
Simulation time 8634536496 ps
CPU time 36.39 seconds
Started Jun 23 04:45:00 PM PDT 24
Finished Jun 23 04:45:36 PM PDT 24
Peak memory 213204 kb
Host smart-c553875e-e165-42a8-b177-195d461e4260
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794625787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2794625787
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4131146760
Short name T373
Test name
Test status
Simulation time 12881372520 ps
CPU time 33.75 seconds
Started Jun 23 04:44:49 PM PDT 24
Finished Jun 23 04:45:23 PM PDT 24
Peak memory 218068 kb
Host smart-eb4768c8-90fc-4e69-9b9a-9142a615ee48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131146760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.4131146760
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3709787507
Short name T387
Test name
Test status
Simulation time 481802397 ps
CPU time 81.4 seconds
Started Jun 23 04:44:51 PM PDT 24
Finished Jun 23 04:46:13 PM PDT 24
Peak memory 214024 kb
Host smart-ecdfdffb-4996-4dae-b04a-ccc866de1fd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709787507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3709787507
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1856617039
Short name T437
Test name
Test status
Simulation time 683566983 ps
CPU time 8.71 seconds
Started Jun 23 04:44:43 PM PDT 24
Finished Jun 23 04:44:52 PM PDT 24
Peak memory 215324 kb
Host smart-a7c29ea4-e92a-4ccf-b438-fe160c0d7817
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856617039 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1856617039
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2511751832
Short name T103
Test name
Test status
Simulation time 460271923 ps
CPU time 8.13 seconds
Started Jun 23 04:44:47 PM PDT 24
Finished Jun 23 04:44:56 PM PDT 24
Peak memory 211564 kb
Host smart-5a8b4cfc-8027-481f-90be-52fdf180396b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511751832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2511751832
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.278694959
Short name T415
Test name
Test status
Simulation time 4184858224 ps
CPU time 28.43 seconds
Started Jun 23 04:44:33 PM PDT 24
Finished Jun 23 04:45:02 PM PDT 24
Peak memory 212848 kb
Host smart-a946316a-9f5b-4aa2-a61b-f69bb4722eca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278694959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.278694959
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3479951494
Short name T370
Test name
Test status
Simulation time 13188073734 ps
CPU time 30.54 seconds
Started Jun 23 04:44:34 PM PDT 24
Finished Jun 23 04:45:05 PM PDT 24
Peak memory 219564 kb
Host smart-d19e108c-0f79-46d5-ba82-02d06452ae7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479951494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3479951494
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.991359083
Short name T57
Test name
Test status
Simulation time 6729960239 ps
CPU time 103.92 seconds
Started Jun 23 04:45:10 PM PDT 24
Finished Jun 23 04:46:55 PM PDT 24
Peak memory 214796 kb
Host smart-7314dccf-521c-4a01-af20-56350309189e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991359083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.991359083
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4076741672
Short name T62
Test name
Test status
Simulation time 4237916291 ps
CPU time 33.31 seconds
Started Jun 23 04:44:32 PM PDT 24
Finished Jun 23 04:45:06 PM PDT 24
Peak memory 210692 kb
Host smart-7d1ca42f-fcb2-407a-8fa6-ba5cbd7bd85e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076741672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.4076741672
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2752714273
Short name T61
Test name
Test status
Simulation time 332197774 ps
CPU time 8.26 seconds
Started Jun 23 04:44:56 PM PDT 24
Finished Jun 23 04:45:05 PM PDT 24
Peak memory 211292 kb
Host smart-bd459196-7cbc-4fd9-bc85-482d0d5cbebc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752714273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2752714273
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4232990524
Short name T68
Test name
Test status
Simulation time 2741063063 ps
CPU time 19.39 seconds
Started Jun 23 04:44:58 PM PDT 24
Finished Jun 23 04:45:18 PM PDT 24
Peak memory 212652 kb
Host smart-9818a6b1-e591-4a07-a6ca-92c93807f9d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232990524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.4232990524
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.114106783
Short name T378
Test name
Test status
Simulation time 3214476554 ps
CPU time 27.01 seconds
Started Jun 23 04:44:44 PM PDT 24
Finished Jun 23 04:45:11 PM PDT 24
Peak memory 217648 kb
Host smart-9903692d-1b36-46f9-8058-d6d92f38db7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114106783 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.114106783
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3603051103
Short name T69
Test name
Test status
Simulation time 3501117983 ps
CPU time 27.79 seconds
Started Jun 23 04:44:39 PM PDT 24
Finished Jun 23 04:45:07 PM PDT 24
Peak memory 211836 kb
Host smart-a91d3846-610b-42f2-af16-c550fc2bbc90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603051103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3603051103
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3472692372
Short name T448
Test name
Test status
Simulation time 3363475969 ps
CPU time 28.2 seconds
Started Jun 23 04:44:30 PM PDT 24
Finished Jun 23 04:44:58 PM PDT 24
Peak memory 211252 kb
Host smart-9030c43f-5be7-4d60-a83b-ddccd179425d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472692372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3472692372
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3773469258
Short name T412
Test name
Test status
Simulation time 319039120 ps
CPU time 8.3 seconds
Started Jun 23 04:44:34 PM PDT 24
Finished Jun 23 04:44:48 PM PDT 24
Peak memory 211128 kb
Host smart-6c72143a-d16f-4450-867b-932919abdcd9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773469258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3773469258
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3487761806
Short name T92
Test name
Test status
Simulation time 14592429713 ps
CPU time 121.64 seconds
Started Jun 23 04:44:51 PM PDT 24
Finished Jun 23 04:46:53 PM PDT 24
Peak memory 214928 kb
Host smart-89ac5ec5-db5d-4aad-8dba-0c9b4e4c94e5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487761806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3487761806
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2730217234
Short name T452
Test name
Test status
Simulation time 689350600 ps
CPU time 8.21 seconds
Started Jun 23 04:44:49 PM PDT 24
Finished Jun 23 04:44:57 PM PDT 24
Peak memory 211792 kb
Host smart-49582d0f-4a0b-4c00-81f6-a5153b4aba9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730217234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2730217234
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3056082823
Short name T383
Test name
Test status
Simulation time 12524253710 ps
CPU time 28.63 seconds
Started Jun 23 04:44:31 PM PDT 24
Finished Jun 23 04:45:00 PM PDT 24
Peak memory 217216 kb
Host smart-392d5623-5cd8-43e3-9adf-3b8d81bcec12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056082823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3056082823
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1917136435
Short name T121
Test name
Test status
Simulation time 13670099431 ps
CPU time 170.24 seconds
Started Jun 23 04:44:45 PM PDT 24
Finished Jun 23 04:47:35 PM PDT 24
Peak memory 214864 kb
Host smart-23c443b7-a6a1-4aa3-9444-167741635510
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917136435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1917136435
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1691311472
Short name T442
Test name
Test status
Simulation time 11779932936 ps
CPU time 26.42 seconds
Started Jun 23 04:44:58 PM PDT 24
Finished Jun 23 04:45:25 PM PDT 24
Peak memory 211724 kb
Host smart-437e501e-e973-4f65-b09a-77a55b095521
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691311472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1691311472
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3460778706
Short name T365
Test name
Test status
Simulation time 174391352 ps
CPU time 8.58 seconds
Started Jun 23 04:44:36 PM PDT 24
Finished Jun 23 04:44:45 PM PDT 24
Peak memory 211328 kb
Host smart-57adf064-8fb7-4806-aad2-c0fecc4a493b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460778706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3460778706
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1287227917
Short name T425
Test name
Test status
Simulation time 215583433 ps
CPU time 15.28 seconds
Started Jun 23 04:44:28 PM PDT 24
Finished Jun 23 04:44:44 PM PDT 24
Peak memory 211328 kb
Host smart-a5a23a27-701b-4589-8332-782c57f61172
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287227917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1287227917
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3420228547
Short name T408
Test name
Test status
Simulation time 2940538583 ps
CPU time 24.51 seconds
Started Jun 23 04:44:40 PM PDT 24
Finished Jun 23 04:45:05 PM PDT 24
Peak memory 218792 kb
Host smart-85aaf669-36cc-4208-9e30-f45c58de96d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420228547 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3420228547
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2163822664
Short name T388
Test name
Test status
Simulation time 2382490138 ps
CPU time 21.93 seconds
Started Jun 23 04:44:53 PM PDT 24
Finished Jun 23 04:45:15 PM PDT 24
Peak memory 212476 kb
Host smart-585b20a3-9e92-4852-919f-1a8f13dbdef4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163822664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2163822664
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2286791831
Short name T398
Test name
Test status
Simulation time 861332303 ps
CPU time 11.12 seconds
Started Jun 23 04:44:39 PM PDT 24
Finished Jun 23 04:44:51 PM PDT 24
Peak memory 211132 kb
Host smart-c76fb665-db49-4855-a8ab-f05791096c5d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286791831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2286791831
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2107218694
Short name T441
Test name
Test status
Simulation time 24517300723 ps
CPU time 32.64 seconds
Started Jun 23 04:44:49 PM PDT 24
Finished Jun 23 04:45:22 PM PDT 24
Peak memory 211244 kb
Host smart-4fb43844-be9d-4949-bd77-ba05bd9bad7f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107218694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2107218694
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1034100240
Short name T414
Test name
Test status
Simulation time 80468835425 ps
CPU time 160.39 seconds
Started Jun 23 04:44:51 PM PDT 24
Finished Jun 23 04:47:32 PM PDT 24
Peak memory 219640 kb
Host smart-9ae89445-72de-491f-8cf9-c03607f83217
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034100240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1034100240
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1373397564
Short name T104
Test name
Test status
Simulation time 3199489494 ps
CPU time 30.05 seconds
Started Jun 23 04:44:40 PM PDT 24
Finished Jun 23 04:45:10 PM PDT 24
Peak memory 212840 kb
Host smart-8a39d7d9-fb68-463b-881b-7cbdba35d133
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373397564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1373397564
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.37357739
Short name T364
Test name
Test status
Simulation time 8189178994 ps
CPU time 24.53 seconds
Started Jun 23 04:44:46 PM PDT 24
Finished Jun 23 04:45:11 PM PDT 24
Peak memory 219092 kb
Host smart-f0301d24-99b9-4c38-82ea-b74550be2060
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37357739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.37357739
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2326276050
Short name T125
Test name
Test status
Simulation time 7761750191 ps
CPU time 171.28 seconds
Started Jun 23 04:45:07 PM PDT 24
Finished Jun 23 04:48:00 PM PDT 24
Peak memory 219560 kb
Host smart-bf2cb3f0-a699-4037-aa0b-a0d3f977f560
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326276050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2326276050
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2284272108
Short name T379
Test name
Test status
Simulation time 15071003911 ps
CPU time 29.11 seconds
Started Jun 23 04:44:35 PM PDT 24
Finished Jun 23 04:45:05 PM PDT 24
Peak memory 212604 kb
Host smart-84a3bcb1-0c12-46d8-b4c0-8c8f37ee0db1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284272108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2284272108
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1857883691
Short name T419
Test name
Test status
Simulation time 1253938443 ps
CPU time 13.5 seconds
Started Jun 23 04:44:41 PM PDT 24
Finished Jun 23 04:44:55 PM PDT 24
Peak memory 211328 kb
Host smart-9ddecc58-3118-4e4c-9f9c-5580fa291ffc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857883691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1857883691
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2860495959
Short name T111
Test name
Test status
Simulation time 728556240 ps
CPU time 11.58 seconds
Started Jun 23 04:44:28 PM PDT 24
Finished Jun 23 04:44:40 PM PDT 24
Peak memory 211908 kb
Host smart-17911269-d381-4104-b5fb-a02cf106ae62
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860495959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2860495959
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3032492631
Short name T386
Test name
Test status
Simulation time 4598739991 ps
CPU time 31.81 seconds
Started Jun 23 04:44:37 PM PDT 24
Finished Jun 23 04:45:09 PM PDT 24
Peak memory 218704 kb
Host smart-010ae9d6-53db-4bf8-a9aa-c001782ffe4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032492631 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3032492631
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3338846819
Short name T376
Test name
Test status
Simulation time 348649621 ps
CPU time 10.68 seconds
Started Jun 23 04:44:35 PM PDT 24
Finished Jun 23 04:44:46 PM PDT 24
Peak memory 211260 kb
Host smart-7547fe80-7662-46d1-a6fc-3b66426df561
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338846819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3338846819
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4084111377
Short name T438
Test name
Test status
Simulation time 4924329877 ps
CPU time 23.37 seconds
Started Jun 23 04:44:32 PM PDT 24
Finished Jun 23 04:44:55 PM PDT 24
Peak memory 211252 kb
Host smart-99c9ead9-27fd-4f18-9d6a-83c7c2759ba0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084111377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.4084111377
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4175263741
Short name T428
Test name
Test status
Simulation time 70348925304 ps
CPU time 32.63 seconds
Started Jun 23 04:45:02 PM PDT 24
Finished Jun 23 04:45:36 PM PDT 24
Peak memory 211348 kb
Host smart-6abbf2d2-9d94-4cfe-9107-170c722096eb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175263741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.4175263741
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1288888854
Short name T447
Test name
Test status
Simulation time 36965724484 ps
CPU time 155.35 seconds
Started Jun 23 04:44:35 PM PDT 24
Finished Jun 23 04:47:10 PM PDT 24
Peak memory 219600 kb
Host smart-56e2b494-5add-47e9-91a2-a00f77dcfe5a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288888854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1288888854
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.252948667
Short name T107
Test name
Test status
Simulation time 332033615 ps
CPU time 8.24 seconds
Started Jun 23 04:44:35 PM PDT 24
Finished Jun 23 04:44:44 PM PDT 24
Peak memory 211940 kb
Host smart-80f38427-b3f8-4f8e-a1a6-aa9bf2b9b657
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252948667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.252948667
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2610822068
Short name T396
Test name
Test status
Simulation time 2886390732 ps
CPU time 27.53 seconds
Started Jun 23 04:44:27 PM PDT 24
Finished Jun 23 04:44:55 PM PDT 24
Peak memory 219552 kb
Host smart-61d98077-7234-4f14-a49e-44361da10e8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610822068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2610822068
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1089501578
Short name T120
Test name
Test status
Simulation time 258226848 ps
CPU time 78.99 seconds
Started Jun 23 04:44:32 PM PDT 24
Finished Jun 23 04:45:52 PM PDT 24
Peak memory 213956 kb
Host smart-aba84921-156f-4eda-8b6e-c14fcbe88cf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089501578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1089501578
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3115624661
Short name T426
Test name
Test status
Simulation time 8364396965 ps
CPU time 31.49 seconds
Started Jun 23 04:44:34 PM PDT 24
Finished Jun 23 04:45:06 PM PDT 24
Peak memory 219604 kb
Host smart-a8815dbd-a437-4b62-a811-8fee10e55c30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115624661 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3115624661
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2091594956
Short name T413
Test name
Test status
Simulation time 7797916090 ps
CPU time 18.17 seconds
Started Jun 23 04:44:51 PM PDT 24
Finished Jun 23 04:45:10 PM PDT 24
Peak memory 213084 kb
Host smart-0bd30b39-bfe4-4d08-a5df-eeef91ebbb49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091594956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2091594956
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1622746682
Short name T115
Test name
Test status
Simulation time 35803972318 ps
CPU time 130.16 seconds
Started Jun 23 04:44:36 PM PDT 24
Finished Jun 23 04:46:46 PM PDT 24
Peak memory 214312 kb
Host smart-a9978202-4719-4d6d-982d-a2dd23479f82
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622746682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1622746682
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1049096274
Short name T440
Test name
Test status
Simulation time 47468607415 ps
CPU time 32.32 seconds
Started Jun 23 04:44:28 PM PDT 24
Finished Jun 23 04:45:01 PM PDT 24
Peak memory 213028 kb
Host smart-added28a-a7e3-4bf8-b982-0a03db7720cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049096274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1049096274
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3755712640
Short name T436
Test name
Test status
Simulation time 4899149233 ps
CPU time 19.28 seconds
Started Jun 23 04:44:37 PM PDT 24
Finished Jun 23 04:44:57 PM PDT 24
Peak memory 219052 kb
Host smart-c0d72ae7-d1ef-4781-9e82-289bb13608b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755712640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3755712640
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2807651269
Short name T366
Test name
Test status
Simulation time 2298460413 ps
CPU time 21.01 seconds
Started Jun 23 04:44:52 PM PDT 24
Finished Jun 23 04:45:14 PM PDT 24
Peak memory 219000 kb
Host smart-c28e1cff-dae9-4107-b3de-afa33cf9e249
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807651269 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2807651269
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.80090813
Short name T91
Test name
Test status
Simulation time 8702880787 ps
CPU time 32.91 seconds
Started Jun 23 04:44:29 PM PDT 24
Finished Jun 23 04:45:02 PM PDT 24
Peak memory 212772 kb
Host smart-6d982032-7cac-40cd-98c9-d91c21e17313
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80090813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.80090813
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.4159611748
Short name T394
Test name
Test status
Simulation time 2999052064 ps
CPU time 37.73 seconds
Started Jun 23 04:44:33 PM PDT 24
Finished Jun 23 04:45:11 PM PDT 24
Peak memory 213604 kb
Host smart-4ac9e9e9-791d-4e24-8c59-b1ac5d335493
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159611748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.4159611748
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2541931858
Short name T105
Test name
Test status
Simulation time 31441212497 ps
CPU time 35.85 seconds
Started Jun 23 04:44:34 PM PDT 24
Finished Jun 23 04:45:10 PM PDT 24
Peak memory 213320 kb
Host smart-0c5ede62-abab-4a93-8d1d-4dae01f7449f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541931858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2541931858
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.580413728
Short name T381
Test name
Test status
Simulation time 10254253931 ps
CPU time 26.69 seconds
Started Jun 23 04:45:07 PM PDT 24
Finished Jun 23 04:45:35 PM PDT 24
Peak memory 219292 kb
Host smart-eaa7f1ed-0cfb-4a30-82a7-716dc5def325
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580413728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.580413728
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2921231269
Short name T119
Test name
Test status
Simulation time 61215316837 ps
CPU time 169.75 seconds
Started Jun 23 04:44:27 PM PDT 24
Finished Jun 23 04:47:17 PM PDT 24
Peak memory 214792 kb
Host smart-200cf98c-6c59-4a2e-a44b-ff7b3322dea6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921231269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2921231269
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3681432261
Short name T427
Test name
Test status
Simulation time 4112573229 ps
CPU time 32.28 seconds
Started Jun 23 04:44:56 PM PDT 24
Finished Jun 23 04:45:29 PM PDT 24
Peak memory 218376 kb
Host smart-f96219a6-f39e-42fd-87d9-ab607d4b0c99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681432261 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3681432261
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3600315123
Short name T449
Test name
Test status
Simulation time 2622091466 ps
CPU time 23.35 seconds
Started Jun 23 04:44:54 PM PDT 24
Finished Jun 23 04:45:23 PM PDT 24
Peak memory 211952 kb
Host smart-1fffa395-ea3e-498a-9f36-d4fb71b51dad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600315123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3600315123
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1779389451
Short name T403
Test name
Test status
Simulation time 9321930472 ps
CPU time 55.38 seconds
Started Jun 23 04:44:54 PM PDT 24
Finished Jun 23 04:45:50 PM PDT 24
Peak memory 215996 kb
Host smart-8f97ebe1-ffa0-4ad6-bda6-e908736051f6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779389451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1779389451
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.788425999
Short name T420
Test name
Test status
Simulation time 22156783983 ps
CPU time 30.43 seconds
Started Jun 23 04:44:43 PM PDT 24
Finished Jun 23 04:45:14 PM PDT 24
Peak memory 213116 kb
Host smart-33df432c-27bf-4754-b4b6-3e3e86e3ec5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788425999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.788425999
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.196926601
Short name T369
Test name
Test status
Simulation time 2659816086 ps
CPU time 27.7 seconds
Started Jun 23 04:44:47 PM PDT 24
Finished Jun 23 04:45:15 PM PDT 24
Peak memory 219052 kb
Host smart-114be991-4b61-4889-bdcb-31690fb3eda4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196926601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.196926601
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1173385139
Short name T117
Test name
Test status
Simulation time 2309193687 ps
CPU time 93.68 seconds
Started Jun 23 04:44:29 PM PDT 24
Finished Jun 23 04:46:03 PM PDT 24
Peak memory 212852 kb
Host smart-066dd874-9f4d-4540-a493-c8a8d18a3c67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173385139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1173385139
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4112972962
Short name T362
Test name
Test status
Simulation time 3958063498 ps
CPU time 29.58 seconds
Started Jun 23 04:44:37 PM PDT 24
Finished Jun 23 04:45:12 PM PDT 24
Peak memory 218248 kb
Host smart-aac6c245-d7ed-4339-bc8e-cee4d74d75bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112972962 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.4112972962
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.65928699
Short name T106
Test name
Test status
Simulation time 16428488132 ps
CPU time 27.97 seconds
Started Jun 23 04:44:28 PM PDT 24
Finished Jun 23 04:44:56 PM PDT 24
Peak memory 212700 kb
Host smart-f626a51e-a98d-4517-9be2-df7c16d4e333
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65928699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.65928699
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.143712141
Short name T391
Test name
Test status
Simulation time 21006856343 ps
CPU time 68.15 seconds
Started Jun 23 04:44:35 PM PDT 24
Finished Jun 23 04:45:44 PM PDT 24
Peak memory 214696 kb
Host smart-3cbfd053-3191-4afd-979a-58b8ee1259de
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143712141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.143712141
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3329139284
Short name T410
Test name
Test status
Simulation time 5780583897 ps
CPU time 20.77 seconds
Started Jun 23 04:44:43 PM PDT 24
Finished Jun 23 04:45:04 PM PDT 24
Peak memory 212304 kb
Host smart-36a06fde-05e5-4eeb-97e1-c68bae42f7d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329139284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3329139284
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2471899207
Short name T446
Test name
Test status
Simulation time 3855409596 ps
CPU time 23.85 seconds
Started Jun 23 04:44:44 PM PDT 24
Finished Jun 23 04:45:08 PM PDT 24
Peak memory 217904 kb
Host smart-dd6e7e85-67e8-4570-9898-6690217283d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471899207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2471899207
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2352839549
Short name T126
Test name
Test status
Simulation time 452265053 ps
CPU time 80.93 seconds
Started Jun 23 04:44:48 PM PDT 24
Finished Jun 23 04:46:09 PM PDT 24
Peak memory 213904 kb
Host smart-64133d88-4e05-4dad-baef-2514c9a16577
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352839549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2352839549
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2372298856
Short name T371
Test name
Test status
Simulation time 4022960594 ps
CPU time 32.05 seconds
Started Jun 23 04:44:39 PM PDT 24
Finished Jun 23 04:45:11 PM PDT 24
Peak memory 218112 kb
Host smart-f4a43370-bd44-4586-ac40-5bfc27d4c4f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372298856 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2372298856
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2187839560
Short name T431
Test name
Test status
Simulation time 53337175172 ps
CPU time 27.71 seconds
Started Jun 23 04:44:57 PM PDT 24
Finished Jun 23 04:45:26 PM PDT 24
Peak memory 213144 kb
Host smart-4afad8bf-d2df-4015-bd88-efc6a56d5730
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187839560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2187839560
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.4222642710
Short name T108
Test name
Test status
Simulation time 4511905798 ps
CPU time 33.22 seconds
Started Jun 23 04:44:44 PM PDT 24
Finished Jun 23 04:45:17 PM PDT 24
Peak memory 213168 kb
Host smart-fe2961ae-3d85-44c8-9484-1342143b22b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222642710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.4222642710
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3339323410
Short name T450
Test name
Test status
Simulation time 2637011547 ps
CPU time 25.76 seconds
Started Jun 23 04:45:02 PM PDT 24
Finished Jun 23 04:45:29 PM PDT 24
Peak memory 219552 kb
Host smart-29ea9ba5-2440-4c6b-a812-5ddb9dc18b11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339323410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3339323410
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.4146550452
Short name T380
Test name
Test status
Simulation time 848227053 ps
CPU time 80.03 seconds
Started Jun 23 04:45:01 PM PDT 24
Finished Jun 23 04:46:22 PM PDT 24
Peak memory 213112 kb
Host smart-f5ab46c9-de68-4387-9960-602e05a37cbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146550452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.4146550452
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3867104962
Short name T186
Test name
Test status
Simulation time 5749067431 ps
CPU time 12.27 seconds
Started Jun 23 05:37:25 PM PDT 24
Finished Jun 23 05:37:38 PM PDT 24
Peak memory 217348 kb
Host smart-e1954978-cf18-42eb-8550-c8d702024650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867104962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3867104962
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.4057340148
Short name T263
Test name
Test status
Simulation time 42257839312 ps
CPU time 480.48 seconds
Started Jun 23 05:37:17 PM PDT 24
Finished Jun 23 05:45:18 PM PDT 24
Peak memory 237476 kb
Host smart-89644344-8a67-4e46-b992-98f6cb9edabf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057340148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.4057340148
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2924513723
Short name T180
Test name
Test status
Simulation time 8331213099 ps
CPU time 67.07 seconds
Started Jun 23 05:37:17 PM PDT 24
Finished Jun 23 05:38:25 PM PDT 24
Peak memory 219332 kb
Host smart-5b56e60b-7ebd-4cfb-96e1-ab0e2c91e7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924513723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2924513723
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.58466637
Short name T353
Test name
Test status
Simulation time 774514282 ps
CPU time 14.83 seconds
Started Jun 23 05:37:13 PM PDT 24
Finished Jun 23 05:37:29 PM PDT 24
Peak memory 218440 kb
Host smart-145bfe19-7d90-42bb-afe5-1e1c0459362c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58466637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.58466637
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2211075310
Short name T351
Test name
Test status
Simulation time 14438949031 ps
CPU time 59.6 seconds
Started Jun 23 05:37:15 PM PDT 24
Finished Jun 23 05:38:15 PM PDT 24
Peak memory 218900 kb
Host smart-d006fbb7-3901-4710-aa63-18638934e987
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211075310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2211075310
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.4044992766
Short name T164
Test name
Test status
Simulation time 6885290190 ps
CPU time 16.89 seconds
Started Jun 23 05:37:25 PM PDT 24
Finished Jun 23 05:37:43 PM PDT 24
Peak memory 217484 kb
Host smart-ee713fdf-4f7a-4b7f-9441-900078a5dd0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044992766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.4044992766
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3687570019
Short name T312
Test name
Test status
Simulation time 23927967654 ps
CPU time 443.93 seconds
Started Jun 23 05:37:17 PM PDT 24
Finished Jun 23 05:44:41 PM PDT 24
Peak memory 239380 kb
Host smart-5d8c0bc5-8d98-4d77-9bbb-570cd9b6d2d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687570019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3687570019
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1226809293
Short name T156
Test name
Test status
Simulation time 10158776877 ps
CPU time 34.59 seconds
Started Jun 23 05:37:18 PM PDT 24
Finished Jun 23 05:37:54 PM PDT 24
Peak memory 219152 kb
Host smart-4476dffd-ba32-454b-a781-65210baa0e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226809293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1226809293
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.419075172
Short name T135
Test name
Test status
Simulation time 475491281 ps
CPU time 10.58 seconds
Started Jun 23 05:37:19 PM PDT 24
Finished Jun 23 05:37:31 PM PDT 24
Peak memory 219344 kb
Host smart-96d1490c-7e25-4f77-a5fe-1d030b0c04d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=419075172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.419075172
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1064472230
Short name T19
Test name
Test status
Simulation time 10013922621 ps
CPU time 239.91 seconds
Started Jun 23 05:37:16 PM PDT 24
Finished Jun 23 05:41:17 PM PDT 24
Peak memory 237632 kb
Host smart-fd0dba50-c7cb-4a71-9ffa-e488d58f0475
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064472230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1064472230
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2611444949
Short name T97
Test name
Test status
Simulation time 55025621681 ps
CPU time 63.84 seconds
Started Jun 23 05:37:17 PM PDT 24
Finished Jun 23 05:38:22 PM PDT 24
Peak memory 216668 kb
Host smart-59179c00-8029-4dff-8d9e-a162a2f43cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611444949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2611444949
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1167812759
Short name T201
Test name
Test status
Simulation time 22061288611 ps
CPU time 128.68 seconds
Started Jun 23 05:37:20 PM PDT 24
Finished Jun 23 05:39:29 PM PDT 24
Peak memory 219360 kb
Host smart-ea51b5d1-6d44-4ac3-971f-0b8b41d8a128
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167812759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1167812759
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1079519978
Short name T155
Test name
Test status
Simulation time 2403378278 ps
CPU time 23.59 seconds
Started Jun 23 05:37:29 PM PDT 24
Finished Jun 23 05:37:53 PM PDT 24
Peak memory 217112 kb
Host smart-2258a790-c10e-4422-ba98-c1cbcb0a2433
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079519978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1079519978
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2095924150
Short name T190
Test name
Test status
Simulation time 34222371944 ps
CPU time 568.82 seconds
Started Jun 23 05:37:28 PM PDT 24
Finished Jun 23 05:46:57 PM PDT 24
Peak memory 241704 kb
Host smart-27795655-1126-4317-a90d-b3f715204455
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095924150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2095924150
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2835019323
Short name T247
Test name
Test status
Simulation time 2160628689 ps
CPU time 24.02 seconds
Started Jun 23 05:37:27 PM PDT 24
Finished Jun 23 05:37:52 PM PDT 24
Peak memory 219340 kb
Host smart-11bedd98-36ea-457f-90ea-0f620d6be0a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2835019323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2835019323
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1664758935
Short name T205
Test name
Test status
Simulation time 3256573178 ps
CPU time 34.26 seconds
Started Jun 23 05:37:25 PM PDT 24
Finished Jun 23 05:38:00 PM PDT 24
Peak memory 216328 kb
Host smart-3e57a33a-7bb4-4cac-9cce-e8ca5a44f044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664758935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1664758935
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.281229554
Short name T268
Test name
Test status
Simulation time 3761836250 ps
CPU time 30.54 seconds
Started Jun 23 05:37:29 PM PDT 24
Finished Jun 23 05:38:00 PM PDT 24
Peak memory 219180 kb
Host smart-2e4d2f77-8c02-4b9a-b465-dc0c6c8a9281
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281229554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.281229554
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.632183787
Short name T194
Test name
Test status
Simulation time 179628041081 ps
CPU time 367.79 seconds
Started Jun 23 05:37:33 PM PDT 24
Finished Jun 23 05:43:41 PM PDT 24
Peak memory 238992 kb
Host smart-5826d1be-6c86-4853-bfda-aaaf8ce4af2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632183787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.632183787
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.355204996
Short name T339
Test name
Test status
Simulation time 48026869592 ps
CPU time 62.94 seconds
Started Jun 23 05:37:31 PM PDT 24
Finished Jun 23 05:38:34 PM PDT 24
Peak memory 219308 kb
Host smart-8a7d6829-8986-4885-bab6-7299a8b7421d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355204996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.355204996
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.56826497
Short name T244
Test name
Test status
Simulation time 697433678 ps
CPU time 10.5 seconds
Started Jun 23 05:37:35 PM PDT 24
Finished Jun 23 05:37:46 PM PDT 24
Peak memory 219280 kb
Host smart-a5a9b516-80c6-4f31-8f3d-8c5770f40588
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=56826497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.56826497
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3400490131
Short name T183
Test name
Test status
Simulation time 22379027539 ps
CPU time 60.65 seconds
Started Jun 23 05:37:28 PM PDT 24
Finished Jun 23 05:38:29 PM PDT 24
Peak memory 217332 kb
Host smart-14d36040-78ba-4326-b98f-90d4c72ce10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400490131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3400490131
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1671030335
Short name T150
Test name
Test status
Simulation time 11482296107 ps
CPU time 78.72 seconds
Started Jun 23 05:37:28 PM PDT 24
Finished Jun 23 05:38:47 PM PDT 24
Peak memory 227552 kb
Host smart-dd7d1f33-0d1d-48d0-bdb0-e57eea02226f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671030335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1671030335
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3000006623
Short name T273
Test name
Test status
Simulation time 6155133858 ps
CPU time 17.94 seconds
Started Jun 23 05:37:36 PM PDT 24
Finished Jun 23 05:37:54 PM PDT 24
Peak memory 217412 kb
Host smart-32063213-26a9-4758-8c0b-ea2804b95332
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000006623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3000006623
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2078402167
Short name T40
Test name
Test status
Simulation time 197645559817 ps
CPU time 606.33 seconds
Started Jun 23 05:37:30 PM PDT 24
Finished Jun 23 05:47:37 PM PDT 24
Peak memory 227976 kb
Host smart-bcaeda91-de20-43e3-9238-b9232f26f49b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078402167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2078402167
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1157615503
Short name T327
Test name
Test status
Simulation time 179900889 ps
CPU time 10.76 seconds
Started Jun 23 05:37:31 PM PDT 24
Finished Jun 23 05:37:43 PM PDT 24
Peak memory 219340 kb
Host smart-73143614-eca7-4dbc-8370-77ca390fe54b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1157615503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1157615503
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1314141904
Short name T288
Test name
Test status
Simulation time 18235743405 ps
CPU time 68.26 seconds
Started Jun 23 05:37:32 PM PDT 24
Finished Jun 23 05:38:41 PM PDT 24
Peak memory 216840 kb
Host smart-7c73c2b3-ef98-4d65-a8fd-f738c82c082d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314141904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1314141904
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.765295869
Short name T267
Test name
Test status
Simulation time 12967161537 ps
CPU time 116.81 seconds
Started Jun 23 05:37:31 PM PDT 24
Finished Jun 23 05:39:29 PM PDT 24
Peak memory 219320 kb
Host smart-0bee3a5f-18dd-442e-8995-8dbb63b7487e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765295869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.765295869
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2037706240
Short name T139
Test name
Test status
Simulation time 2947381161 ps
CPU time 27.05 seconds
Started Jun 23 05:37:31 PM PDT 24
Finished Jun 23 05:37:58 PM PDT 24
Peak memory 217100 kb
Host smart-4282a1f2-fdc4-4efa-8f10-8936c9cfacec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037706240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2037706240
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.604669296
Short name T41
Test name
Test status
Simulation time 45089001986 ps
CPU time 467.79 seconds
Started Jun 23 05:37:34 PM PDT 24
Finished Jun 23 05:45:22 PM PDT 24
Peak memory 242452 kb
Host smart-671e4249-1134-46ee-87b9-278d5dd2f368
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604669296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.604669296
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3160940878
Short name T2
Test name
Test status
Simulation time 15187751421 ps
CPU time 65.59 seconds
Started Jun 23 05:37:34 PM PDT 24
Finished Jun 23 05:38:40 PM PDT 24
Peak memory 219128 kb
Host smart-9be22a57-b264-4406-a59a-dc76b32e6d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160940878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3160940878
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2716715900
Short name T7
Test name
Test status
Simulation time 2717628455 ps
CPU time 24.84 seconds
Started Jun 23 05:37:33 PM PDT 24
Finished Jun 23 05:37:59 PM PDT 24
Peak memory 219372 kb
Host smart-3de173d8-f9c8-4f2a-8c3f-ab91b4e69c32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2716715900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2716715900
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3904376204
Short name T96
Test name
Test status
Simulation time 7542354573 ps
CPU time 68.72 seconds
Started Jun 23 05:37:33 PM PDT 24
Finished Jun 23 05:38:42 PM PDT 24
Peak memory 217276 kb
Host smart-ae0628a7-2fd8-4c46-bc6a-eabe11421e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904376204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3904376204
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.761582393
Short name T188
Test name
Test status
Simulation time 34072921039 ps
CPU time 46.38 seconds
Started Jun 23 05:37:32 PM PDT 24
Finished Jun 23 05:38:19 PM PDT 24
Peak memory 217656 kb
Host smart-017bb921-e848-4706-bc59-bb247b8f4fe0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761582393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.761582393
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.2284673183
Short name T53
Test name
Test status
Simulation time 331758612478 ps
CPU time 1271.18 seconds
Started Jun 23 05:37:33 PM PDT 24
Finished Jun 23 05:58:45 PM PDT 24
Peak memory 237516 kb
Host smart-9c87eea5-e84f-456a-87fc-7a77914c8c43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284673183 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.2284673183
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.266564554
Short name T42
Test name
Test status
Simulation time 2011164703 ps
CPU time 20.77 seconds
Started Jun 23 05:37:36 PM PDT 24
Finished Jun 23 05:37:57 PM PDT 24
Peak memory 217052 kb
Host smart-2ebe8010-bb05-49be-9015-5503930b09fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266564554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.266564554
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3860254271
Short name T222
Test name
Test status
Simulation time 17496631298 ps
CPU time 70.61 seconds
Started Jun 23 05:37:40 PM PDT 24
Finished Jun 23 05:38:51 PM PDT 24
Peak memory 219304 kb
Host smart-9fa474f1-6617-4af1-9365-194570aa406f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860254271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3860254271
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.739483711
Short name T334
Test name
Test status
Simulation time 366588149 ps
CPU time 10.59 seconds
Started Jun 23 05:37:38 PM PDT 24
Finished Jun 23 05:37:48 PM PDT 24
Peak memory 219312 kb
Host smart-dcaece1f-eb4a-468a-b867-7013e48fbed1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=739483711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.739483711
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3813356738
Short name T11
Test name
Test status
Simulation time 5309494547 ps
CPU time 29.41 seconds
Started Jun 23 05:37:33 PM PDT 24
Finished Jun 23 05:38:02 PM PDT 24
Peak memory 216916 kb
Host smart-2ce16130-4c26-4641-845d-88fef42f42e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813356738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3813356738
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2385906171
Short name T238
Test name
Test status
Simulation time 1443264833 ps
CPU time 54.86 seconds
Started Jun 23 05:37:32 PM PDT 24
Finished Jun 23 05:38:27 PM PDT 24
Peak memory 219268 kb
Host smart-f50bae40-22f7-4c41-9470-212e58fb4576
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385906171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2385906171
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1037270111
Short name T298
Test name
Test status
Simulation time 493934833 ps
CPU time 12.49 seconds
Started Jun 23 05:37:40 PM PDT 24
Finished Jun 23 05:37:53 PM PDT 24
Peak memory 217084 kb
Host smart-e3b3e6a7-208d-4f14-8d68-7113fcabd506
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037270111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1037270111
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1911671417
Short name T284
Test name
Test status
Simulation time 18767729015 ps
CPU time 415.62 seconds
Started Jun 23 05:37:37 PM PDT 24
Finished Jun 23 05:44:33 PM PDT 24
Peak memory 225564 kb
Host smart-58d16351-e838-4a39-b895-12f6e413e6e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911671417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1911671417
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1309156080
Short name T331
Test name
Test status
Simulation time 345914239 ps
CPU time 19.34 seconds
Started Jun 23 05:37:40 PM PDT 24
Finished Jun 23 05:38:00 PM PDT 24
Peak memory 219264 kb
Host smart-82a4dd05-3274-40e4-bac0-dcd02155c807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309156080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1309156080
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2647723234
Short name T356
Test name
Test status
Simulation time 6361432186 ps
CPU time 21.96 seconds
Started Jun 23 05:37:36 PM PDT 24
Finished Jun 23 05:37:58 PM PDT 24
Peak memory 217756 kb
Host smart-0ad63596-597b-482a-8bdf-f698ac91c01a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2647723234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2647723234
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.773289517
Short name T3
Test name
Test status
Simulation time 49543133626 ps
CPU time 59.41 seconds
Started Jun 23 05:37:40 PM PDT 24
Finished Jun 23 05:38:40 PM PDT 24
Peak memory 217076 kb
Host smart-bcb5ed89-0fb3-4d9e-8b24-9326fa1fd0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773289517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.773289517
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3151222081
Short name T198
Test name
Test status
Simulation time 190267478 ps
CPU time 20.69 seconds
Started Jun 23 05:37:36 PM PDT 24
Finished Jun 23 05:37:57 PM PDT 24
Peak memory 218852 kb
Host smart-7af29013-48b7-4018-b1d0-8bc8003e93bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151222081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3151222081
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1676937088
Short name T54
Test name
Test status
Simulation time 15844200903 ps
CPU time 564.53 seconds
Started Jun 23 05:37:37 PM PDT 24
Finished Jun 23 05:47:02 PM PDT 24
Peak memory 228428 kb
Host smart-6ecb4235-36e5-49a1-abf9-f93ac3c7b523
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676937088 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.1676937088
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3573713434
Short name T243
Test name
Test status
Simulation time 1732602501 ps
CPU time 10.77 seconds
Started Jun 23 05:37:36 PM PDT 24
Finished Jun 23 05:37:47 PM PDT 24
Peak memory 217016 kb
Host smart-abab5128-4790-4edc-9eaa-2b7dec04bf0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573713434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3573713434
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3361201158
Short name T18
Test name
Test status
Simulation time 2805276199 ps
CPU time 197.77 seconds
Started Jun 23 05:37:41 PM PDT 24
Finished Jun 23 05:40:59 PM PDT 24
Peak memory 241492 kb
Host smart-a451d521-c822-49b1-93f5-aa2e89b02dd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361201158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3361201158
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1367467568
Short name T251
Test name
Test status
Simulation time 23527496970 ps
CPU time 55.84 seconds
Started Jun 23 05:37:40 PM PDT 24
Finished Jun 23 05:38:36 PM PDT 24
Peak memory 219328 kb
Host smart-13b894c6-89e9-46e8-bd53-99aba41783b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367467568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1367467568
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1254937206
Short name T321
Test name
Test status
Simulation time 13690729786 ps
CPU time 28.83 seconds
Started Jun 23 05:37:36 PM PDT 24
Finished Jun 23 05:38:06 PM PDT 24
Peak memory 212012 kb
Host smart-beaced68-59bf-4c36-9b4c-148ef762a14a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1254937206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1254937206
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3220233093
Short name T31
Test name
Test status
Simulation time 21402891570 ps
CPU time 52.36 seconds
Started Jun 23 05:37:36 PM PDT 24
Finished Jun 23 05:38:29 PM PDT 24
Peak memory 216872 kb
Host smart-00742da6-ecc8-411d-9e29-0b39a6d0f279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220233093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3220233093
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.4216434378
Short name T264
Test name
Test status
Simulation time 435458734 ps
CPU time 11.19 seconds
Started Jun 23 05:37:36 PM PDT 24
Finished Jun 23 05:37:48 PM PDT 24
Peak memory 216920 kb
Host smart-ddcb4343-c791-4e4c-a4d7-23ce957d7c2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216434378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.4216434378
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1807997330
Short name T151
Test name
Test status
Simulation time 2754670844 ps
CPU time 23.93 seconds
Started Jun 23 05:37:36 PM PDT 24
Finished Jun 23 05:38:00 PM PDT 24
Peak memory 217196 kb
Host smart-733011d7-cf89-48de-b4ea-854910e8400f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807997330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1807997330
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2051131675
Short name T305
Test name
Test status
Simulation time 81348712674 ps
CPU time 832.14 seconds
Started Jun 23 05:37:41 PM PDT 24
Finished Jun 23 05:51:33 PM PDT 24
Peak memory 234000 kb
Host smart-d0217f50-2339-4523-81a3-57d0f4829458
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051131675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2051131675
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3237184297
Short name T45
Test name
Test status
Simulation time 54142204659 ps
CPU time 60.95 seconds
Started Jun 23 05:37:36 PM PDT 24
Finished Jun 23 05:38:38 PM PDT 24
Peak memory 219332 kb
Host smart-f28f0881-3b8e-4fff-b8eb-db3573bdf0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237184297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3237184297
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1912658616
Short name T142
Test name
Test status
Simulation time 2155716059 ps
CPU time 22.42 seconds
Started Jun 23 05:37:37 PM PDT 24
Finished Jun 23 05:38:00 PM PDT 24
Peak memory 217748 kb
Host smart-05f470d7-32cb-4e47-9ab2-a77a5607ca35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1912658616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1912658616
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.380895422
Short name T78
Test name
Test status
Simulation time 5585646197 ps
CPU time 20.8 seconds
Started Jun 23 05:37:36 PM PDT 24
Finished Jun 23 05:37:57 PM PDT 24
Peak memory 216604 kb
Host smart-ba332a44-c691-4998-b09e-58cfc36987db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380895422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.380895422
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3722903721
Short name T254
Test name
Test status
Simulation time 77813137148 ps
CPU time 180.28 seconds
Started Jun 23 05:37:36 PM PDT 24
Finished Jun 23 05:40:37 PM PDT 24
Peak memory 220428 kb
Host smart-ab1f34a5-80ce-465d-b4ab-4f3625a58bd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722903721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3722903721
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1716117395
Short name T55
Test name
Test status
Simulation time 22289347353 ps
CPU time 3298.06 seconds
Started Jun 23 05:37:37 PM PDT 24
Finished Jun 23 06:32:36 PM PDT 24
Peak memory 235788 kb
Host smart-bb753fbc-9aea-4b76-80aa-f41732766e74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716117395 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.1716117395
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.395373827
Short name T262
Test name
Test status
Simulation time 167658769 ps
CPU time 8.44 seconds
Started Jun 23 05:37:42 PM PDT 24
Finished Jun 23 05:37:52 PM PDT 24
Peak memory 216964 kb
Host smart-697c1fe7-bfeb-4434-8e4b-3625cb24cb7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395373827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.395373827
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3306068138
Short name T280
Test name
Test status
Simulation time 2161431270 ps
CPU time 126.51 seconds
Started Jun 23 05:37:39 PM PDT 24
Finished Jun 23 05:39:46 PM PDT 24
Peak memory 238852 kb
Host smart-9aeb41f1-92fc-414e-911e-96ca56718aaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306068138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3306068138
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2835812570
Short name T228
Test name
Test status
Simulation time 30315814112 ps
CPU time 44.3 seconds
Started Jun 23 05:37:41 PM PDT 24
Finished Jun 23 05:38:26 PM PDT 24
Peak memory 219328 kb
Host smart-3a7c13e2-321f-454c-9d63-b05c10e7782a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835812570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2835812570
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2200287536
Short name T195
Test name
Test status
Simulation time 2458267214 ps
CPU time 24.53 seconds
Started Jun 23 05:37:38 PM PDT 24
Finished Jun 23 05:38:03 PM PDT 24
Peak memory 211448 kb
Host smart-7de1b096-26b7-4054-883b-b8c2ad01cbb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2200287536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2200287536
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.550879511
Short name T358
Test name
Test status
Simulation time 76993352673 ps
CPU time 74.69 seconds
Started Jun 23 05:37:38 PM PDT 24
Finished Jun 23 05:38:53 PM PDT 24
Peak memory 217252 kb
Host smart-48a10d99-f1ad-4fac-9d3b-63ee93811425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550879511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.550879511
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.4242738930
Short name T359
Test name
Test status
Simulation time 10366375561 ps
CPU time 75.95 seconds
Started Jun 23 05:37:39 PM PDT 24
Finished Jun 23 05:38:55 PM PDT 24
Peak memory 227464 kb
Host smart-0e680fa7-20c1-4d20-a853-764c1bbb532d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242738930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.4242738930
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.518067973
Short name T352
Test name
Test status
Simulation time 3993624220 ps
CPU time 31.46 seconds
Started Jun 23 05:37:41 PM PDT 24
Finished Jun 23 05:38:13 PM PDT 24
Peak memory 217212 kb
Host smart-3b2ca67a-c400-464f-99ce-fdaa12db5d10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518067973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.518067973
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2789180233
Short name T37
Test name
Test status
Simulation time 8536868532 ps
CPU time 292.99 seconds
Started Jun 23 05:37:40 PM PDT 24
Finished Jun 23 05:42:33 PM PDT 24
Peak memory 239292 kb
Host smart-7d873b61-5027-4345-8a8a-c13f039cedcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789180233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2789180233
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1827510329
Short name T271
Test name
Test status
Simulation time 16831393066 ps
CPU time 66.76 seconds
Started Jun 23 05:37:44 PM PDT 24
Finished Jun 23 05:38:52 PM PDT 24
Peak memory 219052 kb
Host smart-623ba9b9-024b-4607-97ef-05cfed5e11ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827510329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1827510329
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3437729834
Short name T217
Test name
Test status
Simulation time 392951177 ps
CPU time 10.45 seconds
Started Jun 23 05:37:42 PM PDT 24
Finished Jun 23 05:37:53 PM PDT 24
Peak memory 219316 kb
Host smart-1ec5fcd5-7010-4a08-b15a-afd5b498615d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3437729834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3437729834
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2833488293
Short name T224
Test name
Test status
Simulation time 9598996120 ps
CPU time 35.32 seconds
Started Jun 23 05:37:40 PM PDT 24
Finished Jun 23 05:38:16 PM PDT 24
Peak memory 215904 kb
Host smart-fc0b7f59-e4aa-41a8-948a-561869dd6468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833488293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2833488293
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2544465735
Short name T148
Test name
Test status
Simulation time 17099442101 ps
CPU time 146.2 seconds
Started Jun 23 05:37:41 PM PDT 24
Finished Jun 23 05:40:08 PM PDT 24
Peak memory 227552 kb
Host smart-acba2b84-edc8-43bb-a982-f6bf3749bb30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544465735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2544465735
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3605130695
Short name T326
Test name
Test status
Simulation time 7579465395 ps
CPU time 21.05 seconds
Started Jun 23 05:37:20 PM PDT 24
Finished Jun 23 05:37:41 PM PDT 24
Peak memory 217512 kb
Host smart-08413537-e566-4002-80bb-d84a54f0bb43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605130695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3605130695
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.4043191627
Short name T38
Test name
Test status
Simulation time 114735332581 ps
CPU time 611.7 seconds
Started Jun 23 05:37:21 PM PDT 24
Finished Jun 23 05:47:33 PM PDT 24
Peak memory 240296 kb
Host smart-baeed43b-6b6a-42bb-b519-c3822c63b99d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043191627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.4043191627
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.545376823
Short name T248
Test name
Test status
Simulation time 7380408435 ps
CPU time 55.83 seconds
Started Jun 23 05:37:19 PM PDT 24
Finished Jun 23 05:38:15 PM PDT 24
Peak memory 219336 kb
Host smart-fa5d1a38-0ee3-48d2-bed2-09df404875c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545376823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.545376823
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.561411722
Short name T211
Test name
Test status
Simulation time 1656585552 ps
CPU time 19.64 seconds
Started Jun 23 05:37:26 PM PDT 24
Finished Jun 23 05:37:46 PM PDT 24
Peak memory 219308 kb
Host smart-30ba0b61-d2bb-4112-82e4-2b70c79f0c4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=561411722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.561411722
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3815775293
Short name T23
Test name
Test status
Simulation time 278113914 ps
CPU time 219.35 seconds
Started Jun 23 05:37:17 PM PDT 24
Finished Jun 23 05:40:58 PM PDT 24
Peak memory 236620 kb
Host smart-aee885b9-d11e-4af4-bcc1-08d7043642d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815775293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3815775293
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.926888562
Short name T354
Test name
Test status
Simulation time 6740627551 ps
CPU time 32.23 seconds
Started Jun 23 05:37:17 PM PDT 24
Finished Jun 23 05:37:51 PM PDT 24
Peak memory 217224 kb
Host smart-6d40b500-c941-410d-b432-bded11677680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926888562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.926888562
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2087159426
Short name T349
Test name
Test status
Simulation time 1100407100 ps
CPU time 29.41 seconds
Started Jun 23 05:37:20 PM PDT 24
Finished Jun 23 05:37:50 PM PDT 24
Peak memory 219052 kb
Host smart-e18fd9b2-9f79-4fd7-8330-a4d14b166259
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087159426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2087159426
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.411562509
Short name T147
Test name
Test status
Simulation time 1469558858 ps
CPU time 18.12 seconds
Started Jun 23 05:37:42 PM PDT 24
Finished Jun 23 05:38:01 PM PDT 24
Peak memory 217012 kb
Host smart-b90469c6-7c95-471c-ae85-61459e682b47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411562509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.411562509
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3193946943
Short name T166
Test name
Test status
Simulation time 7906460145 ps
CPU time 170.29 seconds
Started Jun 23 05:37:42 PM PDT 24
Finished Jun 23 05:40:33 PM PDT 24
Peak memory 238628 kb
Host smart-7a2c2ca9-2e4e-4fe7-97ae-7045c714c79c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193946943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3193946943
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2411379774
Short name T191
Test name
Test status
Simulation time 1375540889 ps
CPU time 19.25 seconds
Started Jun 23 05:37:42 PM PDT 24
Finished Jun 23 05:38:02 PM PDT 24
Peak memory 219216 kb
Host smart-f00254f5-0d04-4185-91b8-8fae6e28692a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411379774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2411379774
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2675930925
Short name T99
Test name
Test status
Simulation time 3833487077 ps
CPU time 16.78 seconds
Started Jun 23 05:37:41 PM PDT 24
Finished Jun 23 05:37:58 PM PDT 24
Peak memory 219380 kb
Host smart-7d390f59-9b67-4eb4-a2fe-8e112886ea62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2675930925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2675930925
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3588289658
Short name T299
Test name
Test status
Simulation time 6239130894 ps
CPU time 61.29 seconds
Started Jun 23 05:37:40 PM PDT 24
Finished Jun 23 05:38:42 PM PDT 24
Peak memory 216920 kb
Host smart-8779a074-cf70-4412-9103-9695302d4d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588289658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3588289658
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1367986801
Short name T237
Test name
Test status
Simulation time 9092160377 ps
CPU time 41.23 seconds
Started Jun 23 05:37:40 PM PDT 24
Finished Jun 23 05:38:22 PM PDT 24
Peak memory 217432 kb
Host smart-b929df13-9185-4c51-9ffb-0ec7b690d838
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367986801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1367986801
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.4293637727
Short name T152
Test name
Test status
Simulation time 2733772556 ps
CPU time 12.7 seconds
Started Jun 23 05:37:41 PM PDT 24
Finished Jun 23 05:37:54 PM PDT 24
Peak memory 217044 kb
Host smart-b52d2641-f6e8-46bb-bdf4-3be2830c0193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293637727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.4293637727
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1830505028
Short name T214
Test name
Test status
Simulation time 3763420654 ps
CPU time 214.34 seconds
Started Jun 23 05:37:41 PM PDT 24
Finished Jun 23 05:41:16 PM PDT 24
Peak memory 233504 kb
Host smart-4ad4c158-0038-44f2-b3a9-ff3afbb16d44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830505028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1830505028
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4010610650
Short name T5
Test name
Test status
Simulation time 1541999346 ps
CPU time 28.79 seconds
Started Jun 23 05:37:43 PM PDT 24
Finished Jun 23 05:38:12 PM PDT 24
Peak memory 219240 kb
Host smart-1b0af301-010e-422d-8555-94f6059cc149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010610650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4010610650
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2811617405
Short name T333
Test name
Test status
Simulation time 1968055432 ps
CPU time 21.31 seconds
Started Jun 23 05:37:44 PM PDT 24
Finished Jun 23 05:38:06 PM PDT 24
Peak memory 219336 kb
Host smart-122b338d-2a2c-4c5b-882a-9be94c986fc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2811617405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2811617405
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3833239075
Short name T12
Test name
Test status
Simulation time 7946969404 ps
CPU time 75.43 seconds
Started Jun 23 05:37:43 PM PDT 24
Finished Jun 23 05:38:59 PM PDT 24
Peak memory 217556 kb
Host smart-14e012ad-9a60-4f30-a361-30b002f8159d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833239075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3833239075
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3253895104
Short name T200
Test name
Test status
Simulation time 11170467978 ps
CPU time 94.68 seconds
Started Jun 23 05:37:42 PM PDT 24
Finished Jun 23 05:39:18 PM PDT 24
Peak memory 219300 kb
Host smart-01002816-417e-40d2-9011-af4117eceb27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253895104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3253895104
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1592085900
Short name T347
Test name
Test status
Simulation time 665836655 ps
CPU time 12.9 seconds
Started Jun 23 05:37:46 PM PDT 24
Finished Jun 23 05:37:59 PM PDT 24
Peak memory 217136 kb
Host smart-00b10aa3-0bda-4a88-b56f-dff6e8b9e426
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592085900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1592085900
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2505352221
Short name T236
Test name
Test status
Simulation time 2913569413 ps
CPU time 176.49 seconds
Started Jun 23 05:37:45 PM PDT 24
Finished Jun 23 05:40:42 PM PDT 24
Peak memory 233612 kb
Host smart-f974143e-fd35-4084-b55d-1d670dd36743
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505352221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2505352221
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2562480801
Short name T258
Test name
Test status
Simulation time 350208568 ps
CPU time 19.26 seconds
Started Jun 23 05:37:47 PM PDT 24
Finished Jun 23 05:38:06 PM PDT 24
Peak memory 219264 kb
Host smart-0ce4e130-fe1b-4602-bbbb-405481e01587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562480801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2562480801
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.91041914
Short name T25
Test name
Test status
Simulation time 5000665437 ps
CPU time 24.36 seconds
Started Jun 23 05:37:44 PM PDT 24
Finished Jun 23 05:38:09 PM PDT 24
Peak memory 219100 kb
Host smart-6e5c3c67-d8f0-4862-9c97-a8dd681be1b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=91041914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.91041914
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1990617525
Short name T80
Test name
Test status
Simulation time 29631334274 ps
CPU time 73.06 seconds
Started Jun 23 05:37:41 PM PDT 24
Finished Jun 23 05:38:54 PM PDT 24
Peak memory 216780 kb
Host smart-c7bd0623-b330-493c-9593-f9d3090474fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990617525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1990617525
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1840220052
Short name T291
Test name
Test status
Simulation time 1429749200 ps
CPU time 34.29 seconds
Started Jun 23 05:37:40 PM PDT 24
Finished Jun 23 05:38:15 PM PDT 24
Peak memory 219268 kb
Host smart-c367e6a7-321b-4cc2-a49d-7de1ca53d4dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840220052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1840220052
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1094431127
Short name T56
Test name
Test status
Simulation time 41217104882 ps
CPU time 1525.08 seconds
Started Jun 23 05:37:45 PM PDT 24
Finished Jun 23 06:03:11 PM PDT 24
Peak memory 235856 kb
Host smart-8957772f-f1d0-4a34-b717-c0cd84b01d17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094431127 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.1094431127
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1745325857
Short name T179
Test name
Test status
Simulation time 2873946124 ps
CPU time 18.41 seconds
Started Jun 23 05:37:52 PM PDT 24
Finished Jun 23 05:38:11 PM PDT 24
Peak memory 217324 kb
Host smart-27f48b0b-b3a4-4602-b322-fbcfa533ebb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745325857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1745325857
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4153188291
Short name T168
Test name
Test status
Simulation time 128051838090 ps
CPU time 648.85 seconds
Started Jun 23 05:37:45 PM PDT 24
Finished Jun 23 05:48:35 PM PDT 24
Peak memory 239916 kb
Host smart-c3c88270-49ef-40cb-9e92-6a7b1318da02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153188291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.4153188291
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3887763535
Short name T253
Test name
Test status
Simulation time 2292426013 ps
CPU time 34.29 seconds
Started Jun 23 05:37:51 PM PDT 24
Finished Jun 23 05:38:26 PM PDT 24
Peak memory 219296 kb
Host smart-96156221-54c6-45d3-9d69-fb6e5c8fb547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887763535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3887763535
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2103433627
Short name T260
Test name
Test status
Simulation time 241600009 ps
CPU time 10.54 seconds
Started Jun 23 05:37:44 PM PDT 24
Finished Jun 23 05:37:55 PM PDT 24
Peak memory 219284 kb
Host smart-f4111cc7-328b-4aad-a8fe-052262f0b875
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2103433627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2103433627
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.4113393735
Short name T14
Test name
Test status
Simulation time 2149620784 ps
CPU time 19.68 seconds
Started Jun 23 05:37:45 PM PDT 24
Finished Jun 23 05:38:05 PM PDT 24
Peak memory 216400 kb
Host smart-dbe68cec-e892-4d92-a8d2-e1eda71d0ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113393735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.4113393735
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2207553746
Short name T235
Test name
Test status
Simulation time 1530780284 ps
CPU time 44.88 seconds
Started Jun 23 05:37:44 PM PDT 24
Finished Jun 23 05:38:30 PM PDT 24
Peak memory 219296 kb
Host smart-100c2cba-d61e-498a-9caa-3c4a799b9edc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207553746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2207553746
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3487385693
Short name T301
Test name
Test status
Simulation time 3847222004 ps
CPU time 30.47 seconds
Started Jun 23 05:37:54 PM PDT 24
Finished Jun 23 05:38:25 PM PDT 24
Peak memory 216600 kb
Host smart-a673e5d8-cfc6-4711-aa7d-a09b44ce702d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487385693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3487385693
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3921787151
Short name T279
Test name
Test status
Simulation time 152092271533 ps
CPU time 494.85 seconds
Started Jun 23 05:37:53 PM PDT 24
Finished Jun 23 05:46:08 PM PDT 24
Peak memory 227584 kb
Host smart-438d9652-df2e-45ac-84a8-4da6e371a1c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921787151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3921787151
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.579405921
Short name T276
Test name
Test status
Simulation time 9155128855 ps
CPU time 65.4 seconds
Started Jun 23 05:37:50 PM PDT 24
Finished Jun 23 05:38:57 PM PDT 24
Peak memory 219308 kb
Host smart-ce59d53c-ee88-49db-b2c2-56cef6631d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579405921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.579405921
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1996365987
Short name T181
Test name
Test status
Simulation time 5304146651 ps
CPU time 55.1 seconds
Started Jun 23 05:37:55 PM PDT 24
Finished Jun 23 05:38:51 PM PDT 24
Peak memory 216760 kb
Host smart-120be3ff-f22d-4f12-ba12-35d33272eafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996365987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1996365987
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2520801468
Short name T32
Test name
Test status
Simulation time 7741022901 ps
CPU time 77.83 seconds
Started Jun 23 05:37:56 PM PDT 24
Finished Jun 23 05:39:14 PM PDT 24
Peak memory 219328 kb
Host smart-7daed35f-7815-4f07-9495-426c5a024ecd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520801468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2520801468
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1841770156
Short name T213
Test name
Test status
Simulation time 2631974497 ps
CPU time 20.46 seconds
Started Jun 23 05:37:52 PM PDT 24
Finished Jun 23 05:38:13 PM PDT 24
Peak memory 217064 kb
Host smart-b33c8123-b8af-4585-97af-31ee0187a9af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841770156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1841770156
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2738329165
Short name T360
Test name
Test status
Simulation time 3131193517 ps
CPU time 185.67 seconds
Started Jun 23 05:37:53 PM PDT 24
Finished Jun 23 05:41:00 PM PDT 24
Peak memory 243500 kb
Host smart-2fe2ce74-9771-4732-abdf-c28681c5e836
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738329165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2738329165
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1840302588
Short name T22
Test name
Test status
Simulation time 35651301807 ps
CPU time 69.44 seconds
Started Jun 23 05:37:49 PM PDT 24
Finished Jun 23 05:38:59 PM PDT 24
Peak memory 219332 kb
Host smart-bc69bf9a-f620-427c-bad7-69bf4888de07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840302588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1840302588
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.409917982
Short name T170
Test name
Test status
Simulation time 1710428017 ps
CPU time 9.89 seconds
Started Jun 23 05:37:54 PM PDT 24
Finished Jun 23 05:38:04 PM PDT 24
Peak memory 219312 kb
Host smart-f339003f-4920-492a-bd64-af2b918dd64d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=409917982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.409917982
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.807025526
Short name T249
Test name
Test status
Simulation time 21324934380 ps
CPU time 32.24 seconds
Started Jun 23 05:37:55 PM PDT 24
Finished Jun 23 05:38:28 PM PDT 24
Peak memory 217008 kb
Host smart-5a158b33-169c-4026-bc66-ba6ed6b38041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807025526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.807025526
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.40529207
Short name T219
Test name
Test status
Simulation time 40640417734 ps
CPU time 100.19 seconds
Started Jun 23 05:37:52 PM PDT 24
Finished Jun 23 05:39:32 PM PDT 24
Peak memory 219752 kb
Host smart-55dd9590-182c-4762-b899-f26556bf82b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40529207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 25.rom_ctrl_stress_all.40529207
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1688888081
Short name T182
Test name
Test status
Simulation time 17703086661 ps
CPU time 29.61 seconds
Started Jun 23 05:37:53 PM PDT 24
Finished Jun 23 05:38:23 PM PDT 24
Peak memory 217476 kb
Host smart-2e7eb78c-9b4b-4124-9282-bc029fd69513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688888081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1688888081
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4051868010
Short name T134
Test name
Test status
Simulation time 6433972340 ps
CPU time 57.03 seconds
Started Jun 23 05:37:53 PM PDT 24
Finished Jun 23 05:38:51 PM PDT 24
Peak memory 219300 kb
Host smart-1f38251d-1ee7-433b-ac1c-d479b7b7851d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051868010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4051868010
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.479424092
Short name T172
Test name
Test status
Simulation time 182653419 ps
CPU time 10.7 seconds
Started Jun 23 05:37:52 PM PDT 24
Finished Jun 23 05:38:04 PM PDT 24
Peak memory 219312 kb
Host smart-a41f8b89-4bf8-4b00-899b-6f5c162f7208
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=479424092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.479424092
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.4279619370
Short name T75
Test name
Test status
Simulation time 1832753341 ps
CPU time 33.52 seconds
Started Jun 23 05:37:51 PM PDT 24
Finished Jun 23 05:38:25 PM PDT 24
Peak memory 216720 kb
Host smart-21fc6617-2b2e-4637-af78-2fc8dcec46c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279619370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.4279619370
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1086942113
Short name T216
Test name
Test status
Simulation time 347208712 ps
CPU time 19.72 seconds
Started Jun 23 05:37:56 PM PDT 24
Finished Jun 23 05:38:16 PM PDT 24
Peak memory 217220 kb
Host smart-85829e70-b9e6-4c2d-ad9d-cac54b1dfa1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086942113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1086942113
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2360960791
Short name T13
Test name
Test status
Simulation time 123682281762 ps
CPU time 2510.92 seconds
Started Jun 23 05:37:52 PM PDT 24
Finished Jun 23 06:19:43 PM PDT 24
Peak memory 235776 kb
Host smart-33bfa996-0d85-49a5-8043-7c974aaf4175
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360960791 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.2360960791
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.925375725
Short name T154
Test name
Test status
Simulation time 17400348228 ps
CPU time 31.81 seconds
Started Jun 23 05:37:50 PM PDT 24
Finished Jun 23 05:38:23 PM PDT 24
Peak memory 217352 kb
Host smart-62afbc4e-f6ba-418c-8d9d-505f5b9fb5e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925375725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.925375725
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.397090973
Short name T285
Test name
Test status
Simulation time 890353388111 ps
CPU time 497.79 seconds
Started Jun 23 05:37:55 PM PDT 24
Finished Jun 23 05:46:13 PM PDT 24
Peak memory 228628 kb
Host smart-d2c16afd-f2da-49a6-a4ea-5516723e924c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397090973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.397090973
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.4255163453
Short name T160
Test name
Test status
Simulation time 3308504392 ps
CPU time 40.87 seconds
Started Jun 23 05:37:51 PM PDT 24
Finished Jun 23 05:38:32 PM PDT 24
Peak memory 219300 kb
Host smart-4ac14280-750e-4657-9562-7e673631355f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255163453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.4255163453
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.885248898
Short name T323
Test name
Test status
Simulation time 37946857713 ps
CPU time 28.45 seconds
Started Jun 23 05:37:54 PM PDT 24
Finished Jun 23 05:38:23 PM PDT 24
Peak memory 217600 kb
Host smart-1f0e8ede-fcfb-4748-815f-dea9b422af85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=885248898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.885248898
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3162901629
Short name T310
Test name
Test status
Simulation time 13508287520 ps
CPU time 46.04 seconds
Started Jun 23 05:37:52 PM PDT 24
Finished Jun 23 05:38:39 PM PDT 24
Peak memory 216860 kb
Host smart-39388950-b23d-476f-bd56-0cdfa567d862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162901629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3162901629
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.516743876
Short name T174
Test name
Test status
Simulation time 2069314931 ps
CPU time 54.93 seconds
Started Jun 23 05:37:57 PM PDT 24
Finished Jun 23 05:38:52 PM PDT 24
Peak memory 219268 kb
Host smart-0b5c9397-1e48-4c4d-87b2-26831113b3e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516743876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.516743876
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.803155144
Short name T227
Test name
Test status
Simulation time 2214399998 ps
CPU time 22.12 seconds
Started Jun 23 05:37:52 PM PDT 24
Finished Jun 23 05:38:15 PM PDT 24
Peak memory 217200 kb
Host smart-f3341f0b-5281-4838-a676-f066d61ba001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803155144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.803155144
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1921977906
Short name T296
Test name
Test status
Simulation time 6471952185 ps
CPU time 237.32 seconds
Started Jun 23 05:37:54 PM PDT 24
Finished Jun 23 05:41:52 PM PDT 24
Peak memory 233572 kb
Host smart-2903e84e-90fe-4366-9451-fe3e5d5977de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921977906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1921977906
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3294156784
Short name T275
Test name
Test status
Simulation time 719545117 ps
CPU time 19.88 seconds
Started Jun 23 05:37:52 PM PDT 24
Finished Jun 23 05:38:12 PM PDT 24
Peak memory 219184 kb
Host smart-6abde1c9-1b03-4011-a5f6-89cacd17b420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294156784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3294156784
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2473007311
Short name T336
Test name
Test status
Simulation time 178692283 ps
CPU time 10.8 seconds
Started Jun 23 05:37:55 PM PDT 24
Finished Jun 23 05:38:07 PM PDT 24
Peak memory 219312 kb
Host smart-145c2847-b71f-4329-b683-4cb995ed2d3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2473007311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2473007311
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1276950851
Short name T149
Test name
Test status
Simulation time 21294605920 ps
CPU time 49.11 seconds
Started Jun 23 05:37:52 PM PDT 24
Finished Jun 23 05:38:41 PM PDT 24
Peak memory 216072 kb
Host smart-c2f345c1-1948-4829-a012-1e481db8a4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276950851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1276950851
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3176392014
Short name T146
Test name
Test status
Simulation time 13972214815 ps
CPU time 105.99 seconds
Started Jun 23 05:37:53 PM PDT 24
Finished Jun 23 05:39:40 PM PDT 24
Peak memory 221416 kb
Host smart-0eecf7c4-3dd9-438d-93c3-a569d1cafe0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176392014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3176392014
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.4221754590
Short name T167
Test name
Test status
Simulation time 4015636259 ps
CPU time 32.16 seconds
Started Jun 23 05:37:58 PM PDT 24
Finished Jun 23 05:38:30 PM PDT 24
Peak memory 216948 kb
Host smart-eb4b5d96-c561-43ec-8cec-f369d73acdaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221754590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.4221754590
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1326608721
Short name T345
Test name
Test status
Simulation time 1427881318 ps
CPU time 97.83 seconds
Started Jun 23 05:37:53 PM PDT 24
Finished Jun 23 05:39:31 PM PDT 24
Peak memory 241768 kb
Host smart-249b3679-00f2-4652-b863-3039ec290823
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326608721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1326608721
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3937996119
Short name T242
Test name
Test status
Simulation time 112339085117 ps
CPU time 60.93 seconds
Started Jun 23 05:37:52 PM PDT 24
Finished Jun 23 05:38:54 PM PDT 24
Peak memory 219324 kb
Host smart-13e28245-d3a1-4a60-b336-b37ae4ab56b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937996119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3937996119
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3073547039
Short name T325
Test name
Test status
Simulation time 614275541 ps
CPU time 14.88 seconds
Started Jun 23 05:37:54 PM PDT 24
Finished Jun 23 05:38:10 PM PDT 24
Peak memory 211284 kb
Host smart-22832647-d3c3-4da9-83dd-3ab198a714e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3073547039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3073547039
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2395979327
Short name T300
Test name
Test status
Simulation time 695871312 ps
CPU time 20.24 seconds
Started Jun 23 05:37:53 PM PDT 24
Finished Jun 23 05:38:14 PM PDT 24
Peak memory 217036 kb
Host smart-7275c4a1-d4b0-42a6-95e9-739291f8d7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395979327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2395979327
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3041003615
Short name T81
Test name
Test status
Simulation time 50243211642 ps
CPU time 219.31 seconds
Started Jun 23 05:37:54 PM PDT 24
Finished Jun 23 05:41:34 PM PDT 24
Peak memory 227556 kb
Host smart-656941ab-b66f-423a-bc08-2d8a930576f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041003615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3041003615
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1802673538
Short name T337
Test name
Test status
Simulation time 17805474164 ps
CPU time 33.13 seconds
Started Jun 23 05:37:20 PM PDT 24
Finished Jun 23 05:37:54 PM PDT 24
Peak memory 217472 kb
Host smart-4efcbd83-7561-411c-9c91-f4cfdaa5bda1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802673538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1802673538
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2501533009
Short name T250
Test name
Test status
Simulation time 109212466814 ps
CPU time 703.71 seconds
Started Jun 23 05:37:29 PM PDT 24
Finished Jun 23 05:49:13 PM PDT 24
Peak memory 237172 kb
Host smart-cdcb346b-a56b-4855-93d7-ef9f44630007
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501533009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2501533009
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3966477848
Short name T220
Test name
Test status
Simulation time 4087510020 ps
CPU time 29.13 seconds
Started Jun 23 05:37:19 PM PDT 24
Finished Jun 23 05:37:48 PM PDT 24
Peak memory 218540 kb
Host smart-e5a45c2c-8849-4b92-9662-c0024c2336b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966477848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3966477848
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3268953848
Short name T95
Test name
Test status
Simulation time 13787741495 ps
CPU time 30.03 seconds
Started Jun 23 05:37:19 PM PDT 24
Finished Jun 23 05:37:50 PM PDT 24
Peak memory 219376 kb
Host smart-0d6bce7d-cccc-46bd-aec2-f07861d55b92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3268953848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3268953848
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1138527597
Short name T20
Test name
Test status
Simulation time 15378964350 ps
CPU time 246.74 seconds
Started Jun 23 05:37:18 PM PDT 24
Finished Jun 23 05:41:25 PM PDT 24
Peak memory 235872 kb
Host smart-d53190cd-2f45-4a80-a5ff-5d7130284040
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138527597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1138527597
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3155407854
Short name T171
Test name
Test status
Simulation time 3097138597 ps
CPU time 40.94 seconds
Started Jun 23 05:37:18 PM PDT 24
Finished Jun 23 05:38:00 PM PDT 24
Peak memory 216276 kb
Host smart-ba2f2ff7-242e-4a8b-b229-7bff8cffc146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155407854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3155407854
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.247707439
Short name T29
Test name
Test status
Simulation time 710506939 ps
CPU time 39.12 seconds
Started Jun 23 05:37:19 PM PDT 24
Finished Jun 23 05:37:59 PM PDT 24
Peak memory 219276 kb
Host smart-3893ebab-59d1-440e-b58f-ad19266cd6d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247707439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.247707439
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1449709065
Short name T304
Test name
Test status
Simulation time 3234035318 ps
CPU time 18.37 seconds
Started Jun 23 05:38:00 PM PDT 24
Finished Jun 23 05:38:19 PM PDT 24
Peak memory 217180 kb
Host smart-326d9dde-acaf-4a3f-a481-c105ea61bd2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449709065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1449709065
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3505248033
Short name T209
Test name
Test status
Simulation time 165189197449 ps
CPU time 861.14 seconds
Started Jun 23 05:37:54 PM PDT 24
Finished Jun 23 05:52:16 PM PDT 24
Peak memory 233588 kb
Host smart-e806427f-42e4-4be7-b282-35942ad965df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505248033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3505248033
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3198262628
Short name T274
Test name
Test status
Simulation time 1563401511 ps
CPU time 28.13 seconds
Started Jun 23 05:37:56 PM PDT 24
Finished Jun 23 05:38:25 PM PDT 24
Peak memory 218528 kb
Host smart-459e92e1-0531-4bee-bfec-6e2d496fb349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198262628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3198262628
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2653535868
Short name T329
Test name
Test status
Simulation time 1812408204 ps
CPU time 21.16 seconds
Started Jun 23 05:37:58 PM PDT 24
Finished Jun 23 05:38:20 PM PDT 24
Peak memory 219320 kb
Host smart-b9baa1b5-3ec3-418e-8197-11ae3fc1c7f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2653535868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2653535868
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1151415522
Short name T231
Test name
Test status
Simulation time 38672905952 ps
CPU time 73.46 seconds
Started Jun 23 05:37:57 PM PDT 24
Finished Jun 23 05:39:10 PM PDT 24
Peak memory 216696 kb
Host smart-a31106e3-aa85-433d-9dec-0518d1480b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151415522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1151415522
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.9153492
Short name T212
Test name
Test status
Simulation time 22063730286 ps
CPU time 87.58 seconds
Started Jun 23 05:38:00 PM PDT 24
Finished Jun 23 05:39:28 PM PDT 24
Peak memory 219308 kb
Host smart-f5f9c9ff-97e8-4b99-b14a-4cab5521ea56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9153492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.rom_ctrl_stress_all.9153492
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2164026865
Short name T187
Test name
Test status
Simulation time 16117394234 ps
CPU time 32.7 seconds
Started Jun 23 05:37:55 PM PDT 24
Finished Jun 23 05:38:28 PM PDT 24
Peak memory 217372 kb
Host smart-9a8f9e54-97d2-4073-a9e2-395518baf4ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164026865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2164026865
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3556537765
Short name T342
Test name
Test status
Simulation time 24384846567 ps
CPU time 177.86 seconds
Started Jun 23 05:37:54 PM PDT 24
Finished Jun 23 05:40:53 PM PDT 24
Peak memory 239452 kb
Host smart-09604142-f9ab-476f-91e6-f584a1fcf653
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556537765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3556537765
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1072583735
Short name T175
Test name
Test status
Simulation time 8083351805 ps
CPU time 64.48 seconds
Started Jun 23 05:38:00 PM PDT 24
Finished Jun 23 05:39:05 PM PDT 24
Peak memory 219276 kb
Host smart-c7115f1b-da92-4e23-81e4-4482619ac841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072583735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1072583735
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.530691202
Short name T332
Test name
Test status
Simulation time 6828635881 ps
CPU time 20.3 seconds
Started Jun 23 05:37:54 PM PDT 24
Finished Jun 23 05:38:15 PM PDT 24
Peak memory 219372 kb
Host smart-432230b2-15b5-4d2b-be70-e9e948812e00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=530691202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.530691202
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1057761458
Short name T335
Test name
Test status
Simulation time 5323448456 ps
CPU time 56.48 seconds
Started Jun 23 05:37:58 PM PDT 24
Finished Jun 23 05:38:54 PM PDT 24
Peak memory 216516 kb
Host smart-c2fb7e8b-153b-4bdf-b608-96fb61fdfecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057761458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1057761458
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3189979546
Short name T98
Test name
Test status
Simulation time 35574950972 ps
CPU time 77.17 seconds
Started Jun 23 05:37:54 PM PDT 24
Finished Jun 23 05:39:12 PM PDT 24
Peak memory 219252 kb
Host smart-b39830ef-de75-4476-8372-1e91adddff32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189979546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3189979546
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1895125365
Short name T234
Test name
Test status
Simulation time 3505634962 ps
CPU time 17.59 seconds
Started Jun 23 05:38:07 PM PDT 24
Finished Jun 23 05:38:25 PM PDT 24
Peak memory 217120 kb
Host smart-d29e3931-3aed-4f2d-8eda-9acc9475c427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895125365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1895125365
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1986962251
Short name T39
Test name
Test status
Simulation time 3873690810 ps
CPU time 324.92 seconds
Started Jun 23 05:38:00 PM PDT 24
Finished Jun 23 05:43:26 PM PDT 24
Peak memory 237784 kb
Host smart-b886d385-7326-4c0e-97de-6b8db9dd4f4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986962251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1986962251
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3275082742
Short name T307
Test name
Test status
Simulation time 31284147922 ps
CPU time 60.66 seconds
Started Jun 23 05:38:06 PM PDT 24
Finished Jun 23 05:39:07 PM PDT 24
Peak memory 219188 kb
Host smart-7aa5a268-3f40-4e28-8624-5f0287377d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275082742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3275082742
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.997377836
Short name T140
Test name
Test status
Simulation time 3929773976 ps
CPU time 31.33 seconds
Started Jun 23 05:37:59 PM PDT 24
Finished Jun 23 05:38:30 PM PDT 24
Peak memory 219432 kb
Host smart-47879347-8ee7-4ea7-82bf-5ae4fc139e93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=997377836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.997377836
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1225380249
Short name T192
Test name
Test status
Simulation time 9685068736 ps
CPU time 46.77 seconds
Started Jun 23 05:38:00 PM PDT 24
Finished Jun 23 05:38:47 PM PDT 24
Peak memory 217108 kb
Host smart-f505e5c7-1219-4ce5-96cd-95d4235167eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225380249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1225380249
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3681143323
Short name T303
Test name
Test status
Simulation time 19920882737 ps
CPU time 100.42 seconds
Started Jun 23 05:37:59 PM PDT 24
Finished Jun 23 05:39:39 PM PDT 24
Peak memory 219356 kb
Host smart-24148e1e-ea6a-4ad3-adbe-d8b5a8ae487c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681143323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3681143323
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1816701094
Short name T255
Test name
Test status
Simulation time 1318614901 ps
CPU time 13.24 seconds
Started Jun 23 05:38:14 PM PDT 24
Finished Jun 23 05:38:28 PM PDT 24
Peak memory 217096 kb
Host smart-79de3af4-598d-460e-a58c-5cc8b9147797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816701094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1816701094
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.811416648
Short name T51
Test name
Test status
Simulation time 100011065022 ps
CPU time 267.63 seconds
Started Jun 23 05:38:07 PM PDT 24
Finished Jun 23 05:42:35 PM PDT 24
Peak memory 218208 kb
Host smart-203112f3-3c37-46a9-b8bc-e1eb09eb81cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811416648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.811416648
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2846275575
Short name T350
Test name
Test status
Simulation time 24724953212 ps
CPU time 55.34 seconds
Started Jun 23 05:38:13 PM PDT 24
Finished Jun 23 05:39:09 PM PDT 24
Peak memory 219336 kb
Host smart-5ba3b485-1300-4ec0-aa0b-0cfde069e0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846275575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2846275575
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2784212741
Short name T144
Test name
Test status
Simulation time 1768604204 ps
CPU time 12.63 seconds
Started Jun 23 05:38:06 PM PDT 24
Finished Jun 23 05:38:19 PM PDT 24
Peak memory 218796 kb
Host smart-c4a8f1ac-6a06-4d8e-8a5f-2a1fe2986113
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2784212741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2784212741
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2271644143
Short name T193
Test name
Test status
Simulation time 1689202312 ps
CPU time 19.44 seconds
Started Jun 23 05:38:09 PM PDT 24
Finished Jun 23 05:38:29 PM PDT 24
Peak memory 216928 kb
Host smart-ae0429e5-e5da-4628-a2d6-c7dc333767dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271644143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2271644143
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2936959466
Short name T277
Test name
Test status
Simulation time 9552983207 ps
CPU time 80.87 seconds
Started Jun 23 05:38:06 PM PDT 24
Finished Jun 23 05:39:27 PM PDT 24
Peak memory 219300 kb
Host smart-ffd56ec8-e307-40c9-bf04-002f0a0afa2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936959466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2936959466
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2156504539
Short name T202
Test name
Test status
Simulation time 425289872 ps
CPU time 11.22 seconds
Started Jun 23 05:38:17 PM PDT 24
Finished Jun 23 05:38:29 PM PDT 24
Peak memory 217052 kb
Host smart-5b0b8d20-2dc7-4f15-bf55-345d269cfc36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156504539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2156504539
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.303567956
Short name T17
Test name
Test status
Simulation time 16156054748 ps
CPU time 245.19 seconds
Started Jun 23 05:38:13 PM PDT 24
Finished Jun 23 05:42:18 PM PDT 24
Peak memory 219612 kb
Host smart-c69bc701-c31a-4ef0-b258-0b61e07aa7fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303567956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.303567956
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.802408740
Short name T48
Test name
Test status
Simulation time 4726826772 ps
CPU time 41.18 seconds
Started Jun 23 05:38:12 PM PDT 24
Finished Jun 23 05:38:54 PM PDT 24
Peak memory 219280 kb
Host smart-fd53ed3a-5471-488f-b394-053750d28558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802408740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.802408740
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3355980578
Short name T265
Test name
Test status
Simulation time 184897807 ps
CPU time 10.72 seconds
Started Jun 23 05:38:11 PM PDT 24
Finished Jun 23 05:38:22 PM PDT 24
Peak memory 219312 kb
Host smart-c2285b9c-00c0-4cf6-90a1-a0f77c1233f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3355980578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3355980578
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2172801465
Short name T129
Test name
Test status
Simulation time 8896813356 ps
CPU time 69.32 seconds
Started Jun 23 05:38:11 PM PDT 24
Finished Jun 23 05:39:21 PM PDT 24
Peak memory 216816 kb
Host smart-e02d2a70-c348-4e6e-bdcc-f557f18486fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172801465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2172801465
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3516939373
Short name T131
Test name
Test status
Simulation time 11836057483 ps
CPU time 35.6 seconds
Started Jun 23 05:38:12 PM PDT 24
Finished Jun 23 05:38:48 PM PDT 24
Peak memory 219204 kb
Host smart-9378a1e5-9976-4fa2-b95f-a5df4917431f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516939373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3516939373
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2676495735
Short name T184
Test name
Test status
Simulation time 8560608924 ps
CPU time 22.81 seconds
Started Jun 23 05:38:16 PM PDT 24
Finished Jun 23 05:38:40 PM PDT 24
Peak memory 216976 kb
Host smart-776c1c50-2a6a-4c56-be77-b885a265706f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676495735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2676495735
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.945321726
Short name T239
Test name
Test status
Simulation time 3129321645 ps
CPU time 232.8 seconds
Started Jun 23 05:38:16 PM PDT 24
Finished Jun 23 05:42:09 PM PDT 24
Peak memory 225364 kb
Host smart-948e86f7-d5cf-44c6-8d02-71e70866f929
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945321726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.945321726
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3116489909
Short name T44
Test name
Test status
Simulation time 41775246149 ps
CPU time 68.56 seconds
Started Jun 23 05:38:16 PM PDT 24
Finished Jun 23 05:39:25 PM PDT 24
Peak memory 219224 kb
Host smart-251c71cc-dcae-4a5c-a11d-e468df05f7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116489909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3116489909
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.389524011
Short name T46
Test name
Test status
Simulation time 34542606210 ps
CPU time 30.3 seconds
Started Jun 23 05:38:16 PM PDT 24
Finished Jun 23 05:38:46 PM PDT 24
Peak memory 217656 kb
Host smart-9b20632e-523e-485e-b73a-f2fe90bea456
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=389524011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.389524011
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2259570901
Short name T232
Test name
Test status
Simulation time 30272769691 ps
CPU time 65.84 seconds
Started Jun 23 05:38:17 PM PDT 24
Finished Jun 23 05:39:24 PM PDT 24
Peak memory 217188 kb
Host smart-862ee76f-6173-4065-aaf6-b55898e7c7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259570901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2259570901
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1814785931
Short name T178
Test name
Test status
Simulation time 848129258 ps
CPU time 40.03 seconds
Started Jun 23 05:38:18 PM PDT 24
Finished Jun 23 05:38:59 PM PDT 24
Peak memory 219292 kb
Host smart-76066d5a-329d-4d1c-946e-7e260f2ab545
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814785931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1814785931
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2258858143
Short name T223
Test name
Test status
Simulation time 3518759162 ps
CPU time 27.3 seconds
Started Jun 23 05:38:20 PM PDT 24
Finished Jun 23 05:38:47 PM PDT 24
Peak memory 217200 kb
Host smart-bc8b2880-8754-4b3c-a850-3e12054c436c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258858143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2258858143
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3643580611
Short name T210
Test name
Test status
Simulation time 108621284252 ps
CPU time 307.27 seconds
Started Jun 23 05:38:26 PM PDT 24
Finished Jun 23 05:43:34 PM PDT 24
Peak memory 238176 kb
Host smart-69be45cc-6bfc-4cbc-b934-6baa717c6d04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643580611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3643580611
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1383393658
Short name T361
Test name
Test status
Simulation time 8465490913 ps
CPU time 53.88 seconds
Started Jun 23 05:38:20 PM PDT 24
Finished Jun 23 05:39:14 PM PDT 24
Peak memory 219248 kb
Host smart-b86389ef-870c-44ec-b14e-532c90b4cb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383393658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1383393658
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3102650428
Short name T313
Test name
Test status
Simulation time 783196998 ps
CPU time 15.41 seconds
Started Jun 23 05:38:21 PM PDT 24
Finished Jun 23 05:38:37 PM PDT 24
Peak memory 219336 kb
Host smart-764af3a1-825c-41c9-ad70-9be818f7940e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3102650428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3102650428
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.124289066
Short name T317
Test name
Test status
Simulation time 28824279905 ps
CPU time 64.43 seconds
Started Jun 23 05:38:14 PM PDT 24
Finished Jun 23 05:39:19 PM PDT 24
Peak memory 217248 kb
Host smart-460e332b-6a5f-4784-bed4-134c029a0bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124289066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.124289066
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1845193444
Short name T206
Test name
Test status
Simulation time 33227647042 ps
CPU time 82.58 seconds
Started Jun 23 05:38:17 PM PDT 24
Finished Jun 23 05:39:40 PM PDT 24
Peak memory 227528 kb
Host smart-ebae485e-f17f-4c6d-b41d-c26292c08cf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845193444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1845193444
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2997767414
Short name T319
Test name
Test status
Simulation time 167572736 ps
CPU time 8.51 seconds
Started Jun 23 05:38:26 PM PDT 24
Finished Jun 23 05:38:34 PM PDT 24
Peak memory 216920 kb
Host smart-bec86c2b-01b3-45b0-83c5-54cf0cd60f10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997767414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2997767414
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3101870111
Short name T270
Test name
Test status
Simulation time 2201502261 ps
CPU time 19.65 seconds
Started Jun 23 05:38:25 PM PDT 24
Finished Jun 23 05:38:45 PM PDT 24
Peak memory 219192 kb
Host smart-b6b7023f-0cf2-4277-8c67-fa0c352dc8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101870111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3101870111
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2900373673
Short name T282
Test name
Test status
Simulation time 2350010222 ps
CPU time 23.29 seconds
Started Jun 23 05:38:22 PM PDT 24
Finished Jun 23 05:38:45 PM PDT 24
Peak memory 211368 kb
Host smart-0f022c43-661b-4f42-bdf1-8da5be9c2c27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2900373673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2900373673
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3041919479
Short name T252
Test name
Test status
Simulation time 56655076168 ps
CPU time 49.81 seconds
Started Jun 23 05:38:21 PM PDT 24
Finished Jun 23 05:39:11 PM PDT 24
Peak memory 217212 kb
Host smart-3563d8e6-5c7d-4b6a-a0f5-a12d9100600f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041919479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3041919479
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2898807635
Short name T76
Test name
Test status
Simulation time 13499092291 ps
CPU time 84.24 seconds
Started Jun 23 05:38:20 PM PDT 24
Finished Jun 23 05:39:45 PM PDT 24
Peak memory 219356 kb
Host smart-a3dc734a-954f-4373-befb-dd1d447579d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898807635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2898807635
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2347440466
Short name T8
Test name
Test status
Simulation time 695478842 ps
CPU time 12.84 seconds
Started Jun 23 05:38:24 PM PDT 24
Finished Jun 23 05:38:38 PM PDT 24
Peak memory 217056 kb
Host smart-a861d889-69a1-4d7d-885d-a0c52c103680
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347440466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2347440466
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.836072923
Short name T28
Test name
Test status
Simulation time 4103046120 ps
CPU time 295.09 seconds
Started Jun 23 05:38:26 PM PDT 24
Finished Jun 23 05:43:21 PM PDT 24
Peak memory 234444 kb
Host smart-2e677b24-52b2-469b-9416-fbee05645b69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836072923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.836072923
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3879806007
Short name T158
Test name
Test status
Simulation time 502251599 ps
CPU time 19.75 seconds
Started Jun 23 05:38:24 PM PDT 24
Finished Jun 23 05:38:44 PM PDT 24
Peak memory 219268 kb
Host smart-5647674e-99c9-4119-b808-ff3b35f75beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879806007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3879806007
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.579163666
Short name T204
Test name
Test status
Simulation time 1743393604 ps
CPU time 13.62 seconds
Started Jun 23 05:38:24 PM PDT 24
Finished Jun 23 05:38:37 PM PDT 24
Peak memory 211136 kb
Host smart-0c055677-eca0-4a89-92c5-2a1615114852
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=579163666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.579163666
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1613050490
Short name T176
Test name
Test status
Simulation time 3610027477 ps
CPU time 25.94 seconds
Started Jun 23 05:38:26 PM PDT 24
Finished Jun 23 05:38:52 PM PDT 24
Peak memory 216636 kb
Host smart-931a1e78-96e6-4ce4-b271-03b912f78c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613050490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1613050490
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3505186829
Short name T330
Test name
Test status
Simulation time 548970178 ps
CPU time 36.89 seconds
Started Jun 23 05:38:24 PM PDT 24
Finished Jun 23 05:39:01 PM PDT 24
Peak memory 219384 kb
Host smart-c45e6cd4-9d0c-4e27-9b51-42c346530b2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505186829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3505186829
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2054370248
Short name T100
Test name
Test status
Simulation time 4795154179 ps
CPU time 16.97 seconds
Started Jun 23 05:38:31 PM PDT 24
Finished Jun 23 05:38:48 PM PDT 24
Peak memory 217276 kb
Host smart-dced5c04-ee49-48d8-91cf-5dd2a0c07d47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054370248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2054370248
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3136157506
Short name T132
Test name
Test status
Simulation time 14471534485 ps
CPU time 191.92 seconds
Started Jun 23 05:38:25 PM PDT 24
Finished Jun 23 05:41:37 PM PDT 24
Peak memory 237804 kb
Host smart-2b33a858-b3ee-4dc7-b259-16ff0f106405
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136157506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3136157506
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.849731998
Short name T316
Test name
Test status
Simulation time 74915938131 ps
CPU time 43.92 seconds
Started Jun 23 05:38:30 PM PDT 24
Finished Jun 23 05:39:15 PM PDT 24
Peak memory 219316 kb
Host smart-e9762a91-ba70-41b6-bac3-740310ab134b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849731998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.849731998
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.377690521
Short name T287
Test name
Test status
Simulation time 3113737919 ps
CPU time 28.53 seconds
Started Jun 23 05:38:23 PM PDT 24
Finished Jun 23 05:38:52 PM PDT 24
Peak memory 217756 kb
Host smart-595dbac0-f10d-407b-8477-4c4ca54bb805
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=377690521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.377690521
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.921804322
Short name T344
Test name
Test status
Simulation time 3282230109 ps
CPU time 40.21 seconds
Started Jun 23 05:38:26 PM PDT 24
Finished Jun 23 05:39:06 PM PDT 24
Peak memory 216908 kb
Host smart-7d3d5ba7-b047-4d89-9d89-4b0ca345ed94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921804322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.921804322
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2866060222
Short name T295
Test name
Test status
Simulation time 96201116120 ps
CPU time 147.91 seconds
Started Jun 23 05:38:25 PM PDT 24
Finished Jun 23 05:40:54 PM PDT 24
Peak memory 220664 kb
Host smart-59ba77a8-7f28-4a21-84e6-d66bbde1e0cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866060222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2866060222
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.531418886
Short name T328
Test name
Test status
Simulation time 917802233 ps
CPU time 10.37 seconds
Started Jun 23 05:37:26 PM PDT 24
Finished Jun 23 05:37:37 PM PDT 24
Peak memory 216988 kb
Host smart-208ff4ac-ef6e-4c6a-9e8f-a81a1cef459c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531418886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.531418886
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.903993784
Short name T320
Test name
Test status
Simulation time 51354961135 ps
CPU time 449.05 seconds
Started Jun 23 05:37:23 PM PDT 24
Finished Jun 23 05:44:52 PM PDT 24
Peak memory 217800 kb
Host smart-4284e29f-2355-4dfc-8224-bb45c929ae22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903993784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.903993784
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2859297247
Short name T30
Test name
Test status
Simulation time 9333598909 ps
CPU time 35.76 seconds
Started Jun 23 05:37:24 PM PDT 24
Finished Jun 23 05:38:00 PM PDT 24
Peak memory 219332 kb
Host smart-0f8d77a4-b49e-4b28-a6a1-c3422313a0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859297247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2859297247
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.751920077
Short name T197
Test name
Test status
Simulation time 62326044016 ps
CPU time 31.27 seconds
Started Jun 23 05:37:21 PM PDT 24
Finished Jun 23 05:37:53 PM PDT 24
Peak memory 219408 kb
Host smart-72a33c5c-67e3-4211-8a41-cc0e216d0963
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=751920077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.751920077
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.394542520
Short name T21
Test name
Test status
Simulation time 3255872911 ps
CPU time 230.44 seconds
Started Jun 23 05:37:24 PM PDT 24
Finished Jun 23 05:41:15 PM PDT 24
Peak memory 234856 kb
Host smart-f316d5f1-03de-40f0-8780-8fd9068bd1d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394542520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.394542520
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3279998953
Short name T161
Test name
Test status
Simulation time 31038747598 ps
CPU time 86.19 seconds
Started Jun 23 05:37:22 PM PDT 24
Finished Jun 23 05:38:48 PM PDT 24
Peak memory 216944 kb
Host smart-b1b2b606-4078-4068-bbc9-e23dee6a74d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279998953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3279998953
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1026117961
Short name T113
Test name
Test status
Simulation time 1554459424 ps
CPU time 24.45 seconds
Started Jun 23 05:37:22 PM PDT 24
Finished Jun 23 05:37:46 PM PDT 24
Peak memory 219264 kb
Host smart-5fdc696d-291d-4fce-a384-e7991e84f672
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026117961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1026117961
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.660399152
Short name T163
Test name
Test status
Simulation time 172571234 ps
CPU time 8.41 seconds
Started Jun 23 05:38:32 PM PDT 24
Finished Jun 23 05:38:41 PM PDT 24
Peak memory 216368 kb
Host smart-d4bca5b9-50f0-4648-b347-d6e928a5b0b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660399152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.660399152
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.221694000
Short name T35
Test name
Test status
Simulation time 119986822923 ps
CPU time 946.62 seconds
Started Jun 23 05:38:31 PM PDT 24
Finished Jun 23 05:54:18 PM PDT 24
Peak memory 214672 kb
Host smart-7f93b0ab-4f7b-411e-9340-e464f94b8d2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221694000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.221694000
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2677608966
Short name T130
Test name
Test status
Simulation time 1169688728 ps
CPU time 27.35 seconds
Started Jun 23 05:38:29 PM PDT 24
Finished Jun 23 05:38:57 PM PDT 24
Peak memory 219200 kb
Host smart-31817ec5-8fb4-4b90-b01f-984d79d4c495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677608966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2677608966
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2941767213
Short name T143
Test name
Test status
Simulation time 3968392006 ps
CPU time 33.55 seconds
Started Jun 23 05:38:30 PM PDT 24
Finished Jun 23 05:39:04 PM PDT 24
Peak memory 219572 kb
Host smart-9dd1e126-2287-4865-b21a-3d9ef725d949
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2941767213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2941767213
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1885572474
Short name T324
Test name
Test status
Simulation time 2149881884 ps
CPU time 36.39 seconds
Started Jun 23 05:38:29 PM PDT 24
Finished Jun 23 05:39:06 PM PDT 24
Peak memory 216020 kb
Host smart-d020ef97-ccbf-4a80-a5eb-3bd465ee589f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885572474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1885572474
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2508967115
Short name T196
Test name
Test status
Simulation time 12292599521 ps
CPU time 32.6 seconds
Started Jun 23 05:38:30 PM PDT 24
Finished Jun 23 05:39:02 PM PDT 24
Peak memory 219216 kb
Host smart-1a5c417c-768a-4f64-b83e-a0c010f27471
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508967115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2508967115
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.4026871704
Short name T94
Test name
Test status
Simulation time 167583642 ps
CPU time 8.36 seconds
Started Jun 23 05:38:34 PM PDT 24
Finished Jun 23 05:38:43 PM PDT 24
Peak memory 216996 kb
Host smart-c7d95703-76b8-436c-83fa-cc3618b5912a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026871704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.4026871704
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2922733774
Short name T114
Test name
Test status
Simulation time 9353024920 ps
CPU time 180.5 seconds
Started Jun 23 05:38:31 PM PDT 24
Finished Jun 23 05:41:32 PM PDT 24
Peak memory 240476 kb
Host smart-a99a58c9-e361-4ba3-b445-be1aad1550a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922733774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2922733774
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3683554985
Short name T208
Test name
Test status
Simulation time 36358807432 ps
CPU time 67.49 seconds
Started Jun 23 05:38:32 PM PDT 24
Finished Jun 23 05:39:40 PM PDT 24
Peak memory 218724 kb
Host smart-2b32ed36-b026-45d1-95ad-49e87bc11ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683554985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3683554985
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.650769105
Short name T145
Test name
Test status
Simulation time 185167616 ps
CPU time 10.85 seconds
Started Jun 23 05:38:31 PM PDT 24
Finished Jun 23 05:38:43 PM PDT 24
Peak memory 218368 kb
Host smart-34ddb449-251e-4c9d-ad50-a13feb0e43e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=650769105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.650769105
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3741376243
Short name T278
Test name
Test status
Simulation time 10692732974 ps
CPU time 57.69 seconds
Started Jun 23 05:38:30 PM PDT 24
Finished Jun 23 05:39:29 PM PDT 24
Peak memory 216788 kb
Host smart-991e181f-7a06-4168-8836-ec57b9ed75b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741376243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3741376243
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2564164870
Short name T309
Test name
Test status
Simulation time 1458025641 ps
CPU time 40.01 seconds
Started Jun 23 05:38:31 PM PDT 24
Finished Jun 23 05:39:12 PM PDT 24
Peak memory 218340 kb
Host smart-515d0b88-4554-47bf-ba12-fdc8975ee2bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564164870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2564164870
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.326052176
Short name T294
Test name
Test status
Simulation time 685311383 ps
CPU time 13.06 seconds
Started Jun 23 05:38:33 PM PDT 24
Finished Jun 23 05:38:46 PM PDT 24
Peak memory 216996 kb
Host smart-d3560cf6-f715-447e-a0de-ff57abacddda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326052176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.326052176
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2748948546
Short name T340
Test name
Test status
Simulation time 768706093 ps
CPU time 19.44 seconds
Started Jun 23 05:38:35 PM PDT 24
Finished Jun 23 05:38:55 PM PDT 24
Peak memory 219240 kb
Host smart-18c4393b-2eab-48e3-bd09-fb0e5b6be768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748948546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2748948546
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1853994908
Short name T308
Test name
Test status
Simulation time 177229073 ps
CPU time 10.6 seconds
Started Jun 23 05:38:35 PM PDT 24
Finished Jun 23 05:38:46 PM PDT 24
Peak memory 219332 kb
Host smart-6662b6ab-6f25-4791-aaae-f3dbe64c7e81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1853994908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1853994908
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3651574788
Short name T185
Test name
Test status
Simulation time 2175332838 ps
CPU time 31.38 seconds
Started Jun 23 05:38:37 PM PDT 24
Finished Jun 23 05:39:08 PM PDT 24
Peak memory 215480 kb
Host smart-bb46f2eb-076f-44dc-9e95-044005a1700b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651574788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3651574788
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.715181240
Short name T27
Test name
Test status
Simulation time 2443149366 ps
CPU time 42.81 seconds
Started Jun 23 05:38:35 PM PDT 24
Finished Jun 23 05:39:18 PM PDT 24
Peak memory 219260 kb
Host smart-5703f813-c059-4e77-aeef-95f31099f60b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715181240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.715181240
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.486996674
Short name T157
Test name
Test status
Simulation time 6838935908 ps
CPU time 23.62 seconds
Started Jun 23 05:38:35 PM PDT 24
Finished Jun 23 05:38:59 PM PDT 24
Peak memory 217508 kb
Host smart-2d574528-27c8-4bc3-8f96-6008396f294b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486996674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.486996674
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4116187309
Short name T311
Test name
Test status
Simulation time 153098435530 ps
CPU time 757.85 seconds
Started Jun 23 05:38:35 PM PDT 24
Finished Jun 23 05:51:13 PM PDT 24
Peak memory 238864 kb
Host smart-6488b08f-2423-484e-b9e3-5419277def87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116187309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.4116187309
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.242071551
Short name T199
Test name
Test status
Simulation time 1180542212 ps
CPU time 19.48 seconds
Started Jun 23 05:38:35 PM PDT 24
Finished Jun 23 05:38:55 PM PDT 24
Peak memory 219288 kb
Host smart-339972fc-4dbf-4ce6-83d1-e4ee674f0aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242071551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.242071551
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2249133892
Short name T306
Test name
Test status
Simulation time 15655717755 ps
CPU time 30.31 seconds
Started Jun 23 05:38:37 PM PDT 24
Finished Jun 23 05:39:08 PM PDT 24
Peak memory 211628 kb
Host smart-cef16741-3620-40e9-b9da-b92c0ca5f78e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2249133892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2249133892
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2365119143
Short name T225
Test name
Test status
Simulation time 5038424567 ps
CPU time 39.48 seconds
Started Jun 23 05:38:37 PM PDT 24
Finished Jun 23 05:39:17 PM PDT 24
Peak memory 216364 kb
Host smart-f00c3ff8-1696-436b-bda4-3edcdab7603d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365119143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2365119143
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.504303909
Short name T341
Test name
Test status
Simulation time 8802270553 ps
CPU time 63.68 seconds
Started Jun 23 05:38:38 PM PDT 24
Finished Jun 23 05:39:42 PM PDT 24
Peak memory 219432 kb
Host smart-03465459-2348-4dc0-a225-5037902c44c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504303909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.504303909
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1186260327
Short name T189
Test name
Test status
Simulation time 768882123 ps
CPU time 13.54 seconds
Started Jun 23 05:38:37 PM PDT 24
Finished Jun 23 05:38:51 PM PDT 24
Peak memory 217136 kb
Host smart-8c0fe97f-340c-40b7-8b2b-258a4afb2018
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186260327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1186260327
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.294062893
Short name T101
Test name
Test status
Simulation time 11885907002 ps
CPU time 294.25 seconds
Started Jun 23 05:38:38 PM PDT 24
Finished Jun 23 05:43:33 PM PDT 24
Peak memory 237632 kb
Host smart-9f8a5100-1415-41c9-88b6-7d89ddd41eea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294062893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.294062893
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2823581925
Short name T102
Test name
Test status
Simulation time 20144503744 ps
CPU time 47 seconds
Started Jun 23 05:38:35 PM PDT 24
Finished Jun 23 05:39:22 PM PDT 24
Peak memory 219256 kb
Host smart-5732c80c-6e19-4f08-8339-d785ffb57051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823581925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2823581925
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1402638457
Short name T233
Test name
Test status
Simulation time 1747272393 ps
CPU time 13.37 seconds
Started Jun 23 05:38:39 PM PDT 24
Finished Jun 23 05:38:53 PM PDT 24
Peak memory 218648 kb
Host smart-07e27071-04a1-4e7a-b115-4c35c18d272c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1402638457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1402638457
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3228882185
Short name T77
Test name
Test status
Simulation time 19951738156 ps
CPU time 52.97 seconds
Started Jun 23 05:38:36 PM PDT 24
Finished Jun 23 05:39:29 PM PDT 24
Peak memory 217520 kb
Host smart-eda2dfe6-53fd-4924-9c96-c86b9b190762
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228882185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3228882185
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1767211225
Short name T165
Test name
Test status
Simulation time 2640536899 ps
CPU time 24.59 seconds
Started Jun 23 05:38:43 PM PDT 24
Finished Jun 23 05:39:08 PM PDT 24
Peak memory 217148 kb
Host smart-e5afc2f1-f557-49ce-8bab-71afcae5031d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767211225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1767211225
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2255012572
Short name T226
Test name
Test status
Simulation time 31700328191 ps
CPU time 452.16 seconds
Started Jun 23 05:38:41 PM PDT 24
Finished Jun 23 05:46:13 PM PDT 24
Peak memory 219636 kb
Host smart-1f11401e-5c67-437a-a7c1-af4b176e7ea3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255012572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2255012572
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.734259981
Short name T218
Test name
Test status
Simulation time 1375151841 ps
CPU time 19.25 seconds
Started Jun 23 05:38:40 PM PDT 24
Finished Jun 23 05:39:00 PM PDT 24
Peak memory 219188 kb
Host smart-75e44518-b8af-4c65-857e-dc3c242bd81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734259981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.734259981
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1532966870
Short name T338
Test name
Test status
Simulation time 14752441433 ps
CPU time 27.63 seconds
Started Jun 23 05:38:39 PM PDT 24
Finished Jun 23 05:39:07 PM PDT 24
Peak memory 217636 kb
Host smart-3344e354-ca07-4b3a-9833-d884bf303644
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1532966870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1532966870
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.936968048
Short name T26
Test name
Test status
Simulation time 4629601428 ps
CPU time 47.12 seconds
Started Jun 23 05:38:34 PM PDT 24
Finished Jun 23 05:39:22 PM PDT 24
Peak memory 216808 kb
Host smart-3bab95f4-6beb-4771-b0e1-15c1d5536538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936968048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.936968048
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1017249512
Short name T343
Test name
Test status
Simulation time 6617329846 ps
CPU time 63.44 seconds
Started Jun 23 05:38:38 PM PDT 24
Finished Jun 23 05:39:42 PM PDT 24
Peak memory 217244 kb
Host smart-d8798fbf-6d5d-4d58-891b-6493c2a2ba8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017249512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1017249512
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.767159762
Short name T6
Test name
Test status
Simulation time 169069798 ps
CPU time 8.62 seconds
Started Jun 23 05:38:40 PM PDT 24
Finished Jun 23 05:38:49 PM PDT 24
Peak memory 216968 kb
Host smart-ae09c3d8-f3cc-48ec-8f88-ab36db86587c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767159762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.767159762
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4983924
Short name T36
Test name
Test status
Simulation time 24965058370 ps
CPU time 209.7 seconds
Started Jun 23 05:38:42 PM PDT 24
Finished Jun 23 05:42:12 PM PDT 24
Peak memory 236120 kb
Host smart-1aebb051-28bd-418f-9366-f1e44b3c5dd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4983924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_s
ig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_cor
rupt_sig_fatal_chk.4983924
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1601172448
Short name T283
Test name
Test status
Simulation time 1518606095 ps
CPU time 29.42 seconds
Started Jun 23 05:38:41 PM PDT 24
Finished Jun 23 05:39:11 PM PDT 24
Peak memory 219260 kb
Host smart-6847a679-feb4-42fc-88ee-ff4a0c58e3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601172448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1601172448
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.41608118
Short name T297
Test name
Test status
Simulation time 7523678451 ps
CPU time 21.39 seconds
Started Jun 23 05:38:41 PM PDT 24
Finished Jun 23 05:39:03 PM PDT 24
Peak memory 212020 kb
Host smart-5fa50c95-295b-4f5a-b001-603266c8e0f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=41608118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.41608118
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.555927298
Short name T292
Test name
Test status
Simulation time 24871718840 ps
CPU time 62.95 seconds
Started Jun 23 05:38:39 PM PDT 24
Finished Jun 23 05:39:43 PM PDT 24
Peak memory 215880 kb
Host smart-93dfb64e-1f2b-420a-b62c-dca302924fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555927298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.555927298
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3864219466
Short name T203
Test name
Test status
Simulation time 4522144099 ps
CPU time 61.13 seconds
Started Jun 23 05:38:39 PM PDT 24
Finished Jun 23 05:39:40 PM PDT 24
Peak memory 218928 kb
Host smart-c69fd45d-bb32-4b02-8546-369b234b0948
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864219466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3864219466
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3527897173
Short name T348
Test name
Test status
Simulation time 39780565972 ps
CPU time 26.96 seconds
Started Jun 23 05:38:46 PM PDT 24
Finished Jun 23 05:39:13 PM PDT 24
Peak memory 217400 kb
Host smart-4bdbf4fc-61af-4464-9290-b66c1c2642ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527897173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3527897173
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1512961292
Short name T322
Test name
Test status
Simulation time 32370558487 ps
CPU time 435.74 seconds
Started Jun 23 05:38:44 PM PDT 24
Finished Jun 23 05:46:00 PM PDT 24
Peak memory 217848 kb
Host smart-0cbd391b-b62d-40e4-a946-cc0b1d3c1a27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512961292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1512961292
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2894050074
Short name T177
Test name
Test status
Simulation time 33356644898 ps
CPU time 70.61 seconds
Started Jun 23 05:38:45 PM PDT 24
Finished Jun 23 05:39:56 PM PDT 24
Peak memory 219252 kb
Host smart-b2c9b20a-dcf4-4ed4-aef6-b1f7540ec50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894050074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2894050074
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2684957052
Short name T136
Test name
Test status
Simulation time 534908149 ps
CPU time 12.01 seconds
Started Jun 23 05:38:45 PM PDT 24
Finished Jun 23 05:38:57 PM PDT 24
Peak memory 217556 kb
Host smart-835d32cc-5eb0-43aa-acab-da11b6df332b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2684957052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2684957052
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.587276696
Short name T79
Test name
Test status
Simulation time 2043867381 ps
CPU time 29.15 seconds
Started Jun 23 05:38:46 PM PDT 24
Finished Jun 23 05:39:16 PM PDT 24
Peak memory 216572 kb
Host smart-a6877186-ab08-4bfd-baaf-12c747188d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587276696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.587276696
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2982629949
Short name T82
Test name
Test status
Simulation time 9323074776 ps
CPU time 25.68 seconds
Started Jun 23 05:38:49 PM PDT 24
Finished Jun 23 05:39:15 PM PDT 24
Peak memory 214620 kb
Host smart-c8417f40-41b3-4a2b-8305-0e9961c06e07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982629949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2982629949
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2556536611
Short name T10
Test name
Test status
Simulation time 237574653759 ps
CPU time 1707.56 seconds
Started Jun 23 05:38:45 PM PDT 24
Finished Jun 23 06:07:13 PM PDT 24
Peak memory 238856 kb
Host smart-1e6e2772-4e4d-4f9f-87e0-497d2e0b4810
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556536611 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2556536611
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.752405371
Short name T286
Test name
Test status
Simulation time 4086611928 ps
CPU time 15.53 seconds
Started Jun 23 05:38:50 PM PDT 24
Finished Jun 23 05:39:06 PM PDT 24
Peak memory 217080 kb
Host smart-59d580a1-6884-4f55-883c-b51d02a33bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752405371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.752405371
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2448848344
Short name T159
Test name
Test status
Simulation time 73046366654 ps
CPU time 838.5 seconds
Started Jun 23 05:38:50 PM PDT 24
Finished Jun 23 05:52:49 PM PDT 24
Peak memory 233912 kb
Host smart-cd61b12f-4bc4-476c-bff1-00335f4fe78c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448848344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2448848344
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.4254191187
Short name T259
Test name
Test status
Simulation time 6374503906 ps
CPU time 39.27 seconds
Started Jun 23 05:38:49 PM PDT 24
Finished Jun 23 05:39:29 PM PDT 24
Peak memory 219304 kb
Host smart-6a55eb63-4e30-4dea-8ad9-3e1297e427c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254191187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.4254191187
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2974807781
Short name T357
Test name
Test status
Simulation time 242721461 ps
CPU time 10.33 seconds
Started Jun 23 05:38:53 PM PDT 24
Finished Jun 23 05:39:03 PM PDT 24
Peak memory 219336 kb
Host smart-9250daba-36e1-4c9a-bea2-40d24175768d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2974807781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2974807781
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1301925593
Short name T240
Test name
Test status
Simulation time 19794203683 ps
CPU time 55.69 seconds
Started Jun 23 05:38:48 PM PDT 24
Finished Jun 23 05:39:44 PM PDT 24
Peak memory 217432 kb
Host smart-2fb8cf63-999d-44a9-8f04-8f480f554687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301925593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1301925593
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1813523219
Short name T230
Test name
Test status
Simulation time 3553744144 ps
CPU time 36.82 seconds
Started Jun 23 05:38:50 PM PDT 24
Finished Jun 23 05:39:27 PM PDT 24
Peak memory 214532 kb
Host smart-037a7fb5-bf7c-4182-92d4-c789138105ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813523219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1813523219
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3128058090
Short name T9
Test name
Test status
Simulation time 13982897067 ps
CPU time 28.08 seconds
Started Jun 23 05:38:49 PM PDT 24
Finished Jun 23 05:39:17 PM PDT 24
Peak memory 217476 kb
Host smart-5d1ae908-5725-402d-a20f-1619f3f71785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128058090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3128058090
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.4238313985
Short name T269
Test name
Test status
Simulation time 2199763732 ps
CPU time 167.3 seconds
Started Jun 23 05:38:50 PM PDT 24
Finished Jun 23 05:41:38 PM PDT 24
Peak memory 239472 kb
Host smart-cbf6ec33-7e0b-444d-ab8b-ceef483b64bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238313985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.4238313985
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1417481342
Short name T315
Test name
Test status
Simulation time 662278429 ps
CPU time 19.12 seconds
Started Jun 23 05:38:52 PM PDT 24
Finished Jun 23 05:39:11 PM PDT 24
Peak memory 219260 kb
Host smart-b6a6668b-002c-4087-adae-d1d5c6bee61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417481342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1417481342
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.4025474712
Short name T162
Test name
Test status
Simulation time 175140625 ps
CPU time 10.44 seconds
Started Jun 23 05:38:48 PM PDT 24
Finished Jun 23 05:38:59 PM PDT 24
Peak memory 219332 kb
Host smart-42581956-3a5c-4c74-a58f-a66fdd8907b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4025474712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.4025474712
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2730853828
Short name T169
Test name
Test status
Simulation time 7328091143 ps
CPU time 56.32 seconds
Started Jun 23 05:38:49 PM PDT 24
Finished Jun 23 05:39:46 PM PDT 24
Peak memory 216584 kb
Host smart-2af1613d-0bf9-4093-95d5-ba7462ad37b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730853828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2730853828
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3452605390
Short name T141
Test name
Test status
Simulation time 9638438177 ps
CPU time 67.53 seconds
Started Jun 23 05:38:50 PM PDT 24
Finished Jun 23 05:39:58 PM PDT 24
Peak memory 221784 kb
Host smart-f9b45a30-3d0b-468f-bab0-5e5d33b6543d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452605390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3452605390
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3869120231
Short name T207
Test name
Test status
Simulation time 2839964750 ps
CPU time 16.73 seconds
Started Jun 23 05:37:25 PM PDT 24
Finished Jun 23 05:37:42 PM PDT 24
Peak memory 217212 kb
Host smart-76973abe-4c16-428f-a32d-c0757cae895b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869120231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3869120231
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.395747858
Short name T346
Test name
Test status
Simulation time 147401744814 ps
CPU time 470.72 seconds
Started Jun 23 05:37:25 PM PDT 24
Finished Jun 23 05:45:16 PM PDT 24
Peak memory 238676 kb
Host smart-6e44c077-a6c9-4c54-8aee-3b515e10ae1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395747858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.395747858
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.978970118
Short name T272
Test name
Test status
Simulation time 21112995654 ps
CPU time 50.41 seconds
Started Jun 23 05:37:25 PM PDT 24
Finished Jun 23 05:38:16 PM PDT 24
Peak memory 219144 kb
Host smart-a599bbb5-12b8-4793-b423-0261a17db383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978970118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.978970118
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.981020866
Short name T281
Test name
Test status
Simulation time 10797037767 ps
CPU time 25.67 seconds
Started Jun 23 05:37:22 PM PDT 24
Finished Jun 23 05:37:48 PM PDT 24
Peak memory 219384 kb
Host smart-81553455-45de-4f0c-b48f-af52dafffd5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=981020866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.981020866
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2203144483
Short name T293
Test name
Test status
Simulation time 703861138 ps
CPU time 19.64 seconds
Started Jun 23 05:37:23 PM PDT 24
Finished Jun 23 05:37:43 PM PDT 24
Peak memory 216772 kb
Host smart-ab7ae73a-984b-425a-a1e7-b8a1c000263c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203144483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2203144483
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.762522986
Short name T241
Test name
Test status
Simulation time 46235785351 ps
CPU time 134.68 seconds
Started Jun 23 05:37:24 PM PDT 24
Finished Jun 23 05:39:39 PM PDT 24
Peak memory 220396 kb
Host smart-b579b6f9-9208-46d2-bcd2-14726d1454b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762522986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.762522986
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.610136959
Short name T289
Test name
Test status
Simulation time 459662683 ps
CPU time 8.62 seconds
Started Jun 23 05:37:23 PM PDT 24
Finished Jun 23 05:37:32 PM PDT 24
Peak memory 217072 kb
Host smart-d5fd4348-0326-4640-9415-0c03993e34fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610136959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.610136959
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1405123217
Short name T138
Test name
Test status
Simulation time 42552660199 ps
CPU time 164.32 seconds
Started Jun 23 05:37:24 PM PDT 24
Finished Jun 23 05:40:08 PM PDT 24
Peak memory 237508 kb
Host smart-a23f1296-c9b7-4cea-9246-4bb346516f8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405123217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1405123217
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1891444865
Short name T266
Test name
Test status
Simulation time 1574113234 ps
CPU time 19.18 seconds
Started Jun 23 05:37:23 PM PDT 24
Finished Jun 23 05:37:42 PM PDT 24
Peak memory 219264 kb
Host smart-07be9ffe-30c7-4566-994d-fd08d419ee65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891444865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1891444865
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3473678967
Short name T133
Test name
Test status
Simulation time 3135548588 ps
CPU time 28.05 seconds
Started Jun 23 05:37:26 PM PDT 24
Finished Jun 23 05:37:54 PM PDT 24
Peak memory 217540 kb
Host smart-8ce415d8-7126-49ec-9c85-6cc072d3dc90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3473678967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3473678967
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.629580428
Short name T246
Test name
Test status
Simulation time 14793661068 ps
CPU time 61.04 seconds
Started Jun 23 05:37:27 PM PDT 24
Finished Jun 23 05:38:29 PM PDT 24
Peak memory 216632 kb
Host smart-5cd2040a-d132-4dc2-a704-9be6a685d9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629580428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.629580428
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1220159132
Short name T318
Test name
Test status
Simulation time 11080753000 ps
CPU time 119.2 seconds
Started Jun 23 05:37:24 PM PDT 24
Finished Jun 23 05:39:24 PM PDT 24
Peak memory 219944 kb
Host smart-f40c9564-a42f-41a0-be51-b2538afc519a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220159132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1220159132
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1413594984
Short name T52
Test name
Test status
Simulation time 195727843376 ps
CPU time 1063.02 seconds
Started Jun 23 05:37:24 PM PDT 24
Finished Jun 23 05:55:08 PM PDT 24
Peak memory 235840 kb
Host smart-c734ce40-1c7b-4cef-8547-91fcc38b1607
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413594984 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.1413594984
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.752293966
Short name T229
Test name
Test status
Simulation time 38477272737 ps
CPU time 24.48 seconds
Started Jun 23 05:37:22 PM PDT 24
Finished Jun 23 05:37:47 PM PDT 24
Peak memory 217484 kb
Host smart-85421c3b-4878-4bc9-9285-892b05dd11da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752293966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.752293966
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.234474471
Short name T215
Test name
Test status
Simulation time 163534860579 ps
CPU time 661.41 seconds
Started Jun 23 05:37:23 PM PDT 24
Finished Jun 23 05:48:25 PM PDT 24
Peak memory 225944 kb
Host smart-17cca73b-976c-4e2d-82ac-f0e3f1396df6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234474471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.234474471
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.526390141
Short name T245
Test name
Test status
Simulation time 6458404665 ps
CPU time 55.82 seconds
Started Jun 23 05:37:26 PM PDT 24
Finished Jun 23 05:38:22 PM PDT 24
Peak memory 219228 kb
Host smart-f5958888-96e3-49aa-b5f4-77174cbd17a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526390141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.526390141
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3928407806
Short name T314
Test name
Test status
Simulation time 5288697513 ps
CPU time 18.68 seconds
Started Jun 23 05:37:24 PM PDT 24
Finished Jun 23 05:37:43 PM PDT 24
Peak memory 219368 kb
Host smart-f2b9690e-1839-4718-af21-ed6510d311ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3928407806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3928407806
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.4094124720
Short name T355
Test name
Test status
Simulation time 11688297468 ps
CPU time 57.22 seconds
Started Jun 23 05:37:22 PM PDT 24
Finished Jun 23 05:38:19 PM PDT 24
Peak memory 216516 kb
Host smart-f5ae1fe8-2e74-4cde-9631-83d24be322e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094124720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.4094124720
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2283120429
Short name T290
Test name
Test status
Simulation time 8777928334 ps
CPU time 27.89 seconds
Started Jun 23 05:37:25 PM PDT 24
Finished Jun 23 05:37:54 PM PDT 24
Peak memory 217392 kb
Host smart-5c7a4d70-f23b-4e7e-bf3a-09c268aade09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283120429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2283120429
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3755455414
Short name T256
Test name
Test status
Simulation time 6116735189 ps
CPU time 288.94 seconds
Started Jun 23 05:37:25 PM PDT 24
Finished Jun 23 05:42:15 PM PDT 24
Peak memory 227812 kb
Host smart-eea87983-9c76-4e67-b0fb-d1de2291f42f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755455414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3755455414
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3938126090
Short name T33
Test name
Test status
Simulation time 342889795 ps
CPU time 19.68 seconds
Started Jun 23 05:37:27 PM PDT 24
Finished Jun 23 05:37:47 PM PDT 24
Peak memory 219200 kb
Host smart-e7542296-9cc7-4641-bda6-93e92198779d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938126090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3938126090
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2038847663
Short name T137
Test name
Test status
Simulation time 15783303618 ps
CPU time 32.87 seconds
Started Jun 23 05:37:22 PM PDT 24
Finished Jun 23 05:37:56 PM PDT 24
Peak memory 211744 kb
Host smart-982316cf-ddfb-4e06-9829-fc1af8ea9cc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2038847663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2038847663
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2049172656
Short name T15
Test name
Test status
Simulation time 8267195760 ps
CPU time 66.56 seconds
Started Jun 23 05:37:27 PM PDT 24
Finished Jun 23 05:38:34 PM PDT 24
Peak memory 217512 kb
Host smart-5d7df5fd-0751-4494-b4b2-ba5b2eb84734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049172656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2049172656
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1275618345
Short name T261
Test name
Test status
Simulation time 11292625070 ps
CPU time 27.52 seconds
Started Jun 23 05:37:26 PM PDT 24
Finished Jun 23 05:37:54 PM PDT 24
Peak memory 214632 kb
Host smart-4faa41f6-2528-428c-be18-3be69991a6d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275618345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1275618345
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1787558208
Short name T221
Test name
Test status
Simulation time 170875389 ps
CPU time 8.49 seconds
Started Jun 23 05:37:28 PM PDT 24
Finished Jun 23 05:37:36 PM PDT 24
Peak memory 217024 kb
Host smart-3463ea1a-0ba0-4877-aec4-3f74eeef4aff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787558208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1787558208
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.444063681
Short name T302
Test name
Test status
Simulation time 10483940239 ps
CPU time 218.99 seconds
Started Jun 23 05:37:29 PM PDT 24
Finished Jun 23 05:41:08 PM PDT 24
Peak memory 225508 kb
Host smart-30c86f2b-6695-4ab5-bb56-0fe74c3ba718
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444063681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.444063681
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3448532987
Short name T49
Test name
Test status
Simulation time 414527809 ps
CPU time 19.56 seconds
Started Jun 23 05:37:27 PM PDT 24
Finished Jun 23 05:37:47 PM PDT 24
Peak memory 219268 kb
Host smart-e9f15093-ee7f-4ca5-8f26-c7dced9c2666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448532987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3448532987
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4006528467
Short name T257
Test name
Test status
Simulation time 186570950 ps
CPU time 10.65 seconds
Started Jun 23 05:37:27 PM PDT 24
Finished Jun 23 05:37:39 PM PDT 24
Peak memory 219312 kb
Host smart-7f0b667f-74bd-40e8-a372-fc0bb8a0e4d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4006528467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4006528467
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2102224944
Short name T153
Test name
Test status
Simulation time 24498348291 ps
CPU time 55.14 seconds
Started Jun 23 05:37:28 PM PDT 24
Finished Jun 23 05:38:24 PM PDT 24
Peak memory 217248 kb
Host smart-f15bfd83-c745-44b9-bcbc-61fae2e6bf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102224944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2102224944
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1716479130
Short name T16
Test name
Test status
Simulation time 16296656189 ps
CPU time 130.45 seconds
Started Jun 23 05:37:27 PM PDT 24
Finished Jun 23 05:39:37 PM PDT 24
Peak memory 227532 kb
Host smart-1ac92485-6cfc-4764-82ee-b626f7d4e5d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716479130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1716479130
Directory /workspace/9.rom_ctrl_stress_all/latest
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