Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.21 96.89 91.99 97.68 100.00 98.28 97.30 98.37


Total test records in report: 458
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T302 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3772721539 Jun 24 04:44:04 PM PDT 24 Jun 24 04:49:39 PM PDT 24 17040268882 ps
T303 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.4274441958 Jun 24 04:44:08 PM PDT 24 Jun 24 04:44:46 PM PDT 24 14728570733 ps
T304 /workspace/coverage/default/44.rom_ctrl_smoke.2036130464 Jun 24 04:44:28 PM PDT 24 Jun 24 04:45:47 PM PDT 24 8496455657 ps
T50 /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3099845347 Jun 24 04:44:38 PM PDT 24 Jun 24 06:17:59 PM PDT 24 86078310615 ps
T305 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2033844264 Jun 24 04:44:29 PM PDT 24 Jun 24 04:44:51 PM PDT 24 342526857 ps
T306 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.505284090 Jun 24 04:44:00 PM PDT 24 Jun 24 04:44:26 PM PDT 24 1499595536 ps
T307 /workspace/coverage/default/16.rom_ctrl_alert_test.573916019 Jun 24 04:43:59 PM PDT 24 Jun 24 04:44:29 PM PDT 24 24440938982 ps
T308 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.914741665 Jun 24 04:44:03 PM PDT 24 Jun 24 04:56:24 PM PDT 24 72588839041 ps
T309 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3484715162 Jun 24 04:44:32 PM PDT 24 Jun 24 04:45:07 PM PDT 24 4075600641 ps
T310 /workspace/coverage/default/27.rom_ctrl_smoke.3421079095 Jun 24 04:44:05 PM PDT 24 Jun 24 04:45:25 PM PDT 24 30609633322 ps
T51 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.4043664402 Jun 24 04:43:42 PM PDT 24 Jun 24 05:01:20 PM PDT 24 27910666996 ps
T311 /workspace/coverage/default/23.rom_ctrl_alert_test.1905893500 Jun 24 04:44:04 PM PDT 24 Jun 24 04:44:35 PM PDT 24 4948233047 ps
T312 /workspace/coverage/default/43.rom_ctrl_smoke.2303460029 Jun 24 04:44:28 PM PDT 24 Jun 24 04:45:10 PM PDT 24 5265133404 ps
T313 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1195754440 Jun 24 04:44:18 PM PDT 24 Jun 24 04:46:47 PM PDT 24 2101166978 ps
T314 /workspace/coverage/default/25.rom_ctrl_stress_all.780114983 Jun 24 04:44:03 PM PDT 24 Jun 24 04:45:36 PM PDT 24 28914221530 ps
T315 /workspace/coverage/default/12.rom_ctrl_alert_test.731956189 Jun 24 04:43:46 PM PDT 24 Jun 24 04:44:12 PM PDT 24 2065826249 ps
T316 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2979740650 Jun 24 04:44:20 PM PDT 24 Jun 24 04:44:51 PM PDT 24 8466225804 ps
T52 /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2412391793 Jun 24 04:43:47 PM PDT 24 Jun 24 05:12:04 PM PDT 24 84814756242 ps
T317 /workspace/coverage/default/28.rom_ctrl_smoke.3950096682 Jun 24 04:44:07 PM PDT 24 Jun 24 04:44:36 PM PDT 24 1487710678 ps
T318 /workspace/coverage/default/17.rom_ctrl_alert_test.1745056014 Jun 24 04:44:05 PM PDT 24 Jun 24 04:44:28 PM PDT 24 947939384 ps
T319 /workspace/coverage/default/48.rom_ctrl_stress_all.1321529551 Jun 24 04:44:34 PM PDT 24 Jun 24 04:48:01 PM PDT 24 89326859698 ps
T320 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.154602597 Jun 24 04:43:42 PM PDT 24 Jun 24 04:54:29 PM PDT 24 66699592104 ps
T321 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.937866893 Jun 24 04:44:03 PM PDT 24 Jun 24 04:44:31 PM PDT 24 3351300336 ps
T322 /workspace/coverage/default/1.rom_ctrl_stress_all.4260405698 Jun 24 04:43:44 PM PDT 24 Jun 24 04:45:00 PM PDT 24 5923115941 ps
T323 /workspace/coverage/default/30.rom_ctrl_alert_test.3886266641 Jun 24 04:44:08 PM PDT 24 Jun 24 04:44:26 PM PDT 24 506946125 ps
T324 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.4173005462 Jun 24 04:44:27 PM PDT 24 Jun 24 04:44:49 PM PDT 24 2746283450 ps
T325 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2460074145 Jun 24 04:44:16 PM PDT 24 Jun 24 04:44:30 PM PDT 24 263158086 ps
T326 /workspace/coverage/default/48.rom_ctrl_alert_test.112947123 Jun 24 04:44:34 PM PDT 24 Jun 24 04:45:01 PM PDT 24 9503641969 ps
T327 /workspace/coverage/default/34.rom_ctrl_alert_test.2560089425 Jun 24 04:44:12 PM PDT 24 Jun 24 04:44:27 PM PDT 24 1499153298 ps
T328 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3262251703 Jun 24 04:44:35 PM PDT 24 Jun 24 04:44:59 PM PDT 24 4125120101 ps
T329 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3324437340 Jun 24 04:44:26 PM PDT 24 Jun 24 04:44:37 PM PDT 24 217918534 ps
T330 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3595216274 Jun 24 04:43:40 PM PDT 24 Jun 24 04:50:48 PM PDT 24 74979241733 ps
T331 /workspace/coverage/default/8.rom_ctrl_smoke.3648292433 Jun 24 04:43:41 PM PDT 24 Jun 24 04:44:06 PM PDT 24 1370493346 ps
T332 /workspace/coverage/default/6.rom_ctrl_smoke.1489513194 Jun 24 04:43:39 PM PDT 24 Jun 24 04:44:36 PM PDT 24 4301147121 ps
T333 /workspace/coverage/default/44.rom_ctrl_stress_all.596141972 Jun 24 04:44:27 PM PDT 24 Jun 24 04:46:26 PM PDT 24 27294807318 ps
T334 /workspace/coverage/default/44.rom_ctrl_alert_test.666850462 Jun 24 04:44:31 PM PDT 24 Jun 24 04:44:51 PM PDT 24 1322308673 ps
T335 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2959012140 Jun 24 04:44:27 PM PDT 24 Jun 24 04:56:16 PM PDT 24 151786201238 ps
T336 /workspace/coverage/default/13.rom_ctrl_stress_all.3163543255 Jun 24 04:43:50 PM PDT 24 Jun 24 04:45:44 PM PDT 24 53547927675 ps
T337 /workspace/coverage/default/46.rom_ctrl_stress_all.3208630902 Jun 24 04:44:33 PM PDT 24 Jun 24 04:45:16 PM PDT 24 1607607384 ps
T338 /workspace/coverage/default/46.rom_ctrl_alert_test.1241969086 Jun 24 04:44:36 PM PDT 24 Jun 24 04:44:48 PM PDT 24 660816167 ps
T339 /workspace/coverage/default/8.rom_ctrl_alert_test.4214222047 Jun 24 04:43:41 PM PDT 24 Jun 24 04:43:54 PM PDT 24 688600750 ps
T340 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2030595107 Jun 24 04:43:43 PM PDT 24 Jun 24 04:44:18 PM PDT 24 3514678150 ps
T341 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2780643849 Jun 24 04:43:40 PM PDT 24 Jun 24 04:44:40 PM PDT 24 6374748670 ps
T342 /workspace/coverage/default/2.rom_ctrl_stress_all.3443097921 Jun 24 04:43:45 PM PDT 24 Jun 24 04:44:24 PM PDT 24 2113572556 ps
T343 /workspace/coverage/default/9.rom_ctrl_alert_test.1804592743 Jun 24 04:43:48 PM PDT 24 Jun 24 04:44:26 PM PDT 24 8024139543 ps
T344 /workspace/coverage/default/13.rom_ctrl_smoke.2420820434 Jun 24 04:43:56 PM PDT 24 Jun 24 04:45:07 PM PDT 24 5594285260 ps
T345 /workspace/coverage/default/21.rom_ctrl_stress_all.204560731 Jun 24 04:44:05 PM PDT 24 Jun 24 04:45:04 PM PDT 24 915551337 ps
T346 /workspace/coverage/default/39.rom_ctrl_alert_test.197452134 Jun 24 04:44:20 PM PDT 24 Jun 24 04:44:36 PM PDT 24 1638103519 ps
T347 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.985212132 Jun 24 04:43:58 PM PDT 24 Jun 24 04:48:52 PM PDT 24 117874455912 ps
T348 /workspace/coverage/default/24.rom_ctrl_smoke.1360874551 Jun 24 04:44:01 PM PDT 24 Jun 24 04:44:51 PM PDT 24 7709106932 ps
T349 /workspace/coverage/default/28.rom_ctrl_stress_all.2594512944 Jun 24 04:44:03 PM PDT 24 Jun 24 04:45:58 PM PDT 24 8073548011 ps
T350 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.4279647762 Jun 24 04:44:04 PM PDT 24 Jun 24 04:44:23 PM PDT 24 727858128 ps
T351 /workspace/coverage/default/19.rom_ctrl_alert_test.559943905 Jun 24 04:44:00 PM PDT 24 Jun 24 04:44:28 PM PDT 24 1962706872 ps
T352 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.159759139 Jun 24 04:43:42 PM PDT 24 Jun 24 04:44:07 PM PDT 24 1482129683 ps
T353 /workspace/coverage/default/32.rom_ctrl_alert_test.2128166372 Jun 24 04:44:09 PM PDT 24 Jun 24 04:44:31 PM PDT 24 1645274658 ps
T354 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.234170444 Jun 24 04:43:47 PM PDT 24 Jun 24 04:56:54 PM PDT 24 145562893400 ps
T355 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.135988897 Jun 24 04:44:21 PM PDT 24 Jun 24 04:52:38 PM PDT 24 146167310655 ps
T356 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.295244154 Jun 24 04:44:33 PM PDT 24 Jun 24 04:45:11 PM PDT 24 41135286428 ps
T357 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1026115835 Jun 24 04:44:13 PM PDT 24 Jun 24 04:44:39 PM PDT 24 353355894 ps
T358 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1805965298 Jun 24 04:43:47 PM PDT 24 Jun 24 04:44:46 PM PDT 24 39493935910 ps
T359 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3279389347 Jun 24 04:43:54 PM PDT 24 Jun 24 04:44:15 PM PDT 24 4503413432 ps
T360 /workspace/coverage/default/41.rom_ctrl_smoke.1754850734 Jun 24 04:44:31 PM PDT 24 Jun 24 04:45:19 PM PDT 24 4457833386 ps
T361 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3891818690 Jun 24 04:44:03 PM PDT 24 Jun 24 04:44:41 PM PDT 24 6591027161 ps
T362 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3590207032 Jun 24 04:43:23 PM PDT 24 Jun 24 04:43:54 PM PDT 24 6715515871 ps
T53 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.48370493 Jun 24 04:43:22 PM PDT 24 Jun 24 04:43:57 PM PDT 24 3517640194 ps
T64 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1592119295 Jun 24 04:43:39 PM PDT 24 Jun 24 04:44:18 PM PDT 24 32194790211 ps
T65 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3905338962 Jun 24 04:43:33 PM PDT 24 Jun 24 04:44:09 PM PDT 24 4076307310 ps
T66 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1691393820 Jun 24 04:43:25 PM PDT 24 Jun 24 04:44:01 PM PDT 24 4216494874 ps
T73 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2144362998 Jun 24 04:43:34 PM PDT 24 Jun 24 04:45:48 PM PDT 24 160439785857 ps
T363 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2923940972 Jun 24 04:43:34 PM PDT 24 Jun 24 04:44:04 PM PDT 24 9217496293 ps
T100 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.497774246 Jun 24 04:43:25 PM PDT 24 Jun 24 04:43:38 PM PDT 24 662094107 ps
T61 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1083242004 Jun 24 04:43:32 PM PDT 24 Jun 24 04:46:31 PM PDT 24 3989673813 ps
T74 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1725566212 Jun 24 04:43:27 PM PDT 24 Jun 24 04:45:48 PM PDT 24 34080377023 ps
T75 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1487367731 Jun 24 04:43:34 PM PDT 24 Jun 24 04:43:53 PM PDT 24 999009186 ps
T364 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1384284153 Jun 24 04:43:20 PM PDT 24 Jun 24 04:43:48 PM PDT 24 32931107351 ps
T62 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4019152229 Jun 24 04:43:33 PM PDT 24 Jun 24 04:46:13 PM PDT 24 1573664598 ps
T101 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1437880486 Jun 24 04:43:27 PM PDT 24 Jun 24 04:45:45 PM PDT 24 117204294109 ps
T365 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1981820527 Jun 24 04:43:32 PM PDT 24 Jun 24 04:43:47 PM PDT 24 2774861583 ps
T76 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3216921586 Jun 24 04:43:28 PM PDT 24 Jun 24 04:44:12 PM PDT 24 18032135281 ps
T366 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2137199341 Jun 24 04:43:33 PM PDT 24 Jun 24 04:44:07 PM PDT 24 31107384565 ps
T102 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2245789906 Jun 24 04:43:33 PM PDT 24 Jun 24 04:44:04 PM PDT 24 3125617224 ps
T77 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2640144018 Jun 24 04:43:32 PM PDT 24 Jun 24 04:46:30 PM PDT 24 40434029717 ps
T78 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.271970826 Jun 24 04:43:36 PM PDT 24 Jun 24 04:43:49 PM PDT 24 689058028 ps
T367 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1322617983 Jun 24 04:43:35 PM PDT 24 Jun 24 04:44:05 PM PDT 24 10909946196 ps
T368 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1867019817 Jun 24 04:43:19 PM PDT 24 Jun 24 04:43:43 PM PDT 24 2132501796 ps
T369 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2708331225 Jun 24 04:43:28 PM PDT 24 Jun 24 04:43:53 PM PDT 24 2058398389 ps
T63 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4234933367 Jun 24 04:43:27 PM PDT 24 Jun 24 04:45:00 PM PDT 24 4801209293 ps
T370 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1238271522 Jun 24 04:43:27 PM PDT 24 Jun 24 04:43:56 PM PDT 24 11658397378 ps
T108 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.946468045 Jun 24 04:43:37 PM PDT 24 Jun 24 04:46:32 PM PDT 24 21995838635 ps
T371 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3544772497 Jun 24 04:43:38 PM PDT 24 Jun 24 04:44:09 PM PDT 24 2931022473 ps
T372 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.164654125 Jun 24 04:43:18 PM PDT 24 Jun 24 04:43:45 PM PDT 24 11925599727 ps
T373 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3098549778 Jun 24 04:43:27 PM PDT 24 Jun 24 04:43:40 PM PDT 24 167638577 ps
T374 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.413990038 Jun 24 04:43:33 PM PDT 24 Jun 24 04:44:04 PM PDT 24 2805411694 ps
T375 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1379550281 Jun 24 04:43:23 PM PDT 24 Jun 24 04:43:51 PM PDT 24 2881072690 ps
T376 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4103922687 Jun 24 04:43:35 PM PDT 24 Jun 24 04:43:49 PM PDT 24 186967357 ps
T377 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.825716644 Jun 24 04:43:31 PM PDT 24 Jun 24 04:44:02 PM PDT 24 6213208860 ps
T104 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2583574053 Jun 24 04:43:18 PM PDT 24 Jun 24 04:45:05 PM PDT 24 23573657809 ps
T378 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1071768960 Jun 24 04:43:27 PM PDT 24 Jun 24 04:44:06 PM PDT 24 3260537725 ps
T379 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1625733673 Jun 24 04:43:26 PM PDT 24 Jun 24 04:44:01 PM PDT 24 3830570286 ps
T110 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3909584045 Jun 24 04:43:29 PM PDT 24 Jun 24 04:46:23 PM PDT 24 2573248742 ps
T79 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2593557664 Jun 24 04:43:27 PM PDT 24 Jun 24 04:43:56 PM PDT 24 8530198891 ps
T380 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1090417977 Jun 24 04:43:27 PM PDT 24 Jun 24 04:44:29 PM PDT 24 2152943581 ps
T381 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3316271018 Jun 24 04:43:24 PM PDT 24 Jun 24 04:43:46 PM PDT 24 17226624625 ps
T382 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2574438541 Jun 24 04:43:35 PM PDT 24 Jun 24 04:44:19 PM PDT 24 4100663692 ps
T383 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.333120732 Jun 24 04:43:35 PM PDT 24 Jun 24 04:44:01 PM PDT 24 6822236077 ps
T95 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2153984369 Jun 24 04:43:35 PM PDT 24 Jun 24 04:43:49 PM PDT 24 339085764 ps
T96 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1135345740 Jun 24 04:43:26 PM PDT 24 Jun 24 04:43:58 PM PDT 24 6349393999 ps
T384 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1072039362 Jun 24 04:43:22 PM PDT 24 Jun 24 04:43:47 PM PDT 24 2541078063 ps
T385 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3939033517 Jun 24 04:43:25 PM PDT 24 Jun 24 04:44:01 PM PDT 24 13164570315 ps
T80 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2887820973 Jun 24 04:43:20 PM PDT 24 Jun 24 04:43:37 PM PDT 24 3626934955 ps
T81 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1553592367 Jun 24 04:43:36 PM PDT 24 Jun 24 04:44:00 PM PDT 24 1870559747 ps
T386 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3165233426 Jun 24 04:43:27 PM PDT 24 Jun 24 04:43:51 PM PDT 24 7150516138 ps
T82 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.546312660 Jun 24 04:43:36 PM PDT 24 Jun 24 04:44:05 PM PDT 24 4994214718 ps
T387 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3344501438 Jun 24 04:43:34 PM PDT 24 Jun 24 04:44:12 PM PDT 24 4320290435 ps
T388 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.305853185 Jun 24 04:43:18 PM PDT 24 Jun 24 04:43:47 PM PDT 24 29589642708 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1895284665 Jun 24 04:43:27 PM PDT 24 Jun 24 04:44:04 PM PDT 24 3357188373 ps
T109 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.901049990 Jun 24 04:43:34 PM PDT 24 Jun 24 04:46:13 PM PDT 24 321470209 ps
T390 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.456822 Jun 24 04:43:33 PM PDT 24 Jun 24 04:44:14 PM PDT 24 7856948117 ps
T391 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1677909317 Jun 24 04:43:38 PM PDT 24 Jun 24 04:44:06 PM PDT 24 4956496952 ps
T113 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2206684478 Jun 24 04:43:32 PM PDT 24 Jun 24 04:45:16 PM PDT 24 62652690247 ps
T105 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1520368355 Jun 24 04:43:38 PM PDT 24 Jun 24 04:44:34 PM PDT 24 6972713760 ps
T392 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3760567250 Jun 24 04:43:34 PM PDT 24 Jun 24 04:44:09 PM PDT 24 27532879416 ps
T97 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3865903451 Jun 24 04:43:39 PM PDT 24 Jun 24 04:43:56 PM PDT 24 602968670 ps
T98 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2334679660 Jun 24 04:43:32 PM PDT 24 Jun 24 04:44:04 PM PDT 24 12778909056 ps
T393 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3155970503 Jun 24 04:43:25 PM PDT 24 Jun 24 04:43:57 PM PDT 24 15162401632 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2055155973 Jun 24 04:43:19 PM PDT 24 Jun 24 04:44:09 PM PDT 24 2738145123 ps
T395 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.557235720 Jun 24 04:43:25 PM PDT 24 Jun 24 04:43:58 PM PDT 24 3042331219 ps
T396 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2650592867 Jun 24 04:43:26 PM PDT 24 Jun 24 04:43:48 PM PDT 24 2312312651 ps
T397 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.750850458 Jun 24 04:43:29 PM PDT 24 Jun 24 04:43:42 PM PDT 24 167482888 ps
T398 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2240836848 Jun 24 04:43:27 PM PDT 24 Jun 24 04:45:14 PM PDT 24 4026955682 ps
T86 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3652139813 Jun 24 04:43:32 PM PDT 24 Jun 24 04:46:45 PM PDT 24 22637888799 ps
T87 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3095395134 Jun 24 04:43:27 PM PDT 24 Jun 24 04:44:28 PM PDT 24 1115730480 ps
T106 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4122604870 Jun 24 04:43:25 PM PDT 24 Jun 24 04:46:01 PM PDT 24 588674178 ps
T88 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.955117333 Jun 24 04:43:25 PM PDT 24 Jun 24 04:43:38 PM PDT 24 174321317 ps
T399 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2828364288 Jun 24 04:43:24 PM PDT 24 Jun 24 04:43:57 PM PDT 24 56385800835 ps
T400 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2433782089 Jun 24 04:43:20 PM PDT 24 Jun 24 04:43:46 PM PDT 24 8236292246 ps
T401 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4074044508 Jun 24 04:43:28 PM PDT 24 Jun 24 04:43:41 PM PDT 24 368957981 ps
T99 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.807634711 Jun 24 04:43:32 PM PDT 24 Jun 24 04:44:00 PM PDT 24 2628620465 ps
T402 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.801293273 Jun 24 04:43:34 PM PDT 24 Jun 24 04:44:36 PM PDT 24 1619237669 ps
T403 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2217734650 Jun 24 04:43:33 PM PDT 24 Jun 24 04:44:04 PM PDT 24 3378089958 ps
T107 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4223476458 Jun 24 04:43:28 PM PDT 24 Jun 24 04:46:23 PM PDT 24 3081989397 ps
T116 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1349521058 Jun 24 04:43:19 PM PDT 24 Jun 24 04:46:15 PM PDT 24 3589177347 ps
T404 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3572258209 Jun 24 04:43:35 PM PDT 24 Jun 24 04:44:00 PM PDT 24 2869711482 ps
T405 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1469550824 Jun 24 04:43:26 PM PDT 24 Jun 24 04:43:49 PM PDT 24 5783542709 ps
T406 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3774476949 Jun 24 04:43:39 PM PDT 24 Jun 24 04:43:53 PM PDT 24 190534077 ps
T407 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1182112000 Jun 24 04:43:26 PM PDT 24 Jun 24 04:44:23 PM PDT 24 16682860539 ps
T408 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2162609954 Jun 24 04:43:31 PM PDT 24 Jun 24 04:44:00 PM PDT 24 8198870653 ps
T111 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3547974407 Jun 24 04:43:33 PM PDT 24 Jun 24 04:46:10 PM PDT 24 1236700430 ps
T93 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1537341710 Jun 24 04:43:34 PM PDT 24 Jun 24 04:45:56 PM PDT 24 19991250979 ps
T117 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2858365759 Jun 24 04:43:33 PM PDT 24 Jun 24 04:46:33 PM PDT 24 4826371736 ps
T409 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3106289464 Jun 24 04:43:27 PM PDT 24 Jun 24 04:44:00 PM PDT 24 11620510172 ps
T90 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1524986472 Jun 24 04:43:28 PM PDT 24 Jun 24 04:43:45 PM PDT 24 1031254507 ps
T410 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.899117651 Jun 24 04:43:34 PM PDT 24 Jun 24 04:45:04 PM PDT 24 757972831 ps
T91 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1449463691 Jun 24 04:43:33 PM PDT 24 Jun 24 04:43:46 PM PDT 24 917042734 ps
T411 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.924627105 Jun 24 04:43:35 PM PDT 24 Jun 24 04:44:07 PM PDT 24 3183185942 ps
T412 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.539102762 Jun 24 04:43:34 PM PDT 24 Jun 24 04:45:20 PM PDT 24 11191253658 ps
T413 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4293203626 Jun 24 04:43:20 PM PDT 24 Jun 24 04:43:50 PM PDT 24 6994765034 ps
T414 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.87570090 Jun 24 04:43:34 PM PDT 24 Jun 24 04:43:49 PM PDT 24 344434199 ps
T415 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3821624009 Jun 24 04:43:34 PM PDT 24 Jun 24 04:43:48 PM PDT 24 826974675 ps
T416 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4047240370 Jun 24 04:43:37 PM PDT 24 Jun 24 04:45:46 PM PDT 24 15743657379 ps
T417 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4255533022 Jun 24 04:43:20 PM PDT 24 Jun 24 04:43:32 PM PDT 24 688598022 ps
T418 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2703333597 Jun 24 04:43:34 PM PDT 24 Jun 24 04:43:57 PM PDT 24 5921160199 ps
T419 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.383189002 Jun 24 04:43:37 PM PDT 24 Jun 24 04:46:17 PM PDT 24 290760104 ps
T420 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2203620376 Jun 24 04:43:38 PM PDT 24 Jun 24 04:43:54 PM PDT 24 958103216 ps
T115 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1203230988 Jun 24 04:43:27 PM PDT 24 Jun 24 04:46:14 PM PDT 24 1862496171 ps
T421 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.736765631 Jun 24 04:43:26 PM PDT 24 Jun 24 04:43:59 PM PDT 24 12509148885 ps
T422 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3155801391 Jun 24 04:43:33 PM PDT 24 Jun 24 04:44:07 PM PDT 24 5387622687 ps
T423 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3833285595 Jun 24 04:43:26 PM PDT 24 Jun 24 04:43:52 PM PDT 24 2237540896 ps
T424 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1610319904 Jun 24 04:43:32 PM PDT 24 Jun 24 04:44:11 PM PDT 24 8203220345 ps
T425 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3565252993 Jun 24 04:43:24 PM PDT 24 Jun 24 04:43:36 PM PDT 24 635649615 ps
T426 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3997957820 Jun 24 04:43:27 PM PDT 24 Jun 24 04:43:42 PM PDT 24 2225639496 ps
T427 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3989584773 Jun 24 04:43:37 PM PDT 24 Jun 24 04:43:54 PM PDT 24 421394055 ps
T428 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1154495275 Jun 24 04:43:26 PM PDT 24 Jun 24 04:44:01 PM PDT 24 3270372297 ps
T429 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3245674525 Jun 24 04:43:25 PM PDT 24 Jun 24 04:44:00 PM PDT 24 3731076790 ps
T114 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2802853156 Jun 24 04:43:23 PM PDT 24 Jun 24 04:44:54 PM PDT 24 2572714429 ps
T430 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3362104144 Jun 24 04:43:26 PM PDT 24 Jun 24 04:43:44 PM PDT 24 1357050494 ps
T94 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4065104676 Jun 24 04:43:35 PM PDT 24 Jun 24 04:45:06 PM PDT 24 8313060434 ps
T431 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.221453382 Jun 24 04:43:26 PM PDT 24 Jun 24 04:43:52 PM PDT 24 2492214606 ps
T432 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3835721418 Jun 24 04:43:29 PM PDT 24 Jun 24 04:44:04 PM PDT 24 14658986585 ps
T433 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2101861834 Jun 24 04:43:19 PM PDT 24 Jun 24 04:43:52 PM PDT 24 4311435356 ps
T434 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1545101427 Jun 24 04:43:24 PM PDT 24 Jun 24 04:43:45 PM PDT 24 2995939328 ps
T435 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3289925310 Jun 24 04:43:34 PM PDT 24 Jun 24 04:44:03 PM PDT 24 21446354052 ps
T436 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2013440759 Jun 24 04:43:20 PM PDT 24 Jun 24 04:43:39 PM PDT 24 1406544839 ps
T437 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3784206692 Jun 24 04:43:34 PM PDT 24 Jun 24 04:44:02 PM PDT 24 3744288358 ps
T438 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4162883796 Jun 24 04:43:19 PM PDT 24 Jun 24 04:43:45 PM PDT 24 9738469933 ps
T439 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1771265447 Jun 24 04:43:32 PM PDT 24 Jun 24 04:44:06 PM PDT 24 3625613108 ps
T440 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4267787225 Jun 24 04:43:27 PM PDT 24 Jun 24 04:43:48 PM PDT 24 6341904642 ps
T441 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3561462544 Jun 24 04:43:28 PM PDT 24 Jun 24 04:44:30 PM PDT 24 4308320318 ps
T89 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1515165920 Jun 24 04:43:35 PM PDT 24 Jun 24 04:44:06 PM PDT 24 11879315623 ps
T442 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.115162973 Jun 24 04:43:19 PM PDT 24 Jun 24 04:43:57 PM PDT 24 16389202653 ps
T443 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1533899652 Jun 24 04:43:28 PM PDT 24 Jun 24 04:43:55 PM PDT 24 9507766962 ps
T444 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3524893697 Jun 24 04:43:25 PM PDT 24 Jun 24 04:44:56 PM PDT 24 5057694000 ps
T445 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2573309336 Jun 24 04:43:27 PM PDT 24 Jun 24 04:46:39 PM PDT 24 23614981382 ps
T446 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3950928898 Jun 24 04:43:27 PM PDT 24 Jun 24 04:43:41 PM PDT 24 177933736 ps
T447 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1689915118 Jun 24 04:43:18 PM PDT 24 Jun 24 04:43:31 PM PDT 24 1324143487 ps
T448 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2446816887 Jun 24 04:43:25 PM PDT 24 Jun 24 04:43:54 PM PDT 24 4373244103 ps
T449 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3105771594 Jun 24 04:43:26 PM PDT 24 Jun 24 04:43:58 PM PDT 24 6519554346 ps
T112 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.369859715 Jun 24 04:43:38 PM PDT 24 Jun 24 04:45:25 PM PDT 24 15757334554 ps
T450 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1261408742 Jun 24 04:43:23 PM PDT 24 Jun 24 04:43:56 PM PDT 24 15372800779 ps
T451 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2831970445 Jun 24 04:43:31 PM PDT 24 Jun 24 04:43:44 PM PDT 24 332564050 ps
T452 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3711301966 Jun 24 04:43:26 PM PDT 24 Jun 24 04:43:39 PM PDT 24 364844659 ps
T453 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3503663760 Jun 24 04:43:26 PM PDT 24 Jun 24 04:44:53 PM PDT 24 1131520434 ps
T454 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.436470015 Jun 24 04:43:32 PM PDT 24 Jun 24 04:45:19 PM PDT 24 11318307445 ps
T92 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2282647938 Jun 24 04:43:28 PM PDT 24 Jun 24 04:44:45 PM PDT 24 5001129602 ps
T455 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1865705732 Jun 24 04:43:35 PM PDT 24 Jun 24 04:44:14 PM PDT 24 16018264384 ps
T456 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4066195481 Jun 24 04:43:27 PM PDT 24 Jun 24 04:44:06 PM PDT 24 17228126647 ps
T457 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3716753033 Jun 24 04:43:26 PM PDT 24 Jun 24 04:43:51 PM PDT 24 4355997302 ps
T458 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4004804025 Jun 24 04:43:25 PM PDT 24 Jun 24 04:43:54 PM PDT 24 5236686219 ps

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.205716632
Short name T10
Test name
Test status
Simulation time 2127180009 ps
CPU time 65.12 seconds
Started Jun 24 04:43:54 PM PDT 24
Finished Jun 24 04:45:05 PM PDT 24
Peak memory 220652 kb
Host smart-b968371f-279a-43c5-9785-e7c9b1811325
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205716632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.205716632
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.799106013
Short name T2
Test name
Test status
Simulation time 24549821028 ps
CPU time 505.9 seconds
Started Jun 24 04:44:04 PM PDT 24
Finished Jun 24 04:52:38 PM PDT 24
Peak memory 240176 kb
Host smart-7d728ace-7753-4e3e-bb39-6a4899e1755f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799106013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.799106013
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.484934719
Short name T11
Test name
Test status
Simulation time 79126404853 ps
CPU time 2136.55 seconds
Started Jun 24 04:43:56 PM PDT 24
Finished Jun 24 05:19:39 PM PDT 24
Peak memory 235596 kb
Host smart-f571f449-c156-490f-9afe-e19940593f56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484934719 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.484934719
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2379679360
Short name T7
Test name
Test status
Simulation time 2852165999 ps
CPU time 61.03 seconds
Started Jun 24 04:44:13 PM PDT 24
Finished Jun 24 04:45:20 PM PDT 24
Peak memory 219116 kb
Host smart-64865404-becc-4ef8-8cba-28669882aeb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379679360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2379679360
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4019152229
Short name T62
Test name
Test status
Simulation time 1573664598 ps
CPU time 154.52 seconds
Started Jun 24 04:43:33 PM PDT 24
Finished Jun 24 04:46:13 PM PDT 24
Peak memory 219816 kb
Host smart-bd53eb4a-45c7-47e9-b65c-c487ae20e7f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019152229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.4019152229
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3816909369
Short name T43
Test name
Test status
Simulation time 265403635507 ps
CPU time 609.95 seconds
Started Jun 24 04:44:03 PM PDT 24
Finished Jun 24 04:54:21 PM PDT 24
Peak memory 227992 kb
Host smart-5ca4caea-9b09-44cb-859e-d7b311c95ebe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816909369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3816909369
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.748166060
Short name T18
Test name
Test status
Simulation time 1129276017 ps
CPU time 129.46 seconds
Started Jun 24 04:43:33 PM PDT 24
Finished Jun 24 04:45:47 PM PDT 24
Peak memory 242272 kb
Host smart-be591057-260c-4198-bf8c-ca035b9ec087
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748166060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.748166060
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1725566212
Short name T74
Test name
Test status
Simulation time 34080377023 ps
CPU time 136.49 seconds
Started Jun 24 04:43:27 PM PDT 24
Finished Jun 24 04:45:48 PM PDT 24
Peak memory 214872 kb
Host smart-1f129d08-ab9f-4eb1-aa3f-a017ed764a6c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725566212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1725566212
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3123239199
Short name T8
Test name
Test status
Simulation time 703869963 ps
CPU time 10.93 seconds
Started Jun 24 04:43:47 PM PDT 24
Finished Jun 24 04:44:03 PM PDT 24
Peak memory 217336 kb
Host smart-920f0f18-0243-417c-b41e-8d55b9d56d66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123239199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3123239199
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.946468045
Short name T108
Test name
Test status
Simulation time 21995838635 ps
CPU time 170.24 seconds
Started Jun 24 04:43:37 PM PDT 24
Finished Jun 24 04:46:32 PM PDT 24
Peak memory 219600 kb
Host smart-7cc3bbea-e836-4736-88fe-a19da6477d24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946468045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.946468045
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.637309497
Short name T129
Test name
Test status
Simulation time 18452217421 ps
CPU time 48.58 seconds
Started Jun 24 04:43:48 PM PDT 24
Finished Jun 24 04:44:42 PM PDT 24
Peak memory 219044 kb
Host smart-3ceedf8f-4570-4860-92d7-45b060f222a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637309497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.637309497
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.96491372
Short name T42
Test name
Test status
Simulation time 1139339067 ps
CPU time 19.2 seconds
Started Jun 24 04:43:47 PM PDT 24
Finished Jun 24 04:44:12 PM PDT 24
Peak memory 219068 kb
Host smart-ef66c36e-efb4-4357-a38d-c841537fc284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96491372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.96491372
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3547974407
Short name T111
Test name
Test status
Simulation time 1236700430 ps
CPU time 152.55 seconds
Started Jun 24 04:43:33 PM PDT 24
Finished Jun 24 04:46:10 PM PDT 24
Peak memory 214648 kb
Host smart-80d26649-50c4-4443-b47c-049520fd87c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547974407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3547974407
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1537341710
Short name T93
Test name
Test status
Simulation time 19991250979 ps
CPU time 137.31 seconds
Started Jun 24 04:43:34 PM PDT 24
Finished Jun 24 04:45:56 PM PDT 24
Peak memory 216100 kb
Host smart-f2f61ee1-b65e-4546-9ea4-b4acc58dae3d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537341710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1537341710
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1349521058
Short name T116
Test name
Test status
Simulation time 3589177347 ps
CPU time 173.42 seconds
Started Jun 24 04:43:19 PM PDT 24
Finished Jun 24 04:46:15 PM PDT 24
Peak memory 214712 kb
Host smart-4d762326-23b4-4d3e-85bb-35a1579a567b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349521058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1349521058
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2802853156
Short name T114
Test name
Test status
Simulation time 2572714429 ps
CPU time 88.1 seconds
Started Jun 24 04:43:23 PM PDT 24
Finished Jun 24 04:44:54 PM PDT 24
Peak memory 213984 kb
Host smart-fec7ee13-3590-4122-8185-125342168c99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802853156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2802853156
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2640144018
Short name T77
Test name
Test status
Simulation time 40434029717 ps
CPU time 173.39 seconds
Started Jun 24 04:43:32 PM PDT 24
Finished Jun 24 04:46:30 PM PDT 24
Peak memory 215652 kb
Host smart-077a06c6-6bc5-4594-8e1c-578524b5b8e1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640144018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2640144018
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3493126972
Short name T14
Test name
Test status
Simulation time 94575618136 ps
CPU time 2699.4 seconds
Started Jun 24 04:43:54 PM PDT 24
Finished Jun 24 05:29:00 PM PDT 24
Peak memory 242312 kb
Host smart-c5de645c-b588-4364-9bc4-a97d75eee112
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493126972 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.3493126972
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1072039362
Short name T384
Test name
Test status
Simulation time 2541078063 ps
CPU time 22.84 seconds
Started Jun 24 04:43:22 PM PDT 24
Finished Jun 24 04:43:47 PM PDT 24
Peak memory 211996 kb
Host smart-b250379e-6753-4267-8117-ec99a21dfa80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072039362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1072039362
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3316271018
Short name T381
Test name
Test status
Simulation time 17226624625 ps
CPU time 18.71 seconds
Started Jun 24 04:43:24 PM PDT 24
Finished Jun 24 04:43:46 PM PDT 24
Peak memory 212544 kb
Host smart-80b128af-4642-420d-874d-7bcf8777c87a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316271018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3316271018
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2013440759
Short name T436
Test name
Test status
Simulation time 1406544839 ps
CPU time 15.39 seconds
Started Jun 24 04:43:20 PM PDT 24
Finished Jun 24 04:43:39 PM PDT 24
Peak memory 212752 kb
Host smart-7e0814af-5e07-4072-a320-2656692e6144
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013440759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2013440759
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4293203626
Short name T413
Test name
Test status
Simulation time 6994765034 ps
CPU time 27.11 seconds
Started Jun 24 04:43:20 PM PDT 24
Finished Jun 24 04:43:50 PM PDT 24
Peak memory 219536 kb
Host smart-68ea2468-370e-49bc-b060-03f9e226f653
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293203626 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.4293203626
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2887820973
Short name T80
Test name
Test status
Simulation time 3626934955 ps
CPU time 13.3 seconds
Started Jun 24 04:43:20 PM PDT 24
Finished Jun 24 04:43:37 PM PDT 24
Peak memory 211560 kb
Host smart-dc6ec15e-51c1-4e23-a821-827b98b81661
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887820973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2887820973
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1689915118
Short name T447
Test name
Test status
Simulation time 1324143487 ps
CPU time 10.48 seconds
Started Jun 24 04:43:18 PM PDT 24
Finished Jun 24 04:43:31 PM PDT 24
Peak memory 211112 kb
Host smart-5669e22e-b8bd-4bb0-ae3f-3783c0bbe7a2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689915118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1689915118
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.164654125
Short name T372
Test name
Test status
Simulation time 11925599727 ps
CPU time 24.81 seconds
Started Jun 24 04:43:18 PM PDT 24
Finished Jun 24 04:43:45 PM PDT 24
Peak memory 211564 kb
Host smart-a17f0398-0fda-4be8-a444-77ae45a62ed8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164654125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
164654125
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2583574053
Short name T104
Test name
Test status
Simulation time 23573657809 ps
CPU time 104.2 seconds
Started Jun 24 04:43:18 PM PDT 24
Finished Jun 24 04:45:05 PM PDT 24
Peak memory 212376 kb
Host smart-2000146c-aebb-4a7e-93fe-a7489b6f278f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583574053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2583574053
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4255533022
Short name T417
Test name
Test status
Simulation time 688598022 ps
CPU time 8.24 seconds
Started Jun 24 04:43:20 PM PDT 24
Finished Jun 24 04:43:32 PM PDT 24
Peak memory 211764 kb
Host smart-1246fe6b-f331-4450-af38-1b0e033021a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255533022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.4255533022
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.115162973
Short name T442
Test name
Test status
Simulation time 16389202653 ps
CPU time 34.77 seconds
Started Jun 24 04:43:19 PM PDT 24
Finished Jun 24 04:43:57 PM PDT 24
Peak memory 218044 kb
Host smart-2b8fae3d-f005-4b1b-9473-87e2a2a579a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115162973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.115162973
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1867019817
Short name T368
Test name
Test status
Simulation time 2132501796 ps
CPU time 20.68 seconds
Started Jun 24 04:43:19 PM PDT 24
Finished Jun 24 04:43:43 PM PDT 24
Peak memory 211980 kb
Host smart-4997f7bd-97f8-4a44-b8fc-0745bc8b0a97
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867019817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1867019817
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.305853185
Short name T388
Test name
Test status
Simulation time 29589642708 ps
CPU time 26.74 seconds
Started Jun 24 04:43:18 PM PDT 24
Finished Jun 24 04:43:47 PM PDT 24
Peak memory 212620 kb
Host smart-49d43f47-103b-4b9d-aebd-30f30bc280ea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305853185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.305853185
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2433782089
Short name T400
Test name
Test status
Simulation time 8236292246 ps
CPU time 22.6 seconds
Started Jun 24 04:43:20 PM PDT 24
Finished Jun 24 04:43:46 PM PDT 24
Peak memory 211580 kb
Host smart-e0cda30f-1acd-42bb-8b44-9f93d62edefb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433782089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2433782089
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4004804025
Short name T458
Test name
Test status
Simulation time 5236686219 ps
CPU time 24.6 seconds
Started Jun 24 04:43:25 PM PDT 24
Finished Jun 24 04:43:54 PM PDT 24
Peak memory 219612 kb
Host smart-9bf79272-c4e7-495a-8a6c-61dfc30033c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004804025 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.4004804025
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2101861834
Short name T433
Test name
Test status
Simulation time 4311435356 ps
CPU time 30.42 seconds
Started Jun 24 04:43:19 PM PDT 24
Finished Jun 24 04:43:52 PM PDT 24
Peak memory 212344 kb
Host smart-84a3a2aa-bd19-4959-b384-bbf16c96202e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101861834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2101861834
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1384284153
Short name T364
Test name
Test status
Simulation time 32931107351 ps
CPU time 25.36 seconds
Started Jun 24 04:43:20 PM PDT 24
Finished Jun 24 04:43:48 PM PDT 24
Peak memory 211468 kb
Host smart-7ccb7043-6e8f-40d8-abc3-5dc1de695e6d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384284153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1384284153
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4162883796
Short name T438
Test name
Test status
Simulation time 9738469933 ps
CPU time 23.7 seconds
Started Jun 24 04:43:19 PM PDT 24
Finished Jun 24 04:43:45 PM PDT 24
Peak memory 211400 kb
Host smart-d2127175-dba6-4288-9737-2a91f37a593d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162883796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.4162883796
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2055155973
Short name T394
Test name
Test status
Simulation time 2738145123 ps
CPU time 47.56 seconds
Started Jun 24 04:43:19 PM PDT 24
Finished Jun 24 04:44:09 PM PDT 24
Peak memory 214524 kb
Host smart-25ab625e-5590-4788-9776-c3f895fa244c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055155973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2055155973
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1545101427
Short name T434
Test name
Test status
Simulation time 2995939328 ps
CPU time 17.32 seconds
Started Jun 24 04:43:24 PM PDT 24
Finished Jun 24 04:43:45 PM PDT 24
Peak memory 213376 kb
Host smart-e6d066ce-54a9-481b-9bf1-403c49423300
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545101427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1545101427
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.48370493
Short name T53
Test name
Test status
Simulation time 3517640194 ps
CPU time 32.94 seconds
Started Jun 24 04:43:22 PM PDT 24
Finished Jun 24 04:43:57 PM PDT 24
Peak memory 219288 kb
Host smart-dc63404e-dd8f-46dc-83f7-37776c80ae8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48370493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.48370493
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3774476949
Short name T406
Test name
Test status
Simulation time 190534077 ps
CPU time 9.15 seconds
Started Jun 24 04:43:39 PM PDT 24
Finished Jun 24 04:43:53 PM PDT 24
Peak memory 217532 kb
Host smart-bb016413-3409-4b8c-86c0-3b6b01bd66cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774476949 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3774476949
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1135345740
Short name T96
Test name
Test status
Simulation time 6349393999 ps
CPU time 27.09 seconds
Started Jun 24 04:43:26 PM PDT 24
Finished Jun 24 04:43:58 PM PDT 24
Peak memory 211624 kb
Host smart-53aebc38-3cfa-498f-971b-124c2ce6115c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135345740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1135345740
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1520368355
Short name T105
Test name
Test status
Simulation time 6972713760 ps
CPU time 50.81 seconds
Started Jun 24 04:43:38 PM PDT 24
Finished Jun 24 04:44:34 PM PDT 24
Peak memory 214332 kb
Host smart-7bae3f3f-674d-4ed7-831b-05849f029fe5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520368355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1520368355
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3865903451
Short name T97
Test name
Test status
Simulation time 602968670 ps
CPU time 12.68 seconds
Started Jun 24 04:43:39 PM PDT 24
Finished Jun 24 04:43:56 PM PDT 24
Peak memory 211528 kb
Host smart-47ab309e-c850-4088-8293-50249bc2908f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865903451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3865903451
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3106289464
Short name T409
Test name
Test status
Simulation time 11620510172 ps
CPU time 28.58 seconds
Started Jun 24 04:43:27 PM PDT 24
Finished Jun 24 04:44:00 PM PDT 24
Peak memory 219420 kb
Host smart-46352623-2780-4fad-b286-674bb0f6bca3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106289464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3106289464
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3909584045
Short name T110
Test name
Test status
Simulation time 2573248742 ps
CPU time 168.21 seconds
Started Jun 24 04:43:29 PM PDT 24
Finished Jun 24 04:46:23 PM PDT 24
Peak memory 214592 kb
Host smart-44464fc8-dd38-472a-a811-73d7c61c5947
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909584045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3909584045
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.413990038
Short name T374
Test name
Test status
Simulation time 2805411694 ps
CPU time 25.67 seconds
Started Jun 24 04:43:33 PM PDT 24
Finished Jun 24 04:44:04 PM PDT 24
Peak memory 218228 kb
Host smart-df9b7d70-c721-4480-9a3f-2ce52334fb66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413990038 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.413990038
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1515165920
Short name T89
Test name
Test status
Simulation time 11879315623 ps
CPU time 26.2 seconds
Started Jun 24 04:43:35 PM PDT 24
Finished Jun 24 04:44:06 PM PDT 24
Peak memory 213144 kb
Host smart-5131bb3d-75ec-4e40-8aff-8a40430b929c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515165920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1515165920
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.436470015
Short name T454
Test name
Test status
Simulation time 11318307445 ps
CPU time 101.77 seconds
Started Jun 24 04:43:32 PM PDT 24
Finished Jun 24 04:45:19 PM PDT 24
Peak memory 214680 kb
Host smart-95101992-8269-4fb3-a626-8f329bfb912d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436470015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.436470015
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.807634711
Short name T99
Test name
Test status
Simulation time 2628620465 ps
CPU time 22.94 seconds
Started Jun 24 04:43:32 PM PDT 24
Finished Jun 24 04:44:00 PM PDT 24
Peak memory 212760 kb
Host smart-62a86693-2a11-4582-bfbe-a41ddec152d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807634711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.807634711
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.456822
Short name T390
Test name
Test status
Simulation time 7856948117 ps
CPU time 35.94 seconds
Started Jun 24 04:43:33 PM PDT 24
Finished Jun 24 04:44:14 PM PDT 24
Peak memory 218232 kb
Host smart-2f79d162-0a1a-411d-b612-4b77460c0c73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.456822
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4103922687
Short name T376
Test name
Test status
Simulation time 186967357 ps
CPU time 9.1 seconds
Started Jun 24 04:43:35 PM PDT 24
Finished Jun 24 04:43:49 PM PDT 24
Peak memory 216848 kb
Host smart-d7189ebc-e45a-49cd-9d93-c915db2bf43d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103922687 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.4103922687
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3289925310
Short name T435
Test name
Test status
Simulation time 21446354052 ps
CPU time 24.89 seconds
Started Jun 24 04:43:34 PM PDT 24
Finished Jun 24 04:44:03 PM PDT 24
Peak memory 211592 kb
Host smart-319cd39c-c299-4d75-b00a-dff84a3c56d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289925310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3289925310
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.271970826
Short name T78
Test name
Test status
Simulation time 689058028 ps
CPU time 8.25 seconds
Started Jun 24 04:43:36 PM PDT 24
Finished Jun 24 04:43:49 PM PDT 24
Peak memory 211288 kb
Host smart-b0dcceda-d31e-480d-a94b-f081b23887f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271970826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.271970826
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3572258209
Short name T404
Test name
Test status
Simulation time 2869711482 ps
CPU time 19.75 seconds
Started Jun 24 04:43:35 PM PDT 24
Finished Jun 24 04:44:00 PM PDT 24
Peak memory 219116 kb
Host smart-13e613ad-f9f0-4ee5-92d1-925f0c9285f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572258209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3572258209
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.901049990
Short name T109
Test name
Test status
Simulation time 321470209 ps
CPU time 154.72 seconds
Started Jun 24 04:43:34 PM PDT 24
Finished Jun 24 04:46:13 PM PDT 24
Peak memory 219476 kb
Host smart-82758875-f659-4a3e-be93-554dcc974981
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901049990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.901049990
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2703333597
Short name T418
Test name
Test status
Simulation time 5921160199 ps
CPU time 18.04 seconds
Started Jun 24 04:43:34 PM PDT 24
Finished Jun 24 04:43:57 PM PDT 24
Peak memory 217336 kb
Host smart-cf11b5fe-4e23-48e7-b7bf-10943ac85cd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703333597 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2703333597
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1553592367
Short name T81
Test name
Test status
Simulation time 1870559747 ps
CPU time 19.22 seconds
Started Jun 24 04:43:36 PM PDT 24
Finished Jun 24 04:44:00 PM PDT 24
Peak memory 212272 kb
Host smart-0c955789-5918-4414-8658-b06621dac9c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553592367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1553592367
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3652139813
Short name T86
Test name
Test status
Simulation time 22637888799 ps
CPU time 188.21 seconds
Started Jun 24 04:43:32 PM PDT 24
Finished Jun 24 04:46:45 PM PDT 24
Peak memory 216148 kb
Host smart-a0c6a004-d0d2-42cf-baa0-62007f4da677
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652139813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3652139813
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2153984369
Short name T95
Test name
Test status
Simulation time 339085764 ps
CPU time 8.35 seconds
Started Jun 24 04:43:35 PM PDT 24
Finished Jun 24 04:43:49 PM PDT 24
Peak memory 211964 kb
Host smart-95f4a2b8-5d4d-43b6-a7ad-c75b07365106
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153984369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2153984369
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2923940972
Short name T363
Test name
Test status
Simulation time 9217496293 ps
CPU time 25.32 seconds
Started Jun 24 04:43:34 PM PDT 24
Finished Jun 24 04:44:04 PM PDT 24
Peak memory 217988 kb
Host smart-5a91b824-8ea2-4d75-a680-f4c520a8975a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923940972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2923940972
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1771265447
Short name T439
Test name
Test status
Simulation time 3625613108 ps
CPU time 28.6 seconds
Started Jun 24 04:43:32 PM PDT 24
Finished Jun 24 04:44:06 PM PDT 24
Peak memory 219548 kb
Host smart-845045e8-9ef3-486a-8360-a3674a6f931b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771265447 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1771265447
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1449463691
Short name T91
Test name
Test status
Simulation time 917042734 ps
CPU time 8.14 seconds
Started Jun 24 04:43:33 PM PDT 24
Finished Jun 24 04:43:46 PM PDT 24
Peak memory 211680 kb
Host smart-b4634689-3504-4d5d-af7a-de73487b60f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449463691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1449463691
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2162609954
Short name T408
Test name
Test status
Simulation time 8198870653 ps
CPU time 24.93 seconds
Started Jun 24 04:43:31 PM PDT 24
Finished Jun 24 04:44:00 PM PDT 24
Peak memory 213416 kb
Host smart-390d907d-ad45-4551-8138-efab67de2dab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162609954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2162609954
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1865705732
Short name T455
Test name
Test status
Simulation time 16018264384 ps
CPU time 33.79 seconds
Started Jun 24 04:43:35 PM PDT 24
Finished Jun 24 04:44:14 PM PDT 24
Peak memory 217644 kb
Host smart-6491961f-ed40-4d82-b912-af08cbe4f26d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865705732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1865705732
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.383189002
Short name T419
Test name
Test status
Simulation time 290760104 ps
CPU time 155.06 seconds
Started Jun 24 04:43:37 PM PDT 24
Finished Jun 24 04:46:17 PM PDT 24
Peak memory 215500 kb
Host smart-49aee6e5-5ca3-40c4-9c96-85e5570cecad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383189002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.383189002
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3905338962
Short name T65
Test name
Test status
Simulation time 4076307310 ps
CPU time 31.08 seconds
Started Jun 24 04:43:33 PM PDT 24
Finished Jun 24 04:44:09 PM PDT 24
Peak memory 215012 kb
Host smart-62eb9789-5ee9-4761-a2c7-5b2e4c30eea6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905338962 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3905338962
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2245789906
Short name T102
Test name
Test status
Simulation time 3125617224 ps
CPU time 27.2 seconds
Started Jun 24 04:43:33 PM PDT 24
Finished Jun 24 04:44:04 PM PDT 24
Peak memory 212016 kb
Host smart-77d9709f-0010-4756-bf8b-fed28072e5f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245789906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2245789906
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4065104676
Short name T94
Test name
Test status
Simulation time 8313060434 ps
CPU time 85.75 seconds
Started Jun 24 04:43:35 PM PDT 24
Finished Jun 24 04:45:06 PM PDT 24
Peak memory 215292 kb
Host smart-98df0eee-dac1-4ef1-90ed-19c46ec3f4e3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065104676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.4065104676
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.924627105
Short name T411
Test name
Test status
Simulation time 3183185942 ps
CPU time 26.34 seconds
Started Jun 24 04:43:35 PM PDT 24
Finished Jun 24 04:44:07 PM PDT 24
Peak memory 212816 kb
Host smart-4571ab15-537b-4183-ac0f-8b7e3462d059
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924627105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.924627105
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.333120732
Short name T383
Test name
Test status
Simulation time 6822236077 ps
CPU time 21.59 seconds
Started Jun 24 04:43:35 PM PDT 24
Finished Jun 24 04:44:01 PM PDT 24
Peak memory 219528 kb
Host smart-1396cdef-ea6e-4d23-8054-dcc42bb449aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333120732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.333120732
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1083242004
Short name T61
Test name
Test status
Simulation time 3989673813 ps
CPU time 175.06 seconds
Started Jun 24 04:43:32 PM PDT 24
Finished Jun 24 04:46:31 PM PDT 24
Peak memory 214640 kb
Host smart-534daf67-3db6-4560-b00d-87d1a0de13eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083242004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1083242004
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1981820527
Short name T365
Test name
Test status
Simulation time 2774861583 ps
CPU time 9.94 seconds
Started Jun 24 04:43:32 PM PDT 24
Finished Jun 24 04:43:47 PM PDT 24
Peak memory 214284 kb
Host smart-a3b3b806-bdfd-4044-bed5-7e9949191691
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981820527 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1981820527
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3760567250
Short name T392
Test name
Test status
Simulation time 27532879416 ps
CPU time 29.87 seconds
Started Jun 24 04:43:34 PM PDT 24
Finished Jun 24 04:44:09 PM PDT 24
Peak memory 212980 kb
Host smart-b382ab05-6770-4a80-94f0-80e05038405e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760567250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3760567250
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2144362998
Short name T73
Test name
Test status
Simulation time 160439785857 ps
CPU time 129.07 seconds
Started Jun 24 04:43:34 PM PDT 24
Finished Jun 24 04:45:48 PM PDT 24
Peak memory 214528 kb
Host smart-0e75b369-1b68-46d7-aaa6-12cace8133e5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144362998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2144362998
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2334679660
Short name T98
Test name
Test status
Simulation time 12778909056 ps
CPU time 27.15 seconds
Started Jun 24 04:43:32 PM PDT 24
Finished Jun 24 04:44:04 PM PDT 24
Peak memory 212988 kb
Host smart-7b7724bd-4d22-479f-a57e-e762258c36b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334679660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2334679660
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2574438541
Short name T382
Test name
Test status
Simulation time 4100663692 ps
CPU time 38.34 seconds
Started Jun 24 04:43:35 PM PDT 24
Finished Jun 24 04:44:19 PM PDT 24
Peak memory 217892 kb
Host smart-5b6cf9cf-0506-4c74-a6f1-c81f64c74de2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574438541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2574438541
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2206684478
Short name T113
Test name
Test status
Simulation time 62652690247 ps
CPU time 99.45 seconds
Started Jun 24 04:43:32 PM PDT 24
Finished Jun 24 04:45:16 PM PDT 24
Peak memory 214784 kb
Host smart-c5bc6fb4-09be-4027-9147-b96ab85499b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206684478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2206684478
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3989584773
Short name T427
Test name
Test status
Simulation time 421394055 ps
CPU time 11.78 seconds
Started Jun 24 04:43:37 PM PDT 24
Finished Jun 24 04:43:54 PM PDT 24
Peak memory 215436 kb
Host smart-f27f02c0-0329-47c4-9229-aa09475aaeda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989584773 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3989584773
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3344501438
Short name T387
Test name
Test status
Simulation time 4320290435 ps
CPU time 32.85 seconds
Started Jun 24 04:43:34 PM PDT 24
Finished Jun 24 04:44:12 PM PDT 24
Peak memory 212252 kb
Host smart-fbb5914f-e2e3-44c7-9a89-5da94d4850f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344501438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3344501438
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.539102762
Short name T412
Test name
Test status
Simulation time 11191253658 ps
CPU time 101.3 seconds
Started Jun 24 04:43:34 PM PDT 24
Finished Jun 24 04:45:20 PM PDT 24
Peak memory 214868 kb
Host smart-6d6a13e8-80b9-44ae-8ffa-d376bc8c150b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539102762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.539102762
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2217734650
Short name T403
Test name
Test status
Simulation time 3378089958 ps
CPU time 26.99 seconds
Started Jun 24 04:43:33 PM PDT 24
Finished Jun 24 04:44:04 PM PDT 24
Peak memory 213004 kb
Host smart-460b47fc-26f3-4f8c-8958-0677686c3190
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217734650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2217734650
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3155801391
Short name T422
Test name
Test status
Simulation time 5387622687 ps
CPU time 29.44 seconds
Started Jun 24 04:43:33 PM PDT 24
Finished Jun 24 04:44:07 PM PDT 24
Peak memory 219544 kb
Host smart-9bed552b-270a-4b04-b16a-c4bcb8668e5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155801391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3155801391
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.899117651
Short name T410
Test name
Test status
Simulation time 757972831 ps
CPU time 84.82 seconds
Started Jun 24 04:43:34 PM PDT 24
Finished Jun 24 04:45:04 PM PDT 24
Peak memory 215172 kb
Host smart-ddafac1d-fb08-4a63-bd23-343d45896fab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899117651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.899117651
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1322617983
Short name T367
Test name
Test status
Simulation time 10909946196 ps
CPU time 25 seconds
Started Jun 24 04:43:35 PM PDT 24
Finished Jun 24 04:44:05 PM PDT 24
Peak memory 216032 kb
Host smart-b203a4b0-8a3f-401a-b475-18359c946846
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322617983 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1322617983
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.87570090
Short name T414
Test name
Test status
Simulation time 344434199 ps
CPU time 10.53 seconds
Started Jun 24 04:43:34 PM PDT 24
Finished Jun 24 04:43:49 PM PDT 24
Peak memory 211460 kb
Host smart-740ae7e0-57a1-4c4a-8e9e-d5bd1213bb3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87570090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.87570090
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.801293273
Short name T402
Test name
Test status
Simulation time 1619237669 ps
CPU time 57.11 seconds
Started Jun 24 04:43:34 PM PDT 24
Finished Jun 24 04:44:36 PM PDT 24
Peak memory 215620 kb
Host smart-0b2fda21-0676-4489-bf50-6c177a432553
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801293273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.801293273
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3821624009
Short name T415
Test name
Test status
Simulation time 826974675 ps
CPU time 8.58 seconds
Started Jun 24 04:43:34 PM PDT 24
Finished Jun 24 04:43:48 PM PDT 24
Peak memory 212064 kb
Host smart-2ea8c8d1-aa42-4f19-ad99-accb1f6f4497
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821624009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3821624009
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1610319904
Short name T424
Test name
Test status
Simulation time 8203220345 ps
CPU time 34.49 seconds
Started Jun 24 04:43:32 PM PDT 24
Finished Jun 24 04:44:11 PM PDT 24
Peak memory 218076 kb
Host smart-b4e0fe0b-27e0-4b94-b2ae-8ce087fd19ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610319904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1610319904
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2137199341
Short name T366
Test name
Test status
Simulation time 31107384565 ps
CPU time 28.69 seconds
Started Jun 24 04:43:33 PM PDT 24
Finished Jun 24 04:44:07 PM PDT 24
Peak memory 216708 kb
Host smart-e93ab32a-7902-460f-93b6-8af29b33e6b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137199341 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2137199341
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1487367731
Short name T75
Test name
Test status
Simulation time 999009186 ps
CPU time 14.63 seconds
Started Jun 24 04:43:34 PM PDT 24
Finished Jun 24 04:43:53 PM PDT 24
Peak memory 211348 kb
Host smart-ec82547c-9237-4c8f-acbb-1c687c076262
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487367731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1487367731
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4047240370
Short name T416
Test name
Test status
Simulation time 15743657379 ps
CPU time 124.52 seconds
Started Jun 24 04:43:37 PM PDT 24
Finished Jun 24 04:45:46 PM PDT 24
Peak memory 214936 kb
Host smart-c6f5effd-49bc-4f26-a6f0-f88a4aa526ca
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047240370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.4047240370
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.546312660
Short name T82
Test name
Test status
Simulation time 4994214718 ps
CPU time 23.16 seconds
Started Jun 24 04:43:36 PM PDT 24
Finished Jun 24 04:44:05 PM PDT 24
Peak memory 211968 kb
Host smart-6179509d-2131-44f6-a631-31b5eb340624
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546312660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.546312660
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3784206692
Short name T437
Test name
Test status
Simulation time 3744288358 ps
CPU time 23.21 seconds
Started Jun 24 04:43:34 PM PDT 24
Finished Jun 24 04:44:02 PM PDT 24
Peak memory 219192 kb
Host smart-805829b6-2368-4f38-8cf3-2e4656170811
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784206692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3784206692
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2858365759
Short name T117
Test name
Test status
Simulation time 4826371736 ps
CPU time 174.85 seconds
Started Jun 24 04:43:33 PM PDT 24
Finished Jun 24 04:46:33 PM PDT 24
Peak memory 219600 kb
Host smart-b1857a7f-b419-4761-9d1c-4df48aa11d60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858365759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2858365759
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.497774246
Short name T100
Test name
Test status
Simulation time 662094107 ps
CPU time 8.02 seconds
Started Jun 24 04:43:25 PM PDT 24
Finished Jun 24 04:43:38 PM PDT 24
Peak memory 211604 kb
Host smart-d4d9b138-4752-4ded-96da-30e3a1376840
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497774246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.497774246
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1469550824
Short name T405
Test name
Test status
Simulation time 5783542709 ps
CPU time 18.13 seconds
Started Jun 24 04:43:26 PM PDT 24
Finished Jun 24 04:43:49 PM PDT 24
Peak memory 212108 kb
Host smart-24dd0842-c0cb-4ba1-8158-b8ebb26016ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469550824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1469550824
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3216921586
Short name T76
Test name
Test status
Simulation time 18032135281 ps
CPU time 39.05 seconds
Started Jun 24 04:43:28 PM PDT 24
Finished Jun 24 04:44:12 PM PDT 24
Peak memory 212824 kb
Host smart-0f57db4b-def9-4bc9-9278-dcc3173d1f0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216921586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3216921586
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3105771594
Short name T449
Test name
Test status
Simulation time 6519554346 ps
CPU time 27.53 seconds
Started Jun 24 04:43:26 PM PDT 24
Finished Jun 24 04:43:58 PM PDT 24
Peak memory 217320 kb
Host smart-dbac74df-6e70-4df3-ab7b-498d68e74986
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105771594 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3105771594
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.736765631
Short name T421
Test name
Test status
Simulation time 12509148885 ps
CPU time 29.04 seconds
Started Jun 24 04:43:26 PM PDT 24
Finished Jun 24 04:43:59 PM PDT 24
Peak memory 212576 kb
Host smart-bc9c800f-b8c8-4c47-94d1-e3372e50f3fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736765631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.736765631
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3590207032
Short name T362
Test name
Test status
Simulation time 6715515871 ps
CPU time 27.7 seconds
Started Jun 24 04:43:23 PM PDT 24
Finished Jun 24 04:43:54 PM PDT 24
Peak memory 211592 kb
Host smart-d37bb68d-18a4-4075-8e20-c5ed752870f1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590207032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3590207032
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1238271522
Short name T370
Test name
Test status
Simulation time 11658397378 ps
CPU time 25.33 seconds
Started Jun 24 04:43:27 PM PDT 24
Finished Jun 24 04:43:56 PM PDT 24
Peak memory 211324 kb
Host smart-237e5805-8873-425e-9109-ec341de1a994
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238271522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1238271522
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2573309336
Short name T445
Test name
Test status
Simulation time 23614981382 ps
CPU time 187.81 seconds
Started Jun 24 04:43:27 PM PDT 24
Finished Jun 24 04:46:39 PM PDT 24
Peak memory 215852 kb
Host smart-ea300a1a-cc82-49c8-a436-061cf905514c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573309336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2573309336
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4267787225
Short name T440
Test name
Test status
Simulation time 6341904642 ps
CPU time 17.03 seconds
Started Jun 24 04:43:27 PM PDT 24
Finished Jun 24 04:43:48 PM PDT 24
Peak memory 213044 kb
Host smart-65ffe625-b324-4c24-a3e0-1865b02c6f73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267787225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.4267787225
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1379550281
Short name T375
Test name
Test status
Simulation time 2881072690 ps
CPU time 24.93 seconds
Started Jun 24 04:43:23 PM PDT 24
Finished Jun 24 04:43:51 PM PDT 24
Peak memory 219504 kb
Host smart-67c9808a-dccf-49c0-b8f4-ab05eabb3a8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379550281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1379550281
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4122604870
Short name T106
Test name
Test status
Simulation time 588674178 ps
CPU time 152.81 seconds
Started Jun 24 04:43:25 PM PDT 24
Finished Jun 24 04:46:01 PM PDT 24
Peak memory 219476 kb
Host smart-a4f7f77e-d70f-4cc6-beea-36599d60870f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122604870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.4122604870
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2203620376
Short name T420
Test name
Test status
Simulation time 958103216 ps
CPU time 11.22 seconds
Started Jun 24 04:43:38 PM PDT 24
Finished Jun 24 04:43:54 PM PDT 24
Peak memory 211120 kb
Host smart-636a5380-f9c3-4ed1-b46c-139a97401d10
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203620376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2203620376
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3155970503
Short name T393
Test name
Test status
Simulation time 15162401632 ps
CPU time 27.84 seconds
Started Jun 24 04:43:25 PM PDT 24
Finished Jun 24 04:43:57 PM PDT 24
Peak memory 211680 kb
Host smart-0d853db2-0de0-4df3-bae6-eda5fc828a54
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155970503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3155970503
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1592119295
Short name T64
Test name
Test status
Simulation time 32194790211 ps
CPU time 34.9 seconds
Started Jun 24 04:43:39 PM PDT 24
Finished Jun 24 04:44:18 PM PDT 24
Peak memory 212480 kb
Host smart-ab29ead8-5066-4c6a-ace6-9f2ea8b71156
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592119295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1592119295
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3950928898
Short name T446
Test name
Test status
Simulation time 177933736 ps
CPU time 8.69 seconds
Started Jun 24 04:43:27 PM PDT 24
Finished Jun 24 04:43:41 PM PDT 24
Peak memory 215356 kb
Host smart-2bc5cb86-e255-47e5-9f7a-1f901d654820
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950928898 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3950928898
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3716753033
Short name T457
Test name
Test status
Simulation time 4355997302 ps
CPU time 20.82 seconds
Started Jun 24 04:43:26 PM PDT 24
Finished Jun 24 04:43:51 PM PDT 24
Peak memory 212884 kb
Host smart-658163a4-987d-4199-a617-8eb5f23600ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716753033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3716753033
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1625733673
Short name T379
Test name
Test status
Simulation time 3830570286 ps
CPU time 29.6 seconds
Started Jun 24 04:43:26 PM PDT 24
Finished Jun 24 04:44:01 PM PDT 24
Peak memory 211196 kb
Host smart-e3b915ca-03e0-4521-b1c7-ade2df04e031
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625733673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1625733673
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.825716644
Short name T377
Test name
Test status
Simulation time 6213208860 ps
CPU time 26.38 seconds
Started Jun 24 04:43:31 PM PDT 24
Finished Jun 24 04:44:02 PM PDT 24
Peak memory 211228 kb
Host smart-47a6e003-def5-4a75-967f-2b86f0fa50c0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825716644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
825716644
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2282647938
Short name T92
Test name
Test status
Simulation time 5001129602 ps
CPU time 72.46 seconds
Started Jun 24 04:43:28 PM PDT 24
Finished Jun 24 04:44:45 PM PDT 24
Peak memory 219268 kb
Host smart-97b546fe-b27d-4e43-a68d-2c045afa3d44
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282647938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2282647938
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1691393820
Short name T66
Test name
Test status
Simulation time 4216494874 ps
CPU time 31.4 seconds
Started Jun 24 04:43:25 PM PDT 24
Finished Jun 24 04:44:01 PM PDT 24
Peak memory 212864 kb
Host smart-27cff691-a1ce-4423-ab34-49a93e4c74f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691393820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1691393820
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1895284665
Short name T389
Test name
Test status
Simulation time 3357188373 ps
CPU time 32.6 seconds
Started Jun 24 04:43:27 PM PDT 24
Finished Jun 24 04:44:04 PM PDT 24
Peak memory 219036 kb
Host smart-a575390d-f4fc-4a63-b699-aa057bbf8f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895284665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1895284665
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3503663760
Short name T453
Test name
Test status
Simulation time 1131520434 ps
CPU time 82.87 seconds
Started Jun 24 04:43:26 PM PDT 24
Finished Jun 24 04:44:53 PM PDT 24
Peak memory 215308 kb
Host smart-4734d19c-9b07-4dd0-a202-0d2e2c34af38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503663760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3503663760
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3565252993
Short name T425
Test name
Test status
Simulation time 635649615 ps
CPU time 8.78 seconds
Started Jun 24 04:43:24 PM PDT 24
Finished Jun 24 04:43:36 PM PDT 24
Peak memory 211308 kb
Host smart-febf262d-d716-4726-b27b-9dc010e3d641
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565252993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3565252993
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3098549778
Short name T373
Test name
Test status
Simulation time 167638577 ps
CPU time 8.34 seconds
Started Jun 24 04:43:27 PM PDT 24
Finished Jun 24 04:43:40 PM PDT 24
Peak memory 211408 kb
Host smart-3132994a-5561-4ad0-ba68-43e993bb1115
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098549778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3098549778
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2593557664
Short name T79
Test name
Test status
Simulation time 8530198891 ps
CPU time 25.16 seconds
Started Jun 24 04:43:27 PM PDT 24
Finished Jun 24 04:43:56 PM PDT 24
Peak memory 212352 kb
Host smart-c223a8b3-a7fd-4a1e-b206-b1820c6c256f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593557664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2593557664
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1677909317
Short name T391
Test name
Test status
Simulation time 4956496952 ps
CPU time 22.63 seconds
Started Jun 24 04:43:38 PM PDT 24
Finished Jun 24 04:44:06 PM PDT 24
Peak memory 219648 kb
Host smart-099167bf-8aff-43b8-b001-39ba34adb9bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677909317 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1677909317
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.750850458
Short name T397
Test name
Test status
Simulation time 167482888 ps
CPU time 8.16 seconds
Started Jun 24 04:43:29 PM PDT 24
Finished Jun 24 04:43:42 PM PDT 24
Peak memory 211028 kb
Host smart-87880feb-56e8-45cb-8bc8-920b11caf83a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750850458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.750850458
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2708331225
Short name T369
Test name
Test status
Simulation time 2058398389 ps
CPU time 20.51 seconds
Started Jun 24 04:43:28 PM PDT 24
Finished Jun 24 04:43:53 PM PDT 24
Peak memory 211136 kb
Host smart-77c4d5d7-f1fb-49aa-a198-eb7f649c00e8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708331225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2708331225
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4074044508
Short name T401
Test name
Test status
Simulation time 368957981 ps
CPU time 8.01 seconds
Started Jun 24 04:43:28 PM PDT 24
Finished Jun 24 04:43:41 PM PDT 24
Peak memory 211136 kb
Host smart-5d2a8425-432b-433b-99ed-86addbc3c2ed
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074044508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.4074044508
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1182112000
Short name T407
Test name
Test status
Simulation time 16682860539 ps
CPU time 51.83 seconds
Started Jun 24 04:43:26 PM PDT 24
Finished Jun 24 04:44:23 PM PDT 24
Peak memory 219592 kb
Host smart-e77ffa35-3dc9-4e35-ad51-50be0b72cb63
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182112000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1182112000
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2446816887
Short name T448
Test name
Test status
Simulation time 4373244103 ps
CPU time 25.57 seconds
Started Jun 24 04:43:25 PM PDT 24
Finished Jun 24 04:43:54 PM PDT 24
Peak memory 213364 kb
Host smart-53623c10-0a40-4123-8b2e-1aa9d792d1b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446816887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2446816887
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2650592867
Short name T396
Test name
Test status
Simulation time 2312312651 ps
CPU time 17.45 seconds
Started Jun 24 04:43:26 PM PDT 24
Finished Jun 24 04:43:48 PM PDT 24
Peak memory 219076 kb
Host smart-e72b0b32-4db6-4099-afc5-67e8fd0b672e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650592867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2650592867
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4223476458
Short name T107
Test name
Test status
Simulation time 3081989397 ps
CPU time 170.53 seconds
Started Jun 24 04:43:28 PM PDT 24
Finished Jun 24 04:46:23 PM PDT 24
Peak memory 214620 kb
Host smart-bdee8822-2b20-46b9-b1e7-2f1293f70031
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223476458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.4223476458
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3997957820
Short name T426
Test name
Test status
Simulation time 2225639496 ps
CPU time 10.85 seconds
Started Jun 24 04:43:27 PM PDT 24
Finished Jun 24 04:43:42 PM PDT 24
Peak memory 215624 kb
Host smart-b4ef3f93-442c-410f-8702-fe69b08f5ab2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997957820 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3997957820
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.221453382
Short name T431
Test name
Test status
Simulation time 2492214606 ps
CPU time 22.04 seconds
Started Jun 24 04:43:26 PM PDT 24
Finished Jun 24 04:43:52 PM PDT 24
Peak memory 212720 kb
Host smart-ec2ff89a-c130-4e97-b4d5-04a01fd564dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221453382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.221453382
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3095395134
Short name T87
Test name
Test status
Simulation time 1115730480 ps
CPU time 56.43 seconds
Started Jun 24 04:43:27 PM PDT 24
Finished Jun 24 04:44:28 PM PDT 24
Peak memory 219596 kb
Host smart-65ba1fbf-3ef4-45e7-93e3-505079c25963
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095395134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3095395134
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3835721418
Short name T432
Test name
Test status
Simulation time 14658986585 ps
CPU time 29.31 seconds
Started Jun 24 04:43:29 PM PDT 24
Finished Jun 24 04:44:04 PM PDT 24
Peak memory 212792 kb
Host smart-f4d6b4e5-7dc7-4a65-ad37-9de7751538d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835721418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3835721418
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.557235720
Short name T395
Test name
Test status
Simulation time 3042331219 ps
CPU time 29.96 seconds
Started Jun 24 04:43:25 PM PDT 24
Finished Jun 24 04:43:58 PM PDT 24
Peak memory 219072 kb
Host smart-806fe499-6e7a-4670-9dc1-4aef8062bd96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557235720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.557235720
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3524893697
Short name T444
Test name
Test status
Simulation time 5057694000 ps
CPU time 87.15 seconds
Started Jun 24 04:43:25 PM PDT 24
Finished Jun 24 04:44:56 PM PDT 24
Peak memory 219600 kb
Host smart-03eac8c3-f7d4-442c-81fa-aabbb5ce7592
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524893697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3524893697
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3362104144
Short name T430
Test name
Test status
Simulation time 1357050494 ps
CPU time 13.35 seconds
Started Jun 24 04:43:26 PM PDT 24
Finished Jun 24 04:43:44 PM PDT 24
Peak memory 217752 kb
Host smart-79382398-e943-406f-bbad-46342fbb1986
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362104144 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3362104144
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1524986472
Short name T90
Test name
Test status
Simulation time 1031254507 ps
CPU time 12.3 seconds
Started Jun 24 04:43:28 PM PDT 24
Finished Jun 24 04:43:45 PM PDT 24
Peak memory 211244 kb
Host smart-b04a02ac-c790-4014-a5f4-254f66a16398
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524986472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1524986472
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3561462544
Short name T441
Test name
Test status
Simulation time 4308320318 ps
CPU time 56.94 seconds
Started Jun 24 04:43:28 PM PDT 24
Finished Jun 24 04:44:30 PM PDT 24
Peak memory 215872 kb
Host smart-81896a55-b017-44fd-bdfd-bc75601bdf88
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561462544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3561462544
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3833285595
Short name T423
Test name
Test status
Simulation time 2237540896 ps
CPU time 22.06 seconds
Started Jun 24 04:43:26 PM PDT 24
Finished Jun 24 04:43:52 PM PDT 24
Peak memory 213024 kb
Host smart-1b194571-ad12-4764-825e-c084c2ff9031
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833285595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3833285595
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3245674525
Short name T429
Test name
Test status
Simulation time 3731076790 ps
CPU time 32.53 seconds
Started Jun 24 04:43:25 PM PDT 24
Finished Jun 24 04:44:00 PM PDT 24
Peak memory 219544 kb
Host smart-cd514e54-7db0-42cc-be80-47aab454eb4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245674525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3245674525
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2240836848
Short name T398
Test name
Test status
Simulation time 4026955682 ps
CPU time 103.26 seconds
Started Jun 24 04:43:27 PM PDT 24
Finished Jun 24 04:45:14 PM PDT 24
Peak memory 214224 kb
Host smart-5d0b7085-794b-44f2-a663-c4a28f7f66ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240836848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2240836848
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2828364288
Short name T399
Test name
Test status
Simulation time 56385800835 ps
CPU time 30.29 seconds
Started Jun 24 04:43:24 PM PDT 24
Finished Jun 24 04:43:57 PM PDT 24
Peak memory 218088 kb
Host smart-7b0e8f39-206d-4ba8-89a4-36b29cdac1d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828364288 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2828364288
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.955117333
Short name T88
Test name
Test status
Simulation time 174321317 ps
CPU time 8.28 seconds
Started Jun 24 04:43:25 PM PDT 24
Finished Jun 24 04:43:38 PM PDT 24
Peak memory 211252 kb
Host smart-c78d00bb-28c3-49ae-92a1-a8e399bdfde9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955117333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.955117333
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1154495275
Short name T428
Test name
Test status
Simulation time 3270372297 ps
CPU time 30.1 seconds
Started Jun 24 04:43:26 PM PDT 24
Finished Jun 24 04:44:01 PM PDT 24
Peak memory 211744 kb
Host smart-bf1d9800-e05e-4743-b620-64af1d95bc65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154495275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1154495275
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3939033517
Short name T385
Test name
Test status
Simulation time 13164570315 ps
CPU time 31.39 seconds
Started Jun 24 04:43:25 PM PDT 24
Finished Jun 24 04:44:01 PM PDT 24
Peak memory 219548 kb
Host smart-bdf5ea38-e104-46b4-b177-22df12a31efb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939033517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3939033517
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1203230988
Short name T115
Test name
Test status
Simulation time 1862496171 ps
CPU time 161.82 seconds
Started Jun 24 04:43:27 PM PDT 24
Finished Jun 24 04:46:14 PM PDT 24
Peak memory 219500 kb
Host smart-09293bf7-5049-4eeb-94bc-7352ce460f0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203230988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1203230988
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3711301966
Short name T452
Test name
Test status
Simulation time 364844659 ps
CPU time 9.26 seconds
Started Jun 24 04:43:26 PM PDT 24
Finished Jun 24 04:43:39 PM PDT 24
Peak memory 219532 kb
Host smart-55cd574d-488b-444f-af1b-122a53e018bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711301966 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3711301966
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3165233426
Short name T386
Test name
Test status
Simulation time 7150516138 ps
CPU time 19.31 seconds
Started Jun 24 04:43:27 PM PDT 24
Finished Jun 24 04:43:51 PM PDT 24
Peak memory 211832 kb
Host smart-2aac4bfb-3ee4-4879-b309-4f0b98e75d0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165233426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3165233426
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1090417977
Short name T380
Test name
Test status
Simulation time 2152943581 ps
CPU time 56.96 seconds
Started Jun 24 04:43:27 PM PDT 24
Finished Jun 24 04:44:29 PM PDT 24
Peak memory 214540 kb
Host smart-4d8ea581-4492-4090-b30a-6b412b07f490
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090417977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1090417977
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1533899652
Short name T443
Test name
Test status
Simulation time 9507766962 ps
CPU time 21.86 seconds
Started Jun 24 04:43:28 PM PDT 24
Finished Jun 24 04:43:55 PM PDT 24
Peak memory 213240 kb
Host smart-1be3edaa-6eaf-4c38-b8ee-adab1df5566d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533899652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1533899652
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1261408742
Short name T450
Test name
Test status
Simulation time 15372800779 ps
CPU time 31.2 seconds
Started Jun 24 04:43:23 PM PDT 24
Finished Jun 24 04:43:56 PM PDT 24
Peak memory 219548 kb
Host smart-595543f0-b314-485f-90d4-31bc802490ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261408742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1261408742
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4234933367
Short name T63
Test name
Test status
Simulation time 4801209293 ps
CPU time 88.04 seconds
Started Jun 24 04:43:27 PM PDT 24
Finished Jun 24 04:45:00 PM PDT 24
Peak memory 219692 kb
Host smart-7df7b624-aae5-4e10-ad93-9badd1b4d9f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234933367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.4234933367
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4066195481
Short name T456
Test name
Test status
Simulation time 17228126647 ps
CPU time 33.6 seconds
Started Jun 24 04:43:27 PM PDT 24
Finished Jun 24 04:44:06 PM PDT 24
Peak memory 218876 kb
Host smart-d665bb36-4fd4-48f6-b8f6-08497031cd46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066195481 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.4066195481
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3544772497
Short name T371
Test name
Test status
Simulation time 2931022473 ps
CPU time 25.62 seconds
Started Jun 24 04:43:38 PM PDT 24
Finished Jun 24 04:44:09 PM PDT 24
Peak memory 212056 kb
Host smart-11aa98c3-4f6b-415d-98b4-3567abb4721c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544772497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3544772497
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1437880486
Short name T101
Test name
Test status
Simulation time 117204294109 ps
CPU time 132.47 seconds
Started Jun 24 04:43:27 PM PDT 24
Finished Jun 24 04:45:45 PM PDT 24
Peak memory 219624 kb
Host smart-0085a2bf-9acd-482b-9e89-a8d43484d116
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437880486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1437880486
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2831970445
Short name T451
Test name
Test status
Simulation time 332564050 ps
CPU time 8.47 seconds
Started Jun 24 04:43:31 PM PDT 24
Finished Jun 24 04:43:44 PM PDT 24
Peak memory 211744 kb
Host smart-511fa0a5-6fa5-4694-82c8-0261f666cf42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831970445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2831970445
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1071768960
Short name T378
Test name
Test status
Simulation time 3260537725 ps
CPU time 32.61 seconds
Started Jun 24 04:43:27 PM PDT 24
Finished Jun 24 04:44:06 PM PDT 24
Peak memory 218092 kb
Host smart-02bf83b3-b146-4e45-9384-2086108c0aa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071768960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1071768960
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.369859715
Short name T112
Test name
Test status
Simulation time 15757334554 ps
CPU time 102.11 seconds
Started Jun 24 04:43:38 PM PDT 24
Finished Jun 24 04:45:25 PM PDT 24
Peak memory 219228 kb
Host smart-0f2ed5c9-d870-4f5d-a63f-83ed34f29587
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369859715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.369859715
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2261918751
Short name T247
Test name
Test status
Simulation time 2774186219 ps
CPU time 24.01 seconds
Started Jun 24 04:43:38 PM PDT 24
Finished Jun 24 04:44:07 PM PDT 24
Peak memory 216816 kb
Host smart-06ff5a4b-b508-4c8e-978c-65b7a780ed90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261918751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2261918751
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1945418429
Short name T164
Test name
Test status
Simulation time 96667216976 ps
CPU time 393.33 seconds
Started Jun 24 04:43:34 PM PDT 24
Finished Jun 24 04:50:12 PM PDT 24
Peak memory 238756 kb
Host smart-7438bfcc-fa9f-4f53-8398-d759be5a69ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945418429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1945418429
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3965051028
Short name T142
Test name
Test status
Simulation time 50189614994 ps
CPU time 59.83 seconds
Started Jun 24 04:43:33 PM PDT 24
Finished Jun 24 04:44:38 PM PDT 24
Peak memory 219088 kb
Host smart-7ef1c11f-406d-47b4-858b-697a0d720a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965051028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3965051028
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2749410533
Short name T283
Test name
Test status
Simulation time 2462290801 ps
CPU time 24.65 seconds
Started Jun 24 04:43:36 PM PDT 24
Finished Jun 24 04:44:05 PM PDT 24
Peak memory 211248 kb
Host smart-56075de5-f546-4d23-af11-0f3de2bc53fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2749410533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2749410533
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2894076814
Short name T272
Test name
Test status
Simulation time 6680376505 ps
CPU time 66.01 seconds
Started Jun 24 04:43:33 PM PDT 24
Finished Jun 24 04:44:43 PM PDT 24
Peak memory 217296 kb
Host smart-1cfa4063-5a63-484e-9092-c2da96599c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894076814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2894076814
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2948432327
Short name T207
Test name
Test status
Simulation time 29963418004 ps
CPU time 174.07 seconds
Started Jun 24 04:43:36 PM PDT 24
Finished Jun 24 04:46:35 PM PDT 24
Peak memory 221888 kb
Host smart-9cfdbc71-a350-4aa9-a7d8-1bc0f1185c52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948432327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2948432327
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2079544675
Short name T266
Test name
Test status
Simulation time 4205259900 ps
CPU time 15.97 seconds
Started Jun 24 04:43:40 PM PDT 24
Finished Jun 24 04:44:01 PM PDT 24
Peak memory 217048 kb
Host smart-59c528a8-9c84-416e-ba69-7731023ea49a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079544675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2079544675
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.937456486
Short name T277
Test name
Test status
Simulation time 21867355373 ps
CPU time 291.97 seconds
Started Jun 24 04:43:44 PM PDT 24
Finished Jun 24 04:48:41 PM PDT 24
Peak memory 236640 kb
Host smart-6e8b3828-0c13-41fc-8012-3524951b3930
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937456486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.937456486
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.569378835
Short name T166
Test name
Test status
Simulation time 3934462629 ps
CPU time 43.66 seconds
Started Jun 24 04:43:40 PM PDT 24
Finished Jun 24 04:44:28 PM PDT 24
Peak memory 219132 kb
Host smart-a3673120-03d9-462e-b9d7-473aa22761a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569378835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.569378835
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3762326764
Short name T15
Test name
Test status
Simulation time 7739931409 ps
CPU time 32.74 seconds
Started Jun 24 04:43:41 PM PDT 24
Finished Jun 24 04:44:19 PM PDT 24
Peak memory 211556 kb
Host smart-a3b57500-c0c5-4177-8a90-fdfad0ec5d08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3762326764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3762326764
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2038845438
Short name T17
Test name
Test status
Simulation time 1524520415 ps
CPU time 237.8 seconds
Started Jun 24 04:43:41 PM PDT 24
Finished Jun 24 04:47:44 PM PDT 24
Peak memory 237248 kb
Host smart-32330471-f33d-434d-bdb0-3a98eeb01bf0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038845438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2038845438
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.4293199213
Short name T208
Test name
Test status
Simulation time 6095313076 ps
CPU time 60.17 seconds
Started Jun 24 04:43:42 PM PDT 24
Finished Jun 24 04:44:47 PM PDT 24
Peak memory 216636 kb
Host smart-32e52e39-df91-4808-b118-600957384b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293199213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.4293199213
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.4260405698
Short name T322
Test name
Test status
Simulation time 5923115941 ps
CPU time 71.76 seconds
Started Jun 24 04:43:44 PM PDT 24
Finished Jun 24 04:45:00 PM PDT 24
Peak memory 219164 kb
Host smart-282dbd87-82ba-4b53-94f1-92638c79d822
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260405698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.4260405698
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1316013357
Short name T68
Test name
Test status
Simulation time 167681612 ps
CPU time 8.48 seconds
Started Jun 24 04:43:49 PM PDT 24
Finished Jun 24 04:44:03 PM PDT 24
Peak memory 216940 kb
Host smart-11ba2dc7-e65d-46fd-90e2-d15a3c3fc0c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316013357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1316013357
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3965816091
Short name T37
Test name
Test status
Simulation time 10858272185 ps
CPU time 178.93 seconds
Started Jun 24 04:43:48 PM PDT 24
Finished Jun 24 04:46:52 PM PDT 24
Peak memory 234764 kb
Host smart-302a7f23-f63e-45fc-88fb-47223d66b1f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965816091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3965816091
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3834866748
Short name T279
Test name
Test status
Simulation time 24954543204 ps
CPU time 56.6 seconds
Started Jun 24 04:43:46 PM PDT 24
Finished Jun 24 04:44:47 PM PDT 24
Peak memory 219112 kb
Host smart-910ee6cc-5843-43bd-9d4b-f3e84026d674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834866748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3834866748
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3864951754
Short name T144
Test name
Test status
Simulation time 17158415245 ps
CPU time 34.06 seconds
Started Jun 24 04:43:50 PM PDT 24
Finished Jun 24 04:44:29 PM PDT 24
Peak memory 219192 kb
Host smart-c54caad5-4b29-49a8-9fea-be6d253eb9f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3864951754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3864951754
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2440699342
Short name T173
Test name
Test status
Simulation time 26664623525 ps
CPU time 62.84 seconds
Started Jun 24 04:43:48 PM PDT 24
Finished Jun 24 04:44:56 PM PDT 24
Peak memory 216076 kb
Host smart-5f46a907-1986-4a37-ba1e-1f564947b2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440699342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2440699342
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1795168339
Short name T183
Test name
Test status
Simulation time 4548491543 ps
CPU time 61.55 seconds
Started Jun 24 04:43:48 PM PDT 24
Finished Jun 24 04:44:54 PM PDT 24
Peak memory 216972 kb
Host smart-052205a8-2852-4312-81e5-6d7da60e123b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795168339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1795168339
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2126114783
Short name T293
Test name
Test status
Simulation time 505968477 ps
CPU time 9.88 seconds
Started Jun 24 04:43:48 PM PDT 24
Finished Jun 24 04:44:03 PM PDT 24
Peak memory 216960 kb
Host smart-f177e2f6-ad97-477e-b6c4-901bc9a16af0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126114783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2126114783
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.822650296
Short name T220
Test name
Test status
Simulation time 34269264059 ps
CPU time 440.47 seconds
Started Jun 24 04:43:46 PM PDT 24
Finished Jun 24 04:51:12 PM PDT 24
Peak memory 238412 kb
Host smart-4390cbb1-39fe-48f4-a8ba-328bad0771fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822650296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.822650296
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.709833014
Short name T221
Test name
Test status
Simulation time 2535817872 ps
CPU time 24.64 seconds
Started Jun 24 04:43:54 PM PDT 24
Finished Jun 24 04:44:25 PM PDT 24
Peak memory 219292 kb
Host smart-6cee7380-3cdf-4286-b7be-e55665373011
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=709833014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.709833014
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3067036097
Short name T1
Test name
Test status
Simulation time 14465026305 ps
CPU time 42.64 seconds
Started Jun 24 04:43:49 PM PDT 24
Finished Jun 24 04:44:37 PM PDT 24
Peak memory 215900 kb
Host smart-75bc8e53-79d3-4a94-975c-4c2b5f6f953f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067036097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3067036097
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2737158556
Short name T246
Test name
Test status
Simulation time 11894301869 ps
CPU time 70.24 seconds
Started Jun 24 04:43:48 PM PDT 24
Finished Jun 24 04:45:04 PM PDT 24
Peak memory 219132 kb
Host smart-22116579-e880-4fff-a23f-8e6f391ec846
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737158556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2737158556
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2412391793
Short name T52
Test name
Test status
Simulation time 84814756242 ps
CPU time 1691.17 seconds
Started Jun 24 04:43:47 PM PDT 24
Finished Jun 24 05:12:04 PM PDT 24
Peak memory 237364 kb
Host smart-1a6c8aa3-afe3-45fd-8715-0cce56d422f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412391793 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2412391793
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.731956189
Short name T315
Test name
Test status
Simulation time 2065826249 ps
CPU time 20.99 seconds
Started Jun 24 04:43:46 PM PDT 24
Finished Jun 24 04:44:12 PM PDT 24
Peak memory 216852 kb
Host smart-ba6b4033-49ba-4838-a9e3-2e19217a8182
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731956189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.731956189
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2003848551
Short name T250
Test name
Test status
Simulation time 127337196106 ps
CPU time 686.16 seconds
Started Jun 24 04:43:51 PM PDT 24
Finished Jun 24 04:55:24 PM PDT 24
Peak memory 238592 kb
Host smart-06111d77-3d18-4b96-b304-29ebbb3b6c9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003848551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2003848551
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.450908658
Short name T59
Test name
Test status
Simulation time 1971856186 ps
CPU time 22.44 seconds
Started Jun 24 04:43:48 PM PDT 24
Finished Jun 24 04:44:16 PM PDT 24
Peak memory 219156 kb
Host smart-3609bc8d-dcfe-4d05-8f79-630ddb6be327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450908658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.450908658
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.652629179
Short name T265
Test name
Test status
Simulation time 716803721 ps
CPU time 10.14 seconds
Started Jun 24 04:43:48 PM PDT 24
Finished Jun 24 04:44:04 PM PDT 24
Peak memory 219084 kb
Host smart-8e75051e-9da1-4a5b-b9e5-4483c183f21e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=652629179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.652629179
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1610718947
Short name T301
Test name
Test status
Simulation time 28751591536 ps
CPU time 60.23 seconds
Started Jun 24 04:43:48 PM PDT 24
Finished Jun 24 04:44:54 PM PDT 24
Peak memory 216228 kb
Host smart-18376fa9-c7bd-4503-a7c7-44df78a38a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610718947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1610718947
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1190422332
Short name T181
Test name
Test status
Simulation time 40997939450 ps
CPU time 175.46 seconds
Started Jun 24 04:43:49 PM PDT 24
Finished Jun 24 04:46:50 PM PDT 24
Peak memory 220192 kb
Host smart-88a99347-8725-41d5-b71c-1b96682606b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190422332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1190422332
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2895192195
Short name T133
Test name
Test status
Simulation time 4122591366 ps
CPU time 33.77 seconds
Started Jun 24 04:43:46 PM PDT 24
Finished Jun 24 04:44:25 PM PDT 24
Peak memory 216896 kb
Host smart-3a52c480-c117-4fa9-9daf-8d4a2652b2e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895192195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2895192195
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.234170444
Short name T354
Test name
Test status
Simulation time 145562893400 ps
CPU time 781.87 seconds
Started Jun 24 04:43:47 PM PDT 24
Finished Jun 24 04:56:54 PM PDT 24
Peak memory 216660 kb
Host smart-555d6f0b-e1b6-46f4-9d4a-684c09b49203
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234170444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.234170444
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4061332777
Short name T243
Test name
Test status
Simulation time 3977507116 ps
CPU time 32.43 seconds
Started Jun 24 04:43:50 PM PDT 24
Finished Jun 24 04:44:27 PM PDT 24
Peak memory 219204 kb
Host smart-499b099f-f8fa-4804-a3f2-ff623b46049c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4061332777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4061332777
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2420820434
Short name T344
Test name
Test status
Simulation time 5594285260 ps
CPU time 63.79 seconds
Started Jun 24 04:43:56 PM PDT 24
Finished Jun 24 04:45:07 PM PDT 24
Peak memory 216732 kb
Host smart-4fcd5809-fea1-44ab-9818-072eb0156da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420820434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2420820434
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3163543255
Short name T336
Test name
Test status
Simulation time 53547927675 ps
CPU time 108.94 seconds
Started Jun 24 04:43:50 PM PDT 24
Finished Jun 24 04:45:44 PM PDT 24
Peak memory 218716 kb
Host smart-b91b1495-5e48-4563-a535-e9a24051b6f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163543255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3163543255
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3635730874
Short name T217
Test name
Test status
Simulation time 37677281433 ps
CPU time 297.27 seconds
Started Jun 24 04:43:51 PM PDT 24
Finished Jun 24 04:48:55 PM PDT 24
Peak memory 225656 kb
Host smart-0f4d8c4b-085f-4e47-b8d2-5b635439e312
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635730874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3635730874
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1805965298
Short name T358
Test name
Test status
Simulation time 39493935910 ps
CPU time 54.24 seconds
Started Jun 24 04:43:47 PM PDT 24
Finished Jun 24 04:44:46 PM PDT 24
Peak memory 219244 kb
Host smart-1c9e9488-e3cd-4a59-8466-9622730b896c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805965298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1805965298
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.218983857
Short name T252
Test name
Test status
Simulation time 1565010636 ps
CPU time 19.43 seconds
Started Jun 24 04:43:50 PM PDT 24
Finished Jun 24 04:44:15 PM PDT 24
Peak memory 211256 kb
Host smart-813c763f-4db6-4006-a5a1-c63645becd34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=218983857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.218983857
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2486606868
Short name T118
Test name
Test status
Simulation time 6407007908 ps
CPU time 26.27 seconds
Started Jun 24 04:43:49 PM PDT 24
Finished Jun 24 04:44:21 PM PDT 24
Peak memory 217176 kb
Host smart-2a8561b0-55f2-46d4-90ec-718b9da02924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486606868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2486606868
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1570750995
Short name T299
Test name
Test status
Simulation time 5864986199 ps
CPU time 49.83 seconds
Started Jun 24 04:43:56 PM PDT 24
Finished Jun 24 04:44:52 PM PDT 24
Peak memory 218024 kb
Host smart-3f3eb63c-8494-4c91-9060-3d80f0cc617e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570750995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1570750995
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.17644178
Short name T227
Test name
Test status
Simulation time 4990442759 ps
CPU time 22.64 seconds
Started Jun 24 04:43:57 PM PDT 24
Finished Jun 24 04:44:26 PM PDT 24
Peak memory 217300 kb
Host smart-e3717093-58d0-4d09-a8f7-3bee1faff02e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17644178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.17644178
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1680409724
Short name T40
Test name
Test status
Simulation time 10062425661 ps
CPU time 212.21 seconds
Started Jun 24 04:43:55 PM PDT 24
Finished Jun 24 04:47:34 PM PDT 24
Peak memory 237616 kb
Host smart-22ce8c76-cc79-4986-b9b8-da31205e0c03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680409724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1680409724
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3019469342
Short name T168
Test name
Test status
Simulation time 496629595 ps
CPU time 22.42 seconds
Started Jun 24 04:43:55 PM PDT 24
Finished Jun 24 04:44:24 PM PDT 24
Peak memory 219176 kb
Host smart-39a8b16a-680f-4486-8854-524c16ada792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019469342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3019469342
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2360956115
Short name T128
Test name
Test status
Simulation time 4250246221 ps
CPU time 33.24 seconds
Started Jun 24 04:43:58 PM PDT 24
Finished Jun 24 04:44:37 PM PDT 24
Peak memory 219208 kb
Host smart-d749d67f-2ebd-4caa-9d8c-05faf9e4ee9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2360956115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2360956115
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.335529607
Short name T261
Test name
Test status
Simulation time 8961578453 ps
CPU time 34.8 seconds
Started Jun 24 04:43:48 PM PDT 24
Finished Jun 24 04:44:28 PM PDT 24
Peak memory 216748 kb
Host smart-adcfafa5-5ee9-4f14-819c-3c38aaf2d045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335529607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.335529607
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2881566899
Short name T198
Test name
Test status
Simulation time 36124187158 ps
CPU time 67.12 seconds
Started Jun 24 04:43:49 PM PDT 24
Finished Jun 24 04:45:01 PM PDT 24
Peak memory 219524 kb
Host smart-dedea050-5ddc-4ef4-8143-4b2de965106d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881566899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2881566899
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.573916019
Short name T307
Test name
Test status
Simulation time 24440938982 ps
CPU time 23.41 seconds
Started Jun 24 04:43:59 PM PDT 24
Finished Jun 24 04:44:29 PM PDT 24
Peak memory 217308 kb
Host smart-c2375c84-e8dc-4079-b31f-46b6cc56ad06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573916019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.573916019
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2519107656
Short name T132
Test name
Test status
Simulation time 170331003551 ps
CPU time 400.23 seconds
Started Jun 24 04:43:57 PM PDT 24
Finished Jun 24 04:50:43 PM PDT 24
Peak memory 232244 kb
Host smart-bca8dc71-1f8c-40a0-b69f-40e920e31ed1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519107656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2519107656
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1087580828
Short name T241
Test name
Test status
Simulation time 335887709 ps
CPU time 19.44 seconds
Started Jun 24 04:43:54 PM PDT 24
Finished Jun 24 04:44:20 PM PDT 24
Peak memory 219068 kb
Host smart-8d5065ed-f1b1-49ae-8f00-0d3bf60cc404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087580828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1087580828
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1122931696
Short name T192
Test name
Test status
Simulation time 708473345 ps
CPU time 10.47 seconds
Started Jun 24 04:43:55 PM PDT 24
Finished Jun 24 04:44:11 PM PDT 24
Peak memory 219200 kb
Host smart-9d480544-e583-4d30-8657-6c0583af8853
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1122931696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1122931696
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1216796449
Short name T148
Test name
Test status
Simulation time 34714154829 ps
CPU time 46.22 seconds
Started Jun 24 04:43:59 PM PDT 24
Finished Jun 24 04:44:52 PM PDT 24
Peak memory 217168 kb
Host smart-9ebbea7f-017e-446e-a82e-84577e85b70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216796449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1216796449
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1805523832
Short name T204
Test name
Test status
Simulation time 71350740162 ps
CPU time 211.69 seconds
Started Jun 24 04:44:06 PM PDT 24
Finished Jun 24 04:47:46 PM PDT 24
Peak memory 221492 kb
Host smart-4b3836b0-e73b-4f25-aa53-c104931149b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805523832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1805523832
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1745056014
Short name T318
Test name
Test status
Simulation time 947939384 ps
CPU time 14.28 seconds
Started Jun 24 04:44:05 PM PDT 24
Finished Jun 24 04:44:28 PM PDT 24
Peak memory 216984 kb
Host smart-f7a76d07-3002-4bd5-a36e-eb5ed3af48cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745056014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1745056014
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2695196253
Short name T253
Test name
Test status
Simulation time 41879622442 ps
CPU time 234.1 seconds
Started Jun 24 04:44:05 PM PDT 24
Finished Jun 24 04:48:08 PM PDT 24
Peak memory 219468 kb
Host smart-2ccada99-b7e1-46a8-af8d-d7c97361e6fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695196253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2695196253
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2893245170
Short name T25
Test name
Test status
Simulation time 339003350 ps
CPU time 19.59 seconds
Started Jun 24 04:43:54 PM PDT 24
Finished Jun 24 04:44:20 PM PDT 24
Peak memory 219176 kb
Host smart-89a198e8-db14-49cd-92d6-ceeb30c04ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893245170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2893245170
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3459375861
Short name T169
Test name
Test status
Simulation time 3927901006 ps
CPU time 22.45 seconds
Started Jun 24 04:43:52 PM PDT 24
Finished Jun 24 04:44:21 PM PDT 24
Peak memory 217568 kb
Host smart-9e1ee180-e476-4597-a4bf-6d17bed553b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3459375861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3459375861
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.4189351053
Short name T230
Test name
Test status
Simulation time 3408572062 ps
CPU time 39.24 seconds
Started Jun 24 04:44:04 PM PDT 24
Finished Jun 24 04:44:51 PM PDT 24
Peak memory 215744 kb
Host smart-79283f48-3700-438a-94b7-6fd220a09764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189351053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.4189351053
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1288100043
Short name T184
Test name
Test status
Simulation time 3177393254 ps
CPU time 26.97 seconds
Started Jun 24 04:43:57 PM PDT 24
Finished Jun 24 04:44:30 PM PDT 24
Peak memory 216980 kb
Host smart-be8e8488-9f35-44a2-9ef1-0c55a6f5c62f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288100043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1288100043
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1427067814
Short name T58
Test name
Test status
Simulation time 278392989023 ps
CPU time 727.87 seconds
Started Jun 24 04:43:53 PM PDT 24
Finished Jun 24 04:56:07 PM PDT 24
Peak memory 237188 kb
Host smart-eaff4f39-e032-44b6-a023-8d7307d928d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427067814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1427067814
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.505284090
Short name T306
Test name
Test status
Simulation time 1499595536 ps
CPU time 19.63 seconds
Started Jun 24 04:44:00 PM PDT 24
Finished Jun 24 04:44:26 PM PDT 24
Peak memory 219180 kb
Host smart-b833a0ab-26e3-4cb6-8c67-ac916586d89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505284090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.505284090
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2616817322
Short name T36
Test name
Test status
Simulation time 22077261756 ps
CPU time 25.79 seconds
Started Jun 24 04:43:58 PM PDT 24
Finished Jun 24 04:44:30 PM PDT 24
Peak memory 219212 kb
Host smart-0d15ba1f-9b45-47af-922b-bdb019bbbff2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2616817322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2616817322
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.356999258
Short name T5
Test name
Test status
Simulation time 16513479449 ps
CPU time 45.24 seconds
Started Jun 24 04:44:05 PM PDT 24
Finished Jun 24 04:44:59 PM PDT 24
Peak memory 216896 kb
Host smart-87d17619-e800-41ad-ae7a-5f9a14b47326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356999258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.356999258
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3074283733
Short name T213
Test name
Test status
Simulation time 2481851836 ps
CPU time 62.6 seconds
Started Jun 24 04:43:57 PM PDT 24
Finished Jun 24 04:45:06 PM PDT 24
Peak memory 219828 kb
Host smart-b5595f59-cafa-4839-9d4c-c3e8f63ad7c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074283733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3074283733
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.559943905
Short name T351
Test name
Test status
Simulation time 1962706872 ps
CPU time 21.31 seconds
Started Jun 24 04:44:00 PM PDT 24
Finished Jun 24 04:44:28 PM PDT 24
Peak memory 217076 kb
Host smart-ad5ed409-8c76-4005-b8f7-ec40ebd901e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559943905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.559943905
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1485732725
Short name T300
Test name
Test status
Simulation time 6905410288 ps
CPU time 58.5 seconds
Started Jun 24 04:43:54 PM PDT 24
Finished Jun 24 04:44:59 PM PDT 24
Peak memory 219132 kb
Host smart-7bf6b475-bc16-4f00-8c4f-9643efed6d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485732725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1485732725
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4040124465
Short name T232
Test name
Test status
Simulation time 3134657907 ps
CPU time 26.28 seconds
Started Jun 24 04:43:52 PM PDT 24
Finished Jun 24 04:44:25 PM PDT 24
Peak memory 219184 kb
Host smart-b12c624b-8ee2-4e3d-b30e-98a335d11194
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4040124465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4040124465
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3156612203
Short name T290
Test name
Test status
Simulation time 10549369251 ps
CPU time 39 seconds
Started Jun 24 04:43:56 PM PDT 24
Finished Jun 24 04:44:42 PM PDT 24
Peak memory 216244 kb
Host smart-62c7da24-3fce-4aab-83ce-8f53f7693036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156612203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3156612203
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2978071273
Short name T259
Test name
Test status
Simulation time 16593439653 ps
CPU time 93.02 seconds
Started Jun 24 04:44:03 PM PDT 24
Finished Jun 24 04:45:44 PM PDT 24
Peak memory 220924 kb
Host smart-b5804624-fc50-44ff-8f41-8e89ffd544d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978071273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2978071273
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1070316988
Short name T240
Test name
Test status
Simulation time 319308632 ps
CPU time 8.26 seconds
Started Jun 24 04:43:41 PM PDT 24
Finished Jun 24 04:43:55 PM PDT 24
Peak memory 216552 kb
Host smart-e8ad0d73-aef3-4dc4-8612-28d5153e9e45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070316988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1070316988
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3595216274
Short name T330
Test name
Test status
Simulation time 74979241733 ps
CPU time 423 seconds
Started Jun 24 04:43:40 PM PDT 24
Finished Jun 24 04:50:48 PM PDT 24
Peak memory 238512 kb
Host smart-73e66b66-28a0-4819-b975-f231403ccb0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595216274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3595216274
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1513803138
Short name T234
Test name
Test status
Simulation time 10102035883 ps
CPU time 49.26 seconds
Started Jun 24 04:43:43 PM PDT 24
Finished Jun 24 04:44:37 PM PDT 24
Peak memory 219488 kb
Host smart-3aace637-33c2-45da-bcb9-648b955754d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513803138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1513803138
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.940133352
Short name T145
Test name
Test status
Simulation time 13465371501 ps
CPU time 30.54 seconds
Started Jun 24 04:43:41 PM PDT 24
Finished Jun 24 04:44:17 PM PDT 24
Peak memory 217524 kb
Host smart-796053f5-5c4f-4d25-b31f-584ce54b92dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=940133352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.940133352
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1636248657
Short name T27
Test name
Test status
Simulation time 2857953993 ps
CPU time 131.48 seconds
Started Jun 24 04:43:41 PM PDT 24
Finished Jun 24 04:45:58 PM PDT 24
Peak memory 236704 kb
Host smart-2e0d56fa-966b-4cb4-a8c4-243a52a0e098
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636248657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1636248657
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.645584485
Short name T138
Test name
Test status
Simulation time 23109133103 ps
CPU time 53.78 seconds
Started Jun 24 04:43:47 PM PDT 24
Finished Jun 24 04:44:45 PM PDT 24
Peak memory 216148 kb
Host smart-8f83cf90-19cf-4835-847e-7b12b4199bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645584485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.645584485
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3443097921
Short name T342
Test name
Test status
Simulation time 2113572556 ps
CPU time 33.51 seconds
Started Jun 24 04:43:45 PM PDT 24
Finished Jun 24 04:44:24 PM PDT 24
Peak memory 219068 kb
Host smart-e292da5f-d80e-4ec9-93d3-359706c801ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443097921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3443097921
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.4043664402
Short name T51
Test name
Test status
Simulation time 27910666996 ps
CPU time 1052.69 seconds
Started Jun 24 04:43:42 PM PDT 24
Finished Jun 24 05:01:20 PM PDT 24
Peak memory 232292 kb
Host smart-b5c96107-bf3c-4819-99f0-f8ff81b5b53d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043664402 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.4043664402
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2821188290
Short name T69
Test name
Test status
Simulation time 717468267 ps
CPU time 8.51 seconds
Started Jun 24 04:43:57 PM PDT 24
Finished Jun 24 04:44:12 PM PDT 24
Peak memory 216788 kb
Host smart-d2124268-b4e0-448f-b3f8-0c924201f73b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821188290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2821188290
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.985212132
Short name T347
Test name
Test status
Simulation time 117874455912 ps
CPU time 288.63 seconds
Started Jun 24 04:43:58 PM PDT 24
Finished Jun 24 04:48:52 PM PDT 24
Peak memory 231740 kb
Host smart-081dac15-5a8b-444d-975c-0ce187d9c0e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985212132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.985212132
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3745885469
Short name T55
Test name
Test status
Simulation time 1374039285 ps
CPU time 24.03 seconds
Started Jun 24 04:43:57 PM PDT 24
Finished Jun 24 04:44:27 PM PDT 24
Peak memory 218516 kb
Host smart-dc32f96b-dbe3-4b42-a772-bda15ae2ea26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745885469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3745885469
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3279389347
Short name T359
Test name
Test status
Simulation time 4503413432 ps
CPU time 14.33 seconds
Started Jun 24 04:43:54 PM PDT 24
Finished Jun 24 04:44:15 PM PDT 24
Peak memory 219208 kb
Host smart-c585fe6c-cfeb-4363-8473-02d6d9cca67f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3279389347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3279389347
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3395956589
Short name T263
Test name
Test status
Simulation time 28687744112 ps
CPU time 66.68 seconds
Started Jun 24 04:43:58 PM PDT 24
Finished Jun 24 04:45:10 PM PDT 24
Peak memory 216720 kb
Host smart-0f38e3e6-4ba9-474e-9327-d47c882abb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395956589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3395956589
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.4084542117
Short name T157
Test name
Test status
Simulation time 11977775790 ps
CPU time 42.11 seconds
Started Jun 24 04:43:57 PM PDT 24
Finished Jun 24 04:44:45 PM PDT 24
Peak memory 217580 kb
Host smart-cb365ba0-c696-4982-b388-231d4be87fae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084542117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.4084542117
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3655214541
Short name T13
Test name
Test status
Simulation time 44929759569 ps
CPU time 1773.15 seconds
Started Jun 24 04:43:54 PM PDT 24
Finished Jun 24 05:13:34 PM PDT 24
Peak memory 237156 kb
Host smart-e2e1ca2b-1a64-4b70-bd27-48760e9c88c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655214541 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.3655214541
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.4175052697
Short name T244
Test name
Test status
Simulation time 11999055894 ps
CPU time 26.45 seconds
Started Jun 24 04:43:53 PM PDT 24
Finished Jun 24 04:44:26 PM PDT 24
Peak memory 217276 kb
Host smart-5fd3266f-e942-45cf-b503-a196d491f299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175052697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.4175052697
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1891569240
Short name T143
Test name
Test status
Simulation time 18466026349 ps
CPU time 47.62 seconds
Started Jun 24 04:43:56 PM PDT 24
Finished Jun 24 04:44:50 PM PDT 24
Peak memory 219244 kb
Host smart-ac27838d-46ea-41d5-bdb7-f804a9012bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891569240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1891569240
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.612778355
Short name T136
Test name
Test status
Simulation time 3882207421 ps
CPU time 29.87 seconds
Started Jun 24 04:43:55 PM PDT 24
Finished Jun 24 04:44:30 PM PDT 24
Peak memory 219180 kb
Host smart-09bbb00e-dc9c-46f1-a1ee-0464cc036af1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=612778355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.612778355
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3691293760
Short name T31
Test name
Test status
Simulation time 26687158422 ps
CPU time 68.3 seconds
Started Jun 24 04:44:04 PM PDT 24
Finished Jun 24 04:45:20 PM PDT 24
Peak memory 217144 kb
Host smart-f2c9b442-f1bc-4f02-a264-2191f28ba5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691293760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3691293760
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.204560731
Short name T345
Test name
Test status
Simulation time 915551337 ps
CPU time 50.47 seconds
Started Jun 24 04:44:05 PM PDT 24
Finished Jun 24 04:45:04 PM PDT 24
Peak memory 220064 kb
Host smart-6076323e-e26e-40dd-bba2-e04c8dcf2391
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204560731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.204560731
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3863479958
Short name T22
Test name
Test status
Simulation time 4609822928 ps
CPU time 22.09 seconds
Started Jun 24 04:44:05 PM PDT 24
Finished Jun 24 04:44:35 PM PDT 24
Peak memory 217296 kb
Host smart-19304433-2836-4a62-9965-48b509a43f7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863479958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3863479958
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2883781671
Short name T186
Test name
Test status
Simulation time 94095715084 ps
CPU time 324.62 seconds
Started Jun 24 04:43:58 PM PDT 24
Finished Jun 24 04:49:29 PM PDT 24
Peak memory 219048 kb
Host smart-4c651d8f-be34-4bfc-83bc-3810fd6768f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883781671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2883781671
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.4228466463
Short name T194
Test name
Test status
Simulation time 7643508149 ps
CPU time 63.28 seconds
Started Jun 24 04:43:57 PM PDT 24
Finished Jun 24 04:45:06 PM PDT 24
Peak memory 219108 kb
Host smart-14630abd-13ff-4c70-89c1-f32d3772b96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228466463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.4228466463
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.4279647762
Short name T350
Test name
Test status
Simulation time 727858128 ps
CPU time 10.22 seconds
Started Jun 24 04:44:04 PM PDT 24
Finished Jun 24 04:44:23 PM PDT 24
Peak memory 219144 kb
Host smart-f31b5eeb-0d94-4e62-86ca-c29227d0f5b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4279647762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.4279647762
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1246451534
Short name T9
Test name
Test status
Simulation time 3123014117 ps
CPU time 39.32 seconds
Started Jun 24 04:44:03 PM PDT 24
Finished Jun 24 04:44:50 PM PDT 24
Peak memory 216244 kb
Host smart-aceaec65-c976-4247-9ef9-1b632f1d7d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246451534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1246451534
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.774527066
Short name T264
Test name
Test status
Simulation time 19362354251 ps
CPU time 97.48 seconds
Started Jun 24 04:44:04 PM PDT 24
Finished Jun 24 04:45:50 PM PDT 24
Peak memory 227468 kb
Host smart-37a14aaf-73ce-46f0-94c8-efdd15dbeaa2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774527066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.774527066
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1905893500
Short name T311
Test name
Test status
Simulation time 4948233047 ps
CPU time 23.07 seconds
Started Jun 24 04:44:04 PM PDT 24
Finished Jun 24 04:44:35 PM PDT 24
Peak memory 216720 kb
Host smart-1d4755dd-654a-4e13-bd82-2db6159d4a43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905893500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1905893500
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3335526852
Short name T3
Test name
Test status
Simulation time 264663434065 ps
CPU time 470.9 seconds
Started Jun 24 04:44:04 PM PDT 24
Finished Jun 24 04:52:03 PM PDT 24
Peak memory 241772 kb
Host smart-c0ff2242-6f94-4ed7-b1a7-5fe6c5bdd8ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335526852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3335526852
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3822071542
Short name T156
Test name
Test status
Simulation time 351849061 ps
CPU time 20.82 seconds
Started Jun 24 04:44:08 PM PDT 24
Finished Jun 24 04:44:37 PM PDT 24
Peak memory 221256 kb
Host smart-5972862c-976d-4516-8e96-d6d10b50e0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822071542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3822071542
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.304927363
Short name T280
Test name
Test status
Simulation time 5291472325 ps
CPU time 24.11 seconds
Started Jun 24 04:44:02 PM PDT 24
Finished Jun 24 04:44:33 PM PDT 24
Peak memory 211844 kb
Host smart-446915d5-0846-4d5c-b36a-e1a333381cd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=304927363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.304927363
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2970557573
Short name T121
Test name
Test status
Simulation time 7076253689 ps
CPU time 61.34 seconds
Started Jun 24 04:44:03 PM PDT 24
Finished Jun 24 04:45:12 PM PDT 24
Peak memory 216348 kb
Host smart-569799db-5b2b-4cc7-8b32-37f33b9dfee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970557573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2970557573
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3692991252
Short name T6
Test name
Test status
Simulation time 7967637795 ps
CPU time 39.96 seconds
Started Jun 24 04:44:07 PM PDT 24
Finished Jun 24 04:44:55 PM PDT 24
Peak memory 214380 kb
Host smart-80f751ba-2124-4c07-8d7f-f39f14db3ae2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692991252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3692991252
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1475248041
Short name T67
Test name
Test status
Simulation time 689104274 ps
CPU time 8.48 seconds
Started Jun 24 04:44:01 PM PDT 24
Finished Jun 24 04:44:16 PM PDT 24
Peak memory 216788 kb
Host smart-2fdb2111-88bc-4376-8269-0aeb880ab4c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475248041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1475248041
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.148152009
Short name T137
Test name
Test status
Simulation time 134968296077 ps
CPU time 566.91 seconds
Started Jun 24 04:44:07 PM PDT 24
Finished Jun 24 04:53:43 PM PDT 24
Peak memory 217732 kb
Host smart-d983d315-8d03-4c00-9915-c9f9fd4f0d4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148152009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.148152009
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2680813735
Short name T225
Test name
Test status
Simulation time 7715765914 ps
CPU time 62.84 seconds
Started Jun 24 04:44:01 PM PDT 24
Finished Jun 24 04:45:11 PM PDT 24
Peak memory 219132 kb
Host smart-a395a500-5b42-495f-88fa-2c843280044e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680813735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2680813735
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1784637619
Short name T140
Test name
Test status
Simulation time 2308269398 ps
CPU time 23.56 seconds
Started Jun 24 04:44:06 PM PDT 24
Finished Jun 24 04:44:38 PM PDT 24
Peak memory 219180 kb
Host smart-d2469139-ee10-4332-b821-30ae714187ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1784637619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1784637619
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1360874551
Short name T348
Test name
Test status
Simulation time 7709106932 ps
CPU time 42.93 seconds
Started Jun 24 04:44:01 PM PDT 24
Finished Jun 24 04:44:51 PM PDT 24
Peak memory 216700 kb
Host smart-583c771f-ca5a-4d9b-8222-ba699dd21c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360874551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1360874551
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1314271406
Short name T211
Test name
Test status
Simulation time 5571880001 ps
CPU time 62.46 seconds
Started Jun 24 04:44:02 PM PDT 24
Finished Jun 24 04:45:11 PM PDT 24
Peak memory 219240 kb
Host smart-c32b6f56-610a-42ac-9e1e-9bb8ec1c4a3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314271406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1314271406
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3338152986
Short name T131
Test name
Test status
Simulation time 690195642 ps
CPU time 13.03 seconds
Started Jun 24 04:44:12 PM PDT 24
Finished Jun 24 04:44:31 PM PDT 24
Peak memory 216892 kb
Host smart-108f048e-bc76-4d28-b9a6-3b026276cc3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338152986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3338152986
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3772721539
Short name T302
Test name
Test status
Simulation time 17040268882 ps
CPU time 327.24 seconds
Started Jun 24 04:44:04 PM PDT 24
Finished Jun 24 04:49:39 PM PDT 24
Peak memory 234456 kb
Host smart-6c60b5d5-5601-44f0-81bd-ba5b32081ecd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772721539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3772721539
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2139167162
Short name T24
Test name
Test status
Simulation time 3653511992 ps
CPU time 41.47 seconds
Started Jun 24 04:44:03 PM PDT 24
Finished Jun 24 04:44:52 PM PDT 24
Peak memory 219144 kb
Host smart-f6fc641c-b61f-41a5-ab88-9f40ecac8dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139167162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2139167162
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.683753681
Short name T292
Test name
Test status
Simulation time 7533411286 ps
CPU time 21.13 seconds
Started Jun 24 04:44:08 PM PDT 24
Finished Jun 24 04:44:37 PM PDT 24
Peak memory 211820 kb
Host smart-db25b1e8-8d1b-4094-8406-1ddb9634a632
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=683753681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.683753681
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.4126267980
Short name T71
Test name
Test status
Simulation time 13543111379 ps
CPU time 42.57 seconds
Started Jun 24 04:44:03 PM PDT 24
Finished Jun 24 04:44:54 PM PDT 24
Peak memory 217224 kb
Host smart-fec6ac16-668a-451f-a757-8d69b6c711f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126267980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.4126267980
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.780114983
Short name T314
Test name
Test status
Simulation time 28914221530 ps
CPU time 84.08 seconds
Started Jun 24 04:44:03 PM PDT 24
Finished Jun 24 04:45:36 PM PDT 24
Peak memory 221160 kb
Host smart-66b7a311-bdef-45e2-9007-5c3a662c51e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780114983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.780114983
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.425891408
Short name T30
Test name
Test status
Simulation time 2647563512 ps
CPU time 24.31 seconds
Started Jun 24 04:44:03 PM PDT 24
Finished Jun 24 04:44:34 PM PDT 24
Peak memory 216924 kb
Host smart-e32b5135-6b28-4734-b348-2c16aab5f8da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425891408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.425891408
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.914741665
Short name T308
Test name
Test status
Simulation time 72588839041 ps
CPU time 733.84 seconds
Started Jun 24 04:44:03 PM PDT 24
Finished Jun 24 04:56:24 PM PDT 24
Peak memory 233508 kb
Host smart-e9951b04-d341-4f01-aae6-bdbda4607700
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914741665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.914741665
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1665414593
Short name T46
Test name
Test status
Simulation time 7619569185 ps
CPU time 65.21 seconds
Started Jun 24 04:44:05 PM PDT 24
Finished Jun 24 04:45:18 PM PDT 24
Peak memory 219484 kb
Host smart-88f70321-72a0-497a-90e6-0bbdd7819083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665414593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1665414593
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2947637080
Short name T249
Test name
Test status
Simulation time 24580060177 ps
CPU time 30.33 seconds
Started Jun 24 04:44:03 PM PDT 24
Finished Jun 24 04:44:40 PM PDT 24
Peak memory 217468 kb
Host smart-4871d5cc-dd80-4202-bb45-6183d380e5a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2947637080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2947637080
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1637725268
Short name T178
Test name
Test status
Simulation time 4762558795 ps
CPU time 51.78 seconds
Started Jun 24 04:44:03 PM PDT 24
Finished Jun 24 04:45:02 PM PDT 24
Peak memory 215212 kb
Host smart-ea71ddfa-1507-4d4f-81ba-2cb881e3c19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637725268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1637725268
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3790784933
Short name T196
Test name
Test status
Simulation time 11081712782 ps
CPU time 30.77 seconds
Started Jun 24 04:44:02 PM PDT 24
Finished Jun 24 04:44:39 PM PDT 24
Peak memory 214416 kb
Host smart-43e0af82-3f83-494e-9eef-2c1c0f9ab94b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790784933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3790784933
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.4246779569
Short name T33
Test name
Test status
Simulation time 16400621766 ps
CPU time 27.16 seconds
Started Jun 24 04:44:07 PM PDT 24
Finished Jun 24 04:44:42 PM PDT 24
Peak memory 217184 kb
Host smart-539fc0d6-4e4d-49ea-b490-7f95b5d911a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246779569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.4246779569
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.828840282
Short name T141
Test name
Test status
Simulation time 172377670677 ps
CPU time 542.65 seconds
Started Jun 24 04:44:04 PM PDT 24
Finished Jun 24 04:53:15 PM PDT 24
Peak memory 236460 kb
Host smart-234710c7-1a94-4e5b-9089-72cd9a371972
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828840282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.828840282
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3891818690
Short name T361
Test name
Test status
Simulation time 6591027161 ps
CPU time 31.29 seconds
Started Jun 24 04:44:03 PM PDT 24
Finished Jun 24 04:44:41 PM PDT 24
Peak memory 215336 kb
Host smart-313c3dec-eea0-49aa-9c7c-2ba07cd3402e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891818690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3891818690
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3106051938
Short name T154
Test name
Test status
Simulation time 47377898575 ps
CPU time 32.71 seconds
Started Jun 24 04:44:05 PM PDT 24
Finished Jun 24 04:44:46 PM PDT 24
Peak memory 211808 kb
Host smart-d5216937-e809-4035-a243-a26c51d2f17f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3106051938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3106051938
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3421079095
Short name T310
Test name
Test status
Simulation time 30609633322 ps
CPU time 70.63 seconds
Started Jun 24 04:44:05 PM PDT 24
Finished Jun 24 04:45:25 PM PDT 24
Peak memory 217052 kb
Host smart-1405780f-f595-4fe8-8f62-2e7d256d97f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421079095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3421079095
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2336318084
Short name T195
Test name
Test status
Simulation time 8784751765 ps
CPU time 69.16 seconds
Started Jun 24 04:44:05 PM PDT 24
Finished Jun 24 04:45:23 PM PDT 24
Peak memory 217372 kb
Host smart-b179e676-6e16-47e3-98cd-67159da3e7b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336318084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2336318084
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3242248107
Short name T229
Test name
Test status
Simulation time 1832258053 ps
CPU time 8.34 seconds
Started Jun 24 04:44:04 PM PDT 24
Finished Jun 24 04:44:20 PM PDT 24
Peak memory 216844 kb
Host smart-570eb2df-fc79-4c34-9fb6-3fe50123214f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242248107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3242248107
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3038444492
Short name T158
Test name
Test status
Simulation time 66447118263 ps
CPU time 613.95 seconds
Started Jun 24 04:44:03 PM PDT 24
Finished Jun 24 04:54:25 PM PDT 24
Peak memory 219552 kb
Host smart-047dbf79-a220-405c-a694-124ced76a8db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038444492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3038444492
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3705286087
Short name T35
Test name
Test status
Simulation time 9868195397 ps
CPU time 47.46 seconds
Started Jun 24 04:44:03 PM PDT 24
Finished Jun 24 04:44:58 PM PDT 24
Peak memory 219132 kb
Host smart-b203b970-889a-4fc9-ad57-c4ef6396d418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705286087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3705286087
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.4274441958
Short name T303
Test name
Test status
Simulation time 14728570733 ps
CPU time 30.28 seconds
Started Jun 24 04:44:08 PM PDT 24
Finished Jun 24 04:44:46 PM PDT 24
Peak memory 211876 kb
Host smart-41391468-e769-4bb9-8808-a5fc8c373244
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4274441958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.4274441958
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3950096682
Short name T317
Test name
Test status
Simulation time 1487710678 ps
CPU time 20.36 seconds
Started Jun 24 04:44:07 PM PDT 24
Finished Jun 24 04:44:36 PM PDT 24
Peak memory 216564 kb
Host smart-e7e2f812-cc0a-4566-a728-8564bb1f9258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950096682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3950096682
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2594512944
Short name T349
Test name
Test status
Simulation time 8073548011 ps
CPU time 106.94 seconds
Started Jun 24 04:44:03 PM PDT 24
Finished Jun 24 04:45:58 PM PDT 24
Peak memory 219140 kb
Host smart-c6e630d2-c9c3-402d-a6b7-941c5baca40f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594512944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2594512944
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3516196995
Short name T49
Test name
Test status
Simulation time 211553933476 ps
CPU time 2083.75 seconds
Started Jun 24 04:44:02 PM PDT 24
Finished Jun 24 05:18:53 PM PDT 24
Peak memory 239556 kb
Host smart-8c30657e-55c8-43bc-895b-89f630b83655
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516196995 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3516196995
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2608590060
Short name T191
Test name
Test status
Simulation time 17541280882 ps
CPU time 34.18 seconds
Started Jun 24 04:44:07 PM PDT 24
Finished Jun 24 04:44:50 PM PDT 24
Peak memory 216844 kb
Host smart-9647bd20-b3fb-4381-bcc6-45c32de3bd90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608590060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2608590060
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1976163183
Short name T202
Test name
Test status
Simulation time 148308466704 ps
CPU time 865.55 seconds
Started Jun 24 04:44:05 PM PDT 24
Finished Jun 24 04:58:39 PM PDT 24
Peak memory 235876 kb
Host smart-e504cc60-4924-4735-8f03-9cc97d52f0be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976163183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1976163183
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1026314767
Short name T29
Test name
Test status
Simulation time 1501050977 ps
CPU time 19.56 seconds
Started Jun 24 04:44:03 PM PDT 24
Finished Jun 24 04:44:31 PM PDT 24
Peak memory 219068 kb
Host smart-731e9cd7-f679-453d-95d9-72024995b789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026314767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1026314767
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.198183586
Short name T273
Test name
Test status
Simulation time 44955369297 ps
CPU time 33.74 seconds
Started Jun 24 04:44:04 PM PDT 24
Finished Jun 24 04:44:46 PM PDT 24
Peak memory 217560 kb
Host smart-0e8ad8af-521f-446e-abc2-e4c5edabce5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=198183586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.198183586
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1101226387
Short name T256
Test name
Test status
Simulation time 8199735435 ps
CPU time 83.97 seconds
Started Jun 24 04:44:03 PM PDT 24
Finished Jun 24 04:45:34 PM PDT 24
Peak memory 217228 kb
Host smart-4e3b6f8c-3bf8-4883-ba3b-3b7f7d3d6fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101226387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1101226387
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2579301852
Short name T254
Test name
Test status
Simulation time 7722779567 ps
CPU time 83.61 seconds
Started Jun 24 04:44:03 PM PDT 24
Finished Jun 24 04:45:34 PM PDT 24
Peak memory 227324 kb
Host smart-6c0d9a3f-4110-434a-82ab-af2a18ae97f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579301852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2579301852
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.122756549
Short name T151
Test name
Test status
Simulation time 775292408 ps
CPU time 13.31 seconds
Started Jun 24 04:43:42 PM PDT 24
Finished Jun 24 04:44:01 PM PDT 24
Peak memory 216860 kb
Host smart-2dbe7154-0a4b-4271-885b-f137439e8fad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122756549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.122756549
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4216720276
Short name T188
Test name
Test status
Simulation time 88450411071 ps
CPU time 390.22 seconds
Started Jun 24 04:43:46 PM PDT 24
Finished Jun 24 04:50:21 PM PDT 24
Peak memory 232644 kb
Host smart-e11bc027-683f-4b29-b3cc-45e52259d5f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216720276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.4216720276
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1123119531
Short name T175
Test name
Test status
Simulation time 28195340739 ps
CPU time 59.46 seconds
Started Jun 24 04:43:47 PM PDT 24
Finished Jun 24 04:44:51 PM PDT 24
Peak memory 219084 kb
Host smart-514ab9c2-6944-4bed-b50d-265d645d3c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123119531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1123119531
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2030595107
Short name T340
Test name
Test status
Simulation time 3514678150 ps
CPU time 30.2 seconds
Started Jun 24 04:43:43 PM PDT 24
Finished Jun 24 04:44:18 PM PDT 24
Peak memory 211460 kb
Host smart-eb6242e6-6e5f-4278-b4a9-94298b2181ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2030595107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2030595107
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2100378567
Short name T19
Test name
Test status
Simulation time 230276357 ps
CPU time 118.46 seconds
Started Jun 24 04:43:44 PM PDT 24
Finished Jun 24 04:45:48 PM PDT 24
Peak memory 235800 kb
Host smart-4f4b77a2-fb16-4cad-87c9-9d6ff0c8ed35
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100378567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2100378567
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1085661547
Short name T135
Test name
Test status
Simulation time 14668069460 ps
CPU time 60.08 seconds
Started Jun 24 04:43:40 PM PDT 24
Finished Jun 24 04:44:45 PM PDT 24
Peak memory 215552 kb
Host smart-cbcd71cb-cf71-4233-8ddf-ee60a6aae4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085661547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1085661547
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2145797898
Short name T296
Test name
Test status
Simulation time 16458161167 ps
CPU time 68.2 seconds
Started Jun 24 04:43:41 PM PDT 24
Finished Jun 24 04:44:54 PM PDT 24
Peak memory 218024 kb
Host smart-7e5fcb4e-bec6-483e-a766-721efc9ac2c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145797898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2145797898
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3886266641
Short name T323
Test name
Test status
Simulation time 506946125 ps
CPU time 10.21 seconds
Started Jun 24 04:44:08 PM PDT 24
Finished Jun 24 04:44:26 PM PDT 24
Peak memory 217004 kb
Host smart-5cc4a39c-c203-4ce1-95d7-23601e11abec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886266641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3886266641
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1950536590
Short name T278
Test name
Test status
Simulation time 138531489588 ps
CPU time 424.57 seconds
Started Jun 24 04:44:04 PM PDT 24
Finished Jun 24 04:51:17 PM PDT 24
Peak memory 225224 kb
Host smart-ecbb0d91-70cd-4867-a05a-7158d212f2bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950536590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1950536590
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3391931261
Short name T122
Test name
Test status
Simulation time 23600105104 ps
CPU time 55.75 seconds
Started Jun 24 04:44:04 PM PDT 24
Finished Jun 24 04:45:08 PM PDT 24
Peak memory 218984 kb
Host smart-cfb71a83-87c2-40e4-a153-be3c3b985066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391931261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3391931261
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.937866893
Short name T321
Test name
Test status
Simulation time 3351300336 ps
CPU time 19.99 seconds
Started Jun 24 04:44:03 PM PDT 24
Finished Jun 24 04:44:31 PM PDT 24
Peak memory 219316 kb
Host smart-00150a7a-8a92-43d5-a86b-0b22b356e580
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=937866893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.937866893
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3121360865
Short name T85
Test name
Test status
Simulation time 9248951479 ps
CPU time 55.61 seconds
Started Jun 24 04:44:06 PM PDT 24
Finished Jun 24 04:45:10 PM PDT 24
Peak memory 215932 kb
Host smart-0f93e45a-d2a4-4a2b-b4aa-05199e55cb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121360865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3121360865
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.781194857
Short name T176
Test name
Test status
Simulation time 386745614 ps
CPU time 27.56 seconds
Started Jun 24 04:44:06 PM PDT 24
Finished Jun 24 04:44:42 PM PDT 24
Peak memory 218052 kb
Host smart-dd56f03f-2e39-4578-9495-8eba59213980
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781194857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.781194857
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2564031412
Short name T274
Test name
Test status
Simulation time 174214209 ps
CPU time 8.57 seconds
Started Jun 24 04:44:11 PM PDT 24
Finished Jun 24 04:44:26 PM PDT 24
Peak memory 216788 kb
Host smart-d41b5865-0fc2-472b-b904-b3da2ec7a4ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564031412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2564031412
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2027835553
Short name T47
Test name
Test status
Simulation time 4731368291 ps
CPU time 128.78 seconds
Started Jun 24 04:44:10 PM PDT 24
Finished Jun 24 04:46:26 PM PDT 24
Peak memory 236036 kb
Host smart-fe4c0428-17b8-44e9-a65d-6f1e65087a11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027835553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2027835553
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1026115835
Short name T357
Test name
Test status
Simulation time 353355894 ps
CPU time 20.07 seconds
Started Jun 24 04:44:13 PM PDT 24
Finished Jun 24 04:44:39 PM PDT 24
Peak memory 219068 kb
Host smart-fa9d58bd-e1cc-432e-81ba-72a1e6c66161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026115835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1026115835
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3457192516
Short name T297
Test name
Test status
Simulation time 15551774695 ps
CPU time 27.01 seconds
Started Jun 24 04:44:12 PM PDT 24
Finished Jun 24 04:44:45 PM PDT 24
Peak memory 219316 kb
Host smart-55438716-6aac-4dfc-b5d7-b77079d4410f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3457192516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3457192516
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2715898644
Short name T23
Test name
Test status
Simulation time 8013671413 ps
CPU time 64.72 seconds
Started Jun 24 04:44:07 PM PDT 24
Finished Jun 24 04:45:20 PM PDT 24
Peak memory 217144 kb
Host smart-1a5eb14e-5ed5-4730-8b75-ff8ad6a16f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715898644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2715898644
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1143501607
Short name T179
Test name
Test status
Simulation time 59162052381 ps
CPU time 155.73 seconds
Started Jun 24 04:44:04 PM PDT 24
Finished Jun 24 04:46:48 PM PDT 24
Peak memory 229740 kb
Host smart-3a332661-ac9c-4d83-b922-094b1baedf0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143501607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1143501607
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2128166372
Short name T353
Test name
Test status
Simulation time 1645274658 ps
CPU time 14.19 seconds
Started Jun 24 04:44:09 PM PDT 24
Finished Jun 24 04:44:31 PM PDT 24
Peak memory 216868 kb
Host smart-6b4497c9-fcd0-40e9-929e-b20e6413e07a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128166372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2128166372
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2885286777
Short name T268
Test name
Test status
Simulation time 7791161540 ps
CPU time 202.22 seconds
Started Jun 24 04:44:08 PM PDT 24
Finished Jun 24 04:47:38 PM PDT 24
Peak memory 237508 kb
Host smart-67ac52fb-397b-438b-9e18-5d8a71e0d561
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885286777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2885286777
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2649794321
Short name T219
Test name
Test status
Simulation time 2664976038 ps
CPU time 36.43 seconds
Started Jun 24 04:44:13 PM PDT 24
Finished Jun 24 04:44:55 PM PDT 24
Peak memory 218892 kb
Host smart-c62043c3-ad8f-4a6d-950c-2dd6a40f65ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649794321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2649794321
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3496957650
Short name T223
Test name
Test status
Simulation time 1322628949 ps
CPU time 18.69 seconds
Started Jun 24 04:44:14 PM PDT 24
Finished Jun 24 04:44:38 PM PDT 24
Peak memory 219068 kb
Host smart-e1502c8f-75b3-4599-96a2-99f7d7c8a182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3496957650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3496957650
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1412340072
Short name T72
Test name
Test status
Simulation time 2480386902 ps
CPU time 35.21 seconds
Started Jun 24 04:44:09 PM PDT 24
Finished Jun 24 04:44:52 PM PDT 24
Peak memory 216300 kb
Host smart-7153e3c3-80d8-41ba-9bad-621b63aaf2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412340072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1412340072
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.4253673887
Short name T258
Test name
Test status
Simulation time 10926998722 ps
CPU time 24.74 seconds
Started Jun 24 04:44:11 PM PDT 24
Finished Jun 24 04:44:42 PM PDT 24
Peak memory 217208 kb
Host smart-9597e4f0-4941-4b02-875a-0f432f4ea0d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253673887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.4253673887
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3178468631
Short name T189
Test name
Test status
Simulation time 26224811407 ps
CPU time 275.62 seconds
Started Jun 24 04:44:12 PM PDT 24
Finished Jun 24 04:48:54 PM PDT 24
Peak memory 239456 kb
Host smart-150b26de-e817-41d8-91ae-4c4659657708
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178468631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3178468631
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.584586936
Short name T212
Test name
Test status
Simulation time 640754910 ps
CPU time 19.64 seconds
Started Jun 24 04:44:13 PM PDT 24
Finished Jun 24 04:44:38 PM PDT 24
Peak memory 219072 kb
Host smart-47e2f2c1-0a07-497a-aa2d-d570a95683f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584586936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.584586936
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2460074145
Short name T325
Test name
Test status
Simulation time 263158086 ps
CPU time 10.46 seconds
Started Jun 24 04:44:16 PM PDT 24
Finished Jun 24 04:44:30 PM PDT 24
Peak memory 219116 kb
Host smart-e58d8930-fdaa-473e-94f2-8ead6e742ead
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2460074145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2460074145
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3295195798
Short name T222
Test name
Test status
Simulation time 8882753856 ps
CPU time 43.41 seconds
Started Jun 24 04:44:13 PM PDT 24
Finished Jun 24 04:45:02 PM PDT 24
Peak memory 216804 kb
Host smart-2b63ef68-282a-43f3-b55a-4649fc102ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295195798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3295195798
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.4223179991
Short name T103
Test name
Test status
Simulation time 11947662908 ps
CPU time 53.29 seconds
Started Jun 24 04:44:09 PM PDT 24
Finished Jun 24 04:45:10 PM PDT 24
Peak memory 219264 kb
Host smart-ce24c44e-67dc-4193-b2bb-13d9fe92dfdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223179991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.4223179991
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2560089425
Short name T327
Test name
Test status
Simulation time 1499153298 ps
CPU time 8.39 seconds
Started Jun 24 04:44:12 PM PDT 24
Finished Jun 24 04:44:27 PM PDT 24
Peak memory 216928 kb
Host smart-44974530-dba9-4607-aa9e-bd678cbaa3e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560089425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2560089425
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3657351285
Short name T214
Test name
Test status
Simulation time 2814633393 ps
CPU time 207.11 seconds
Started Jun 24 04:44:11 PM PDT 24
Finished Jun 24 04:47:45 PM PDT 24
Peak memory 228196 kb
Host smart-d3d97910-8f51-4de0-b1be-2734e04ec884
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657351285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3657351285
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.625811952
Short name T226
Test name
Test status
Simulation time 33657793490 ps
CPU time 67.07 seconds
Started Jun 24 04:44:10 PM PDT 24
Finished Jun 24 04:45:25 PM PDT 24
Peak memory 219244 kb
Host smart-632c134e-154b-466e-8aa4-620dc1fb46a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625811952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.625811952
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3308871312
Short name T45
Test name
Test status
Simulation time 700780379 ps
CPU time 14.74 seconds
Started Jun 24 04:44:09 PM PDT 24
Finished Jun 24 04:44:32 PM PDT 24
Peak memory 218584 kb
Host smart-cf9e6a26-d3a5-4474-8b5d-dd11b8886f5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3308871312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3308871312
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.977143968
Short name T119
Test name
Test status
Simulation time 7541471763 ps
CPU time 30.74 seconds
Started Jun 24 04:44:09 PM PDT 24
Finished Jun 24 04:44:47 PM PDT 24
Peak memory 216284 kb
Host smart-7cd1faf9-b830-4881-aeef-3d3ff142adfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977143968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.977143968
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1523892510
Short name T125
Test name
Test status
Simulation time 2072908595 ps
CPU time 40.57 seconds
Started Jun 24 04:44:09 PM PDT 24
Finished Jun 24 04:44:57 PM PDT 24
Peak memory 219096 kb
Host smart-ef990e0b-1fa0-4f09-b370-c83e6e6e928a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523892510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1523892510
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2719314715
Short name T190
Test name
Test status
Simulation time 1230252986 ps
CPU time 12.67 seconds
Started Jun 24 04:44:11 PM PDT 24
Finished Jun 24 04:44:31 PM PDT 24
Peak memory 216908 kb
Host smart-dd5b72ad-9dd8-426e-878e-8bf359550c0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719314715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2719314715
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.4019251949
Short name T270
Test name
Test status
Simulation time 55283721434 ps
CPU time 481.85 seconds
Started Jun 24 04:44:11 PM PDT 24
Finished Jun 24 04:52:19 PM PDT 24
Peak memory 234424 kb
Host smart-ea28d7d7-6154-401f-a627-ea4ae230e97f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019251949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.4019251949
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.231908403
Short name T282
Test name
Test status
Simulation time 3420088037 ps
CPU time 40.98 seconds
Started Jun 24 04:44:11 PM PDT 24
Finished Jun 24 04:44:59 PM PDT 24
Peak memory 219124 kb
Host smart-479f2e97-30b3-484b-93bc-1c047eee70c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231908403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.231908403
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1983718420
Short name T57
Test name
Test status
Simulation time 707638569 ps
CPU time 10.64 seconds
Started Jun 24 04:44:11 PM PDT 24
Finished Jun 24 04:44:28 PM PDT 24
Peak memory 219252 kb
Host smart-b24a419c-4ee1-4893-8510-77f74051e6ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1983718420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1983718420
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.173426413
Short name T187
Test name
Test status
Simulation time 8942658300 ps
CPU time 50.44 seconds
Started Jun 24 04:44:13 PM PDT 24
Finished Jun 24 04:45:09 PM PDT 24
Peak memory 215692 kb
Host smart-709d4a84-afed-4f6c-a041-f4b682bbaa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173426413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.173426413
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2610830805
Short name T123
Test name
Test status
Simulation time 775150529 ps
CPU time 14.84 seconds
Started Jun 24 04:44:11 PM PDT 24
Finished Jun 24 04:44:33 PM PDT 24
Peak memory 218712 kb
Host smart-034b0f59-316e-438e-8b62-d2df8b38a1f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610830805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2610830805
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3559919181
Short name T185
Test name
Test status
Simulation time 750491287 ps
CPU time 8.36 seconds
Started Jun 24 04:44:19 PM PDT 24
Finished Jun 24 04:44:30 PM PDT 24
Peak memory 216764 kb
Host smart-8052e7a5-87dc-4ccd-b4b0-d276adfd9d8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559919181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3559919181
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2491122752
Short name T275
Test name
Test status
Simulation time 36284264390 ps
CPU time 470.11 seconds
Started Jun 24 04:44:14 PM PDT 24
Finished Jun 24 04:52:09 PM PDT 24
Peak memory 235752 kb
Host smart-b1905b0a-a4ff-4635-8020-c25c96f76207
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491122752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2491122752
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3657345110
Short name T298
Test name
Test status
Simulation time 1011173969 ps
CPU time 22.2 seconds
Started Jun 24 04:44:15 PM PDT 24
Finished Jun 24 04:44:41 PM PDT 24
Peak memory 215268 kb
Host smart-dbbbe1d2-b4e7-4db2-b8be-d3352541f444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657345110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3657345110
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3842517714
Short name T150
Test name
Test status
Simulation time 2744540409 ps
CPU time 26.07 seconds
Started Jun 24 04:44:09 PM PDT 24
Finished Jun 24 04:44:43 PM PDT 24
Peak memory 219316 kb
Host smart-05d01bcb-3a74-455d-8762-e8155d3ef89b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3842517714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3842517714
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.4046144517
Short name T235
Test name
Test status
Simulation time 4482208393 ps
CPU time 53.45 seconds
Started Jun 24 04:44:13 PM PDT 24
Finished Jun 24 04:45:12 PM PDT 24
Peak memory 216420 kb
Host smart-ac45e7cf-8fbd-4aa4-b5bd-0d1d6903d7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046144517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.4046144517
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1302404653
Short name T4
Test name
Test status
Simulation time 3323146140 ps
CPU time 57.6 seconds
Started Jun 24 04:44:10 PM PDT 24
Finished Jun 24 04:45:15 PM PDT 24
Peak memory 219252 kb
Host smart-bcd2cce2-8d54-4d65-86ae-9a5ad887e04f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302404653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1302404653
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1425682619
Short name T285
Test name
Test status
Simulation time 3458042184 ps
CPU time 27.41 seconds
Started Jun 24 04:44:18 PM PDT 24
Finished Jun 24 04:44:48 PM PDT 24
Peak memory 217004 kb
Host smart-f1ec31e8-a245-4758-a74e-da33c16cda52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425682619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1425682619
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1906573480
Short name T130
Test name
Test status
Simulation time 2628906357 ps
CPU time 166.62 seconds
Started Jun 24 04:44:20 PM PDT 24
Finished Jun 24 04:47:09 PM PDT 24
Peak memory 219380 kb
Host smart-24481485-8b00-482f-bb8b-064de15ea245
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906573480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1906573480
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.4133210163
Short name T200
Test name
Test status
Simulation time 6991292905 ps
CPU time 58.86 seconds
Started Jun 24 04:44:18 PM PDT 24
Finished Jun 24 04:45:20 PM PDT 24
Peak memory 219116 kb
Host smart-856381db-b212-413b-8cb6-55967049a968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133210163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.4133210163
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1488967239
Short name T206
Test name
Test status
Simulation time 180650410 ps
CPU time 10.28 seconds
Started Jun 24 04:44:18 PM PDT 24
Finished Jun 24 04:44:31 PM PDT 24
Peak memory 219120 kb
Host smart-0ee8c58c-b7bc-4644-9bbe-d28c1c9be5c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1488967239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1488967239
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.791420400
Short name T161
Test name
Test status
Simulation time 2625974601 ps
CPU time 39.4 seconds
Started Jun 24 04:44:20 PM PDT 24
Finished Jun 24 04:45:01 PM PDT 24
Peak memory 216360 kb
Host smart-4746ccb7-739f-4ef7-a7c9-8c4324be9d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791420400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.791420400
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1698803767
Short name T260
Test name
Test status
Simulation time 22835613002 ps
CPU time 61.72 seconds
Started Jun 24 04:44:18 PM PDT 24
Finished Jun 24 04:45:23 PM PDT 24
Peak memory 218828 kb
Host smart-7a1b1240-d2bb-4508-9b3f-bb14c77ca2dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698803767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1698803767
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2931805386
Short name T209
Test name
Test status
Simulation time 14681805369 ps
CPU time 30.09 seconds
Started Jun 24 04:44:18 PM PDT 24
Finished Jun 24 04:44:51 PM PDT 24
Peak memory 217388 kb
Host smart-6326dd11-103a-46c7-81eb-f1b104d48685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931805386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2931805386
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.135988897
Short name T355
Test name
Test status
Simulation time 146167310655 ps
CPU time 495.67 seconds
Started Jun 24 04:44:21 PM PDT 24
Finished Jun 24 04:52:38 PM PDT 24
Peak memory 239256 kb
Host smart-df1c4b2c-6e7d-41af-9491-09e34adc0545
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135988897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.135988897
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3446623741
Short name T60
Test name
Test status
Simulation time 8208415455 ps
CPU time 64.52 seconds
Started Jun 24 04:44:19 PM PDT 24
Finished Jun 24 04:45:26 PM PDT 24
Peak memory 219132 kb
Host smart-4bd70913-682c-4867-8ccd-4d30a18267d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446623741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3446623741
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2057249415
Short name T231
Test name
Test status
Simulation time 3713009857 ps
CPU time 31.29 seconds
Started Jun 24 04:44:21 PM PDT 24
Finished Jun 24 04:44:54 PM PDT 24
Peak memory 211372 kb
Host smart-559f9773-e0ba-493b-b487-619025cbbd33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2057249415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2057249415
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1389409335
Short name T289
Test name
Test status
Simulation time 23072633378 ps
CPU time 35.98 seconds
Started Jun 24 04:44:18 PM PDT 24
Finished Jun 24 04:44:57 PM PDT 24
Peak memory 217192 kb
Host smart-c38d7ecd-a52e-4304-a460-f8973f0dca4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389409335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1389409335
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.989199638
Short name T251
Test name
Test status
Simulation time 21725351910 ps
CPU time 64.56 seconds
Started Jun 24 04:44:21 PM PDT 24
Finished Jun 24 04:45:27 PM PDT 24
Peak memory 217220 kb
Host smart-fb0f38a0-8670-4999-bd9f-849285e8460b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989199638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.989199638
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.197452134
Short name T346
Test name
Test status
Simulation time 1638103519 ps
CPU time 13.96 seconds
Started Jun 24 04:44:20 PM PDT 24
Finished Jun 24 04:44:36 PM PDT 24
Peak memory 216792 kb
Host smart-af52503d-11b2-41d8-9cd5-577160661322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197452134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.197452134
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2963929279
Short name T155
Test name
Test status
Simulation time 58548487531 ps
CPU time 332.71 seconds
Started Jun 24 04:44:21 PM PDT 24
Finished Jun 24 04:49:56 PM PDT 24
Peak memory 241612 kb
Host smart-777cb9b7-05a7-4717-8e9d-4c574fee0960
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963929279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2963929279
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3959863505
Short name T159
Test name
Test status
Simulation time 52579200055 ps
CPU time 64.89 seconds
Started Jun 24 04:44:18 PM PDT 24
Finished Jun 24 04:45:26 PM PDT 24
Peak memory 219132 kb
Host smart-04c830a0-56e9-4034-8276-7fdb18833b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959863505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3959863505
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.407191623
Short name T34
Test name
Test status
Simulation time 2181915483 ps
CPU time 22.02 seconds
Started Jun 24 04:44:19 PM PDT 24
Finished Jun 24 04:44:44 PM PDT 24
Peak memory 219208 kb
Host smart-68808d4b-a266-4266-8822-8ad6d94fa169
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=407191623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.407191623
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1763297722
Short name T255
Test name
Test status
Simulation time 2809826819 ps
CPU time 24.81 seconds
Started Jun 24 04:44:22 PM PDT 24
Finished Jun 24 04:44:48 PM PDT 24
Peak memory 216400 kb
Host smart-aca167d5-615a-487c-ad08-a35b26524adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763297722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1763297722
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3733845318
Short name T215
Test name
Test status
Simulation time 2560094162 ps
CPU time 30.78 seconds
Started Jun 24 04:44:22 PM PDT 24
Finished Jun 24 04:44:54 PM PDT 24
Peak memory 218960 kb
Host smart-b55c2113-efbd-43fc-b24e-dcfbd7a5b1a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733845318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3733845318
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1378019507
Short name T21
Test name
Test status
Simulation time 2340518539 ps
CPU time 13.93 seconds
Started Jun 24 04:43:38 PM PDT 24
Finished Jun 24 04:44:02 PM PDT 24
Peak memory 216940 kb
Host smart-c4ff6d8b-417d-4f60-bf84-bd0d535e05c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378019507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1378019507
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.154602597
Short name T320
Test name
Test status
Simulation time 66699592104 ps
CPU time 642.54 seconds
Started Jun 24 04:43:42 PM PDT 24
Finished Jun 24 04:54:29 PM PDT 24
Peak memory 234932 kb
Host smart-c17aaca4-5d99-4b67-aff3-6e73dd3c5a81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154602597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.154602597
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2780643849
Short name T341
Test name
Test status
Simulation time 6374748670 ps
CPU time 55.65 seconds
Started Jun 24 04:43:40 PM PDT 24
Finished Jun 24 04:44:40 PM PDT 24
Peak memory 219140 kb
Host smart-0ab99eac-918f-49fd-8b2c-6d24bccec6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780643849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2780643849
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1611001224
Short name T126
Test name
Test status
Simulation time 16403854094 ps
CPU time 33.11 seconds
Started Jun 24 04:43:41 PM PDT 24
Finished Jun 24 04:44:20 PM PDT 24
Peak memory 211772 kb
Host smart-899d8355-854b-43e1-8847-a3a4a8da6ed2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1611001224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1611001224
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1326266130
Short name T26
Test name
Test status
Simulation time 1721896671 ps
CPU time 229.19 seconds
Started Jun 24 04:43:41 PM PDT 24
Finished Jun 24 04:47:36 PM PDT 24
Peak memory 235356 kb
Host smart-426e91c8-5800-4ede-9033-3d5e701845ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326266130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1326266130
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1956494067
Short name T180
Test name
Test status
Simulation time 1557292884 ps
CPU time 19.89 seconds
Started Jun 24 04:43:41 PM PDT 24
Finished Jun 24 04:44:06 PM PDT 24
Peak memory 214616 kb
Host smart-b42bb811-4921-4c09-997b-8e24291e21c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956494067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1956494067
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3877323070
Short name T32
Test name
Test status
Simulation time 21786689720 ps
CPU time 54.85 seconds
Started Jun 24 04:43:42 PM PDT 24
Finished Jun 24 04:44:42 PM PDT 24
Peak memory 217488 kb
Host smart-31dcfff2-f0a3-4f48-96ad-10b01832080d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877323070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3877323070
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3604215044
Short name T197
Test name
Test status
Simulation time 687859024 ps
CPU time 8.23 seconds
Started Jun 24 04:44:26 PM PDT 24
Finished Jun 24 04:44:35 PM PDT 24
Peak memory 217100 kb
Host smart-319cf59b-161f-42fa-b641-551eff4feca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604215044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3604215044
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1195754440
Short name T313
Test name
Test status
Simulation time 2101166978 ps
CPU time 146.24 seconds
Started Jun 24 04:44:18 PM PDT 24
Finished Jun 24 04:46:47 PM PDT 24
Peak memory 215964 kb
Host smart-d21e405a-6986-401f-aa69-e96351f74fd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195754440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1195754440
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2473101762
Short name T134
Test name
Test status
Simulation time 6757477411 ps
CPU time 59.5 seconds
Started Jun 24 04:44:21 PM PDT 24
Finished Jun 24 04:45:22 PM PDT 24
Peak memory 219076 kb
Host smart-2520f650-1461-425f-a166-c23b12e912e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473101762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2473101762
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2979740650
Short name T316
Test name
Test status
Simulation time 8466225804 ps
CPU time 29.32 seconds
Started Jun 24 04:44:20 PM PDT 24
Finished Jun 24 04:44:51 PM PDT 24
Peak memory 211752 kb
Host smart-d5c0b75d-f1f6-4268-9053-7abd5d9b9508
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979740650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2979740650
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3317210078
Short name T120
Test name
Test status
Simulation time 346180457 ps
CPU time 19.98 seconds
Started Jun 24 04:44:21 PM PDT 24
Finished Jun 24 04:44:42 PM PDT 24
Peak memory 216068 kb
Host smart-59defba1-6796-460b-92c6-c51eb1b9eb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317210078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3317210078
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3568347675
Short name T83
Test name
Test status
Simulation time 1670395310 ps
CPU time 56.06 seconds
Started Jun 24 04:44:20 PM PDT 24
Finished Jun 24 04:45:18 PM PDT 24
Peak memory 219184 kb
Host smart-d135fc74-66eb-48d3-b644-94fbea32e2ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568347675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3568347675
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1746849656
Short name T228
Test name
Test status
Simulation time 11568434989 ps
CPU time 17.32 seconds
Started Jun 24 04:44:26 PM PDT 24
Finished Jun 24 04:44:46 PM PDT 24
Peak memory 217228 kb
Host smart-2e3313e2-4a57-404b-b3ae-77b8364c273d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746849656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1746849656
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3602778970
Short name T16
Test name
Test status
Simulation time 5881168749 ps
CPU time 250.54 seconds
Started Jun 24 04:44:26 PM PDT 24
Finished Jun 24 04:48:38 PM PDT 24
Peak memory 239712 kb
Host smart-c8532384-cff9-4458-8850-52fb630276c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602778970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3602778970
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2033844264
Short name T305
Test name
Test status
Simulation time 342526857 ps
CPU time 19.04 seconds
Started Jun 24 04:44:29 PM PDT 24
Finished Jun 24 04:44:51 PM PDT 24
Peak memory 219044 kb
Host smart-162e9463-da07-4226-9eb5-d7b046f1ebed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033844264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2033844264
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3484715162
Short name T309
Test name
Test status
Simulation time 4075600641 ps
CPU time 32.48 seconds
Started Jun 24 04:44:32 PM PDT 24
Finished Jun 24 04:45:07 PM PDT 24
Peak memory 211372 kb
Host smart-3ce37fd0-0d69-487f-b58f-0e17cbc8e6ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3484715162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3484715162
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1754850734
Short name T360
Test name
Test status
Simulation time 4457833386 ps
CPU time 44.88 seconds
Started Jun 24 04:44:31 PM PDT 24
Finished Jun 24 04:45:19 PM PDT 24
Peak memory 216324 kb
Host smart-9e4d8ee3-e5ea-4d66-be1c-c9be8a0dcebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754850734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1754850734
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3891878876
Short name T287
Test name
Test status
Simulation time 26936473309 ps
CPU time 252.88 seconds
Started Jun 24 04:44:25 PM PDT 24
Finished Jun 24 04:48:40 PM PDT 24
Peak memory 227356 kb
Host smart-b43a1e4e-7409-4aa2-8eb5-cc3c76484c3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891878876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3891878876
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1695561937
Short name T172
Test name
Test status
Simulation time 248392486 ps
CPU time 8.28 seconds
Started Jun 24 04:44:26 PM PDT 24
Finished Jun 24 04:44:35 PM PDT 24
Peak memory 216752 kb
Host smart-cdc71aea-a59e-48f3-aef1-ad47d13d138a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695561937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1695561937
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.336409937
Short name T295
Test name
Test status
Simulation time 581922288662 ps
CPU time 771.04 seconds
Started Jun 24 04:44:31 PM PDT 24
Finished Jun 24 04:57:26 PM PDT 24
Peak memory 239180 kb
Host smart-1610bbf0-f636-4696-a0b6-27aeb0ea8650
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336409937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.336409937
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.120066890
Short name T242
Test name
Test status
Simulation time 16044606465 ps
CPU time 67.66 seconds
Started Jun 24 04:44:28 PM PDT 24
Finished Jun 24 04:45:39 PM PDT 24
Peak memory 219112 kb
Host smart-0e41835d-c403-4d97-a048-cf6cf47fe11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120066890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.120066890
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.701048980
Short name T294
Test name
Test status
Simulation time 13175262165 ps
CPU time 31.78 seconds
Started Jun 24 04:44:27 PM PDT 24
Finished Jun 24 04:45:01 PM PDT 24
Peak memory 217560 kb
Host smart-7ed2ba3d-cf7d-4137-9f9f-b76749fe5a6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=701048980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.701048980
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.3121303810
Short name T70
Test name
Test status
Simulation time 4939515909 ps
CPU time 49.05 seconds
Started Jun 24 04:44:27 PM PDT 24
Finished Jun 24 04:45:20 PM PDT 24
Peak memory 216196 kb
Host smart-ce821a8e-eebc-40c1-a88b-7f9c512a1249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121303810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3121303810
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1925466083
Short name T182
Test name
Test status
Simulation time 1258579318 ps
CPU time 75.52 seconds
Started Jun 24 04:44:25 PM PDT 24
Finished Jun 24 04:45:42 PM PDT 24
Peak memory 219172 kb
Host smart-5d9cdd7d-d7e2-4660-ad15-b05a0a080b39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925466083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1925466083
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2286949774
Short name T224
Test name
Test status
Simulation time 7549443681 ps
CPU time 31.32 seconds
Started Jun 24 04:44:27 PM PDT 24
Finished Jun 24 04:45:00 PM PDT 24
Peak memory 217300 kb
Host smart-bed65553-4d70-45d7-8bd6-89d84d2cde30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286949774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2286949774
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1913883851
Short name T41
Test name
Test status
Simulation time 42496191896 ps
CPU time 493.79 seconds
Started Jun 24 04:44:26 PM PDT 24
Finished Jun 24 04:52:42 PM PDT 24
Peak memory 237936 kb
Host smart-5545ae62-1f37-4ad5-b084-685ef372a01f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913883851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1913883851
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.695894967
Short name T152
Test name
Test status
Simulation time 18582021562 ps
CPU time 46.2 seconds
Started Jun 24 04:44:27 PM PDT 24
Finished Jun 24 04:45:15 PM PDT 24
Peak memory 219220 kb
Host smart-49e0e61c-7efc-4ac1-915a-2bd1afd605c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695894967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.695894967
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3324437340
Short name T329
Test name
Test status
Simulation time 217918534 ps
CPU time 10.31 seconds
Started Jun 24 04:44:26 PM PDT 24
Finished Jun 24 04:44:37 PM PDT 24
Peak memory 219144 kb
Host smart-685da316-4e88-4941-956c-f3f90383889b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3324437340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3324437340
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2303460029
Short name T312
Test name
Test status
Simulation time 5265133404 ps
CPU time 38.56 seconds
Started Jun 24 04:44:28 PM PDT 24
Finished Jun 24 04:45:10 PM PDT 24
Peak memory 217520 kb
Host smart-44d031d9-58ef-42cd-ab2b-9cb9ae704246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303460029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2303460029
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1258383175
Short name T124
Test name
Test status
Simulation time 63330720003 ps
CPU time 163.89 seconds
Started Jun 24 04:44:27 PM PDT 24
Finished Jun 24 04:47:15 PM PDT 24
Peak memory 221004 kb
Host smart-b6c3f3fd-80f8-4c7e-9416-0070f782b85a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258383175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1258383175
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.238937746
Short name T48
Test name
Test status
Simulation time 121188309976 ps
CPU time 1192.28 seconds
Started Jun 24 04:44:28 PM PDT 24
Finished Jun 24 05:04:24 PM PDT 24
Peak memory 235940 kb
Host smart-5d848dbc-e9fe-4974-9d1e-451f2840030a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238937746 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.238937746
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.666850462
Short name T334
Test name
Test status
Simulation time 1322308673 ps
CPU time 16.66 seconds
Started Jun 24 04:44:31 PM PDT 24
Finished Jun 24 04:44:51 PM PDT 24
Peak memory 216984 kb
Host smart-8da3bd64-ee6c-4138-882e-7dd322827f94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666850462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.666850462
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2959012140
Short name T335
Test name
Test status
Simulation time 151786201238 ps
CPU time 705.6 seconds
Started Jun 24 04:44:27 PM PDT 24
Finished Jun 24 04:56:16 PM PDT 24
Peak memory 225272 kb
Host smart-e7ca12ea-9827-44e8-8247-e93c7712831f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959012140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2959012140
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1577761113
Short name T245
Test name
Test status
Simulation time 30696498670 ps
CPU time 67.09 seconds
Started Jun 24 04:44:29 PM PDT 24
Finished Jun 24 04:45:39 PM PDT 24
Peak memory 219220 kb
Host smart-22eb26f3-75e8-4c23-b77b-32f9ce85b8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577761113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1577761113
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3079443288
Short name T262
Test name
Test status
Simulation time 733907267 ps
CPU time 10.38 seconds
Started Jun 24 04:44:29 PM PDT 24
Finished Jun 24 04:44:43 PM PDT 24
Peak memory 219224 kb
Host smart-253c4546-9a02-416d-9d10-3779f4e8b670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3079443288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3079443288
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2036130464
Short name T304
Test name
Test status
Simulation time 8496455657 ps
CPU time 75.37 seconds
Started Jun 24 04:44:28 PM PDT 24
Finished Jun 24 04:45:47 PM PDT 24
Peak memory 216304 kb
Host smart-6e8187d3-df12-4b26-b420-9126189c95c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036130464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2036130464
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.596141972
Short name T333
Test name
Test status
Simulation time 27294807318 ps
CPU time 116.95 seconds
Started Jun 24 04:44:27 PM PDT 24
Finished Jun 24 04:46:26 PM PDT 24
Peak memory 220132 kb
Host smart-7519ce0e-52e3-4677-a892-86e097f29615
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596141972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.596141972
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.840390877
Short name T174
Test name
Test status
Simulation time 8190135335 ps
CPU time 20.73 seconds
Started Jun 24 04:44:31 PM PDT 24
Finished Jun 24 04:44:55 PM PDT 24
Peak memory 217320 kb
Host smart-4dfa57b1-8de7-4ebd-a554-ebd3c160b247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840390877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.840390877
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.222766760
Short name T167
Test name
Test status
Simulation time 31087930619 ps
CPU time 313.51 seconds
Started Jun 24 04:44:25 PM PDT 24
Finished Jun 24 04:49:40 PM PDT 24
Peak memory 227872 kb
Host smart-90b6ff5f-a34a-4451-9042-b1b5dc66cb30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222766760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.222766760
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.4173005462
Short name T324
Test name
Test status
Simulation time 2746283450 ps
CPU time 19.3 seconds
Started Jun 24 04:44:27 PM PDT 24
Finished Jun 24 04:44:49 PM PDT 24
Peak memory 219108 kb
Host smart-0f5275f6-94c3-4d50-b750-09ecb70339f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173005462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.4173005462
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2446059107
Short name T28
Test name
Test status
Simulation time 180469146 ps
CPU time 10.08 seconds
Started Jun 24 04:44:27 PM PDT 24
Finished Jun 24 04:44:41 PM PDT 24
Peak memory 219116 kb
Host smart-139f0ec1-1263-429e-b8d6-a7a57f076719
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2446059107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2446059107
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1687695741
Short name T44
Test name
Test status
Simulation time 8053729064 ps
CPU time 70.72 seconds
Started Jun 24 04:44:27 PM PDT 24
Finished Jun 24 04:45:41 PM PDT 24
Peak memory 216728 kb
Host smart-e8aa4334-6f9b-4be1-baef-b01cabc26ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687695741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1687695741
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1254950551
Short name T147
Test name
Test status
Simulation time 1931775843 ps
CPU time 25.97 seconds
Started Jun 24 04:44:27 PM PDT 24
Finished Jun 24 04:44:55 PM PDT 24
Peak memory 216444 kb
Host smart-ef982eb9-d10a-4918-bd99-91bffafa4225
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254950551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1254950551
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.1734441235
Short name T12
Test name
Test status
Simulation time 18028200425 ps
CPU time 744.52 seconds
Started Jun 24 04:44:26 PM PDT 24
Finished Jun 24 04:56:52 PM PDT 24
Peak memory 228600 kb
Host smart-64ad5b6c-600b-4401-a35a-1b34a610828a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734441235 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.1734441235
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1241969086
Short name T338
Test name
Test status
Simulation time 660816167 ps
CPU time 8.45 seconds
Started Jun 24 04:44:36 PM PDT 24
Finished Jun 24 04:44:48 PM PDT 24
Peak memory 216892 kb
Host smart-c7c69ed3-d471-4ad0-8946-0354ddec87c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241969086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1241969086
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3702884588
Short name T237
Test name
Test status
Simulation time 46522769345 ps
CPU time 479.25 seconds
Started Jun 24 04:44:33 PM PDT 24
Finished Jun 24 04:52:37 PM PDT 24
Peak memory 229272 kb
Host smart-5e67e759-933f-4639-be35-62b09a751ba7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702884588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3702884588
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3262251703
Short name T328
Test name
Test status
Simulation time 4125120101 ps
CPU time 19.65 seconds
Started Jun 24 04:44:35 PM PDT 24
Finished Jun 24 04:44:59 PM PDT 24
Peak memory 219108 kb
Host smart-5d81b972-221b-4b8d-87ae-a9a6a3f115a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262251703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3262251703
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.319843432
Short name T160
Test name
Test status
Simulation time 181406928 ps
CPU time 10.53 seconds
Started Jun 24 04:44:31 PM PDT 24
Finished Jun 24 04:44:45 PM PDT 24
Peak memory 219224 kb
Host smart-f428f9bb-613d-481b-b927-7e666e184843
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=319843432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.319843432
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3432923262
Short name T177
Test name
Test status
Simulation time 1023530537 ps
CPU time 27.11 seconds
Started Jun 24 04:44:36 PM PDT 24
Finished Jun 24 04:45:07 PM PDT 24
Peak memory 215636 kb
Host smart-b55be0df-fd5c-455f-a552-c5cb9a73aec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432923262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3432923262
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3208630902
Short name T337
Test name
Test status
Simulation time 1607607384 ps
CPU time 39.96 seconds
Started Jun 24 04:44:33 PM PDT 24
Finished Jun 24 04:45:16 PM PDT 24
Peak memory 219076 kb
Host smart-a5693398-c1a8-44eb-b61d-15bf5ce943b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208630902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3208630902
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3688839772
Short name T267
Test name
Test status
Simulation time 3296954553 ps
CPU time 8.43 seconds
Started Jun 24 04:44:34 PM PDT 24
Finished Jun 24 04:44:46 PM PDT 24
Peak memory 217072 kb
Host smart-0946cb52-2a3e-4873-86ca-8f5bdd97f976
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688839772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3688839772
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2574269377
Short name T171
Test name
Test status
Simulation time 66198154248 ps
CPU time 341.18 seconds
Started Jun 24 04:44:34 PM PDT 24
Finished Jun 24 04:50:20 PM PDT 24
Peak memory 228288 kb
Host smart-47917519-7553-4964-aa90-01a7cec055ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574269377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2574269377
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.295244154
Short name T356
Test name
Test status
Simulation time 41135286428 ps
CPU time 35.4 seconds
Started Jun 24 04:44:33 PM PDT 24
Finished Jun 24 04:45:11 PM PDT 24
Peak memory 219120 kb
Host smart-db675ba3-dcfb-4558-94a8-b2fc8909fc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295244154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.295244154
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.668165471
Short name T163
Test name
Test status
Simulation time 1857432945 ps
CPU time 16.43 seconds
Started Jun 24 04:44:35 PM PDT 24
Finished Jun 24 04:44:56 PM PDT 24
Peak memory 211116 kb
Host smart-288d712f-44bf-4ff7-9e2c-46be20a6597b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=668165471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.668165471
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1600860395
Short name T271
Test name
Test status
Simulation time 565435770 ps
CPU time 19.96 seconds
Started Jun 24 04:44:32 PM PDT 24
Finished Jun 24 04:44:56 PM PDT 24
Peak memory 215972 kb
Host smart-9ebf8838-d975-45b5-b3fa-3d73bec73d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600860395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1600860395
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2783805879
Short name T233
Test name
Test status
Simulation time 8023487359 ps
CPU time 88.88 seconds
Started Jun 24 04:44:33 PM PDT 24
Finished Jun 24 04:46:06 PM PDT 24
Peak memory 219240 kb
Host smart-0ffd9aea-661f-411c-a56f-7d4594168346
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783805879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2783805879
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.112947123
Short name T326
Test name
Test status
Simulation time 9503641969 ps
CPU time 23.13 seconds
Started Jun 24 04:44:34 PM PDT 24
Finished Jun 24 04:45:01 PM PDT 24
Peak memory 217204 kb
Host smart-6c25de69-a538-4422-9a19-3f3e2ddcb36d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112947123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.112947123
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2019858283
Short name T218
Test name
Test status
Simulation time 1436179859 ps
CPU time 19.36 seconds
Started Jun 24 04:44:32 PM PDT 24
Finished Jun 24 04:44:54 PM PDT 24
Peak memory 219124 kb
Host smart-555c1d6d-9fd3-4dce-b14e-3155f9ddac7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019858283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2019858283
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3208997476
Short name T216
Test name
Test status
Simulation time 7194530535 ps
CPU time 29.56 seconds
Started Jun 24 04:44:33 PM PDT 24
Finished Jun 24 04:45:05 PM PDT 24
Peak memory 219180 kb
Host smart-d064f4fb-6248-4a53-a8e5-7ff6d15e2ebd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3208997476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3208997476
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3497395880
Short name T149
Test name
Test status
Simulation time 360321221 ps
CPU time 20.23 seconds
Started Jun 24 04:44:34 PM PDT 24
Finished Jun 24 04:44:58 PM PDT 24
Peak memory 215800 kb
Host smart-9f7c4fd0-fc5e-4be0-b03e-401f51ce46a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497395880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3497395880
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1321529551
Short name T319
Test name
Test status
Simulation time 89326859698 ps
CPU time 202.69 seconds
Started Jun 24 04:44:34 PM PDT 24
Finished Jun 24 04:48:01 PM PDT 24
Peak memory 219248 kb
Host smart-b5cfcfa9-19d7-4614-b16a-1204687ec719
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321529551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1321529551
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3099845347
Short name T50
Test name
Test status
Simulation time 86078310615 ps
CPU time 5597.73 seconds
Started Jun 24 04:44:38 PM PDT 24
Finished Jun 24 06:17:59 PM PDT 24
Peak memory 239960 kb
Host smart-55f1b720-0ab1-41a1-974e-0d1bf4a9c6bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099845347 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.3099845347
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2287040007
Short name T170
Test name
Test status
Simulation time 3075817679 ps
CPU time 13.52 seconds
Started Jun 24 04:44:33 PM PDT 24
Finished Jun 24 04:44:50 PM PDT 24
Peak memory 217048 kb
Host smart-bc1fffcf-abd6-44ba-88a0-da1a3597dbd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287040007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2287040007
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1543952086
Short name T38
Test name
Test status
Simulation time 14606987140 ps
CPU time 297.66 seconds
Started Jun 24 04:44:33 PM PDT 24
Finished Jun 24 04:49:34 PM PDT 24
Peak memory 216604 kb
Host smart-3e6bd678-b657-48b2-a1b2-f7d59cf79499
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543952086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1543952086
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2671352266
Short name T257
Test name
Test status
Simulation time 6213997106 ps
CPU time 58.43 seconds
Started Jun 24 04:44:33 PM PDT 24
Finished Jun 24 04:45:35 PM PDT 24
Peak memory 219216 kb
Host smart-273779f0-7ee0-4d4d-bada-5ded5e6bbc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671352266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2671352266
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1865227863
Short name T127
Test name
Test status
Simulation time 2091556463 ps
CPU time 14.07 seconds
Started Jun 24 04:44:33 PM PDT 24
Finished Jun 24 04:44:51 PM PDT 24
Peak memory 219116 kb
Host smart-27ba125e-4d4c-4dce-ac30-bbbd768f33d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1865227863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1865227863
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3324527831
Short name T193
Test name
Test status
Simulation time 10674213482 ps
CPU time 52.49 seconds
Started Jun 24 04:44:32 PM PDT 24
Finished Jun 24 04:45:28 PM PDT 24
Peak memory 215192 kb
Host smart-728917e2-9edb-4978-964c-46dfffa051ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324527831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3324527831
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.532283341
Short name T84
Test name
Test status
Simulation time 40996901095 ps
CPU time 81.55 seconds
Started Jun 24 04:44:33 PM PDT 24
Finished Jun 24 04:45:58 PM PDT 24
Peak memory 219192 kb
Host smart-bbe945a8-61cc-446f-bb91-24960f4cfda4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532283341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.532283341
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1188294037
Short name T276
Test name
Test status
Simulation time 2634500845 ps
CPU time 24.92 seconds
Started Jun 24 04:43:43 PM PDT 24
Finished Jun 24 04:44:13 PM PDT 24
Peak memory 217012 kb
Host smart-04da0e1a-4f06-40ca-8f44-c9efcaa96305
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188294037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1188294037
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1588625995
Short name T153
Test name
Test status
Simulation time 8271192427 ps
CPU time 250.55 seconds
Started Jun 24 04:43:39 PM PDT 24
Finished Jun 24 04:47:55 PM PDT 24
Peak memory 236928 kb
Host smart-81c34952-01b8-40af-8ee8-4e038ebe655b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588625995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1588625995
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.326998454
Short name T56
Test name
Test status
Simulation time 8172288149 ps
CPU time 65.93 seconds
Started Jun 24 04:43:41 PM PDT 24
Finished Jun 24 04:44:53 PM PDT 24
Peak memory 219096 kb
Host smart-3a1ad044-d341-45d3-b1ef-38c17079885b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326998454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.326998454
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.513083555
Short name T199
Test name
Test status
Simulation time 3568045358 ps
CPU time 30.27 seconds
Started Jun 24 04:43:40 PM PDT 24
Finished Jun 24 04:44:15 PM PDT 24
Peak memory 219188 kb
Host smart-7bd25a9f-6b29-4e77-88e5-a196da28d2ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=513083555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.513083555
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1406022906
Short name T284
Test name
Test status
Simulation time 2124212364 ps
CPU time 23.03 seconds
Started Jun 24 04:43:42 PM PDT 24
Finished Jun 24 04:44:10 PM PDT 24
Peak memory 216588 kb
Host smart-db4ee95f-acf4-4a04-8c86-9ebea37b4699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406022906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1406022906
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3462500578
Short name T162
Test name
Test status
Simulation time 5160500535 ps
CPU time 62.47 seconds
Started Jun 24 04:43:47 PM PDT 24
Finished Jun 24 04:44:55 PM PDT 24
Peak memory 220716 kb
Host smart-e79b8e01-b983-48b6-8338-1e1cc0a54f4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462500578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3462500578
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.818862336
Short name T238
Test name
Test status
Simulation time 9609870307 ps
CPU time 28.15 seconds
Started Jun 24 04:43:43 PM PDT 24
Finished Jun 24 04:44:17 PM PDT 24
Peak memory 217320 kb
Host smart-3c069a0d-af74-432e-a170-a28dc97190fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818862336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.818862336
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.90327801
Short name T288
Test name
Test status
Simulation time 78944874793 ps
CPU time 381.12 seconds
Started Jun 24 04:43:41 PM PDT 24
Finished Jun 24 04:50:07 PM PDT 24
Peak memory 238632 kb
Host smart-15596ae6-029c-4883-8f35-000ed877db82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90327801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_cor
rupt_sig_fatal_chk.90327801
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1918892234
Short name T248
Test name
Test status
Simulation time 6661044925 ps
CPU time 59.21 seconds
Started Jun 24 04:43:42 PM PDT 24
Finished Jun 24 04:44:47 PM PDT 24
Peak memory 219504 kb
Host smart-b7e6c819-3273-47d6-846e-dab2611647d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918892234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1918892234
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.221592027
Short name T281
Test name
Test status
Simulation time 1016701737 ps
CPU time 17.11 seconds
Started Jun 24 04:43:40 PM PDT 24
Finished Jun 24 04:44:02 PM PDT 24
Peak memory 218224 kb
Host smart-9d2f79d2-5170-442b-ba59-527e89eaf1cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=221592027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.221592027
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1489513194
Short name T332
Test name
Test status
Simulation time 4301147121 ps
CPU time 52.66 seconds
Started Jun 24 04:43:39 PM PDT 24
Finished Jun 24 04:44:36 PM PDT 24
Peak memory 216108 kb
Host smart-330fe22e-7752-46cc-bbc8-58f848a99ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489513194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1489513194
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3511852114
Short name T203
Test name
Test status
Simulation time 2283111200 ps
CPU time 28.53 seconds
Started Jun 24 04:43:43 PM PDT 24
Finished Jun 24 04:44:17 PM PDT 24
Peak memory 216356 kb
Host smart-3b2c1b33-2d55-429e-92d4-d83b60cc20d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511852114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3511852114
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3671092714
Short name T201
Test name
Test status
Simulation time 16016271542 ps
CPU time 31.12 seconds
Started Jun 24 04:43:39 PM PDT 24
Finished Jun 24 04:44:16 PM PDT 24
Peak memory 217408 kb
Host smart-9e7b5a1c-9efa-49cd-b93a-c5d6b2e29d65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671092714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3671092714
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3726046998
Short name T210
Test name
Test status
Simulation time 54260466964 ps
CPU time 207.15 seconds
Started Jun 24 04:43:43 PM PDT 24
Finished Jun 24 04:47:15 PM PDT 24
Peak memory 233540 kb
Host smart-eaf03632-e7d3-40ce-a3ba-019eedb1d256
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726046998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3726046998
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3725842781
Short name T236
Test name
Test status
Simulation time 5416785056 ps
CPU time 51.92 seconds
Started Jun 24 04:43:41 PM PDT 24
Finished Jun 24 04:44:38 PM PDT 24
Peak memory 219516 kb
Host smart-8c21303e-e681-45c5-aa3c-f6ca43f2bc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725842781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3725842781
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.2893874296
Short name T291
Test name
Test status
Simulation time 729024022 ps
CPU time 10.8 seconds
Started Jun 24 04:43:46 PM PDT 24
Finished Jun 24 04:44:01 PM PDT 24
Peak memory 219084 kb
Host smart-ad94d756-84a5-4a01-961b-4d7bf123edd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2893874296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.2893874296
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1798864540
Short name T205
Test name
Test status
Simulation time 360045792 ps
CPU time 20.71 seconds
Started Jun 24 04:43:42 PM PDT 24
Finished Jun 24 04:44:08 PM PDT 24
Peak memory 215524 kb
Host smart-12dd45bb-5b52-4974-ae45-3e364f10d2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798864540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1798864540
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2534913165
Short name T239
Test name
Test status
Simulation time 14909146737 ps
CPU time 82.24 seconds
Started Jun 24 04:43:41 PM PDT 24
Finished Jun 24 04:45:09 PM PDT 24
Peak memory 219252 kb
Host smart-a1d789be-3a2b-4064-ae0c-934b7262660d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534913165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2534913165
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4214222047
Short name T339
Test name
Test status
Simulation time 688600750 ps
CPU time 8.22 seconds
Started Jun 24 04:43:41 PM PDT 24
Finished Jun 24 04:43:54 PM PDT 24
Peak memory 216864 kb
Host smart-424521ab-3e83-47d7-a1c4-184727bb8380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214222047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4214222047
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1322980598
Short name T139
Test name
Test status
Simulation time 807074374745 ps
CPU time 813.95 seconds
Started Jun 24 04:43:45 PM PDT 24
Finished Jun 24 04:57:24 PM PDT 24
Peak memory 217732 kb
Host smart-64be6c2e-f4f7-44fa-b35f-850529b22cf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322980598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1322980598
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2116476783
Short name T54
Test name
Test status
Simulation time 51877654173 ps
CPU time 57.4 seconds
Started Jun 24 04:43:39 PM PDT 24
Finished Jun 24 04:44:41 PM PDT 24
Peak memory 219064 kb
Host smart-6082549f-65fd-4fcc-8e40-d17d799ceac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116476783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2116476783
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.159759139
Short name T352
Test name
Test status
Simulation time 1482129683 ps
CPU time 19.68 seconds
Started Jun 24 04:43:42 PM PDT 24
Finished Jun 24 04:44:07 PM PDT 24
Peak memory 217396 kb
Host smart-38a26a19-fb83-4e97-b889-f63363e7d5b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=159759139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.159759139
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3648292433
Short name T331
Test name
Test status
Simulation time 1370493346 ps
CPU time 20.29 seconds
Started Jun 24 04:43:41 PM PDT 24
Finished Jun 24 04:44:06 PM PDT 24
Peak memory 216624 kb
Host smart-86731042-52fa-4c78-8a33-8f5ca50eaac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648292433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3648292433
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3187209017
Short name T269
Test name
Test status
Simulation time 91619344251 ps
CPU time 201.21 seconds
Started Jun 24 04:43:39 PM PDT 24
Finished Jun 24 04:47:05 PM PDT 24
Peak memory 220344 kb
Host smart-5ad2efc1-64cb-4a7a-aab3-af70f8df6bae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187209017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3187209017
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1804592743
Short name T343
Test name
Test status
Simulation time 8024139543 ps
CPU time 32.39 seconds
Started Jun 24 04:43:48 PM PDT 24
Finished Jun 24 04:44:26 PM PDT 24
Peak memory 217292 kb
Host smart-f8d364cc-1c09-4489-9464-364859bc7fbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804592743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1804592743
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.4196249761
Short name T39
Test name
Test status
Simulation time 22896747870 ps
CPU time 360.82 seconds
Started Jun 24 04:43:51 PM PDT 24
Finished Jun 24 04:49:58 PM PDT 24
Peak memory 236608 kb
Host smart-c2738bd8-ad13-48d2-a6c4-c99f0170f880
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196249761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.4196249761
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3786471512
Short name T20
Test name
Test status
Simulation time 62323186210 ps
CPU time 62.08 seconds
Started Jun 24 04:43:47 PM PDT 24
Finished Jun 24 04:44:55 PM PDT 24
Peak memory 219036 kb
Host smart-69e8ed28-7cde-4052-b0be-9bddec95334f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786471512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3786471512
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2514633899
Short name T146
Test name
Test status
Simulation time 4189628227 ps
CPU time 33.19 seconds
Started Jun 24 04:43:56 PM PDT 24
Finished Jun 24 04:44:36 PM PDT 24
Peak memory 211248 kb
Host smart-ffd65c0a-ef19-451a-b075-08d704446882
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2514633899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2514633899
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1151203078
Short name T165
Test name
Test status
Simulation time 4566765175 ps
CPU time 45.37 seconds
Started Jun 24 04:43:49 PM PDT 24
Finished Jun 24 04:44:39 PM PDT 24
Peak memory 216680 kb
Host smart-5312034e-5823-4f37-b8ab-5c12c7e6edca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151203078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1151203078
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.4229565946
Short name T286
Test name
Test status
Simulation time 17993845954 ps
CPU time 63.85 seconds
Started Jun 24 04:43:49 PM PDT 24
Finished Jun 24 04:44:58 PM PDT 24
Peak memory 219168 kb
Host smart-995bd179-6db5-4792-a312-5072ae6d7137
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229565946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.4229565946
Directory /workspace/9.rom_ctrl_stress_all/latest
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