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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.28 96.89 92.13 97.68 100.00 98.62 97.30 98.37


Total test records in report: 461
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T15 /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3384995681 Jun 25 05:59:57 PM PDT 24 Jun 25 07:03:43 PM PDT 24 446305200987 ps
T299 /workspace/coverage/default/23.rom_ctrl_stress_all.3876662043 Jun 25 05:59:25 PM PDT 24 Jun 25 06:01:13 PM PDT 24 11673140881 ps
T300 /workspace/coverage/default/40.rom_ctrl_smoke.3461339098 Jun 25 06:00:21 PM PDT 24 Jun 25 06:01:16 PM PDT 24 26975950673 ps
T109 /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2024177232 Jun 25 06:00:31 PM PDT 24 Jun 25 06:17:59 PM PDT 24 26150023558 ps
T301 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3695009896 Jun 25 06:00:27 PM PDT 24 Jun 25 06:00:56 PM PDT 24 3297203653 ps
T16 /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.859651187 Jun 25 06:00:23 PM PDT 24 Jun 25 08:37:04 PM PDT 24 41612221338 ps
T302 /workspace/coverage/default/6.rom_ctrl_stress_all.1394394894 Jun 25 05:58:29 PM PDT 24 Jun 25 06:00:23 PM PDT 24 36324634812 ps
T303 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2508268622 Jun 25 05:59:10 PM PDT 24 Jun 25 06:06:33 PM PDT 24 55658170491 ps
T304 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1904754843 Jun 25 06:00:42 PM PDT 24 Jun 25 06:03:08 PM PDT 24 3932184090 ps
T305 /workspace/coverage/default/8.rom_ctrl_stress_all.1635584673 Jun 25 05:58:34 PM PDT 24 Jun 25 05:59:43 PM PDT 24 2115100270 ps
T306 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2271351902 Jun 25 05:59:44 PM PDT 24 Jun 25 06:00:17 PM PDT 24 3368557244 ps
T307 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3541667766 Jun 25 05:59:51 PM PDT 24 Jun 25 06:02:38 PM PDT 24 3987273849 ps
T308 /workspace/coverage/default/13.rom_ctrl_smoke.3263005232 Jun 25 05:58:50 PM PDT 24 Jun 25 05:59:12 PM PDT 24 1574257997 ps
T309 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1742157740 Jun 25 06:00:28 PM PDT 24 Jun 25 06:00:57 PM PDT 24 6436342692 ps
T48 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1171147914 Jun 25 05:58:43 PM PDT 24 Jun 25 05:59:50 PM PDT 24 8504159780 ps
T310 /workspace/coverage/default/14.rom_ctrl_smoke.1017999554 Jun 25 05:58:50 PM PDT 24 Jun 25 05:59:30 PM PDT 24 2359290196 ps
T311 /workspace/coverage/default/20.rom_ctrl_smoke.1873381085 Jun 25 05:59:17 PM PDT 24 Jun 25 06:00:03 PM PDT 24 16380361730 ps
T312 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.873197425 Jun 25 05:58:36 PM PDT 24 Jun 25 05:59:38 PM PDT 24 27986262476 ps
T313 /workspace/coverage/default/0.rom_ctrl_smoke.3951629842 Jun 25 05:57:46 PM PDT 24 Jun 25 05:58:29 PM PDT 24 3073955091 ps
T314 /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1124657430 Jun 25 05:59:42 PM PDT 24 Jun 25 06:15:40 PM PDT 24 24622327027 ps
T315 /workspace/coverage/default/44.rom_ctrl_smoke.1360151695 Jun 25 06:00:27 PM PDT 24 Jun 25 06:00:49 PM PDT 24 1386012678 ps
T316 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2998269857 Jun 25 06:00:37 PM PDT 24 Jun 25 06:01:38 PM PDT 24 76561945309 ps
T317 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3247140077 Jun 25 05:58:41 PM PDT 24 Jun 25 05:58:52 PM PDT 24 881204550 ps
T318 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1754500701 Jun 25 05:59:51 PM PDT 24 Jun 25 06:07:04 PM PDT 24 119910038742 ps
T319 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4274386810 Jun 25 05:59:39 PM PDT 24 Jun 25 06:00:16 PM PDT 24 2392418729 ps
T320 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2467794112 Jun 25 06:00:08 PM PDT 24 Jun 25 06:00:32 PM PDT 24 8609962757 ps
T321 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1325423399 Jun 25 05:59:02 PM PDT 24 Jun 25 06:03:25 PM PDT 24 7891414801 ps
T322 /workspace/coverage/default/46.rom_ctrl_stress_all.1868622779 Jun 25 06:00:35 PM PDT 24 Jun 25 06:01:01 PM PDT 24 387485331 ps
T323 /workspace/coverage/default/10.rom_ctrl_stress_all.2990580411 Jun 25 05:58:34 PM PDT 24 Jun 25 05:59:30 PM PDT 24 4629583931 ps
T324 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1199679058 Jun 25 06:00:35 PM PDT 24 Jun 25 06:01:10 PM PDT 24 4282351452 ps
T325 /workspace/coverage/default/29.rom_ctrl_stress_all.3121824285 Jun 25 05:59:50 PM PDT 24 Jun 25 06:01:43 PM PDT 24 35111620927 ps
T326 /workspace/coverage/default/31.rom_ctrl_stress_all.692865894 Jun 25 05:59:57 PM PDT 24 Jun 25 06:00:50 PM PDT 24 10666611308 ps
T327 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.815142387 Jun 25 05:59:09 PM PDT 24 Jun 25 05:59:42 PM PDT 24 15708694483 ps
T328 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3660117055 Jun 25 05:59:28 PM PDT 24 Jun 25 06:05:18 PM PDT 24 86043884225 ps
T329 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.701422376 Jun 25 05:59:42 PM PDT 24 Jun 25 06:00:56 PM PDT 24 17035659816 ps
T330 /workspace/coverage/default/48.rom_ctrl_stress_all.3088862906 Jun 25 06:00:35 PM PDT 24 Jun 25 06:00:50 PM PDT 24 281360376 ps
T331 /workspace/coverage/default/3.rom_ctrl_smoke.3334245512 Jun 25 05:58:09 PM PDT 24 Jun 25 05:58:55 PM PDT 24 14517623916 ps
T332 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1082772467 Jun 25 05:59:28 PM PDT 24 Jun 25 06:07:23 PM PDT 24 210673685475 ps
T333 /workspace/coverage/default/26.rom_ctrl_alert_test.3938256560 Jun 25 05:59:41 PM PDT 24 Jun 25 06:00:10 PM PDT 24 2924673956 ps
T334 /workspace/coverage/default/38.rom_ctrl_alert_test.2388751662 Jun 25 06:00:21 PM PDT 24 Jun 25 06:00:40 PM PDT 24 5789344122 ps
T335 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3817952964 Jun 25 05:59:26 PM PDT 24 Jun 25 06:00:07 PM PDT 24 3443459453 ps
T336 /workspace/coverage/default/3.rom_ctrl_stress_all.2725263940 Jun 25 05:58:21 PM PDT 24 Jun 25 06:00:16 PM PDT 24 53911388755 ps
T337 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3356396475 Jun 25 05:59:58 PM PDT 24 Jun 25 06:00:12 PM PDT 24 355607165 ps
T338 /workspace/coverage/default/27.rom_ctrl_smoke.675802535 Jun 25 05:59:42 PM PDT 24 Jun 25 06:00:21 PM PDT 24 1657000708 ps
T339 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2238779507 Jun 25 06:00:21 PM PDT 24 Jun 25 06:00:37 PM PDT 24 1024882528 ps
T340 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2309659205 Jun 25 05:59:57 PM PDT 24 Jun 25 06:00:46 PM PDT 24 15694283252 ps
T341 /workspace/coverage/default/19.rom_ctrl_stress_all.1398466383 Jun 25 05:59:17 PM PDT 24 Jun 25 06:02:09 PM PDT 24 17123835263 ps
T342 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2138058480 Jun 25 05:58:28 PM PDT 24 Jun 25 06:03:24 PM PDT 24 33570405980 ps
T343 /workspace/coverage/default/35.rom_ctrl_stress_all.2997821517 Jun 25 06:00:05 PM PDT 24 Jun 25 06:02:57 PM PDT 24 17085774993 ps
T344 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2844894777 Jun 25 06:00:44 PM PDT 24 Jun 25 06:01:10 PM PDT 24 2746563944 ps
T345 /workspace/coverage/default/2.rom_ctrl_smoke.4099002694 Jun 25 05:58:04 PM PDT 24 Jun 25 05:58:43 PM PDT 24 11625407299 ps
T346 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2032566801 Jun 25 05:58:20 PM PDT 24 Jun 25 05:58:57 PM PDT 24 2349647751 ps
T347 /workspace/coverage/default/49.rom_ctrl_smoke.3835751329 Jun 25 06:00:44 PM PDT 24 Jun 25 06:02:04 PM PDT 24 8141267208 ps
T348 /workspace/coverage/default/45.rom_ctrl_stress_all.545230789 Jun 25 06:00:28 PM PDT 24 Jun 25 06:01:12 PM PDT 24 825819486 ps
T349 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.282645442 Jun 25 06:00:21 PM PDT 24 Jun 25 06:02:59 PM PDT 24 3470067769 ps
T350 /workspace/coverage/default/18.rom_ctrl_stress_all.1541297590 Jun 25 05:59:17 PM PDT 24 Jun 25 06:00:13 PM PDT 24 13372964191 ps
T351 /workspace/coverage/default/39.rom_ctrl_alert_test.1557307923 Jun 25 06:00:22 PM PDT 24 Jun 25 06:00:41 PM PDT 24 2617373561 ps
T352 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1794320950 Jun 25 06:00:28 PM PDT 24 Jun 25 06:06:17 PM PDT 24 152307515200 ps
T353 /workspace/coverage/default/20.rom_ctrl_alert_test.2714406719 Jun 25 05:59:25 PM PDT 24 Jun 25 05:59:50 PM PDT 24 6082951139 ps
T354 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2255236466 Jun 25 05:59:26 PM PDT 24 Jun 25 05:59:47 PM PDT 24 346487571 ps
T355 /workspace/coverage/default/31.rom_ctrl_alert_test.2250397013 Jun 25 05:59:56 PM PDT 24 Jun 25 06:00:23 PM PDT 24 3769259278 ps
T356 /workspace/coverage/default/29.rom_ctrl_alert_test.3475597322 Jun 25 05:59:52 PM PDT 24 Jun 25 06:00:29 PM PDT 24 7056451173 ps
T357 /workspace/coverage/default/21.rom_ctrl_alert_test.3469044508 Jun 25 05:59:26 PM PDT 24 Jun 25 05:59:36 PM PDT 24 2354494233 ps
T358 /workspace/coverage/default/18.rom_ctrl_alert_test.2352727868 Jun 25 05:59:17 PM PDT 24 Jun 25 05:59:34 PM PDT 24 4989740416 ps
T359 /workspace/coverage/default/4.rom_ctrl_alert_test.1690728302 Jun 25 05:58:19 PM PDT 24 Jun 25 05:58:51 PM PDT 24 4591827013 ps
T360 /workspace/coverage/default/9.rom_ctrl_alert_test.3378659 Jun 25 05:58:41 PM PDT 24 Jun 25 05:59:05 PM PDT 24 3393623311 ps
T64 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3379029243 Jun 25 04:47:59 PM PDT 24 Jun 25 04:48:34 PM PDT 24 16043009453 ps
T65 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.537749090 Jun 25 04:48:31 PM PDT 24 Jun 25 04:48:58 PM PDT 24 2997818035 ps
T66 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1449972177 Jun 25 04:48:07 PM PDT 24 Jun 25 04:48:33 PM PDT 24 749968167 ps
T361 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1444886748 Jun 25 04:47:52 PM PDT 24 Jun 25 04:48:19 PM PDT 24 5046682672 ps
T71 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1668654535 Jun 25 04:48:29 PM PDT 24 Jun 25 04:51:56 PM PDT 24 50073718339 ps
T61 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.939547575 Jun 25 04:47:57 PM PDT 24 Jun 25 04:50:56 PM PDT 24 21610541514 ps
T72 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2179534259 Jun 25 04:47:55 PM PDT 24 Jun 25 04:49:54 PM PDT 24 26790660532 ps
T103 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3709026836 Jun 25 04:48:32 PM PDT 24 Jun 25 04:49:42 PM PDT 24 1035803618 ps
T96 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1521677424 Jun 25 04:48:19 PM PDT 24 Jun 25 04:48:34 PM PDT 24 346027370 ps
T362 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1728800545 Jun 25 04:47:56 PM PDT 24 Jun 25 04:48:28 PM PDT 24 12400397833 ps
T62 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2900490280 Jun 25 04:47:58 PM PDT 24 Jun 25 04:49:39 PM PDT 24 8474697381 ps
T73 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2779102393 Jun 25 04:47:59 PM PDT 24 Jun 25 04:48:27 PM PDT 24 10865569039 ps
T63 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3504151388 Jun 25 04:47:56 PM PDT 24 Jun 25 04:50:38 PM PDT 24 352639398 ps
T74 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.787855774 Jun 25 04:48:21 PM PDT 24 Jun 25 04:50:33 PM PDT 24 133761793218 ps
T97 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3708896314 Jun 25 04:47:56 PM PDT 24 Jun 25 04:48:14 PM PDT 24 1778913486 ps
T363 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1568874137 Jun 25 04:47:49 PM PDT 24 Jun 25 04:48:06 PM PDT 24 739063128 ps
T112 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.945639937 Jun 25 04:48:01 PM PDT 24 Jun 25 04:50:48 PM PDT 24 2018228559 ps
T364 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3878831403 Jun 25 04:47:57 PM PDT 24 Jun 25 04:48:13 PM PDT 24 717610677 ps
T104 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1509547415 Jun 25 04:47:58 PM PDT 24 Jun 25 04:48:42 PM PDT 24 694042819 ps
T365 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2527539936 Jun 25 04:47:52 PM PDT 24 Jun 25 04:48:13 PM PDT 24 2512933751 ps
T75 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2450732037 Jun 25 04:48:23 PM PDT 24 Jun 25 04:48:56 PM PDT 24 2809572416 ps
T366 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.230562829 Jun 25 04:47:52 PM PDT 24 Jun 25 04:48:29 PM PDT 24 7724933626 ps
T367 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4219076023 Jun 25 04:48:28 PM PDT 24 Jun 25 04:49:16 PM PDT 24 7845783410 ps
T368 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2676980614 Jun 25 04:48:27 PM PDT 24 Jun 25 04:49:08 PM PDT 24 7548363658 ps
T76 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2906718771 Jun 25 04:47:55 PM PDT 24 Jun 25 04:51:09 PM PDT 24 24080089090 ps
T369 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2626222327 Jun 25 04:48:10 PM PDT 24 Jun 25 04:50:23 PM PDT 24 16257183522 ps
T370 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2083102750 Jun 25 04:48:30 PM PDT 24 Jun 25 04:48:57 PM PDT 24 689310535 ps
T371 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3870247989 Jun 25 04:47:54 PM PDT 24 Jun 25 04:48:23 PM PDT 24 7549283123 ps
T372 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2222958904 Jun 25 04:47:53 PM PDT 24 Jun 25 04:48:13 PM PDT 24 2759473087 ps
T373 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1197385423 Jun 25 04:47:53 PM PDT 24 Jun 25 04:48:22 PM PDT 24 11564777527 ps
T77 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1170827160 Jun 25 04:47:55 PM PDT 24 Jun 25 04:50:39 PM PDT 24 90861971432 ps
T374 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3871536493 Jun 25 04:48:19 PM PDT 24 Jun 25 04:48:47 PM PDT 24 12550554351 ps
T98 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1688710484 Jun 25 04:47:57 PM PDT 24 Jun 25 04:48:16 PM PDT 24 343545381 ps
T115 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.749704727 Jun 25 04:47:55 PM PDT 24 Jun 25 04:50:39 PM PDT 24 6971335590 ps
T375 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.141148231 Jun 25 04:48:09 PM PDT 24 Jun 25 04:48:41 PM PDT 24 15129513422 ps
T113 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1403663290 Jun 25 04:47:56 PM PDT 24 Jun 25 04:50:43 PM PDT 24 2580863616 ps
T78 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3752077611 Jun 25 04:47:56 PM PDT 24 Jun 25 04:48:17 PM PDT 24 4891528712 ps
T376 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1016206635 Jun 25 04:47:52 PM PDT 24 Jun 25 04:48:18 PM PDT 24 5612604698 ps
T377 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3268786085 Jun 25 04:47:58 PM PDT 24 Jun 25 04:48:23 PM PDT 24 2389806625 ps
T378 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2005206158 Jun 25 04:48:03 PM PDT 24 Jun 25 04:48:15 PM PDT 24 1002032028 ps
T379 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1679788176 Jun 25 04:47:54 PM PDT 24 Jun 25 04:48:14 PM PDT 24 1220776577 ps
T380 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3616942625 Jun 25 04:47:51 PM PDT 24 Jun 25 04:48:22 PM PDT 24 3104428230 ps
T99 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.290503893 Jun 25 04:48:26 PM PDT 24 Jun 25 04:48:46 PM PDT 24 661309622 ps
T79 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3171543696 Jun 25 04:48:23 PM PDT 24 Jun 25 04:49:05 PM PDT 24 17389844113 ps
T110 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3068431747 Jun 25 04:48:20 PM PDT 24 Jun 25 04:51:10 PM PDT 24 3380712824 ps
T381 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.687718018 Jun 25 04:47:58 PM PDT 24 Jun 25 04:48:26 PM PDT 24 7769897237 ps
T100 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2080327609 Jun 25 04:47:51 PM PDT 24 Jun 25 04:48:09 PM PDT 24 679133608 ps
T87 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1106959868 Jun 25 04:48:25 PM PDT 24 Jun 25 04:48:55 PM PDT 24 8193680004 ps
T382 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.12968180 Jun 25 04:48:23 PM PDT 24 Jun 25 04:48:41 PM PDT 24 612935320 ps
T383 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2593574777 Jun 25 04:47:57 PM PDT 24 Jun 25 04:48:35 PM PDT 24 8583561061 ps
T88 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.4120286033 Jun 25 04:47:52 PM PDT 24 Jun 25 04:48:04 PM PDT 24 345381703 ps
T90 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2106957903 Jun 25 04:48:05 PM PDT 24 Jun 25 04:49:56 PM PDT 24 11845969416 ps
T95 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1159721874 Jun 25 04:48:16 PM PDT 24 Jun 25 04:48:26 PM PDT 24 169337422 ps
T384 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.172509998 Jun 25 04:48:01 PM PDT 24 Jun 25 04:48:13 PM PDT 24 710390126 ps
T385 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.154879988 Jun 25 04:47:56 PM PDT 24 Jun 25 04:48:25 PM PDT 24 2809897329 ps
T386 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4240996589 Jun 25 04:47:51 PM PDT 24 Jun 25 04:48:15 PM PDT 24 4082818829 ps
T101 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3336761148 Jun 25 04:47:52 PM PDT 24 Jun 25 04:48:17 PM PDT 24 5647351681 ps
T387 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.184120536 Jun 25 04:48:24 PM PDT 24 Jun 25 04:50:23 PM PDT 24 12616086882 ps
T102 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2439421792 Jun 25 04:48:23 PM PDT 24 Jun 25 04:48:59 PM PDT 24 5222721090 ps
T388 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3662677188 Jun 25 04:48:00 PM PDT 24 Jun 25 04:48:15 PM PDT 24 495901816 ps
T389 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3101544067 Jun 25 04:48:07 PM PDT 24 Jun 25 04:48:44 PM PDT 24 15720369593 ps
T390 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3465852458 Jun 25 04:47:57 PM PDT 24 Jun 25 04:48:34 PM PDT 24 16764580820 ps
T111 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.378187693 Jun 25 04:48:10 PM PDT 24 Jun 25 04:51:05 PM PDT 24 14643480583 ps
T94 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.560140960 Jun 25 04:47:52 PM PDT 24 Jun 25 04:51:20 PM PDT 24 109789761910 ps
T391 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4245373362 Jun 25 04:47:52 PM PDT 24 Jun 25 04:48:30 PM PDT 24 4435348494 ps
T392 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.199300005 Jun 25 04:48:19 PM PDT 24 Jun 25 04:48:43 PM PDT 24 7893546860 ps
T393 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1746131780 Jun 25 04:47:52 PM PDT 24 Jun 25 04:48:26 PM PDT 24 4457859300 ps
T394 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1105962926 Jun 25 04:47:55 PM PDT 24 Jun 25 04:48:22 PM PDT 24 1804890407 ps
T395 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2339488143 Jun 25 04:47:56 PM PDT 24 Jun 25 04:50:12 PM PDT 24 49233386345 ps
T116 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1395720444 Jun 25 04:47:56 PM PDT 24 Jun 25 04:49:30 PM PDT 24 337851007 ps
T91 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3042249407 Jun 25 04:47:56 PM PDT 24 Jun 25 04:48:10 PM PDT 24 199191030 ps
T396 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.524644817 Jun 25 04:47:56 PM PDT 24 Jun 25 04:48:22 PM PDT 24 13540222280 ps
T397 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1014182086 Jun 25 04:48:22 PM PDT 24 Jun 25 04:49:03 PM PDT 24 14827817503 ps
T398 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4096816641 Jun 25 04:48:14 PM PDT 24 Jun 25 04:48:43 PM PDT 24 3889776230 ps
T119 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2099836290 Jun 25 04:47:52 PM PDT 24 Jun 25 04:49:41 PM PDT 24 22191840599 ps
T399 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1023834916 Jun 25 04:48:14 PM PDT 24 Jun 25 04:48:41 PM PDT 24 12897316514 ps
T400 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2768966296 Jun 25 04:47:52 PM PDT 24 Jun 25 04:48:11 PM PDT 24 3785972396 ps
T401 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.595139459 Jun 25 04:48:02 PM PDT 24 Jun 25 04:48:13 PM PDT 24 167787063 ps
T402 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1701577941 Jun 25 04:48:22 PM PDT 24 Jun 25 04:48:49 PM PDT 24 7206229124 ps
T403 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.331557908 Jun 25 04:47:55 PM PDT 24 Jun 25 04:48:10 PM PDT 24 1322504524 ps
T404 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2872155763 Jun 25 04:47:59 PM PDT 24 Jun 25 04:49:20 PM PDT 24 28390968891 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.18752370 Jun 25 04:47:52 PM PDT 24 Jun 25 04:48:23 PM PDT 24 13422991954 ps
T406 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.881073932 Jun 25 04:47:58 PM PDT 24 Jun 25 04:48:35 PM PDT 24 4144922343 ps
T407 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2013531274 Jun 25 04:47:57 PM PDT 24 Jun 25 04:48:21 PM PDT 24 2939958882 ps
T408 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2233413724 Jun 25 04:48:05 PM PDT 24 Jun 25 04:48:18 PM PDT 24 338356188 ps
T409 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.442977368 Jun 25 04:48:21 PM PDT 24 Jun 25 04:48:59 PM PDT 24 6861092958 ps
T410 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2480697720 Jun 25 04:48:21 PM PDT 24 Jun 25 04:48:39 PM PDT 24 717322439 ps
T411 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.460059478 Jun 25 04:47:53 PM PDT 24 Jun 25 04:49:21 PM PDT 24 277964362 ps
T412 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1694070114 Jun 25 04:47:49 PM PDT 24 Jun 25 04:48:25 PM PDT 24 4351099725 ps
T413 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.304873080 Jun 25 04:48:21 PM PDT 24 Jun 25 04:48:36 PM PDT 24 172822429 ps
T414 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.529091913 Jun 25 04:47:58 PM PDT 24 Jun 25 04:48:32 PM PDT 24 3672184823 ps
T415 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3170411985 Jun 25 04:47:54 PM PDT 24 Jun 25 04:48:07 PM PDT 24 552009681 ps
T118 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3038770657 Jun 25 04:48:20 PM PDT 24 Jun 25 04:49:46 PM PDT 24 1023957280 ps
T416 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4032602594 Jun 25 04:47:59 PM PDT 24 Jun 25 04:48:34 PM PDT 24 4294868915 ps
T417 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2611107012 Jun 25 04:47:55 PM PDT 24 Jun 25 04:48:08 PM PDT 24 331898204 ps
T418 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.586426427 Jun 25 04:48:14 PM PDT 24 Jun 25 04:48:24 PM PDT 24 174598952 ps
T419 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1583655176 Jun 25 04:47:52 PM PDT 24 Jun 25 04:48:34 PM PDT 24 10002668134 ps
T420 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3747540768 Jun 25 04:47:54 PM PDT 24 Jun 25 04:48:12 PM PDT 24 788069090 ps
T421 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1504170926 Jun 25 04:48:09 PM PDT 24 Jun 25 04:48:22 PM PDT 24 174363494 ps
T422 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1940629279 Jun 25 04:48:21 PM PDT 24 Jun 25 04:51:56 PM PDT 24 150707121153 ps
T423 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1229043011 Jun 25 04:47:51 PM PDT 24 Jun 25 04:48:13 PM PDT 24 13631292856 ps
T424 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3919650007 Jun 25 04:47:54 PM PDT 24 Jun 25 04:50:50 PM PDT 24 4827357917 ps
T425 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3521392358 Jun 25 04:48:25 PM PDT 24 Jun 25 04:49:03 PM PDT 24 62718919557 ps
T426 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2945501570 Jun 25 04:47:55 PM PDT 24 Jun 25 04:48:22 PM PDT 24 2286574976 ps
T427 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.127556593 Jun 25 04:48:11 PM PDT 24 Jun 25 04:48:35 PM PDT 24 2431753014 ps
T428 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3665916787 Jun 25 04:47:56 PM PDT 24 Jun 25 04:48:24 PM PDT 24 20676835364 ps
T429 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.530324207 Jun 25 04:48:28 PM PDT 24 Jun 25 04:49:03 PM PDT 24 2212282173 ps
T430 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2140801662 Jun 25 04:47:57 PM PDT 24 Jun 25 04:48:19 PM PDT 24 1579902377 ps
T431 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3290517085 Jun 25 04:48:15 PM PDT 24 Jun 25 04:48:51 PM PDT 24 3780910695 ps
T432 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1558106250 Jun 25 04:48:18 PM PDT 24 Jun 25 04:48:52 PM PDT 24 14416120495 ps
T433 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2731568845 Jun 25 04:47:51 PM PDT 24 Jun 25 04:50:36 PM PDT 24 17295826153 ps
T434 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4021080702 Jun 25 04:48:23 PM PDT 24 Jun 25 04:49:12 PM PDT 24 4235782459 ps
T120 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4107129162 Jun 25 04:48:19 PM PDT 24 Jun 25 04:49:47 PM PDT 24 255025311 ps
T435 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1141023929 Jun 25 04:47:56 PM PDT 24 Jun 25 04:48:19 PM PDT 24 1432537806 ps
T436 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.851596887 Jun 25 04:47:56 PM PDT 24 Jun 25 04:48:34 PM PDT 24 40174974935 ps
T437 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.480425172 Jun 25 04:48:24 PM PDT 24 Jun 25 04:48:45 PM PDT 24 576347338 ps
T438 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4010426056 Jun 25 04:47:54 PM PDT 24 Jun 25 04:48:10 PM PDT 24 177949530 ps
T439 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3274765592 Jun 25 04:47:57 PM PDT 24 Jun 25 04:48:31 PM PDT 24 14312477517 ps
T440 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2596944647 Jun 25 04:48:08 PM PDT 24 Jun 25 04:49:37 PM PDT 24 2048489174 ps
T441 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2347856472 Jun 25 04:47:55 PM PDT 24 Jun 25 04:49:40 PM PDT 24 14445313319 ps
T442 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.410472701 Jun 25 04:48:23 PM PDT 24 Jun 25 04:51:08 PM PDT 24 304494520 ps
T443 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1358178724 Jun 25 04:47:52 PM PDT 24 Jun 25 04:48:04 PM PDT 24 167763438 ps
T444 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3173956433 Jun 25 04:48:15 PM PDT 24 Jun 25 04:49:14 PM PDT 24 2668486870 ps
T445 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.138080765 Jun 25 04:47:51 PM PDT 24 Jun 25 04:48:28 PM PDT 24 4752081480 ps
T446 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.385719925 Jun 25 04:47:51 PM PDT 24 Jun 25 04:48:09 PM PDT 24 636230898 ps
T447 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4230251335 Jun 25 04:47:56 PM PDT 24 Jun 25 04:50:47 PM PDT 24 2878368529 ps
T448 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1039872192 Jun 25 04:47:57 PM PDT 24 Jun 25 04:48:33 PM PDT 24 6653967590 ps
T449 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.433605692 Jun 25 04:47:50 PM PDT 24 Jun 25 04:48:19 PM PDT 24 28612693774 ps
T89 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4201781453 Jun 25 04:48:25 PM PDT 24 Jun 25 04:49:00 PM PDT 24 5899635673 ps
T450 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2976785455 Jun 25 04:47:49 PM PDT 24 Jun 25 04:48:00 PM PDT 24 175596913 ps
T92 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3592946407 Jun 25 04:47:56 PM PDT 24 Jun 25 04:48:39 PM PDT 24 705091311 ps
T451 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.773817999 Jun 25 04:47:57 PM PDT 24 Jun 25 04:48:30 PM PDT 24 20237096002 ps
T452 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3547801045 Jun 25 04:47:52 PM PDT 24 Jun 25 04:48:17 PM PDT 24 7568800647 ps
T453 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3759293392 Jun 25 04:48:18 PM PDT 24 Jun 25 04:48:43 PM PDT 24 2397077386 ps
T454 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2088795931 Jun 25 04:47:58 PM PDT 24 Jun 25 04:48:31 PM PDT 24 15308810880 ps
T455 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1080598605 Jun 25 04:47:56 PM PDT 24 Jun 25 04:48:23 PM PDT 24 4417214752 ps
T117 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3039958527 Jun 25 04:47:56 PM PDT 24 Jun 25 04:50:57 PM PDT 24 8294428216 ps
T93 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1565638949 Jun 25 04:47:54 PM PDT 24 Jun 25 04:50:54 PM PDT 24 42119937627 ps
T456 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3977478926 Jun 25 04:48:20 PM PDT 24 Jun 25 04:48:37 PM PDT 24 2036065722 ps
T457 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1696561603 Jun 25 04:48:33 PM PDT 24 Jun 25 04:49:08 PM PDT 24 2106101395 ps
T458 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3270027632 Jun 25 04:47:57 PM PDT 24 Jun 25 04:48:27 PM PDT 24 5577536901 ps
T459 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1612408668 Jun 25 04:48:32 PM PDT 24 Jun 25 04:50:18 PM PDT 24 1994313818 ps
T114 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1030661469 Jun 25 04:47:53 PM PDT 24 Jun 25 04:50:34 PM PDT 24 631072479 ps
T460 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3454134210 Jun 25 04:48:21 PM PDT 24 Jun 25 04:48:40 PM PDT 24 174479743 ps
T461 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.269922060 Jun 25 04:47:57 PM PDT 24 Jun 25 04:49:33 PM PDT 24 27504753572 ps

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3108888042
Short name T6
Test name
Test status
Simulation time 85956138252 ps
CPU time 711.05 seconds
Started Jun 25 06:00:20 PM PDT 24
Finished Jun 25 06:12:12 PM PDT 24
Peak memory 224600 kb
Host smart-b0e305a0-bd30-4c29-8a1f-d54a62033c0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108888042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3108888042
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3304546174
Short name T11
Test name
Test status
Simulation time 45654779537 ps
CPU time 872.63 seconds
Started Jun 25 05:58:27 PM PDT 24
Finished Jun 25 06:13:00 PM PDT 24
Peak memory 231236 kb
Host smart-8bf866d5-a06d-4f8e-b59e-358004a4845c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304546174 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.3304546174
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.939547575
Short name T61
Test name
Test status
Simulation time 21610541514 ps
CPU time 174.32 seconds
Started Jun 25 04:47:57 PM PDT 24
Finished Jun 25 04:50:56 PM PDT 24
Peak memory 213900 kb
Host smart-b11c50e7-a507-4993-9173-d7b302c09d94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939547575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.939547575
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3814610738
Short name T46
Test name
Test status
Simulation time 5181704651 ps
CPU time 57.37 seconds
Started Jun 25 06:00:30 PM PDT 24
Finished Jun 25 06:01:28 PM PDT 24
Peak memory 216844 kb
Host smart-9c6b1996-e30c-43f2-b2c8-db00266b03be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814610738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3814610738
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.839282781
Short name T182
Test name
Test status
Simulation time 41756529700 ps
CPU time 581.61 seconds
Started Jun 25 05:59:58 PM PDT 24
Finished Jun 25 06:09:43 PM PDT 24
Peak memory 238180 kb
Host smart-625a5a42-b8a5-4377-8f45-43dc397b28c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839282781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.839282781
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2179534259
Short name T72
Test name
Test status
Simulation time 26790660532 ps
CPU time 114.26 seconds
Started Jun 25 04:47:55 PM PDT 24
Finished Jun 25 04:49:54 PM PDT 24
Peak memory 213884 kb
Host smart-8e8c3d3b-8c07-4ec9-af99-6a14d7d1fcb3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179534259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2179534259
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.272573964
Short name T21
Test name
Test status
Simulation time 11665534740 ps
CPU time 243.38 seconds
Started Jun 25 05:58:21 PM PDT 24
Finished Jun 25 06:02:26 PM PDT 24
Peak memory 238384 kb
Host smart-815e1254-7cf2-438a-b0a1-75d1a9201139
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272573964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.272573964
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2037683439
Short name T24
Test name
Test status
Simulation time 171009480 ps
CPU time 8.57 seconds
Started Jun 25 05:58:51 PM PDT 24
Finished Jun 25 05:59:01 PM PDT 24
Peak memory 217268 kb
Host smart-23f34c48-8722-4440-898d-cf1fbf242d03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037683439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2037683439
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3504151388
Short name T63
Test name
Test status
Simulation time 352639398 ps
CPU time 155.99 seconds
Started Jun 25 04:47:56 PM PDT 24
Finished Jun 25 04:50:38 PM PDT 24
Peak memory 213752 kb
Host smart-38f79ea1-e32f-4125-b85c-ad2d94185f64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504151388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3504151388
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1030661469
Short name T114
Test name
Test status
Simulation time 631072479 ps
CPU time 155.37 seconds
Started Jun 25 04:47:53 PM PDT 24
Finished Jun 25 04:50:34 PM PDT 24
Peak memory 213908 kb
Host smart-8f2e551b-17b5-4f6d-952a-ffdaeb22dbd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030661469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1030661469
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.684937208
Short name T133
Test name
Test status
Simulation time 4605275355 ps
CPU time 27.23 seconds
Started Jun 25 06:00:05 PM PDT 24
Finished Jun 25 06:00:33 PM PDT 24
Peak memory 219444 kb
Host smart-842ba79f-44e2-4b36-aaf6-1a856d5d65ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684937208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.684937208
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3063377889
Short name T45
Test name
Test status
Simulation time 1319974589 ps
CPU time 19.23 seconds
Started Jun 25 06:00:29 PM PDT 24
Finished Jun 25 06:00:50 PM PDT 24
Peak memory 219368 kb
Host smart-3417d1d2-6fbf-4120-af36-312a14cfbf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063377889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3063377889
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1171147914
Short name T48
Test name
Test status
Simulation time 8504159780 ps
CPU time 66.63 seconds
Started Jun 25 05:58:43 PM PDT 24
Finished Jun 25 05:59:50 PM PDT 24
Peak memory 219416 kb
Host smart-9182b276-f2e7-4ce5-92da-d11dc973b50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171147914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1171147914
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.4065875824
Short name T1
Test name
Test status
Simulation time 2200530361 ps
CPU time 22.69 seconds
Started Jun 25 05:59:35 PM PDT 24
Finished Jun 25 06:00:01 PM PDT 24
Peak memory 219444 kb
Host smart-191aa573-6f2b-4871-a150-39e8df812608
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4065875824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.4065875824
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.410472701
Short name T442
Test name
Test status
Simulation time 304494520 ps
CPU time 155.56 seconds
Started Jun 25 04:48:23 PM PDT 24
Finished Jun 25 04:51:08 PM PDT 24
Peak memory 214008 kb
Host smart-dc7a140e-c219-4942-893b-f91fbcd326b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410472701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.410472701
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.57585224
Short name T3
Test name
Test status
Simulation time 120522907456 ps
CPU time 574.98 seconds
Started Jun 25 05:58:43 PM PDT 24
Finished Jun 25 06:08:19 PM PDT 24
Peak memory 236140 kb
Host smart-f339d9a6-81a8-4191-9c6c-7a0d89c39ada
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57585224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_co
rrupt_sig_fatal_chk.57585224
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2080327609
Short name T100
Test name
Test status
Simulation time 679133608 ps
CPU time 14.34 seconds
Started Jun 25 04:47:51 PM PDT 24
Finished Jun 25 04:48:09 PM PDT 24
Peak memory 212316 kb
Host smart-bba702dd-1d0e-4fee-bf49-385162d651bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080327609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2080327609
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3384995681
Short name T15
Test name
Test status
Simulation time 446305200987 ps
CPU time 3821.46 seconds
Started Jun 25 05:59:57 PM PDT 24
Finished Jun 25 07:03:43 PM PDT 24
Peak memory 252228 kb
Host smart-130397c7-11ce-42d3-a459-d05e0d7c88ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384995681 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.3384995681
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.638190311
Short name T181
Test name
Test status
Simulation time 88723038871 ps
CPU time 168.88 seconds
Started Jun 25 05:58:20 PM PDT 24
Finished Jun 25 06:01:11 PM PDT 24
Peak memory 219864 kb
Host smart-4878073e-1a98-4282-9553-5e404e75450a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638190311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.638190311
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3101544067
Short name T389
Test name
Test status
Simulation time 15720369593 ps
CPU time 30.62 seconds
Started Jun 25 04:48:07 PM PDT 24
Finished Jun 25 04:48:44 PM PDT 24
Peak memory 212180 kb
Host smart-4f455282-d8ba-4919-902e-10ff95394d67
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101544067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3101544067
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1568874137
Short name T363
Test name
Test status
Simulation time 739063128 ps
CPU time 13.96 seconds
Started Jun 25 04:47:49 PM PDT 24
Finished Jun 25 04:48:06 PM PDT 24
Peak memory 210592 kb
Host smart-1831adeb-11e5-4b93-a57f-174125a25a84
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568874137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1568874137
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2222958904
Short name T372
Test name
Test status
Simulation time 2759473087 ps
CPU time 15.58 seconds
Started Jun 25 04:47:53 PM PDT 24
Finished Jun 25 04:48:13 PM PDT 24
Peak memory 210628 kb
Host smart-b3c61d92-7aa9-4ebc-b03d-458bc5461c07
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222958904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2222958904
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4032602594
Short name T416
Test name
Test status
Simulation time 4294868915 ps
CPU time 30.98 seconds
Started Jun 25 04:47:59 PM PDT 24
Finished Jun 25 04:48:34 PM PDT 24
Peak memory 216984 kb
Host smart-6f8f1796-de76-4a4f-a2aa-f912d7778faa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032602594 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.4032602594
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.4120286033
Short name T88
Test name
Test status
Simulation time 345381703 ps
CPU time 8.24 seconds
Started Jun 25 04:47:52 PM PDT 24
Finished Jun 25 04:48:04 PM PDT 24
Peak memory 210516 kb
Host smart-bed211d3-ad52-45b4-9e8a-33eaa7c945f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120286033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.4120286033
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1694070114
Short name T412
Test name
Test status
Simulation time 4351099725 ps
CPU time 33.35 seconds
Started Jun 25 04:47:49 PM PDT 24
Finished Jun 25 04:48:25 PM PDT 24
Peak memory 210520 kb
Host smart-a2fcf96f-c218-456f-bdb5-5bb21f4c49b3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694070114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1694070114
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.230562829
Short name T366
Test name
Test status
Simulation time 7724933626 ps
CPU time 32.39 seconds
Started Jun 25 04:47:52 PM PDT 24
Finished Jun 25 04:48:29 PM PDT 24
Peak memory 210492 kb
Host smart-45705949-37d6-4b04-a5a2-976edfcca57c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230562829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
230562829
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.560140960
Short name T94
Test name
Test status
Simulation time 109789761910 ps
CPU time 204.02 seconds
Started Jun 25 04:47:52 PM PDT 24
Finished Jun 25 04:51:20 PM PDT 24
Peak memory 214956 kb
Host smart-0ea024f4-ab4b-4d7e-8d2c-8bf1834f0308
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560140960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.560140960
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.433605692
Short name T449
Test name
Test status
Simulation time 28612693774 ps
CPU time 26.46 seconds
Started Jun 25 04:47:50 PM PDT 24
Finished Jun 25 04:48:19 PM PDT 24
Peak memory 218580 kb
Host smart-453f8555-2b78-4a04-b626-9d70401c3b3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433605692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.433605692
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3039958527
Short name T117
Test name
Test status
Simulation time 8294428216 ps
CPU time 176.14 seconds
Started Jun 25 04:47:56 PM PDT 24
Finished Jun 25 04:50:57 PM PDT 24
Peak memory 214240 kb
Host smart-cf3a57f6-944f-4cca-bb24-8e8d3aa14385
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039958527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3039958527
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.138080765
Short name T445
Test name
Test status
Simulation time 4752081480 ps
CPU time 32.35 seconds
Started Jun 25 04:47:51 PM PDT 24
Finished Jun 25 04:48:28 PM PDT 24
Peak memory 211460 kb
Host smart-45c918a5-3cc2-4d3d-9644-6dad169aae56
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138080765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.138080765
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1358178724
Short name T443
Test name
Test status
Simulation time 167763438 ps
CPU time 8.58 seconds
Started Jun 25 04:47:52 PM PDT 24
Finished Jun 25 04:48:04 PM PDT 24
Peak memory 210596 kb
Host smart-e5d92dde-94c7-4d9e-8a7c-ff4809a0a5d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358178724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1358178724
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1016206635
Short name T376
Test name
Test status
Simulation time 5612604698 ps
CPU time 21.07 seconds
Started Jun 25 04:47:52 PM PDT 24
Finished Jun 25 04:48:18 PM PDT 24
Peak memory 212028 kb
Host smart-7aa273e9-1e06-4fec-b420-6ec5b04848f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016206635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1016206635
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2976785455
Short name T450
Test name
Test status
Simulation time 175596913 ps
CPU time 8.79 seconds
Started Jun 25 04:47:49 PM PDT 24
Finished Jun 25 04:48:00 PM PDT 24
Peak memory 216780 kb
Host smart-63c3d8df-544c-4563-877f-4383bb280844
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976785455 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2976785455
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.4245373362
Short name T391
Test name
Test status
Simulation time 4435348494 ps
CPU time 34.09 seconds
Started Jun 25 04:47:52 PM PDT 24
Finished Jun 25 04:48:30 PM PDT 24
Peak memory 211776 kb
Host smart-582b6881-99ac-4baa-9db5-df0e763e32fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245373362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.4245373362
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3274765592
Short name T439
Test name
Test status
Simulation time 14312477517 ps
CPU time 28.86 seconds
Started Jun 25 04:47:57 PM PDT 24
Finished Jun 25 04:48:31 PM PDT 24
Peak memory 211000 kb
Host smart-b9a1bf27-0a8a-4311-8003-356745a682e5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274765592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3274765592
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1444886748
Short name T361
Test name
Test status
Simulation time 5046682672 ps
CPU time 21.81 seconds
Started Jun 25 04:47:52 PM PDT 24
Finished Jun 25 04:48:19 PM PDT 24
Peak memory 210524 kb
Host smart-475c2080-b419-450e-b07e-7e663bf679b4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444886748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1444886748
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2872155763
Short name T404
Test name
Test status
Simulation time 28390968891 ps
CPU time 76.98 seconds
Started Jun 25 04:47:59 PM PDT 24
Finished Jun 25 04:49:20 PM PDT 24
Peak memory 213792 kb
Host smart-4cebd06c-258a-424a-bb06-a5d43dff71e9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872155763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2872155763
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3336761148
Short name T101
Test name
Test status
Simulation time 5647351681 ps
CPU time 20.98 seconds
Started Jun 25 04:47:52 PM PDT 24
Finished Jun 25 04:48:17 PM PDT 24
Peak memory 212576 kb
Host smart-89a9b580-5796-4fe4-bb53-0a9a66e7eaca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336761148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3336761148
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.687718018
Short name T381
Test name
Test status
Simulation time 7769897237 ps
CPU time 23.07 seconds
Started Jun 25 04:47:58 PM PDT 24
Finished Jun 25 04:48:26 PM PDT 24
Peak memory 219056 kb
Host smart-627cd4cd-2b83-480c-9740-d0e7e7c0146d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687718018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.687718018
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2900490280
Short name T62
Test name
Test status
Simulation time 8474697381 ps
CPU time 94.06 seconds
Started Jun 25 04:47:58 PM PDT 24
Finished Jun 25 04:49:39 PM PDT 24
Peak memory 214056 kb
Host smart-3d10974e-50d6-4b37-82a6-3e8617d3a7f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900490280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2900490280
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.172509998
Short name T384
Test name
Test status
Simulation time 710390126 ps
CPU time 8.77 seconds
Started Jun 25 04:48:01 PM PDT 24
Finished Jun 25 04:48:13 PM PDT 24
Peak memory 218888 kb
Host smart-65493103-6b1e-4626-b1d4-e0433a0492f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172509998 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.172509998
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2140801662
Short name T430
Test name
Test status
Simulation time 1579902377 ps
CPU time 17.77 seconds
Started Jun 25 04:47:57 PM PDT 24
Finished Jun 25 04:48:19 PM PDT 24
Peak memory 211832 kb
Host smart-2a8a6e7f-1e21-4166-b5cc-4e9b25455f83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140801662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2140801662
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2906718771
Short name T76
Test name
Test status
Simulation time 24080089090 ps
CPU time 188.86 seconds
Started Jun 25 04:47:55 PM PDT 24
Finished Jun 25 04:51:09 PM PDT 24
Peak memory 215228 kb
Host smart-21d9f388-ff6f-422e-8bad-f722995035f7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906718771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2906718771
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.773817999
Short name T451
Test name
Test status
Simulation time 20237096002 ps
CPU time 28.46 seconds
Started Jun 25 04:47:57 PM PDT 24
Finished Jun 25 04:48:30 PM PDT 24
Peak memory 212688 kb
Host smart-4b5676ac-c5b5-4d54-90fd-f04308948bbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773817999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.773817999
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1039872192
Short name T448
Test name
Test status
Simulation time 6653967590 ps
CPU time 30.96 seconds
Started Jun 25 04:47:57 PM PDT 24
Finished Jun 25 04:48:33 PM PDT 24
Peak memory 217456 kb
Host smart-14bb2f80-0b64-4335-8a3f-8d19b054d815
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039872192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1039872192
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.749704727
Short name T115
Test name
Test status
Simulation time 6971335590 ps
CPU time 159.69 seconds
Started Jun 25 04:47:55 PM PDT 24
Finished Jun 25 04:50:39 PM PDT 24
Peak memory 214272 kb
Host smart-997fe3fe-4009-472e-9168-87d908d098e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749704727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.749704727
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1679788176
Short name T379
Test name
Test status
Simulation time 1220776577 ps
CPU time 15.54 seconds
Started Jun 25 04:47:54 PM PDT 24
Finished Jun 25 04:48:14 PM PDT 24
Peak memory 214188 kb
Host smart-01b7e254-0e35-404c-bc3d-8d055ad4e201
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679788176 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1679788176
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3752077611
Short name T78
Test name
Test status
Simulation time 4891528712 ps
CPU time 16.5 seconds
Started Jun 25 04:47:56 PM PDT 24
Finished Jun 25 04:48:17 PM PDT 24
Peak memory 211988 kb
Host smart-457d6779-4661-4c10-9f75-d30b2002575f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752077611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3752077611
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1509547415
Short name T104
Test name
Test status
Simulation time 694042819 ps
CPU time 38.91 seconds
Started Jun 25 04:47:58 PM PDT 24
Finished Jun 25 04:48:42 PM PDT 24
Peak memory 213668 kb
Host smart-6fb6ffc1-0b0b-4309-9601-8b7bb9c77015
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509547415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1509547415
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3759293392
Short name T453
Test name
Test status
Simulation time 2397077386 ps
CPU time 22.73 seconds
Started Jun 25 04:48:18 PM PDT 24
Finished Jun 25 04:48:43 PM PDT 24
Peak memory 212168 kb
Host smart-f49f76f2-8bd4-44e8-8b9f-38b01d196055
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759293392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3759293392
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4096816641
Short name T398
Test name
Test status
Simulation time 3889776230 ps
CPU time 27.83 seconds
Started Jun 25 04:48:14 PM PDT 24
Finished Jun 25 04:48:43 PM PDT 24
Peak memory 218360 kb
Host smart-934c41da-e45a-4379-8cab-ee7bb131a227
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096816641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.4096816641
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.378187693
Short name T111
Test name
Test status
Simulation time 14643480583 ps
CPU time 173.75 seconds
Started Jun 25 04:48:10 PM PDT 24
Finished Jun 25 04:51:05 PM PDT 24
Peak memory 214072 kb
Host smart-80d4c967-17dc-4928-9193-607c447623bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378187693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.378187693
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.141148231
Short name T375
Test name
Test status
Simulation time 15129513422 ps
CPU time 30.67 seconds
Started Jun 25 04:48:09 PM PDT 24
Finished Jun 25 04:48:41 PM PDT 24
Peak memory 217644 kb
Host smart-b07cb2f3-fabc-4dca-9483-eeb5fe8958d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141148231 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.141148231
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1080598605
Short name T455
Test name
Test status
Simulation time 4417214752 ps
CPU time 21.52 seconds
Started Jun 25 04:47:56 PM PDT 24
Finished Jun 25 04:48:23 PM PDT 24
Peak memory 212020 kb
Host smart-2dcd48bc-cd43-4e3d-8840-498101c9fb70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080598605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1080598605
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1668654535
Short name T71
Test name
Test status
Simulation time 50073718339 ps
CPU time 194.88 seconds
Started Jun 25 04:48:29 PM PDT 24
Finished Jun 25 04:51:56 PM PDT 24
Peak memory 214844 kb
Host smart-d5829c4b-bf84-4977-8c75-881c9b7be945
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668654535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1668654535
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2945501570
Short name T426
Test name
Test status
Simulation time 2286574976 ps
CPU time 22.06 seconds
Started Jun 25 04:47:55 PM PDT 24
Finished Jun 25 04:48:22 PM PDT 24
Peak memory 212064 kb
Host smart-6351a0bb-d06f-4a87-bff0-091fbb5f7bc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945501570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2945501570
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3878831403
Short name T364
Test name
Test status
Simulation time 717610677 ps
CPU time 11.44 seconds
Started Jun 25 04:47:57 PM PDT 24
Finished Jun 25 04:48:13 PM PDT 24
Peak memory 217120 kb
Host smart-91deb646-a34b-4bc3-971b-2bcda56d3987
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878831403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3878831403
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1403663290
Short name T113
Test name
Test status
Simulation time 2580863616 ps
CPU time 161.07 seconds
Started Jun 25 04:47:56 PM PDT 24
Finished Jun 25 04:50:43 PM PDT 24
Peak memory 213828 kb
Host smart-6dac7d4a-8155-4db0-a4eb-ca3756ef6d9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403663290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1403663290
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3977478926
Short name T456
Test name
Test status
Simulation time 2036065722 ps
CPU time 12.13 seconds
Started Jun 25 04:48:20 PM PDT 24
Finished Jun 25 04:48:37 PM PDT 24
Peak memory 218792 kb
Host smart-6cc679e1-02d1-4e12-9d5a-b5f0037fbd06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977478926 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3977478926
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2611107012
Short name T417
Test name
Test status
Simulation time 331898204 ps
CPU time 8.37 seconds
Started Jun 25 04:47:55 PM PDT 24
Finished Jun 25 04:48:08 PM PDT 24
Peak memory 210616 kb
Host smart-89aedc70-e8a6-40a3-809d-c92adcf4b66a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611107012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2611107012
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.184120536
Short name T387
Test name
Test status
Simulation time 12616086882 ps
CPU time 109.67 seconds
Started Jun 25 04:48:24 PM PDT 24
Finished Jun 25 04:50:23 PM PDT 24
Peak memory 213808 kb
Host smart-11b171da-17a5-4c28-9113-40d6252079cc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184120536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.184120536
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.304873080
Short name T413
Test name
Test status
Simulation time 172822429 ps
CPU time 8.09 seconds
Started Jun 25 04:48:21 PM PDT 24
Finished Jun 25 04:48:36 PM PDT 24
Peak memory 211068 kb
Host smart-61b8bd22-21ef-4d4d-823f-23f846611b51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304873080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.304873080
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1504170926
Short name T421
Test name
Test status
Simulation time 174363494 ps
CPU time 11.98 seconds
Started Jun 25 04:48:09 PM PDT 24
Finished Jun 25 04:48:22 PM PDT 24
Peak memory 217396 kb
Host smart-928e56bc-2100-473f-b1c1-70e1e5e7676b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504170926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1504170926
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3068431747
Short name T110
Test name
Test status
Simulation time 3380712824 ps
CPU time 165.09 seconds
Started Jun 25 04:48:20 PM PDT 24
Finished Jun 25 04:51:10 PM PDT 24
Peak memory 214988 kb
Host smart-c424bf7b-355a-4c36-8c7d-39471c3262b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068431747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3068431747
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2676980614
Short name T368
Test name
Test status
Simulation time 7548363658 ps
CPU time 29.22 seconds
Started Jun 25 04:48:27 PM PDT 24
Finished Jun 25 04:49:08 PM PDT 24
Peak memory 215036 kb
Host smart-aa16e476-d498-439a-8322-c35c285e5f13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676980614 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2676980614
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4201781453
Short name T89
Test name
Test status
Simulation time 5899635673 ps
CPU time 23.6 seconds
Started Jun 25 04:48:25 PM PDT 24
Finished Jun 25 04:49:00 PM PDT 24
Peak memory 210588 kb
Host smart-730759a7-7532-4835-9a0c-48f11a0c9412
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201781453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.4201781453
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3173956433
Short name T444
Test name
Test status
Simulation time 2668486870 ps
CPU time 55.92 seconds
Started Jun 25 04:48:15 PM PDT 24
Finished Jun 25 04:49:14 PM PDT 24
Peak memory 213828 kb
Host smart-321221ee-b18e-484f-98f4-c4f4a32866c6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173956433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3173956433
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2439421792
Short name T102
Test name
Test status
Simulation time 5222721090 ps
CPU time 27.74 seconds
Started Jun 25 04:48:23 PM PDT 24
Finished Jun 25 04:48:59 PM PDT 24
Peak memory 212684 kb
Host smart-ef7e9187-e030-46f8-b848-b4151126b715
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439421792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2439421792
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2013531274
Short name T407
Test name
Test status
Simulation time 2939958882 ps
CPU time 18.46 seconds
Started Jun 25 04:47:57 PM PDT 24
Finished Jun 25 04:48:21 PM PDT 24
Peak memory 218476 kb
Host smart-98b3b543-6fc8-49e1-a89c-353f5271a021
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013531274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2013531274
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1612408668
Short name T459
Test name
Test status
Simulation time 1994313818 ps
CPU time 92.37 seconds
Started Jun 25 04:48:32 PM PDT 24
Finished Jun 25 04:50:18 PM PDT 24
Peak memory 213572 kb
Host smart-6b262f92-f344-4594-86ce-33d6642f58e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612408668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1612408668
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.530324207
Short name T429
Test name
Test status
Simulation time 2212282173 ps
CPU time 21.69 seconds
Started Jun 25 04:48:28 PM PDT 24
Finished Jun 25 04:49:03 PM PDT 24
Peak memory 217828 kb
Host smart-a859f8ce-bf92-4692-a1c2-96d5c13b6c1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530324207 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.530324207
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1106959868
Short name T87
Test name
Test status
Simulation time 8193680004 ps
CPU time 19.9 seconds
Started Jun 25 04:48:25 PM PDT 24
Finished Jun 25 04:48:55 PM PDT 24
Peak memory 211940 kb
Host smart-37d0b030-41b3-4bc8-8031-9c9c31a198f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106959868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1106959868
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2106957903
Short name T90
Test name
Test status
Simulation time 11845969416 ps
CPU time 109.36 seconds
Started Jun 25 04:48:05 PM PDT 24
Finished Jun 25 04:49:56 PM PDT 24
Peak memory 214108 kb
Host smart-cf3bf698-479a-4820-8a2e-197b3364b17d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106957903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2106957903
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.127556593
Short name T427
Test name
Test status
Simulation time 2431753014 ps
CPU time 22.59 seconds
Started Jun 25 04:48:11 PM PDT 24
Finished Jun 25 04:48:35 PM PDT 24
Peak memory 212568 kb
Host smart-111e94b4-d83a-4679-9824-6a30646919c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127556593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.127556593
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3290517085
Short name T431
Test name
Test status
Simulation time 3780910695 ps
CPU time 34.05 seconds
Started Jun 25 04:48:15 PM PDT 24
Finished Jun 25 04:48:51 PM PDT 24
Peak memory 218268 kb
Host smart-1854a598-ef94-46c3-b93b-5324339da354
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290517085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3290517085
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1696561603
Short name T457
Test name
Test status
Simulation time 2106101395 ps
CPU time 20.71 seconds
Started Jun 25 04:48:33 PM PDT 24
Finished Jun 25 04:49:08 PM PDT 24
Peak memory 215880 kb
Host smart-3c8e4d29-7988-4529-961b-5b52f3210f5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696561603 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1696561603
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3270027632
Short name T458
Test name
Test status
Simulation time 5577536901 ps
CPU time 24.38 seconds
Started Jun 25 04:47:57 PM PDT 24
Finished Jun 25 04:48:27 PM PDT 24
Peak memory 212136 kb
Host smart-6525593e-4c12-424a-bd53-ad7154835f4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270027632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3270027632
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3709026836
Short name T103
Test name
Test status
Simulation time 1035803618 ps
CPU time 55.69 seconds
Started Jun 25 04:48:32 PM PDT 24
Finished Jun 25 04:49:42 PM PDT 24
Peak memory 214688 kb
Host smart-436875f2-3487-42f3-9bdc-5e48ebcf9e2c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709026836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3709026836
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3379029243
Short name T64
Test name
Test status
Simulation time 16043009453 ps
CPU time 31.15 seconds
Started Jun 25 04:47:59 PM PDT 24
Finished Jun 25 04:48:34 PM PDT 24
Peak memory 212280 kb
Host smart-e9c6147b-f0b3-4e7e-9bae-2852d9f9d0b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379029243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3379029243
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3870247989
Short name T371
Test name
Test status
Simulation time 7549283123 ps
CPU time 24.5 seconds
Started Jun 25 04:47:54 PM PDT 24
Finished Jun 25 04:48:23 PM PDT 24
Peak memory 218764 kb
Host smart-f5710cc8-f354-4534-952b-65461f7ac081
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870247989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3870247989
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3038770657
Short name T118
Test name
Test status
Simulation time 1023957280 ps
CPU time 81.78 seconds
Started Jun 25 04:48:20 PM PDT 24
Finished Jun 25 04:49:46 PM PDT 24
Peak memory 213668 kb
Host smart-8d4d3ef1-7d9e-40f7-be62-ec6adb7b3c5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038770657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3038770657
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1701577941
Short name T402
Test name
Test status
Simulation time 7206229124 ps
CPU time 18.93 seconds
Started Jun 25 04:48:22 PM PDT 24
Finished Jun 25 04:48:49 PM PDT 24
Peak memory 217048 kb
Host smart-fefa0dcb-d992-4989-be6d-4492382fafb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701577941 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1701577941
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1449972177
Short name T66
Test name
Test status
Simulation time 749968167 ps
CPU time 13.65 seconds
Started Jun 25 04:48:07 PM PDT 24
Finished Jun 25 04:48:33 PM PDT 24
Peak memory 210480 kb
Host smart-239c8bd5-ed45-45c1-8de3-252113face51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449972177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1449972177
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2347856472
Short name T441
Test name
Test status
Simulation time 14445313319 ps
CPU time 100.38 seconds
Started Jun 25 04:47:55 PM PDT 24
Finished Jun 25 04:49:40 PM PDT 24
Peak memory 215256 kb
Host smart-4a84ea00-d96a-4488-851d-ddbf967f0c99
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347856472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2347856472
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.480425172
Short name T437
Test name
Test status
Simulation time 576347338 ps
CPU time 9.92 seconds
Started Jun 25 04:48:24 PM PDT 24
Finished Jun 25 04:48:45 PM PDT 24
Peak memory 211072 kb
Host smart-6bbb7de1-a526-40b8-a88d-5b371d69f037
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480425172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.480425172
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2233413724
Short name T408
Test name
Test status
Simulation time 338356188 ps
CPU time 11.8 seconds
Started Jun 25 04:48:05 PM PDT 24
Finished Jun 25 04:48:18 PM PDT 24
Peak memory 218812 kb
Host smart-3d941756-5c73-4cc4-b69a-c0973a5a3755
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233413724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2233413724
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2596944647
Short name T440
Test name
Test status
Simulation time 2048489174 ps
CPU time 87.43 seconds
Started Jun 25 04:48:08 PM PDT 24
Finished Jun 25 04:49:37 PM PDT 24
Peak memory 213560 kb
Host smart-6f39a60d-553c-42ca-a8b8-ce50da35d191
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596944647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2596944647
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.199300005
Short name T392
Test name
Test status
Simulation time 7893546860 ps
CPU time 21.2 seconds
Started Jun 25 04:48:19 PM PDT 24
Finished Jun 25 04:48:43 PM PDT 24
Peak memory 214300 kb
Host smart-9bf119e4-08da-4550-9171-0962916de78a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199300005 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.199300005
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3665916787
Short name T428
Test name
Test status
Simulation time 20676835364 ps
CPU time 23.27 seconds
Started Jun 25 04:47:56 PM PDT 24
Finished Jun 25 04:48:24 PM PDT 24
Peak memory 210808 kb
Host smart-d4a4303a-f702-42ed-ab5d-c40eba256556
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665916787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3665916787
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2339488143
Short name T395
Test name
Test status
Simulation time 49233386345 ps
CPU time 130.88 seconds
Started Jun 25 04:47:56 PM PDT 24
Finished Jun 25 04:50:12 PM PDT 24
Peak memory 214912 kb
Host smart-0e8f33e2-a10b-4a83-b72e-fb8ac6d6559b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339488143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2339488143
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2088795931
Short name T454
Test name
Test status
Simulation time 15308810880 ps
CPU time 28.81 seconds
Started Jun 25 04:47:58 PM PDT 24
Finished Jun 25 04:48:31 PM PDT 24
Peak memory 212520 kb
Host smart-638a6860-d18e-44c9-9498-5c38c05516c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088795931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2088795931
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4219076023
Short name T367
Test name
Test status
Simulation time 7845783410 ps
CPU time 35.76 seconds
Started Jun 25 04:48:28 PM PDT 24
Finished Jun 25 04:49:16 PM PDT 24
Peak memory 217624 kb
Host smart-1a493445-9ddc-4073-aa7c-976275f866bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219076023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.4219076023
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.537749090
Short name T65
Test name
Test status
Simulation time 2997818035 ps
CPU time 13.87 seconds
Started Jun 25 04:48:31 PM PDT 24
Finished Jun 25 04:48:58 PM PDT 24
Peak memory 218908 kb
Host smart-f4d2008e-1884-4ce9-93cc-80c89fc39e0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537749090 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.537749090
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1159721874
Short name T95
Test name
Test status
Simulation time 169337422 ps
CPU time 8.3 seconds
Started Jun 25 04:48:16 PM PDT 24
Finished Jun 25 04:48:26 PM PDT 24
Peak memory 211060 kb
Host smart-e8966e58-b5a3-490c-984d-9f95201a05fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159721874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1159721874
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2626222327
Short name T369
Test name
Test status
Simulation time 16257183522 ps
CPU time 130.94 seconds
Started Jun 25 04:48:10 PM PDT 24
Finished Jun 25 04:50:23 PM PDT 24
Peak memory 214024 kb
Host smart-92550409-66e3-4dca-bacf-ec0483f141cb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626222327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2626222327
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1521677424
Short name T96
Test name
Test status
Simulation time 346027370 ps
CPU time 12.17 seconds
Started Jun 25 04:48:19 PM PDT 24
Finished Jun 25 04:48:34 PM PDT 24
Peak memory 212188 kb
Host smart-43107165-7f22-4048-bab3-3a9c0ca72c8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521677424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1521677424
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2083102750
Short name T370
Test name
Test status
Simulation time 689310535 ps
CPU time 13.59 seconds
Started Jun 25 04:48:30 PM PDT 24
Finished Jun 25 04:48:57 PM PDT 24
Peak memory 218468 kb
Host smart-19716c24-e547-43ae-b6e6-34d7856d1091
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083102750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2083102750
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4107129162
Short name T120
Test name
Test status
Simulation time 255025311 ps
CPU time 83.05 seconds
Started Jun 25 04:48:19 PM PDT 24
Finished Jun 25 04:49:47 PM PDT 24
Peak memory 213524 kb
Host smart-602ebb99-5432-4cfb-bb06-ef410443e886
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107129162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.4107129162
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4240996589
Short name T386
Test name
Test status
Simulation time 4082818829 ps
CPU time 20.11 seconds
Started Jun 25 04:47:51 PM PDT 24
Finished Jun 25 04:48:15 PM PDT 24
Peak memory 211040 kb
Host smart-30c26168-1478-47a5-8fc8-39661d99b3f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240996589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.4240996589
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3547801045
Short name T452
Test name
Test status
Simulation time 7568800647 ps
CPU time 21.05 seconds
Started Jun 25 04:47:52 PM PDT 24
Finished Jun 25 04:48:17 PM PDT 24
Peak memory 211948 kb
Host smart-8e63feb2-418a-4997-8261-460dd449c7f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547801045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3547801045
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1583655176
Short name T419
Test name
Test status
Simulation time 10002668134 ps
CPU time 36.99 seconds
Started Jun 25 04:47:52 PM PDT 24
Finished Jun 25 04:48:34 PM PDT 24
Peak memory 212156 kb
Host smart-6fd873ca-aee8-40d1-8fb0-b89f5884e3c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583655176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1583655176
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2768966296
Short name T400
Test name
Test status
Simulation time 3785972396 ps
CPU time 14.79 seconds
Started Jun 25 04:47:52 PM PDT 24
Finished Jun 25 04:48:11 PM PDT 24
Peak memory 215476 kb
Host smart-eaf4202f-0af0-4b10-b2a9-b959b83129c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768966296 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2768966296
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3616942625
Short name T380
Test name
Test status
Simulation time 3104428230 ps
CPU time 26.71 seconds
Started Jun 25 04:47:51 PM PDT 24
Finished Jun 25 04:48:22 PM PDT 24
Peak memory 211516 kb
Host smart-97c2a689-bfc9-4557-9ebf-5d5c95a0943f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616942625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3616942625
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2593574777
Short name T383
Test name
Test status
Simulation time 8583561061 ps
CPU time 32.91 seconds
Started Jun 25 04:47:57 PM PDT 24
Finished Jun 25 04:48:35 PM PDT 24
Peak memory 210784 kb
Host smart-fcca56e3-d9e7-490f-8f5e-bb9fdf560507
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593574777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2593574777
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1141023929
Short name T435
Test name
Test status
Simulation time 1432537806 ps
CPU time 17.34 seconds
Started Jun 25 04:47:56 PM PDT 24
Finished Jun 25 04:48:19 PM PDT 24
Peak memory 210476 kb
Host smart-4c29dd01-96e0-476a-bf77-df623e689df3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141023929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1141023929
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1170827160
Short name T77
Test name
Test status
Simulation time 90861971432 ps
CPU time 159.58 seconds
Started Jun 25 04:47:55 PM PDT 24
Finished Jun 25 04:50:39 PM PDT 24
Peak memory 215076 kb
Host smart-0250164d-135e-48a1-975d-f726e23329e9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170827160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1170827160
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.851596887
Short name T436
Test name
Test status
Simulation time 40174974935 ps
CPU time 32.72 seconds
Started Jun 25 04:47:56 PM PDT 24
Finished Jun 25 04:48:34 PM PDT 24
Peak memory 212264 kb
Host smart-2540f697-25f3-4c71-be9a-b6637a8de0a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851596887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.851596887
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.385719925
Short name T446
Test name
Test status
Simulation time 636230898 ps
CPU time 14.72 seconds
Started Jun 25 04:47:51 PM PDT 24
Finished Jun 25 04:48:09 PM PDT 24
Peak memory 216388 kb
Host smart-7e1be7e6-5a68-44af-8628-393f289012ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385719925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.385719925
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4230251335
Short name T447
Test name
Test status
Simulation time 2878368529 ps
CPU time 166.82 seconds
Started Jun 25 04:47:56 PM PDT 24
Finished Jun 25 04:50:47 PM PDT 24
Peak memory 213740 kb
Host smart-6111783a-d838-4513-9ac2-f29c6be9a8e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230251335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.4230251335
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2779102393
Short name T73
Test name
Test status
Simulation time 10865569039 ps
CPU time 24.38 seconds
Started Jun 25 04:47:59 PM PDT 24
Finished Jun 25 04:48:27 PM PDT 24
Peak memory 211960 kb
Host smart-c4fe99b5-135d-4dc9-b7dd-a3b1b663a863
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779102393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2779102393
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2527539936
Short name T365
Test name
Test status
Simulation time 2512933751 ps
CPU time 16.33 seconds
Started Jun 25 04:47:52 PM PDT 24
Finished Jun 25 04:48:13 PM PDT 24
Peak memory 210660 kb
Host smart-dc0866f5-0eca-4593-b9f5-51b73bd6fc6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527539936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2527539936
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1746131780
Short name T393
Test name
Test status
Simulation time 4457859300 ps
CPU time 30.09 seconds
Started Jun 25 04:47:52 PM PDT 24
Finished Jun 25 04:48:26 PM PDT 24
Peak memory 211332 kb
Host smart-7ec9cd04-0e64-478d-9550-c2032a663932
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746131780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1746131780
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1014182086
Short name T397
Test name
Test status
Simulation time 14827817503 ps
CPU time 31.97 seconds
Started Jun 25 04:48:22 PM PDT 24
Finished Jun 25 04:49:03 PM PDT 24
Peak memory 217988 kb
Host smart-23c5dc1a-be60-4514-a234-caf3a4fef7ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014182086 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1014182086
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.18752370
Short name T405
Test name
Test status
Simulation time 13422991954 ps
CPU time 27.43 seconds
Started Jun 25 04:47:52 PM PDT 24
Finished Jun 25 04:48:23 PM PDT 24
Peak memory 211980 kb
Host smart-361f4424-90dd-458b-914d-f99de2d8eb2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18752370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.18752370
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1197385423
Short name T373
Test name
Test status
Simulation time 11564777527 ps
CPU time 25.23 seconds
Started Jun 25 04:47:53 PM PDT 24
Finished Jun 25 04:48:22 PM PDT 24
Peak memory 210796 kb
Host smart-cbd50c8e-92bb-464b-8826-45ee5c6fb0f0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197385423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1197385423
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1229043011
Short name T423
Test name
Test status
Simulation time 13631292856 ps
CPU time 18.41 seconds
Started Jun 25 04:47:51 PM PDT 24
Finished Jun 25 04:48:13 PM PDT 24
Peak memory 210776 kb
Host smart-7a5bc8dc-b754-4381-9bd4-aed0d90caadf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229043011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1229043011
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2731568845
Short name T433
Test name
Test status
Simulation time 17295826153 ps
CPU time 160.41 seconds
Started Jun 25 04:47:51 PM PDT 24
Finished Jun 25 04:50:36 PM PDT 24
Peak memory 214740 kb
Host smart-7771ebd1-3e1b-44e2-bafc-5ae08b9234f0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731568845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2731568845
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.529091913
Short name T414
Test name
Test status
Simulation time 3672184823 ps
CPU time 29.82 seconds
Started Jun 25 04:47:58 PM PDT 24
Finished Jun 25 04:48:32 PM PDT 24
Peak memory 212408 kb
Host smart-1fac02d6-7140-4fff-accb-17c862d7cc80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529091913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.529091913
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4010426056
Short name T438
Test name
Test status
Simulation time 177949530 ps
CPU time 12.23 seconds
Started Jun 25 04:47:54 PM PDT 24
Finished Jun 25 04:48:10 PM PDT 24
Peak memory 217144 kb
Host smart-e61e1649-0452-4a7b-84ca-6a234c10a218
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010426056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4010426056
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3042249407
Short name T91
Test name
Test status
Simulation time 199191030 ps
CPU time 8.54 seconds
Started Jun 25 04:47:56 PM PDT 24
Finished Jun 25 04:48:10 PM PDT 24
Peak memory 210676 kb
Host smart-62e79552-ce5f-41cf-87cb-d6881289f5c7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042249407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3042249407
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.881073932
Short name T406
Test name
Test status
Simulation time 4144922343 ps
CPU time 32.19 seconds
Started Jun 25 04:47:58 PM PDT 24
Finished Jun 25 04:48:35 PM PDT 24
Peak memory 211204 kb
Host smart-c5d06a23-6021-4644-8bb0-f2c2ca568980
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881073932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.881073932
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4021080702
Short name T434
Test name
Test status
Simulation time 4235782459 ps
CPU time 39.37 seconds
Started Jun 25 04:48:23 PM PDT 24
Finished Jun 25 04:49:12 PM PDT 24
Peak memory 212060 kb
Host smart-b6b1eaa0-cd48-4fe9-8882-e77253abdfce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021080702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4021080702
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.524644817
Short name T396
Test name
Test status
Simulation time 13540222280 ps
CPU time 20.18 seconds
Started Jun 25 04:47:56 PM PDT 24
Finished Jun 25 04:48:22 PM PDT 24
Peak memory 215900 kb
Host smart-dc13227c-01a2-48ea-abfd-be21534b3d2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524644817 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.524644817
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2450732037
Short name T75
Test name
Test status
Simulation time 2809572416 ps
CPU time 24.88 seconds
Started Jun 25 04:48:23 PM PDT 24
Finished Jun 25 04:48:56 PM PDT 24
Peak memory 211780 kb
Host smart-32df17b2-26b8-40fd-994d-9fd80fcaf3ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450732037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2450732037
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.586426427
Short name T418
Test name
Test status
Simulation time 174598952 ps
CPU time 8.25 seconds
Started Jun 25 04:48:14 PM PDT 24
Finished Jun 25 04:48:24 PM PDT 24
Peak memory 210456 kb
Host smart-c9e1da1f-cde6-448e-9138-b8688146ab79
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586426427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.586426427
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.12968180
Short name T382
Test name
Test status
Simulation time 612935320 ps
CPU time 8.05 seconds
Started Jun 25 04:48:23 PM PDT 24
Finished Jun 25 04:48:41 PM PDT 24
Peak memory 210436 kb
Host smart-5bfc66c3-1bed-4700-83e6-581bbf855bbd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12968180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.12968180
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.290503893
Short name T99
Test name
Test status
Simulation time 661309622 ps
CPU time 8.28 seconds
Started Jun 25 04:48:26 PM PDT 24
Finished Jun 25 04:48:46 PM PDT 24
Peak memory 211036 kb
Host smart-5ec8f79c-7a64-4f64-bf11-6fc1c75d44af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290503893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.290503893
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3268786085
Short name T377
Test name
Test status
Simulation time 2389806625 ps
CPU time 21 seconds
Started Jun 25 04:47:58 PM PDT 24
Finished Jun 25 04:48:23 PM PDT 24
Peak memory 218604 kb
Host smart-2c13174f-0fe5-47a9-8dc8-167863688d90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268786085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3268786085
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2099836290
Short name T119
Test name
Test status
Simulation time 22191840599 ps
CPU time 104.51 seconds
Started Jun 25 04:47:52 PM PDT 24
Finished Jun 25 04:49:41 PM PDT 24
Peak memory 213912 kb
Host smart-0e3e6bb7-1ad7-4c1d-9dd1-da0d6d2c10a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099836290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2099836290
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1728800545
Short name T362
Test name
Test status
Simulation time 12400397833 ps
CPU time 27.01 seconds
Started Jun 25 04:47:56 PM PDT 24
Finished Jun 25 04:48:28 PM PDT 24
Peak memory 218224 kb
Host smart-587cbd41-fa3f-4e62-91bd-ad78ad5f4772
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728800545 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1728800545
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.331557908
Short name T403
Test name
Test status
Simulation time 1322504524 ps
CPU time 10.64 seconds
Started Jun 25 04:47:55 PM PDT 24
Finished Jun 25 04:48:10 PM PDT 24
Peak memory 210964 kb
Host smart-e67b45a2-63a7-4a74-a6be-03824bd7b952
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331557908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.331557908
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.787855774
Short name T74
Test name
Test status
Simulation time 133761793218 ps
CPU time 124.74 seconds
Started Jun 25 04:48:21 PM PDT 24
Finished Jun 25 04:50:33 PM PDT 24
Peak memory 213772 kb
Host smart-ae8400d5-096d-4946-b648-e388272352c5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787855774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.787855774
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3747540768
Short name T420
Test name
Test status
Simulation time 788069090 ps
CPU time 12.48 seconds
Started Jun 25 04:47:54 PM PDT 24
Finished Jun 25 04:48:12 PM PDT 24
Peak memory 212548 kb
Host smart-1b259d08-7694-4399-8563-3f791dc534f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747540768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3747540768
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1105962926
Short name T394
Test name
Test status
Simulation time 1804890407 ps
CPU time 22.99 seconds
Started Jun 25 04:47:55 PM PDT 24
Finished Jun 25 04:48:22 PM PDT 24
Peak memory 217228 kb
Host smart-2a4481b9-fa98-49ba-8d07-0e8fa100af51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105962926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1105962926
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.460059478
Short name T411
Test name
Test status
Simulation time 277964362 ps
CPU time 83.57 seconds
Started Jun 25 04:47:53 PM PDT 24
Finished Jun 25 04:49:21 PM PDT 24
Peak memory 213632 kb
Host smart-b11d1ef6-01e9-4c3c-a7fe-091e8054416c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460059478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.460059478
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2005206158
Short name T378
Test name
Test status
Simulation time 1002032028 ps
CPU time 10.02 seconds
Started Jun 25 04:48:03 PM PDT 24
Finished Jun 25 04:48:15 PM PDT 24
Peak memory 217256 kb
Host smart-2f32b7a0-6b0b-4b4e-91b4-0c3406a4588a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005206158 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2005206158
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.595139459
Short name T401
Test name
Test status
Simulation time 167787063 ps
CPU time 8.57 seconds
Started Jun 25 04:48:02 PM PDT 24
Finished Jun 25 04:48:13 PM PDT 24
Peak memory 210592 kb
Host smart-1e24bbd7-739b-4a56-97dc-d17a92246760
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595139459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.595139459
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1565638949
Short name T93
Test name
Test status
Simulation time 42119937627 ps
CPU time 174.57 seconds
Started Jun 25 04:47:54 PM PDT 24
Finished Jun 25 04:50:54 PM PDT 24
Peak memory 215764 kb
Host smart-e0ed0bfb-fc30-4241-9e81-d1823869d688
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565638949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1565638949
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3708896314
Short name T97
Test name
Test status
Simulation time 1778913486 ps
CPU time 12.92 seconds
Started Jun 25 04:47:56 PM PDT 24
Finished Jun 25 04:48:14 PM PDT 24
Peak memory 211236 kb
Host smart-6f752821-24e7-4b0d-844d-923a8ba2ef56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708896314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3708896314
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2480697720
Short name T410
Test name
Test status
Simulation time 717322439 ps
CPU time 11.21 seconds
Started Jun 25 04:48:21 PM PDT 24
Finished Jun 25 04:48:39 PM PDT 24
Peak memory 217152 kb
Host smart-13d7ece3-621c-4227-814b-4abb14cc31d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480697720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2480697720
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1395720444
Short name T116
Test name
Test status
Simulation time 337851007 ps
CPU time 84.82 seconds
Started Jun 25 04:47:56 PM PDT 24
Finished Jun 25 04:49:30 PM PDT 24
Peak memory 213548 kb
Host smart-694345f7-f2f4-456d-99c9-7ec83ce42e05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395720444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1395720444
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1023834916
Short name T399
Test name
Test status
Simulation time 12897316514 ps
CPU time 24.9 seconds
Started Jun 25 04:48:14 PM PDT 24
Finished Jun 25 04:48:41 PM PDT 24
Peak memory 216712 kb
Host smart-79f63602-833b-43e9-8128-bda33eab1b89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023834916 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1023834916
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3171543696
Short name T79
Test name
Test status
Simulation time 17389844113 ps
CPU time 31.72 seconds
Started Jun 25 04:48:23 PM PDT 24
Finished Jun 25 04:49:05 PM PDT 24
Peak memory 212260 kb
Host smart-cda53117-1b07-46b2-8bf2-0abd5772332a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171543696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3171543696
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3592946407
Short name T92
Test name
Test status
Simulation time 705091311 ps
CPU time 38.51 seconds
Started Jun 25 04:47:56 PM PDT 24
Finished Jun 25 04:48:39 PM PDT 24
Peak memory 213672 kb
Host smart-595b0be9-43de-41a2-bd82-a0d7107ab04c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592946407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3592946407
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3170411985
Short name T415
Test name
Test status
Simulation time 552009681 ps
CPU time 8.33 seconds
Started Jun 25 04:47:54 PM PDT 24
Finished Jun 25 04:48:07 PM PDT 24
Peak memory 210896 kb
Host smart-9f387737-5516-4987-a91b-549be4ae870c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170411985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3170411985
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.442977368
Short name T409
Test name
Test status
Simulation time 6861092958 ps
CPU time 30.87 seconds
Started Jun 25 04:48:21 PM PDT 24
Finished Jun 25 04:48:59 PM PDT 24
Peak memory 218208 kb
Host smart-56dc5786-598d-44bb-a40d-d2546bda8cad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442977368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.442977368
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3919650007
Short name T424
Test name
Test status
Simulation time 4827357917 ps
CPU time 170.75 seconds
Started Jun 25 04:47:54 PM PDT 24
Finished Jun 25 04:50:50 PM PDT 24
Peak memory 214004 kb
Host smart-b1a1f7a5-c9b7-4cb3-86d3-80952ba0bc16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919650007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3919650007
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.154879988
Short name T385
Test name
Test status
Simulation time 2809897329 ps
CPU time 24.68 seconds
Started Jun 25 04:47:56 PM PDT 24
Finished Jun 25 04:48:25 PM PDT 24
Peak memory 217696 kb
Host smart-f7b1912c-bca1-4727-a888-58c829b085e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154879988 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.154879988
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3662677188
Short name T388
Test name
Test status
Simulation time 495901816 ps
CPU time 12.03 seconds
Started Jun 25 04:48:00 PM PDT 24
Finished Jun 25 04:48:15 PM PDT 24
Peak memory 210524 kb
Host smart-288f0722-bc79-4324-baae-021d86cf5627
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662677188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3662677188
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.269922060
Short name T461
Test name
Test status
Simulation time 27504753572 ps
CPU time 90.5 seconds
Started Jun 25 04:47:57 PM PDT 24
Finished Jun 25 04:49:33 PM PDT 24
Peak memory 215332 kb
Host smart-1956bf22-4d93-4471-9f82-583bc6c4e977
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269922060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.269922060
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3521392358
Short name T425
Test name
Test status
Simulation time 62718919557 ps
CPU time 28.28 seconds
Started Jun 25 04:48:25 PM PDT 24
Finished Jun 25 04:49:03 PM PDT 24
Peak memory 212404 kb
Host smart-d2fad567-1ac3-4893-964f-1722b4b690cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521392358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3521392358
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3454134210
Short name T460
Test name
Test status
Simulation time 174479743 ps
CPU time 10.95 seconds
Started Jun 25 04:48:21 PM PDT 24
Finished Jun 25 04:48:40 PM PDT 24
Peak memory 217104 kb
Host smart-27342793-68d3-43da-b4d0-4a557fbaea16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454134210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3454134210
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3871536493
Short name T374
Test name
Test status
Simulation time 12550554351 ps
CPU time 25.63 seconds
Started Jun 25 04:48:19 PM PDT 24
Finished Jun 25 04:48:47 PM PDT 24
Peak memory 217808 kb
Host smart-06e43b58-790f-41ec-8938-504449c7477f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871536493 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3871536493
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3465852458
Short name T390
Test name
Test status
Simulation time 16764580820 ps
CPU time 32.29 seconds
Started Jun 25 04:47:57 PM PDT 24
Finished Jun 25 04:48:34 PM PDT 24
Peak memory 211684 kb
Host smart-499446cc-8bdc-430d-b076-5a1d5cd02a95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465852458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3465852458
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1940629279
Short name T422
Test name
Test status
Simulation time 150707121153 ps
CPU time 206.69 seconds
Started Jun 25 04:48:21 PM PDT 24
Finished Jun 25 04:51:56 PM PDT 24
Peak memory 214944 kb
Host smart-73e5fca7-477a-40f0-8c68-6eb2c10ccc3c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940629279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1940629279
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1688710484
Short name T98
Test name
Test status
Simulation time 343545381 ps
CPU time 14.6 seconds
Started Jun 25 04:47:57 PM PDT 24
Finished Jun 25 04:48:16 PM PDT 24
Peak memory 212288 kb
Host smart-bc174537-c7be-4b48-a0cf-6fa1b7622ffd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688710484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1688710484
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1558106250
Short name T432
Test name
Test status
Simulation time 14416120495 ps
CPU time 32.03 seconds
Started Jun 25 04:48:18 PM PDT 24
Finished Jun 25 04:48:52 PM PDT 24
Peak memory 218848 kb
Host smart-749e1efd-0ef4-459f-aae6-a4647240ec3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558106250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1558106250
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.945639937
Short name T112
Test name
Test status
Simulation time 2018228559 ps
CPU time 163.3 seconds
Started Jun 25 04:48:01 PM PDT 24
Finished Jun 25 04:50:48 PM PDT 24
Peak memory 218828 kb
Host smart-c618dd96-4fae-48e6-9a7d-554ffa79df14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945639937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.945639937
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1469372751
Short name T243
Test name
Test status
Simulation time 35755649903 ps
CPU time 27.46 seconds
Started Jun 25 05:57:56 PM PDT 24
Finished Jun 25 05:58:25 PM PDT 24
Peak memory 217656 kb
Host smart-33dba453-ffd9-44c3-b5f1-2215dec8be19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469372751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1469372751
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2914688003
Short name T2
Test name
Test status
Simulation time 28947424617 ps
CPU time 483.2 seconds
Started Jun 25 05:57:56 PM PDT 24
Finished Jun 25 06:06:00 PM PDT 24
Peak memory 234236 kb
Host smart-baa735ea-964e-4220-a46f-d5a315e60893
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914688003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2914688003
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3447490012
Short name T240
Test name
Test status
Simulation time 26851325919 ps
CPU time 53.19 seconds
Started Jun 25 05:57:55 PM PDT 24
Finished Jun 25 05:58:49 PM PDT 24
Peak memory 219372 kb
Host smart-aa5b4cad-3714-4443-8e89-b5166fc69944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447490012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3447490012
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3448439395
Short name T296
Test name
Test status
Simulation time 8264619154 ps
CPU time 23.49 seconds
Started Jun 25 05:57:56 PM PDT 24
Finished Jun 25 05:58:20 PM PDT 24
Peak memory 212008 kb
Host smart-33f4f7d5-9f19-4099-b65b-566c6b08c5c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3448439395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3448439395
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.4186065975
Short name T23
Test name
Test status
Simulation time 17482418801 ps
CPU time 251.13 seconds
Started Jun 25 05:57:57 PM PDT 24
Finished Jun 25 06:02:10 PM PDT 24
Peak memory 236036 kb
Host smart-4db6c339-2320-4bb6-ac7e-0a4921969ba6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186065975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.4186065975
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3951629842
Short name T313
Test name
Test status
Simulation time 3073955091 ps
CPU time 41.63 seconds
Started Jun 25 05:57:46 PM PDT 24
Finished Jun 25 05:58:29 PM PDT 24
Peak memory 216388 kb
Host smart-f0d7f41c-ecee-4b4d-80a1-d3f7e6982120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951629842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3951629842
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.995966326
Short name T135
Test name
Test status
Simulation time 8422374336 ps
CPU time 36.39 seconds
Started Jun 25 05:57:53 PM PDT 24
Finished Jun 25 05:58:30 PM PDT 24
Peak memory 219260 kb
Host smart-68f255ab-8efc-469c-9ec3-469017375abf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995966326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.995966326
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.103227960
Short name T183
Test name
Test status
Simulation time 2825584102 ps
CPU time 25.83 seconds
Started Jun 25 05:58:12 PM PDT 24
Finished Jun 25 05:58:40 PM PDT 24
Peak memory 213360 kb
Host smart-69f34bc2-fe3a-4825-98c6-5f3cc3d8b3da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103227960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.103227960
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3251701156
Short name T105
Test name
Test status
Simulation time 38968659994 ps
CPU time 349 seconds
Started Jun 25 05:58:04 PM PDT 24
Finished Jun 25 06:03:54 PM PDT 24
Peak memory 217108 kb
Host smart-1b682b72-8425-4f52-ab01-086fb38701a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251701156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3251701156
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3810768241
Short name T282
Test name
Test status
Simulation time 15343140465 ps
CPU time 49.21 seconds
Started Jun 25 05:58:05 PM PDT 24
Finished Jun 25 05:58:55 PM PDT 24
Peak memory 219420 kb
Host smart-eb110acf-d7ce-4dc8-a4ac-b1951ff41f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810768241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3810768241
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.4170139053
Short name T208
Test name
Test status
Simulation time 14184892754 ps
CPU time 31.41 seconds
Started Jun 25 05:58:03 PM PDT 24
Finished Jun 25 05:58:36 PM PDT 24
Peak memory 219400 kb
Host smart-e8748e2f-99eb-42a8-8dc4-7c68fbec4a61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4170139053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.4170139053
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2055504554
Short name T29
Test name
Test status
Simulation time 1864155086 ps
CPU time 116.88 seconds
Started Jun 25 05:58:04 PM PDT 24
Finished Jun 25 06:00:02 PM PDT 24
Peak memory 236436 kb
Host smart-bfbe1141-78c2-421a-9ac6-1a5468329e1f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055504554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2055504554
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1134951835
Short name T148
Test name
Test status
Simulation time 689053051 ps
CPU time 20.28 seconds
Started Jun 25 05:57:55 PM PDT 24
Finished Jun 25 05:58:17 PM PDT 24
Peak memory 216376 kb
Host smart-20125c56-83d9-4d0c-b297-9b9c60608de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134951835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1134951835
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2139538824
Short name T134
Test name
Test status
Simulation time 26238008188 ps
CPU time 126.61 seconds
Started Jun 25 05:57:56 PM PDT 24
Finished Jun 25 06:00:03 PM PDT 24
Peak memory 220340 kb
Host smart-8fd8c265-11d3-4b77-a27e-f6137f0adc2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139538824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2139538824
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3381378489
Short name T231
Test name
Test status
Simulation time 16011888702 ps
CPU time 596.19 seconds
Started Jun 25 05:58:04 PM PDT 24
Finished Jun 25 06:08:01 PM PDT 24
Peak memory 227464 kb
Host smart-24c11e1e-7a70-43a4-918e-2154835e2a73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381378489 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.3381378489
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2405936900
Short name T252
Test name
Test status
Simulation time 30018991326 ps
CPU time 25.29 seconds
Started Jun 25 05:58:42 PM PDT 24
Finished Jun 25 05:59:08 PM PDT 24
Peak memory 217624 kb
Host smart-def8fecb-2add-469c-b454-73b3c6cb072b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405936900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2405936900
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2342628985
Short name T154
Test name
Test status
Simulation time 7845718749 ps
CPU time 63.44 seconds
Started Jun 25 05:58:45 PM PDT 24
Finished Jun 25 05:59:50 PM PDT 24
Peak memory 219312 kb
Host smart-074f76d6-cdc1-4d3e-a8a9-567497f514a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342628985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2342628985
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.195882051
Short name T176
Test name
Test status
Simulation time 6029243591 ps
CPU time 27.36 seconds
Started Jun 25 05:58:43 PM PDT 24
Finished Jun 25 05:59:11 PM PDT 24
Peak memory 219440 kb
Host smart-b377a81b-ccf0-4cda-a879-c1d2766adee6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=195882051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.195882051
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3076204983
Short name T173
Test name
Test status
Simulation time 14325409836 ps
CPU time 79.6 seconds
Started Jun 25 05:58:37 PM PDT 24
Finished Jun 25 05:59:57 PM PDT 24
Peak memory 217588 kb
Host smart-d1baeba2-2043-45af-b31f-d68d83cd3818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076204983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3076204983
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2990580411
Short name T323
Test name
Test status
Simulation time 4629583931 ps
CPU time 55.78 seconds
Started Jun 25 05:58:34 PM PDT 24
Finished Jun 25 05:59:30 PM PDT 24
Peak memory 218872 kb
Host smart-c41f5d3f-720c-4567-85fd-6325290ae9ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990580411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2990580411
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1588783987
Short name T283
Test name
Test status
Simulation time 14921829313 ps
CPU time 29.72 seconds
Started Jun 25 05:58:44 PM PDT 24
Finished Jun 25 05:59:14 PM PDT 24
Peak memory 213376 kb
Host smart-dac2f483-7d84-47ca-a695-6bed69f7784d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588783987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1588783987
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.488202311
Short name T171
Test name
Test status
Simulation time 26268345949 ps
CPU time 470.71 seconds
Started Jun 25 05:58:42 PM PDT 24
Finished Jun 25 06:06:34 PM PDT 24
Peak memory 234708 kb
Host smart-ea38a9ed-fd7a-46f2-834e-22a08c7a8750
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488202311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.488202311
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3245211396
Short name T59
Test name
Test status
Simulation time 2977607893 ps
CPU time 13.12 seconds
Started Jun 25 05:58:42 PM PDT 24
Finished Jun 25 05:58:56 PM PDT 24
Peak memory 218588 kb
Host smart-6ef20b84-8567-4dc6-8782-e5c870e26ef6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3245211396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3245211396
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.537915072
Short name T156
Test name
Test status
Simulation time 16426916876 ps
CPU time 44.6 seconds
Started Jun 25 05:58:44 PM PDT 24
Finished Jun 25 05:59:29 PM PDT 24
Peak memory 217084 kb
Host smart-2ed17715-19ac-4a94-b723-548670746610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537915072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.537915072
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.755343830
Short name T175
Test name
Test status
Simulation time 12717312365 ps
CPU time 122.04 seconds
Started Jun 25 05:58:42 PM PDT 24
Finished Jun 25 06:00:44 PM PDT 24
Peak memory 219428 kb
Host smart-02f6d201-3c13-4f8c-bdcd-dc091c9dbb3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755343830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.755343830
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.519898796
Short name T276
Test name
Test status
Simulation time 74334064568 ps
CPU time 418.05 seconds
Started Jun 25 05:58:42 PM PDT 24
Finished Jun 25 06:05:41 PM PDT 24
Peak memory 238060 kb
Host smart-b70aaa0f-2cb6-4ab0-b9f2-4f855ded44f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519898796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.519898796
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1603507201
Short name T132
Test name
Test status
Simulation time 13358408006 ps
CPU time 58.97 seconds
Started Jun 25 05:58:50 PM PDT 24
Finished Jun 25 05:59:50 PM PDT 24
Peak memory 219376 kb
Host smart-90faa1ed-345b-406e-ba51-4b39e1ed3cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603507201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1603507201
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3639170612
Short name T36
Test name
Test status
Simulation time 2101225043 ps
CPU time 13.74 seconds
Started Jun 25 05:58:43 PM PDT 24
Finished Jun 25 05:58:58 PM PDT 24
Peak memory 219320 kb
Host smart-a56bf86d-4f62-44c6-8b39-06b6ca3c41bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3639170612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3639170612
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1053670707
Short name T14
Test name
Test status
Simulation time 6568754423 ps
CPU time 57.27 seconds
Started Jun 25 05:58:43 PM PDT 24
Finished Jun 25 05:59:42 PM PDT 24
Peak memory 216964 kb
Host smart-8c1827e6-f1c6-4751-b547-e3c6f514d50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053670707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1053670707
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1433880958
Short name T214
Test name
Test status
Simulation time 14723932768 ps
CPU time 38.96 seconds
Started Jun 25 05:58:42 PM PDT 24
Finished Jun 25 05:59:22 PM PDT 24
Peak memory 214876 kb
Host smart-428ed527-0b22-49f7-92e4-7eef805f7ab7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433880958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1433880958
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.817368604
Short name T162
Test name
Test status
Simulation time 688396386 ps
CPU time 8.33 seconds
Started Jun 25 05:58:50 PM PDT 24
Finished Jun 25 05:59:00 PM PDT 24
Peak memory 217124 kb
Host smart-94bc7f38-e36c-4a9a-84c5-d78824dca6eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817368604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.817368604
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2942509085
Short name T50
Test name
Test status
Simulation time 42701755970 ps
CPU time 623.79 seconds
Started Jun 25 05:58:49 PM PDT 24
Finished Jun 25 06:09:13 PM PDT 24
Peak memory 228588 kb
Host smart-8b73a3c8-50c1-485c-869c-e0f79ebefb01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942509085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2942509085
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1122532717
Short name T180
Test name
Test status
Simulation time 11793943993 ps
CPU time 54.29 seconds
Started Jun 25 05:58:50 PM PDT 24
Finished Jun 25 05:59:46 PM PDT 24
Peak memory 219440 kb
Host smart-c626d79e-ccb6-42df-aa32-e42e115df7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122532717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1122532717
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3178463319
Short name T123
Test name
Test status
Simulation time 15374861441 ps
CPU time 33.35 seconds
Started Jun 25 05:58:50 PM PDT 24
Finished Jun 25 05:59:25 PM PDT 24
Peak memory 211960 kb
Host smart-8d6d147d-314c-4581-89d0-4c184e979251
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3178463319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3178463319
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3263005232
Short name T308
Test name
Test status
Simulation time 1574257997 ps
CPU time 20.07 seconds
Started Jun 25 05:58:50 PM PDT 24
Finished Jun 25 05:59:12 PM PDT 24
Peak memory 215952 kb
Host smart-409b0cde-dfe2-4691-b6e2-e7b692f50375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263005232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3263005232
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3535538126
Short name T294
Test name
Test status
Simulation time 29035773200 ps
CPU time 176.15 seconds
Started Jun 25 05:58:50 PM PDT 24
Finished Jun 25 06:01:48 PM PDT 24
Peak memory 220132 kb
Host smart-8a53aec3-ceac-4961-baf2-580694d2aa28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535538126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3535538126
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2275715646
Short name T207
Test name
Test status
Simulation time 53438389036 ps
CPU time 32.94 seconds
Started Jun 25 05:59:02 PM PDT 24
Finished Jun 25 05:59:35 PM PDT 24
Peak memory 217620 kb
Host smart-8538240e-bf41-4923-aaa3-c5c3eef4e2d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275715646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2275715646
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1325423399
Short name T321
Test name
Test status
Simulation time 7891414801 ps
CPU time 262.93 seconds
Started Jun 25 05:59:02 PM PDT 24
Finished Jun 25 06:03:25 PM PDT 24
Peak memory 236808 kb
Host smart-ce2b5743-327d-4341-a810-fc2ceec5961c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325423399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1325423399
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2803667291
Short name T277
Test name
Test status
Simulation time 70974299634 ps
CPU time 45.23 seconds
Started Jun 25 05:58:59 PM PDT 24
Finished Jun 25 05:59:45 PM PDT 24
Peak memory 219252 kb
Host smart-9022935a-3b5d-4a60-95bb-55d001bad382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803667291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2803667291
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4062982576
Short name T35
Test name
Test status
Simulation time 8224352922 ps
CPU time 32.76 seconds
Started Jun 25 05:59:00 PM PDT 24
Finished Jun 25 05:59:33 PM PDT 24
Peak memory 219412 kb
Host smart-c4c15267-75d1-4665-b2af-408b3c63d8f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4062982576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4062982576
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1017999554
Short name T310
Test name
Test status
Simulation time 2359290196 ps
CPU time 38.35 seconds
Started Jun 25 05:58:50 PM PDT 24
Finished Jun 25 05:59:30 PM PDT 24
Peak memory 218048 kb
Host smart-5efd645d-a0bd-4c92-b9c2-e102d1482710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017999554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1017999554
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1424109786
Short name T151
Test name
Test status
Simulation time 1097879110 ps
CPU time 65.58 seconds
Started Jun 25 05:58:59 PM PDT 24
Finished Jun 25 06:00:05 PM PDT 24
Peak memory 221596 kb
Host smart-46b97c2f-4765-4fbd-ace6-7fa002131fc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424109786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1424109786
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.135935896
Short name T51
Test name
Test status
Simulation time 22775024186 ps
CPU time 845.96 seconds
Started Jun 25 05:58:58 PM PDT 24
Finished Jun 25 06:13:04 PM PDT 24
Peak memory 230532 kb
Host smart-39e675b0-9f32-4bf8-8f99-0180c762f078
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135935896 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.135935896
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3141632855
Short name T152
Test name
Test status
Simulation time 171101957 ps
CPU time 8.21 seconds
Started Jun 25 05:59:10 PM PDT 24
Finished Jun 25 05:59:19 PM PDT 24
Peak memory 217108 kb
Host smart-874487b9-ec60-4d7a-8333-2f372cec5641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141632855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3141632855
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3418623690
Short name T255
Test name
Test status
Simulation time 123162214596 ps
CPU time 431.97 seconds
Started Jun 25 05:58:58 PM PDT 24
Finished Jun 25 06:06:11 PM PDT 24
Peak memory 234160 kb
Host smart-0c0cb1d2-156c-4f9f-a948-a0c8895b16f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418623690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3418623690
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2751961256
Short name T228
Test name
Test status
Simulation time 8216088453 ps
CPU time 21.25 seconds
Started Jun 25 05:59:01 PM PDT 24
Finished Jun 25 05:59:23 PM PDT 24
Peak memory 219416 kb
Host smart-ca774515-5c3b-4c90-8070-31701af43160
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2751961256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2751961256
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.812645485
Short name T193
Test name
Test status
Simulation time 5028126008 ps
CPU time 55.34 seconds
Started Jun 25 05:58:59 PM PDT 24
Finished Jun 25 05:59:55 PM PDT 24
Peak memory 216476 kb
Host smart-f31fde78-7525-448d-bcdc-aae776f0733b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812645485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.812645485
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.396796667
Short name T124
Test name
Test status
Simulation time 32088747189 ps
CPU time 59.42 seconds
Started Jun 25 05:58:59 PM PDT 24
Finished Jun 25 05:59:59 PM PDT 24
Peak memory 216856 kb
Host smart-2eb305c6-0344-4df5-bf10-670bfd913bfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396796667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.396796667
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3576703044
Short name T184
Test name
Test status
Simulation time 167384430 ps
CPU time 8.32 seconds
Started Jun 25 05:59:09 PM PDT 24
Finished Jun 25 05:59:18 PM PDT 24
Peak memory 217236 kb
Host smart-7085420f-6766-4595-b709-ee8ae0e04edb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576703044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3576703044
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2219036610
Short name T40
Test name
Test status
Simulation time 45352672566 ps
CPU time 457.23 seconds
Started Jun 25 05:59:10 PM PDT 24
Finished Jun 25 06:06:48 PM PDT 24
Peak memory 234824 kb
Host smart-3c10e7c9-2559-4225-91a9-ea113ef1d965
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219036610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2219036610
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1837122553
Short name T159
Test name
Test status
Simulation time 30842263464 ps
CPU time 62.01 seconds
Started Jun 25 05:59:09 PM PDT 24
Finished Jun 25 06:00:12 PM PDT 24
Peak memory 219420 kb
Host smart-671d9b87-816a-4860-9b04-c495d1c4838a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837122553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1837122553
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.815142387
Short name T327
Test name
Test status
Simulation time 15708694483 ps
CPU time 32.49 seconds
Started Jun 25 05:59:09 PM PDT 24
Finished Jun 25 05:59:42 PM PDT 24
Peak memory 212080 kb
Host smart-ce1ef058-9f44-4d7f-bf1d-9b6c2d066a80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=815142387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.815142387
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3053872414
Short name T138
Test name
Test status
Simulation time 19625119323 ps
CPU time 48.94 seconds
Started Jun 25 05:59:08 PM PDT 24
Finished Jun 25 05:59:58 PM PDT 24
Peak memory 216920 kb
Host smart-0295122c-52e8-45d7-a8cb-9e6a0042553b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053872414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3053872414
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1934223274
Short name T192
Test name
Test status
Simulation time 11166107406 ps
CPU time 143.88 seconds
Started Jun 25 05:59:08 PM PDT 24
Finished Jun 25 06:01:33 PM PDT 24
Peak memory 220788 kb
Host smart-3e97906c-c3b6-459f-8935-7ff19491078a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934223274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1934223274
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1329860622
Short name T261
Test name
Test status
Simulation time 4076259131 ps
CPU time 29.49 seconds
Started Jun 25 05:59:19 PM PDT 24
Finished Jun 25 05:59:50 PM PDT 24
Peak memory 213264 kb
Host smart-e4ad0126-e45c-49e3-bd45-8d1bee68c77e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329860622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1329860622
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2508268622
Short name T303
Test name
Test status
Simulation time 55658170491 ps
CPU time 441.55 seconds
Started Jun 25 05:59:10 PM PDT 24
Finished Jun 25 06:06:33 PM PDT 24
Peak memory 233852 kb
Host smart-57dafec2-835b-496d-a355-c98df96a7be6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508268622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2508268622
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3440567741
Short name T140
Test name
Test status
Simulation time 94622707596 ps
CPU time 70.7 seconds
Started Jun 25 05:59:19 PM PDT 24
Finished Jun 25 06:00:31 PM PDT 24
Peak memory 219360 kb
Host smart-2e684418-ad6e-49b8-9d71-34192bb2c946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440567741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3440567741
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1122510563
Short name T122
Test name
Test status
Simulation time 6556693676 ps
CPU time 20.14 seconds
Started Jun 25 05:59:09 PM PDT 24
Finished Jun 25 05:59:30 PM PDT 24
Peak memory 212048 kb
Host smart-52fce6ff-cc68-4b0f-8b29-2235c186f7f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1122510563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1122510563
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2608990944
Short name T226
Test name
Test status
Simulation time 32129521067 ps
CPU time 64.71 seconds
Started Jun 25 05:59:09 PM PDT 24
Finished Jun 25 06:00:15 PM PDT 24
Peak memory 217276 kb
Host smart-d02fb2cd-71b4-49a2-aa2d-050fcb938a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608990944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2608990944
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2142648897
Short name T287
Test name
Test status
Simulation time 746906459 ps
CPU time 48.49 seconds
Started Jun 25 05:59:09 PM PDT 24
Finished Jun 25 05:59:58 PM PDT 24
Peak memory 219344 kb
Host smart-2fbeb4b5-9db8-430a-adab-9b193494f5d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142648897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2142648897
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2352727868
Short name T358
Test name
Test status
Simulation time 4989740416 ps
CPU time 15.8 seconds
Started Jun 25 05:59:17 PM PDT 24
Finished Jun 25 05:59:34 PM PDT 24
Peak memory 217536 kb
Host smart-efecf12a-0524-441d-a851-608f14172685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352727868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2352727868
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2524067121
Short name T41
Test name
Test status
Simulation time 289305547194 ps
CPU time 491.46 seconds
Started Jun 25 05:59:20 PM PDT 24
Finished Jun 25 06:07:33 PM PDT 24
Peak memory 219600 kb
Host smart-d12ddf48-116b-40f4-9368-2f6c2d1baa72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524067121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2524067121
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.4103277074
Short name T149
Test name
Test status
Simulation time 10836648017 ps
CPU time 50.42 seconds
Started Jun 25 05:59:17 PM PDT 24
Finished Jun 25 06:00:09 PM PDT 24
Peak memory 219420 kb
Host smart-ffba863f-d9c5-43e2-935b-dc50a50ead3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103277074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.4103277074
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3407089532
Short name T7
Test name
Test status
Simulation time 6757167056 ps
CPU time 28.52 seconds
Started Jun 25 05:59:17 PM PDT 24
Finished Jun 25 05:59:47 PM PDT 24
Peak memory 212320 kb
Host smart-bc67ed6a-9240-47f0-9bf9-c6c0c971d48f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3407089532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3407089532
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.4268338570
Short name T223
Test name
Test status
Simulation time 1359369642 ps
CPU time 19.06 seconds
Started Jun 25 05:59:20 PM PDT 24
Finished Jun 25 05:59:40 PM PDT 24
Peak memory 216276 kb
Host smart-75111a98-cbe9-43ac-b60d-b047379bc6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268338570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.4268338570
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1541297590
Short name T350
Test name
Test status
Simulation time 13372964191 ps
CPU time 54.78 seconds
Started Jun 25 05:59:17 PM PDT 24
Finished Jun 25 06:00:13 PM PDT 24
Peak memory 219448 kb
Host smart-c714a16f-19c3-4c72-a7e7-8aed93ad6e6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541297590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1541297590
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.937206133
Short name T70
Test name
Test status
Simulation time 5751660328 ps
CPU time 25.53 seconds
Started Jun 25 05:59:19 PM PDT 24
Finished Jun 25 05:59:46 PM PDT 24
Peak memory 217532 kb
Host smart-2a9093dd-2a50-4d5e-ae95-cbbf8b718d95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937206133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.937206133
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2078899578
Short name T147
Test name
Test status
Simulation time 3081083370 ps
CPU time 227.35 seconds
Started Jun 25 05:59:17 PM PDT 24
Finished Jun 25 06:03:05 PM PDT 24
Peak memory 237060 kb
Host smart-923f6749-fe90-4d5b-9ee9-42832bd326e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078899578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2078899578
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2150247708
Short name T270
Test name
Test status
Simulation time 2023948003 ps
CPU time 31.66 seconds
Started Jun 25 05:59:18 PM PDT 24
Finished Jun 25 05:59:51 PM PDT 24
Peak memory 219340 kb
Host smart-7e394116-8853-453c-8c34-6edab93f6ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150247708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2150247708
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4227746544
Short name T275
Test name
Test status
Simulation time 1813217083 ps
CPU time 20.42 seconds
Started Jun 25 05:59:17 PM PDT 24
Finished Jun 25 05:59:39 PM PDT 24
Peak memory 219332 kb
Host smart-50ba75f6-0fad-4176-8d10-03cc7a99345e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4227746544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4227746544
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3135984205
Short name T281
Test name
Test status
Simulation time 347495922 ps
CPU time 19.78 seconds
Started Jun 25 05:59:19 PM PDT 24
Finished Jun 25 05:59:40 PM PDT 24
Peak memory 216088 kb
Host smart-4774ffc5-5055-4c77-bb76-ae1cd9936471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135984205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3135984205
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1398466383
Short name T341
Test name
Test status
Simulation time 17123835263 ps
CPU time 170.6 seconds
Started Jun 25 05:59:17 PM PDT 24
Finished Jun 25 06:02:09 PM PDT 24
Peak memory 219444 kb
Host smart-ec37e78a-1c84-40a2-a491-3383acbfd522
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398466383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1398466383
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.580736381
Short name T190
Test name
Test status
Simulation time 1691136689 ps
CPU time 18.23 seconds
Started Jun 25 05:58:10 PM PDT 24
Finished Jun 25 05:58:29 PM PDT 24
Peak memory 217188 kb
Host smart-0a831d7d-dd50-4a7d-be27-ca4d4267abbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580736381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.580736381
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2237499552
Short name T200
Test name
Test status
Simulation time 96032215182 ps
CPU time 377.09 seconds
Started Jun 25 05:58:05 PM PDT 24
Finished Jun 25 06:04:23 PM PDT 24
Peak memory 216936 kb
Host smart-02ab6152-678a-4c0d-b31a-d3c6884fb82b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237499552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2237499552
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2777865923
Short name T196
Test name
Test status
Simulation time 6738017632 ps
CPU time 29.64 seconds
Started Jun 25 05:58:12 PM PDT 24
Finished Jun 25 05:58:43 PM PDT 24
Peak memory 219392 kb
Host smart-2db0dffa-0f17-4f0f-a461-487c469075e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777865923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2777865923
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1186927650
Short name T230
Test name
Test status
Simulation time 49837386010 ps
CPU time 34.55 seconds
Started Jun 25 05:58:04 PM PDT 24
Finished Jun 25 05:58:39 PM PDT 24
Peak memory 219412 kb
Host smart-361d3c85-647a-4f7c-81a9-471be76b1b0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1186927650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1186927650
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.976872933
Short name T28
Test name
Test status
Simulation time 3006532124 ps
CPU time 133.53 seconds
Started Jun 25 05:58:05 PM PDT 24
Finished Jun 25 06:00:20 PM PDT 24
Peak memory 238300 kb
Host smart-7f0cd989-f525-4271-84cc-60589cfcca0e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976872933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.976872933
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.4099002694
Short name T345
Test name
Test status
Simulation time 11625407299 ps
CPU time 37.68 seconds
Started Jun 25 05:58:04 PM PDT 24
Finished Jun 25 05:58:43 PM PDT 24
Peak memory 216864 kb
Host smart-7f5b31c0-fbea-40e0-815a-1dc278fe985b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099002694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.4099002694
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3062987345
Short name T285
Test name
Test status
Simulation time 1213985567 ps
CPU time 25.34 seconds
Started Jun 25 05:58:04 PM PDT 24
Finished Jun 25 05:58:30 PM PDT 24
Peak memory 214796 kb
Host smart-3578b162-4075-43cd-a467-3e0c45f06791
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062987345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3062987345
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2714406719
Short name T353
Test name
Test status
Simulation time 6082951139 ps
CPU time 24.23 seconds
Started Jun 25 05:59:25 PM PDT 24
Finished Jun 25 05:59:50 PM PDT 24
Peak memory 217488 kb
Host smart-37bafd46-b822-4cc0-918e-eea042662675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714406719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2714406719
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.815447613
Short name T145
Test name
Test status
Simulation time 134407489084 ps
CPU time 454.4 seconds
Started Jun 25 05:59:26 PM PDT 24
Finished Jun 25 06:07:02 PM PDT 24
Peak memory 239808 kb
Host smart-79b5b0f5-d6ab-4e82-8aa1-04f006e2d21e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815447613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.815447613
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2975863536
Short name T251
Test name
Test status
Simulation time 788292176 ps
CPU time 19.36 seconds
Started Jun 25 05:59:26 PM PDT 24
Finished Jun 25 05:59:46 PM PDT 24
Peak memory 219352 kb
Host smart-fcd77621-9f1b-4ebd-bf76-75419c10eef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975863536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2975863536
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2940036845
Short name T284
Test name
Test status
Simulation time 11136014940 ps
CPU time 25.55 seconds
Started Jun 25 05:59:28 PM PDT 24
Finished Jun 25 05:59:54 PM PDT 24
Peak memory 212052 kb
Host smart-f006adab-f14d-4df5-b733-001aeeac699c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2940036845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2940036845
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1873381085
Short name T311
Test name
Test status
Simulation time 16380361730 ps
CPU time 44.29 seconds
Started Jun 25 05:59:17 PM PDT 24
Finished Jun 25 06:00:03 PM PDT 24
Peak memory 216124 kb
Host smart-bf093baa-8ebc-4476-8e5b-dc927095b99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873381085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1873381085
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1792566480
Short name T143
Test name
Test status
Simulation time 2123395409 ps
CPU time 32.53 seconds
Started Jun 25 05:59:26 PM PDT 24
Finished Jun 25 06:00:00 PM PDT 24
Peak memory 216380 kb
Host smart-820452f2-2297-4304-abbc-74f7932c5f5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792566480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1792566480
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3469044508
Short name T357
Test name
Test status
Simulation time 2354494233 ps
CPU time 8.43 seconds
Started Jun 25 05:59:26 PM PDT 24
Finished Jun 25 05:59:36 PM PDT 24
Peak memory 217184 kb
Host smart-7e5ae5e9-b818-45b7-a022-f4677cdc7008
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469044508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3469044508
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1082772467
Short name T332
Test name
Test status
Simulation time 210673685475 ps
CPU time 473.69 seconds
Started Jun 25 05:59:28 PM PDT 24
Finished Jun 25 06:07:23 PM PDT 24
Peak memory 238048 kb
Host smart-ed1e97a0-c98c-499a-a660-ac5d9d988259
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082772467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1082772467
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2255236466
Short name T354
Test name
Test status
Simulation time 346487571 ps
CPU time 20.02 seconds
Started Jun 25 05:59:26 PM PDT 24
Finished Jun 25 05:59:47 PM PDT 24
Peak memory 219328 kb
Host smart-75cf240e-1018-4673-bca6-f6c78e5cfbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255236466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2255236466
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3795557015
Short name T274
Test name
Test status
Simulation time 179696612 ps
CPU time 10.56 seconds
Started Jun 25 05:59:27 PM PDT 24
Finished Jun 25 05:59:39 PM PDT 24
Peak memory 219376 kb
Host smart-6bebf9ab-1cef-4029-ac62-6339df8827f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3795557015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3795557015
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2709041016
Short name T130
Test name
Test status
Simulation time 3788283008 ps
CPU time 41.95 seconds
Started Jun 25 05:59:28 PM PDT 24
Finished Jun 25 06:00:11 PM PDT 24
Peak memory 216292 kb
Host smart-8fa0d83e-445c-4b42-afb1-003b3a67079f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709041016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2709041016
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.153898675
Short name T215
Test name
Test status
Simulation time 21077058463 ps
CPU time 85.82 seconds
Started Jun 25 05:59:28 PM PDT 24
Finished Jun 25 06:00:55 PM PDT 24
Peak memory 219396 kb
Host smart-3b050e58-556a-439e-85c4-92414dd4f6c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153898675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.153898675
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.554056034
Short name T187
Test name
Test status
Simulation time 9690110270 ps
CPU time 24.19 seconds
Started Jun 25 05:59:27 PM PDT 24
Finished Jun 25 05:59:52 PM PDT 24
Peak memory 213388 kb
Host smart-b7ff8ed7-acb9-470e-b05c-9acbb26c0692
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554056034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.554056034
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3660117055
Short name T328
Test name
Test status
Simulation time 86043884225 ps
CPU time 348.3 seconds
Started Jun 25 05:59:28 PM PDT 24
Finished Jun 25 06:05:18 PM PDT 24
Peak memory 235580 kb
Host smart-47bc45be-dde7-4d37-891b-f40d43081bf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660117055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3660117055
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3150553627
Short name T31
Test name
Test status
Simulation time 2746168521 ps
CPU time 19.56 seconds
Started Jun 25 05:59:26 PM PDT 24
Finished Jun 25 05:59:47 PM PDT 24
Peak memory 219412 kb
Host smart-1d5a54ce-1ad1-490e-8cab-7d6a50c6dc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150553627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3150553627
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.672690341
Short name T4
Test name
Test status
Simulation time 3555769199 ps
CPU time 30.04 seconds
Started Jun 25 05:59:25 PM PDT 24
Finished Jun 25 05:59:56 PM PDT 24
Peak memory 219424 kb
Host smart-b68e3546-19ee-40a4-bb31-674ae1cd7202
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=672690341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.672690341
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2124098300
Short name T167
Test name
Test status
Simulation time 8663712693 ps
CPU time 47.59 seconds
Started Jun 25 05:59:25 PM PDT 24
Finished Jun 25 06:00:14 PM PDT 24
Peak memory 219360 kb
Host smart-c8063425-25a9-42ee-8769-0a424ba1adc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124098300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2124098300
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1921960528
Short name T205
Test name
Test status
Simulation time 2428535748 ps
CPU time 23.19 seconds
Started Jun 25 05:59:35 PM PDT 24
Finished Jun 25 06:00:01 PM PDT 24
Peak memory 213356 kb
Host smart-3884cf8e-16bd-439f-86c1-8d11c60c4e1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921960528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1921960528
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3157493011
Short name T19
Test name
Test status
Simulation time 114012541202 ps
CPU time 390.62 seconds
Started Jun 25 05:59:28 PM PDT 24
Finished Jun 25 06:06:00 PM PDT 24
Peak memory 239404 kb
Host smart-32c81508-a0fe-4621-ab6b-87fd5a5fe90b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157493011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3157493011
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3817952964
Short name T335
Test name
Test status
Simulation time 3443459453 ps
CPU time 39.7 seconds
Started Jun 25 05:59:26 PM PDT 24
Finished Jun 25 06:00:07 PM PDT 24
Peak memory 219424 kb
Host smart-ee73c863-cb63-488a-b0e5-743fc492e67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817952964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3817952964
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3151754490
Short name T221
Test name
Test status
Simulation time 1595452309 ps
CPU time 19.47 seconds
Started Jun 25 05:59:25 PM PDT 24
Finished Jun 25 05:59:45 PM PDT 24
Peak memory 219332 kb
Host smart-9a7e83ab-1459-4126-a71e-6b0ae211c9a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3151754490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3151754490
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.3097063082
Short name T107
Test name
Test status
Simulation time 359102457 ps
CPU time 20.04 seconds
Started Jun 25 05:59:26 PM PDT 24
Finished Jun 25 05:59:48 PM PDT 24
Peak memory 216268 kb
Host smart-044b8c11-6189-43f1-9631-8ca473053e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097063082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.3097063082
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3876662043
Short name T299
Test name
Test status
Simulation time 11673140881 ps
CPU time 107.2 seconds
Started Jun 25 05:59:25 PM PDT 24
Finished Jun 25 06:01:13 PM PDT 24
Peak memory 217768 kb
Host smart-1f33dabb-75e1-4309-b1b3-b6153c31d0a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876662043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3876662043
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.802300293
Short name T286
Test name
Test status
Simulation time 10712772908 ps
CPU time 15.88 seconds
Started Jun 25 05:59:34 PM PDT 24
Finished Jun 25 05:59:52 PM PDT 24
Peak memory 217508 kb
Host smart-9f69b297-54d6-467d-bbaa-fbe933964b6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802300293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.802300293
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.4270699222
Short name T219
Test name
Test status
Simulation time 207857399635 ps
CPU time 577.72 seconds
Started Jun 25 05:59:35 PM PDT 24
Finished Jun 25 06:09:17 PM PDT 24
Peak memory 219588 kb
Host smart-c9b8cbb1-99de-4be2-848a-1573cb9c7832
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270699222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.4270699222
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4274386810
Short name T319
Test name
Test status
Simulation time 2392418729 ps
CPU time 27.68 seconds
Started Jun 25 05:59:39 PM PDT 24
Finished Jun 25 06:00:16 PM PDT 24
Peak memory 219388 kb
Host smart-152e6c66-157d-4821-8492-c311becdc7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274386810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4274386810
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2230018078
Short name T234
Test name
Test status
Simulation time 6603164637 ps
CPU time 28.64 seconds
Started Jun 25 05:59:35 PM PDT 24
Finished Jun 25 06:00:06 PM PDT 24
Peak memory 217504 kb
Host smart-77f5f0b4-6f21-4852-8a82-e15099bf33d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230018078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2230018078
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.566752638
Short name T121
Test name
Test status
Simulation time 7437597083 ps
CPU time 61.5 seconds
Started Jun 25 05:59:35 PM PDT 24
Finished Jun 25 06:00:40 PM PDT 24
Peak memory 218084 kb
Host smart-fe581d67-7188-4763-9882-b80666d7f5d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566752638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.566752638
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.4139334769
Short name T56
Test name
Test status
Simulation time 32338516872 ps
CPU time 2947.41 seconds
Started Jun 25 05:59:34 PM PDT 24
Finished Jun 25 06:48:45 PM PDT 24
Peak memory 231020 kb
Host smart-838a966f-4527-480b-ac01-aac66448edbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139334769 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.4139334769
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2028454413
Short name T161
Test name
Test status
Simulation time 2736787513 ps
CPU time 22.35 seconds
Started Jun 25 05:59:36 PM PDT 24
Finished Jun 25 06:00:04 PM PDT 24
Peak memory 217220 kb
Host smart-8b2f227b-9282-47ba-aa4a-9503b26066f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028454413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2028454413
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3690067333
Short name T43
Test name
Test status
Simulation time 68624210651 ps
CPU time 719.52 seconds
Started Jun 25 05:59:37 PM PDT 24
Finished Jun 25 06:11:43 PM PDT 24
Peak memory 224600 kb
Host smart-6fd6c825-c9c2-4786-b280-fad64f3621c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690067333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3690067333
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1677379159
Short name T32
Test name
Test status
Simulation time 1436590443 ps
CPU time 19.39 seconds
Started Jun 25 05:59:36 PM PDT 24
Finished Jun 25 06:00:02 PM PDT 24
Peak memory 219344 kb
Host smart-8ac87c70-1bbf-4c23-b33d-f08170abd2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677379159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1677379159
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3470716072
Short name T178
Test name
Test status
Simulation time 8204871894 ps
CPU time 30.72 seconds
Started Jun 25 05:59:36 PM PDT 24
Finished Jun 25 06:00:12 PM PDT 24
Peak memory 219432 kb
Host smart-c6f3e70d-f342-4037-99b5-0ca870b30f3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3470716072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3470716072
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1071919754
Short name T259
Test name
Test status
Simulation time 2731159194 ps
CPU time 38.73 seconds
Started Jun 25 05:59:36 PM PDT 24
Finished Jun 25 06:00:20 PM PDT 24
Peak memory 216264 kb
Host smart-b07caf3d-c0f0-4de8-99af-bc9349762e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071919754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1071919754
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.954570167
Short name T5
Test name
Test status
Simulation time 10608151830 ps
CPU time 34.05 seconds
Started Jun 25 05:59:37 PM PDT 24
Finished Jun 25 06:00:17 PM PDT 24
Peak memory 214820 kb
Host smart-8ff4f038-93b5-4886-8ad0-75626728a68f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954570167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.954570167
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3938256560
Short name T333
Test name
Test status
Simulation time 2924673956 ps
CPU time 19.08 seconds
Started Jun 25 05:59:41 PM PDT 24
Finished Jun 25 06:00:10 PM PDT 24
Peak memory 217376 kb
Host smart-a80d7a68-3e28-4bec-8ff9-209003061bd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938256560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3938256560
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3226795287
Short name T297
Test name
Test status
Simulation time 61903074732 ps
CPU time 567.97 seconds
Started Jun 25 05:59:45 PM PDT 24
Finished Jun 25 06:09:23 PM PDT 24
Peak memory 219560 kb
Host smart-a870e0d4-7832-45cf-8b0c-639841d1857b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226795287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3226795287
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1562574134
Short name T34
Test name
Test status
Simulation time 1376266957 ps
CPU time 19.28 seconds
Started Jun 25 05:59:41 PM PDT 24
Finished Jun 25 06:00:10 PM PDT 24
Peak memory 219332 kb
Host smart-133afe44-7191-45a7-990a-cc5077629304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562574134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1562574134
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2433741461
Short name T238
Test name
Test status
Simulation time 335160551 ps
CPU time 12.01 seconds
Started Jun 25 05:59:39 PM PDT 24
Finished Jun 25 06:00:00 PM PDT 24
Peak memory 219344 kb
Host smart-700bf3a5-c950-4350-aceb-4702bcf01960
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2433741461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2433741461
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3312870729
Short name T18
Test name
Test status
Simulation time 8253173790 ps
CPU time 37.72 seconds
Started Jun 25 05:59:35 PM PDT 24
Finished Jun 25 06:00:16 PM PDT 24
Peak memory 217532 kb
Host smart-00c3f3db-6049-41c5-90a2-1a18e3a86bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312870729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3312870729
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1283733320
Short name T235
Test name
Test status
Simulation time 16458855506 ps
CPU time 153.53 seconds
Started Jun 25 05:59:35 PM PDT 24
Finished Jun 25 06:02:12 PM PDT 24
Peak memory 220536 kb
Host smart-5496fc49-caef-460a-ad2b-d4357d000637
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283733320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1283733320
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1704134684
Short name T108
Test name
Test status
Simulation time 233571805818 ps
CPU time 2444.54 seconds
Started Jun 25 05:59:41 PM PDT 24
Finished Jun 25 06:40:35 PM PDT 24
Peak memory 244128 kb
Host smart-c112efd4-1772-4411-b6fc-599669acc531
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704134684 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1704134684
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3803864661
Short name T68
Test name
Test status
Simulation time 2642500305 ps
CPU time 18.52 seconds
Started Jun 25 05:59:42 PM PDT 24
Finished Jun 25 06:00:10 PM PDT 24
Peak memory 213364 kb
Host smart-fed0ef7c-f1ba-4075-a0a9-9f3e088c1bdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803864661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3803864661
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1439891719
Short name T47
Test name
Test status
Simulation time 6920147229 ps
CPU time 191.4 seconds
Started Jun 25 05:59:42 PM PDT 24
Finished Jun 25 06:03:03 PM PDT 24
Peak memory 236336 kb
Host smart-7fd45efb-04e3-473b-8506-6ab4934b7422
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439891719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1439891719
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2939603040
Short name T125
Test name
Test status
Simulation time 1376415138 ps
CPU time 19.06 seconds
Started Jun 25 05:59:41 PM PDT 24
Finished Jun 25 06:00:09 PM PDT 24
Peak memory 219376 kb
Host smart-80cd6bd6-6898-422c-a8dc-4de27ab4eb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939603040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2939603040
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1823396062
Short name T268
Test name
Test status
Simulation time 4269222429 ps
CPU time 22.46 seconds
Started Jun 25 05:59:45 PM PDT 24
Finished Jun 25 06:00:17 PM PDT 24
Peak memory 219408 kb
Host smart-44f2e052-a70f-454b-a300-788fc95d7821
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1823396062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1823396062
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.675802535
Short name T338
Test name
Test status
Simulation time 1657000708 ps
CPU time 30.04 seconds
Started Jun 25 05:59:42 PM PDT 24
Finished Jun 25 06:00:21 PM PDT 24
Peak memory 216932 kb
Host smart-36264638-a0b9-416e-988c-2082aa5d6c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675802535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.675802535
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1274331851
Short name T188
Test name
Test status
Simulation time 12780713857 ps
CPU time 103.47 seconds
Started Jun 25 05:59:45 PM PDT 24
Finished Jun 25 06:01:38 PM PDT 24
Peak memory 219400 kb
Host smart-4c4a3df7-901c-4b58-9457-9508bdca684e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274331851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1274331851
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1124657430
Short name T314
Test name
Test status
Simulation time 24622327027 ps
CPU time 948.11 seconds
Started Jun 25 05:59:42 PM PDT 24
Finished Jun 25 06:15:40 PM PDT 24
Peak memory 235872 kb
Host smart-76a00be0-ef51-45b4-b069-60c90a5d5637
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124657430 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.1124657430
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1428611588
Short name T264
Test name
Test status
Simulation time 1869016887 ps
CPU time 19.71 seconds
Started Jun 25 05:59:49 PM PDT 24
Finished Jun 25 06:00:17 PM PDT 24
Peak memory 217116 kb
Host smart-e65afb58-e96c-4706-8f56-509ab31379cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428611588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1428611588
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3421552655
Short name T210
Test name
Test status
Simulation time 16430043308 ps
CPU time 281.05 seconds
Started Jun 25 05:59:43 PM PDT 24
Finished Jun 25 06:04:34 PM PDT 24
Peak memory 233928 kb
Host smart-d92136d2-7321-4082-8538-6d7888156740
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421552655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3421552655
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.701422376
Short name T329
Test name
Test status
Simulation time 17035659816 ps
CPU time 64.48 seconds
Started Jun 25 05:59:42 PM PDT 24
Finished Jun 25 06:00:56 PM PDT 24
Peak memory 219420 kb
Host smart-5d5de182-acde-4b15-a74f-f0fbea196ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701422376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.701422376
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2271351902
Short name T306
Test name
Test status
Simulation time 3368557244 ps
CPU time 23.55 seconds
Started Jun 25 05:59:44 PM PDT 24
Finished Jun 25 06:00:17 PM PDT 24
Peak memory 219368 kb
Host smart-77b08afe-43a3-4060-a8ee-bd3b8d0d43c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2271351902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2271351902
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3260149233
Short name T279
Test name
Test status
Simulation time 8038112376 ps
CPU time 42.77 seconds
Started Jun 25 05:59:42 PM PDT 24
Finished Jun 25 06:00:34 PM PDT 24
Peak memory 217132 kb
Host smart-b936abeb-c2cf-40cf-8900-eac2db967146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260149233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3260149233
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.837135791
Short name T246
Test name
Test status
Simulation time 6175392331 ps
CPU time 58.11 seconds
Started Jun 25 05:59:41 PM PDT 24
Finished Jun 25 06:00:48 PM PDT 24
Peak memory 219000 kb
Host smart-57dafdbb-83ac-4f42-9393-cde3df1f9c10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837135791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.837135791
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3475597322
Short name T356
Test name
Test status
Simulation time 7056451173 ps
CPU time 30.51 seconds
Started Jun 25 05:59:52 PM PDT 24
Finished Jun 25 06:00:29 PM PDT 24
Peak memory 213360 kb
Host smart-1121f3cf-174d-4755-a491-00164371fc36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475597322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3475597322
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1754500701
Short name T318
Test name
Test status
Simulation time 119910038742 ps
CPU time 425.69 seconds
Started Jun 25 05:59:51 PM PDT 24
Finished Jun 25 06:07:04 PM PDT 24
Peak memory 240692 kb
Host smart-1cea5969-8e3e-4d64-bf10-7168ce1a3b61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754500701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1754500701
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2138524632
Short name T27
Test name
Test status
Simulation time 3456269865 ps
CPU time 31.59 seconds
Started Jun 25 05:59:49 PM PDT 24
Finished Jun 25 06:00:29 PM PDT 24
Peak memory 219416 kb
Host smart-9ffa5764-9018-4db8-8188-ab41a169d055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138524632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2138524632
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1530289017
Short name T172
Test name
Test status
Simulation time 20513245800 ps
CPU time 32.39 seconds
Started Jun 25 05:59:48 PM PDT 24
Finished Jun 25 06:00:29 PM PDT 24
Peak memory 217764 kb
Host smart-fb2668dc-5e24-43c7-b5a2-b0823697e765
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1530289017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1530289017
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3234752002
Short name T232
Test name
Test status
Simulation time 18348372035 ps
CPU time 71.52 seconds
Started Jun 25 05:59:50 PM PDT 24
Finished Jun 25 06:01:09 PM PDT 24
Peak memory 217056 kb
Host smart-4cccdf42-c8a9-4ccf-9257-c746ad4ebbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234752002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3234752002
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3121824285
Short name T325
Test name
Test status
Simulation time 35111620927 ps
CPU time 105.47 seconds
Started Jun 25 05:59:50 PM PDT 24
Finished Jun 25 06:01:43 PM PDT 24
Peak memory 219444 kb
Host smart-26bc0f65-7c07-4010-a3fd-c61d4f68aed6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121824285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3121824285
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3368106799
Short name T37
Test name
Test status
Simulation time 8551805022 ps
CPU time 19.61 seconds
Started Jun 25 05:58:08 PM PDT 24
Finished Jun 25 05:58:28 PM PDT 24
Peak memory 217640 kb
Host smart-54272a27-7c32-4f96-a808-00b6a9a53169
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368106799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3368106799
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3889886176
Short name T239
Test name
Test status
Simulation time 73710501231 ps
CPU time 241.98 seconds
Started Jun 25 05:58:21 PM PDT 24
Finished Jun 25 06:02:24 PM PDT 24
Peak memory 216080 kb
Host smart-fe7c3ee5-d095-47bd-a452-67bc4d9e6496
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889886176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3889886176
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1890581745
Short name T194
Test name
Test status
Simulation time 4813580842 ps
CPU time 27.83 seconds
Started Jun 25 05:58:21 PM PDT 24
Finished Jun 25 05:58:50 PM PDT 24
Peak memory 215556 kb
Host smart-15ca89e3-b58c-4979-afcb-08e876afedea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890581745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1890581745
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1918424081
Short name T198
Test name
Test status
Simulation time 3820031924 ps
CPU time 16.66 seconds
Started Jun 25 05:58:21 PM PDT 24
Finished Jun 25 05:58:39 PM PDT 24
Peak memory 217720 kb
Host smart-7c8d9cb9-3c0a-4a0c-8ffb-e9fd2952f240
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1918424081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1918424081
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3334245512
Short name T331
Test name
Test status
Simulation time 14517623916 ps
CPU time 44.89 seconds
Started Jun 25 05:58:09 PM PDT 24
Finished Jun 25 05:58:55 PM PDT 24
Peak memory 216812 kb
Host smart-a18b814a-1286-473a-b24e-4c00e49a57ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334245512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3334245512
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2725263940
Short name T336
Test name
Test status
Simulation time 53911388755 ps
CPU time 113.68 seconds
Started Jun 25 05:58:21 PM PDT 24
Finished Jun 25 06:00:16 PM PDT 24
Peak memory 221032 kb
Host smart-7bd875ae-b714-401e-b94f-8fc156e45029
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725263940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2725263940
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.965949090
Short name T67
Test name
Test status
Simulation time 15582420280 ps
CPU time 17.11 seconds
Started Jun 25 05:59:56 PM PDT 24
Finished Jun 25 06:00:18 PM PDT 24
Peak memory 217692 kb
Host smart-49b1cd58-00a1-4ed6-8fce-70f32f0c5390
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965949090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.965949090
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3541667766
Short name T307
Test name
Test status
Simulation time 3987273849 ps
CPU time 159.59 seconds
Started Jun 25 05:59:51 PM PDT 24
Finished Jun 25 06:02:38 PM PDT 24
Peak memory 228312 kb
Host smart-5cfd16d7-9115-48a6-a4c5-01fba43faac4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541667766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3541667766
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2827142623
Short name T9
Test name
Test status
Simulation time 8395108280 ps
CPU time 44.18 seconds
Started Jun 25 05:59:51 PM PDT 24
Finished Jun 25 06:00:42 PM PDT 24
Peak memory 219396 kb
Host smart-7c6160de-f262-4b59-8297-58f4dd6e3d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827142623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2827142623
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2413724415
Short name T126
Test name
Test status
Simulation time 8140950872 ps
CPU time 27.41 seconds
Started Jun 25 05:59:51 PM PDT 24
Finished Jun 25 06:00:26 PM PDT 24
Peak memory 217760 kb
Host smart-c23b59d1-0b22-44da-8fd2-285c947be602
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2413724415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2413724415
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.805140535
Short name T206
Test name
Test status
Simulation time 343560513 ps
CPU time 20.23 seconds
Started Jun 25 05:59:51 PM PDT 24
Finished Jun 25 06:00:18 PM PDT 24
Peak memory 215948 kb
Host smart-ad88fcab-df5c-4420-ac7e-10b23db34894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805140535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.805140535
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3421156645
Short name T82
Test name
Test status
Simulation time 7682775328 ps
CPU time 37.92 seconds
Started Jun 25 05:59:51 PM PDT 24
Finished Jun 25 06:00:36 PM PDT 24
Peak memory 219404 kb
Host smart-4a8703e8-f905-4f34-88c8-2ff5a9dae15f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421156645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3421156645
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2250397013
Short name T355
Test name
Test status
Simulation time 3769259278 ps
CPU time 22.21 seconds
Started Jun 25 05:59:56 PM PDT 24
Finished Jun 25 06:00:23 PM PDT 24
Peak memory 217356 kb
Host smart-1380ebe5-599a-449c-8711-ee6c30b54af1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250397013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2250397013
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.854270811
Short name T244
Test name
Test status
Simulation time 156123125392 ps
CPU time 718.37 seconds
Started Jun 25 05:59:58 PM PDT 24
Finished Jun 25 06:12:01 PM PDT 24
Peak memory 236300 kb
Host smart-5d171006-53aa-4679-97ff-22133575a44f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854270811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.854270811
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.4293840487
Short name T137
Test name
Test status
Simulation time 5373172759 ps
CPU time 34.74 seconds
Started Jun 25 05:59:59 PM PDT 24
Finished Jun 25 06:00:37 PM PDT 24
Peak memory 219432 kb
Host smart-10374590-ae28-4ab1-b01b-9f23ae0bcc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293840487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.4293840487
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3356396475
Short name T337
Test name
Test status
Simulation time 355607165 ps
CPU time 10.5 seconds
Started Jun 25 05:59:58 PM PDT 24
Finished Jun 25 06:00:12 PM PDT 24
Peak memory 219308 kb
Host smart-10ed594d-a77c-40dc-b28f-dc3af279a67b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3356396475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3356396475
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.4112127427
Short name T168
Test name
Test status
Simulation time 1802841278 ps
CPU time 31.82 seconds
Started Jun 25 05:59:57 PM PDT 24
Finished Jun 25 06:00:33 PM PDT 24
Peak memory 216656 kb
Host smart-8a5e558e-74c4-4afa-aa12-856f0a611b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112127427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.4112127427
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.692865894
Short name T326
Test name
Test status
Simulation time 10666611308 ps
CPU time 48.91 seconds
Started Jun 25 05:59:57 PM PDT 24
Finished Jun 25 06:00:50 PM PDT 24
Peak memory 217472 kb
Host smart-61cfa91e-3e5f-4733-8e0d-a09d1b5905ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692865894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.692865894
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3921697506
Short name T69
Test name
Test status
Simulation time 3847516171 ps
CPU time 29.87 seconds
Started Jun 25 05:59:57 PM PDT 24
Finished Jun 25 06:00:31 PM PDT 24
Peak memory 213396 kb
Host smart-48d38003-b323-4e95-8268-3feca4820667
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921697506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3921697506
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2309659205
Short name T340
Test name
Test status
Simulation time 15694283252 ps
CPU time 44.95 seconds
Started Jun 25 05:59:57 PM PDT 24
Finished Jun 25 06:00:46 PM PDT 24
Peak memory 219232 kb
Host smart-744e5087-08ca-4679-9a11-b6bbaaabad9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309659205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2309659205
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3828523217
Short name T20
Test name
Test status
Simulation time 16793576451 ps
CPU time 34.07 seconds
Started Jun 25 05:59:57 PM PDT 24
Finished Jun 25 06:00:36 PM PDT 24
Peak memory 219392 kb
Host smart-93aa4b4b-6bc4-4e93-aa42-66321c81bfc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3828523217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3828523217
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3159194075
Short name T241
Test name
Test status
Simulation time 7245297468 ps
CPU time 38.01 seconds
Started Jun 25 05:59:57 PM PDT 24
Finished Jun 25 06:00:39 PM PDT 24
Peak memory 217524 kb
Host smart-e3364b72-cd3c-4f46-a0c8-fe703bc74968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159194075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3159194075
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3650266023
Short name T237
Test name
Test status
Simulation time 39643387053 ps
CPU time 114.22 seconds
Started Jun 25 05:59:59 PM PDT 24
Finished Jun 25 06:01:56 PM PDT 24
Peak memory 222824 kb
Host smart-2f02ab99-2865-4cce-9f7a-6a64dc1d30bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650266023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3650266023
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.4121429751
Short name T128
Test name
Test status
Simulation time 661070997 ps
CPU time 8.43 seconds
Started Jun 25 06:00:06 PM PDT 24
Finished Jun 25 06:00:17 PM PDT 24
Peak memory 217220 kb
Host smart-4b571fd9-f14c-4631-b0d7-68d91972a6ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121429751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.4121429751
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1087682820
Short name T155
Test name
Test status
Simulation time 346427449623 ps
CPU time 548.15 seconds
Started Jun 25 05:59:57 PM PDT 24
Finished Jun 25 06:09:10 PM PDT 24
Peak memory 242412 kb
Host smart-0d31f455-8b2d-419b-b380-64901ed208b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087682820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1087682820
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3782229334
Short name T49
Test name
Test status
Simulation time 27465145167 ps
CPU time 58.56 seconds
Started Jun 25 06:00:05 PM PDT 24
Finished Jun 25 06:01:05 PM PDT 24
Peak memory 219216 kb
Host smart-9740bff5-15f2-41ab-ab31-59c0c350853a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782229334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3782229334
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3858436270
Short name T60
Test name
Test status
Simulation time 1454703967 ps
CPU time 18.94 seconds
Started Jun 25 05:59:57 PM PDT 24
Finished Jun 25 06:00:20 PM PDT 24
Peak memory 219332 kb
Host smart-f001c7ac-03dd-43d6-b1c2-bd2e691e3252
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3858436270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3858436270
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1157605202
Short name T204
Test name
Test status
Simulation time 1369404407 ps
CPU time 20.68 seconds
Started Jun 25 05:59:57 PM PDT 24
Finished Jun 25 06:00:22 PM PDT 24
Peak memory 216560 kb
Host smart-91709a07-571f-4fa1-8ac0-b887e6dcd069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157605202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1157605202
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.778497294
Short name T262
Test name
Test status
Simulation time 8082197710 ps
CPU time 49.8 seconds
Started Jun 25 05:59:57 PM PDT 24
Finished Jun 25 06:00:51 PM PDT 24
Peak memory 217636 kb
Host smart-6ac43ed8-6740-444b-ab53-366851f43f69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778497294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.778497294
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.579784466
Short name T25
Test name
Test status
Simulation time 169350460 ps
CPU time 8.38 seconds
Started Jun 25 06:00:08 PM PDT 24
Finished Jun 25 06:00:18 PM PDT 24
Peak memory 213008 kb
Host smart-2671da1a-20f7-4e54-9838-e3423892a00e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579784466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.579784466
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1526522759
Short name T189
Test name
Test status
Simulation time 287100118019 ps
CPU time 727.41 seconds
Started Jun 25 06:00:05 PM PDT 24
Finished Jun 25 06:12:15 PM PDT 24
Peak memory 236260 kb
Host smart-f61905f7-8c7a-4463-ab7f-0d69c54e95c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526522759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1526522759
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2726018697
Short name T249
Test name
Test status
Simulation time 689357463 ps
CPU time 19.69 seconds
Started Jun 25 06:00:05 PM PDT 24
Finished Jun 25 06:00:26 PM PDT 24
Peak memory 219380 kb
Host smart-fcf2b877-0a9a-4611-85a8-b3375ba9dca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726018697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2726018697
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2467794112
Short name T320
Test name
Test status
Simulation time 8609962757 ps
CPU time 22.47 seconds
Started Jun 25 06:00:08 PM PDT 24
Finished Jun 25 06:00:32 PM PDT 24
Peak memory 219380 kb
Host smart-67aa196d-8fb0-4539-ab06-4a8a87531bb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2467794112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2467794112
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1211873020
Short name T267
Test name
Test status
Simulation time 7836329004 ps
CPU time 46.81 seconds
Started Jun 25 06:00:06 PM PDT 24
Finished Jun 25 06:00:54 PM PDT 24
Peak memory 217084 kb
Host smart-90a160b8-371b-47dd-b12e-3719e714c30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211873020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1211873020
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.176601835
Short name T80
Test name
Test status
Simulation time 1857058153 ps
CPU time 50.81 seconds
Started Jun 25 06:00:05 PM PDT 24
Finished Jun 25 06:00:57 PM PDT 24
Peak memory 219348 kb
Host smart-010dde17-c7dc-4365-80f7-da4d1bbbad8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176601835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.176601835
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.34440664
Short name T236
Test name
Test status
Simulation time 660885941 ps
CPU time 8.45 seconds
Started Jun 25 06:00:06 PM PDT 24
Finished Jun 25 06:00:17 PM PDT 24
Peak memory 217080 kb
Host smart-a2b74198-01d2-45d9-9e0c-9836c2861d44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34440664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.34440664
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.492029285
Short name T106
Test name
Test status
Simulation time 8523136089 ps
CPU time 136.45 seconds
Started Jun 25 06:00:06 PM PDT 24
Finished Jun 25 06:02:24 PM PDT 24
Peak memory 235872 kb
Host smart-1ae6baec-732b-4c34-92c3-bad8d0d87079
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492029285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.492029285
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.940328024
Short name T191
Test name
Test status
Simulation time 2014863346 ps
CPU time 14.14 seconds
Started Jun 25 06:00:08 PM PDT 24
Finished Jun 25 06:00:24 PM PDT 24
Peak memory 219340 kb
Host smart-1d8ccaba-d228-44e3-960d-a4cafe4162e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=940328024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.940328024
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3522764736
Short name T254
Test name
Test status
Simulation time 8718357892 ps
CPU time 52.12 seconds
Started Jun 25 06:00:08 PM PDT 24
Finished Jun 25 06:01:02 PM PDT 24
Peak memory 216588 kb
Host smart-653feb72-fbfb-4cc9-8bc5-5c530d3090a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522764736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3522764736
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2997821517
Short name T343
Test name
Test status
Simulation time 17085774993 ps
CPU time 171.26 seconds
Started Jun 25 06:00:05 PM PDT 24
Finished Jun 25 06:02:57 PM PDT 24
Peak memory 219424 kb
Host smart-2cdc8c27-6a9c-41a3-a0c6-67820a2016f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997821517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2997821517
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3367370440
Short name T291
Test name
Test status
Simulation time 2031345329 ps
CPU time 20.38 seconds
Started Jun 25 06:00:13 PM PDT 24
Finished Jun 25 06:00:35 PM PDT 24
Peak memory 217248 kb
Host smart-82cc31c3-e7a8-4e94-8872-bd85da2419e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367370440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3367370440
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2204020586
Short name T233
Test name
Test status
Simulation time 15920640571 ps
CPU time 46.12 seconds
Started Jun 25 06:00:07 PM PDT 24
Finished Jun 25 06:00:55 PM PDT 24
Peak memory 219412 kb
Host smart-eec05121-4cda-4589-9b0d-660bc0a170fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204020586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2204020586
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2169870877
Short name T58
Test name
Test status
Simulation time 694354170 ps
CPU time 13.08 seconds
Started Jun 25 06:00:06 PM PDT 24
Finished Jun 25 06:00:21 PM PDT 24
Peak memory 218632 kb
Host smart-eaaee9cd-68d4-48f6-bc04-4ad890c44e41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2169870877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2169870877
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.4206141111
Short name T265
Test name
Test status
Simulation time 19830553384 ps
CPU time 52.63 seconds
Started Jun 25 06:00:05 PM PDT 24
Finished Jun 25 06:00:59 PM PDT 24
Peak memory 216444 kb
Host smart-b4caefbf-92a1-466b-8623-859638481e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206141111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.4206141111
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1970375649
Short name T201
Test name
Test status
Simulation time 20389512508 ps
CPU time 55.3 seconds
Started Jun 25 06:00:07 PM PDT 24
Finished Jun 25 06:01:04 PM PDT 24
Peak memory 219360 kb
Host smart-a60b9226-1b92-4db0-a6aa-220a4632df5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970375649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1970375649
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3952910414
Short name T258
Test name
Test status
Simulation time 689322681 ps
CPU time 8.41 seconds
Started Jun 25 06:00:12 PM PDT 24
Finished Jun 25 06:00:22 PM PDT 24
Peak memory 217244 kb
Host smart-dc66d824-a153-4f0c-8775-d559caaaab76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952910414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3952910414
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.153357453
Short name T272
Test name
Test status
Simulation time 15414673030 ps
CPU time 253.17 seconds
Started Jun 25 06:00:13 PM PDT 24
Finished Jun 25 06:04:28 PM PDT 24
Peak memory 240432 kb
Host smart-9b3a19a8-263d-421c-bffd-fabc7ca64890
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153357453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.153357453
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1165088889
Short name T136
Test name
Test status
Simulation time 6967972533 ps
CPU time 53.58 seconds
Started Jun 25 06:00:14 PM PDT 24
Finished Jun 25 06:01:09 PM PDT 24
Peak memory 219376 kb
Host smart-294268b5-ada5-48c9-a46f-97f73503e4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165088889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1165088889
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3713798594
Short name T131
Test name
Test status
Simulation time 5746184275 ps
CPU time 25.93 seconds
Started Jun 25 06:00:12 PM PDT 24
Finished Jun 25 06:00:40 PM PDT 24
Peak memory 217764 kb
Host smart-08ce143d-b185-479e-bae6-accca69aa470
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3713798594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3713798594
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1713262453
Short name T38
Test name
Test status
Simulation time 771153000 ps
CPU time 19.93 seconds
Started Jun 25 06:00:13 PM PDT 24
Finished Jun 25 06:00:34 PM PDT 24
Peak memory 216848 kb
Host smart-e8d9bb5b-37c8-4c42-be4f-cfd53a64a7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713262453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1713262453
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1165047205
Short name T292
Test name
Test status
Simulation time 1406597995 ps
CPU time 40.27 seconds
Started Jun 25 06:00:12 PM PDT 24
Finished Jun 25 06:00:54 PM PDT 24
Peak memory 219344 kb
Host smart-e46a9992-5266-4652-b3c3-e59d23ad5d64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165047205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1165047205
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2388751662
Short name T334
Test name
Test status
Simulation time 5789344122 ps
CPU time 17.73 seconds
Started Jun 25 06:00:21 PM PDT 24
Finished Jun 25 06:00:40 PM PDT 24
Peak memory 217532 kb
Host smart-9b2a8cd4-dd2a-40f0-b2f9-c3157790e5c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388751662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2388751662
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.282645442
Short name T349
Test name
Test status
Simulation time 3470067769 ps
CPU time 156.85 seconds
Started Jun 25 06:00:21 PM PDT 24
Finished Jun 25 06:02:59 PM PDT 24
Peak memory 218240 kb
Host smart-c9f6cf76-b7a1-43ec-a09e-78744b51ac3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282645442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.282645442
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1441978593
Short name T8
Test name
Test status
Simulation time 346179751 ps
CPU time 19.42 seconds
Started Jun 25 06:00:22 PM PDT 24
Finished Jun 25 06:00:43 PM PDT 24
Peak memory 219280 kb
Host smart-6081593b-ec7d-4b41-b5de-f7941f5ed9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441978593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1441978593
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2238779507
Short name T339
Test name
Test status
Simulation time 1024882528 ps
CPU time 14.02 seconds
Started Jun 25 06:00:21 PM PDT 24
Finished Jun 25 06:00:37 PM PDT 24
Peak memory 219352 kb
Host smart-e870712f-e9a6-480d-bb15-27d4054ed17e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2238779507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2238779507
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.243922371
Short name T85
Test name
Test status
Simulation time 2896753800 ps
CPU time 42.51 seconds
Started Jun 25 06:00:13 PM PDT 24
Finished Jun 25 06:00:57 PM PDT 24
Peak memory 216180 kb
Host smart-75a3a6b9-45f0-4249-83d3-a2f6187a3b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243922371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.243922371
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3452961709
Short name T146
Test name
Test status
Simulation time 1205674381 ps
CPU time 34.18 seconds
Started Jun 25 06:00:13 PM PDT 24
Finished Jun 25 06:00:48 PM PDT 24
Peak memory 219348 kb
Host smart-544cb549-2c7d-4f4a-ad46-5d8b74c734a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452961709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3452961709
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.859651187
Short name T16
Test name
Test status
Simulation time 41612221338 ps
CPU time 9398.59 seconds
Started Jun 25 06:00:23 PM PDT 24
Finished Jun 25 08:37:04 PM PDT 24
Peak memory 235916 kb
Host smart-96a74199-5530-4f41-b22e-8bf07bb0ac69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859651187 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.859651187
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1557307923
Short name T351
Test name
Test status
Simulation time 2617373561 ps
CPU time 16.78 seconds
Started Jun 25 06:00:22 PM PDT 24
Finished Jun 25 06:00:41 PM PDT 24
Peak memory 217132 kb
Host smart-ff1839cf-dd8b-47d4-bb21-c35901448e44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557307923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1557307923
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3802285712
Short name T33
Test name
Test status
Simulation time 12335889013 ps
CPU time 206.45 seconds
Started Jun 25 06:00:23 PM PDT 24
Finished Jun 25 06:03:51 PM PDT 24
Peak memory 218016 kb
Host smart-70b88225-adbd-4933-8a67-004913788581
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802285712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3802285712
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1801482063
Short name T209
Test name
Test status
Simulation time 82045122042 ps
CPU time 45.38 seconds
Started Jun 25 06:00:23 PM PDT 24
Finished Jun 25 06:01:10 PM PDT 24
Peak memory 219276 kb
Host smart-077ae3b1-a880-4fb8-9134-745443002179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801482063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1801482063
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3325907400
Short name T197
Test name
Test status
Simulation time 3283373111 ps
CPU time 28.87 seconds
Started Jun 25 06:00:23 PM PDT 24
Finished Jun 25 06:00:53 PM PDT 24
Peak memory 219416 kb
Host smart-db2c9c01-58ed-408f-b2ee-e8189c3ab7b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3325907400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3325907400
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2298415658
Short name T83
Test name
Test status
Simulation time 7105589646 ps
CPU time 64.42 seconds
Started Jun 25 06:00:23 PM PDT 24
Finished Jun 25 06:01:29 PM PDT 24
Peak memory 216600 kb
Host smart-398fb81d-4d91-4d8e-ac60-a4e90da25f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298415658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2298415658
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3274567981
Short name T224
Test name
Test status
Simulation time 7809486565 ps
CPU time 31.82 seconds
Started Jun 25 06:00:22 PM PDT 24
Finished Jun 25 06:00:56 PM PDT 24
Peak memory 219292 kb
Host smart-615d0ed9-1616-425e-af3d-d010b341c23d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274567981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3274567981
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1690728302
Short name T359
Test name
Test status
Simulation time 4591827013 ps
CPU time 29.99 seconds
Started Jun 25 05:58:19 PM PDT 24
Finished Jun 25 05:58:51 PM PDT 24
Peak memory 217260 kb
Host smart-186e3e5f-a2fe-43f3-afea-52728e82e215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690728302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1690728302
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.731828045
Short name T185
Test name
Test status
Simulation time 12087480316 ps
CPU time 202.06 seconds
Started Jun 25 05:58:19 PM PDT 24
Finished Jun 25 06:01:43 PM PDT 24
Peak memory 236888 kb
Host smart-b80f11cc-bdeb-42a0-817b-c461b3d86bd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731828045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.731828045
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2032566801
Short name T346
Test name
Test status
Simulation time 2349647751 ps
CPU time 34.91 seconds
Started Jun 25 05:58:20 PM PDT 24
Finished Jun 25 05:58:57 PM PDT 24
Peak memory 219444 kb
Host smart-9f64e9af-6eec-44a1-9c6f-fc7f5e37451d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032566801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2032566801
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1569627231
Short name T225
Test name
Test status
Simulation time 7863216126 ps
CPU time 21.47 seconds
Started Jun 25 05:58:19 PM PDT 24
Finished Jun 25 05:58:42 PM PDT 24
Peak memory 211964 kb
Host smart-2eaeedc0-7404-46ec-985f-27b1704f2d4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1569627231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1569627231
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.701821112
Short name T22
Test name
Test status
Simulation time 11563831431 ps
CPU time 238.57 seconds
Started Jun 25 05:58:19 PM PDT 24
Finished Jun 25 06:02:20 PM PDT 24
Peak memory 238140 kb
Host smart-6bb2a3a5-cd92-4de3-88e7-0f77f56203d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701821112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.701821112
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3948278251
Short name T26
Test name
Test status
Simulation time 4235455442 ps
CPU time 33.5 seconds
Started Jun 25 06:00:31 PM PDT 24
Finished Jun 25 06:01:06 PM PDT 24
Peak memory 217264 kb
Host smart-8e8371c4-abb9-4b5b-9b72-01c3412b2cbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948278251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3948278251
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3579459038
Short name T44
Test name
Test status
Simulation time 7027328914 ps
CPU time 61.02 seconds
Started Jun 25 06:00:29 PM PDT 24
Finished Jun 25 06:01:32 PM PDT 24
Peak memory 219340 kb
Host smart-1f167b2e-5e8b-4b7f-addd-1ac2cf6adc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579459038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3579459038
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1164512255
Short name T127
Test name
Test status
Simulation time 8705092677 ps
CPU time 33.36 seconds
Started Jun 25 06:00:20 PM PDT 24
Finished Jun 25 06:00:55 PM PDT 24
Peak memory 219392 kb
Host smart-99cc2fe1-8a01-45ff-b66c-6cea4f3bb0ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1164512255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1164512255
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3461339098
Short name T300
Test name
Test status
Simulation time 26975950673 ps
CPU time 53.64 seconds
Started Jun 25 06:00:21 PM PDT 24
Finished Jun 25 06:01:16 PM PDT 24
Peak memory 216980 kb
Host smart-7799e835-e3ef-4840-8df3-bb8ac5e54ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461339098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3461339098
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.4049992635
Short name T170
Test name
Test status
Simulation time 51193231818 ps
CPU time 137.78 seconds
Started Jun 25 06:00:22 PM PDT 24
Finished Jun 25 06:02:42 PM PDT 24
Peak memory 218276 kb
Host smart-050a231c-bb0e-46c6-941e-e1bcc1d9d128
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049992635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.4049992635
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1288897145
Short name T12
Test name
Test status
Simulation time 109387816370 ps
CPU time 936.35 seconds
Started Jun 25 06:00:35 PM PDT 24
Finished Jun 25 06:16:13 PM PDT 24
Peak memory 233740 kb
Host smart-b0a70a8c-085b-409d-ad80-c26359bdea37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288897145 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.1288897145
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1196398794
Short name T160
Test name
Test status
Simulation time 2353208741 ps
CPU time 8.45 seconds
Started Jun 25 06:00:27 PM PDT 24
Finished Jun 25 06:00:37 PM PDT 24
Peak memory 217316 kb
Host smart-fb72d524-4aae-4ef6-9fdd-8edd8fa0aa99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196398794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1196398794
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.580483802
Short name T10
Test name
Test status
Simulation time 51477402582 ps
CPU time 595.76 seconds
Started Jun 25 06:00:31 PM PDT 24
Finished Jun 25 06:10:28 PM PDT 24
Peak memory 233920 kb
Host smart-4f19ae5c-9f60-4001-8aea-009f4a8e0ed3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580483802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.580483802
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2486468359
Short name T242
Test name
Test status
Simulation time 16784226363 ps
CPU time 65.04 seconds
Started Jun 25 06:00:30 PM PDT 24
Finished Jun 25 06:01:36 PM PDT 24
Peak memory 219328 kb
Host smart-9e9001f2-4754-4516-aac7-3960daf38d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486468359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2486468359
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1742157740
Short name T309
Test name
Test status
Simulation time 6436342692 ps
CPU time 27.94 seconds
Started Jun 25 06:00:28 PM PDT 24
Finished Jun 25 06:00:57 PM PDT 24
Peak memory 219416 kb
Host smart-3f53acd7-443f-45e8-8ca3-e0cbee71922e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1742157740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1742157740
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.334038775
Short name T144
Test name
Test status
Simulation time 11661094129 ps
CPU time 74.15 seconds
Started Jun 25 06:00:29 PM PDT 24
Finished Jun 25 06:01:44 PM PDT 24
Peak memory 220704 kb
Host smart-49d741a1-1399-4dcc-92c4-89796d6532b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334038775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.334038775
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2787600112
Short name T195
Test name
Test status
Simulation time 2382646395 ps
CPU time 22.35 seconds
Started Jun 25 06:00:29 PM PDT 24
Finished Jun 25 06:00:53 PM PDT 24
Peak memory 217276 kb
Host smart-0912c311-acc6-4db5-99db-d3b371caf6f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787600112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2787600112
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1794320950
Short name T352
Test name
Test status
Simulation time 152307515200 ps
CPU time 346.52 seconds
Started Jun 25 06:00:28 PM PDT 24
Finished Jun 25 06:06:17 PM PDT 24
Peak memory 224584 kb
Host smart-1a6ac8a5-c484-4008-a025-fa03b08261a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794320950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1794320950
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.655893528
Short name T229
Test name
Test status
Simulation time 1736937723 ps
CPU time 20.6 seconds
Started Jun 25 06:00:29 PM PDT 24
Finished Jun 25 06:00:51 PM PDT 24
Peak memory 219356 kb
Host smart-edfbaef2-775f-4052-92b0-e2ad381ec0f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=655893528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.655893528
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1078738335
Short name T212
Test name
Test status
Simulation time 2856753064 ps
CPU time 20.14 seconds
Started Jun 25 06:00:28 PM PDT 24
Finished Jun 25 06:00:50 PM PDT 24
Peak memory 216080 kb
Host smart-00f79f1b-31b3-4611-814f-a910e841d5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078738335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1078738335
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.787420761
Short name T245
Test name
Test status
Simulation time 742231852 ps
CPU time 45.15 seconds
Started Jun 25 06:00:29 PM PDT 24
Finished Jun 25 06:01:16 PM PDT 24
Peak memory 219368 kb
Host smart-2175ae5c-64a5-4407-aa0f-10fb5df6d91d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787420761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.787420761
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2024177232
Short name T109
Test name
Test status
Simulation time 26150023558 ps
CPU time 1046.36 seconds
Started Jun 25 06:00:31 PM PDT 24
Finished Jun 25 06:17:59 PM PDT 24
Peak memory 236952 kb
Host smart-c3f2f8ba-bf69-4279-ba3a-75a1a97cf05b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024177232 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2024177232
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3324209239
Short name T269
Test name
Test status
Simulation time 4936752550 ps
CPU time 31.74 seconds
Started Jun 25 06:00:35 PM PDT 24
Finished Jun 25 06:01:08 PM PDT 24
Peak memory 217328 kb
Host smart-aa66b0bb-aedf-4c4c-90b4-c0c5d1363896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324209239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3324209239
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3496527899
Short name T263
Test name
Test status
Simulation time 201736423992 ps
CPU time 961.22 seconds
Started Jun 25 06:00:29 PM PDT 24
Finished Jun 25 06:16:32 PM PDT 24
Peak memory 237248 kb
Host smart-dc5be265-70a6-42a5-9b67-5bc847dc1662
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496527899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3496527899
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3096308872
Short name T177
Test name
Test status
Simulation time 14433414870 ps
CPU time 42.05 seconds
Started Jun 25 06:00:28 PM PDT 24
Finished Jun 25 06:01:11 PM PDT 24
Peak memory 219380 kb
Host smart-d46f9d28-f096-4d77-babc-ade92d3fc888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096308872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3096308872
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3695009896
Short name T301
Test name
Test status
Simulation time 3297203653 ps
CPU time 27.81 seconds
Started Jun 25 06:00:27 PM PDT 24
Finished Jun 25 06:00:56 PM PDT 24
Peak memory 211472 kb
Host smart-e449e18b-3918-415a-8316-fe4b2e5a1ab0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3695009896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3695009896
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3218467170
Short name T17
Test name
Test status
Simulation time 362854563 ps
CPU time 20.5 seconds
Started Jun 25 06:00:28 PM PDT 24
Finished Jun 25 06:00:50 PM PDT 24
Peak memory 216460 kb
Host smart-8c29fdba-186d-4bf1-b5a8-1cbbd7e01351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218467170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3218467170
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.368726711
Short name T30
Test name
Test status
Simulation time 33672367654 ps
CPU time 57.82 seconds
Started Jun 25 06:00:28 PM PDT 24
Finished Jun 25 06:01:28 PM PDT 24
Peak memory 219444 kb
Host smart-2019ed5c-0283-472a-95ae-adc9c7b16533
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368726711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.368726711
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1799704391
Short name T213
Test name
Test status
Simulation time 228605895 ps
CPU time 8.38 seconds
Started Jun 25 06:00:30 PM PDT 24
Finished Jun 25 06:00:39 PM PDT 24
Peak memory 217208 kb
Host smart-9dbb29f4-53fa-4efe-a445-164006d89a4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799704391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1799704391
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1920640157
Short name T150
Test name
Test status
Simulation time 627864869174 ps
CPU time 493.08 seconds
Started Jun 25 06:00:27 PM PDT 24
Finished Jun 25 06:08:41 PM PDT 24
Peak memory 224192 kb
Host smart-8b10a7b4-c79f-40f4-8e1a-6cea3ee765fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920640157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1920640157
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1861173379
Short name T142
Test name
Test status
Simulation time 2437852597 ps
CPU time 27.37 seconds
Started Jun 25 06:00:35 PM PDT 24
Finished Jun 25 06:01:04 PM PDT 24
Peak memory 219272 kb
Host smart-19593446-7784-4f58-a241-7fe1da866938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861173379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1861173379
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.482698366
Short name T248
Test name
Test status
Simulation time 526730542 ps
CPU time 13.74 seconds
Started Jun 25 06:00:30 PM PDT 24
Finished Jun 25 06:00:45 PM PDT 24
Peak memory 219456 kb
Host smart-605aace5-23c7-4df7-bab6-a9e6bf914ed9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=482698366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.482698366
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1360151695
Short name T315
Test name
Test status
Simulation time 1386012678 ps
CPU time 20.16 seconds
Started Jun 25 06:00:27 PM PDT 24
Finished Jun 25 06:00:49 PM PDT 24
Peak memory 216496 kb
Host smart-e8893d08-336a-4dcd-a51a-9064dab72dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360151695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1360151695
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1320577542
Short name T57
Test name
Test status
Simulation time 55711723289 ps
CPU time 10662 seconds
Started Jun 25 06:00:28 PM PDT 24
Finished Jun 25 08:58:13 PM PDT 24
Peak memory 237164 kb
Host smart-1879f2e2-d218-4ce2-b37e-fa7efa1b9de0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320577542 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.1320577542
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2493850250
Short name T169
Test name
Test status
Simulation time 3620958046 ps
CPU time 27.73 seconds
Started Jun 25 06:00:35 PM PDT 24
Finished Jun 25 06:01:05 PM PDT 24
Peak memory 217288 kb
Host smart-7c5d05db-83c5-413a-979d-91096a144d34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493850250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2493850250
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4237586236
Short name T42
Test name
Test status
Simulation time 236198151032 ps
CPU time 663.84 seconds
Started Jun 25 06:00:30 PM PDT 24
Finished Jun 25 06:11:35 PM PDT 24
Peak memory 238684 kb
Host smart-720aac3f-be57-433a-ae44-c74a2ddc8f92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237586236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.4237586236
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2998269857
Short name T316
Test name
Test status
Simulation time 76561945309 ps
CPU time 59.21 seconds
Started Jun 25 06:00:37 PM PDT 24
Finished Jun 25 06:01:38 PM PDT 24
Peak memory 219276 kb
Host smart-7909bc6b-b601-4253-b673-acc0e3633c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998269857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2998269857
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4287127462
Short name T289
Test name
Test status
Simulation time 6123193603 ps
CPU time 21.6 seconds
Started Jun 25 06:00:30 PM PDT 24
Finished Jun 25 06:00:53 PM PDT 24
Peak memory 219404 kb
Host smart-0fdaa93f-0de2-4b54-882e-aa6d031eb872
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4287127462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4287127462
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.349334643
Short name T216
Test name
Test status
Simulation time 360730955 ps
CPU time 19.94 seconds
Started Jun 25 06:00:28 PM PDT 24
Finished Jun 25 06:00:50 PM PDT 24
Peak memory 215384 kb
Host smart-9ed56251-4278-4522-b347-078a32e651fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349334643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.349334643
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.545230789
Short name T348
Test name
Test status
Simulation time 825819486 ps
CPU time 42.27 seconds
Started Jun 25 06:00:28 PM PDT 24
Finished Jun 25 06:01:12 PM PDT 24
Peak memory 219368 kb
Host smart-00cdc87c-8c46-46d6-90cc-7f4172fec663
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545230789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.545230789
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3262196362
Short name T163
Test name
Test status
Simulation time 3950826973 ps
CPU time 32.08 seconds
Started Jun 25 06:00:38 PM PDT 24
Finished Jun 25 06:01:11 PM PDT 24
Peak memory 217236 kb
Host smart-b5c21883-8796-4390-bac2-20bf6167e326
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262196362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3262196362
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.706977227
Short name T39
Test name
Test status
Simulation time 216878195259 ps
CPU time 557.7 seconds
Started Jun 25 06:00:37 PM PDT 24
Finished Jun 25 06:09:56 PM PDT 24
Peak memory 225748 kb
Host smart-746ddabd-9af0-44ef-ade9-ca45f5a82e26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706977227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.706977227
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3969742992
Short name T218
Test name
Test status
Simulation time 5133412620 ps
CPU time 52.35 seconds
Started Jun 25 06:00:38 PM PDT 24
Finished Jun 25 06:01:31 PM PDT 24
Peak memory 219272 kb
Host smart-6d85c918-18fb-49e0-bd9c-bd1907b6a26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969742992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3969742992
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.563719424
Short name T186
Test name
Test status
Simulation time 671974857 ps
CPU time 10.51 seconds
Started Jun 25 06:00:37 PM PDT 24
Finished Jun 25 06:00:49 PM PDT 24
Peak memory 219308 kb
Host smart-74ee6779-1e81-46b0-a4e7-3a72370ea1c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=563719424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.563719424
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.676496886
Short name T158
Test name
Test status
Simulation time 684272505 ps
CPU time 19.78 seconds
Started Jun 25 06:00:36 PM PDT 24
Finished Jun 25 06:00:58 PM PDT 24
Peak memory 216560 kb
Host smart-c1ea9521-0154-492d-b155-40e5eeec270e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676496886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.676496886
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1868622779
Short name T322
Test name
Test status
Simulation time 387485331 ps
CPU time 24.78 seconds
Started Jun 25 06:00:35 PM PDT 24
Finished Jun 25 06:01:01 PM PDT 24
Peak memory 217796 kb
Host smart-482aa668-ea11-4f99-9f6a-0d9084940f7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868622779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1868622779
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1177798605
Short name T139
Test name
Test status
Simulation time 2743405491 ps
CPU time 17.26 seconds
Started Jun 25 06:00:37 PM PDT 24
Finished Jun 25 06:00:56 PM PDT 24
Peak memory 217304 kb
Host smart-0674fbd2-6d6e-45b2-8eb8-f5912422d6b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177798605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1177798605
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1007013409
Short name T202
Test name
Test status
Simulation time 151773969517 ps
CPU time 805.38 seconds
Started Jun 25 06:00:35 PM PDT 24
Finished Jun 25 06:14:03 PM PDT 24
Peak memory 226096 kb
Host smart-196dacd2-53d9-4c93-8ee4-4d9eff7e5167
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007013409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1007013409
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1522408324
Short name T298
Test name
Test status
Simulation time 3412030742 ps
CPU time 39.72 seconds
Started Jun 25 06:00:38 PM PDT 24
Finished Jun 25 06:01:19 PM PDT 24
Peak memory 219424 kb
Host smart-d059f396-9182-467d-a23a-fff0fdee202d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522408324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1522408324
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1199679058
Short name T324
Test name
Test status
Simulation time 4282351452 ps
CPU time 32.9 seconds
Started Jun 25 06:00:35 PM PDT 24
Finished Jun 25 06:01:10 PM PDT 24
Peak memory 211512 kb
Host smart-6c9fc100-ab43-437a-8412-d103972d1b0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1199679058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1199679058
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2662329423
Short name T84
Test name
Test status
Simulation time 1359925613 ps
CPU time 20.99 seconds
Started Jun 25 06:00:35 PM PDT 24
Finished Jun 25 06:00:58 PM PDT 24
Peak memory 217476 kb
Host smart-c4601181-c48e-4c31-a7f3-7e6f29cc7d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662329423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2662329423
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2551356110
Short name T247
Test name
Test status
Simulation time 132988025784 ps
CPU time 126.57 seconds
Started Jun 25 06:00:36 PM PDT 24
Finished Jun 25 06:02:45 PM PDT 24
Peak memory 220744 kb
Host smart-f24ee6b8-4739-465f-81dd-608ac5b7068b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551356110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2551356110
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.228117404
Short name T55
Test name
Test status
Simulation time 169644780024 ps
CPU time 1650.89 seconds
Started Jun 25 06:00:36 PM PDT 24
Finished Jun 25 06:28:09 PM PDT 24
Peak memory 238460 kb
Host smart-e4bf25b3-d99d-487b-83e2-7dfc5c686439
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228117404 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.228117404
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.4192418165
Short name T227
Test name
Test status
Simulation time 3146574682 ps
CPU time 26.89 seconds
Started Jun 25 06:00:43 PM PDT 24
Finished Jun 25 06:01:11 PM PDT 24
Peak memory 217332 kb
Host smart-8b9e996a-7122-4cb2-9e5c-6ac9cbfec712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192418165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.4192418165
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2235002327
Short name T293
Test name
Test status
Simulation time 85521760648 ps
CPU time 283.34 seconds
Started Jun 25 06:00:48 PM PDT 24
Finished Jun 25 06:05:33 PM PDT 24
Peak memory 219576 kb
Host smart-183d4648-84c8-4fe1-8623-8bf63188975c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235002327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2235002327
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2430081075
Short name T203
Test name
Test status
Simulation time 63700533557 ps
CPU time 54.06 seconds
Started Jun 25 06:00:44 PM PDT 24
Finished Jun 25 06:01:39 PM PDT 24
Peak memory 219444 kb
Host smart-8e0bd7f4-49ed-4067-99fe-0b443b38ad4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430081075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2430081075
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3490382245
Short name T220
Test name
Test status
Simulation time 14400825779 ps
CPU time 24.19 seconds
Started Jun 25 06:00:37 PM PDT 24
Finished Jun 25 06:01:03 PM PDT 24
Peak memory 219400 kb
Host smart-c53a9510-8df5-4c50-8a7d-16be2a3666b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3490382245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3490382245
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3219673456
Short name T164
Test name
Test status
Simulation time 5994781377 ps
CPU time 47.08 seconds
Started Jun 25 06:00:36 PM PDT 24
Finished Jun 25 06:01:25 PM PDT 24
Peak memory 216824 kb
Host smart-1b8c4726-732d-49a2-b72c-cbc8be5c465f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219673456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3219673456
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3088862906
Short name T330
Test name
Test status
Simulation time 281360376 ps
CPU time 13.69 seconds
Started Jun 25 06:00:35 PM PDT 24
Finished Jun 25 06:00:50 PM PDT 24
Peak memory 218840 kb
Host smart-09cd790a-2ca2-4c68-ad42-64d24623d68f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088862906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3088862906
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.4153323575
Short name T13
Test name
Test status
Simulation time 31075248503 ps
CPU time 477.19 seconds
Started Jun 25 06:00:45 PM PDT 24
Finished Jun 25 06:08:43 PM PDT 24
Peak memory 228916 kb
Host smart-58a29497-708a-409e-a8de-ad51a245cdbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153323575 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.4153323575
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3182110254
Short name T174
Test name
Test status
Simulation time 786964094 ps
CPU time 8.34 seconds
Started Jun 25 06:00:45 PM PDT 24
Finished Jun 25 06:00:54 PM PDT 24
Peak memory 217136 kb
Host smart-3350f9e1-e3f0-4180-ba3a-977dcead087c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182110254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3182110254
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1904754843
Short name T304
Test name
Test status
Simulation time 3932184090 ps
CPU time 144.61 seconds
Started Jun 25 06:00:42 PM PDT 24
Finished Jun 25 06:03:08 PM PDT 24
Peak memory 219608 kb
Host smart-b9f22e35-3892-432d-9a23-bce236e7514e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904754843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1904754843
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.4240013929
Short name T165
Test name
Test status
Simulation time 33538790280 ps
CPU time 63.21 seconds
Started Jun 25 06:00:47 PM PDT 24
Finished Jun 25 06:01:51 PM PDT 24
Peak memory 219408 kb
Host smart-4fa7ab23-1ecd-44e5-8c44-83075c29210d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240013929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.4240013929
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2844894777
Short name T344
Test name
Test status
Simulation time 2746563944 ps
CPU time 25.19 seconds
Started Jun 25 06:00:44 PM PDT 24
Finished Jun 25 06:01:10 PM PDT 24
Peak memory 219392 kb
Host smart-c5c633bd-f486-4e2e-a5ee-55cdf754b73c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2844894777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2844894777
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3835751329
Short name T347
Test name
Test status
Simulation time 8141267208 ps
CPU time 79.2 seconds
Started Jun 25 06:00:44 PM PDT 24
Finished Jun 25 06:02:04 PM PDT 24
Peak memory 216716 kb
Host smart-5e1297b0-23ba-4d17-94d6-b886012e53a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835751329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3835751329
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3933613549
Short name T199
Test name
Test status
Simulation time 3073191423 ps
CPU time 41.57 seconds
Started Jun 25 06:00:43 PM PDT 24
Finished Jun 25 06:01:25 PM PDT 24
Peak memory 217424 kb
Host smart-f9e7f767-cceb-4505-b2b2-18db0453fe81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933613549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3933613549
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.4212014356
Short name T54
Test name
Test status
Simulation time 16941775569 ps
CPU time 344.41 seconds
Started Jun 25 06:00:44 PM PDT 24
Finished Jun 25 06:06:29 PM PDT 24
Peak memory 228968 kb
Host smart-730ae6fe-55c4-400b-b663-16991e9a4896
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212014356 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.4212014356
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.305423425
Short name T260
Test name
Test status
Simulation time 21643061392 ps
CPU time 19.83 seconds
Started Jun 25 05:58:26 PM PDT 24
Finished Jun 25 05:58:46 PM PDT 24
Peak memory 217524 kb
Host smart-f3225e17-6cf5-41d8-8e21-9f09d9bba33c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305423425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.305423425
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.547020241
Short name T250
Test name
Test status
Simulation time 56864852147 ps
CPU time 563.82 seconds
Started Jun 25 05:58:20 PM PDT 24
Finished Jun 25 06:07:46 PM PDT 24
Peak memory 238012 kb
Host smart-4a4d8e3a-3394-4814-8d9e-1ecadd3b2f2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547020241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.547020241
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4285715947
Short name T217
Test name
Test status
Simulation time 15677337741 ps
CPU time 41.58 seconds
Started Jun 25 05:58:27 PM PDT 24
Finished Jun 25 05:59:10 PM PDT 24
Peak memory 219424 kb
Host smart-134e6b71-031c-4b49-b1f8-b9955fc17139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285715947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.4285715947
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2369111817
Short name T273
Test name
Test status
Simulation time 4270771886 ps
CPU time 22.74 seconds
Started Jun 25 05:58:20 PM PDT 24
Finished Jun 25 05:58:44 PM PDT 24
Peak memory 217792 kb
Host smart-c6236df6-1ed9-4952-b835-a8306309689f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2369111817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2369111817
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.4023530905
Short name T86
Test name
Test status
Simulation time 19747009471 ps
CPU time 55.11 seconds
Started Jun 25 05:58:19 PM PDT 24
Finished Jun 25 05:59:16 PM PDT 24
Peak memory 216524 kb
Host smart-7ceee66f-8079-4beb-bcc4-3eb2347e41f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023530905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.4023530905
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1160978863
Short name T271
Test name
Test status
Simulation time 554501990 ps
CPU time 39.71 seconds
Started Jun 25 05:58:20 PM PDT 24
Finished Jun 25 05:59:01 PM PDT 24
Peak memory 219392 kb
Host smart-5f67c8c7-9f31-4d98-8efc-d9e5215eeb09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160978863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1160978863
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.206163475
Short name T53
Test name
Test status
Simulation time 110022731764 ps
CPU time 2065.64 seconds
Started Jun 25 05:58:28 PM PDT 24
Finished Jun 25 06:32:55 PM PDT 24
Peak memory 238944 kb
Host smart-9d445c7e-4a99-4717-b513-df1a5dd2294f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206163475 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.206163475
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1921550537
Short name T153
Test name
Test status
Simulation time 4701877724 ps
CPU time 30.28 seconds
Started Jun 25 05:58:29 PM PDT 24
Finished Jun 25 05:59:00 PM PDT 24
Peak memory 213336 kb
Host smart-5f4c4ba8-9e48-4de9-9649-2a9a1a1b33c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921550537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1921550537
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3751901428
Short name T166
Test name
Test status
Simulation time 170762181757 ps
CPU time 412.26 seconds
Started Jun 25 05:58:27 PM PDT 24
Finished Jun 25 06:05:21 PM PDT 24
Peak memory 219220 kb
Host smart-5f679cb1-782d-446e-a1a0-bc1a802884b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751901428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3751901428
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2045128664
Short name T295
Test name
Test status
Simulation time 7005543278 ps
CPU time 57.52 seconds
Started Jun 25 05:58:27 PM PDT 24
Finished Jun 25 05:59:25 PM PDT 24
Peak memory 219356 kb
Host smart-91cca77d-eff3-4c7d-977b-49e901ecfcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045128664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2045128664
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2799825519
Short name T290
Test name
Test status
Simulation time 4270782726 ps
CPU time 33.73 seconds
Started Jun 25 05:58:27 PM PDT 24
Finished Jun 25 05:59:01 PM PDT 24
Peak memory 219412 kb
Host smart-a799f5c5-4496-4060-a8ff-c9f84b414d95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2799825519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2799825519
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3140126596
Short name T81
Test name
Test status
Simulation time 1500299618 ps
CPU time 20 seconds
Started Jun 25 05:58:27 PM PDT 24
Finished Jun 25 05:58:49 PM PDT 24
Peak memory 216836 kb
Host smart-73ec058a-d3d7-4924-99a1-5f9a2b337ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140126596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3140126596
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1394394894
Short name T302
Test name
Test status
Simulation time 36324634812 ps
CPU time 112.86 seconds
Started Jun 25 05:58:29 PM PDT 24
Finished Jun 25 06:00:23 PM PDT 24
Peak memory 223240 kb
Host smart-33c607c4-e2ee-4aa6-b63d-b3e29cc9f962
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394394894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1394394894
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.4086504461
Short name T278
Test name
Test status
Simulation time 8204903668 ps
CPU time 20.7 seconds
Started Jun 25 05:58:26 PM PDT 24
Finished Jun 25 05:58:48 PM PDT 24
Peak memory 217636 kb
Host smart-a59c0f59-0c0c-4e3a-93d7-4104effb6e62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086504461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.4086504461
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2138058480
Short name T342
Test name
Test status
Simulation time 33570405980 ps
CPU time 295.18 seconds
Started Jun 25 05:58:28 PM PDT 24
Finished Jun 25 06:03:24 PM PDT 24
Peak memory 219260 kb
Host smart-af7969f8-ca49-48df-9165-f2b254bf0cbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138058480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2138058480
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.715683597
Short name T288
Test name
Test status
Simulation time 6971833152 ps
CPU time 59.58 seconds
Started Jun 25 05:58:26 PM PDT 24
Finished Jun 25 05:59:27 PM PDT 24
Peak memory 219464 kb
Host smart-0c8240ee-8af8-4bf5-99b6-8b2bc39d4649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715683597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.715683597
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1809741657
Short name T222
Test name
Test status
Simulation time 411308076 ps
CPU time 10.62 seconds
Started Jun 25 05:58:27 PM PDT 24
Finished Jun 25 05:58:39 PM PDT 24
Peak memory 219352 kb
Host smart-a442f6d2-bb7e-43a3-9e39-2edc7a8ff2f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1809741657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1809741657
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1553608480
Short name T253
Test name
Test status
Simulation time 8580100896 ps
CPU time 41.07 seconds
Started Jun 25 05:58:27 PM PDT 24
Finished Jun 25 05:59:09 PM PDT 24
Peak memory 217764 kb
Host smart-47ac5409-a1b2-4380-a2af-be9912c27a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553608480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1553608480
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.4285598651
Short name T256
Test name
Test status
Simulation time 17514117413 ps
CPU time 88.98 seconds
Started Jun 25 05:58:27 PM PDT 24
Finished Jun 25 05:59:57 PM PDT 24
Peak memory 219944 kb
Host smart-70a184e9-e46f-40c4-97c9-03643d723d9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285598651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.4285598651
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1316803778
Short name T52
Test name
Test status
Simulation time 203322700360 ps
CPU time 4305.95 seconds
Started Jun 25 05:58:27 PM PDT 24
Finished Jun 25 07:10:15 PM PDT 24
Peak memory 237220 kb
Host smart-7e8c57a7-c143-4e94-b0b4-5b1505fd19d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316803778 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.1316803778
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2987932614
Short name T280
Test name
Test status
Simulation time 27591859381 ps
CPU time 22.82 seconds
Started Jun 25 05:58:36 PM PDT 24
Finished Jun 25 05:59:00 PM PDT 24
Peak memory 217524 kb
Host smart-3c616b33-b681-4771-b5c7-36abcb18f104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987932614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2987932614
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.4042092545
Short name T179
Test name
Test status
Simulation time 1513750217 ps
CPU time 101.14 seconds
Started Jun 25 05:58:35 PM PDT 24
Finished Jun 25 06:00:17 PM PDT 24
Peak memory 219016 kb
Host smart-e2aa345b-5749-48e4-bc19-c498e0e03b7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042092545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.4042092545
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.937238763
Short name T211
Test name
Test status
Simulation time 14136018199 ps
CPU time 59.27 seconds
Started Jun 25 05:58:35 PM PDT 24
Finished Jun 25 05:59:35 PM PDT 24
Peak memory 219420 kb
Host smart-c7917d07-cb0d-4929-8ccb-893426d5348a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937238763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.937238763
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3247140077
Short name T317
Test name
Test status
Simulation time 881204550 ps
CPU time 10.38 seconds
Started Jun 25 05:58:41 PM PDT 24
Finished Jun 25 05:58:52 PM PDT 24
Peak memory 218808 kb
Host smart-86c73012-3f6c-4cc1-88c0-1dbb295720c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3247140077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3247140077
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.491087288
Short name T129
Test name
Test status
Simulation time 680798324 ps
CPU time 19.61 seconds
Started Jun 25 05:58:27 PM PDT 24
Finished Jun 25 05:58:47 PM PDT 24
Peak memory 216660 kb
Host smart-de3e26ce-5c78-42a1-9045-4a6530f03cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491087288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.491087288
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1635584673
Short name T305
Test name
Test status
Simulation time 2115100270 ps
CPU time 68.63 seconds
Started Jun 25 05:58:34 PM PDT 24
Finished Jun 25 05:59:43 PM PDT 24
Peak memory 219356 kb
Host smart-1c06bc6f-7930-4588-ac61-2e9827da996f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635584673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1635584673
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3378659
Short name T360
Test name
Test status
Simulation time 3393623311 ps
CPU time 23.21 seconds
Started Jun 25 05:58:41 PM PDT 24
Finished Jun 25 05:59:05 PM PDT 24
Peak memory 216664 kb
Host smart-50b4fb8a-ac99-4664-98ab-2014996492c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3378659
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.493286463
Short name T157
Test name
Test status
Simulation time 44644127156 ps
CPU time 489.84 seconds
Started Jun 25 05:58:36 PM PDT 24
Finished Jun 25 06:06:47 PM PDT 24
Peak memory 239112 kb
Host smart-34384e2a-8967-4e37-a2c2-8ac915de943a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493286463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.493286463
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.873197425
Short name T312
Test name
Test status
Simulation time 27986262476 ps
CPU time 61.15 seconds
Started Jun 25 05:58:36 PM PDT 24
Finished Jun 25 05:59:38 PM PDT 24
Peak memory 219308 kb
Host smart-229a60f2-aeac-4f6e-a78d-f743eca3aef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873197425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.873197425
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2169942150
Short name T141
Test name
Test status
Simulation time 762664899 ps
CPU time 10.53 seconds
Started Jun 25 05:58:34 PM PDT 24
Finished Jun 25 05:58:46 PM PDT 24
Peak memory 219292 kb
Host smart-06159016-3c76-443f-8924-79b8d6bd3178
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2169942150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2169942150
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.49051517
Short name T257
Test name
Test status
Simulation time 689355005 ps
CPU time 20.28 seconds
Started Jun 25 05:58:35 PM PDT 24
Finished Jun 25 05:58:57 PM PDT 24
Peak memory 216732 kb
Host smart-b5fd8179-1d9c-43c2-ae31-4985a9204402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49051517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.49051517
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3745602680
Short name T266
Test name
Test status
Simulation time 63016646453 ps
CPU time 123.29 seconds
Started Jun 25 05:58:34 PM PDT 24
Finished Jun 25 06:00:38 PM PDT 24
Peak memory 219428 kb
Host smart-f542a71b-08f7-4971-ada3-2b0a82d393a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745602680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3745602680
Directory /workspace/9.rom_ctrl_stress_all/latest
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