Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.21 96.89 91.99 97.68 100.00 98.28 97.30 98.37


Total test records in report: 454
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T18 /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1284959990 Jun 26 04:44:50 PM PDT 24 Jun 26 04:59:34 PM PDT 24 140909462948 ps
T297 /workspace/coverage/default/1.rom_ctrl_smoke.4040857961 Jun 26 04:44:10 PM PDT 24 Jun 26 04:45:39 PM PDT 24 14745582056 ps
T298 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2025830793 Jun 26 04:44:44 PM PDT 24 Jun 26 04:46:18 PM PDT 24 29558750861 ps
T299 /workspace/coverage/default/41.rom_ctrl_alert_test.2775186844 Jun 26 04:44:59 PM PDT 24 Jun 26 04:45:39 PM PDT 24 1534934258 ps
T300 /workspace/coverage/default/12.rom_ctrl_alert_test.3737047541 Jun 26 04:44:37 PM PDT 24 Jun 26 04:45:22 PM PDT 24 4793108442 ps
T301 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3600067437 Jun 26 04:44:24 PM PDT 24 Jun 26 04:45:07 PM PDT 24 346243528 ps
T302 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2942752316 Jun 26 04:44:17 PM PDT 24 Jun 26 04:48:23 PM PDT 24 6473692390 ps
T44 /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3444775383 Jun 26 04:44:59 PM PDT 24 Jun 26 06:21:19 PM PDT 24 182501095972 ps
T303 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1403621723 Jun 26 04:44:33 PM PDT 24 Jun 26 04:45:30 PM PDT 24 3340339128 ps
T304 /workspace/coverage/default/49.rom_ctrl_stress_all.16240855 Jun 26 04:45:13 PM PDT 24 Jun 26 04:45:43 PM PDT 24 742825520 ps
T305 /workspace/coverage/default/6.rom_ctrl_stress_all.1212847560 Jun 26 04:44:23 PM PDT 24 Jun 26 04:45:16 PM PDT 24 1401594385 ps
T306 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2733858940 Jun 26 04:44:50 PM PDT 24 Jun 26 04:45:43 PM PDT 24 13851922531 ps
T307 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3595946944 Jun 26 04:44:24 PM PDT 24 Jun 26 04:50:11 PM PDT 24 24859199995 ps
T308 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3459723511 Jun 26 04:44:19 PM PDT 24 Jun 26 04:44:59 PM PDT 24 2702870575 ps
T309 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1243169266 Jun 26 04:44:28 PM PDT 24 Jun 26 04:45:10 PM PDT 24 2018566230 ps
T310 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.433819229 Jun 26 04:44:20 PM PDT 24 Jun 26 04:45:10 PM PDT 24 1194601610 ps
T311 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1562230574 Jun 26 04:45:02 PM PDT 24 Jun 26 04:45:52 PM PDT 24 5275831534 ps
T312 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1671970567 Jun 26 04:44:42 PM PDT 24 Jun 26 04:46:01 PM PDT 24 5353930353 ps
T313 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3202859024 Jun 26 04:44:26 PM PDT 24 Jun 26 04:52:14 PM PDT 24 158971642077 ps
T314 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2356791511 Jun 26 04:45:14 PM PDT 24 Jun 26 04:46:09 PM PDT 24 3902777476 ps
T315 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1702761151 Jun 26 04:44:24 PM PDT 24 Jun 26 04:57:30 PM PDT 24 86703158057 ps
T316 /workspace/coverage/default/29.rom_ctrl_alert_test.2275098676 Jun 26 04:44:42 PM PDT 24 Jun 26 04:45:43 PM PDT 24 3887521490 ps
T317 /workspace/coverage/default/30.rom_ctrl_stress_all.1469478275 Jun 26 04:44:46 PM PDT 24 Jun 26 04:46:05 PM PDT 24 4318678817 ps
T318 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.68588397 Jun 26 04:44:43 PM PDT 24 Jun 26 04:46:19 PM PDT 24 9369695112 ps
T319 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3124446912 Jun 26 04:44:21 PM PDT 24 Jun 26 04:45:27 PM PDT 24 7858693037 ps
T320 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.277377164 Jun 26 04:45:11 PM PDT 24 Jun 26 04:46:05 PM PDT 24 13600024223 ps
T321 /workspace/coverage/default/11.rom_ctrl_stress_all.487448857 Jun 26 04:44:32 PM PDT 24 Jun 26 04:46:11 PM PDT 24 1271557205 ps
T322 /workspace/coverage/default/32.rom_ctrl_stress_all.1780939070 Jun 26 04:44:58 PM PDT 24 Jun 26 04:46:15 PM PDT 24 894083911 ps
T323 /workspace/coverage/default/42.rom_ctrl_alert_test.3041099919 Jun 26 04:44:58 PM PDT 24 Jun 26 04:45:34 PM PDT 24 603216222 ps
T324 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3770752775 Jun 26 04:45:02 PM PDT 24 Jun 26 04:48:55 PM PDT 24 3246426319 ps
T325 /workspace/coverage/default/8.rom_ctrl_smoke.487490437 Jun 26 04:44:16 PM PDT 24 Jun 26 04:44:57 PM PDT 24 3064740039 ps
T326 /workspace/coverage/default/17.rom_ctrl_alert_test.3850879373 Jun 26 04:44:30 PM PDT 24 Jun 26 04:45:28 PM PDT 24 18898624114 ps
T327 /workspace/coverage/default/41.rom_ctrl_stress_all.3346316551 Jun 26 04:45:02 PM PDT 24 Jun 26 04:45:45 PM PDT 24 2409391185 ps
T328 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.334537333 Jun 26 04:44:29 PM PDT 24 Jun 26 04:45:13 PM PDT 24 956686664 ps
T329 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2156532303 Jun 26 04:44:41 PM PDT 24 Jun 26 04:45:22 PM PDT 24 186581957 ps
T330 /workspace/coverage/default/17.rom_ctrl_smoke.4235262884 Jun 26 04:44:43 PM PDT 24 Jun 26 04:45:48 PM PDT 24 4972173630 ps
T331 /workspace/coverage/default/38.rom_ctrl_smoke.801173518 Jun 26 04:45:06 PM PDT 24 Jun 26 04:46:11 PM PDT 24 3956060847 ps
T332 /workspace/coverage/default/21.rom_ctrl_smoke.1383901849 Jun 26 04:44:29 PM PDT 24 Jun 26 04:46:03 PM PDT 24 11907641804 ps
T333 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1028563910 Jun 26 04:44:24 PM PDT 24 Jun 26 04:44:59 PM PDT 24 729805594 ps
T334 /workspace/coverage/default/12.rom_ctrl_smoke.613342741 Jun 26 04:44:37 PM PDT 24 Jun 26 04:45:26 PM PDT 24 4884083887 ps
T45 /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1646874933 Jun 26 04:45:02 PM PDT 24 Jun 26 05:15:55 PM PDT 24 95957118103 ps
T46 /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.297321232 Jun 26 04:44:34 PM PDT 24 Jun 26 04:55:08 PM PDT 24 58722511553 ps
T335 /workspace/coverage/default/6.rom_ctrl_alert_test.2028060996 Jun 26 04:44:19 PM PDT 24 Jun 26 04:44:50 PM PDT 24 787100561 ps
T336 /workspace/coverage/default/18.rom_ctrl_stress_all.3054297824 Jun 26 04:44:39 PM PDT 24 Jun 26 04:45:24 PM PDT 24 1203056509 ps
T337 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3044340984 Jun 26 04:44:14 PM PDT 24 Jun 26 04:45:32 PM PDT 24 7197352855 ps
T338 /workspace/coverage/default/26.rom_ctrl_stress_all.2782157802 Jun 26 04:44:49 PM PDT 24 Jun 26 04:45:52 PM PDT 24 13040865025 ps
T339 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.232487803 Jun 26 04:44:17 PM PDT 24 Jun 26 04:45:17 PM PDT 24 12667561424 ps
T340 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3472437103 Jun 26 04:44:47 PM PDT 24 Jun 26 04:45:53 PM PDT 24 3071556026 ps
T341 /workspace/coverage/default/23.rom_ctrl_alert_test.2484005986 Jun 26 04:44:40 PM PDT 24 Jun 26 04:45:33 PM PDT 24 2466550689 ps
T342 /workspace/coverage/default/43.rom_ctrl_stress_all.3691644117 Jun 26 04:45:06 PM PDT 24 Jun 26 04:45:57 PM PDT 24 2125650414 ps
T343 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.817470345 Jun 26 04:44:35 PM PDT 24 Jun 26 04:45:30 PM PDT 24 10403830233 ps
T344 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2323371553 Jun 26 04:44:30 PM PDT 24 Jun 26 04:49:35 PM PDT 24 11178109633 ps
T345 /workspace/coverage/default/15.rom_ctrl_alert_test.1826754183 Jun 26 04:44:32 PM PDT 24 Jun 26 04:45:13 PM PDT 24 838884543 ps
T346 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3289323346 Jun 26 04:44:55 PM PDT 24 Jun 26 04:46:05 PM PDT 24 4619852631 ps
T347 /workspace/coverage/default/43.rom_ctrl_smoke.773062052 Jun 26 04:45:00 PM PDT 24 Jun 26 04:46:26 PM PDT 24 16101726680 ps
T348 /workspace/coverage/default/13.rom_ctrl_stress_all.1218520138 Jun 26 04:44:32 PM PDT 24 Jun 26 04:45:39 PM PDT 24 559565987 ps
T349 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2967003168 Jun 26 04:44:29 PM PDT 24 Jun 26 04:46:02 PM PDT 24 30772163290 ps
T350 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.562579580 Jun 26 04:44:39 PM PDT 24 Jun 26 04:57:17 PM PDT 24 962444200229 ps
T351 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4056793638 Jun 26 04:44:27 PM PDT 24 Jun 26 04:45:13 PM PDT 24 4118697490 ps
T55 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.489665827 Jun 26 04:45:37 PM PDT 24 Jun 26 04:45:52 PM PDT 24 1333125792 ps
T56 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.567322883 Jun 26 04:46:03 PM PDT 24 Jun 26 04:46:31 PM PDT 24 12353044436 ps
T47 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.361798277 Jun 26 04:46:02 PM PDT 24 Jun 26 04:46:16 PM PDT 24 176333467 ps
T52 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4230334246 Jun 26 04:46:11 PM PDT 24 Jun 26 04:47:44 PM PDT 24 3199571255 ps
T352 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4163194145 Jun 26 04:45:31 PM PDT 24 Jun 26 04:45:56 PM PDT 24 6539474196 ps
T88 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3437057563 Jun 26 04:45:49 PM PDT 24 Jun 26 04:46:21 PM PDT 24 3914014038 ps
T89 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4253292469 Jun 26 04:45:51 PM PDT 24 Jun 26 04:47:41 PM PDT 24 12499513936 ps
T53 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2970504606 Jun 26 04:46:03 PM PDT 24 Jun 26 04:48:40 PM PDT 24 356689692 ps
T353 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1955022411 Jun 26 04:45:42 PM PDT 24 Jun 26 04:46:03 PM PDT 24 32688833603 ps
T354 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2054357836 Jun 26 04:45:49 PM PDT 24 Jun 26 04:46:21 PM PDT 24 6402628852 ps
T355 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3946781584 Jun 26 04:45:40 PM PDT 24 Jun 26 04:46:03 PM PDT 24 2221096351 ps
T83 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3467690245 Jun 26 04:45:24 PM PDT 24 Jun 26 04:46:02 PM PDT 24 4371174811 ps
T356 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2050280836 Jun 26 04:45:43 PM PDT 24 Jun 26 04:45:55 PM PDT 24 688466842 ps
T59 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1194239745 Jun 26 04:45:49 PM PDT 24 Jun 26 04:46:45 PM PDT 24 4691886283 ps
T54 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3891183350 Jun 26 04:45:43 PM PDT 24 Jun 26 04:47:12 PM PDT 24 4220080345 ps
T357 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3334808967 Jun 26 04:45:54 PM PDT 24 Jun 26 04:46:26 PM PDT 24 17559225158 ps
T90 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3585855194 Jun 26 04:46:03 PM PDT 24 Jun 26 04:48:44 PM PDT 24 406372565 ps
T358 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.637449893 Jun 26 04:46:11 PM PDT 24 Jun 26 04:46:45 PM PDT 24 3733500825 ps
T60 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3488695781 Jun 26 04:46:11 PM PDT 24 Jun 26 04:47:10 PM PDT 24 1054339597 ps
T61 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2471331162 Jun 26 04:45:19 PM PDT 24 Jun 26 04:46:52 PM PDT 24 14722353748 ps
T62 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3856486754 Jun 26 04:45:55 PM PDT 24 Jun 26 04:46:30 PM PDT 24 4795222843 ps
T359 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2466981144 Jun 26 04:46:00 PM PDT 24 Jun 26 04:46:35 PM PDT 24 3574319667 ps
T63 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.355269516 Jun 26 04:45:29 PM PDT 24 Jun 26 04:45:52 PM PDT 24 2501657245 ps
T360 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3537273111 Jun 26 04:45:40 PM PDT 24 Jun 26 04:46:07 PM PDT 24 16801345304 ps
T361 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3623357481 Jun 26 04:46:00 PM PDT 24 Jun 26 04:46:16 PM PDT 24 2403848453 ps
T84 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3415174944 Jun 26 04:46:11 PM PDT 24 Jun 26 04:46:43 PM PDT 24 4078997385 ps
T97 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2513507320 Jun 26 04:45:54 PM PDT 24 Jun 26 04:47:25 PM PDT 24 1190667681 ps
T362 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3667261797 Jun 26 04:45:55 PM PDT 24 Jun 26 04:46:06 PM PDT 24 363628415 ps
T64 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2650244872 Jun 26 04:45:40 PM PDT 24 Jun 26 04:48:47 PM PDT 24 87987705728 ps
T65 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.627544948 Jun 26 04:45:57 PM PDT 24 Jun 26 04:48:38 PM PDT 24 16684081428 ps
T363 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2424970580 Jun 26 04:45:43 PM PDT 24 Jun 26 04:47:12 PM PDT 24 5295594833 ps
T364 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.996210665 Jun 26 04:45:54 PM PDT 24 Jun 26 04:46:14 PM PDT 24 4109143568 ps
T365 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2669225236 Jun 26 04:46:09 PM PDT 24 Jun 26 04:46:23 PM PDT 24 174403447 ps
T366 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3400477546 Jun 26 04:45:36 PM PDT 24 Jun 26 04:46:03 PM PDT 24 9921985417 ps
T66 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.674670930 Jun 26 04:46:10 PM PDT 24 Jun 26 04:47:08 PM PDT 24 1050567207 ps
T367 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.711362012 Jun 26 04:45:30 PM PDT 24 Jun 26 04:46:00 PM PDT 24 12354680934 ps
T368 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2988466763 Jun 26 04:45:18 PM PDT 24 Jun 26 04:45:36 PM PDT 24 345524269 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1131559887 Jun 26 04:45:23 PM PDT 24 Jun 26 04:45:56 PM PDT 24 3159639351 ps
T67 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.54048054 Jun 26 04:45:46 PM PDT 24 Jun 26 04:45:56 PM PDT 24 338718152 ps
T370 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.495597025 Jun 26 04:46:02 PM PDT 24 Jun 26 04:46:12 PM PDT 24 744075183 ps
T85 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4155626715 Jun 26 04:45:37 PM PDT 24 Jun 26 04:45:47 PM PDT 24 170805085 ps
T75 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1951743880 Jun 26 04:46:09 PM PDT 24 Jun 26 04:46:41 PM PDT 24 4326890030 ps
T76 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.677768836 Jun 26 04:45:46 PM PDT 24 Jun 26 04:46:16 PM PDT 24 13419633016 ps
T77 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3354020114 Jun 26 04:45:44 PM PDT 24 Jun 26 04:48:56 PM PDT 24 100613895826 ps
T86 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3564713756 Jun 26 04:46:12 PM PDT 24 Jun 26 04:46:38 PM PDT 24 10783595936 ps
T371 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1435646548 Jun 26 04:46:10 PM PDT 24 Jun 26 04:46:39 PM PDT 24 36943510153 ps
T372 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1472270783 Jun 26 04:45:44 PM PDT 24 Jun 26 04:46:03 PM PDT 24 6286579362 ps
T373 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1409704755 Jun 26 04:46:00 PM PDT 24 Jun 26 04:46:22 PM PDT 24 3700797163 ps
T87 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1258308639 Jun 26 04:46:03 PM PDT 24 Jun 26 04:46:26 PM PDT 24 2234345269 ps
T93 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2187702156 Jun 26 04:45:57 PM PDT 24 Jun 26 04:47:29 PM PDT 24 3590199455 ps
T374 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3228506541 Jun 26 04:46:13 PM PDT 24 Jun 26 04:46:34 PM PDT 24 7536510559 ps
T375 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1922275475 Jun 26 04:45:51 PM PDT 24 Jun 26 04:46:06 PM PDT 24 172548302 ps
T376 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.331000316 Jun 26 04:45:46 PM PDT 24 Jun 26 04:46:07 PM PDT 24 8193692957 ps
T377 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4056427070 Jun 26 04:46:02 PM PDT 24 Jun 26 04:46:29 PM PDT 24 11573563451 ps
T378 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.510077095 Jun 26 04:46:03 PM PDT 24 Jun 26 04:46:25 PM PDT 24 4942542224 ps
T98 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2496199844 Jun 26 04:45:49 PM PDT 24 Jun 26 04:48:35 PM PDT 24 4238461950 ps
T379 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1926499277 Jun 26 04:45:43 PM PDT 24 Jun 26 04:46:19 PM PDT 24 8678540310 ps
T380 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2008675519 Jun 26 04:46:02 PM PDT 24 Jun 26 04:46:21 PM PDT 24 1480715118 ps
T381 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.613158978 Jun 26 04:45:36 PM PDT 24 Jun 26 04:46:09 PM PDT 24 4376285781 ps
T382 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1702729669 Jun 26 04:46:11 PM PDT 24 Jun 26 04:46:32 PM PDT 24 1814591079 ps
T383 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3031278925 Jun 26 04:45:31 PM PDT 24 Jun 26 04:45:45 PM PDT 24 762957696 ps
T384 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2455968536 Jun 26 04:46:11 PM PDT 24 Jun 26 04:48:54 PM PDT 24 5725123664 ps
T385 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.998138203 Jun 26 04:45:34 PM PDT 24 Jun 26 04:46:07 PM PDT 24 4187091636 ps
T386 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1685558849 Jun 26 04:45:16 PM PDT 24 Jun 26 04:45:49 PM PDT 24 2393849294 ps
T94 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2756453191 Jun 26 04:46:10 PM PDT 24 Jun 26 04:48:50 PM PDT 24 390520439 ps
T387 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1524985056 Jun 26 04:46:10 PM PDT 24 Jun 26 04:46:32 PM PDT 24 4034862982 ps
T388 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1317984712 Jun 26 04:45:40 PM PDT 24 Jun 26 04:45:50 PM PDT 24 360960192 ps
T389 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.420253440 Jun 26 04:45:49 PM PDT 24 Jun 26 04:46:10 PM PDT 24 7493619513 ps
T390 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.555727530 Jun 26 04:45:18 PM PDT 24 Jun 26 04:45:45 PM PDT 24 13907503103 ps
T391 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1204014359 Jun 26 04:45:46 PM PDT 24 Jun 26 04:46:19 PM PDT 24 16315953239 ps
T392 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2406555767 Jun 26 04:45:27 PM PDT 24 Jun 26 04:47:49 PM PDT 24 34878233952 ps
T393 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.543443836 Jun 26 04:46:04 PM PDT 24 Jun 26 04:46:31 PM PDT 24 11164052549 ps
T394 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3056302513 Jun 26 04:46:09 PM PDT 24 Jun 26 04:46:25 PM PDT 24 3926288013 ps
T395 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.463187602 Jun 26 04:45:44 PM PDT 24 Jun 26 04:45:53 PM PDT 24 688464073 ps
T396 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2885892497 Jun 26 04:45:15 PM PDT 24 Jun 26 04:45:58 PM PDT 24 3068335023 ps
T397 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3197158113 Jun 26 04:45:24 PM PDT 24 Jun 26 04:45:59 PM PDT 24 11639967819 ps
T398 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2981494724 Jun 26 04:45:56 PM PDT 24 Jun 26 04:46:14 PM PDT 24 827854012 ps
T399 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1095144095 Jun 26 04:45:52 PM PDT 24 Jun 26 04:46:01 PM PDT 24 661457303 ps
T400 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1743877103 Jun 26 04:46:04 PM PDT 24 Jun 26 04:46:14 PM PDT 24 688674884 ps
T401 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.628493621 Jun 26 04:46:10 PM PDT 24 Jun 26 04:46:19 PM PDT 24 660894274 ps
T402 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3457082497 Jun 26 04:45:16 PM PDT 24 Jun 26 04:45:39 PM PDT 24 513847274 ps
T403 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1129557335 Jun 26 04:46:10 PM PDT 24 Jun 26 04:46:32 PM PDT 24 1825230068 ps
T404 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3444079406 Jun 26 04:45:55 PM PDT 24 Jun 26 04:46:17 PM PDT 24 21056734605 ps
T405 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2240490725 Jun 26 04:45:17 PM PDT 24 Jun 26 04:45:50 PM PDT 24 12162200159 ps
T406 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2270105141 Jun 26 04:45:37 PM PDT 24 Jun 26 04:46:36 PM PDT 24 2169052647 ps
T407 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.831761353 Jun 26 04:46:27 PM PDT 24 Jun 26 04:47:01 PM PDT 24 6419090291 ps
T95 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1177396105 Jun 26 04:45:38 PM PDT 24 Jun 26 04:47:06 PM PDT 24 483437033 ps
T82 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.422591398 Jun 26 04:45:49 PM PDT 24 Jun 26 04:47:42 PM PDT 24 11846301617 ps
T408 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.665725745 Jun 26 04:45:52 PM PDT 24 Jun 26 04:46:18 PM PDT 24 4253702741 ps
T409 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.853623369 Jun 26 04:45:56 PM PDT 24 Jun 26 04:46:07 PM PDT 24 917843240 ps
T410 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.871614133 Jun 26 04:45:30 PM PDT 24 Jun 26 04:45:56 PM PDT 24 2959588220 ps
T411 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3679933271 Jun 26 04:46:02 PM PDT 24 Jun 26 04:46:16 PM PDT 24 354422896 ps
T78 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3738772979 Jun 26 04:46:03 PM PDT 24 Jun 26 04:48:49 PM PDT 24 90831331371 ps
T412 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2480866496 Jun 26 04:45:43 PM PDT 24 Jun 26 04:46:19 PM PDT 24 8216464925 ps
T96 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.872729620 Jun 26 04:46:01 PM PDT 24 Jun 26 04:48:44 PM PDT 24 5969290892 ps
T413 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.378984061 Jun 26 04:46:00 PM PDT 24 Jun 26 04:47:49 PM PDT 24 12303707484 ps
T414 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2836836300 Jun 26 04:45:56 PM PDT 24 Jun 26 04:46:36 PM PDT 24 1429302157 ps
T91 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.966516777 Jun 26 04:46:03 PM PDT 24 Jun 26 04:48:59 PM PDT 24 7762747565 ps
T415 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.397074090 Jun 26 04:45:58 PM PDT 24 Jun 26 04:46:22 PM PDT 24 23646196389 ps
T416 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4032734712 Jun 26 04:45:49 PM PDT 24 Jun 26 04:46:22 PM PDT 24 17109547548 ps
T417 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4006972718 Jun 26 04:45:57 PM PDT 24 Jun 26 04:46:23 PM PDT 24 2895918890 ps
T418 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1471127644 Jun 26 04:46:10 PM PDT 24 Jun 26 04:46:21 PM PDT 24 187543748 ps
T419 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3077713535 Jun 26 04:45:36 PM PDT 24 Jun 26 04:45:49 PM PDT 24 2388086864 ps
T420 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2016447515 Jun 26 04:46:10 PM PDT 24 Jun 26 04:46:28 PM PDT 24 429383906 ps
T421 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3206553869 Jun 26 04:45:52 PM PDT 24 Jun 26 04:46:06 PM PDT 24 596433582 ps
T422 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.353608945 Jun 26 04:46:11 PM PDT 24 Jun 26 04:48:17 PM PDT 24 29386330681 ps
T423 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1472386616 Jun 26 04:45:56 PM PDT 24 Jun 26 04:47:34 PM PDT 24 10873048264 ps
T424 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1508258247 Jun 26 04:46:13 PM PDT 24 Jun 26 04:46:46 PM PDT 24 7415937613 ps
T92 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.596626767 Jun 26 04:46:08 PM PDT 24 Jun 26 04:49:03 PM PDT 24 3837785691 ps
T425 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3624749364 Jun 26 04:45:29 PM PDT 24 Jun 26 04:45:52 PM PDT 24 3622214866 ps
T79 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1718305101 Jun 26 04:46:03 PM PDT 24 Jun 26 04:47:01 PM PDT 24 2156264494 ps
T426 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2508478674 Jun 26 04:46:08 PM PDT 24 Jun 26 04:48:44 PM PDT 24 60259699916 ps
T427 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1863838906 Jun 26 04:45:57 PM PDT 24 Jun 26 04:46:22 PM PDT 24 15457314967 ps
T428 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.690376017 Jun 26 04:45:18 PM PDT 24 Jun 26 04:45:47 PM PDT 24 2176654446 ps
T100 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3742535885 Jun 26 04:45:51 PM PDT 24 Jun 26 04:47:32 PM PDT 24 30462358794 ps
T429 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1565164164 Jun 26 04:46:09 PM PDT 24 Jun 26 04:46:39 PM PDT 24 4669045277 ps
T430 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.372161071 Jun 26 04:45:43 PM PDT 24 Jun 26 04:46:13 PM PDT 24 14412212143 ps
T81 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3101728249 Jun 26 04:46:11 PM PDT 24 Jun 26 04:46:21 PM PDT 24 174346892 ps
T431 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.211373878 Jun 26 04:45:56 PM PDT 24 Jun 26 04:46:32 PM PDT 24 17219922176 ps
T432 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4188621752 Jun 26 04:46:00 PM PDT 24 Jun 26 04:46:29 PM PDT 24 12166273605 ps
T433 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4055341741 Jun 26 04:45:51 PM PDT 24 Jun 26 04:46:01 PM PDT 24 460693087 ps
T434 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2371734118 Jun 26 04:46:12 PM PDT 24 Jun 26 04:47:52 PM PDT 24 12331174041 ps
T435 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1357785354 Jun 26 04:46:03 PM PDT 24 Jun 26 04:46:13 PM PDT 24 611854178 ps
T436 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3108526125 Jun 26 04:45:50 PM PDT 24 Jun 26 04:46:16 PM PDT 24 22140461219 ps
T437 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2721767552 Jun 26 04:46:12 PM PDT 24 Jun 26 04:46:32 PM PDT 24 1155777944 ps
T438 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2057460711 Jun 26 04:46:00 PM PDT 24 Jun 26 04:48:19 PM PDT 24 17294541943 ps
T439 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3722924057 Jun 26 04:45:38 PM PDT 24 Jun 26 04:46:01 PM PDT 24 11455906386 ps
T440 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2644349937 Jun 26 04:45:46 PM PDT 24 Jun 26 04:46:19 PM PDT 24 40188548025 ps
T441 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2667221372 Jun 26 04:45:56 PM PDT 24 Jun 26 04:46:24 PM PDT 24 13013196202 ps
T442 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1468449234 Jun 26 04:45:41 PM PDT 24 Jun 26 04:46:09 PM PDT 24 3358260766 ps
T101 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.918202707 Jun 26 04:45:25 PM PDT 24 Jun 26 04:47:07 PM PDT 24 12401248685 ps
T443 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2603663718 Jun 26 04:46:09 PM PDT 24 Jun 26 04:46:21 PM PDT 24 332005185 ps
T444 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.734631991 Jun 26 04:45:49 PM PDT 24 Jun 26 04:46:23 PM PDT 24 18362557216 ps
T445 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2025487350 Jun 26 04:45:46 PM PDT 24 Jun 26 04:46:22 PM PDT 24 3774752470 ps
T446 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1025292550 Jun 26 04:45:19 PM PDT 24 Jun 26 04:47:09 PM PDT 24 4099940479 ps
T99 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3872334871 Jun 26 04:46:09 PM PDT 24 Jun 26 04:48:48 PM PDT 24 5113605065 ps
T447 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.866073277 Jun 26 04:46:10 PM PDT 24 Jun 26 04:46:42 PM PDT 24 13311689637 ps
T448 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1501226493 Jun 26 04:46:03 PM PDT 24 Jun 26 04:46:41 PM PDT 24 7721046246 ps
T449 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3406377487 Jun 26 04:45:49 PM PDT 24 Jun 26 04:46:28 PM PDT 24 25216947524 ps
T450 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1901261518 Jun 26 04:46:11 PM PDT 24 Jun 26 04:46:41 PM PDT 24 3270879450 ps
T80 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1770795299 Jun 26 04:46:01 PM PDT 24 Jun 26 04:46:15 PM PDT 24 496573464 ps
T451 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3027623591 Jun 26 04:46:08 PM PDT 24 Jun 26 04:47:49 PM PDT 24 20300212029 ps
T452 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.602382003 Jun 26 04:45:49 PM PDT 24 Jun 26 04:46:00 PM PDT 24 168974135 ps
T453 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3896035922 Jun 26 04:45:56 PM PDT 24 Jun 26 04:46:35 PM PDT 24 706403904 ps
T454 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4131058034 Jun 26 04:46:10 PM PDT 24 Jun 26 04:46:46 PM PDT 24 22106720163 ps

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.234457209
Short name T4
Test name
Test status
Simulation time 39457438645 ps
CPU time 505.18 seconds
Started Jun 26 04:44:30 PM PDT 24
Finished Jun 26 04:53:24 PM PDT 24
Peak memory 242256 kb
Host smart-790a7606-52c1-454e-868c-dedb6afe3671
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234457209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.234457209
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.291056198
Short name T13
Test name
Test status
Simulation time 16747131104 ps
CPU time 873.43 seconds
Started Jun 26 04:44:56 PM PDT 24
Finished Jun 26 04:59:54 PM PDT 24
Peak memory 227592 kb
Host smart-7b84df0d-a2a4-4d4b-928a-dbd7218a0d98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291056198 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.291056198
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3456377392
Short name T201
Test name
Test status
Simulation time 28146051161 ps
CPU time 600.9 seconds
Started Jun 26 04:44:49 PM PDT 24
Finished Jun 26 04:55:18 PM PDT 24
Peak memory 239636 kb
Host smart-5cbe58c9-3269-4e46-aa50-b8af94a6c82c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456377392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3456377392
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3585855194
Short name T90
Test name
Test status
Simulation time 406372565 ps
CPU time 158.96 seconds
Started Jun 26 04:46:03 PM PDT 24
Finished Jun 26 04:48:44 PM PDT 24
Peak memory 214060 kb
Host smart-f668fa01-9380-4419-9381-5f02697b1bd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585855194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3585855194
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1983280619
Short name T16
Test name
Test status
Simulation time 34065943999 ps
CPU time 124.14 seconds
Started Jun 26 04:45:08 PM PDT 24
Finished Jun 26 04:47:29 PM PDT 24
Peak memory 219852 kb
Host smart-ffb19c2f-e946-48e9-b6a5-1c6e8fb1c90f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983280619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1983280619
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3931550069
Short name T21
Test name
Test status
Simulation time 815389279 ps
CPU time 228.8 seconds
Started Jun 26 04:44:11 PM PDT 24
Finished Jun 26 04:48:17 PM PDT 24
Peak memory 234716 kb
Host smart-7560626c-ea31-4441-abb3-0d57f00019ee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931550069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3931550069
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1194239745
Short name T59
Test name
Test status
Simulation time 4691886283 ps
CPU time 55.39 seconds
Started Jun 26 04:45:49 PM PDT 24
Finished Jun 26 04:46:45 PM PDT 24
Peak memory 215596 kb
Host smart-ac1842a9-edd7-4ad8-9f38-33a409320cbb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194239745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1194239745
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.596626767
Short name T92
Test name
Test status
Simulation time 3837785691 ps
CPU time 173.78 seconds
Started Jun 26 04:46:08 PM PDT 24
Finished Jun 26 04:49:03 PM PDT 24
Peak memory 214068 kb
Host smart-29341442-5920-4f8e-89f0-c6c9619674d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596626767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.596626767
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1634610305
Short name T7
Test name
Test status
Simulation time 2870704006 ps
CPU time 12.9 seconds
Started Jun 26 04:44:12 PM PDT 24
Finished Jun 26 04:44:44 PM PDT 24
Peak memory 217132 kb
Host smart-7d4f04ed-e5ae-44e3-b48d-a8dd4b0d04a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634610305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1634610305
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2392767711
Short name T6
Test name
Test status
Simulation time 28037291911 ps
CPU time 321.04 seconds
Started Jun 26 04:44:11 PM PDT 24
Finished Jun 26 04:49:51 PM PDT 24
Peak memory 219464 kb
Host smart-43fc9955-7b3e-4e99-bee6-38e75245a381
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392767711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2392767711
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3738772979
Short name T78
Test name
Test status
Simulation time 90831331371 ps
CPU time 164.08 seconds
Started Jun 26 04:46:03 PM PDT 24
Finished Jun 26 04:48:49 PM PDT 24
Peak memory 215160 kb
Host smart-8a1b266e-91bc-4c9b-976f-ab4bc36612ca
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738772979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3738772979
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.4181990065
Short name T135
Test name
Test status
Simulation time 17127162544 ps
CPU time 71.09 seconds
Started Jun 26 04:44:11 PM PDT 24
Finished Jun 26 04:45:41 PM PDT 24
Peak memory 219300 kb
Host smart-4c1bf4d2-c282-4d8a-8a4a-867cf2a4c584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181990065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.4181990065
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4056793638
Short name T351
Test name
Test status
Simulation time 4118697490 ps
CPU time 19.23 seconds
Started Jun 26 04:44:27 PM PDT 24
Finished Jun 26 04:45:13 PM PDT 24
Peak memory 219296 kb
Host smart-d470d92f-3cfb-4f4a-954f-fd024a9737e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056793638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.4056793638
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.918202707
Short name T101
Test name
Test status
Simulation time 12401248685 ps
CPU time 97.47 seconds
Started Jun 26 04:45:25 PM PDT 24
Finished Jun 26 04:47:07 PM PDT 24
Peak memory 213756 kb
Host smart-c56481c5-ffa9-4d4c-b09c-33175bc7b584
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918202707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.918202707
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.966516777
Short name T91
Test name
Test status
Simulation time 7762747565 ps
CPU time 173.98 seconds
Started Jun 26 04:46:03 PM PDT 24
Finished Jun 26 04:48:59 PM PDT 24
Peak memory 214244 kb
Host smart-c46e6f5f-5240-4ebc-b1c9-d9b6c4db8786
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966516777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.966516777
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.4090482861
Short name T118
Test name
Test status
Simulation time 35216304831 ps
CPU time 29.37 seconds
Started Jun 26 04:44:30 PM PDT 24
Finished Jun 26 04:45:28 PM PDT 24
Peak memory 219316 kb
Host smart-02fdbd21-4410-425f-9bf5-53e005891a98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4090482861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.4090482861
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1284959990
Short name T18
Test name
Test status
Simulation time 140909462948 ps
CPU time 856.47 seconds
Started Jun 26 04:44:50 PM PDT 24
Finished Jun 26 04:59:34 PM PDT 24
Peak memory 235820 kb
Host smart-6f2baf30-e1ac-464b-b282-2b63349bf413
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284959990 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1284959990
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1685558849
Short name T386
Test name
Test status
Simulation time 2393849294 ps
CPU time 22 seconds
Started Jun 26 04:45:16 PM PDT 24
Finished Jun 26 04:45:49 PM PDT 24
Peak memory 211340 kb
Host smart-e8fe23e4-8832-45be-bb0a-04b4797f2f5d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685558849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1685558849
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2988466763
Short name T368
Test name
Test status
Simulation time 345524269 ps
CPU time 8.28 seconds
Started Jun 26 04:45:18 PM PDT 24
Finished Jun 26 04:45:36 PM PDT 24
Peak memory 210700 kb
Host smart-00f440d3-2ee0-4924-a8bd-8dc692f93065
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988466763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2988466763
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.690376017
Short name T428
Test name
Test status
Simulation time 2176654446 ps
CPU time 18.98 seconds
Started Jun 26 04:45:18 PM PDT 24
Finished Jun 26 04:45:47 PM PDT 24
Peak memory 211548 kb
Host smart-548dc561-6e55-4ed3-8e26-96e16c56f2fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690376017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.690376017
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1131559887
Short name T369
Test name
Test status
Simulation time 3159639351 ps
CPU time 26.88 seconds
Started Jun 26 04:45:23 PM PDT 24
Finished Jun 26 04:45:56 PM PDT 24
Peak memory 218420 kb
Host smart-a407e9ae-76d4-48d9-9b3d-18d4a71d4997
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131559887 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1131559887
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3457082497
Short name T402
Test name
Test status
Simulation time 513847274 ps
CPU time 11.76 seconds
Started Jun 26 04:45:16 PM PDT 24
Finished Jun 26 04:45:39 PM PDT 24
Peak memory 210616 kb
Host smart-4a0aaf06-60bd-4e7e-bb07-74062b30ca07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457082497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3457082497
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.555727530
Short name T390
Test name
Test status
Simulation time 13907503103 ps
CPU time 17.27 seconds
Started Jun 26 04:45:18 PM PDT 24
Finished Jun 26 04:45:45 PM PDT 24
Peak memory 210632 kb
Host smart-445a170b-10be-403d-9698-0471a99d96a0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555727530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.555727530
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2240490725
Short name T405
Test name
Test status
Simulation time 12162200159 ps
CPU time 22.17 seconds
Started Jun 26 04:45:17 PM PDT 24
Finished Jun 26 04:45:50 PM PDT 24
Peak memory 210728 kb
Host smart-778d3b34-601d-4133-87e0-0baef87f3f3e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240490725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2240490725
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2471331162
Short name T61
Test name
Test status
Simulation time 14722353748 ps
CPU time 83.55 seconds
Started Jun 26 04:45:19 PM PDT 24
Finished Jun 26 04:46:52 PM PDT 24
Peak memory 214868 kb
Host smart-45580dda-50fa-4c6a-885d-4ff6e85f2511
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471331162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2471331162
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3467690245
Short name T83
Test name
Test status
Simulation time 4371174811 ps
CPU time 33.07 seconds
Started Jun 26 04:45:24 PM PDT 24
Finished Jun 26 04:46:02 PM PDT 24
Peak memory 212328 kb
Host smart-6d1228fb-49d2-42f8-93ed-fd84405731c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467690245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3467690245
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2885892497
Short name T396
Test name
Test status
Simulation time 3068335023 ps
CPU time 31.31 seconds
Started Jun 26 04:45:15 PM PDT 24
Finished Jun 26 04:45:58 PM PDT 24
Peak memory 218536 kb
Host smart-2a740b75-3ee6-47b8-acbb-6c01e31cba64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885892497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2885892497
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1025292550
Short name T446
Test name
Test status
Simulation time 4099940479 ps
CPU time 100.79 seconds
Started Jun 26 04:45:19 PM PDT 24
Finished Jun 26 04:47:09 PM PDT 24
Peak memory 212556 kb
Host smart-54f30545-f19f-4498-a183-e3467e3c689b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025292550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1025292550
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.871614133
Short name T410
Test name
Test status
Simulation time 2959588220 ps
CPU time 24.46 seconds
Started Jun 26 04:45:30 PM PDT 24
Finished Jun 26 04:45:56 PM PDT 24
Peak memory 211852 kb
Host smart-5287a9a4-5a06-43c6-b3fe-868c884cd599
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871614133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.871614133
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4163194145
Short name T352
Test name
Test status
Simulation time 6539474196 ps
CPU time 23.53 seconds
Started Jun 26 04:45:31 PM PDT 24
Finished Jun 26 04:45:56 PM PDT 24
Peak memory 210680 kb
Host smart-1b4db1c0-e7bd-48e5-a01b-9b5816d1d8d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163194145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4163194145
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.355269516
Short name T63
Test name
Test status
Simulation time 2501657245 ps
CPU time 21.63 seconds
Started Jun 26 04:45:29 PM PDT 24
Finished Jun 26 04:45:52 PM PDT 24
Peak memory 211900 kb
Host smart-f98bf926-5eac-427f-9f58-e96865cd7999
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355269516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.355269516
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3624749364
Short name T425
Test name
Test status
Simulation time 3622214866 ps
CPU time 21.08 seconds
Started Jun 26 04:45:29 PM PDT 24
Finished Jun 26 04:45:52 PM PDT 24
Peak memory 216316 kb
Host smart-7512b052-a427-4a57-b178-80f824232de0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624749364 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3624749364
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.711362012
Short name T367
Test name
Test status
Simulation time 12354680934 ps
CPU time 28.65 seconds
Started Jun 26 04:45:30 PM PDT 24
Finished Jun 26 04:46:00 PM PDT 24
Peak memory 212288 kb
Host smart-70529a1b-4974-48a1-941f-be1186ac5257
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711362012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.711362012
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.613158978
Short name T381
Test name
Test status
Simulation time 4376285781 ps
CPU time 32 seconds
Started Jun 26 04:45:36 PM PDT 24
Finished Jun 26 04:46:09 PM PDT 24
Peak memory 210520 kb
Host smart-6618fb48-1db6-4870-b8db-c7441d2f83cb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613158978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.613158978
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.998138203
Short name T385
Test name
Test status
Simulation time 4187091636 ps
CPU time 32.2 seconds
Started Jun 26 04:45:34 PM PDT 24
Finished Jun 26 04:46:07 PM PDT 24
Peak memory 210544 kb
Host smart-edff0ee0-4f9d-4272-a721-5595b7dd5947
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998138203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
998138203
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2406555767
Short name T392
Test name
Test status
Simulation time 34878233952 ps
CPU time 139.67 seconds
Started Jun 26 04:45:27 PM PDT 24
Finished Jun 26 04:47:49 PM PDT 24
Peak memory 213756 kb
Host smart-7095801b-11fb-46a4-8ba2-3e7555db2170
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406555767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2406555767
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3031278925
Short name T383
Test name
Test status
Simulation time 762957696 ps
CPU time 12.96 seconds
Started Jun 26 04:45:31 PM PDT 24
Finished Jun 26 04:45:45 PM PDT 24
Peak memory 211044 kb
Host smart-7beaa7d1-df00-4f5b-99f9-f2a005099d1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031278925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3031278925
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3197158113
Short name T397
Test name
Test status
Simulation time 11639967819 ps
CPU time 29.56 seconds
Started Jun 26 04:45:24 PM PDT 24
Finished Jun 26 04:45:59 PM PDT 24
Peak memory 218760 kb
Host smart-b994c64d-6f06-4dee-af08-8be36199d671
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197158113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3197158113
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1409704755
Short name T373
Test name
Test status
Simulation time 3700797163 ps
CPU time 19.88 seconds
Started Jun 26 04:46:00 PM PDT 24
Finished Jun 26 04:46:22 PM PDT 24
Peak memory 219056 kb
Host smart-a848a3e0-fb6f-4074-836b-b222d7091ac6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409704755 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1409704755
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1770795299
Short name T80
Test name
Test status
Simulation time 496573464 ps
CPU time 11.81 seconds
Started Jun 26 04:46:01 PM PDT 24
Finished Jun 26 04:46:15 PM PDT 24
Peak memory 210616 kb
Host smart-1bab74ef-9b68-4ecc-aec9-eedb8a3891d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770795299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1770795299
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2836836300
Short name T414
Test name
Test status
Simulation time 1429302157 ps
CPU time 38.32 seconds
Started Jun 26 04:45:56 PM PDT 24
Finished Jun 26 04:46:36 PM PDT 24
Peak memory 213692 kb
Host smart-730f9533-7b5d-4876-8597-349784742a76
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836836300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2836836300
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1743877103
Short name T400
Test name
Test status
Simulation time 688674884 ps
CPU time 8.32 seconds
Started Jun 26 04:46:04 PM PDT 24
Finished Jun 26 04:46:14 PM PDT 24
Peak memory 211104 kb
Host smart-f92ca901-2744-4a9b-ae2d-1044ed36b1c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743877103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1743877103
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.510077095
Short name T378
Test name
Test status
Simulation time 4942542224 ps
CPU time 20.72 seconds
Started Jun 26 04:46:03 PM PDT 24
Finished Jun 26 04:46:25 PM PDT 24
Peak memory 218588 kb
Host smart-e5526e56-65f0-46ee-b284-32b092a1739d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510077095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.510077095
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.495597025
Short name T370
Test name
Test status
Simulation time 744075183 ps
CPU time 8.59 seconds
Started Jun 26 04:46:02 PM PDT 24
Finished Jun 26 04:46:12 PM PDT 24
Peak memory 214824 kb
Host smart-7d7d3956-c68d-4ad2-99e6-3e0db503dc74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495597025 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.495597025
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4056427070
Short name T377
Test name
Test status
Simulation time 11573563451 ps
CPU time 25.18 seconds
Started Jun 26 04:46:02 PM PDT 24
Finished Jun 26 04:46:29 PM PDT 24
Peak memory 212368 kb
Host smart-2941bf4a-1ad6-4211-8004-b5a27601c3b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056427070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.4056427070
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1258308639
Short name T87
Test name
Test status
Simulation time 2234345269 ps
CPU time 21.16 seconds
Started Jun 26 04:46:03 PM PDT 24
Finished Jun 26 04:46:26 PM PDT 24
Peak memory 212248 kb
Host smart-cb4629f7-b05f-48b3-b2d7-16add611f83f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258308639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1258308639
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2466981144
Short name T359
Test name
Test status
Simulation time 3574319667 ps
CPU time 32.55 seconds
Started Jun 26 04:46:00 PM PDT 24
Finished Jun 26 04:46:35 PM PDT 24
Peak memory 218616 kb
Host smart-9d4ebd63-e59f-4d9b-a614-b5208527e08a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466981144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2466981144
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2970504606
Short name T53
Test name
Test status
Simulation time 356689692 ps
CPU time 155.08 seconds
Started Jun 26 04:46:03 PM PDT 24
Finished Jun 26 04:48:40 PM PDT 24
Peak memory 213836 kb
Host smart-67eaa8ef-7c00-49a3-8501-0996543c93c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970504606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2970504606
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4188621752
Short name T432
Test name
Test status
Simulation time 12166273605 ps
CPU time 26.82 seconds
Started Jun 26 04:46:00 PM PDT 24
Finished Jun 26 04:46:29 PM PDT 24
Peak memory 217480 kb
Host smart-f89a87d6-b11e-4e7c-9952-daaa1f5a8f93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188621752 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.4188621752
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2008675519
Short name T380
Test name
Test status
Simulation time 1480715118 ps
CPU time 17.11 seconds
Started Jun 26 04:46:02 PM PDT 24
Finished Jun 26 04:46:21 PM PDT 24
Peak memory 211228 kb
Host smart-796c5b77-de18-4a16-8f06-09e2520c4481
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008675519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2008675519
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.378984061
Short name T413
Test name
Test status
Simulation time 12303707484 ps
CPU time 107.35 seconds
Started Jun 26 04:46:00 PM PDT 24
Finished Jun 26 04:47:49 PM PDT 24
Peak memory 213756 kb
Host smart-2b6cda48-a703-4e64-bbbf-bdfce6c1deae
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378984061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.378984061
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1357785354
Short name T435
Test name
Test status
Simulation time 611854178 ps
CPU time 8.11 seconds
Started Jun 26 04:46:03 PM PDT 24
Finished Jun 26 04:46:13 PM PDT 24
Peak memory 210832 kb
Host smart-d5cc204f-27d2-4ff6-800a-f7b2ddc9859a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357785354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1357785354
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.361798277
Short name T47
Test name
Test status
Simulation time 176333467 ps
CPU time 11.86 seconds
Started Jun 26 04:46:02 PM PDT 24
Finished Jun 26 04:46:16 PM PDT 24
Peak memory 217284 kb
Host smart-6724f174-95ac-4d98-a1a3-75390c9120ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361798277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.361798277
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.872729620
Short name T96
Test name
Test status
Simulation time 5969290892 ps
CPU time 160.81 seconds
Started Jun 26 04:46:01 PM PDT 24
Finished Jun 26 04:48:44 PM PDT 24
Peak memory 214144 kb
Host smart-b31bdfa3-7826-4156-8ebc-97237ee363b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872729620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.872729620
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.543443836
Short name T393
Test name
Test status
Simulation time 11164052549 ps
CPU time 25.69 seconds
Started Jun 26 04:46:04 PM PDT 24
Finished Jun 26 04:46:31 PM PDT 24
Peak memory 216016 kb
Host smart-f50ade03-7140-4db2-8f3c-86ecfc155380
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543443836 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.543443836
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.567322883
Short name T56
Test name
Test status
Simulation time 12353044436 ps
CPU time 26.79 seconds
Started Jun 26 04:46:03 PM PDT 24
Finished Jun 26 04:46:31 PM PDT 24
Peak memory 212240 kb
Host smart-0fe940c2-c170-4b9a-b92b-1405c1676218
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567322883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.567322883
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1718305101
Short name T79
Test name
Test status
Simulation time 2156264494 ps
CPU time 55.84 seconds
Started Jun 26 04:46:03 PM PDT 24
Finished Jun 26 04:47:01 PM PDT 24
Peak memory 214204 kb
Host smart-72273967-de3f-4c4e-9430-c005d7316200
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718305101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1718305101
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3679933271
Short name T411
Test name
Test status
Simulation time 354422896 ps
CPU time 12 seconds
Started Jun 26 04:46:02 PM PDT 24
Finished Jun 26 04:46:16 PM PDT 24
Peak memory 212476 kb
Host smart-dabf0ce2-123f-4eab-bde0-ace4423f9952
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679933271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3679933271
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3623357481
Short name T361
Test name
Test status
Simulation time 2403848453 ps
CPU time 15.22 seconds
Started Jun 26 04:46:00 PM PDT 24
Finished Jun 26 04:46:16 PM PDT 24
Peak memory 217276 kb
Host smart-39fdc9bb-2c34-4617-a951-57e112913124
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623357481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3623357481
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1702729669
Short name T382
Test name
Test status
Simulation time 1814591079 ps
CPU time 19 seconds
Started Jun 26 04:46:11 PM PDT 24
Finished Jun 26 04:46:32 PM PDT 24
Peak memory 216496 kb
Host smart-13d5c8cb-7890-42e0-a0ca-8eab2f94ae54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702729669 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1702729669
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3056302513
Short name T394
Test name
Test status
Simulation time 3926288013 ps
CPU time 14.4 seconds
Started Jun 26 04:46:09 PM PDT 24
Finished Jun 26 04:46:25 PM PDT 24
Peak memory 210776 kb
Host smart-04b0f833-a91c-4a16-a900-8c4c4043394c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056302513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3056302513
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2057460711
Short name T438
Test name
Test status
Simulation time 17294541943 ps
CPU time 137.44 seconds
Started Jun 26 04:46:00 PM PDT 24
Finished Jun 26 04:48:19 PM PDT 24
Peak memory 214852 kb
Host smart-ef88d30b-9cae-4ef0-836f-5879b26d2079
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057460711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2057460711
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2603663718
Short name T443
Test name
Test status
Simulation time 332005185 ps
CPU time 10.9 seconds
Started Jun 26 04:46:09 PM PDT 24
Finished Jun 26 04:46:21 PM PDT 24
Peak memory 210952 kb
Host smart-a304389f-3f61-4f96-9972-917b644c7c8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603663718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2603663718
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1501226493
Short name T448
Test name
Test status
Simulation time 7721046246 ps
CPU time 36.19 seconds
Started Jun 26 04:46:03 PM PDT 24
Finished Jun 26 04:46:41 PM PDT 24
Peak memory 217636 kb
Host smart-b02605b6-e54e-4230-bd04-4dedfb15f240
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501226493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1501226493
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2756453191
Short name T94
Test name
Test status
Simulation time 390520439 ps
CPU time 158.8 seconds
Started Jun 26 04:46:10 PM PDT 24
Finished Jun 26 04:48:50 PM PDT 24
Peak memory 213936 kb
Host smart-d0e4ff11-b97d-4ca8-81e8-2f06a2405a38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756453191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2756453191
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1471127644
Short name T418
Test name
Test status
Simulation time 187543748 ps
CPU time 9.55 seconds
Started Jun 26 04:46:10 PM PDT 24
Finished Jun 26 04:46:21 PM PDT 24
Peak memory 216992 kb
Host smart-9f37bf9a-9dad-42c0-8bca-0344a546af4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471127644 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1471127644
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1524985056
Short name T387
Test name
Test status
Simulation time 4034862982 ps
CPU time 20.63 seconds
Started Jun 26 04:46:10 PM PDT 24
Finished Jun 26 04:46:32 PM PDT 24
Peak memory 211732 kb
Host smart-1e8a5342-4c38-4535-b0ec-0fc4becb40bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524985056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1524985056
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.2508478674
Short name T426
Test name
Test status
Simulation time 60259699916 ps
CPU time 155.77 seconds
Started Jun 26 04:46:08 PM PDT 24
Finished Jun 26 04:48:44 PM PDT 24
Peak memory 214900 kb
Host smart-70f253eb-f706-4c83-b8f5-2c19d0d205ee
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508478674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.2508478674
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1508258247
Short name T424
Test name
Test status
Simulation time 7415937613 ps
CPU time 31.71 seconds
Started Jun 26 04:46:13 PM PDT 24
Finished Jun 26 04:46:46 PM PDT 24
Peak memory 212412 kb
Host smart-ff2e9e34-a08e-484a-8a35-f9ef74dcd44e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508258247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1508258247
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.637449893
Short name T358
Test name
Test status
Simulation time 3733500825 ps
CPU time 33.02 seconds
Started Jun 26 04:46:11 PM PDT 24
Finished Jun 26 04:46:45 PM PDT 24
Peak memory 218408 kb
Host smart-b93d0166-6036-4ba8-816e-b334dcc04bd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637449893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.637449893
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4230334246
Short name T52
Test name
Test status
Simulation time 3199571255 ps
CPU time 90.69 seconds
Started Jun 26 04:46:11 PM PDT 24
Finished Jun 26 04:47:44 PM PDT 24
Peak memory 213716 kb
Host smart-63c62857-a795-4264-bac9-f14e935e19f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230334246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.4230334246
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1565164164
Short name T429
Test name
Test status
Simulation time 4669045277 ps
CPU time 29.31 seconds
Started Jun 26 04:46:09 PM PDT 24
Finished Jun 26 04:46:39 PM PDT 24
Peak memory 217092 kb
Host smart-1ed63936-7487-477b-b805-cb8094130ed0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565164164 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1565164164
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1951743880
Short name T75
Test name
Test status
Simulation time 4326890030 ps
CPU time 31.29 seconds
Started Jun 26 04:46:09 PM PDT 24
Finished Jun 26 04:46:41 PM PDT 24
Peak memory 211728 kb
Host smart-d2e5f373-198e-4e8f-9a6d-a02a8f81c9e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951743880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1951743880
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3488695781
Short name T60
Test name
Test status
Simulation time 1054339597 ps
CPU time 57.13 seconds
Started Jun 26 04:46:11 PM PDT 24
Finished Jun 26 04:47:10 PM PDT 24
Peak memory 213836 kb
Host smart-f9303019-afa1-4f68-80c2-06fb6a516fe1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488695781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3488695781
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3415174944
Short name T84
Test name
Test status
Simulation time 4078997385 ps
CPU time 29.91 seconds
Started Jun 26 04:46:11 PM PDT 24
Finished Jun 26 04:46:43 PM PDT 24
Peak memory 212132 kb
Host smart-2ad5cb11-909a-411f-9b89-56f4474ad273
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415174944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3415174944
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.831761353
Short name T407
Test name
Test status
Simulation time 6419090291 ps
CPU time 31.33 seconds
Started Jun 26 04:46:27 PM PDT 24
Finished Jun 26 04:47:01 PM PDT 24
Peak memory 218912 kb
Host smart-0f324797-d9b1-439e-a79d-7e6051da7f84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831761353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.831761353
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2371734118
Short name T434
Test name
Test status
Simulation time 12331174041 ps
CPU time 98.39 seconds
Started Jun 26 04:46:12 PM PDT 24
Finished Jun 26 04:47:52 PM PDT 24
Peak memory 213872 kb
Host smart-1141fda8-e2a5-4a43-881b-1b17471c928e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371734118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2371734118
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1435646548
Short name T371
Test name
Test status
Simulation time 36943510153 ps
CPU time 27.11 seconds
Started Jun 26 04:46:10 PM PDT 24
Finished Jun 26 04:46:39 PM PDT 24
Peak memory 216100 kb
Host smart-a4d7d430-1e20-4229-b626-0a2bc7c1369e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435646548 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1435646548
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3101728249
Short name T81
Test name
Test status
Simulation time 174346892 ps
CPU time 8.26 seconds
Started Jun 26 04:46:11 PM PDT 24
Finished Jun 26 04:46:21 PM PDT 24
Peak memory 210624 kb
Host smart-2f7a9214-4933-4e64-8ae0-b953ed3eea0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101728249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3101728249
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3027623591
Short name T451
Test name
Test status
Simulation time 20300212029 ps
CPU time 99.42 seconds
Started Jun 26 04:46:08 PM PDT 24
Finished Jun 26 04:47:49 PM PDT 24
Peak memory 214840 kb
Host smart-494b8215-3d83-438a-97ab-96d4b0a5a2b0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027623591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3027623591
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3564713756
Short name T86
Test name
Test status
Simulation time 10783595936 ps
CPU time 24.26 seconds
Started Jun 26 04:46:12 PM PDT 24
Finished Jun 26 04:46:38 PM PDT 24
Peak memory 212820 kb
Host smart-f669fc28-e0bd-4e3c-90e6-34c5302d7edb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564713756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3564713756
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.866073277
Short name T447
Test name
Test status
Simulation time 13311689637 ps
CPU time 29.79 seconds
Started Jun 26 04:46:10 PM PDT 24
Finished Jun 26 04:46:42 PM PDT 24
Peak memory 218524 kb
Host smart-45f408d2-8369-4319-bf84-2da8f176bced
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866073277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.866073277
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4131058034
Short name T454
Test name
Test status
Simulation time 22106720163 ps
CPU time 33.41 seconds
Started Jun 26 04:46:10 PM PDT 24
Finished Jun 26 04:46:46 PM PDT 24
Peak memory 217648 kb
Host smart-9887a9d2-0b02-441a-99a8-baeffea4a45c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131058034 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.4131058034
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3228506541
Short name T374
Test name
Test status
Simulation time 7536510559 ps
CPU time 19.98 seconds
Started Jun 26 04:46:13 PM PDT 24
Finished Jun 26 04:46:34 PM PDT 24
Peak memory 212292 kb
Host smart-7f1e76cd-3ad4-4613-abfc-0c84e896c41d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228506541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3228506541
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.353608945
Short name T422
Test name
Test status
Simulation time 29386330681 ps
CPU time 123.78 seconds
Started Jun 26 04:46:11 PM PDT 24
Finished Jun 26 04:48:17 PM PDT 24
Peak memory 214096 kb
Host smart-2396b23d-6eb0-4a08-a240-473a91115eef
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353608945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.353608945
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1901261518
Short name T450
Test name
Test status
Simulation time 3270879450 ps
CPU time 27.94 seconds
Started Jun 26 04:46:11 PM PDT 24
Finished Jun 26 04:46:41 PM PDT 24
Peak memory 212092 kb
Host smart-354d6599-d6d1-4145-b452-fd29d1f28b13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901261518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1901261518
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2669225236
Short name T365
Test name
Test status
Simulation time 174403447 ps
CPU time 12.75 seconds
Started Jun 26 04:46:09 PM PDT 24
Finished Jun 26 04:46:23 PM PDT 24
Peak memory 217456 kb
Host smart-2ebd692d-329f-40fc-8dc4-74021405200f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669225236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2669225236
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2455968536
Short name T384
Test name
Test status
Simulation time 5725123664 ps
CPU time 160.92 seconds
Started Jun 26 04:46:11 PM PDT 24
Finished Jun 26 04:48:54 PM PDT 24
Peak memory 214024 kb
Host smart-0d355224-93c6-4cb8-b0e1-5bdbdd6030c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455968536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2455968536
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1129557335
Short name T403
Test name
Test status
Simulation time 1825230068 ps
CPU time 19.95 seconds
Started Jun 26 04:46:10 PM PDT 24
Finished Jun 26 04:46:32 PM PDT 24
Peak memory 216868 kb
Host smart-a7e1706f-1db1-4e4b-8bc6-eb293bfb5c33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129557335 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1129557335
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.628493621
Short name T401
Test name
Test status
Simulation time 660894274 ps
CPU time 8.23 seconds
Started Jun 26 04:46:10 PM PDT 24
Finished Jun 26 04:46:19 PM PDT 24
Peak memory 210604 kb
Host smart-a8212869-132a-47a3-b0f6-37e17dc4fab3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628493621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.628493621
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.674670930
Short name T66
Test name
Test status
Simulation time 1050567207 ps
CPU time 56.71 seconds
Started Jun 26 04:46:10 PM PDT 24
Finished Jun 26 04:47:08 PM PDT 24
Peak memory 215296 kb
Host smart-a995618c-fbde-4eb7-9945-1959cad1d21e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674670930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.674670930
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2721767552
Short name T437
Test name
Test status
Simulation time 1155777944 ps
CPU time 18.45 seconds
Started Jun 26 04:46:12 PM PDT 24
Finished Jun 26 04:46:32 PM PDT 24
Peak memory 212220 kb
Host smart-27651023-ccfd-4d2c-b679-cee50e82a06e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721767552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2721767552
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2016447515
Short name T420
Test name
Test status
Simulation time 429383906 ps
CPU time 16 seconds
Started Jun 26 04:46:10 PM PDT 24
Finished Jun 26 04:46:28 PM PDT 24
Peak memory 218864 kb
Host smart-137de7e0-bde7-40dc-a904-49d6e095fa63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016447515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2016447515
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3872334871
Short name T99
Test name
Test status
Simulation time 5113605065 ps
CPU time 158.04 seconds
Started Jun 26 04:46:09 PM PDT 24
Finished Jun 26 04:48:48 PM PDT 24
Peak memory 214184 kb
Host smart-1ee1027d-0f91-47c5-9f35-77b61490cb64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872334871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3872334871
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1468449234
Short name T442
Test name
Test status
Simulation time 3358260766 ps
CPU time 27.32 seconds
Started Jun 26 04:45:41 PM PDT 24
Finished Jun 26 04:46:09 PM PDT 24
Peak memory 211488 kb
Host smart-8311d32b-c4f7-4251-a330-efc04c9adcbd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468449234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1468449234
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3077713535
Short name T419
Test name
Test status
Simulation time 2388086864 ps
CPU time 12.61 seconds
Started Jun 26 04:45:36 PM PDT 24
Finished Jun 26 04:45:49 PM PDT 24
Peak memory 210680 kb
Host smart-5b291441-f267-4c19-ba72-8516bf6bb62d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077713535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3077713535
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.489665827
Short name T55
Test name
Test status
Simulation time 1333125792 ps
CPU time 14.24 seconds
Started Jun 26 04:45:37 PM PDT 24
Finished Jun 26 04:45:52 PM PDT 24
Peak memory 210632 kb
Host smart-99e30818-400d-4d42-b3bd-9ac7fe71b27c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489665827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.489665827
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3537273111
Short name T360
Test name
Test status
Simulation time 16801345304 ps
CPU time 25.55 seconds
Started Jun 26 04:45:40 PM PDT 24
Finished Jun 26 04:46:07 PM PDT 24
Peak memory 218944 kb
Host smart-b162e5db-24c6-48e4-b95d-5f19f62abfe3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537273111 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3537273111
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.4155626715
Short name T85
Test name
Test status
Simulation time 170805085 ps
CPU time 8.21 seconds
Started Jun 26 04:45:37 PM PDT 24
Finished Jun 26 04:45:47 PM PDT 24
Peak memory 210724 kb
Host smart-5430166a-5b64-4f3f-b26e-41da48b76564
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155626715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.4155626715
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1317984712
Short name T388
Test name
Test status
Simulation time 360960192 ps
CPU time 8.29 seconds
Started Jun 26 04:45:40 PM PDT 24
Finished Jun 26 04:45:50 PM PDT 24
Peak memory 210560 kb
Host smart-bfcbbb7d-2409-436c-a7b5-0a18f9a0a056
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317984712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1317984712
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3946781584
Short name T355
Test name
Test status
Simulation time 2221096351 ps
CPU time 21.33 seconds
Started Jun 26 04:45:40 PM PDT 24
Finished Jun 26 04:46:03 PM PDT 24
Peak memory 210524 kb
Host smart-3daa4f22-5bd5-4a9c-9e07-4e056508a40f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946781584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3946781584
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2650244872
Short name T64
Test name
Test status
Simulation time 87987705728 ps
CPU time 185.58 seconds
Started Jun 26 04:45:40 PM PDT 24
Finished Jun 26 04:48:47 PM PDT 24
Peak memory 214876 kb
Host smart-43cc7655-d521-4d66-ae8b-3de3c488a5ed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650244872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2650244872
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3722924057
Short name T439
Test name
Test status
Simulation time 11455906386 ps
CPU time 21.41 seconds
Started Jun 26 04:45:38 PM PDT 24
Finished Jun 26 04:46:01 PM PDT 24
Peak memory 212360 kb
Host smart-25670363-b3e3-4c3b-88e5-a2f71ac4ce12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722924057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3722924057
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3400477546
Short name T366
Test name
Test status
Simulation time 9921985417 ps
CPU time 26.48 seconds
Started Jun 26 04:45:36 PM PDT 24
Finished Jun 26 04:46:03 PM PDT 24
Peak memory 218676 kb
Host smart-7eb7d21d-e54f-4bdb-8c2c-f50e58394a68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400477546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3400477546
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1177396105
Short name T95
Test name
Test status
Simulation time 483437033 ps
CPU time 86.12 seconds
Started Jun 26 04:45:38 PM PDT 24
Finished Jun 26 04:47:06 PM PDT 24
Peak memory 213240 kb
Host smart-8465ef64-b830-4f00-abe0-9c3c45525f5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177396105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1177396105
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.677768836
Short name T76
Test name
Test status
Simulation time 13419633016 ps
CPU time 29.76 seconds
Started Jun 26 04:45:46 PM PDT 24
Finished Jun 26 04:46:16 PM PDT 24
Peak memory 212228 kb
Host smart-a639bb53-5666-438a-8e66-2b5f166cbf1e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677768836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.677768836
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1955022411
Short name T353
Test name
Test status
Simulation time 32688833603 ps
CPU time 19.28 seconds
Started Jun 26 04:45:42 PM PDT 24
Finished Jun 26 04:46:03 PM PDT 24
Peak memory 211020 kb
Host smart-66afaf2f-f5b5-4bc3-963c-ddfc198044d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955022411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1955022411
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2025487350
Short name T445
Test name
Test status
Simulation time 3774752470 ps
CPU time 35.77 seconds
Started Jun 26 04:45:46 PM PDT 24
Finished Jun 26 04:46:22 PM PDT 24
Peak memory 211252 kb
Host smart-b0e14a51-3e65-4d15-81a5-4864eac620f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025487350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2025487350
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.372161071
Short name T430
Test name
Test status
Simulation time 14412212143 ps
CPU time 28.56 seconds
Started Jun 26 04:45:43 PM PDT 24
Finished Jun 26 04:46:13 PM PDT 24
Peak memory 215660 kb
Host smart-029d3d69-2419-423c-8bf0-aea468b644b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372161071 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.372161071
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.54048054
Short name T67
Test name
Test status
Simulation time 338718152 ps
CPU time 8.4 seconds
Started Jun 26 04:45:46 PM PDT 24
Finished Jun 26 04:45:56 PM PDT 24
Peak memory 210788 kb
Host smart-095938d0-c986-4081-b76c-5dcd730fe2ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54048054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.54048054
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.331000316
Short name T376
Test name
Test status
Simulation time 8193692957 ps
CPU time 20.6 seconds
Started Jun 26 04:45:46 PM PDT 24
Finished Jun 26 04:46:07 PM PDT 24
Peak memory 210712 kb
Host smart-b66de44f-f120-4e2a-8e9c-b2b9cbeadb27
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331000316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.331000316
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1472270783
Short name T372
Test name
Test status
Simulation time 6286579362 ps
CPU time 17.84 seconds
Started Jun 26 04:45:44 PM PDT 24
Finished Jun 26 04:46:03 PM PDT 24
Peak memory 210656 kb
Host smart-9677a3b9-7467-47e2-a388-0c823887b4b5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472270783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1472270783
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2270105141
Short name T406
Test name
Test status
Simulation time 2169052647 ps
CPU time 57.34 seconds
Started Jun 26 04:45:37 PM PDT 24
Finished Jun 26 04:46:36 PM PDT 24
Peak memory 215120 kb
Host smart-6f0e4dac-f286-4ca0-be9f-499f09257466
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270105141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2270105141
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1204014359
Short name T391
Test name
Test status
Simulation time 16315953239 ps
CPU time 32.18 seconds
Started Jun 26 04:45:46 PM PDT 24
Finished Jun 26 04:46:19 PM PDT 24
Peak memory 212272 kb
Host smart-f47ccf8f-7114-4e87-98b7-79ac107de16b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204014359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1204014359
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2050280836
Short name T356
Test name
Test status
Simulation time 688466842 ps
CPU time 10.98 seconds
Started Jun 26 04:45:43 PM PDT 24
Finished Jun 26 04:45:55 PM PDT 24
Peak memory 218144 kb
Host smart-57e3f84a-fb3a-4644-a824-06bff2812d72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050280836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2050280836
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3891183350
Short name T54
Test name
Test status
Simulation time 4220080345 ps
CPU time 87.51 seconds
Started Jun 26 04:45:43 PM PDT 24
Finished Jun 26 04:47:12 PM PDT 24
Peak memory 214784 kb
Host smart-cfe69d87-eebb-4330-9e77-724ce03cb7a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891183350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3891183350
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3437057563
Short name T88
Test name
Test status
Simulation time 3914014038 ps
CPU time 31.23 seconds
Started Jun 26 04:45:49 PM PDT 24
Finished Jun 26 04:46:21 PM PDT 24
Peak memory 210972 kb
Host smart-bff8e66c-b903-411a-992f-c9cad8d356af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437057563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3437057563
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4032734712
Short name T416
Test name
Test status
Simulation time 17109547548 ps
CPU time 31.14 seconds
Started Jun 26 04:45:49 PM PDT 24
Finished Jun 26 04:46:22 PM PDT 24
Peak memory 211008 kb
Host smart-dc724ca8-06ec-4691-88ae-1db68fbbaf97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032734712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.4032734712
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2480866496
Short name T412
Test name
Test status
Simulation time 8216464925 ps
CPU time 35.37 seconds
Started Jun 26 04:45:43 PM PDT 24
Finished Jun 26 04:46:19 PM PDT 24
Peak memory 211892 kb
Host smart-4f3f638f-99b5-4f20-8812-0fd263befd1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480866496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2480866496
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3108526125
Short name T436
Test name
Test status
Simulation time 22140461219 ps
CPU time 24.57 seconds
Started Jun 26 04:45:50 PM PDT 24
Finished Jun 26 04:46:16 PM PDT 24
Peak memory 216320 kb
Host smart-53b2cd85-bb9f-4189-8966-c981835bea33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108526125 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3108526125
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.996210665
Short name T364
Test name
Test status
Simulation time 4109143568 ps
CPU time 18.91 seconds
Started Jun 26 04:45:54 PM PDT 24
Finished Jun 26 04:46:14 PM PDT 24
Peak memory 211868 kb
Host smart-4fa674c4-6f93-446e-8b07-8a7dc4d6d6b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996210665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.996210665
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2644349937
Short name T440
Test name
Test status
Simulation time 40188548025 ps
CPU time 31.84 seconds
Started Jun 26 04:45:46 PM PDT 24
Finished Jun 26 04:46:19 PM PDT 24
Peak memory 210940 kb
Host smart-2e7a7902-de56-4867-ac9d-0e231fe8f633
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644349937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2644349937
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.463187602
Short name T395
Test name
Test status
Simulation time 688464073 ps
CPU time 8.13 seconds
Started Jun 26 04:45:44 PM PDT 24
Finished Jun 26 04:45:53 PM PDT 24
Peak memory 210484 kb
Host smart-91968aab-7645-4da0-b8c8-dd1a194289bc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463187602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
463187602
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3354020114
Short name T77
Test name
Test status
Simulation time 100613895826 ps
CPU time 190.99 seconds
Started Jun 26 04:45:44 PM PDT 24
Finished Jun 26 04:48:56 PM PDT 24
Peak memory 218852 kb
Host smart-657e0348-6f15-4213-bea7-3f4ec22350b8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354020114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3354020114
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1095144095
Short name T399
Test name
Test status
Simulation time 661457303 ps
CPU time 8.33 seconds
Started Jun 26 04:45:52 PM PDT 24
Finished Jun 26 04:46:01 PM PDT 24
Peak memory 211240 kb
Host smart-58fe1257-4a7b-48b9-9531-35f390afc561
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095144095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1095144095
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1926499277
Short name T379
Test name
Test status
Simulation time 8678540310 ps
CPU time 34.99 seconds
Started Jun 26 04:45:43 PM PDT 24
Finished Jun 26 04:46:19 PM PDT 24
Peak memory 217124 kb
Host smart-8edf5332-89ab-40b0-87ba-e1ead1c8b6e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926499277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1926499277
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2424970580
Short name T363
Test name
Test status
Simulation time 5295594833 ps
CPU time 87.4 seconds
Started Jun 26 04:45:43 PM PDT 24
Finished Jun 26 04:47:12 PM PDT 24
Peak memory 214000 kb
Host smart-6f010a54-c589-4af6-bccb-a3a349298ea5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424970580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2424970580
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.665725745
Short name T408
Test name
Test status
Simulation time 4253702741 ps
CPU time 25.14 seconds
Started Jun 26 04:45:52 PM PDT 24
Finished Jun 26 04:46:18 PM PDT 24
Peak memory 217128 kb
Host smart-e00b18e5-750e-4786-8f77-c7de776f7686
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665725745 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.665725745
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.734631991
Short name T444
Test name
Test status
Simulation time 18362557216 ps
CPU time 32.81 seconds
Started Jun 26 04:45:49 PM PDT 24
Finished Jun 26 04:46:23 PM PDT 24
Peak memory 212120 kb
Host smart-1f997b30-243e-4ed2-8fc1-c8f3e8ae3316
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734631991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.734631991
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.4253292469
Short name T89
Test name
Test status
Simulation time 12499513936 ps
CPU time 108.22 seconds
Started Jun 26 04:45:51 PM PDT 24
Finished Jun 26 04:47:41 PM PDT 24
Peak memory 215168 kb
Host smart-37a4585c-36bf-472b-9965-a93ab988a6bd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253292469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.4253292469
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3206553869
Short name T421
Test name
Test status
Simulation time 596433582 ps
CPU time 12.43 seconds
Started Jun 26 04:45:52 PM PDT 24
Finished Jun 26 04:46:06 PM PDT 24
Peak memory 211112 kb
Host smart-5f212098-50a0-4458-a037-c49531407cf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206553869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3206553869
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3406377487
Short name T449
Test name
Test status
Simulation time 25216947524 ps
CPU time 37.47 seconds
Started Jun 26 04:45:49 PM PDT 24
Finished Jun 26 04:46:28 PM PDT 24
Peak memory 218888 kb
Host smart-6dfc3de8-6437-4a63-9d17-0aa43d446794
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406377487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3406377487
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2513507320
Short name T97
Test name
Test status
Simulation time 1190667681 ps
CPU time 89.7 seconds
Started Jun 26 04:45:54 PM PDT 24
Finished Jun 26 04:47:25 PM PDT 24
Peak memory 213668 kb
Host smart-47a2ce47-8e7d-4eaa-bf1a-7ba6676c4ae8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513507320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2513507320
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3334808967
Short name T357
Test name
Test status
Simulation time 17559225158 ps
CPU time 30.7 seconds
Started Jun 26 04:45:54 PM PDT 24
Finished Jun 26 04:46:26 PM PDT 24
Peak memory 218976 kb
Host smart-6e724e44-270e-4e9e-a48d-1fea6b2a3a8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334808967 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3334808967
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4055341741
Short name T433
Test name
Test status
Simulation time 460693087 ps
CPU time 8.59 seconds
Started Jun 26 04:45:51 PM PDT 24
Finished Jun 26 04:46:01 PM PDT 24
Peak memory 211000 kb
Host smart-acb7b81d-96e4-434f-8c22-5c2530a4f003
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055341741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.4055341741
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.422591398
Short name T82
Test name
Test status
Simulation time 11846301617 ps
CPU time 112.18 seconds
Started Jun 26 04:45:49 PM PDT 24
Finished Jun 26 04:47:42 PM PDT 24
Peak memory 213980 kb
Host smart-f201850b-b650-41ee-b0e5-e779843203bb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422591398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.422591398
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.397074090
Short name T415
Test name
Test status
Simulation time 23646196389 ps
CPU time 21.97 seconds
Started Jun 26 04:45:58 PM PDT 24
Finished Jun 26 04:46:22 PM PDT 24
Peak memory 212432 kb
Host smart-3bd4d995-217e-4694-9b6a-1c4c228068b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397074090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.397074090
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2054357836
Short name T354
Test name
Test status
Simulation time 6402628852 ps
CPU time 30.19 seconds
Started Jun 26 04:45:49 PM PDT 24
Finished Jun 26 04:46:21 PM PDT 24
Peak memory 217272 kb
Host smart-663f93ef-dc95-44b5-aa5e-0cd49d13fe46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054357836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2054357836
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2496199844
Short name T98
Test name
Test status
Simulation time 4238461950 ps
CPU time 165.66 seconds
Started Jun 26 04:45:49 PM PDT 24
Finished Jun 26 04:48:35 PM PDT 24
Peak memory 214032 kb
Host smart-4d9b7775-fb92-4cdf-a907-aad8007f1e98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496199844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2496199844
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3444079406
Short name T404
Test name
Test status
Simulation time 21056734605 ps
CPU time 20.61 seconds
Started Jun 26 04:45:55 PM PDT 24
Finished Jun 26 04:46:17 PM PDT 24
Peak memory 217892 kb
Host smart-e155e9bc-b1fe-4f68-a8a0-6941989e828b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444079406 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3444079406
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.420253440
Short name T389
Test name
Test status
Simulation time 7493619513 ps
CPU time 19.02 seconds
Started Jun 26 04:45:49 PM PDT 24
Finished Jun 26 04:46:10 PM PDT 24
Peak memory 212232 kb
Host smart-faf6bbf2-e46c-4dac-9d8c-467b012b16be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420253440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.420253440
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.602382003
Short name T452
Test name
Test status
Simulation time 168974135 ps
CPU time 8.41 seconds
Started Jun 26 04:45:49 PM PDT 24
Finished Jun 26 04:46:00 PM PDT 24
Peak memory 211364 kb
Host smart-d5e0e944-2983-4811-8df9-83c5d3555fbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602382003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.602382003
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1922275475
Short name T375
Test name
Test status
Simulation time 172548302 ps
CPU time 13.09 seconds
Started Jun 26 04:45:51 PM PDT 24
Finished Jun 26 04:46:06 PM PDT 24
Peak memory 216396 kb
Host smart-e8c561bf-d964-45ef-8421-ae21ca9f9475
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922275475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1922275475
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3742535885
Short name T100
Test name
Test status
Simulation time 30462358794 ps
CPU time 99.39 seconds
Started Jun 26 04:45:51 PM PDT 24
Finished Jun 26 04:47:32 PM PDT 24
Peak memory 213968 kb
Host smart-4df32d34-c7f3-4002-b1d2-fb6b79231712
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742535885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3742535885
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3667261797
Short name T362
Test name
Test status
Simulation time 363628415 ps
CPU time 8.91 seconds
Started Jun 26 04:45:55 PM PDT 24
Finished Jun 26 04:46:06 PM PDT 24
Peak memory 216460 kb
Host smart-585f5f02-c9cb-4d52-86fc-9cd9b8710941
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667261797 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3667261797
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1863838906
Short name T427
Test name
Test status
Simulation time 15457314967 ps
CPU time 24.12 seconds
Started Jun 26 04:45:57 PM PDT 24
Finished Jun 26 04:46:22 PM PDT 24
Peak memory 212420 kb
Host smart-4ea71b19-28cd-43ea-a15d-44efd231cee7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863838906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1863838906
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3896035922
Short name T453
Test name
Test status
Simulation time 706403904 ps
CPU time 37.92 seconds
Started Jun 26 04:45:56 PM PDT 24
Finished Jun 26 04:46:35 PM PDT 24
Peak memory 213172 kb
Host smart-c1bbb900-87f8-4320-a021-d15cd3f8c517
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896035922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3896035922
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2667221372
Short name T441
Test name
Test status
Simulation time 13013196202 ps
CPU time 27.1 seconds
Started Jun 26 04:45:56 PM PDT 24
Finished Jun 26 04:46:24 PM PDT 24
Peak memory 212836 kb
Host smart-00936600-78b5-46ad-b513-1e1cd61633c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667221372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2667221372
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2981494724
Short name T398
Test name
Test status
Simulation time 827854012 ps
CPU time 17.33 seconds
Started Jun 26 04:45:56 PM PDT 24
Finished Jun 26 04:46:14 PM PDT 24
Peak memory 218940 kb
Host smart-43c178d3-7c7e-4827-b3bd-999cb4e14b62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981494724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2981494724
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1472386616
Short name T423
Test name
Test status
Simulation time 10873048264 ps
CPU time 96.83 seconds
Started Jun 26 04:45:56 PM PDT 24
Finished Jun 26 04:47:34 PM PDT 24
Peak memory 213904 kb
Host smart-2db7686b-d4f1-42dc-85af-95590c0ea6f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472386616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1472386616
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.853623369
Short name T409
Test name
Test status
Simulation time 917843240 ps
CPU time 9.09 seconds
Started Jun 26 04:45:56 PM PDT 24
Finished Jun 26 04:46:07 PM PDT 24
Peak memory 217148 kb
Host smart-461897e5-f583-4e21-9622-147717b4118c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853623369 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.853623369
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.4006972718
Short name T417
Test name
Test status
Simulation time 2895918890 ps
CPU time 25.17 seconds
Started Jun 26 04:45:57 PM PDT 24
Finished Jun 26 04:46:23 PM PDT 24
Peak memory 211300 kb
Host smart-e5839f2a-82ac-4362-a7b6-e05a303948ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006972718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.4006972718
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.627544948
Short name T65
Test name
Test status
Simulation time 16684081428 ps
CPU time 159.11 seconds
Started Jun 26 04:45:57 PM PDT 24
Finished Jun 26 04:48:38 PM PDT 24
Peak memory 215808 kb
Host smart-73166d7f-c0db-4273-9d20-44b4c3dec525
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627544948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.627544948
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3856486754
Short name T62
Test name
Test status
Simulation time 4795222843 ps
CPU time 33.26 seconds
Started Jun 26 04:45:55 PM PDT 24
Finished Jun 26 04:46:30 PM PDT 24
Peak memory 212228 kb
Host smart-a158c257-4590-4a52-a6e0-cc911bf0492e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856486754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3856486754
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.211373878
Short name T431
Test name
Test status
Simulation time 17219922176 ps
CPU time 35.06 seconds
Started Jun 26 04:45:56 PM PDT 24
Finished Jun 26 04:46:32 PM PDT 24
Peak memory 218612 kb
Host smart-35cf0b2c-8875-4648-942b-4a3f20807313
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211373878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.211373878
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2187702156
Short name T93
Test name
Test status
Simulation time 3590199455 ps
CPU time 90.32 seconds
Started Jun 26 04:45:57 PM PDT 24
Finished Jun 26 04:47:29 PM PDT 24
Peak memory 213784 kb
Host smart-0bb52df2-7f6e-440d-afd5-9472912a0abf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187702156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2187702156
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2765961748
Short name T221
Test name
Test status
Simulation time 174441535 ps
CPU time 8.42 seconds
Started Jun 26 04:44:12 PM PDT 24
Finished Jun 26 04:44:41 PM PDT 24
Peak memory 217128 kb
Host smart-86e53cfb-d933-4f94-8164-3c862b461d09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765961748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2765961748
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2890272389
Short name T133
Test name
Test status
Simulation time 3693494912 ps
CPU time 15.07 seconds
Started Jun 26 04:44:13 PM PDT 24
Finished Jun 26 04:44:47 PM PDT 24
Peak memory 218868 kb
Host smart-d935a28e-97e6-42c1-99cd-380bc981af94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2890272389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2890272389
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2401268734
Short name T23
Test name
Test status
Simulation time 10104404444 ps
CPU time 127.25 seconds
Started Jun 26 04:44:10 PM PDT 24
Finished Jun 26 04:46:35 PM PDT 24
Peak memory 237516 kb
Host smart-94a78747-0515-45c7-ad8e-77f4da6f8b05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401268734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2401268734
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1066718139
Short name T74
Test name
Test status
Simulation time 5991591639 ps
CPU time 31.22 seconds
Started Jun 26 04:44:12 PM PDT 24
Finished Jun 26 04:45:02 PM PDT 24
Peak memory 216796 kb
Host smart-4a121ad3-8938-4a52-a969-c1f8a720a222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066718139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1066718139
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.1996343841
Short name T269
Test name
Test status
Simulation time 33008734527 ps
CPU time 90.64 seconds
Started Jun 26 04:44:11 PM PDT 24
Finished Jun 26 04:46:01 PM PDT 24
Peak memory 219536 kb
Host smart-27e9f6b4-ba7b-4ec2-90e1-7bf56cc4424f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996343841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.1996343841
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3044340984
Short name T337
Test name
Test status
Simulation time 7197352855 ps
CPU time 57.23 seconds
Started Jun 26 04:44:14 PM PDT 24
Finished Jun 26 04:45:32 PM PDT 24
Peak memory 219320 kb
Host smart-12088d3f-5d90-43dd-8333-c463c5b5f3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044340984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3044340984
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.33721363
Short name T235
Test name
Test status
Simulation time 3670642746 ps
CPU time 30.43 seconds
Started Jun 26 04:44:13 PM PDT 24
Finished Jun 26 04:45:03 PM PDT 24
Peak memory 211260 kb
Host smart-7510edf0-8b8b-4253-aca5-0df725e99945
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33721363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.33721363
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.4040857961
Short name T297
Test name
Test status
Simulation time 14745582056 ps
CPU time 70.2 seconds
Started Jun 26 04:44:10 PM PDT 24
Finished Jun 26 04:45:39 PM PDT 24
Peak memory 216176 kb
Host smart-676db9e8-8d68-44de-9851-1701fb6cd3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040857961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.4040857961
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3630331214
Short name T223
Test name
Test status
Simulation time 5940504263 ps
CPU time 45.76 seconds
Started Jun 26 04:44:13 PM PDT 24
Finished Jun 26 04:45:18 PM PDT 24
Peak memory 219820 kb
Host smart-333c2dc6-e52d-47e3-bc23-63e940d740b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630331214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3630331214
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3760295405
Short name T58
Test name
Test status
Simulation time 660744705 ps
CPU time 8.03 seconds
Started Jun 26 04:44:35 PM PDT 24
Finished Jun 26 04:45:12 PM PDT 24
Peak memory 217056 kb
Host smart-dcc56c27-5c0e-40a8-8dc7-414394ec6412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760295405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3760295405
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.37054554
Short name T181
Test name
Test status
Simulation time 38448716859 ps
CPU time 237.75 seconds
Started Jun 26 04:44:32 PM PDT 24
Finished Jun 26 04:48:57 PM PDT 24
Peak memory 218044 kb
Host smart-1c8db65f-1dbc-438f-8aa2-a686f29e317b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37054554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_co
rrupt_sig_fatal_chk.37054554
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.982673920
Short name T216
Test name
Test status
Simulation time 2073935564 ps
CPU time 31.97 seconds
Started Jun 26 04:44:37 PM PDT 24
Finished Jun 26 04:45:39 PM PDT 24
Peak memory 218744 kb
Host smart-39fc1d61-624f-4de8-a248-e1fdf541ee03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982673920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.982673920
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.4167315093
Short name T236
Test name
Test status
Simulation time 12533842920 ps
CPU time 25.77 seconds
Started Jun 26 04:44:30 PM PDT 24
Finished Jun 26 04:45:23 PM PDT 24
Peak memory 219316 kb
Host smart-db0fa3fc-4b3a-44d9-ac6c-f488af729189
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4167315093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.4167315093
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.832635989
Short name T275
Test name
Test status
Simulation time 9770638801 ps
CPU time 47.34 seconds
Started Jun 26 04:44:21 PM PDT 24
Finished Jun 26 04:45:32 PM PDT 24
Peak memory 216708 kb
Host smart-52a83cde-7195-4f70-80c9-f3423a72f4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832635989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.832635989
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.353145937
Short name T72
Test name
Test status
Simulation time 8064450156 ps
CPU time 50.77 seconds
Started Jun 26 04:44:29 PM PDT 24
Finished Jun 26 04:45:47 PM PDT 24
Peak memory 219392 kb
Host smart-29f79a9a-d3a8-4697-a3e1-39761c087191
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353145937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.353145937
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1376516691
Short name T184
Test name
Test status
Simulation time 3518594702 ps
CPU time 27.08 seconds
Started Jun 26 04:44:27 PM PDT 24
Finished Jun 26 04:45:21 PM PDT 24
Peak memory 216988 kb
Host smart-28255c66-982d-4ee5-bad0-339e6fbd9132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376516691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1376516691
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2805719871
Short name T179
Test name
Test status
Simulation time 110362388298 ps
CPU time 514.53 seconds
Started Jun 26 04:44:32 PM PDT 24
Finished Jun 26 04:53:34 PM PDT 24
Peak memory 233636 kb
Host smart-74be9650-5fc6-424b-a3ac-6496d480eeea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805719871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2805719871
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.915046180
Short name T240
Test name
Test status
Simulation time 30946408847 ps
CPU time 51.43 seconds
Started Jun 26 04:44:33 PM PDT 24
Finished Jun 26 04:45:53 PM PDT 24
Peak memory 219332 kb
Host smart-20d8450c-b1f1-4f22-b77d-be455b157906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915046180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.915046180
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.817470345
Short name T343
Test name
Test status
Simulation time 10403830233 ps
CPU time 25.54 seconds
Started Jun 26 04:44:35 PM PDT 24
Finished Jun 26 04:45:30 PM PDT 24
Peak memory 219396 kb
Host smart-54988281-ba75-4813-af37-89c7f7ab0be2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=817470345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.817470345
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2077335603
Short name T152
Test name
Test status
Simulation time 44813156226 ps
CPU time 73.9 seconds
Started Jun 26 04:44:27 PM PDT 24
Finished Jun 26 04:46:08 PM PDT 24
Peak memory 216800 kb
Host smart-e94cbe28-ac68-4baf-be04-2881851086c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077335603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2077335603
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.487448857
Short name T321
Test name
Test status
Simulation time 1271557205 ps
CPU time 71.45 seconds
Started Jun 26 04:44:32 PM PDT 24
Finished Jun 26 04:46:11 PM PDT 24
Peak memory 219244 kb
Host smart-da177e77-dcaf-4522-a67d-30200a59c46b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487448857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.487448857
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3737047541
Short name T300
Test name
Test status
Simulation time 4793108442 ps
CPU time 15.24 seconds
Started Jun 26 04:44:37 PM PDT 24
Finished Jun 26 04:45:22 PM PDT 24
Peak memory 217532 kb
Host smart-51e12c5a-b948-4ea2-85da-ee4179d98779
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737047541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3737047541
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3202859024
Short name T313
Test name
Test status
Simulation time 158971642077 ps
CPU time 440.96 seconds
Started Jun 26 04:44:26 PM PDT 24
Finished Jun 26 04:52:14 PM PDT 24
Peak memory 217836 kb
Host smart-895e6aa2-13cf-4437-8bae-f4112c5a89bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202859024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3202859024
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3852349589
Short name T144
Test name
Test status
Simulation time 18496748882 ps
CPU time 37.67 seconds
Started Jun 26 04:44:27 PM PDT 24
Finished Jun 26 04:45:31 PM PDT 24
Peak memory 219320 kb
Host smart-dc54945f-f881-4dad-9904-83c884266d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852349589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3852349589
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3101225454
Short name T123
Test name
Test status
Simulation time 3667869239 ps
CPU time 28.71 seconds
Started Jun 26 04:44:30 PM PDT 24
Finished Jun 26 04:45:28 PM PDT 24
Peak memory 211292 kb
Host smart-5900e038-cf2b-4b2c-bb81-1fd586972658
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3101225454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3101225454
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.613342741
Short name T334
Test name
Test status
Simulation time 4884083887 ps
CPU time 19.6 seconds
Started Jun 26 04:44:37 PM PDT 24
Finished Jun 26 04:45:26 PM PDT 24
Peak memory 216712 kb
Host smart-f1275015-8d9c-4733-bcaa-5caed8ac3fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613342741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.613342741
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.269958314
Short name T185
Test name
Test status
Simulation time 18827580327 ps
CPU time 69.98 seconds
Started Jun 26 04:44:35 PM PDT 24
Finished Jun 26 04:46:14 PM PDT 24
Peak memory 220072 kb
Host smart-7c294df4-a58c-403c-bff2-b75c44fca0b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269958314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.269958314
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2569150256
Short name T249
Test name
Test status
Simulation time 13588016648 ps
CPU time 28.88 seconds
Started Jun 26 04:44:21 PM PDT 24
Finished Jun 26 04:45:12 PM PDT 24
Peak memory 217540 kb
Host smart-b8531698-a691-46e3-989d-d767720792d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569150256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2569150256
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.936045075
Short name T237
Test name
Test status
Simulation time 469371652942 ps
CPU time 599.19 seconds
Started Jun 26 04:44:25 PM PDT 24
Finished Jun 26 04:54:50 PM PDT 24
Peak memory 225376 kb
Host smart-2ba2b804-fefa-49ef-b079-bb11e835ddba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936045075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.936045075
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.998445334
Short name T1
Test name
Test status
Simulation time 21993565117 ps
CPU time 57.14 seconds
Started Jun 26 04:44:27 PM PDT 24
Finished Jun 26 04:45:51 PM PDT 24
Peak memory 219184 kb
Host smart-60557a38-e134-42fd-a427-060e2a03149e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998445334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.998445334
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.837907531
Short name T263
Test name
Test status
Simulation time 24990916159 ps
CPU time 31.31 seconds
Started Jun 26 04:44:25 PM PDT 24
Finished Jun 26 04:45:22 PM PDT 24
Peak memory 217632 kb
Host smart-ed0d666d-44ce-47a0-9758-9fd6663b3706
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=837907531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.837907531
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2841156390
Short name T161
Test name
Test status
Simulation time 5303810580 ps
CPU time 53.54 seconds
Started Jun 26 04:44:28 PM PDT 24
Finished Jun 26 04:45:47 PM PDT 24
Peak memory 216232 kb
Host smart-dfe2861c-c973-4a8d-a78e-8e1e4c45b558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841156390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2841156390
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1218520138
Short name T348
Test name
Test status
Simulation time 559565987 ps
CPU time 37.82 seconds
Started Jun 26 04:44:32 PM PDT 24
Finished Jun 26 04:45:39 PM PDT 24
Peak memory 219240 kb
Host smart-940a8662-a619-407c-ab87-2c82a66ebf69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218520138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1218520138
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3499793659
Short name T57
Test name
Test status
Simulation time 8848220199 ps
CPU time 21.36 seconds
Started Jun 26 04:46:00 PM PDT 24
Finished Jun 26 04:46:23 PM PDT 24
Peak memory 217540 kb
Host smart-687f81c3-275d-4362-b31a-895f9dedb846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499793659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3499793659
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3593102481
Short name T261
Test name
Test status
Simulation time 12790447335 ps
CPU time 254.35 seconds
Started Jun 26 04:44:25 PM PDT 24
Finished Jun 26 04:49:05 PM PDT 24
Peak memory 234912 kb
Host smart-4b6d9735-4fc7-4bfe-b94d-5b58e2bf3e0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593102481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3593102481
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2889956324
Short name T282
Test name
Test status
Simulation time 15676558951 ps
CPU time 42.82 seconds
Started Jun 26 04:44:27 PM PDT 24
Finished Jun 26 04:45:37 PM PDT 24
Peak memory 219220 kb
Host smart-c4c6b287-9d69-4f08-b8e8-2023ea6f3078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889956324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2889956324
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1881173564
Short name T186
Test name
Test status
Simulation time 185428667 ps
CPU time 10.34 seconds
Started Jun 26 04:44:22 PM PDT 24
Finished Jun 26 04:44:55 PM PDT 24
Peak memory 219264 kb
Host smart-e4919405-752c-482c-972a-38cca328c535
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1881173564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1881173564
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1138875195
Short name T220
Test name
Test status
Simulation time 2554683673 ps
CPU time 34.28 seconds
Started Jun 26 04:44:24 PM PDT 24
Finished Jun 26 04:45:23 PM PDT 24
Peak memory 215964 kb
Host smart-f5790311-5092-4124-956e-a2b236fba81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138875195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1138875195
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2257829506
Short name T19
Test name
Test status
Simulation time 1871323643 ps
CPU time 14.75 seconds
Started Jun 26 04:44:26 PM PDT 24
Finished Jun 26 04:45:08 PM PDT 24
Peak memory 219236 kb
Host smart-7c91838a-38c3-4624-887e-e381b70fac76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257829506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2257829506
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1826754183
Short name T345
Test name
Test status
Simulation time 838884543 ps
CPU time 13.82 seconds
Started Jun 26 04:44:32 PM PDT 24
Finished Jun 26 04:45:13 PM PDT 24
Peak memory 217392 kb
Host smart-c59bf19d-a532-4ff2-8616-ae47e874bcb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826754183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1826754183
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4009677298
Short name T31
Test name
Test status
Simulation time 73170736389 ps
CPU time 759.13 seconds
Started Jun 26 04:44:30 PM PDT 24
Finished Jun 26 04:57:36 PM PDT 24
Peak memory 234924 kb
Host smart-69eb1176-374f-415a-8fbb-b6290d58fc98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009677298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.4009677298
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2572822301
Short name T199
Test name
Test status
Simulation time 345205336 ps
CPU time 12.8 seconds
Started Jun 26 04:44:27 PM PDT 24
Finished Jun 26 04:45:06 PM PDT 24
Peak memory 218612 kb
Host smart-5dcd7edd-4209-4a04-ac35-4fa20a1c9316
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2572822301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2572822301
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.457448029
Short name T109
Test name
Test status
Simulation time 10528862488 ps
CPU time 39.29 seconds
Started Jun 26 04:44:32 PM PDT 24
Finished Jun 26 04:45:39 PM PDT 24
Peak memory 215884 kb
Host smart-b240c249-0343-4575-8093-1177c7df5040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457448029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.457448029
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.318005863
Short name T183
Test name
Test status
Simulation time 352229861 ps
CPU time 19.51 seconds
Started Jun 26 04:44:36 PM PDT 24
Finished Jun 26 04:45:24 PM PDT 24
Peak memory 216124 kb
Host smart-dd44e64a-2cd0-4455-a978-ee21c77fa358
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318005863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.318005863
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.963414379
Short name T203
Test name
Test status
Simulation time 257208536 ps
CPU time 9.62 seconds
Started Jun 26 04:44:30 PM PDT 24
Finished Jun 26 04:45:09 PM PDT 24
Peak memory 217152 kb
Host smart-0d1de184-44c3-4cf4-9fd0-406396c9d1e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963414379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.963414379
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.232034499
Short name T32
Test name
Test status
Simulation time 102610048236 ps
CPU time 531.65 seconds
Started Jun 26 04:44:32 PM PDT 24
Finished Jun 26 04:53:51 PM PDT 24
Peak memory 237572 kb
Host smart-04965fdb-1383-4aa3-8eba-ed7e319a0efd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232034499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.232034499
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2967003168
Short name T349
Test name
Test status
Simulation time 30772163290 ps
CPU time 65.04 seconds
Started Jun 26 04:44:29 PM PDT 24
Finished Jun 26 04:46:02 PM PDT 24
Peak memory 219392 kb
Host smart-b157d045-f41a-4e69-a980-7ba136264619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967003168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2967003168
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1142674881
Short name T285
Test name
Test status
Simulation time 184881702 ps
CPU time 10.38 seconds
Started Jun 26 04:44:33 PM PDT 24
Finished Jun 26 04:45:12 PM PDT 24
Peak memory 219320 kb
Host smart-be90ad03-aaf7-4f1b-a537-eaf0c6ce5f4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1142674881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1142674881
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2667468681
Short name T130
Test name
Test status
Simulation time 1054021394 ps
CPU time 29.75 seconds
Started Jun 26 04:44:40 PM PDT 24
Finished Jun 26 04:45:39 PM PDT 24
Peak memory 216220 kb
Host smart-6f997d10-fcd8-48f5-8fef-bd6274bb2064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667468681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2667468681
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3954300798
Short name T165
Test name
Test status
Simulation time 2094775748 ps
CPU time 33.29 seconds
Started Jun 26 04:44:32 PM PDT 24
Finished Jun 26 04:45:33 PM PDT 24
Peak memory 219236 kb
Host smart-3ccf0e15-1d06-4a65-a76e-adeaf6b5674a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954300798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3954300798
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3850879373
Short name T326
Test name
Test status
Simulation time 18898624114 ps
CPU time 31.24 seconds
Started Jun 26 04:44:30 PM PDT 24
Finished Jun 26 04:45:28 PM PDT 24
Peak memory 217540 kb
Host smart-693ca592-1556-43c6-8abb-a023ac16fdad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850879373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3850879373
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3130823723
Short name T34
Test name
Test status
Simulation time 409571170068 ps
CPU time 954.77 seconds
Started Jun 26 04:44:42 PM PDT 24
Finished Jun 26 05:01:06 PM PDT 24
Peak memory 233672 kb
Host smart-57585a90-fd43-4e8e-ad8e-031f3fa4087f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130823723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3130823723
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2892156400
Short name T151
Test name
Test status
Simulation time 28982439410 ps
CPU time 67.24 seconds
Started Jun 26 04:44:29 PM PDT 24
Finished Jun 26 04:46:04 PM PDT 24
Peak memory 219360 kb
Host smart-358f0247-7597-4bdd-859a-f00229887a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892156400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2892156400
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.4235262884
Short name T330
Test name
Test status
Simulation time 4972173630 ps
CPU time 35.35 seconds
Started Jun 26 04:44:43 PM PDT 24
Finished Jun 26 04:45:48 PM PDT 24
Peak memory 217284 kb
Host smart-c5ec0905-ab79-487b-8bde-c32367d6bd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235262884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.4235262884
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3264910212
Short name T107
Test name
Test status
Simulation time 154226431687 ps
CPU time 145.13 seconds
Started Jun 26 04:44:32 PM PDT 24
Finished Jun 26 04:47:27 PM PDT 24
Peak memory 219792 kb
Host smart-ef15d07d-1dba-490a-8493-624de62e7920
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264910212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3264910212
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2227109246
Short name T231
Test name
Test status
Simulation time 1470071352 ps
CPU time 13.61 seconds
Started Jun 26 04:44:30 PM PDT 24
Finished Jun 26 04:45:11 PM PDT 24
Peak memory 213192 kb
Host smart-50f1d2b8-b3b8-4742-ad63-bb9962ea428c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227109246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2227109246
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2909710392
Short name T217
Test name
Test status
Simulation time 111337017281 ps
CPU time 1071.53 seconds
Started Jun 26 04:44:29 PM PDT 24
Finished Jun 26 05:02:48 PM PDT 24
Peak memory 217012 kb
Host smart-bd5d9243-0d79-47fd-b7b8-50c64cc10183
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909710392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2909710392
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1062394671
Short name T127
Test name
Test status
Simulation time 1709859070 ps
CPU time 29.97 seconds
Started Jun 26 04:44:29 PM PDT 24
Finished Jun 26 04:45:27 PM PDT 24
Peak memory 215772 kb
Host smart-153c46ad-eb40-4dbc-ae10-9cbfa075a10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062394671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1062394671
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1243169266
Short name T309
Test name
Test status
Simulation time 2018566230 ps
CPU time 13.51 seconds
Started Jun 26 04:44:28 PM PDT 24
Finished Jun 26 04:45:10 PM PDT 24
Peak memory 219260 kb
Host smart-e7d95646-cbc8-4109-bbb1-36d1384a89c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1243169266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1243169266
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2185102808
Short name T131
Test name
Test status
Simulation time 23673772101 ps
CPU time 62.26 seconds
Started Jun 26 04:44:28 PM PDT 24
Finished Jun 26 04:45:56 PM PDT 24
Peak memory 217408 kb
Host smart-95b3b8f3-efab-45e3-9c3b-89381af04c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185102808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2185102808
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3054297824
Short name T336
Test name
Test status
Simulation time 1203056509 ps
CPU time 14.64 seconds
Started Jun 26 04:44:39 PM PDT 24
Finished Jun 26 04:45:24 PM PDT 24
Peak memory 219280 kb
Host smart-d401b055-afc3-44bc-a88a-34bf41fb322f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054297824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3054297824
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1805678291
Short name T138
Test name
Test status
Simulation time 765332923 ps
CPU time 13.8 seconds
Started Jun 26 04:44:30 PM PDT 24
Finished Jun 26 04:45:13 PM PDT 24
Peak memory 217044 kb
Host smart-43208ad0-d0ff-47c5-bb25-7a7023dcbff6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805678291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1805678291
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1159104497
Short name T126
Test name
Test status
Simulation time 7915865878 ps
CPU time 33 seconds
Started Jun 26 04:44:30 PM PDT 24
Finished Jun 26 04:45:30 PM PDT 24
Peak memory 211584 kb
Host smart-21e92428-6db5-4e83-a8cb-db8fd2039fbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1159104497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1159104497
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1157141067
Short name T283
Test name
Test status
Simulation time 7699355158 ps
CPU time 72.73 seconds
Started Jun 26 04:44:27 PM PDT 24
Finished Jun 26 04:46:06 PM PDT 24
Peak memory 217044 kb
Host smart-c1266e05-7b80-4520-a492-45e2ed094824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157141067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1157141067
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3376825192
Short name T69
Test name
Test status
Simulation time 3443721040 ps
CPU time 42.35 seconds
Started Jun 26 04:44:40 PM PDT 24
Finished Jun 26 04:45:52 PM PDT 24
Peak memory 218400 kb
Host smart-a9c41c2c-bd4d-4165-b07e-5653191d2198
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376825192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3376825192
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3131096394
Short name T113
Test name
Test status
Simulation time 14391567480 ps
CPU time 29.49 seconds
Started Jun 26 04:44:15 PM PDT 24
Finished Jun 26 04:45:05 PM PDT 24
Peak memory 217360 kb
Host smart-f0ff9ea2-7c72-4557-8c4c-7db9f310093a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131096394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3131096394
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.657883046
Short name T40
Test name
Test status
Simulation time 35323028135 ps
CPU time 338.44 seconds
Started Jun 26 04:44:14 PM PDT 24
Finished Jun 26 04:50:13 PM PDT 24
Peak memory 226304 kb
Host smart-eae774b3-f44a-4189-a2f0-d52e799b96b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657883046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.657883046
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1647300862
Short name T171
Test name
Test status
Simulation time 57743881268 ps
CPU time 66.85 seconds
Started Jun 26 04:44:14 PM PDT 24
Finished Jun 26 04:45:42 PM PDT 24
Peak memory 219328 kb
Host smart-cd69788e-7587-4906-8de6-a9044fcc57d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647300862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1647300862
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2127170466
Short name T294
Test name
Test status
Simulation time 1857004946 ps
CPU time 21.05 seconds
Started Jun 26 04:44:12 PM PDT 24
Finished Jun 26 04:44:52 PM PDT 24
Peak memory 219220 kb
Host smart-9581a375-33fa-42f6-a745-20aeccca3dc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2127170466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2127170466
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.378583753
Short name T26
Test name
Test status
Simulation time 12211401775 ps
CPU time 131.48 seconds
Started Jun 26 04:44:15 PM PDT 24
Finished Jun 26 04:46:47 PM PDT 24
Peak memory 238408 kb
Host smart-cf2aa5a9-21e2-46db-83b0-ccc72abfd849
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378583753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.378583753
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3400638006
Short name T68
Test name
Test status
Simulation time 4936070651 ps
CPU time 51.52 seconds
Started Jun 26 04:44:13 PM PDT 24
Finished Jun 26 04:45:24 PM PDT 24
Peak memory 216596 kb
Host smart-e519420f-4dd5-416e-bcf3-12b0808c3092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400638006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3400638006
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.909053493
Short name T215
Test name
Test status
Simulation time 12458438152 ps
CPU time 45.7 seconds
Started Jun 26 04:44:12 PM PDT 24
Finished Jun 26 04:45:16 PM PDT 24
Peak memory 218220 kb
Host smart-963d9187-2712-4dbc-8f79-a7146102e0cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909053493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.909053493
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1254472665
Short name T14
Test name
Test status
Simulation time 26019411041 ps
CPU time 970.89 seconds
Started Jun 26 04:44:17 PM PDT 24
Finished Jun 26 05:00:50 PM PDT 24
Peak memory 235756 kb
Host smart-af222b09-3b20-4453-98c5-ab66a3fd1df3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254472665 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1254472665
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2244180211
Short name T234
Test name
Test status
Simulation time 8160657144 ps
CPU time 24.28 seconds
Started Jun 26 04:44:32 PM PDT 24
Finished Jun 26 04:45:26 PM PDT 24
Peak memory 217428 kb
Host smart-8b80a471-6885-4dcd-9a4e-61a493ef241b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244180211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2244180211
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2323371553
Short name T344
Test name
Test status
Simulation time 11178109633 ps
CPU time 277.58 seconds
Started Jun 26 04:44:30 PM PDT 24
Finished Jun 26 04:49:35 PM PDT 24
Peak memory 228644 kb
Host smart-54840069-56a8-41a1-ba72-52a0f60850fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323371553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2323371553
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1490275634
Short name T214
Test name
Test status
Simulation time 16403586949 ps
CPU time 65.7 seconds
Started Jun 26 04:44:32 PM PDT 24
Finished Jun 26 04:46:07 PM PDT 24
Peak memory 219268 kb
Host smart-677f1990-e5a9-4f46-bf70-cb3900dfd891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490275634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1490275634
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2286903503
Short name T158
Test name
Test status
Simulation time 2501725369 ps
CPU time 24.4 seconds
Started Jun 26 04:44:49 PM PDT 24
Finished Jun 26 04:45:41 PM PDT 24
Peak memory 219324 kb
Host smart-07eb85ca-ea67-4c3d-a109-0dccadd58292
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2286903503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2286903503
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.285873949
Short name T50
Test name
Test status
Simulation time 25078185282 ps
CPU time 66.94 seconds
Started Jun 26 04:44:29 PM PDT 24
Finished Jun 26 04:46:04 PM PDT 24
Peak memory 216820 kb
Host smart-8f5f49c9-b259-4f94-b34a-2fdcfd7a3841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285873949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.285873949
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3762350066
Short name T112
Test name
Test status
Simulation time 2700373520 ps
CPU time 45.98 seconds
Started Jun 26 04:44:30 PM PDT 24
Finished Jun 26 04:45:43 PM PDT 24
Peak memory 218768 kb
Host smart-ad840a2c-2cb6-42cb-a0ff-48415c5299c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762350066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3762350066
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2099159211
Short name T125
Test name
Test status
Simulation time 7227448171 ps
CPU time 19.51 seconds
Started Jun 26 04:44:28 PM PDT 24
Finished Jun 26 04:45:16 PM PDT 24
Peak memory 217372 kb
Host smart-8cc3f2dc-1178-4fa6-9296-c318c32d4685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099159211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2099159211
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1974300913
Short name T166
Test name
Test status
Simulation time 269265388751 ps
CPU time 690.79 seconds
Started Jun 26 04:44:27 PM PDT 24
Finished Jun 26 04:56:25 PM PDT 24
Peak memory 219432 kb
Host smart-acc1cac3-dab3-466e-9bee-2a1c8974da05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974300913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1974300913
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.833179748
Short name T154
Test name
Test status
Simulation time 72232711451 ps
CPU time 58.98 seconds
Started Jun 26 04:44:28 PM PDT 24
Finished Jun 26 04:45:55 PM PDT 24
Peak memory 219392 kb
Host smart-f3bde100-1447-4d53-b641-afbe03e8a8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833179748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.833179748
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.334537333
Short name T328
Test name
Test status
Simulation time 956686664 ps
CPU time 16.33 seconds
Started Jun 26 04:44:29 PM PDT 24
Finished Jun 26 04:45:13 PM PDT 24
Peak memory 218604 kb
Host smart-f854d5fa-7958-437b-87d6-1f00d97a5105
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=334537333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.334537333
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1383901849
Short name T332
Test name
Test status
Simulation time 11907641804 ps
CPU time 66.39 seconds
Started Jun 26 04:44:29 PM PDT 24
Finished Jun 26 04:46:03 PM PDT 24
Peak memory 217136 kb
Host smart-cd22e61c-c01f-4109-8703-784390cde459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383901849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1383901849
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3705623823
Short name T247
Test name
Test status
Simulation time 1505383492 ps
CPU time 23.85 seconds
Started Jun 26 04:44:30 PM PDT 24
Finished Jun 26 04:45:23 PM PDT 24
Peak memory 219232 kb
Host smart-b3d3e819-60a3-4a53-bfc7-933d894e87c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705623823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3705623823
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1494021335
Short name T106
Test name
Test status
Simulation time 6516474065 ps
CPU time 12.98 seconds
Started Jun 26 04:44:36 PM PDT 24
Finished Jun 26 04:45:17 PM PDT 24
Peak memory 217404 kb
Host smart-53845ded-c886-40ea-bce9-73df777895ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494021335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1494021335
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.492240805
Short name T180
Test name
Test status
Simulation time 5708808671 ps
CPU time 51.89 seconds
Started Jun 26 04:44:41 PM PDT 24
Finished Jun 26 04:46:03 PM PDT 24
Peak memory 219132 kb
Host smart-bf796f48-3db4-4807-84d0-fd33e9984d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492240805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.492240805
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1403621723
Short name T303
Test name
Test status
Simulation time 3340339128 ps
CPU time 28.24 seconds
Started Jun 26 04:44:33 PM PDT 24
Finished Jun 26 04:45:30 PM PDT 24
Peak memory 219324 kb
Host smart-e9963e45-6606-4c4d-83dc-07ad22cc7db1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1403621723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1403621723
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2126640238
Short name T278
Test name
Test status
Simulation time 352484891 ps
CPU time 20.86 seconds
Started Jun 26 04:44:33 PM PDT 24
Finished Jun 26 04:45:22 PM PDT 24
Peak memory 216324 kb
Host smart-c334ca4b-8761-4d2e-aa28-0d18a810f582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126640238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2126640238
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3428409811
Short name T250
Test name
Test status
Simulation time 10871971279 ps
CPU time 54.52 seconds
Started Jun 26 04:44:31 PM PDT 24
Finished Jun 26 04:45:54 PM PDT 24
Peak memory 217484 kb
Host smart-a55348c7-a91e-4663-904c-bd576c87d343
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428409811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3428409811
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2484005986
Short name T341
Test name
Test status
Simulation time 2466550689 ps
CPU time 23.59 seconds
Started Jun 26 04:44:40 PM PDT 24
Finished Jun 26 04:45:33 PM PDT 24
Peak memory 217148 kb
Host smart-4c686043-bd32-4302-b9e2-4ca03e9606bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484005986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2484005986
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.562579580
Short name T350
Test name
Test status
Simulation time 962444200229 ps
CPU time 727.38 seconds
Started Jun 26 04:44:39 PM PDT 24
Finished Jun 26 04:57:17 PM PDT 24
Peak memory 219456 kb
Host smart-14e6b9f0-d3fe-4795-8133-1c17940f2823
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562579580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.562579580
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2640381930
Short name T202
Test name
Test status
Simulation time 46372796268 ps
CPU time 48.75 seconds
Started Jun 26 04:44:39 PM PDT 24
Finished Jun 26 04:45:56 PM PDT 24
Peak memory 219304 kb
Host smart-badb5e05-04d7-4339-ad65-975ae0ddd4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640381930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2640381930
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2156532303
Short name T329
Test name
Test status
Simulation time 186581957 ps
CPU time 10.79 seconds
Started Jun 26 04:44:41 PM PDT 24
Finished Jun 26 04:45:22 PM PDT 24
Peak memory 219264 kb
Host smart-826f12a3-724d-4da9-96ab-3a310c144b75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2156532303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2156532303
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2999391736
Short name T204
Test name
Test status
Simulation time 8087968584 ps
CPU time 64.78 seconds
Started Jun 26 04:44:43 PM PDT 24
Finished Jun 26 04:46:16 PM PDT 24
Peak memory 216636 kb
Host smart-e49dd73f-f943-4e40-8d01-170075d6d6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999391736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2999391736
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3019389232
Short name T139
Test name
Test status
Simulation time 5500515612 ps
CPU time 56.05 seconds
Started Jun 26 04:44:36 PM PDT 24
Finished Jun 26 04:46:01 PM PDT 24
Peak memory 219344 kb
Host smart-ec3ad256-08e0-4557-b125-fb28926f46dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019389232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3019389232
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.344890700
Short name T163
Test name
Test status
Simulation time 1380729417 ps
CPU time 10.62 seconds
Started Jun 26 04:44:50 PM PDT 24
Finished Jun 26 04:45:28 PM PDT 24
Peak memory 216960 kb
Host smart-7fad5213-a247-4536-8ec3-464f4bce9030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344890700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.344890700
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.858698859
Short name T244
Test name
Test status
Simulation time 17812811870 ps
CPU time 299.25 seconds
Started Jun 26 04:44:35 PM PDT 24
Finished Jun 26 04:50:04 PM PDT 24
Peak memory 219468 kb
Host smart-4efdc932-5dfb-46af-a029-83f8a9cf5ee3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858698859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.858698859
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.68588397
Short name T318
Test name
Test status
Simulation time 9369695112 ps
CPU time 66.37 seconds
Started Jun 26 04:44:43 PM PDT 24
Finished Jun 26 04:46:19 PM PDT 24
Peak memory 219312 kb
Host smart-b4bf5eb1-eec4-416f-acd0-1f648f63217f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68588397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.68588397
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1141436117
Short name T267
Test name
Test status
Simulation time 2571188367 ps
CPU time 19.15 seconds
Started Jun 26 04:44:44 PM PDT 24
Finished Jun 26 04:45:32 PM PDT 24
Peak memory 219300 kb
Host smart-4274146e-3caf-40d1-8861-27219a837ed3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1141436117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1141436117
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1913881179
Short name T148
Test name
Test status
Simulation time 1376931983 ps
CPU time 19.69 seconds
Started Jun 26 04:44:44 PM PDT 24
Finished Jun 26 04:45:33 PM PDT 24
Peak memory 216680 kb
Host smart-22272ab2-1284-4f55-a2c6-0185df329d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913881179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1913881179
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2426868124
Short name T209
Test name
Test status
Simulation time 33556809772 ps
CPU time 133.57 seconds
Started Jun 26 04:44:39 PM PDT 24
Finished Jun 26 04:47:21 PM PDT 24
Peak memory 227520 kb
Host smart-254deb61-11c8-4084-94fe-78a85192697d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426868124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2426868124
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.443393645
Short name T25
Test name
Test status
Simulation time 3857164305 ps
CPU time 32.16 seconds
Started Jun 26 04:44:46 PM PDT 24
Finished Jun 26 04:45:47 PM PDT 24
Peak memory 217260 kb
Host smart-51315b24-e448-4518-b654-36bb54f18f0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443393645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.443393645
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.591640582
Short name T226
Test name
Test status
Simulation time 7166394175 ps
CPU time 202.5 seconds
Started Jun 26 04:44:44 PM PDT 24
Finished Jun 26 04:48:36 PM PDT 24
Peak memory 219516 kb
Host smart-f389511d-fcaf-447d-bd66-4851775f176e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591640582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.591640582
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2644420302
Short name T270
Test name
Test status
Simulation time 38113098472 ps
CPU time 55.13 seconds
Started Jun 26 04:44:51 PM PDT 24
Finished Jun 26 04:46:14 PM PDT 24
Peak memory 219228 kb
Host smart-9d9b7d93-9c23-4e52-84c6-c60a29e56337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644420302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2644420302
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2733858940
Short name T306
Test name
Test status
Simulation time 13851922531 ps
CPU time 25.34 seconds
Started Jun 26 04:44:50 PM PDT 24
Finished Jun 26 04:45:43 PM PDT 24
Peak memory 212068 kb
Host smart-a7cc493b-235c-4d08-a48c-af07714284bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2733858940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2733858940
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.315447518
Short name T279
Test name
Test status
Simulation time 45876224499 ps
CPU time 79.37 seconds
Started Jun 26 04:44:51 PM PDT 24
Finished Jun 26 04:46:38 PM PDT 24
Peak memory 217204 kb
Host smart-2c2c9ebf-0f81-4a12-bd9b-d382d4b3a891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315447518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.315447518
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1993424855
Short name T266
Test name
Test status
Simulation time 25230386033 ps
CPU time 214.93 seconds
Started Jun 26 04:44:52 PM PDT 24
Finished Jun 26 04:48:54 PM PDT 24
Peak memory 222708 kb
Host smart-690110a1-5e05-4511-b9f8-67eca0e8674b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993424855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1993424855
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2659098788
Short name T246
Test name
Test status
Simulation time 6583996306 ps
CPU time 10.69 seconds
Started Jun 26 04:44:42 PM PDT 24
Finished Jun 26 04:45:22 PM PDT 24
Peak memory 217508 kb
Host smart-6e6b501c-df22-402d-ba75-aeed167da6d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659098788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2659098788
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.723727824
Short name T292
Test name
Test status
Simulation time 6783389767 ps
CPU time 240.52 seconds
Started Jun 26 04:44:51 PM PDT 24
Finished Jun 26 04:49:19 PM PDT 24
Peak memory 242764 kb
Host smart-7b46a696-77db-4353-9460-92e9f3d5a6c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723727824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.723727824
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4178986417
Short name T3
Test name
Test status
Simulation time 5108534674 ps
CPU time 48.34 seconds
Started Jun 26 04:44:44 PM PDT 24
Finished Jun 26 04:46:01 PM PDT 24
Peak memory 219324 kb
Host smart-b036bce5-e6e6-4668-8d85-dfdcef6530fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178986417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4178986417
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1699018912
Short name T227
Test name
Test status
Simulation time 1334349068 ps
CPU time 14.87 seconds
Started Jun 26 04:44:42 PM PDT 24
Finished Jun 26 04:45:26 PM PDT 24
Peak memory 211672 kb
Host smart-0b39eb59-abd5-4887-9fca-511bf2264c6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1699018912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1699018912
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2254429842
Short name T232
Test name
Test status
Simulation time 3319020797 ps
CPU time 32.41 seconds
Started Jun 26 04:44:47 PM PDT 24
Finished Jun 26 04:45:48 PM PDT 24
Peak memory 216212 kb
Host smart-358b2cfc-a70d-4c57-9f2a-d51929a8f322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254429842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2254429842
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2782157802
Short name T338
Test name
Test status
Simulation time 13040865025 ps
CPU time 34.91 seconds
Started Jun 26 04:44:49 PM PDT 24
Finished Jun 26 04:45:52 PM PDT 24
Peak memory 219240 kb
Host smart-14265e7f-f42c-42fa-85c6-aa6ab694fd68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782157802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2782157802
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3727480931
Short name T289
Test name
Test status
Simulation time 661381005 ps
CPU time 8.21 seconds
Started Jun 26 04:44:51 PM PDT 24
Finished Jun 26 04:45:27 PM PDT 24
Peak memory 216944 kb
Host smart-8fafeea5-187c-43f5-b8fa-25e7e5b331c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727480931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3727480931
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.500630593
Short name T276
Test name
Test status
Simulation time 118451470903 ps
CPU time 1138.19 seconds
Started Jun 26 04:44:42 PM PDT 24
Finished Jun 26 05:04:10 PM PDT 24
Peak memory 234648 kb
Host smart-29404eee-bbe3-4bff-a675-c010ffdbd20f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500630593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.500630593
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2408247286
Short name T248
Test name
Test status
Simulation time 62481171580 ps
CPU time 57.48 seconds
Started Jun 26 04:44:42 PM PDT 24
Finished Jun 26 04:46:09 PM PDT 24
Peak memory 219372 kb
Host smart-c4ed0942-30aa-441a-827f-72065cd0884f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408247286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2408247286
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1147429376
Short name T124
Test name
Test status
Simulation time 2909501625 ps
CPU time 18.44 seconds
Started Jun 26 04:44:46 PM PDT 24
Finished Jun 26 04:45:33 PM PDT 24
Peak memory 217728 kb
Host smart-4251d5d4-8d57-4249-80a5-b2f5babb4eb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1147429376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1147429376
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3888277165
Short name T70
Test name
Test status
Simulation time 356442808 ps
CPU time 20.08 seconds
Started Jun 26 04:44:50 PM PDT 24
Finished Jun 26 04:45:37 PM PDT 24
Peak memory 216468 kb
Host smart-76541797-a3be-4fdb-a781-1dca406ebcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888277165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3888277165
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1864390545
Short name T262
Test name
Test status
Simulation time 43100843364 ps
CPU time 87.06 seconds
Started Jun 26 04:44:52 PM PDT 24
Finished Jun 26 04:46:46 PM PDT 24
Peak memory 219408 kb
Host smart-6cbb93ba-0db0-438b-bd0f-67f1b62c524e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864390545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1864390545
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1654679380
Short name T29
Test name
Test status
Simulation time 1031219360 ps
CPU time 9.85 seconds
Started Jun 26 04:44:56 PM PDT 24
Finished Jun 26 04:45:30 PM PDT 24
Peak memory 217188 kb
Host smart-cb7bf3a3-2790-4d09-a79a-aa597c044499
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654679380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1654679380
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.803065127
Short name T189
Test name
Test status
Simulation time 66033885405 ps
CPU time 256.07 seconds
Started Jun 26 04:44:48 PM PDT 24
Finished Jun 26 04:49:32 PM PDT 24
Peak memory 219208 kb
Host smart-58861ce8-b4d3-446d-98b8-b91f6d3c2bbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803065127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.803065127
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2025830793
Short name T298
Test name
Test status
Simulation time 29558750861 ps
CPU time 64.54 seconds
Started Jun 26 04:44:44 PM PDT 24
Finished Jun 26 04:46:18 PM PDT 24
Peak memory 219160 kb
Host smart-b67d977c-36fc-4c67-a8b8-08be9ce2fdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025830793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2025830793
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1066091468
Short name T229
Test name
Test status
Simulation time 7068328869 ps
CPU time 30.9 seconds
Started Jun 26 04:44:43 PM PDT 24
Finished Jun 26 04:45:44 PM PDT 24
Peak memory 211900 kb
Host smart-d9fdadea-b5d1-4ba5-97d5-0752e2569332
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1066091468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1066091468
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3326322933
Short name T274
Test name
Test status
Simulation time 4822281584 ps
CPU time 36.82 seconds
Started Jun 26 04:44:42 PM PDT 24
Finished Jun 26 04:45:48 PM PDT 24
Peak memory 216812 kb
Host smart-4091aeb9-8b19-4482-a321-a60014c9ec07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326322933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3326322933
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.4081610238
Short name T277
Test name
Test status
Simulation time 2095633425 ps
CPU time 24.58 seconds
Started Jun 26 04:44:43 PM PDT 24
Finished Jun 26 04:45:37 PM PDT 24
Peak memory 214796 kb
Host smart-f5f28962-8a2c-45aa-b9d7-8c7950b0c786
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081610238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.4081610238
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2275098676
Short name T316
Test name
Test status
Simulation time 3887521490 ps
CPU time 31.46 seconds
Started Jun 26 04:44:42 PM PDT 24
Finished Jun 26 04:45:43 PM PDT 24
Peak memory 217232 kb
Host smart-581c888a-0fcd-4e21-a4f9-11dd429520aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275098676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2275098676
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4097518047
Short name T172
Test name
Test status
Simulation time 48916555983 ps
CPU time 361.13 seconds
Started Jun 26 04:44:46 PM PDT 24
Finished Jun 26 04:51:16 PM PDT 24
Peak memory 242780 kb
Host smart-b7e3fedf-2f3b-4b47-86e6-f64c8e79c4fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097518047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.4097518047
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1671970567
Short name T312
Test name
Test status
Simulation time 5353930353 ps
CPU time 49.8 seconds
Started Jun 26 04:44:42 PM PDT 24
Finished Jun 26 04:46:01 PM PDT 24
Peak memory 219388 kb
Host smart-1c0d6b69-7c29-4f0d-9881-1b6f158dc0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671970567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1671970567
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3551383659
Short name T120
Test name
Test status
Simulation time 14910381888 ps
CPU time 25.25 seconds
Started Jun 26 04:44:42 PM PDT 24
Finished Jun 26 04:45:37 PM PDT 24
Peak memory 211988 kb
Host smart-5740abe4-7b71-4f1f-8848-ce76caa7ddfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3551383659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3551383659
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.678317229
Short name T115
Test name
Test status
Simulation time 352813136 ps
CPU time 19.87 seconds
Started Jun 26 04:44:42 PM PDT 24
Finished Jun 26 04:45:31 PM PDT 24
Peak memory 216336 kb
Host smart-68ff97e5-11d7-4daf-96a4-53430261a764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678317229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.678317229
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.41982230
Short name T288
Test name
Test status
Simulation time 6729528469 ps
CPU time 69.85 seconds
Started Jun 26 04:44:50 PM PDT 24
Finished Jun 26 04:46:27 PM PDT 24
Peak memory 217756 kb
Host smart-9efab465-2e78-4167-a6e3-108eda0599bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41982230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 29.rom_ctrl_stress_all.41982230
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3070517753
Short name T15
Test name
Test status
Simulation time 58311788068 ps
CPU time 588.5 seconds
Started Jun 26 04:44:51 PM PDT 24
Finished Jun 26 04:55:07 PM PDT 24
Peak memory 232356 kb
Host smart-e4c56b70-cd57-4121-9505-b9a0b6dd9040
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070517753 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3070517753
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3924553348
Short name T140
Test name
Test status
Simulation time 3256898876 ps
CPU time 18.01 seconds
Started Jun 26 04:44:15 PM PDT 24
Finished Jun 26 04:44:53 PM PDT 24
Peak memory 217144 kb
Host smart-b81efd5b-ca6c-473f-8394-f6884745298d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924553348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3924553348
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2013491771
Short name T257
Test name
Test status
Simulation time 213060754498 ps
CPU time 297.58 seconds
Started Jun 26 04:44:17 PM PDT 24
Finished Jun 26 04:49:35 PM PDT 24
Peak memory 225792 kb
Host smart-9ba458c1-f81a-4310-9029-fc4e6bf9483e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013491771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2013491771
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.232487803
Short name T339
Test name
Test status
Simulation time 12667561424 ps
CPU time 38.2 seconds
Started Jun 26 04:44:17 PM PDT 24
Finished Jun 26 04:45:17 PM PDT 24
Peak memory 219272 kb
Host smart-80077bb8-3e32-4518-9b34-80e3180b37e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232487803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.232487803
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3441233230
Short name T116
Test name
Test status
Simulation time 459762355 ps
CPU time 10.4 seconds
Started Jun 26 04:44:14 PM PDT 24
Finished Jun 26 04:44:46 PM PDT 24
Peak memory 219260 kb
Host smart-103a3eed-e284-41a3-9424-b9a8e3c0b794
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3441233230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3441233230
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1726181466
Short name T22
Test name
Test status
Simulation time 1173145411 ps
CPU time 121.97 seconds
Started Jun 26 04:44:15 PM PDT 24
Finished Jun 26 04:46:37 PM PDT 24
Peak memory 235144 kb
Host smart-807aa7d1-41d3-44d1-952f-ec08fd7d8823
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726181466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1726181466
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.323767441
Short name T295
Test name
Test status
Simulation time 28405055866 ps
CPU time 61.61 seconds
Started Jun 26 04:44:17 PM PDT 24
Finished Jun 26 04:45:41 PM PDT 24
Peak memory 217268 kb
Host smart-90564870-d1c5-4aa2-b66c-8cac21dc0479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323767441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.323767441
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.752881120
Short name T137
Test name
Test status
Simulation time 5603192223 ps
CPU time 65.12 seconds
Started Jun 26 04:44:17 PM PDT 24
Finished Jun 26 04:45:42 PM PDT 24
Peak memory 217800 kb
Host smart-1f60f765-061b-40e5-b182-947ebec75724
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752881120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.752881120
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3783237119
Short name T205
Test name
Test status
Simulation time 9182955013 ps
CPU time 22.4 seconds
Started Jun 26 04:44:59 PM PDT 24
Finished Jun 26 04:45:44 PM PDT 24
Peak memory 217416 kb
Host smart-bf5bde22-022b-4dee-aa14-2d92f50ff5d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783237119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3783237119
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1740037002
Short name T33
Test name
Test status
Simulation time 118890368732 ps
CPU time 454.7 seconds
Started Jun 26 04:44:51 PM PDT 24
Finished Jun 26 04:52:53 PM PDT 24
Peak memory 235580 kb
Host smart-47eb7555-b59f-4c3a-9093-5343756ae70c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740037002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1740037002
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3472437103
Short name T340
Test name
Test status
Simulation time 3071556026 ps
CPU time 37.07 seconds
Started Jun 26 04:44:47 PM PDT 24
Finished Jun 26 04:45:53 PM PDT 24
Peak memory 219304 kb
Host smart-74a6af57-e8e6-4e97-92ad-fe1c4f8f6a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472437103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3472437103
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2306211662
Short name T260
Test name
Test status
Simulation time 4295431609 ps
CPU time 32.23 seconds
Started Jun 26 04:44:46 PM PDT 24
Finished Jun 26 04:45:47 PM PDT 24
Peak memory 219296 kb
Host smart-3f2fc41e-57e4-472e-88dd-0fd554a40374
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2306211662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2306211662
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1542217832
Short name T213
Test name
Test status
Simulation time 5563246324 ps
CPU time 25.74 seconds
Started Jun 26 04:44:47 PM PDT 24
Finished Jun 26 04:45:41 PM PDT 24
Peak memory 216420 kb
Host smart-217fc7ae-5ed6-422b-9c58-f39475ae41fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542217832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1542217832
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1469478275
Short name T317
Test name
Test status
Simulation time 4318678817 ps
CPU time 50.11 seconds
Started Jun 26 04:44:46 PM PDT 24
Finished Jun 26 04:46:05 PM PDT 24
Peak memory 220832 kb
Host smart-c00b1a54-27f5-492b-8efa-5972afd4623b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469478275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1469478275
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1376151295
Short name T160
Test name
Test status
Simulation time 176107392 ps
CPU time 8.34 seconds
Started Jun 26 04:44:50 PM PDT 24
Finished Jun 26 04:45:25 PM PDT 24
Peak memory 218208 kb
Host smart-368c763e-f76b-4069-a184-324b6e237250
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376151295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1376151295
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1214968418
Short name T111
Test name
Test status
Simulation time 57786664213 ps
CPU time 563.07 seconds
Started Jun 26 04:44:56 PM PDT 24
Finished Jun 26 04:54:44 PM PDT 24
Peak memory 237916 kb
Host smart-49822ac9-eac4-48ff-91ff-e9aa67196933
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214968418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1214968418
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2341875124
Short name T192
Test name
Test status
Simulation time 18401607796 ps
CPU time 47.47 seconds
Started Jun 26 04:45:00 PM PDT 24
Finished Jun 26 04:46:09 PM PDT 24
Peak memory 219376 kb
Host smart-576977a5-de7e-4149-8538-e6d060107d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341875124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2341875124
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.558403188
Short name T212
Test name
Test status
Simulation time 2820817697 ps
CPU time 25.94 seconds
Started Jun 26 04:44:56 PM PDT 24
Finished Jun 26 04:45:46 PM PDT 24
Peak memory 211240 kb
Host smart-fbd158c2-520a-40bf-83ac-23031a44b74e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=558403188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.558403188
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.363710448
Short name T105
Test name
Test status
Simulation time 7102617956 ps
CPU time 59.95 seconds
Started Jun 26 04:44:54 PM PDT 24
Finished Jun 26 04:46:20 PM PDT 24
Peak memory 216196 kb
Host smart-51c85687-3bc9-40d0-b34f-d51f6bb5b243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363710448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.363710448
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2340398156
Short name T286
Test name
Test status
Simulation time 1597976083 ps
CPU time 24.51 seconds
Started Jun 26 04:44:56 PM PDT 24
Finished Jun 26 04:45:45 PM PDT 24
Peak memory 219244 kb
Host smart-fb6ab6ab-e7d8-4bbd-b36c-689ccf73a0e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340398156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2340398156
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3444775383
Short name T44
Test name
Test status
Simulation time 182501095972 ps
CPU time 5756.71 seconds
Started Jun 26 04:44:59 PM PDT 24
Finished Jun 26 06:21:19 PM PDT 24
Peak memory 240388 kb
Host smart-08a7cd23-1d36-483b-a192-e2eab834b083
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444775383 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.3444775383
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2981497775
Short name T253
Test name
Test status
Simulation time 16806297422 ps
CPU time 31.91 seconds
Started Jun 26 04:45:00 PM PDT 24
Finished Jun 26 04:45:54 PM PDT 24
Peak memory 217424 kb
Host smart-9f29ebd2-0630-456a-89c0-0600c756b527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981497775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2981497775
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.370597090
Short name T252
Test name
Test status
Simulation time 1435355948 ps
CPU time 19.51 seconds
Started Jun 26 04:44:57 PM PDT 24
Finished Jun 26 04:45:41 PM PDT 24
Peak memory 219304 kb
Host smart-fad5bb04-56e2-427c-b547-273b1b4690b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370597090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.370597090
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2608835972
Short name T159
Test name
Test status
Simulation time 3469707516 ps
CPU time 29.21 seconds
Started Jun 26 04:44:54 PM PDT 24
Finished Jun 26 04:45:49 PM PDT 24
Peak memory 211252 kb
Host smart-8c118b95-4f43-44c3-9155-5ff9fa1fc36b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2608835972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2608835972
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1314569954
Short name T264
Test name
Test status
Simulation time 689557876 ps
CPU time 19.9 seconds
Started Jun 26 04:44:52 PM PDT 24
Finished Jun 26 04:45:38 PM PDT 24
Peak memory 216068 kb
Host smart-3a395f20-e89b-4cf1-8a37-3383e9a636ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314569954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1314569954
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1780939070
Short name T322
Test name
Test status
Simulation time 894083911 ps
CPU time 53.36 seconds
Started Jun 26 04:44:58 PM PDT 24
Finished Jun 26 04:46:15 PM PDT 24
Peak memory 227444 kb
Host smart-4cee70f2-a3b6-489e-b7e2-fa6a62c3c5de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780939070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1780939070
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.269135125
Short name T117
Test name
Test status
Simulation time 29188551995 ps
CPU time 31.73 seconds
Started Jun 26 04:44:55 PM PDT 24
Finished Jun 26 04:45:52 PM PDT 24
Peak memory 213272 kb
Host smart-0192b97b-31c9-479d-8d95-19792beeffa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269135125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.269135125
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3023712509
Short name T39
Test name
Test status
Simulation time 117120671201 ps
CPU time 353.02 seconds
Started Jun 26 04:44:51 PM PDT 24
Finished Jun 26 04:51:11 PM PDT 24
Peak memory 238432 kb
Host smart-d16498d1-3821-46f3-bc91-6a6e2d3c4203
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023712509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3023712509
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2000970095
Short name T37
Test name
Test status
Simulation time 1320464101 ps
CPU time 19.08 seconds
Started Jun 26 04:45:06 PM PDT 24
Finished Jun 26 04:45:43 PM PDT 24
Peak memory 219160 kb
Host smart-da8592ae-695f-4027-af83-dbbebbaa4568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000970095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2000970095
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.401010425
Short name T5
Test name
Test status
Simulation time 20868422622 ps
CPU time 33.27 seconds
Started Jun 26 04:44:55 PM PDT 24
Finished Jun 26 04:45:53 PM PDT 24
Peak memory 217852 kb
Host smart-02904534-8ea3-469e-9a0c-2f0841bac7ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=401010425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.401010425
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2890271045
Short name T142
Test name
Test status
Simulation time 33539819199 ps
CPU time 82.38 seconds
Started Jun 26 04:44:57 PM PDT 24
Finished Jun 26 04:46:43 PM PDT 24
Peak memory 217216 kb
Host smart-b6a9d7de-177a-45eb-87b9-febde895f610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890271045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2890271045
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2675587110
Short name T73
Test name
Test status
Simulation time 3118511115 ps
CPU time 67.43 seconds
Started Jun 26 04:44:56 PM PDT 24
Finished Jun 26 04:46:28 PM PDT 24
Peak memory 219340 kb
Host smart-60ba537d-a1ad-43e2-8325-3c766c6e4f83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675587110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2675587110
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3403264963
Short name T273
Test name
Test status
Simulation time 7870613183 ps
CPU time 29.59 seconds
Started Jun 26 04:45:04 PM PDT 24
Finished Jun 26 04:45:53 PM PDT 24
Peak memory 217448 kb
Host smart-bdeda47d-ca76-40d6-8937-0abbc90003a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403264963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3403264963
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.63380898
Short name T9
Test name
Test status
Simulation time 62265604802 ps
CPU time 740.64 seconds
Started Jun 26 04:44:55 PM PDT 24
Finished Jun 26 04:57:41 PM PDT 24
Peak memory 239084 kb
Host smart-8b1da958-8cb6-48df-873f-22b9f56d2662
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63380898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_co
rrupt_sig_fatal_chk.63380898
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3564533149
Short name T10
Test name
Test status
Simulation time 67299279107 ps
CPU time 56.45 seconds
Started Jun 26 04:44:57 PM PDT 24
Finished Jun 26 04:46:17 PM PDT 24
Peak memory 219288 kb
Host smart-53de568a-f550-49f8-955c-ef743829cea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564533149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3564533149
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2648880634
Short name T20
Test name
Test status
Simulation time 467904142 ps
CPU time 10.4 seconds
Started Jun 26 04:45:00 PM PDT 24
Finished Jun 26 04:45:32 PM PDT 24
Peak memory 219204 kb
Host smart-2fad7218-a5a2-4541-9b92-684788523f0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2648880634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2648880634
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3512473944
Short name T174
Test name
Test status
Simulation time 7357246326 ps
CPU time 63.31 seconds
Started Jun 26 04:44:56 PM PDT 24
Finished Jun 26 04:46:23 PM PDT 24
Peak memory 217472 kb
Host smart-541b9d32-8009-4df8-a90f-7708efdc52e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512473944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3512473944
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.877039199
Short name T175
Test name
Test status
Simulation time 13752227541 ps
CPU time 55.66 seconds
Started Jun 26 04:45:06 PM PDT 24
Finished Jun 26 04:46:19 PM PDT 24
Peak memory 216640 kb
Host smart-ab318808-0c2e-46b0-b1cb-6572b0cce7d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877039199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.877039199
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.788715336
Short name T287
Test name
Test status
Simulation time 522053054 ps
CPU time 11.72 seconds
Started Jun 26 04:44:58 PM PDT 24
Finished Jun 26 04:45:33 PM PDT 24
Peak memory 217024 kb
Host smart-56ea7b25-1faa-4db9-8c02-5c89a418f11d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788715336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.788715336
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.558157918
Short name T259
Test name
Test status
Simulation time 152685686347 ps
CPU time 545.57 seconds
Started Jun 26 04:44:57 PM PDT 24
Finished Jun 26 04:54:27 PM PDT 24
Peak memory 240548 kb
Host smart-43f84d09-0f77-43e0-a9ef-84ee5ff03c45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558157918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.558157918
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3289323346
Short name T346
Test name
Test status
Simulation time 4619852631 ps
CPU time 45.52 seconds
Started Jun 26 04:44:55 PM PDT 24
Finished Jun 26 04:46:05 PM PDT 24
Peak memory 219328 kb
Host smart-12dce158-25bf-4658-b6db-cee261de1aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289323346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3289323346
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2815336460
Short name T224
Test name
Test status
Simulation time 17259389869 ps
CPU time 30.05 seconds
Started Jun 26 04:44:59 PM PDT 24
Finished Jun 26 04:45:51 PM PDT 24
Peak memory 217672 kb
Host smart-faad344b-ea7b-45b5-a951-21d138fdfa46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2815336460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2815336460
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3763333694
Short name T71
Test name
Test status
Simulation time 27000482564 ps
CPU time 65.47 seconds
Started Jun 26 04:44:56 PM PDT 24
Finished Jun 26 04:46:26 PM PDT 24
Peak memory 217276 kb
Host smart-2bbbd623-6516-4302-88be-4dd9898f00c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763333694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3763333694
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.84405253
Short name T157
Test name
Test status
Simulation time 3066899967 ps
CPU time 34.09 seconds
Started Jun 26 04:44:53 PM PDT 24
Finished Jun 26 04:45:53 PM PDT 24
Peak memory 216916 kb
Host smart-630abdfd-a198-4506-a317-03643c0f9cd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84405253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 35.rom_ctrl_stress_all.84405253
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3842207407
Short name T194
Test name
Test status
Simulation time 3430697829 ps
CPU time 13.78 seconds
Started Jun 26 04:44:57 PM PDT 24
Finished Jun 26 04:45:35 PM PDT 24
Peak memory 217156 kb
Host smart-d22dc69e-065a-46d2-ae1f-eb1a744094fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842207407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3842207407
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1806195754
Short name T191
Test name
Test status
Simulation time 46322268659 ps
CPU time 533.67 seconds
Started Jun 26 04:44:59 PM PDT 24
Finished Jun 26 04:54:15 PM PDT 24
Peak memory 241912 kb
Host smart-9e03ba66-84c0-48ff-9662-3a128a5c6624
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806195754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1806195754
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3048929552
Short name T251
Test name
Test status
Simulation time 27960878621 ps
CPU time 55.24 seconds
Started Jun 26 04:44:56 PM PDT 24
Finished Jun 26 04:46:15 PM PDT 24
Peak memory 219372 kb
Host smart-26b3d6fe-2da7-480c-9f69-3602e5ebce59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048929552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3048929552
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2879281279
Short name T150
Test name
Test status
Simulation time 961786579 ps
CPU time 15.67 seconds
Started Jun 26 04:44:59 PM PDT 24
Finished Jun 26 04:45:37 PM PDT 24
Peak memory 219256 kb
Host smart-2d7ca397-1a55-4f5b-9bc5-34c9be096338
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2879281279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2879281279
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3112536446
Short name T132
Test name
Test status
Simulation time 28220252671 ps
CPU time 61.45 seconds
Started Jun 26 04:44:57 PM PDT 24
Finished Jun 26 04:46:22 PM PDT 24
Peak memory 216684 kb
Host smart-f7c66167-0ea7-409b-ad60-04bf4e6cf749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112536446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3112536446
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.4078572712
Short name T296
Test name
Test status
Simulation time 2573515872 ps
CPU time 31.22 seconds
Started Jun 26 04:44:58 PM PDT 24
Finished Jun 26 04:45:53 PM PDT 24
Peak memory 214580 kb
Host smart-4681b36e-928e-4409-b190-d98dc5f8f585
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078572712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.4078572712
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.4258608028
Short name T290
Test name
Test status
Simulation time 174333969 ps
CPU time 8.32 seconds
Started Jun 26 04:45:00 PM PDT 24
Finished Jun 26 04:45:30 PM PDT 24
Peak memory 217984 kb
Host smart-a6ad3183-440a-4045-9786-3476e4889138
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258608028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.4258608028
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.99444390
Short name T225
Test name
Test status
Simulation time 430591860096 ps
CPU time 988.79 seconds
Started Jun 26 04:44:59 PM PDT 24
Finished Jun 26 05:01:50 PM PDT 24
Peak memory 240488 kb
Host smart-e0aa6457-9bc6-4259-9e5d-1477571db001
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99444390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_co
rrupt_sig_fatal_chk.99444390
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3305128311
Short name T173
Test name
Test status
Simulation time 8866145033 ps
CPU time 69.3 seconds
Started Jun 26 04:45:06 PM PDT 24
Finished Jun 26 04:46:33 PM PDT 24
Peak memory 219216 kb
Host smart-150739ab-99e1-49b3-8d56-c45119e3e04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305128311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3305128311
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2133744485
Short name T155
Test name
Test status
Simulation time 7709629644 ps
CPU time 30.23 seconds
Started Jun 26 04:44:57 PM PDT 24
Finished Jun 26 04:45:51 PM PDT 24
Peak memory 219228 kb
Host smart-7e0e3ed8-f67c-4918-bcb1-6cef40f8d266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2133744485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2133744485
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2154677480
Short name T293
Test name
Test status
Simulation time 28890560906 ps
CPU time 77.31 seconds
Started Jun 26 04:45:06 PM PDT 24
Finished Jun 26 04:46:41 PM PDT 24
Peak memory 217152 kb
Host smart-234fe5fd-5104-4a29-aca4-73cb3e230aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154677480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2154677480
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3591931351
Short name T164
Test name
Test status
Simulation time 12362759278 ps
CPU time 78.38 seconds
Started Jun 26 04:44:59 PM PDT 24
Finished Jun 26 04:46:40 PM PDT 24
Peak memory 219332 kb
Host smart-42da13b0-e19c-4baf-ae9f-22a7755f6e50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591931351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3591931351
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3854191403
Short name T233
Test name
Test status
Simulation time 8514302813 ps
CPU time 20.65 seconds
Started Jun 26 04:45:04 PM PDT 24
Finished Jun 26 04:45:44 PM PDT 24
Peak memory 217488 kb
Host smart-4572d1e5-a378-4223-b316-b4d43671c8ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854191403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3854191403
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.28602694
Short name T255
Test name
Test status
Simulation time 7633145753 ps
CPU time 152.09 seconds
Started Jun 26 04:44:56 PM PDT 24
Finished Jun 26 04:47:52 PM PDT 24
Peak memory 238688 kb
Host smart-7701d49e-7097-4e32-bd77-ec42c2aa10fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28602694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_co
rrupt_sig_fatal_chk.28602694
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2042783205
Short name T238
Test name
Test status
Simulation time 4916578527 ps
CPU time 47.12 seconds
Started Jun 26 04:45:00 PM PDT 24
Finished Jun 26 04:46:09 PM PDT 24
Peak memory 219328 kb
Host smart-fa7752fb-be01-47c3-9f78-c4824c1804b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042783205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2042783205
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3870910525
Short name T265
Test name
Test status
Simulation time 186127163 ps
CPU time 10.31 seconds
Started Jun 26 04:44:56 PM PDT 24
Finished Jun 26 04:45:30 PM PDT 24
Peak memory 219264 kb
Host smart-0ce85218-ee3f-4e6c-bc73-76d8e2cb4c5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3870910525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3870910525
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.801173518
Short name T331
Test name
Test status
Simulation time 3956060847 ps
CPU time 47.58 seconds
Started Jun 26 04:45:06 PM PDT 24
Finished Jun 26 04:46:11 PM PDT 24
Peak memory 215724 kb
Host smart-a172231b-dec0-45e8-8e37-5048aad48703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801173518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.801173518
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1899086828
Short name T228
Test name
Test status
Simulation time 12112925677 ps
CPU time 128.72 seconds
Started Jun 26 04:44:57 PM PDT 24
Finished Jun 26 04:47:30 PM PDT 24
Peak memory 220312 kb
Host smart-4c3164ee-52b5-426f-ae09-c8f9293268e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899086828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1899086828
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1872396380
Short name T245
Test name
Test status
Simulation time 6602469997 ps
CPU time 17.52 seconds
Started Jun 26 04:44:56 PM PDT 24
Finished Jun 26 04:45:38 PM PDT 24
Peak memory 217424 kb
Host smart-375c243b-f2f7-4150-af3f-5020ee9bbff1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872396380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1872396380
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.934210207
Short name T271
Test name
Test status
Simulation time 24623993141 ps
CPU time 175.12 seconds
Started Jun 26 04:45:00 PM PDT 24
Finished Jun 26 04:48:17 PM PDT 24
Peak memory 217060 kb
Host smart-4166b772-4e6c-4c38-8380-b84451c74414
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934210207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_c
orrupt_sig_fatal_chk.934210207
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.176184556
Short name T49
Test name
Test status
Simulation time 30216064918 ps
CPU time 65.44 seconds
Started Jun 26 04:45:00 PM PDT 24
Finished Jun 26 04:46:27 PM PDT 24
Peak memory 219236 kb
Host smart-f76c0c9a-3d32-45de-a8d8-b85233a169e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176184556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.176184556
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1594181505
Short name T182
Test name
Test status
Simulation time 2891569483 ps
CPU time 25.98 seconds
Started Jun 26 04:44:57 PM PDT 24
Finished Jun 26 04:45:47 PM PDT 24
Peak memory 211432 kb
Host smart-21c6bf93-2d70-4a23-8cf0-8262f18ccd50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1594181505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1594181505
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1351724168
Short name T230
Test name
Test status
Simulation time 1432508860 ps
CPU time 19.72 seconds
Started Jun 26 04:44:53 PM PDT 24
Finished Jun 26 04:45:39 PM PDT 24
Peak memory 216548 kb
Host smart-69611060-3741-4ada-a6b7-abbc439ae46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351724168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1351724168
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2621090548
Short name T141
Test name
Test status
Simulation time 66783981810 ps
CPU time 138.57 seconds
Started Jun 26 04:44:53 PM PDT 24
Finished Jun 26 04:47:38 PM PDT 24
Peak memory 220184 kb
Host smart-ec619f58-4af5-4700-9502-50b39f255d64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621090548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2621090548
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.4072720322
Short name T177
Test name
Test status
Simulation time 1100966537 ps
CPU time 8.13 seconds
Started Jun 26 04:44:19 PM PDT 24
Finished Jun 26 04:44:49 PM PDT 24
Peak memory 217336 kb
Host smart-1fc014d8-a97c-4f1d-9715-d24e30b68d89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072720322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.4072720322
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.387487224
Short name T2
Test name
Test status
Simulation time 22806107377 ps
CPU time 312.96 seconds
Started Jun 26 04:44:16 PM PDT 24
Finished Jun 26 04:49:50 PM PDT 24
Peak memory 239356 kb
Host smart-83662888-de25-4ce3-af48-d48e413a3996
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387487224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.387487224
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1456880470
Short name T168
Test name
Test status
Simulation time 26194897068 ps
CPU time 59.15 seconds
Started Jun 26 04:44:20 PM PDT 24
Finished Jun 26 04:45:42 PM PDT 24
Peak memory 219528 kb
Host smart-0988f982-9c34-45ba-bb39-e2af5702bbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456880470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1456880470
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3162834961
Short name T242
Test name
Test status
Simulation time 3461870770 ps
CPU time 15.68 seconds
Started Jun 26 04:44:19 PM PDT 24
Finished Jun 26 04:44:57 PM PDT 24
Peak memory 217632 kb
Host smart-1ced6e82-86ca-43e8-a211-28e3e9ca447f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3162834961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3162834961
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.444013263
Short name T27
Test name
Test status
Simulation time 1295566638 ps
CPU time 222.07 seconds
Started Jun 26 04:44:23 PM PDT 24
Finished Jun 26 04:48:29 PM PDT 24
Peak memory 235868 kb
Host smart-d4d5aa1a-ef57-438d-91da-bee20e1fc0fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444013263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.444013263
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3923694386
Short name T114
Test name
Test status
Simulation time 2086977623 ps
CPU time 35.29 seconds
Started Jun 26 04:44:16 PM PDT 24
Finished Jun 26 04:45:12 PM PDT 24
Peak memory 216608 kb
Host smart-844663d4-a7d8-4104-ae3e-664fda69ec9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923694386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3923694386
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2741273531
Short name T146
Test name
Test status
Simulation time 13122236607 ps
CPU time 39 seconds
Started Jun 26 04:44:16 PM PDT 24
Finished Jun 26 04:45:16 PM PDT 24
Peak memory 219132 kb
Host smart-c9eba156-3965-434a-b20a-6eb0c484e2ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741273531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2741273531
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2715293202
Short name T136
Test name
Test status
Simulation time 3096912904 ps
CPU time 25.54 seconds
Started Jun 26 04:45:06 PM PDT 24
Finished Jun 26 04:45:49 PM PDT 24
Peak memory 217328 kb
Host smart-327f2404-7d7e-416b-8873-58abe43848a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715293202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2715293202
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2090410514
Short name T178
Test name
Test status
Simulation time 397718365089 ps
CPU time 1045.74 seconds
Started Jun 26 04:44:54 PM PDT 24
Finished Jun 26 05:02:45 PM PDT 24
Peak memory 226128 kb
Host smart-4c0595eb-3e7d-4f33-9d09-7f516653939b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090410514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2090410514
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.927191452
Short name T36
Test name
Test status
Simulation time 404589429 ps
CPU time 18.85 seconds
Started Jun 26 04:45:00 PM PDT 24
Finished Jun 26 04:45:41 PM PDT 24
Peak memory 219232 kb
Host smart-311e0bc1-02d8-4819-a67c-6d99570c62de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927191452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.927191452
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3141561236
Short name T102
Test name
Test status
Simulation time 6458644069 ps
CPU time 24.17 seconds
Started Jun 26 04:44:55 PM PDT 24
Finished Jun 26 04:45:44 PM PDT 24
Peak memory 211700 kb
Host smart-d1baab9e-6d00-4ee5-bb3d-3f1e64aba78a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3141561236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3141561236
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2650139045
Short name T284
Test name
Test status
Simulation time 13028611447 ps
CPU time 70.27 seconds
Started Jun 26 04:44:56 PM PDT 24
Finished Jun 26 04:46:30 PM PDT 24
Peak memory 217424 kb
Host smart-d261ba18-9c7d-4651-b2b3-7db5a03588b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650139045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2650139045
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1561040910
Short name T254
Test name
Test status
Simulation time 26054395325 ps
CPU time 158.26 seconds
Started Jun 26 04:44:58 PM PDT 24
Finished Jun 26 04:47:59 PM PDT 24
Peak memory 220316 kb
Host smart-f387693b-bad2-4c63-a816-3a8adf162875
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561040910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1561040910
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2775186844
Short name T299
Test name
Test status
Simulation time 1534934258 ps
CPU time 17.73 seconds
Started Jun 26 04:44:59 PM PDT 24
Finished Jun 26 04:45:39 PM PDT 24
Peak memory 213176 kb
Host smart-d33f7e28-e7db-44d4-b7db-727fabf9df72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775186844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2775186844
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1136964606
Short name T193
Test name
Test status
Simulation time 260532747816 ps
CPU time 624.35 seconds
Started Jun 26 04:45:00 PM PDT 24
Finished Jun 26 04:55:47 PM PDT 24
Peak memory 238256 kb
Host smart-9fbaebee-c802-4924-931e-fd41686a2360
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136964606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1136964606
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1562230574
Short name T311
Test name
Test status
Simulation time 5275831534 ps
CPU time 28.69 seconds
Started Jun 26 04:45:02 PM PDT 24
Finished Jun 26 04:45:52 PM PDT 24
Peak memory 218564 kb
Host smart-5f38c37a-aecf-4f5b-be20-cc0c310e286d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562230574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1562230574
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.396319209
Short name T188
Test name
Test status
Simulation time 808032108 ps
CPU time 10.86 seconds
Started Jun 26 04:44:58 PM PDT 24
Finished Jun 26 04:45:32 PM PDT 24
Peak memory 219232 kb
Host smart-ee967a90-d39c-4e67-81da-a71402696d73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=396319209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.396319209
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2451518868
Short name T211
Test name
Test status
Simulation time 6194740790 ps
CPU time 61.93 seconds
Started Jun 26 04:45:06 PM PDT 24
Finished Jun 26 04:46:26 PM PDT 24
Peak memory 216912 kb
Host smart-9c51f19c-a380-4925-8f70-21cebd13f07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451518868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2451518868
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3346316551
Short name T327
Test name
Test status
Simulation time 2409391185 ps
CPU time 22.16 seconds
Started Jun 26 04:45:02 PM PDT 24
Finished Jun 26 04:45:45 PM PDT 24
Peak memory 216872 kb
Host smart-d4492e05-4d03-43e3-bd38-32a1beca4f91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346316551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3346316551
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3193766435
Short name T42
Test name
Test status
Simulation time 70654067157 ps
CPU time 1281.42 seconds
Started Jun 26 04:45:01 PM PDT 24
Finished Jun 26 05:06:44 PM PDT 24
Peak memory 237384 kb
Host smart-db10f55c-e617-476e-ad36-a67f7924ba83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193766435 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3193766435
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3041099919
Short name T323
Test name
Test status
Simulation time 603216222 ps
CPU time 12.79 seconds
Started Jun 26 04:44:58 PM PDT 24
Finished Jun 26 04:45:34 PM PDT 24
Peak memory 217196 kb
Host smart-d137ff93-a597-47ad-b0f6-dd998e72e544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041099919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3041099919
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3770752775
Short name T324
Test name
Test status
Simulation time 3246426319 ps
CPU time 212.1 seconds
Started Jun 26 04:45:02 PM PDT 24
Finished Jun 26 04:48:55 PM PDT 24
Peak memory 218272 kb
Host smart-4a64dc5a-8cde-4fe9-9c77-16e85cced281
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770752775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3770752775
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.184127907
Short name T167
Test name
Test status
Simulation time 1228565573 ps
CPU time 25.86 seconds
Started Jun 26 04:44:59 PM PDT 24
Finished Jun 26 04:45:48 PM PDT 24
Peak memory 218764 kb
Host smart-da6afaa1-8fdd-4d27-804e-24b66a23fbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184127907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.184127907
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.640089083
Short name T8
Test name
Test status
Simulation time 2335163799 ps
CPU time 17.46 seconds
Started Jun 26 04:44:58 PM PDT 24
Finished Jun 26 04:45:39 PM PDT 24
Peak memory 211276 kb
Host smart-122aadfb-2030-489b-bdfd-5163120e0ecc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=640089083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.640089083
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1218642555
Short name T197
Test name
Test status
Simulation time 10819125464 ps
CPU time 56.79 seconds
Started Jun 26 04:45:06 PM PDT 24
Finished Jun 26 04:46:20 PM PDT 24
Peak memory 216452 kb
Host smart-4d04a10b-000b-4838-aa4a-65508d9e49d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218642555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1218642555
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1480203304
Short name T28
Test name
Test status
Simulation time 8020343371 ps
CPU time 31.84 seconds
Started Jun 26 04:45:08 PM PDT 24
Finished Jun 26 04:45:57 PM PDT 24
Peak memory 217564 kb
Host smart-df796bf7-e4b6-4216-852d-9240ca2b674c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480203304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1480203304
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.819606330
Short name T35
Test name
Test status
Simulation time 5327318418 ps
CPU time 175.07 seconds
Started Jun 26 04:45:03 PM PDT 24
Finished Jun 26 04:48:18 PM PDT 24
Peak memory 219452 kb
Host smart-ffeba561-3a91-499e-b287-f7d18bf5289d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819606330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.819606330
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.917124569
Short name T241
Test name
Test status
Simulation time 5401528502 ps
CPU time 51.91 seconds
Started Jun 26 04:45:02 PM PDT 24
Finished Jun 26 04:46:15 PM PDT 24
Peak memory 219264 kb
Host smart-25bf4395-c946-4bd1-b511-5edae805128f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917124569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.917124569
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.359764647
Short name T149
Test name
Test status
Simulation time 3435422925 ps
CPU time 29.72 seconds
Started Jun 26 04:45:02 PM PDT 24
Finished Jun 26 04:45:53 PM PDT 24
Peak memory 211540 kb
Host smart-5bedc288-524c-4e03-b2b3-dab13db517eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=359764647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.359764647
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.773062052
Short name T347
Test name
Test status
Simulation time 16101726680 ps
CPU time 64.22 seconds
Started Jun 26 04:45:00 PM PDT 24
Finished Jun 26 04:46:26 PM PDT 24
Peak memory 216672 kb
Host smart-c028b03e-0ff6-4474-9f81-28c74e726cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773062052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.773062052
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3691644117
Short name T342
Test name
Test status
Simulation time 2125650414 ps
CPU time 33.69 seconds
Started Jun 26 04:45:06 PM PDT 24
Finished Jun 26 04:45:57 PM PDT 24
Peak memory 219240 kb
Host smart-5a50a4bd-ae87-4e09-a7f9-13cb90fd913f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691644117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3691644117
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1646874933
Short name T45
Test name
Test status
Simulation time 95957118103 ps
CPU time 1832.34 seconds
Started Jun 26 04:45:02 PM PDT 24
Finished Jun 26 05:15:55 PM PDT 24
Peak memory 235760 kb
Host smart-042f05a0-5234-4946-994f-f601cdba39b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646874933 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1646874933
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1077321874
Short name T207
Test name
Test status
Simulation time 8860402037 ps
CPU time 23.43 seconds
Started Jun 26 04:45:12 PM PDT 24
Finished Jun 26 04:45:49 PM PDT 24
Peak memory 217432 kb
Host smart-24180e28-153d-4b17-bb77-e642b06e1e57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077321874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1077321874
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2149379161
Short name T156
Test name
Test status
Simulation time 280040511059 ps
CPU time 606.88 seconds
Started Jun 26 04:45:09 PM PDT 24
Finished Jun 26 04:55:32 PM PDT 24
Peak memory 219472 kb
Host smart-48b1830a-695a-4291-9e09-21738da3945a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149379161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2149379161
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1535897585
Short name T195
Test name
Test status
Simulation time 991924294 ps
CPU time 22.53 seconds
Started Jun 26 04:45:09 PM PDT 24
Finished Jun 26 04:45:48 PM PDT 24
Peak memory 219264 kb
Host smart-a9bdb511-5b6c-48cb-8973-29064eab0279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535897585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1535897585
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3964220465
Short name T222
Test name
Test status
Simulation time 3948440951 ps
CPU time 15.74 seconds
Started Jun 26 04:45:10 PM PDT 24
Finished Jun 26 04:45:41 PM PDT 24
Peak memory 219300 kb
Host smart-fc5e8648-fb2d-4b11-bda8-032a277550b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3964220465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3964220465
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.220382386
Short name T268
Test name
Test status
Simulation time 703733058 ps
CPU time 19.4 seconds
Started Jun 26 04:45:09 PM PDT 24
Finished Jun 26 04:45:44 PM PDT 24
Peak memory 216140 kb
Host smart-23c11767-d5b5-4f15-9be7-33afe43fba2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220382386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.220382386
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4234891800
Short name T128
Test name
Test status
Simulation time 9353624508 ps
CPU time 37.05 seconds
Started Jun 26 04:45:10 PM PDT 24
Finished Jun 26 04:46:02 PM PDT 24
Peak memory 212200 kb
Host smart-77a65d6a-a13f-4693-956c-69fd6351a023
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234891800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4234891800
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1249638242
Short name T24
Test name
Test status
Simulation time 51204689060 ps
CPU time 30.11 seconds
Started Jun 26 04:45:07 PM PDT 24
Finished Jun 26 04:45:55 PM PDT 24
Peak memory 217552 kb
Host smart-03b74d55-1103-46c6-b476-6991f14fe76b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249638242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1249638242
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.492416028
Short name T256
Test name
Test status
Simulation time 362605852951 ps
CPU time 922.65 seconds
Started Jun 26 04:45:06 PM PDT 24
Finished Jun 26 05:00:46 PM PDT 24
Peak memory 225492 kb
Host smart-72148d51-ebd1-4b64-8259-52e6f4612b36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492416028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.492416028
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1249039449
Short name T38
Test name
Test status
Simulation time 2968530267 ps
CPU time 35.92 seconds
Started Jun 26 04:45:10 PM PDT 24
Finished Jun 26 04:46:01 PM PDT 24
Peak memory 219312 kb
Host smart-4ec7c14d-bdbe-4cc8-8b2c-be1ec7cddf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249039449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1249039449
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2037204906
Short name T153
Test name
Test status
Simulation time 13377909803 ps
CPU time 29.8 seconds
Started Jun 26 04:45:08 PM PDT 24
Finished Jun 26 04:45:55 PM PDT 24
Peak memory 219304 kb
Host smart-bdc2204f-3de5-453b-98a7-d3413420b5cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2037204906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2037204906
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2475824694
Short name T51
Test name
Test status
Simulation time 9154747035 ps
CPU time 33.44 seconds
Started Jun 26 04:45:07 PM PDT 24
Finished Jun 26 04:45:58 PM PDT 24
Peak memory 217132 kb
Host smart-e7d4c25b-a5f8-4be2-ba35-9f1cb92f4433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475824694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2475824694
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.962050491
Short name T104
Test name
Test status
Simulation time 11938106107 ps
CPU time 73.63 seconds
Started Jun 26 04:45:08 PM PDT 24
Finished Jun 26 04:46:38 PM PDT 24
Peak memory 219312 kb
Host smart-771f36a7-5df6-4a6d-9793-8737d26e3fdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962050491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.962050491
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1265827978
Short name T129
Test name
Test status
Simulation time 4442440314 ps
CPU time 21.25 seconds
Started Jun 26 04:45:09 PM PDT 24
Finished Jun 26 04:45:46 PM PDT 24
Peak memory 217560 kb
Host smart-0b6759a5-e576-431a-b23b-aead3762abec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265827978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1265827978
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1254167560
Short name T147
Test name
Test status
Simulation time 33382074769 ps
CPU time 573.98 seconds
Started Jun 26 04:45:09 PM PDT 24
Finished Jun 26 04:54:59 PM PDT 24
Peak memory 239196 kb
Host smart-af4dabcf-86ae-4653-ad5f-3de6d5e38574
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254167560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1254167560
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.671455394
Short name T258
Test name
Test status
Simulation time 17741428180 ps
CPU time 46.44 seconds
Started Jun 26 04:45:08 PM PDT 24
Finished Jun 26 04:46:11 PM PDT 24
Peak memory 219256 kb
Host smart-b55e27cc-1b90-42bf-a02e-e9edea85b12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671455394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.671455394
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3509291150
Short name T103
Test name
Test status
Simulation time 4333504510 ps
CPU time 33.64 seconds
Started Jun 26 04:45:10 PM PDT 24
Finished Jun 26 04:45:59 PM PDT 24
Peak memory 219288 kb
Host smart-473cc21c-fedb-4158-b3e3-d4a987bf9f1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3509291150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3509291150
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3567840625
Short name T176
Test name
Test status
Simulation time 8581640452 ps
CPU time 35.56 seconds
Started Jun 26 04:45:08 PM PDT 24
Finished Jun 26 04:46:00 PM PDT 24
Peak memory 217208 kb
Host smart-b9f16d2d-f850-4bea-8e66-6624aff5f9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567840625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3567840625
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3148522605
Short name T17
Test name
Test status
Simulation time 4784317510 ps
CPU time 54.88 seconds
Started Jun 26 04:45:08 PM PDT 24
Finished Jun 26 04:46:20 PM PDT 24
Peak memory 219404 kb
Host smart-d4558bb0-814b-4a04-98d0-9df4ecea8c38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148522605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3148522605
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2726074655
Short name T208
Test name
Test status
Simulation time 2055509758 ps
CPU time 20.16 seconds
Started Jun 26 04:45:14 PM PDT 24
Finished Jun 26 04:45:47 PM PDT 24
Peak memory 217036 kb
Host smart-3fef6889-462d-4adc-b7a1-0931fc93572c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726074655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2726074655
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.90957953
Short name T143
Test name
Test status
Simulation time 721624078421 ps
CPU time 741.6 seconds
Started Jun 26 04:45:13 PM PDT 24
Finished Jun 26 04:57:48 PM PDT 24
Peak memory 240432 kb
Host smart-b8f32b6e-2bc5-46f0-b15f-c215cbd51148
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90957953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_co
rrupt_sig_fatal_chk.90957953
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.277377164
Short name T320
Test name
Test status
Simulation time 13600024223 ps
CPU time 38.95 seconds
Started Jun 26 04:45:11 PM PDT 24
Finished Jun 26 04:46:05 PM PDT 24
Peak memory 219336 kb
Host smart-dbded05e-f491-4198-84e9-3440330d9d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277377164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.277377164
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1603617392
Short name T121
Test name
Test status
Simulation time 4203880958 ps
CPU time 32.5 seconds
Started Jun 26 04:45:09 PM PDT 24
Finished Jun 26 04:45:57 PM PDT 24
Peak memory 219264 kb
Host smart-8edfda07-7148-4313-9679-27e76b580ec9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1603617392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1603617392
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1437170030
Short name T239
Test name
Test status
Simulation time 1881228695 ps
CPU time 30.67 seconds
Started Jun 26 04:45:08 PM PDT 24
Finished Jun 26 04:45:55 PM PDT 24
Peak memory 215212 kb
Host smart-259f307d-87aa-4b01-ac82-127d1cbfd65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437170030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1437170030
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.4257150538
Short name T41
Test name
Test status
Simulation time 5284061066 ps
CPU time 24.75 seconds
Started Jun 26 04:45:13 PM PDT 24
Finished Jun 26 04:45:51 PM PDT 24
Peak memory 217396 kb
Host smart-1c2c6fd0-41d9-416a-af9d-e78cc0e2d7fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257150538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.4257150538
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1611220945
Short name T272
Test name
Test status
Simulation time 1991865967 ps
CPU time 136.93 seconds
Started Jun 26 04:45:13 PM PDT 24
Finished Jun 26 04:47:43 PM PDT 24
Peak memory 228588 kb
Host smart-08755827-46a7-4f85-860a-e3b933019cfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611220945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1611220945
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2356791511
Short name T314
Test name
Test status
Simulation time 3902777476 ps
CPU time 42.7 seconds
Started Jun 26 04:45:14 PM PDT 24
Finished Jun 26 04:46:09 PM PDT 24
Peak memory 218656 kb
Host smart-2683ed42-8413-4d52-8292-274c373e61c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356791511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2356791511
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3739950327
Short name T280
Test name
Test status
Simulation time 4308431171 ps
CPU time 17.07 seconds
Started Jun 26 04:45:14 PM PDT 24
Finished Jun 26 04:45:43 PM PDT 24
Peak memory 211648 kb
Host smart-e1b37b6e-6001-42ad-9351-445026c7c57c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3739950327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3739950327
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3998200483
Short name T108
Test name
Test status
Simulation time 18860202683 ps
CPU time 54.83 seconds
Started Jun 26 04:45:13 PM PDT 24
Finished Jun 26 04:46:21 PM PDT 24
Peak memory 216888 kb
Host smart-5a6dbaa1-2463-4b15-9c27-2ac34843b615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998200483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3998200483
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3757011356
Short name T243
Test name
Test status
Simulation time 25783279739 ps
CPU time 139.45 seconds
Started Jun 26 04:45:12 PM PDT 24
Finished Jun 26 04:47:45 PM PDT 24
Peak memory 221972 kb
Host smart-139fff17-fd8c-48f1-bff2-dffdc7a446a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757011356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3757011356
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2041460370
Short name T48
Test name
Test status
Simulation time 234689659 ps
CPU time 8.28 seconds
Started Jun 26 04:45:12 PM PDT 24
Finished Jun 26 04:45:34 PM PDT 24
Peak memory 217140 kb
Host smart-a8017253-c715-4ac7-9017-589d55b3cbb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041460370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2041460370
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2000361378
Short name T30
Test name
Test status
Simulation time 203243917994 ps
CPU time 451.17 seconds
Started Jun 26 04:45:14 PM PDT 24
Finished Jun 26 04:52:58 PM PDT 24
Peak memory 218320 kb
Host smart-9b659c1a-81c5-4067-9b77-0e3219e4e67e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000361378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2000361378
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3044359527
Short name T219
Test name
Test status
Simulation time 5211037747 ps
CPU time 27.47 seconds
Started Jun 26 04:45:13 PM PDT 24
Finished Jun 26 04:45:54 PM PDT 24
Peak memory 219324 kb
Host smart-31d696c5-f4d9-4dbe-bb05-61017ec58eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044359527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3044359527
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.493218712
Short name T12
Test name
Test status
Simulation time 16813713944 ps
CPU time 33.58 seconds
Started Jun 26 04:45:15 PM PDT 24
Finished Jun 26 04:46:01 PM PDT 24
Peak memory 219324 kb
Host smart-fcfa4b1e-93bd-4c3c-a39d-e0198d3ea8c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=493218712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.493218712
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1914828719
Short name T218
Test name
Test status
Simulation time 2404306158 ps
CPU time 30.55 seconds
Started Jun 26 04:45:16 PM PDT 24
Finished Jun 26 04:45:58 PM PDT 24
Peak memory 216276 kb
Host smart-cbb1c3a8-4a42-4749-a07d-32f8041a6ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914828719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1914828719
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.16240855
Short name T304
Test name
Test status
Simulation time 742825520 ps
CPU time 16.92 seconds
Started Jun 26 04:45:13 PM PDT 24
Finished Jun 26 04:45:43 PM PDT 24
Peak memory 218876 kb
Host smart-bf4bec2e-3fda-46d3-a535-046b29544781
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16240855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 49.rom_ctrl_stress_all.16240855
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3416134265
Short name T145
Test name
Test status
Simulation time 5363011603 ps
CPU time 17.2 seconds
Started Jun 26 04:44:27 PM PDT 24
Finished Jun 26 04:45:11 PM PDT 24
Peak memory 217444 kb
Host smart-b4b2ae23-8a67-4f1c-9453-af012c22aff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416134265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3416134265
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2155995002
Short name T170
Test name
Test status
Simulation time 171277206605 ps
CPU time 504.84 seconds
Started Jun 26 04:44:18 PM PDT 24
Finished Jun 26 04:53:04 PM PDT 24
Peak memory 234796 kb
Host smart-c2453605-5b04-4a4e-bc40-a45ae494ceee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155995002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2155995002
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.433819229
Short name T310
Test name
Test status
Simulation time 1194601610 ps
CPU time 27.33 seconds
Started Jun 26 04:44:20 PM PDT 24
Finished Jun 26 04:45:10 PM PDT 24
Peak memory 219536 kb
Host smart-88b9e02a-a0b7-45a2-bcb2-06929e294383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433819229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.433819229
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.356414580
Short name T11
Test name
Test status
Simulation time 26549537492 ps
CPU time 30.79 seconds
Started Jun 26 04:44:20 PM PDT 24
Finished Jun 26 04:45:14 PM PDT 24
Peak memory 217872 kb
Host smart-4d19069d-083a-40d8-af9b-4c853b20cf1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=356414580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.356414580
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3416468798
Short name T162
Test name
Test status
Simulation time 356709087 ps
CPU time 19.98 seconds
Started Jun 26 04:44:25 PM PDT 24
Finished Jun 26 04:45:11 PM PDT 24
Peak memory 216348 kb
Host smart-12f60636-043e-4670-a111-7063a0ff306a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416468798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3416468798
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2060112957
Short name T210
Test name
Test status
Simulation time 3318379308 ps
CPU time 59.85 seconds
Started Jun 26 04:44:21 PM PDT 24
Finished Jun 26 04:45:43 PM PDT 24
Peak memory 219584 kb
Host smart-d0babb11-2500-44a2-a4cf-19baa46e7017
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060112957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2060112957
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2482415240
Short name T43
Test name
Test status
Simulation time 63879834986 ps
CPU time 614.6 seconds
Started Jun 26 04:44:16 PM PDT 24
Finished Jun 26 04:54:52 PM PDT 24
Peak memory 235716 kb
Host smart-95badc96-d090-4ed7-a385-e716fd483ef4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482415240 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2482415240
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2028060996
Short name T335
Test name
Test status
Simulation time 787100561 ps
CPU time 8.4 seconds
Started Jun 26 04:44:19 PM PDT 24
Finished Jun 26 04:44:50 PM PDT 24
Peak memory 217024 kb
Host smart-a57f6529-20b2-4fb5-9073-1832b97d3ab2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028060996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2028060996
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3595946944
Short name T307
Test name
Test status
Simulation time 24859199995 ps
CPU time 321.94 seconds
Started Jun 26 04:44:24 PM PDT 24
Finished Jun 26 04:50:11 PM PDT 24
Peak memory 239696 kb
Host smart-80b0174b-f32a-4a2d-a90b-9e186059ff71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595946944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3595946944
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2001067423
Short name T134
Test name
Test status
Simulation time 2494277813 ps
CPU time 35.67 seconds
Started Jun 26 04:44:27 PM PDT 24
Finished Jun 26 04:45:29 PM PDT 24
Peak memory 219312 kb
Host smart-7c309cb2-476d-4ea1-9beb-e8892517ceb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001067423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2001067423
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2640115977
Short name T187
Test name
Test status
Simulation time 12353650093 ps
CPU time 26.8 seconds
Started Jun 26 04:44:17 PM PDT 24
Finished Jun 26 04:45:04 PM PDT 24
Peak memory 219324 kb
Host smart-2185f02e-02d0-4fcf-9d3a-80fa8db85ef9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2640115977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2640115977
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1876199571
Short name T110
Test name
Test status
Simulation time 34976423505 ps
CPU time 83.27 seconds
Started Jun 26 04:44:21 PM PDT 24
Finished Jun 26 04:46:06 PM PDT 24
Peak memory 217872 kb
Host smart-526c30d0-e70b-4488-9956-b4e5883e3f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876199571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1876199571
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1212847560
Short name T305
Test name
Test status
Simulation time 1401594385 ps
CPU time 29.14 seconds
Started Jun 26 04:44:23 PM PDT 24
Finished Jun 26 04:45:16 PM PDT 24
Peak memory 219244 kb
Host smart-3ca9b0fe-5704-4188-9d62-e373e59a41ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212847560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1212847560
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2329334596
Short name T200
Test name
Test status
Simulation time 3374324142 ps
CPU time 27.13 seconds
Started Jun 26 04:44:21 PM PDT 24
Finished Jun 26 04:45:12 PM PDT 24
Peak memory 217252 kb
Host smart-ee0c05de-26a7-4706-b06e-42cf754ab3e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329334596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2329334596
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.4284434339
Short name T291
Test name
Test status
Simulation time 97697435944 ps
CPU time 1134.67 seconds
Started Jun 26 04:44:20 PM PDT 24
Finished Jun 26 05:03:37 PM PDT 24
Peak memory 217888 kb
Host smart-3175af48-9138-4897-9159-7eee52ef25f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284434339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.4284434339
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.361756017
Short name T196
Test name
Test status
Simulation time 57370743111 ps
CPU time 59.99 seconds
Started Jun 26 04:44:32 PM PDT 24
Finished Jun 26 04:45:59 PM PDT 24
Peak memory 219356 kb
Host smart-bdcb2e07-6d46-46dd-bca3-d0d039643ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361756017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.361756017
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3459723511
Short name T308
Test name
Test status
Simulation time 2702870575 ps
CPU time 18.2 seconds
Started Jun 26 04:44:19 PM PDT 24
Finished Jun 26 04:44:59 PM PDT 24
Peak memory 219260 kb
Host smart-14430677-286f-4dbe-ba51-284dcf349668
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3459723511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3459723511
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3773541329
Short name T198
Test name
Test status
Simulation time 9917341686 ps
CPU time 38.16 seconds
Started Jun 26 04:44:19 PM PDT 24
Finished Jun 26 04:45:19 PM PDT 24
Peak memory 216424 kb
Host smart-69e116c8-d305-4441-a1d1-c7f86937e868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773541329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3773541329
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.502287969
Short name T281
Test name
Test status
Simulation time 18482706226 ps
CPU time 31.65 seconds
Started Jun 26 04:44:22 PM PDT 24
Finished Jun 26 04:45:16 PM PDT 24
Peak memory 213264 kb
Host smart-e1ee69bb-e129-4402-9ad2-38644ca5e0da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502287969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.502287969
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2942752316
Short name T302
Test name
Test status
Simulation time 6473692390 ps
CPU time 226.12 seconds
Started Jun 26 04:44:17 PM PDT 24
Finished Jun 26 04:48:23 PM PDT 24
Peak memory 240156 kb
Host smart-ae82f43e-49ec-4f17-be68-e81cfd46c4ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942752316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2942752316
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3600067437
Short name T301
Test name
Test status
Simulation time 346243528 ps
CPU time 18.71 seconds
Started Jun 26 04:44:24 PM PDT 24
Finished Jun 26 04:45:07 PM PDT 24
Peak memory 218760 kb
Host smart-e8b53488-9ce7-4a69-afa2-a0a664cc3b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600067437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3600067437
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1915303123
Short name T122
Test name
Test status
Simulation time 9655570259 ps
CPU time 23.73 seconds
Started Jun 26 04:44:17 PM PDT 24
Finished Jun 26 04:45:03 PM PDT 24
Peak memory 211952 kb
Host smart-5b0656b6-2dce-4949-9c45-8fd70b87cb3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1915303123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1915303123
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.487490437
Short name T325
Test name
Test status
Simulation time 3064740039 ps
CPU time 19.9 seconds
Started Jun 26 04:44:16 PM PDT 24
Finished Jun 26 04:44:57 PM PDT 24
Peak memory 217000 kb
Host smart-91937b18-2e6a-4c98-8770-31ecc8a9c83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487490437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.487490437
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2023716108
Short name T190
Test name
Test status
Simulation time 6171089665 ps
CPU time 39.86 seconds
Started Jun 26 04:44:31 PM PDT 24
Finished Jun 26 04:45:39 PM PDT 24
Peak memory 219308 kb
Host smart-336603e5-c9f3-48f9-a607-0a0fca55c754
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023716108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2023716108
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.297321232
Short name T46
Test name
Test status
Simulation time 58722511553 ps
CPU time 606.27 seconds
Started Jun 26 04:44:34 PM PDT 24
Finished Jun 26 04:55:08 PM PDT 24
Peak memory 230016 kb
Host smart-2d77c5a3-0e0c-446e-a01b-acb00194348a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297321232 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.297321232
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2736670380
Short name T119
Test name
Test status
Simulation time 661762932 ps
CPU time 8.31 seconds
Started Jun 26 04:44:21 PM PDT 24
Finished Jun 26 04:44:53 PM PDT 24
Peak memory 217136 kb
Host smart-6ab0f50d-a993-410a-b20e-97e3fb770356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736670380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2736670380
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1702761151
Short name T315
Test name
Test status
Simulation time 86703158057 ps
CPU time 760.84 seconds
Started Jun 26 04:44:24 PM PDT 24
Finished Jun 26 04:57:30 PM PDT 24
Peak memory 238832 kb
Host smart-6e0b8e44-2cb2-4039-806a-a569a069106d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702761151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1702761151
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3124446912
Short name T319
Test name
Test status
Simulation time 7858693037 ps
CPU time 41.8 seconds
Started Jun 26 04:44:21 PM PDT 24
Finished Jun 26 04:45:27 PM PDT 24
Peak memory 219292 kb
Host smart-edc7cb3c-c098-4141-b5dd-42cdad10c74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124446912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3124446912
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1028563910
Short name T333
Test name
Test status
Simulation time 729805594 ps
CPU time 10.07 seconds
Started Jun 26 04:44:24 PM PDT 24
Finished Jun 26 04:44:59 PM PDT 24
Peak memory 218772 kb
Host smart-7292e822-9388-4d6b-b254-70b4182bd3db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1028563910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1028563910
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1539220894
Short name T206
Test name
Test status
Simulation time 5461988909 ps
CPU time 61.01 seconds
Started Jun 26 04:44:32 PM PDT 24
Finished Jun 26 04:46:00 PM PDT 24
Peak memory 216364 kb
Host smart-0fe0857c-ac5e-4a80-af32-172ebc908775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539220894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1539220894
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1691362820
Short name T169
Test name
Test status
Simulation time 824210721 ps
CPU time 16.49 seconds
Started Jun 26 04:44:24 PM PDT 24
Finished Jun 26 04:45:05 PM PDT 24
Peak memory 218620 kb
Host smart-f4c56f47-c483-4013-b551-27d54394d52c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691362820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1691362820
Directory /workspace/9.rom_ctrl_stress_all/latest
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