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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.18 96.89 91.99 97.68 100.00 98.28 97.30 98.14


Total test records in report: 455
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T303 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2611357133 Jun 27 04:39:46 PM PDT 24 Jun 27 04:40:06 PM PDT 24 3400558682 ps
T304 /workspace/coverage/default/32.rom_ctrl_smoke.1477944651 Jun 27 04:40:11 PM PDT 24 Jun 27 04:41:15 PM PDT 24 5907873836 ps
T305 /workspace/coverage/default/25.rom_ctrl_alert_test.2089124023 Jun 27 04:40:06 PM PDT 24 Jun 27 04:40:20 PM PDT 24 319916168 ps
T306 /workspace/coverage/default/48.rom_ctrl_alert_test.2885763760 Jun 27 04:40:25 PM PDT 24 Jun 27 04:40:47 PM PDT 24 2122030460 ps
T307 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1093498233 Jun 27 04:40:17 PM PDT 24 Jun 27 04:50:19 PM PDT 24 213959858033 ps
T308 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.279565802 Jun 27 04:40:11 PM PDT 24 Jun 27 04:40:44 PM PDT 24 13721083504 ps
T309 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1163629658 Jun 27 04:39:50 PM PDT 24 Jun 27 04:40:25 PM PDT 24 13496609986 ps
T310 /workspace/coverage/default/17.rom_ctrl_stress_all.810854839 Jun 27 04:39:50 PM PDT 24 Jun 27 04:40:27 PM PDT 24 3412671761 ps
T311 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1449023174 Jun 27 04:40:07 PM PDT 24 Jun 27 04:41:08 PM PDT 24 25598811726 ps
T312 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1123931688 Jun 27 04:39:40 PM PDT 24 Jun 27 04:43:47 PM PDT 24 14918584226 ps
T313 /workspace/coverage/default/5.rom_ctrl_smoke.859818866 Jun 27 04:39:50 PM PDT 24 Jun 27 04:40:59 PM PDT 24 30731021030 ps
T314 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.96513038 Jun 27 04:39:50 PM PDT 24 Jun 27 04:40:27 PM PDT 24 12800304277 ps
T315 /workspace/coverage/default/2.rom_ctrl_alert_test.2473492730 Jun 27 04:39:43 PM PDT 24 Jun 27 04:40:12 PM PDT 24 13561387401 ps
T316 /workspace/coverage/default/40.rom_ctrl_alert_test.823646714 Jun 27 04:40:16 PM PDT 24 Jun 27 04:40:48 PM PDT 24 13778777308 ps
T317 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.285711811 Jun 27 04:39:48 PM PDT 24 Jun 27 04:40:30 PM PDT 24 30761042159 ps
T318 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.834534932 Jun 27 04:39:51 PM PDT 24 Jun 27 04:40:12 PM PDT 24 2103382613 ps
T56 /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.13527442 Jun 27 04:39:51 PM PDT 24 Jun 27 06:34:05 PM PDT 24 99046230176 ps
T319 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.139849797 Jun 27 04:40:05 PM PDT 24 Jun 27 04:49:21 PM PDT 24 269135341883 ps
T320 /workspace/coverage/default/33.rom_ctrl_stress_all.2858313513 Jun 27 04:40:15 PM PDT 24 Jun 27 04:41:42 PM PDT 24 8963778062 ps
T321 /workspace/coverage/default/31.rom_ctrl_smoke.3864378775 Jun 27 04:40:08 PM PDT 24 Jun 27 04:40:32 PM PDT 24 355297447 ps
T322 /workspace/coverage/default/49.rom_ctrl_smoke.1960780638 Jun 27 04:40:28 PM PDT 24 Jun 27 04:41:15 PM PDT 24 5241055852 ps
T323 /workspace/coverage/default/43.rom_ctrl_smoke.3342534129 Jun 27 04:40:07 PM PDT 24 Jun 27 04:41:25 PM PDT 24 7537337344 ps
T324 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2349534982 Jun 27 04:39:43 PM PDT 24 Jun 27 04:39:56 PM PDT 24 177606144 ps
T325 /workspace/coverage/default/0.rom_ctrl_smoke.3171568427 Jun 27 04:39:27 PM PDT 24 Jun 27 04:40:07 PM PDT 24 3267620659 ps
T326 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.627226059 Jun 27 04:40:07 PM PDT 24 Jun 27 04:43:34 PM PDT 24 3156656289 ps
T327 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1127356731 Jun 27 04:40:10 PM PDT 24 Jun 27 04:40:50 PM PDT 24 5032157495 ps
T328 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.496550285 Jun 27 04:39:31 PM PDT 24 Jun 27 04:39:47 PM PDT 24 4594318812 ps
T329 /workspace/coverage/default/27.rom_ctrl_smoke.862579181 Jun 27 04:40:12 PM PDT 24 Jun 27 04:41:13 PM PDT 24 12828731694 ps
T330 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2839148778 Jun 27 04:39:47 PM PDT 24 Jun 27 04:40:02 PM PDT 24 188882324 ps
T331 /workspace/coverage/default/33.rom_ctrl_alert_test.4233702866 Jun 27 04:40:16 PM PDT 24 Jun 27 04:40:52 PM PDT 24 4319798955 ps
T332 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.555930803 Jun 27 04:40:13 PM PDT 24 Jun 27 04:41:21 PM PDT 24 16357157605 ps
T333 /workspace/coverage/default/29.rom_ctrl_stress_all.2858749424 Jun 27 04:40:00 PM PDT 24 Jun 27 04:40:26 PM PDT 24 402255158 ps
T334 /workspace/coverage/default/14.rom_ctrl_smoke.2665807174 Jun 27 04:39:45 PM PDT 24 Jun 27 04:40:46 PM PDT 24 14688427211 ps
T335 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.48259594 Jun 27 04:40:24 PM PDT 24 Jun 27 04:41:03 PM PDT 24 11116077841 ps
T336 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.179605286 Jun 27 04:39:49 PM PDT 24 Jun 27 04:40:52 PM PDT 24 6790288825 ps
T337 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2260165650 Jun 27 04:39:46 PM PDT 24 Jun 27 04:45:54 PM PDT 24 186202822832 ps
T338 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2015829335 Jun 27 04:40:08 PM PDT 24 Jun 27 04:40:36 PM PDT 24 1877613222 ps
T339 /workspace/coverage/default/36.rom_ctrl_alert_test.278955931 Jun 27 04:40:17 PM PDT 24 Jun 27 04:40:46 PM PDT 24 2792004714 ps
T340 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.266170049 Jun 27 04:39:43 PM PDT 24 Jun 27 04:40:04 PM PDT 24 346310181 ps
T341 /workspace/coverage/default/3.rom_ctrl_alert_test.1572564830 Jun 27 04:39:45 PM PDT 24 Jun 27 04:40:13 PM PDT 24 10901280400 ps
T342 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.336464866 Jun 27 04:39:49 PM PDT 24 Jun 27 04:40:14 PM PDT 24 350598977 ps
T343 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.741445826 Jun 27 04:39:45 PM PDT 24 Jun 27 04:40:07 PM PDT 24 5984609942 ps
T344 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3610481562 Jun 27 04:39:45 PM PDT 24 Jun 27 04:40:56 PM PDT 24 16445054774 ps
T345 /workspace/coverage/default/12.rom_ctrl_alert_test.979059612 Jun 27 04:39:48 PM PDT 24 Jun 27 04:40:19 PM PDT 24 10484454410 ps
T346 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3364354956 Jun 27 04:40:06 PM PDT 24 Jun 27 04:40:37 PM PDT 24 43281612335 ps
T347 /workspace/coverage/default/13.rom_ctrl_alert_test.3484926370 Jun 27 04:39:50 PM PDT 24 Jun 27 04:40:19 PM PDT 24 13300021166 ps
T348 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2329263169 Jun 27 04:39:49 PM PDT 24 Jun 27 04:40:51 PM PDT 24 12367511323 ps
T349 /workspace/coverage/default/21.rom_ctrl_smoke.3691132103 Jun 27 04:39:50 PM PDT 24 Jun 27 04:41:04 PM PDT 24 6740808755 ps
T350 /workspace/coverage/default/18.rom_ctrl_alert_test.408982755 Jun 27 04:39:47 PM PDT 24 Jun 27 04:40:09 PM PDT 24 6460512385 ps
T351 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2803183834 Jun 27 04:40:40 PM PDT 24 Jun 27 04:41:05 PM PDT 24 2571346853 ps
T352 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3872571497 Jun 27 04:40:03 PM PDT 24 Jun 27 04:40:40 PM PDT 24 28529036527 ps
T353 /workspace/coverage/default/49.rom_ctrl_alert_test.3763509461 Jun 27 04:40:26 PM PDT 24 Jun 27 04:40:57 PM PDT 24 7980411853 ps
T354 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.131476002 Jun 27 04:40:16 PM PDT 24 Jun 27 04:40:34 PM PDT 24 13318849809 ps
T355 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.251501988 Jun 27 04:39:48 PM PDT 24 Jun 27 04:40:18 PM PDT 24 8947955379 ps
T356 /workspace/coverage/default/6.rom_ctrl_smoke.2029515343 Jun 27 04:39:50 PM PDT 24 Jun 27 04:40:38 PM PDT 24 5175475961 ps
T357 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1176994780 Jun 27 04:40:06 PM PDT 24 Jun 27 04:47:09 PM PDT 24 80224634941 ps
T358 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3446668957 Jun 27 04:40:06 PM PDT 24 Jun 27 04:46:15 PM PDT 24 68156882927 ps
T359 /workspace/coverage/default/23.rom_ctrl_alert_test.4259247078 Jun 27 04:40:07 PM PDT 24 Jun 27 04:40:43 PM PDT 24 12721905608 ps
T360 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2260726636 Jun 27 04:40:04 PM PDT 24 Jun 27 04:40:42 PM PDT 24 20131714472 ps
T361 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3963350815 Jun 27 04:40:18 PM PDT 24 Jun 27 04:42:38 PM PDT 24 6466082230 ps
T70 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.603751119 Jun 27 04:17:33 PM PDT 24 Jun 27 04:18:07 PM PDT 24 3932877198 ps
T71 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2055676886 Jun 27 04:17:35 PM PDT 24 Jun 27 04:17:49 PM PDT 24 1428981411 ps
T72 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1110764795 Jun 27 04:22:48 PM PDT 24 Jun 27 04:24:59 PM PDT 24 72844211761 ps
T362 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3991356434 Jun 27 04:17:51 PM PDT 24 Jun 27 04:18:03 PM PDT 24 749788196 ps
T363 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3718507949 Jun 27 04:19:53 PM PDT 24 Jun 27 04:20:18 PM PDT 24 5140034777 ps
T364 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2856161043 Jun 27 04:17:36 PM PDT 24 Jun 27 04:17:56 PM PDT 24 3599926553 ps
T365 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.831849279 Jun 27 04:23:03 PM PDT 24 Jun 27 04:23:14 PM PDT 24 612799432 ps
T105 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.999715546 Jun 27 04:20:09 PM PDT 24 Jun 27 04:20:19 PM PDT 24 360909618 ps
T366 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3599109784 Jun 27 04:17:37 PM PDT 24 Jun 27 04:18:13 PM PDT 24 29304076751 ps
T367 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2191480645 Jun 27 04:22:36 PM PDT 24 Jun 27 04:22:52 PM PDT 24 2318406760 ps
T111 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4085832543 Jun 27 04:23:21 PM PDT 24 Jun 27 04:23:53 PM PDT 24 9329249559 ps
T368 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3961336821 Jun 27 04:17:36 PM PDT 24 Jun 27 04:17:59 PM PDT 24 17389982413 ps
T80 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3299008111 Jun 27 04:17:34 PM PDT 24 Jun 27 04:18:08 PM PDT 24 57491444421 ps
T369 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2959337816 Jun 27 04:17:31 PM PDT 24 Jun 27 04:18:05 PM PDT 24 14365544427 ps
T112 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3152550833 Jun 27 04:23:13 PM PDT 24 Jun 27 04:23:50 PM PDT 24 25080423509 ps
T66 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3138108169 Jun 27 04:17:43 PM PDT 24 Jun 27 04:19:27 PM PDT 24 26261160737 ps
T370 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3549746537 Jun 27 04:20:10 PM PDT 24 Jun 27 04:20:38 PM PDT 24 12651937964 ps
T106 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.299655249 Jun 27 04:20:56 PM PDT 24 Jun 27 04:21:10 PM PDT 24 694604090 ps
T371 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4274495026 Jun 27 04:17:36 PM PDT 24 Jun 27 04:17:59 PM PDT 24 3964850080 ps
T67 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.52130945 Jun 27 04:17:51 PM PDT 24 Jun 27 04:20:28 PM PDT 24 326148803 ps
T107 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2015672425 Jun 27 04:17:47 PM PDT 24 Jun 27 04:18:46 PM PDT 24 4116160370 ps
T81 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3123110336 Jun 27 04:23:08 PM PDT 24 Jun 27 04:24:53 PM PDT 24 31676419700 ps
T372 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.811420990 Jun 27 04:18:25 PM PDT 24 Jun 27 04:18:59 PM PDT 24 4267818857 ps
T373 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2760684754 Jun 27 04:23:19 PM PDT 24 Jun 27 04:24:01 PM PDT 24 4112795919 ps
T374 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2135774292 Jun 27 04:17:31 PM PDT 24 Jun 27 04:18:10 PM PDT 24 17307282175 ps
T82 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3451715295 Jun 27 04:19:56 PM PDT 24 Jun 27 04:20:30 PM PDT 24 4166586510 ps
T68 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.756286381 Jun 27 04:18:30 PM PDT 24 Jun 27 04:21:15 PM PDT 24 1153153598 ps
T116 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.275294217 Jun 27 04:22:40 PM PDT 24 Jun 27 04:24:19 PM PDT 24 13594263948 ps
T375 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.655377923 Jun 27 04:22:22 PM PDT 24 Jun 27 04:22:34 PM PDT 24 174657851 ps
T83 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2635495951 Jun 27 04:17:33 PM PDT 24 Jun 27 04:18:07 PM PDT 24 3573385512 ps
T376 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3346799236 Jun 27 04:17:36 PM PDT 24 Jun 27 04:17:47 PM PDT 24 750745269 ps
T377 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2826880706 Jun 27 04:17:34 PM PDT 24 Jun 27 04:17:57 PM PDT 24 13417420219 ps
T84 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2033941059 Jun 27 04:17:34 PM PDT 24 Jun 27 04:18:05 PM PDT 24 14099760576 ps
T378 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2400976922 Jun 27 04:17:36 PM PDT 24 Jun 27 04:18:03 PM PDT 24 3032895335 ps
T85 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2271424845 Jun 27 04:18:50 PM PDT 24 Jun 27 04:19:15 PM PDT 24 9646793696 ps
T379 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.110081208 Jun 27 04:19:17 PM PDT 24 Jun 27 04:19:42 PM PDT 24 2548637888 ps
T115 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.136270433 Jun 27 04:20:38 PM PDT 24 Jun 27 04:22:10 PM PDT 24 4947604741 ps
T86 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2550804268 Jun 27 04:17:31 PM PDT 24 Jun 27 04:17:44 PM PDT 24 171040268 ps
T380 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2279413041 Jun 27 04:17:30 PM PDT 24 Jun 27 04:17:47 PM PDT 24 5655497871 ps
T381 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3790681457 Jun 27 04:17:33 PM PDT 24 Jun 27 04:17:56 PM PDT 24 6844147895 ps
T117 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.964679060 Jun 27 04:17:33 PM PDT 24 Jun 27 04:19:04 PM PDT 24 1782776507 ps
T382 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1532738513 Jun 27 04:17:34 PM PDT 24 Jun 27 04:17:49 PM PDT 24 352805930 ps
T87 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3599001938 Jun 27 04:17:46 PM PDT 24 Jun 27 04:20:31 PM PDT 24 19066772184 ps
T383 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1416072336 Jun 27 04:23:07 PM PDT 24 Jun 27 04:23:41 PM PDT 24 19698971757 ps
T108 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3513880842 Jun 27 04:18:53 PM PDT 24 Jun 27 04:19:08 PM PDT 24 674340121 ps
T88 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.5063178 Jun 27 04:18:30 PM PDT 24 Jun 27 04:19:49 PM PDT 24 26331369738 ps
T109 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2121256857 Jun 27 04:20:55 PM PDT 24 Jun 27 04:21:27 PM PDT 24 19982437998 ps
T384 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2693767598 Jun 27 04:17:36 PM PDT 24 Jun 27 04:17:48 PM PDT 24 824539200 ps
T120 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.141686966 Jun 27 04:17:36 PM PDT 24 Jun 27 04:19:11 PM PDT 24 2284764843 ps
T385 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1299838728 Jun 27 04:23:03 PM PDT 24 Jun 27 04:23:33 PM PDT 24 5545836301 ps
T386 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2129596516 Jun 27 04:22:40 PM PDT 24 Jun 27 04:23:43 PM PDT 24 3759408864 ps
T127 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.588182025 Jun 27 04:17:47 PM PDT 24 Jun 27 04:20:26 PM PDT 24 1349100517 ps
T92 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2984786182 Jun 27 04:23:12 PM PDT 24 Jun 27 04:24:27 PM PDT 24 20872475272 ps
T387 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1714505896 Jun 27 04:17:35 PM PDT 24 Jun 27 04:17:51 PM PDT 24 2319899962 ps
T388 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3617956150 Jun 27 04:17:36 PM PDT 24 Jun 27 04:17:55 PM PDT 24 6169434304 ps
T389 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.690500357 Jun 27 04:17:26 PM PDT 24 Jun 27 04:17:39 PM PDT 24 599079442 ps
T390 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3718775960 Jun 27 04:20:56 PM PDT 24 Jun 27 04:23:05 PM PDT 24 20412806963 ps
T391 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.374023845 Jun 27 04:17:32 PM PDT 24 Jun 27 04:17:58 PM PDT 24 2889412987 ps
T392 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3606647026 Jun 27 04:22:41 PM PDT 24 Jun 27 04:23:08 PM PDT 24 2412583287 ps
T110 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2510803101 Jun 27 04:17:30 PM PDT 24 Jun 27 04:17:43 PM PDT 24 2407387491 ps
T393 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3261471550 Jun 27 04:17:33 PM PDT 24 Jun 27 04:18:06 PM PDT 24 3931080235 ps
T394 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.884118943 Jun 27 04:22:41 PM PDT 24 Jun 27 04:23:09 PM PDT 24 24968666133 ps
T395 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.577565367 Jun 27 04:17:31 PM PDT 24 Jun 27 04:17:43 PM PDT 24 1090547909 ps
T93 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.149669802 Jun 27 04:17:33 PM PDT 24 Jun 27 04:18:33 PM PDT 24 1077288809 ps
T396 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4616760 Jun 27 04:22:36 PM PDT 24 Jun 27 04:23:07 PM PDT 24 16488454552 ps
T397 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3210030598 Jun 27 04:17:34 PM PDT 24 Jun 27 04:18:10 PM PDT 24 20516248521 ps
T398 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.22818079 Jun 27 04:17:33 PM PDT 24 Jun 27 04:17:44 PM PDT 24 174662734 ps
T399 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3698758258 Jun 27 04:22:47 PM PDT 24 Jun 27 04:23:18 PM PDT 24 10060562817 ps
T400 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3283723839 Jun 27 04:17:40 PM PDT 24 Jun 27 04:18:02 PM PDT 24 8981680322 ps
T401 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.859508877 Jun 27 04:18:34 PM PDT 24 Jun 27 04:18:53 PM PDT 24 1676966101 ps
T402 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1504111370 Jun 27 04:19:17 PM PDT 24 Jun 27 04:19:30 PM PDT 24 184058706 ps
T94 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3330331224 Jun 27 04:17:35 PM PDT 24 Jun 27 04:17:55 PM PDT 24 1538928835 ps
T126 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1871727310 Jun 27 04:17:36 PM PDT 24 Jun 27 04:20:37 PM PDT 24 20446872524 ps
T121 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3358545198 Jun 27 04:17:36 PM PDT 24 Jun 27 04:20:17 PM PDT 24 5718847454 ps
T403 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2537155267 Jun 27 04:21:18 PM PDT 24 Jun 27 04:21:42 PM PDT 24 2726091036 ps
T404 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2696993801 Jun 27 04:22:23 PM PDT 24 Jun 27 04:22:53 PM PDT 24 2992735072 ps
T405 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1411603741 Jun 27 04:19:02 PM PDT 24 Jun 27 04:19:15 PM PDT 24 176842760 ps
T406 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2531370011 Jun 27 04:20:10 PM PDT 24 Jun 27 04:20:36 PM PDT 24 5485268581 ps
T407 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.724149859 Jun 27 04:19:24 PM PDT 24 Jun 27 04:19:58 PM PDT 24 9984430510 ps
T408 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.911002287 Jun 27 04:20:06 PM PDT 24 Jun 27 04:20:25 PM PDT 24 3797606675 ps
T118 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2058160083 Jun 27 04:22:22 PM PDT 24 Jun 27 04:25:13 PM PDT 24 3655337018 ps
T409 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.254037620 Jun 27 04:17:36 PM PDT 24 Jun 27 04:18:17 PM PDT 24 8889604904 ps
T410 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4188486176 Jun 27 04:17:33 PM PDT 24 Jun 27 04:17:51 PM PDT 24 182532901 ps
T411 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.948857771 Jun 27 04:17:33 PM PDT 24 Jun 27 04:17:59 PM PDT 24 8996334497 ps
T412 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2829943837 Jun 27 04:19:54 PM PDT 24 Jun 27 04:20:20 PM PDT 24 17628024314 ps
T413 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3618664487 Jun 27 04:23:13 PM PDT 24 Jun 27 04:23:47 PM PDT 24 56132560731 ps
T414 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.840886264 Jun 27 04:17:35 PM PDT 24 Jun 27 04:17:55 PM PDT 24 1278549186 ps
T95 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2434208938 Jun 27 04:23:42 PM PDT 24 Jun 27 04:26:10 PM PDT 24 14412461670 ps
T415 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2702010048 Jun 27 04:20:09 PM PDT 24 Jun 27 04:20:41 PM PDT 24 3757249414 ps
T416 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.649646428 Jun 27 04:17:36 PM PDT 24 Jun 27 04:17:48 PM PDT 24 167402886 ps
T417 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2421438761 Jun 27 04:20:37 PM PDT 24 Jun 27 04:20:52 PM PDT 24 167695587 ps
T418 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2489067628 Jun 27 04:20:39 PM PDT 24 Jun 27 04:21:04 PM PDT 24 4396664255 ps
T419 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2515693833 Jun 27 04:18:34 PM PDT 24 Jun 27 04:19:52 PM PDT 24 6257258422 ps
T420 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.641061398 Jun 27 04:21:07 PM PDT 24 Jun 27 04:22:54 PM PDT 24 4100774317 ps
T421 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2628494706 Jun 27 04:20:36 PM PDT 24 Jun 27 04:22:03 PM PDT 24 1188658173 ps
T422 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.818654284 Jun 27 04:22:22 PM PDT 24 Jun 27 04:22:38 PM PDT 24 1319799904 ps
T423 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4091618 Jun 27 04:17:27 PM PDT 24 Jun 27 04:18:03 PM PDT 24 4104602037 ps
T96 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.641331794 Jun 27 04:17:33 PM PDT 24 Jun 27 04:18:31 PM PDT 24 2862974902 ps
T424 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4060336272 Jun 27 04:21:03 PM PDT 24 Jun 27 04:21:13 PM PDT 24 167783211 ps
T97 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3918351070 Jun 27 04:17:34 PM PDT 24 Jun 27 04:17:49 PM PDT 24 839999815 ps
T425 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.587698851 Jun 27 04:17:35 PM PDT 24 Jun 27 04:17:47 PM PDT 24 171521393 ps
T426 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.230466513 Jun 27 04:22:41 PM PDT 24 Jun 27 04:23:02 PM PDT 24 746044856 ps
T98 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2408795444 Jun 27 04:22:40 PM PDT 24 Jun 27 04:23:37 PM PDT 24 1044181688 ps
T99 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2693022998 Jun 27 04:17:35 PM PDT 24 Jun 27 04:18:02 PM PDT 24 10772350763 ps
T100 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4237132965 Jun 27 04:17:34 PM PDT 24 Jun 27 04:17:49 PM PDT 24 2404918048 ps
T427 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.843342263 Jun 27 04:20:04 PM PDT 24 Jun 27 04:20:32 PM PDT 24 13613983703 ps
T123 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3168262757 Jun 27 04:23:15 PM PDT 24 Jun 27 04:25:56 PM PDT 24 24824101759 ps
T428 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.855910536 Jun 27 04:22:47 PM PDT 24 Jun 27 04:23:23 PM PDT 24 3955611241 ps
T429 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1864907484 Jun 27 04:22:42 PM PDT 24 Jun 27 04:23:09 PM PDT 24 5105576378 ps
T430 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4036175038 Jun 27 04:22:23 PM PDT 24 Jun 27 04:22:48 PM PDT 24 5603976556 ps
T122 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1424005868 Jun 27 04:21:07 PM PDT 24 Jun 27 04:22:31 PM PDT 24 239850481 ps
T431 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3342752741 Jun 27 04:23:08 PM PDT 24 Jun 27 04:23:40 PM PDT 24 13442362428 ps
T432 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4289515177 Jun 27 04:17:26 PM PDT 24 Jun 27 04:17:41 PM PDT 24 925881150 ps
T433 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.625606717 Jun 27 04:17:34 PM PDT 24 Jun 27 04:17:46 PM PDT 24 170991084 ps
T434 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.754703213 Jun 27 04:18:17 PM PDT 24 Jun 27 04:18:38 PM PDT 24 10934581939 ps
T124 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1235369036 Jun 27 04:17:43 PM PDT 24 Jun 27 04:20:19 PM PDT 24 5959517326 ps
T435 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.960018917 Jun 27 04:20:09 PM PDT 24 Jun 27 04:20:19 PM PDT 24 209998670 ps
T436 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2019427715 Jun 27 04:22:47 PM PDT 24 Jun 27 04:24:59 PM PDT 24 13098493604 ps
T437 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2051097970 Jun 27 04:22:56 PM PDT 24 Jun 27 04:23:09 PM PDT 24 891106273 ps
T103 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3816937204 Jun 27 04:23:08 PM PDT 24 Jun 27 04:25:04 PM PDT 24 51062603927 ps
T438 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1925056405 Jun 27 04:17:35 PM PDT 24 Jun 27 04:19:11 PM PDT 24 6004668865 ps
T439 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2712316645 Jun 27 04:17:34 PM PDT 24 Jun 27 04:18:13 PM PDT 24 4265647560 ps
T440 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2161679349 Jun 27 04:19:40 PM PDT 24 Jun 27 04:20:11 PM PDT 24 12897849195 ps
T104 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1041473209 Jun 27 04:19:14 PM PDT 24 Jun 27 04:19:23 PM PDT 24 826541673 ps
T101 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1131145342 Jun 27 04:23:19 PM PDT 24 Jun 27 04:24:41 PM PDT 24 2512031919 ps
T125 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4128624757 Jun 27 04:18:41 PM PDT 24 Jun 27 04:21:24 PM PDT 24 975842712 ps
T441 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1175936661 Jun 27 04:17:35 PM PDT 24 Jun 27 04:18:04 PM PDT 24 33783653542 ps
T442 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.479696890 Jun 27 04:17:27 PM PDT 24 Jun 27 04:17:50 PM PDT 24 9184619241 ps
T443 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.706612385 Jun 27 04:21:24 PM PDT 24 Jun 27 04:21:52 PM PDT 24 16751051536 ps
T444 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3842532190 Jun 27 04:17:36 PM PDT 24 Jun 27 04:17:48 PM PDT 24 174534486 ps
T128 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2267722384 Jun 27 04:22:36 PM PDT 24 Jun 27 04:24:18 PM PDT 24 4068373251 ps
T445 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4144145626 Jun 27 04:17:34 PM PDT 24 Jun 27 04:17:52 PM PDT 24 4448511110 ps
T446 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2237866546 Jun 27 04:17:34 PM PDT 24 Jun 27 04:19:34 PM PDT 24 44542579022 ps
T447 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.475861492 Jun 27 04:17:33 PM PDT 24 Jun 27 04:18:59 PM PDT 24 14428505650 ps
T448 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2995349464 Jun 27 04:22:36 PM PDT 24 Jun 27 04:22:50 PM PDT 24 167364663 ps
T129 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3839845283 Jun 27 04:17:26 PM PDT 24 Jun 27 04:20:26 PM PDT 24 4979179453 ps
T449 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2588181808 Jun 27 04:17:35 PM PDT 24 Jun 27 04:19:13 PM PDT 24 7193777044 ps
T450 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.196212455 Jun 27 04:17:33 PM PDT 24 Jun 27 04:17:57 PM PDT 24 18509640606 ps
T451 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.961571284 Jun 27 04:17:36 PM PDT 24 Jun 27 04:18:11 PM PDT 24 8048705553 ps
T452 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.335653635 Jun 27 04:22:22 PM PDT 24 Jun 27 04:22:50 PM PDT 24 2659652631 ps
T453 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2406993615 Jun 27 04:23:02 PM PDT 24 Jun 27 04:23:22 PM PDT 24 1122767606 ps
T454 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4058475301 Jun 27 04:17:34 PM PDT 24 Jun 27 04:17:54 PM PDT 24 5929670249 ps
T455 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1659837419 Jun 27 04:20:36 PM PDT 24 Jun 27 04:21:01 PM PDT 24 4771885696 ps
T119 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.199965275 Jun 27 04:17:35 PM PDT 24 Jun 27 04:19:06 PM PDT 24 9476207354 ps
T102 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4262376173 Jun 27 04:21:03 PM PDT 24 Jun 27 04:21:24 PM PDT 24 10390031131 ps

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.106074443
Short name T6
Test name
Test status
Simulation time 358917193616 ps
CPU time 715.07 seconds
Started Jun 27 04:40:10 PM PDT 24
Finished Jun 27 04:52:09 PM PDT 24
Peak memory 225508 kb
Host smart-c11aab55-8d46-4d67-b6a8-64b6dcbd0f53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106074443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.106074443
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.706081200
Short name T12
Test name
Test status
Simulation time 28267570160 ps
CPU time 1616.4 seconds
Started Jun 27 04:40:06 PM PDT 24
Finished Jun 27 05:07:07 PM PDT 24
Peak memory 235716 kb
Host smart-81d54c3c-595f-420c-99e1-641d81151849
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706081200 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.706081200
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3959681770
Short name T9
Test name
Test status
Simulation time 17983852870 ps
CPU time 83.16 seconds
Started Jun 27 04:39:47 PM PDT 24
Finished Jun 27 04:41:16 PM PDT 24
Peak memory 219196 kb
Host smart-0e5df09b-faaf-487e-80f5-aa07712eda0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959681770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3959681770
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3943200998
Short name T7
Test name
Test status
Simulation time 4637494281 ps
CPU time 89.99 seconds
Started Jun 27 04:39:53 PM PDT 24
Finished Jun 27 04:41:31 PM PDT 24
Peak memory 219832 kb
Host smart-1d2be384-fbe2-4dcd-904c-9f882e615894
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943200998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3943200998
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2246702774
Short name T26
Test name
Test status
Simulation time 1196977543 ps
CPU time 15.37 seconds
Started Jun 27 04:39:38 PM PDT 24
Finished Jun 27 04:39:54 PM PDT 24
Peak memory 213164 kb
Host smart-3e7e9c34-5c2c-4ae6-ba22-b8873ce6e76c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246702774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2246702774
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.52130945
Short name T67
Test name
Test status
Simulation time 326148803 ps
CPU time 156.21 seconds
Started Jun 27 04:17:51 PM PDT 24
Finished Jun 27 04:20:28 PM PDT 24
Peak memory 213664 kb
Host smart-fe09e45c-2852-46c4-898f-218a44ac1528
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52130945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_int
g_err.52130945
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4121131882
Short name T132
Test name
Test status
Simulation time 20921777871 ps
CPU time 29.46 seconds
Started Jun 27 04:40:20 PM PDT 24
Finished Jun 27 04:40:52 PM PDT 24
Peak memory 217868 kb
Host smart-719bd854-53a1-4779-ad54-4f2bcb79c345
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4121131882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4121131882
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3818386469
Short name T19
Test name
Test status
Simulation time 4619966469 ps
CPU time 23.94 seconds
Started Jun 27 04:40:07 PM PDT 24
Finished Jun 27 04:40:35 PM PDT 24
Peak memory 219220 kb
Host smart-47e82076-bec6-40f8-bf20-2e799e2697f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3818386469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3818386469
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.452819968
Short name T23
Test name
Test status
Simulation time 4080552989 ps
CPU time 123.14 seconds
Started Jun 27 04:39:43 PM PDT 24
Finished Jun 27 04:41:48 PM PDT 24
Peak memory 236584 kb
Host smart-279de0b7-54ff-48f1-a826-d03dfe125d96
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452819968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.452819968
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3123110336
Short name T81
Test name
Test status
Simulation time 31676419700 ps
CPU time 100.21 seconds
Started Jun 27 04:23:08 PM PDT 24
Finished Jun 27 04:24:53 PM PDT 24
Peak memory 215044 kb
Host smart-67c8d4b8-5ce5-44c3-a96c-16b7f5023a63
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123110336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3123110336
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3714350665
Short name T141
Test name
Test status
Simulation time 19906938442 ps
CPU time 432.93 seconds
Started Jun 27 04:39:46 PM PDT 24
Finished Jun 27 04:47:04 PM PDT 24
Peak memory 242696 kb
Host smart-5dc660cd-73bb-43d2-aa67-8a19ea4e2706
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714350665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3714350665
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1871727310
Short name T126
Test name
Test status
Simulation time 20446872524 ps
CPU time 177.16 seconds
Started Jun 27 04:17:36 PM PDT 24
Finished Jun 27 04:20:37 PM PDT 24
Peak memory 215400 kb
Host smart-d1de4cef-8fd3-4202-a305-66864d17ba7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871727310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1871727310
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2789156992
Short name T134
Test name
Test status
Simulation time 1285208261 ps
CPU time 11.65 seconds
Started Jun 27 04:40:06 PM PDT 24
Finished Jun 27 04:40:22 PM PDT 24
Peak memory 218996 kb
Host smart-d1e43355-084f-40da-ae7a-355616ebdef4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2789156992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2789156992
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1424005868
Short name T122
Test name
Test status
Simulation time 239850481 ps
CPU time 83.27 seconds
Started Jun 27 04:21:07 PM PDT 24
Finished Jun 27 04:22:31 PM PDT 24
Peak memory 214040 kb
Host smart-aa6e20b4-02d3-4466-91ce-96131aa6feaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424005868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1424005868
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3764428653
Short name T29
Test name
Test status
Simulation time 34832603433 ps
CPU time 65.57 seconds
Started Jun 27 04:39:43 PM PDT 24
Finished Jun 27 04:40:51 PM PDT 24
Peak memory 219268 kb
Host smart-6450d473-5c7b-4a23-8c95-dd9ce41acfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764428653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3764428653
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1989141622
Short name T203
Test name
Test status
Simulation time 1321943457 ps
CPU time 19.57 seconds
Started Jun 27 04:39:50 PM PDT 24
Finished Jun 27 04:40:18 PM PDT 24
Peak memory 215420 kb
Host smart-60b922f3-4813-41c3-ad61-350ad12864eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989141622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1989141622
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.5063178
Short name T88
Test name
Test status
Simulation time 26331369738 ps
CPU time 77.28 seconds
Started Jun 27 04:18:30 PM PDT 24
Finished Jun 27 04:19:49 PM PDT 24
Peak memory 213784 kb
Host smart-9cece605-c1d3-4bba-a54d-9878973bf255
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5063178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pass
thru_mem_tl_intg_err.5063178
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1235369036
Short name T124
Test name
Test status
Simulation time 5959517326 ps
CPU time 154.79 seconds
Started Jun 27 04:17:43 PM PDT 24
Finished Jun 27 04:20:19 PM PDT 24
Peak memory 213052 kb
Host smart-5866f2a6-13cb-4c29-bdd9-17199cde97ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235369036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1235369036
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2058160083
Short name T118
Test name
Test status
Simulation time 3655337018 ps
CPU time 169.64 seconds
Started Jun 27 04:22:22 PM PDT 24
Finished Jun 27 04:25:13 PM PDT 24
Peak memory 213252 kb
Host smart-05b6edad-c1ed-41dd-9333-c9a289b2d51f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058160083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2058160083
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3942362751
Short name T40
Test name
Test status
Simulation time 140236702754 ps
CPU time 704.45 seconds
Started Jun 27 04:39:54 PM PDT 24
Finished Jun 27 04:51:47 PM PDT 24
Peak memory 225688 kb
Host smart-2f855c5d-c76e-49d5-baf0-ee7c6057d914
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942362751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3942362751
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3718507949
Short name T363
Test name
Test status
Simulation time 5140034777 ps
CPU time 23.74 seconds
Started Jun 27 04:19:53 PM PDT 24
Finished Jun 27 04:20:18 PM PDT 24
Peak memory 217220 kb
Host smart-345a9162-8630-4d9c-b723-a2263c59d021
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718507949 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3718507949
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3143701811
Short name T15
Test name
Test status
Simulation time 183419761099 ps
CPU time 1605.92 seconds
Started Jun 27 04:39:52 PM PDT 24
Finished Jun 27 05:06:46 PM PDT 24
Peak memory 239376 kb
Host smart-2534907d-f635-458d-902b-70b993abe8f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143701811 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3143701811
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3330331224
Short name T94
Test name
Test status
Simulation time 1538928835 ps
CPU time 17.37 seconds
Started Jun 27 04:17:35 PM PDT 24
Finished Jun 27 04:17:55 PM PDT 24
Peak memory 211728 kb
Host smart-d815568d-8d11-45a3-b293-6267cfb6123a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330331224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3330331224
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.196212455
Short name T450
Test name
Test status
Simulation time 18509640606 ps
CPU time 21.24 seconds
Started Jun 27 04:17:33 PM PDT 24
Finished Jun 27 04:17:57 PM PDT 24
Peak memory 207952 kb
Host smart-3f74cd4d-f126-4079-b6c2-4ab04f1af2c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196212455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.196212455
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.948857771
Short name T411
Test name
Test status
Simulation time 8996334497 ps
CPU time 23.38 seconds
Started Jun 27 04:17:33 PM PDT 24
Finished Jun 27 04:17:59 PM PDT 24
Peak memory 209108 kb
Host smart-822eb6c4-5b37-484d-83f7-8d2787a8d130
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948857771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.948857771
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.577565367
Short name T395
Test name
Test status
Simulation time 1090547909 ps
CPU time 10.32 seconds
Started Jun 27 04:17:31 PM PDT 24
Finished Jun 27 04:17:43 PM PDT 24
Peak memory 216664 kb
Host smart-4da77ac1-849f-4f8c-8c94-9694393272cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577565367 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.577565367
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1714505896
Short name T387
Test name
Test status
Simulation time 2319899962 ps
CPU time 12.38 seconds
Started Jun 27 04:17:35 PM PDT 24
Finished Jun 27 04:17:51 PM PDT 24
Peak memory 211124 kb
Host smart-99a91196-a8fc-40e5-9b8d-a056b5bf9b4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714505896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1714505896
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3342752741
Short name T431
Test name
Test status
Simulation time 13442362428 ps
CPU time 27.05 seconds
Started Jun 27 04:23:08 PM PDT 24
Finished Jun 27 04:23:40 PM PDT 24
Peak memory 210308 kb
Host smart-9bd03234-5f44-44f0-b660-82581acc14f8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342752741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3342752741
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2279413041
Short name T380
Test name
Test status
Simulation time 5655497871 ps
CPU time 15.6 seconds
Started Jun 27 04:17:30 PM PDT 24
Finished Jun 27 04:17:47 PM PDT 24
Peak memory 209772 kb
Host smart-24ffe087-a147-4814-8bec-9569787e0940
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279413041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2279413041
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2015672425
Short name T107
Test name
Test status
Simulation time 4116160370 ps
CPU time 56.74 seconds
Started Jun 27 04:17:47 PM PDT 24
Finished Jun 27 04:18:46 PM PDT 24
Peak memory 215344 kb
Host smart-fb5f1e4f-aed9-4025-b693-38dee0462749
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015672425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2015672425
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2635495951
Short name T83
Test name
Test status
Simulation time 3573385512 ps
CPU time 31.07 seconds
Started Jun 27 04:17:33 PM PDT 24
Finished Jun 27 04:18:07 PM PDT 24
Peak memory 209048 kb
Host smart-9a6b793d-c94a-4a95-a8cf-a6c73ffd468d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635495951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2635495951
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2856161043
Short name T364
Test name
Test status
Simulation time 3599926553 ps
CPU time 17.12 seconds
Started Jun 27 04:17:36 PM PDT 24
Finished Jun 27 04:17:56 PM PDT 24
Peak memory 218424 kb
Host smart-a5f7d0e8-d093-4143-8375-99c9a8ea943c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856161043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2856161043
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4237132965
Short name T100
Test name
Test status
Simulation time 2404918048 ps
CPU time 12.49 seconds
Started Jun 27 04:17:34 PM PDT 24
Finished Jun 27 04:17:49 PM PDT 24
Peak memory 211124 kb
Host smart-96be36a6-4ca8-42b0-aa0d-04d6e576173f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237132965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.4237132965
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4144145626
Short name T445
Test name
Test status
Simulation time 4448511110 ps
CPU time 14.9 seconds
Started Jun 27 04:17:34 PM PDT 24
Finished Jun 27 04:17:52 PM PDT 24
Peak memory 210028 kb
Host smart-0696d4df-64bd-410b-b873-7a3025fd15fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144145626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4144145626
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.4188486176
Short name T410
Test name
Test status
Simulation time 182532901 ps
CPU time 15.56 seconds
Started Jun 27 04:17:33 PM PDT 24
Finished Jun 27 04:17:51 PM PDT 24
Peak memory 207956 kb
Host smart-e9745e37-100d-4bc9-9f34-c9df61fe4a3e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188486176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.4188486176
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4058475301
Short name T454
Test name
Test status
Simulation time 5929670249 ps
CPU time 16.48 seconds
Started Jun 27 04:17:34 PM PDT 24
Finished Jun 27 04:17:54 PM PDT 24
Peak memory 216500 kb
Host smart-312d0d05-d968-4e64-b2b5-633548d38f4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058475301 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.4058475301
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2271424845
Short name T85
Test name
Test status
Simulation time 9646793696 ps
CPU time 23.51 seconds
Started Jun 27 04:18:50 PM PDT 24
Finished Jun 27 04:19:15 PM PDT 24
Peak memory 212744 kb
Host smart-a0b626b3-dc36-43ee-a622-648e92ded132
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271424845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2271424845
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3346799236
Short name T376
Test name
Test status
Simulation time 750745269 ps
CPU time 8.03 seconds
Started Jun 27 04:17:36 PM PDT 24
Finished Jun 27 04:17:47 PM PDT 24
Peak memory 210820 kb
Host smart-d24204bb-e9cf-4bd1-95d7-881977dceab8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346799236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3346799236
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3599109784
Short name T366
Test name
Test status
Simulation time 29304076751 ps
CPU time 33.26 seconds
Started Jun 27 04:17:37 PM PDT 24
Finished Jun 27 04:18:13 PM PDT 24
Peak memory 210824 kb
Host smart-23ea6865-07af-4e52-a5ea-bbef03493c6b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599109784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3599109784
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.641331794
Short name T96
Test name
Test status
Simulation time 2862974902 ps
CPU time 56.92 seconds
Started Jun 27 04:17:33 PM PDT 24
Finished Jun 27 04:18:31 PM PDT 24
Peak memory 214096 kb
Host smart-febb20cb-20a5-44f8-9776-6a372766326c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641331794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas
sthru_mem_tl_intg_err.641331794
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2489067628
Short name T418
Test name
Test status
Simulation time 4396664255 ps
CPU time 21.61 seconds
Started Jun 27 04:20:39 PM PDT 24
Finished Jun 27 04:21:04 PM PDT 24
Peak memory 212680 kb
Host smart-134aa847-6542-486e-bbe2-8620a1647d32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489067628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2489067628
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2712316645
Short name T439
Test name
Test status
Simulation time 4265647560 ps
CPU time 35.94 seconds
Started Jun 27 04:17:34 PM PDT 24
Finished Jun 27 04:18:13 PM PDT 24
Peak memory 217952 kb
Host smart-55a1327b-6cfb-438e-a07f-bdb794e9dc03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712316645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2712316645
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3358545198
Short name T121
Test name
Test status
Simulation time 5718847454 ps
CPU time 156.87 seconds
Started Jun 27 04:17:36 PM PDT 24
Finished Jun 27 04:20:17 PM PDT 24
Peak memory 214188 kb
Host smart-1e19c7d4-79da-4d22-a290-7ffaf725014e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358545198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3358545198
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.960018917
Short name T435
Test name
Test status
Simulation time 209998670 ps
CPU time 8.75 seconds
Started Jun 27 04:20:09 PM PDT 24
Finished Jun 27 04:20:19 PM PDT 24
Peak memory 215316 kb
Host smart-a55346ea-2588-44c9-bc4f-e2022160a1dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960018917 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.960018917
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1041473209
Short name T104
Test name
Test status
Simulation time 826541673 ps
CPU time 8.06 seconds
Started Jun 27 04:19:14 PM PDT 24
Finished Jun 27 04:19:23 PM PDT 24
Peak memory 210844 kb
Host smart-658012be-0787-4263-8854-04c049ecf273
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041473209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1041473209
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2434208938
Short name T95
Test name
Test status
Simulation time 14412461670 ps
CPU time 133.22 seconds
Started Jun 27 04:23:42 PM PDT 24
Finished Jun 27 04:26:10 PM PDT 24
Peak memory 214984 kb
Host smart-e86d5a00-6527-4b1d-bc11-0194e429f9cf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434208938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2434208938
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1864907484
Short name T429
Test name
Test status
Simulation time 5105576378 ps
CPU time 23.42 seconds
Started Jun 27 04:22:42 PM PDT 24
Finished Jun 27 04:23:09 PM PDT 24
Peak memory 212208 kb
Host smart-25be0b52-d109-4ed5-af2e-0865ca8d42cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864907484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1864907484
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2995349464
Short name T448
Test name
Test status
Simulation time 167364663 ps
CPU time 12.8 seconds
Started Jun 27 04:22:36 PM PDT 24
Finished Jun 27 04:22:50 PM PDT 24
Peak memory 217364 kb
Host smart-c486f907-41a6-408c-b1fe-75bd6c9f75ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995349464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2995349464
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1659837419
Short name T455
Test name
Test status
Simulation time 4771885696 ps
CPU time 22.01 seconds
Started Jun 27 04:20:36 PM PDT 24
Finished Jun 27 04:21:01 PM PDT 24
Peak memory 212160 kb
Host smart-c8b6434e-459c-40a8-83a7-274acfa63310
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659837419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1659837419
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3718775960
Short name T390
Test name
Test status
Simulation time 20412806963 ps
CPU time 127.83 seconds
Started Jun 27 04:20:56 PM PDT 24
Finished Jun 27 04:23:05 PM PDT 24
Peak memory 213756 kb
Host smart-18cc62c1-a27c-4538-a7e2-7089f714aa6f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718775960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3718775960
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3513880842
Short name T108
Test name
Test status
Simulation time 674340121 ps
CPU time 13.77 seconds
Started Jun 27 04:18:53 PM PDT 24
Finished Jun 27 04:19:08 PM PDT 24
Peak memory 211292 kb
Host smart-223eb407-0a52-4f39-92f7-5dade73ebe1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513880842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3513880842
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1504111370
Short name T402
Test name
Test status
Simulation time 184058706 ps
CPU time 11.92 seconds
Started Jun 27 04:19:17 PM PDT 24
Finished Jun 27 04:19:30 PM PDT 24
Peak memory 218792 kb
Host smart-e251a451-7790-45cd-a738-29b616f6924b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504111370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1504111370
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.811420990
Short name T372
Test name
Test status
Simulation time 4267818857 ps
CPU time 33.26 seconds
Started Jun 27 04:18:25 PM PDT 24
Finished Jun 27 04:18:59 PM PDT 24
Peak memory 215212 kb
Host smart-08d72b81-8e04-4b5b-b5af-e575b5f455af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811420990 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.811420990
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3152550833
Short name T112
Test name
Test status
Simulation time 25080423509 ps
CPU time 32.65 seconds
Started Jun 27 04:23:13 PM PDT 24
Finished Jun 27 04:23:50 PM PDT 24
Peak memory 211792 kb
Host smart-5dca6009-b288-4e1d-a52e-56ecb36afc05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152550833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3152550833
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2408795444
Short name T98
Test name
Test status
Simulation time 1044181688 ps
CPU time 54.38 seconds
Started Jun 27 04:22:40 PM PDT 24
Finished Jun 27 04:23:37 PM PDT 24
Peak memory 213388 kb
Host smart-772e8d44-0645-4332-8fd9-9fa40c6844c4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408795444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2408795444
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4060336272
Short name T424
Test name
Test status
Simulation time 167783211 ps
CPU time 8.66 seconds
Started Jun 27 04:21:03 PM PDT 24
Finished Jun 27 04:21:13 PM PDT 24
Peak memory 211704 kb
Host smart-ee8cb6da-d81d-4c9a-a119-9e36120c6951
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060336272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.4060336272
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.855910536
Short name T428
Test name
Test status
Simulation time 3955611241 ps
CPU time 33.44 seconds
Started Jun 27 04:22:47 PM PDT 24
Finished Jun 27 04:23:23 PM PDT 24
Peak memory 218152 kb
Host smart-12f375f3-e534-4a9f-94e9-885a65c22800
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855910536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.855910536
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2267722384
Short name T128
Test name
Test status
Simulation time 4068373251 ps
CPU time 101.45 seconds
Started Jun 27 04:22:36 PM PDT 24
Finished Jun 27 04:24:18 PM PDT 24
Peak memory 218832 kb
Host smart-71e81176-9ecc-4129-a5fa-a72b11270b3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267722384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2267722384
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3698758258
Short name T399
Test name
Test status
Simulation time 10060562817 ps
CPU time 28.6 seconds
Started Jun 27 04:22:47 PM PDT 24
Finished Jun 27 04:23:18 PM PDT 24
Peak memory 217796 kb
Host smart-4a1bd838-327d-4e11-9a1d-3490c5e7a56d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698758258 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3698758258
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.4262376173
Short name T102
Test name
Test status
Simulation time 10390031131 ps
CPU time 19.84 seconds
Started Jun 27 04:21:03 PM PDT 24
Finished Jun 27 04:21:24 PM PDT 24
Peak memory 211468 kb
Host smart-b9ffe2a1-6e01-4721-b75e-6a7c1bdc52b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262376173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.4262376173
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2984786182
Short name T92
Test name
Test status
Simulation time 20872475272 ps
CPU time 70.87 seconds
Started Jun 27 04:23:12 PM PDT 24
Finished Jun 27 04:24:27 PM PDT 24
Peak memory 213488 kb
Host smart-2b592bd2-84be-4586-8295-e2b46b0d9f07
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984786182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2984786182
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4036175038
Short name T430
Test name
Test status
Simulation time 5603976556 ps
CPU time 23.86 seconds
Started Jun 27 04:22:23 PM PDT 24
Finished Jun 27 04:22:48 PM PDT 24
Peak memory 211776 kb
Host smart-20d3d714-73dd-4dbb-9dca-44caaf024de6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036175038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.4036175038
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2696993801
Short name T404
Test name
Test status
Simulation time 2992735072 ps
CPU time 29.07 seconds
Started Jun 27 04:22:23 PM PDT 24
Finished Jun 27 04:22:53 PM PDT 24
Peak memory 217884 kb
Host smart-6b959acd-3144-4f51-8ce5-57b1b8b09af1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696993801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2696993801
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.756286381
Short name T68
Test name
Test status
Simulation time 1153153598 ps
CPU time 164.01 seconds
Started Jun 27 04:18:30 PM PDT 24
Finished Jun 27 04:21:15 PM PDT 24
Peak memory 212852 kb
Host smart-d3fa312f-c94f-4fbd-a40f-3de27146cca2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756286381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.756286381
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2531370011
Short name T406
Test name
Test status
Simulation time 5485268581 ps
CPU time 24.29 seconds
Started Jun 27 04:20:10 PM PDT 24
Finished Jun 27 04:20:36 PM PDT 24
Peak memory 214468 kb
Host smart-fd705429-670d-44a3-aaa5-d48670eaed7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531370011 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2531370011
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.724149859
Short name T407
Test name
Test status
Simulation time 9984430510 ps
CPU time 32.69 seconds
Started Jun 27 04:19:24 PM PDT 24
Finished Jun 27 04:19:58 PM PDT 24
Peak memory 211936 kb
Host smart-8a28c441-a05c-4a66-baeb-2cbd1d0c26f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724149859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.724149859
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1110764795
Short name T72
Test name
Test status
Simulation time 72844211761 ps
CPU time 128.42 seconds
Started Jun 27 04:22:48 PM PDT 24
Finished Jun 27 04:24:59 PM PDT 24
Peak memory 213768 kb
Host smart-8150d8d7-405f-4a8e-b0f6-489d98b93698
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110764795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1110764795
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2121256857
Short name T109
Test name
Test status
Simulation time 19982437998 ps
CPU time 29.95 seconds
Started Jun 27 04:20:55 PM PDT 24
Finished Jun 27 04:21:27 PM PDT 24
Peak memory 212340 kb
Host smart-dd72ce88-d21c-490b-8fe1-8995e25c0689
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121256857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2121256857
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.230466513
Short name T426
Test name
Test status
Simulation time 746044856 ps
CPU time 17.15 seconds
Started Jun 27 04:22:41 PM PDT 24
Finished Jun 27 04:23:02 PM PDT 24
Peak memory 218280 kb
Host smart-f265cc15-d7c0-45ee-bd26-dc3142eaa730
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230466513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.230466513
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3549746537
Short name T370
Test name
Test status
Simulation time 12651937964 ps
CPU time 27.03 seconds
Started Jun 27 04:20:10 PM PDT 24
Finished Jun 27 04:20:38 PM PDT 24
Peak memory 217352 kb
Host smart-5cdb529c-a72e-4cb9-924d-1b6577c34813
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549746537 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3549746537
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3618664487
Short name T413
Test name
Test status
Simulation time 56132560731 ps
CPU time 29.6 seconds
Started Jun 27 04:23:13 PM PDT 24
Finished Jun 27 04:23:47 PM PDT 24
Peak memory 211992 kb
Host smart-7b541994-0c26-42e7-b31b-3ac870fbbd8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618664487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3618664487
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3599001938
Short name T87
Test name
Test status
Simulation time 19066772184 ps
CPU time 162.29 seconds
Started Jun 27 04:17:46 PM PDT 24
Finished Jun 27 04:20:31 PM PDT 24
Peak memory 214972 kb
Host smart-4ccb2cc2-9d3b-4c16-90dd-67118e55264d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599001938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3599001938
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3451715295
Short name T82
Test name
Test status
Simulation time 4166586510 ps
CPU time 33.36 seconds
Started Jun 27 04:19:56 PM PDT 24
Finished Jun 27 04:20:30 PM PDT 24
Peak memory 212400 kb
Host smart-1c218404-1b6b-40dc-87e3-650553b3486d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451715295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3451715295
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.818654284
Short name T422
Test name
Test status
Simulation time 1319799904 ps
CPU time 14.77 seconds
Started Jun 27 04:22:22 PM PDT 24
Finished Jun 27 04:22:38 PM PDT 24
Peak memory 214784 kb
Host smart-1823c308-ba9b-44fe-94da-e0ddeb009200
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818654284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.818654284
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2628494706
Short name T421
Test name
Test status
Simulation time 1188658173 ps
CPU time 84.35 seconds
Started Jun 27 04:20:36 PM PDT 24
Finished Jun 27 04:22:03 PM PDT 24
Peak memory 213580 kb
Host smart-ca0e0971-3a0f-4b16-8e38-acb150bb90b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628494706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2628494706
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.884118943
Short name T394
Test name
Test status
Simulation time 24968666133 ps
CPU time 24.6 seconds
Started Jun 27 04:22:41 PM PDT 24
Finished Jun 27 04:23:09 PM PDT 24
Peak memory 216752 kb
Host smart-35072701-be7e-442d-85c5-ed5344857dca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884118943 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.884118943
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.859508877
Short name T401
Test name
Test status
Simulation time 1676966101 ps
CPU time 18.06 seconds
Started Jun 27 04:18:34 PM PDT 24
Finished Jun 27 04:18:53 PM PDT 24
Peak memory 211728 kb
Host smart-65511a1b-dfab-4c1b-bd5b-1323e545f9af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859508877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.859508877
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2019427715
Short name T436
Test name
Test status
Simulation time 13098493604 ps
CPU time 129.38 seconds
Started Jun 27 04:22:47 PM PDT 24
Finished Jun 27 04:24:59 PM PDT 24
Peak memory 213640 kb
Host smart-9cced071-d1fe-46fe-bcb0-d6f24072a2ed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019427715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2019427715
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.999715546
Short name T105
Test name
Test status
Simulation time 360909618 ps
CPU time 8.64 seconds
Started Jun 27 04:20:09 PM PDT 24
Finished Jun 27 04:20:19 PM PDT 24
Peak memory 211500 kb
Host smart-506ca1c2-9c17-4b2d-9089-9197c1b4d79f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999715546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.999715546
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.843342263
Short name T427
Test name
Test status
Simulation time 13613983703 ps
CPU time 27.39 seconds
Started Jun 27 04:20:04 PM PDT 24
Finished Jun 27 04:20:32 PM PDT 24
Peak memory 218444 kb
Host smart-4ce8d87e-3afe-4137-8210-398f475536ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843342263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.843342263
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3138108169
Short name T66
Test name
Test status
Simulation time 26261160737 ps
CPU time 101.5 seconds
Started Jun 27 04:17:43 PM PDT 24
Finished Jun 27 04:19:27 PM PDT 24
Peak memory 213892 kb
Host smart-dd998a47-1268-41f1-a846-a7a481c38f33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138108169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3138108169
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2702010048
Short name T415
Test name
Test status
Simulation time 3757249414 ps
CPU time 30.8 seconds
Started Jun 27 04:20:09 PM PDT 24
Finished Jun 27 04:20:41 PM PDT 24
Peak memory 217608 kb
Host smart-428d5c9f-01b6-4763-b73e-b82a7f40560e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702010048 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2702010048
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.911002287
Short name T408
Test name
Test status
Simulation time 3797606675 ps
CPU time 17.56 seconds
Started Jun 27 04:20:06 PM PDT 24
Finished Jun 27 04:20:25 PM PDT 24
Peak memory 211072 kb
Host smart-990540d7-2856-4d4e-b808-b40ea12adef6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911002287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.911002287
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1411603741
Short name T405
Test name
Test status
Simulation time 176842760 ps
CPU time 12.16 seconds
Started Jun 27 04:19:02 PM PDT 24
Finished Jun 27 04:19:15 PM PDT 24
Peak memory 212220 kb
Host smart-43a3d9e7-87f9-4e85-b6ec-a58557e16c68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411603741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1411603741
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3991356434
Short name T362
Test name
Test status
Simulation time 749788196 ps
CPU time 11.41 seconds
Started Jun 27 04:17:51 PM PDT 24
Finished Jun 27 04:18:03 PM PDT 24
Peak memory 218808 kb
Host smart-4183127a-b47a-4619-84b3-a176307d30db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991356434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3991356434
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3168262757
Short name T123
Test name
Test status
Simulation time 24824101759 ps
CPU time 155.46 seconds
Started Jun 27 04:23:15 PM PDT 24
Finished Jun 27 04:25:56 PM PDT 24
Peak memory 214004 kb
Host smart-b07ad38d-111b-4d03-b410-44abd109dc8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168262757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3168262757
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4616760
Short name T396
Test name
Test status
Simulation time 16488454552 ps
CPU time 29.66 seconds
Started Jun 27 04:22:36 PM PDT 24
Finished Jun 27 04:23:07 PM PDT 24
Peak memory 217192 kb
Host smart-f7dfd65e-aabb-4e44-8be7-780414ffe943
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4616760 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.4616760
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2051097970
Short name T437
Test name
Test status
Simulation time 891106273 ps
CPU time 12.64 seconds
Started Jun 27 04:22:56 PM PDT 24
Finished Jun 27 04:23:09 PM PDT 24
Peak memory 211632 kb
Host smart-7d0496bd-4d7c-4551-a61b-b660840593da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051097970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2051097970
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.136270433
Short name T115
Test name
Test status
Simulation time 4947604741 ps
CPU time 88.17 seconds
Started Jun 27 04:20:38 PM PDT 24
Finished Jun 27 04:22:10 PM PDT 24
Peak memory 214880 kb
Host smart-ebe4275c-7e42-4de6-a8a8-ac436383baa5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136270433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.136270433
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3283723839
Short name T400
Test name
Test status
Simulation time 8981680322 ps
CPU time 20.35 seconds
Started Jun 27 04:17:40 PM PDT 24
Finished Jun 27 04:18:02 PM PDT 24
Peak memory 212628 kb
Host smart-b7b7190d-202f-4a29-8e66-a63151499434
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283723839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3283723839
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.335653635
Short name T452
Test name
Test status
Simulation time 2659652631 ps
CPU time 26.48 seconds
Started Jun 27 04:22:22 PM PDT 24
Finished Jun 27 04:22:50 PM PDT 24
Peak memory 217356 kb
Host smart-59fb5852-b4a2-4770-8e59-e080b3de8e77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335653635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.335653635
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.641061398
Short name T420
Test name
Test status
Simulation time 4100774317 ps
CPU time 105.85 seconds
Started Jun 27 04:21:07 PM PDT 24
Finished Jun 27 04:22:54 PM PDT 24
Peak memory 213532 kb
Host smart-b47f97b7-e846-45e7-9358-fdbcb3214fdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641061398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.641061398
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3606647026
Short name T392
Test name
Test status
Simulation time 2412583287 ps
CPU time 23.08 seconds
Started Jun 27 04:22:41 PM PDT 24
Finished Jun 27 04:23:08 PM PDT 24
Peak memory 217328 kb
Host smart-ae8bfddb-b709-4ecc-9a1b-93408d5cefda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606647026 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3606647026
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.706612385
Short name T443
Test name
Test status
Simulation time 16751051536 ps
CPU time 27.48 seconds
Started Jun 27 04:21:24 PM PDT 24
Finished Jun 27 04:21:52 PM PDT 24
Peak memory 212348 kb
Host smart-a55b0949-d80a-406c-ab41-593bc8f87211
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706612385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.706612385
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2129596516
Short name T386
Test name
Test status
Simulation time 3759408864 ps
CPU time 59.78 seconds
Started Jun 27 04:22:40 PM PDT 24
Finished Jun 27 04:23:43 PM PDT 24
Peak memory 213432 kb
Host smart-9b1d46d5-5715-466b-a83c-7cbc1b38064d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129596516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2129596516
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2406993615
Short name T453
Test name
Test status
Simulation time 1122767606 ps
CPU time 18.13 seconds
Started Jun 27 04:23:02 PM PDT 24
Finished Jun 27 04:23:22 PM PDT 24
Peak memory 211408 kb
Host smart-0d9ddd7e-d014-4bb5-8c75-ea3fd0d0e017
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406993615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2406993615
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.655377923
Short name T375
Test name
Test status
Simulation time 174657851 ps
CPU time 10.68 seconds
Started Jun 27 04:22:22 PM PDT 24
Finished Jun 27 04:22:34 PM PDT 24
Peak memory 216656 kb
Host smart-6aab75bb-83ed-4805-af03-be9a31dc8f1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655377923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.655377923
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.22818079
Short name T398
Test name
Test status
Simulation time 174662734 ps
CPU time 8.12 seconds
Started Jun 27 04:17:33 PM PDT 24
Finished Jun 27 04:17:44 PM PDT 24
Peak memory 207880 kb
Host smart-73fd457c-689b-4279-8285-3d6117160803
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22818079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasi
ng.22818079
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2055676886
Short name T71
Test name
Test status
Simulation time 1428981411 ps
CPU time 10.29 seconds
Started Jun 27 04:17:35 PM PDT 24
Finished Jun 27 04:17:49 PM PDT 24
Peak memory 209604 kb
Host smart-9556ddfb-c09d-4d91-a4b0-c6834d783988
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055676886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2055676886
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3299008111
Short name T80
Test name
Test status
Simulation time 57491444421 ps
CPU time 32.09 seconds
Started Jun 27 04:17:34 PM PDT 24
Finished Jun 27 04:18:08 PM PDT 24
Peak memory 212116 kb
Host smart-65df4c88-cab9-4eba-a836-40ef9b8a56b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299008111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3299008111
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3961336821
Short name T368
Test name
Test status
Simulation time 17389982413 ps
CPU time 19.37 seconds
Started Jun 27 04:17:36 PM PDT 24
Finished Jun 27 04:17:59 PM PDT 24
Peak memory 217536 kb
Host smart-7a3f69dd-1c7e-4178-a781-b4eeb883717c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961336821 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3961336821
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2161679349
Short name T440
Test name
Test status
Simulation time 12897849195 ps
CPU time 28.84 seconds
Started Jun 27 04:19:40 PM PDT 24
Finished Jun 27 04:20:11 PM PDT 24
Peak memory 212188 kb
Host smart-e14c1223-3a12-4418-9a1c-f0105357bea3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161679349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2161679349
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3261471550
Short name T393
Test name
Test status
Simulation time 3931080235 ps
CPU time 30.55 seconds
Started Jun 27 04:17:33 PM PDT 24
Finished Jun 27 04:18:06 PM PDT 24
Peak memory 207620 kb
Host smart-0dc3c9a6-9823-412c-8f7c-acdf2f377aa8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261471550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3261471550
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.831849279
Short name T365
Test name
Test status
Simulation time 612799432 ps
CPU time 7.92 seconds
Started Jun 27 04:23:03 PM PDT 24
Finished Jun 27 04:23:14 PM PDT 24
Peak memory 209464 kb
Host smart-421d7197-7c67-40a9-a659-b59335101ff9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831849279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
831849279
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1131145342
Short name T101
Test name
Test status
Simulation time 2512031919 ps
CPU time 71.73 seconds
Started Jun 27 04:23:19 PM PDT 24
Finished Jun 27 04:24:41 PM PDT 24
Peak memory 214660 kb
Host smart-d15e564d-9ed2-4ce4-ac02-3402795c1662
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131145342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1131145342
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.479696890
Short name T442
Test name
Test status
Simulation time 9184619241 ps
CPU time 22.08 seconds
Started Jun 27 04:17:27 PM PDT 24
Finished Jun 27 04:17:50 PM PDT 24
Peak memory 211372 kb
Host smart-3083dcfc-a7fa-4a4f-bd78-27a22a0361b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479696890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.479696890
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1175936661
Short name T441
Test name
Test status
Simulation time 33783653542 ps
CPU time 25.57 seconds
Started Jun 27 04:17:35 PM PDT 24
Finished Jun 27 04:18:04 PM PDT 24
Peak memory 218092 kb
Host smart-db893811-239a-4432-aef1-0e5bf54eaaf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175936661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1175936661
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2588181808
Short name T449
Test name
Test status
Simulation time 7193777044 ps
CPU time 93.85 seconds
Started Jun 27 04:17:35 PM PDT 24
Finished Jun 27 04:19:13 PM PDT 24
Peak memory 212364 kb
Host smart-19875a03-33e7-435e-b513-650e08e65d9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588181808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2588181808
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.754703213
Short name T434
Test name
Test status
Simulation time 10934581939 ps
CPU time 20.33 seconds
Started Jun 27 04:18:17 PM PDT 24
Finished Jun 27 04:18:38 PM PDT 24
Peak memory 210524 kb
Host smart-3cd13f1a-3d3a-41aa-be95-6cbc47e4266f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754703213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.754703213
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2033941059
Short name T84
Test name
Test status
Simulation time 14099760576 ps
CPU time 27.74 seconds
Started Jun 27 04:17:34 PM PDT 24
Finished Jun 27 04:18:05 PM PDT 24
Peak memory 210976 kb
Host smart-c73a4e25-92d9-4ecd-92e5-b202ba7bbe97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033941059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2033941059
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2550804268
Short name T86
Test name
Test status
Simulation time 171040268 ps
CPU time 11.63 seconds
Started Jun 27 04:17:31 PM PDT 24
Finished Jun 27 04:17:44 PM PDT 24
Peak memory 210256 kb
Host smart-c7205b3e-a035-4c65-a7f2-ca8bd9e428e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550804268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2550804268
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.4274495026
Short name T371
Test name
Test status
Simulation time 3964850080 ps
CPU time 19.08 seconds
Started Jun 27 04:17:36 PM PDT 24
Finished Jun 27 04:17:59 PM PDT 24
Peak memory 217468 kb
Host smart-15212c15-40e9-4da8-90f6-0da411d8cc6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274495026 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.4274495026
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3790681457
Short name T381
Test name
Test status
Simulation time 6844147895 ps
CPU time 21.27 seconds
Started Jun 27 04:17:33 PM PDT 24
Finished Jun 27 04:17:56 PM PDT 24
Peak memory 211836 kb
Host smart-d2cdb6f5-e84b-4252-b928-d923b1f20ff3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790681457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3790681457
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3210030598
Short name T397
Test name
Test status
Simulation time 20516248521 ps
CPU time 31.75 seconds
Started Jun 27 04:17:34 PM PDT 24
Finished Jun 27 04:18:10 PM PDT 24
Peak memory 211156 kb
Host smart-072679b6-1d28-4049-9d84-dd0c0fe36458
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210030598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3210030598
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2693767598
Short name T384
Test name
Test status
Simulation time 824539200 ps
CPU time 7.71 seconds
Started Jun 27 04:17:36 PM PDT 24
Finished Jun 27 04:17:48 PM PDT 24
Peak memory 210048 kb
Host smart-2878b767-2c3d-424b-adcf-1297f9e0103f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693767598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2693767598
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.475861492
Short name T447
Test name
Test status
Simulation time 14428505650 ps
CPU time 83.14 seconds
Started Jun 27 04:17:33 PM PDT 24
Finished Jun 27 04:18:59 PM PDT 24
Peak memory 214432 kb
Host smart-be540106-eda5-4684-9069-18c2d985ed99
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475861492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.475861492
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.4091618
Short name T423
Test name
Test status
Simulation time 4104602037 ps
CPU time 35.03 seconds
Started Jun 27 04:17:27 PM PDT 24
Finished Jun 27 04:18:03 PM PDT 24
Peak memory 212124 kb
Host smart-66777a1b-e32c-47c1-aec1-4a2279c27f29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_same_csr_outstanding.4091618
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2135774292
Short name T374
Test name
Test status
Simulation time 17307282175 ps
CPU time 37.65 seconds
Started Jun 27 04:17:31 PM PDT 24
Finished Jun 27 04:18:10 PM PDT 24
Peak memory 218612 kb
Host smart-1da09986-6506-42c3-a4b2-90815c3d27dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135774292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2135774292
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3839845283
Short name T129
Test name
Test status
Simulation time 4979179453 ps
CPU time 178.7 seconds
Started Jun 27 04:17:26 PM PDT 24
Finished Jun 27 04:20:26 PM PDT 24
Peak memory 213672 kb
Host smart-8635996f-b552-47fc-9d3d-217eae12821d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839845283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3839845283
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2826880706
Short name T377
Test name
Test status
Simulation time 13417420219 ps
CPU time 19.92 seconds
Started Jun 27 04:17:34 PM PDT 24
Finished Jun 27 04:17:57 PM PDT 24
Peak memory 211656 kb
Host smart-e6ab1e6e-652e-48e1-8dec-f06c94201191
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826880706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2826880706
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.603751119
Short name T70
Test name
Test status
Simulation time 3932877198 ps
CPU time 30.94 seconds
Started Jun 27 04:17:33 PM PDT 24
Finished Jun 27 04:18:07 PM PDT 24
Peak memory 208260 kb
Host smart-f393198c-c402-4eaf-b999-58eebd41e71e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603751119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.603751119
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.690500357
Short name T389
Test name
Test status
Simulation time 599079442 ps
CPU time 11.65 seconds
Started Jun 27 04:17:26 PM PDT 24
Finished Jun 27 04:17:39 PM PDT 24
Peak memory 209164 kb
Host smart-25a6a1cd-8a6e-488b-9833-f350c84c06e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690500357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.690500357
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3617956150
Short name T388
Test name
Test status
Simulation time 6169434304 ps
CPU time 15.61 seconds
Started Jun 27 04:17:36 PM PDT 24
Finished Jun 27 04:17:55 PM PDT 24
Peak memory 216060 kb
Host smart-6094686e-bd48-4e23-8fdc-58400ab79da4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617956150 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3617956150
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3918351070
Short name T97
Test name
Test status
Simulation time 839999815 ps
CPU time 11.25 seconds
Started Jun 27 04:17:34 PM PDT 24
Finished Jun 27 04:17:49 PM PDT 24
Peak memory 211020 kb
Host smart-0d158235-f2fb-41e7-a975-0234570eb831
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918351070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3918351070
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2400976922
Short name T378
Test name
Test status
Simulation time 3032895335 ps
CPU time 23.08 seconds
Started Jun 27 04:17:36 PM PDT 24
Finished Jun 27 04:18:03 PM PDT 24
Peak memory 210164 kb
Host smart-d3e82caf-01f6-46c1-be52-ddff5af35f0c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400976922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2400976922
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.649646428
Short name T416
Test name
Test status
Simulation time 167402886 ps
CPU time 7.71 seconds
Started Jun 27 04:17:36 PM PDT 24
Finished Jun 27 04:17:48 PM PDT 24
Peak memory 210024 kb
Host smart-fb6fd102-93de-417a-a6c9-3fbe5340e2aa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649646428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
649646428
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1925056405
Short name T438
Test name
Test status
Simulation time 6004668865 ps
CPU time 92.38 seconds
Started Jun 27 04:17:35 PM PDT 24
Finished Jun 27 04:19:11 PM PDT 24
Peak memory 214664 kb
Host smart-fba43653-7dd4-478a-ba52-81510fd2acc6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925056405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1925056405
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4289515177
Short name T432
Test name
Test status
Simulation time 925881150 ps
CPU time 13.89 seconds
Started Jun 27 04:17:26 PM PDT 24
Finished Jun 27 04:17:41 PM PDT 24
Peak memory 209764 kb
Host smart-22ee7473-67ab-4bb5-839e-1f6127661686
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289515177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.4289515177
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.254037620
Short name T409
Test name
Test status
Simulation time 8889604904 ps
CPU time 37.33 seconds
Started Jun 27 04:17:36 PM PDT 24
Finished Jun 27 04:18:17 PM PDT 24
Peak memory 218096 kb
Host smart-2182c0d3-47e9-4555-8607-36a83e5371b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254037620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.254037620
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4128624757
Short name T125
Test name
Test status
Simulation time 975842712 ps
CPU time 161.81 seconds
Started Jun 27 04:18:41 PM PDT 24
Finished Jun 27 04:21:24 PM PDT 24
Peak memory 213920 kb
Host smart-238d4065-c04c-4bfe-8ff5-1bc863c10eb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128624757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.4128624757
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.587698851
Short name T425
Test name
Test status
Simulation time 171521393 ps
CPU time 8.22 seconds
Started Jun 27 04:17:35 PM PDT 24
Finished Jun 27 04:17:47 PM PDT 24
Peak memory 214936 kb
Host smart-61ee4835-2e8e-43b1-a3d4-9106ea5fbf4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587698851 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.587698851
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2693022998
Short name T99
Test name
Test status
Simulation time 10772350763 ps
CPU time 23.01 seconds
Started Jun 27 04:17:35 PM PDT 24
Finished Jun 27 04:18:02 PM PDT 24
Peak memory 211772 kb
Host smart-4a6b7479-60ee-404b-b724-2649a22e6d5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693022998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2693022998
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.149669802
Short name T93
Test name
Test status
Simulation time 1077288809 ps
CPU time 57.45 seconds
Started Jun 27 04:17:33 PM PDT 24
Finished Jun 27 04:18:33 PM PDT 24
Peak memory 211144 kb
Host smart-3a57e39b-5e53-4f7b-a5a8-d4b06d38587f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149669802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.149669802
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2537155267
Short name T403
Test name
Test status
Simulation time 2726091036 ps
CPU time 23.85 seconds
Started Jun 27 04:21:18 PM PDT 24
Finished Jun 27 04:21:42 PM PDT 24
Peak memory 212240 kb
Host smart-75af01ae-58ab-4a32-b4a6-0364759a059d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537155267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2537155267
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1299838728
Short name T385
Test name
Test status
Simulation time 5545836301 ps
CPU time 26.83 seconds
Started Jun 27 04:23:03 PM PDT 24
Finished Jun 27 04:23:33 PM PDT 24
Peak memory 216508 kb
Host smart-3eb57a52-f28d-482b-8bb0-2b24426564f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299838728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1299838728
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.588182025
Short name T127
Test name
Test status
Simulation time 1349100517 ps
CPU time 156.7 seconds
Started Jun 27 04:17:47 PM PDT 24
Finished Jun 27 04:20:26 PM PDT 24
Peak memory 213680 kb
Host smart-0f512212-9a98-4c78-a2ad-7256d258eefb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588182025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.588182025
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.961571284
Short name T451
Test name
Test status
Simulation time 8048705553 ps
CPU time 31.52 seconds
Started Jun 27 04:17:36 PM PDT 24
Finished Jun 27 04:18:11 PM PDT 24
Peak memory 218164 kb
Host smart-0d47ecea-2675-4feb-b506-571d2c026847
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961571284 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.961571284
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2760684754
Short name T373
Test name
Test status
Simulation time 4112795919 ps
CPU time 31.9 seconds
Started Jun 27 04:23:19 PM PDT 24
Finished Jun 27 04:24:01 PM PDT 24
Peak memory 211144 kb
Host smart-01cff6f0-e425-473a-a4d9-8faa81925243
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760684754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2760684754
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2237866546
Short name T446
Test name
Test status
Simulation time 44542579022 ps
CPU time 116.11 seconds
Started Jun 27 04:17:34 PM PDT 24
Finished Jun 27 04:19:34 PM PDT 24
Peak memory 214028 kb
Host smart-8dfc3eb1-4ac6-4dc3-9662-9c20d68ba36c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237866546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2237866546
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.840886264
Short name T414
Test name
Test status
Simulation time 1278549186 ps
CPU time 15.95 seconds
Started Jun 27 04:17:35 PM PDT 24
Finished Jun 27 04:17:55 PM PDT 24
Peak memory 210420 kb
Host smart-acd5b15a-42d3-4036-a0ac-da1a6eb3adcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840886264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.840886264
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2421438761
Short name T417
Test name
Test status
Simulation time 167695587 ps
CPU time 12.04 seconds
Started Jun 27 04:20:37 PM PDT 24
Finished Jun 27 04:20:52 PM PDT 24
Peak memory 218812 kb
Host smart-e826c053-b5f0-439e-ad95-12caddcbb2f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421438761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2421438761
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.141686966
Short name T120
Test name
Test status
Simulation time 2284764843 ps
CPU time 91.63 seconds
Started Jun 27 04:17:36 PM PDT 24
Finished Jun 27 04:19:11 PM PDT 24
Peak memory 212920 kb
Host smart-1441ffe9-07c1-4025-a6e7-f09f72397d8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141686966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.141686966
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.374023845
Short name T391
Test name
Test status
Simulation time 2889412987 ps
CPU time 25.72 seconds
Started Jun 27 04:17:32 PM PDT 24
Finished Jun 27 04:17:58 PM PDT 24
Peak memory 216996 kb
Host smart-ce9dd0c6-8266-4278-8d9d-5e780a7177c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374023845 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.374023845
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.625606717
Short name T433
Test name
Test status
Simulation time 170991084 ps
CPU time 8.05 seconds
Started Jun 27 04:17:34 PM PDT 24
Finished Jun 27 04:17:46 PM PDT 24
Peak memory 210084 kb
Host smart-6b0f8fe6-5765-4b62-b327-058287916a22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625606717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.625606717
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2515693833
Short name T419
Test name
Test status
Simulation time 6257258422 ps
CPU time 78.15 seconds
Started Jun 27 04:18:34 PM PDT 24
Finished Jun 27 04:19:52 PM PDT 24
Peak memory 214752 kb
Host smart-b3b9dd88-7fd7-4b9d-9f4f-744db74ff1b1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515693833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2515693833
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3842532190
Short name T444
Test name
Test status
Simulation time 174534486 ps
CPU time 7.86 seconds
Started Jun 27 04:17:36 PM PDT 24
Finished Jun 27 04:17:48 PM PDT 24
Peak memory 210800 kb
Host smart-07f27909-16ae-4c70-9ef9-78fbf8908ce1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842532190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3842532190
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1532738513
Short name T382
Test name
Test status
Simulation time 352805930 ps
CPU time 12.47 seconds
Started Jun 27 04:17:34 PM PDT 24
Finished Jun 27 04:17:49 PM PDT 24
Peak memory 217600 kb
Host smart-39d302a7-8152-494e-b62b-419c2386b028
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532738513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1532738513
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.199965275
Short name T119
Test name
Test status
Simulation time 9476207354 ps
CPU time 86.95 seconds
Started Jun 27 04:17:35 PM PDT 24
Finished Jun 27 04:19:06 PM PDT 24
Peak memory 213004 kb
Host smart-019e5690-3da8-4abb-be3a-399b3d250442
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199965275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.199965275
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1416072336
Short name T383
Test name
Test status
Simulation time 19698971757 ps
CPU time 28.79 seconds
Started Jun 27 04:23:07 PM PDT 24
Finished Jun 27 04:23:41 PM PDT 24
Peak memory 217640 kb
Host smart-f7ca64a0-9102-46aa-be63-87af4fe03fba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416072336 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1416072336
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4085832543
Short name T111
Test name
Test status
Simulation time 9329249559 ps
CPU time 20.06 seconds
Started Jun 27 04:23:21 PM PDT 24
Finished Jun 27 04:23:53 PM PDT 24
Peak memory 211828 kb
Host smart-fe191723-8cdc-48f5-a292-3b4f09ee4443
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085832543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.4085832543
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2510803101
Short name T110
Test name
Test status
Simulation time 2407387491 ps
CPU time 12.23 seconds
Started Jun 27 04:17:30 PM PDT 24
Finished Jun 27 04:17:43 PM PDT 24
Peak memory 211140 kb
Host smart-3c33a8fa-fd21-4204-98fa-78384638ec86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510803101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2510803101
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2959337816
Short name T369
Test name
Test status
Simulation time 14365544427 ps
CPU time 32.84 seconds
Started Jun 27 04:17:31 PM PDT 24
Finished Jun 27 04:18:05 PM PDT 24
Peak memory 218060 kb
Host smart-01bb7770-8e12-4495-b57d-4812dc73419e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959337816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2959337816
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.964679060
Short name T117
Test name
Test status
Simulation time 1782776507 ps
CPU time 90.3 seconds
Started Jun 27 04:17:33 PM PDT 24
Finished Jun 27 04:19:04 PM PDT 24
Peak memory 213288 kb
Host smart-30e8da93-10ca-44e9-b8ab-71d071cd1ee1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964679060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.964679060
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2191480645
Short name T367
Test name
Test status
Simulation time 2318406760 ps
CPU time 15.47 seconds
Started Jun 27 04:22:36 PM PDT 24
Finished Jun 27 04:22:52 PM PDT 24
Peak memory 215508 kb
Host smart-f65793d8-2085-4fa7-9a8a-7fafded1bfb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191480645 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2191480645
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.110081208
Short name T379
Test name
Test status
Simulation time 2548637888 ps
CPU time 24.08 seconds
Started Jun 27 04:19:17 PM PDT 24
Finished Jun 27 04:19:42 PM PDT 24
Peak memory 211268 kb
Host smart-7ae86b9e-f8f3-4b57-b316-4cbd4cdb94ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110081208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.110081208
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3816937204
Short name T103
Test name
Test status
Simulation time 51062603927 ps
CPU time 112.23 seconds
Started Jun 27 04:23:08 PM PDT 24
Finished Jun 27 04:25:04 PM PDT 24
Peak memory 213744 kb
Host smart-625e0867-b297-45cb-b0bf-8064eb9ca517
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816937204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3816937204
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.299655249
Short name T106
Test name
Test status
Simulation time 694604090 ps
CPU time 12.51 seconds
Started Jun 27 04:20:56 PM PDT 24
Finished Jun 27 04:21:10 PM PDT 24
Peak memory 212372 kb
Host smart-a323e7d0-30a3-454d-8285-510e2f4f31ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299655249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.299655249
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2829943837
Short name T412
Test name
Test status
Simulation time 17628024314 ps
CPU time 24.7 seconds
Started Jun 27 04:19:54 PM PDT 24
Finished Jun 27 04:20:20 PM PDT 24
Peak memory 218764 kb
Host smart-cb018428-5a7a-4705-9ec6-b847a3682df7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829943837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2829943837
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.275294217
Short name T116
Test name
Test status
Simulation time 13594263948 ps
CPU time 97.05 seconds
Started Jun 27 04:22:40 PM PDT 24
Finished Jun 27 04:24:19 PM PDT 24
Peak memory 213092 kb
Host smart-48a95f49-6bb9-40e9-b07d-d476cb887bf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275294217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.275294217
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2883935308
Short name T249
Test name
Test status
Simulation time 13051764335 ps
CPU time 27.49 seconds
Started Jun 27 04:39:31 PM PDT 24
Finished Jun 27 04:40:00 PM PDT 24
Peak memory 217352 kb
Host smart-2178b8a0-4437-4cc4-9d60-20ebd4ac36ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883935308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2883935308
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3416625448
Short name T287
Test name
Test status
Simulation time 17183691549 ps
CPU time 347.75 seconds
Started Jun 27 04:39:31 PM PDT 24
Finished Jun 27 04:45:20 PM PDT 24
Peak memory 250352 kb
Host smart-28e76b49-5e27-4177-9217-3b448c89dbfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416625448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3416625448
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2123833279
Short name T35
Test name
Test status
Simulation time 13664539329 ps
CPU time 64.03 seconds
Started Jun 27 04:39:32 PM PDT 24
Finished Jun 27 04:40:37 PM PDT 24
Peak memory 219252 kb
Host smart-17c7a817-02ee-43c7-8119-df6c6409db15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123833279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2123833279
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.496550285
Short name T328
Test name
Test status
Simulation time 4594318812 ps
CPU time 15.22 seconds
Started Jun 27 04:39:31 PM PDT 24
Finished Jun 27 04:39:47 PM PDT 24
Peak memory 219268 kb
Host smart-f9fba823-2727-4e57-a5f5-de90696e8601
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=496550285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.496550285
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3099959136
Short name T24
Test name
Test status
Simulation time 4301422828 ps
CPU time 138.66 seconds
Started Jun 27 04:39:27 PM PDT 24
Finished Jun 27 04:41:46 PM PDT 24
Peak memory 238360 kb
Host smart-082cede0-d2de-4ece-87ad-2e6042564376
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099959136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3099959136
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3171568427
Short name T325
Test name
Test status
Simulation time 3267620659 ps
CPU time 39.39 seconds
Started Jun 27 04:39:27 PM PDT 24
Finished Jun 27 04:40:07 PM PDT 24
Peak memory 216812 kb
Host smart-02fb0002-33a3-4dd2-952f-0f5f5daea1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171568427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3171568427
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1040287456
Short name T262
Test name
Test status
Simulation time 23495225417 ps
CPU time 19.39 seconds
Started Jun 27 04:39:43 PM PDT 24
Finished Jun 27 04:40:04 PM PDT 24
Peak memory 213160 kb
Host smart-9206264e-162b-406d-93a4-7fdba6be00de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040287456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1040287456
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.601653022
Short name T41
Test name
Test status
Simulation time 16380317334 ps
CPU time 314.04 seconds
Started Jun 27 04:39:43 PM PDT 24
Finished Jun 27 04:44:58 PM PDT 24
Peak memory 224560 kb
Host smart-347e8ee9-2db4-4701-95e4-aec4d2931149
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601653022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_co
rrupt_sig_fatal_chk.601653022
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2050794782
Short name T243
Test name
Test status
Simulation time 24905950895 ps
CPU time 56.55 seconds
Started Jun 27 04:39:39 PM PDT 24
Finished Jun 27 04:40:37 PM PDT 24
Peak memory 219224 kb
Host smart-f9309a57-d431-4769-a4b4-522c57772cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050794782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2050794782
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1334983610
Short name T193
Test name
Test status
Simulation time 3119205654 ps
CPU time 15.35 seconds
Started Jun 27 04:39:44 PM PDT 24
Finished Jun 27 04:40:01 PM PDT 24
Peak memory 219320 kb
Host smart-f9a19823-213e-4c57-a3a6-17aa7a13b7d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1334983610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1334983610
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1719540388
Short name T22
Test name
Test status
Simulation time 3801060395 ps
CPU time 244.91 seconds
Started Jun 27 04:39:43 PM PDT 24
Finished Jun 27 04:43:50 PM PDT 24
Peak memory 237744 kb
Host smart-12cd7e5c-777e-4556-9992-ad2c88f89c1b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719540388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1719540388
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1984903277
Short name T283
Test name
Test status
Simulation time 5576112271 ps
CPU time 52.95 seconds
Started Jun 27 04:39:29 PM PDT 24
Finished Jun 27 04:40:23 PM PDT 24
Peak memory 216252 kb
Host smart-8cbb3f6f-2c55-4df2-834f-fac0d86cf7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984903277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1984903277
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3420949668
Short name T27
Test name
Test status
Simulation time 3103181153 ps
CPU time 52.38 seconds
Started Jun 27 04:39:43 PM PDT 24
Finished Jun 27 04:40:37 PM PDT 24
Peak memory 218928 kb
Host smart-b75c0aac-93cb-444a-b33c-ac64cd995622
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420949668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3420949668
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1031566734
Short name T79
Test name
Test status
Simulation time 3775511851 ps
CPU time 28.89 seconds
Started Jun 27 04:39:53 PM PDT 24
Finished Jun 27 04:40:30 PM PDT 24
Peak memory 217008 kb
Host smart-7bb9e464-266d-486a-ac70-4a4f8793496d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031566734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1031566734
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1591401159
Short name T230
Test name
Test status
Simulation time 155444047910 ps
CPU time 340.06 seconds
Started Jun 27 04:39:53 PM PDT 24
Finished Jun 27 04:45:41 PM PDT 24
Peak memory 219340 kb
Host smart-a28128a9-60fb-470a-9de2-bd3b185072ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591401159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1591401159
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.4003144792
Short name T131
Test name
Test status
Simulation time 3193057944 ps
CPU time 27.16 seconds
Started Jun 27 04:39:52 PM PDT 24
Finished Jun 27 04:40:27 PM PDT 24
Peak memory 211436 kb
Host smart-fb788840-78e9-4535-8370-6e9113867bde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4003144792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.4003144792
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1923103906
Short name T268
Test name
Test status
Simulation time 17059012273 ps
CPU time 54.51 seconds
Started Jun 27 04:40:12 PM PDT 24
Finished Jun 27 04:41:11 PM PDT 24
Peak memory 216556 kb
Host smart-6b1a25f3-f434-40df-a2c1-f41ad0a64cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923103906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1923103906
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1909884943
Short name T148
Test name
Test status
Simulation time 23642294199 ps
CPU time 154.63 seconds
Started Jun 27 04:39:43 PM PDT 24
Finished Jun 27 04:42:20 PM PDT 24
Peak memory 219264 kb
Host smart-ff120731-344c-49fb-a05f-730504cb0b6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909884943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1909884943
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.941571154
Short name T255
Test name
Test status
Simulation time 10808231472 ps
CPU time 25.23 seconds
Started Jun 27 04:39:49 PM PDT 24
Finished Jun 27 04:40:21 PM PDT 24
Peak memory 217016 kb
Host smart-eb9cce06-be1b-4db3-8ca3-771f07de3bee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941571154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.941571154
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1032889225
Short name T5
Test name
Test status
Simulation time 857606643 ps
CPU time 13.22 seconds
Started Jun 27 04:39:52 PM PDT 24
Finished Jun 27 04:40:13 PM PDT 24
Peak memory 218768 kb
Host smart-6daa2e48-0af2-4576-b378-61d61896bf9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1032889225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1032889225
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1852611996
Short name T293
Test name
Test status
Simulation time 9167528929 ps
CPU time 65.01 seconds
Started Jun 27 04:39:52 PM PDT 24
Finished Jun 27 04:41:05 PM PDT 24
Peak memory 217256 kb
Host smart-6bed2625-7d52-4283-8e2d-016e0f75fe5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852611996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1852611996
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.979059612
Short name T345
Test name
Test status
Simulation time 10484454410 ps
CPU time 24.7 seconds
Started Jun 27 04:39:48 PM PDT 24
Finished Jun 27 04:40:19 PM PDT 24
Peak memory 217296 kb
Host smart-92535c68-3f5a-43c7-97c8-a2dbde6404f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979059612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.979059612
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.233098846
Short name T147
Test name
Test status
Simulation time 5489818237 ps
CPU time 242.75 seconds
Started Jun 27 04:39:47 PM PDT 24
Finished Jun 27 04:43:54 PM PDT 24
Peak memory 235588 kb
Host smart-746c1e65-f483-4586-8608-a37cfbadb5ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233098846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.233098846
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.285711811
Short name T317
Test name
Test status
Simulation time 30761042159 ps
CPU time 36.14 seconds
Started Jun 27 04:39:48 PM PDT 24
Finished Jun 27 04:40:30 PM PDT 24
Peak memory 218668 kb
Host smart-aff53c29-878d-497c-be1c-1a198a605d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285711811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.285711811
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2611357133
Short name T303
Test name
Test status
Simulation time 3400558682 ps
CPU time 15.26 seconds
Started Jun 27 04:39:46 PM PDT 24
Finished Jun 27 04:40:06 PM PDT 24
Peak memory 211544 kb
Host smart-8f5dd897-5b38-41d7-97fc-892e4d684eaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2611357133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2611357133
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3760103129
Short name T18
Test name
Test status
Simulation time 694163050 ps
CPU time 26.77 seconds
Started Jun 27 04:39:48 PM PDT 24
Finished Jun 27 04:40:19 PM PDT 24
Peak memory 217176 kb
Host smart-f61e3619-4ce1-48e6-96be-0a73c634f1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760103129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3760103129
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3484926370
Short name T347
Test name
Test status
Simulation time 13300021166 ps
CPU time 21.9 seconds
Started Jun 27 04:39:50 PM PDT 24
Finished Jun 27 04:40:19 PM PDT 24
Peak memory 217368 kb
Host smart-6eb0b62a-e11e-4fc1-a71e-7bd171e5dd6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484926370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3484926370
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2636300963
Short name T160
Test name
Test status
Simulation time 146251469961 ps
CPU time 248.23 seconds
Started Jun 27 04:39:45 PM PDT 24
Finished Jun 27 04:43:57 PM PDT 24
Peak memory 239956 kb
Host smart-b1d7b5fb-1899-4794-89fb-0208fd22bd44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636300963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2636300963
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.336464866
Short name T342
Test name
Test status
Simulation time 350598977 ps
CPU time 18.77 seconds
Started Jun 27 04:39:49 PM PDT 24
Finished Jun 27 04:40:14 PM PDT 24
Peak memory 218536 kb
Host smart-7bcaf340-9365-499c-9e0d-61cc45ae9fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336464866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.336464866
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.251501988
Short name T355
Test name
Test status
Simulation time 8947955379 ps
CPU time 23.17 seconds
Started Jun 27 04:39:48 PM PDT 24
Finished Jun 27 04:40:18 PM PDT 24
Peak memory 211708 kb
Host smart-8ac61051-0f1f-4e1e-8b95-40feb61580ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=251501988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.251501988
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.620887959
Short name T208
Test name
Test status
Simulation time 5100513351 ps
CPU time 60.9 seconds
Started Jun 27 04:39:43 PM PDT 24
Finished Jun 27 04:40:45 PM PDT 24
Peak memory 216920 kb
Host smart-796c70e2-cea0-4fe5-a9eb-60cfc69a7089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620887959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.620887959
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.4291347521
Short name T161
Test name
Test status
Simulation time 78962034967 ps
CPU time 208.11 seconds
Started Jun 27 04:39:46 PM PDT 24
Finished Jun 27 04:43:17 PM PDT 24
Peak memory 227460 kb
Host smart-1194cc28-29ea-4e81-addc-5df654074469
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291347521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.4291347521
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3326483908
Short name T36
Test name
Test status
Simulation time 211586897 ps
CPU time 8.32 seconds
Started Jun 27 04:39:52 PM PDT 24
Finished Jun 27 04:40:08 PM PDT 24
Peak memory 218020 kb
Host smart-0be7bb4b-c858-43a6-8a56-9a418424413e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326483908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3326483908
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2374810757
Short name T264
Test name
Test status
Simulation time 17287974426 ps
CPU time 275.35 seconds
Started Jun 27 04:39:52 PM PDT 24
Finished Jun 27 04:44:36 PM PDT 24
Peak memory 219012 kb
Host smart-68102fee-d83c-4b6b-89d3-609ffdafb888
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374810757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2374810757
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1126007665
Short name T113
Test name
Test status
Simulation time 775015526 ps
CPU time 15.03 seconds
Started Jun 27 04:39:52 PM PDT 24
Finished Jun 27 04:40:15 PM PDT 24
Peak memory 218952 kb
Host smart-6bf50f63-e7da-4fa9-b19c-5320e509f33a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1126007665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1126007665
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2665807174
Short name T334
Test name
Test status
Simulation time 14688427211 ps
CPU time 58.33 seconds
Started Jun 27 04:39:45 PM PDT 24
Finished Jun 27 04:40:46 PM PDT 24
Peak memory 216608 kb
Host smart-c439470d-ef3e-4c55-b352-b43daeb9f844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665807174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2665807174
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.386857269
Short name T34
Test name
Test status
Simulation time 8555533917 ps
CPU time 80.97 seconds
Started Jun 27 04:39:46 PM PDT 24
Finished Jun 27 04:41:12 PM PDT 24
Peak memory 217140 kb
Host smart-33712c8e-b369-4992-958c-d0a8fff7386d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386857269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.386857269
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2450743463
Short name T73
Test name
Test status
Simulation time 3917732214 ps
CPU time 30.96 seconds
Started Jun 27 04:39:51 PM PDT 24
Finished Jun 27 04:40:29 PM PDT 24
Peak memory 217060 kb
Host smart-6a07740a-5201-4de6-ab09-7f899c769307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450743463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2450743463
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2054714776
Short name T294
Test name
Test status
Simulation time 2608692987 ps
CPU time 106.61 seconds
Started Jun 27 04:39:49 PM PDT 24
Finished Jun 27 04:41:43 PM PDT 24
Peak memory 225168 kb
Host smart-59f96733-b32e-4ce2-b548-6dcdc174525a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054714776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2054714776
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2253066312
Short name T182
Test name
Test status
Simulation time 32676693224 ps
CPU time 40.03 seconds
Started Jun 27 04:39:51 PM PDT 24
Finished Jun 27 04:40:38 PM PDT 24
Peak memory 219256 kb
Host smart-23614c96-e640-4af5-85d5-c27657828c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253066312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2253066312
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.834534932
Short name T318
Test name
Test status
Simulation time 2103382613 ps
CPU time 13.66 seconds
Started Jun 27 04:39:51 PM PDT 24
Finished Jun 27 04:40:12 PM PDT 24
Peak memory 211432 kb
Host smart-e006ddeb-d9e6-4af7-b3c7-bd307396bc89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=834534932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.834534932
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1060829443
Short name T211
Test name
Test status
Simulation time 6040664250 ps
CPU time 58.89 seconds
Started Jun 27 04:39:49 PM PDT 24
Finished Jun 27 04:40:54 PM PDT 24
Peak memory 216376 kb
Host smart-85b31b01-f005-442a-939b-0a93a068938b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060829443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1060829443
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1085391998
Short name T2
Test name
Test status
Simulation time 2856572830 ps
CPU time 47.91 seconds
Started Jun 27 04:39:42 PM PDT 24
Finished Jun 27 04:40:30 PM PDT 24
Peak memory 219280 kb
Host smart-e6972dd9-390b-4f7f-9a95-34f73fcffae3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085391998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1085391998
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2182703390
Short name T234
Test name
Test status
Simulation time 2748493919 ps
CPU time 8.09 seconds
Started Jun 27 04:39:50 PM PDT 24
Finished Jun 27 04:40:05 PM PDT 24
Peak memory 217152 kb
Host smart-3b30af06-e03e-4eb9-8789-7a8401903cf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182703390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2182703390
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1882699026
Short name T42
Test name
Test status
Simulation time 54339923478 ps
CPU time 315.39 seconds
Started Jun 27 04:39:51 PM PDT 24
Finished Jun 27 04:45:13 PM PDT 24
Peak memory 216776 kb
Host smart-99d7a396-3430-4765-adfc-ca9c5e5c803d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882699026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1882699026
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.182639728
Short name T59
Test name
Test status
Simulation time 35515853040 ps
CPU time 70.97 seconds
Started Jun 27 04:39:48 PM PDT 24
Finished Jun 27 04:41:05 PM PDT 24
Peak memory 219212 kb
Host smart-729782bf-e4c9-4fbf-bf22-454faf5ad158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182639728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.182639728
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3216562397
Short name T277
Test name
Test status
Simulation time 6637587914 ps
CPU time 27.32 seconds
Started Jun 27 04:39:49 PM PDT 24
Finished Jun 27 04:40:24 PM PDT 24
Peak memory 217596 kb
Host smart-099f4b0b-4132-41f2-a9dd-2da6febd5241
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3216562397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3216562397
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2017138125
Short name T232
Test name
Test status
Simulation time 384328019 ps
CPU time 19.97 seconds
Started Jun 27 04:39:49 PM PDT 24
Finished Jun 27 04:40:15 PM PDT 24
Peak memory 216564 kb
Host smart-1fb7abba-bdd7-41a4-bc1b-c124f1f06b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017138125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2017138125
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.533475037
Short name T261
Test name
Test status
Simulation time 1696003702 ps
CPU time 37.38 seconds
Started Jun 27 04:39:49 PM PDT 24
Finished Jun 27 04:40:33 PM PDT 24
Peak memory 219180 kb
Host smart-82bffe3d-cdc8-4276-99be-e2a32a04ac7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533475037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.533475037
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.283985450
Short name T214
Test name
Test status
Simulation time 34904765459 ps
CPU time 30.96 seconds
Started Jun 27 04:39:53 PM PDT 24
Finished Jun 27 04:40:32 PM PDT 24
Peak memory 217120 kb
Host smart-abc5f4c1-fb3c-4002-a3a1-2625d98c41da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283985450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.283985450
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2895530840
Short name T32
Test name
Test status
Simulation time 53986373139 ps
CPU time 305.24 seconds
Started Jun 27 04:40:16 PM PDT 24
Finished Jun 27 04:45:25 PM PDT 24
Peak memory 236668 kb
Host smart-568453d9-36bd-4c0b-b977-f32f282e4850
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895530840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2895530840
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.690161642
Short name T47
Test name
Test status
Simulation time 6851823460 ps
CPU time 30.23 seconds
Started Jun 27 04:39:50 PM PDT 24
Finished Jun 27 04:40:27 PM PDT 24
Peak memory 219208 kb
Host smart-dbf981a8-155e-4e3f-aa04-0196bbf3abef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690161642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.690161642
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1163629658
Short name T309
Test name
Test status
Simulation time 13496609986 ps
CPU time 26.84 seconds
Started Jun 27 04:39:50 PM PDT 24
Finished Jun 27 04:40:25 PM PDT 24
Peak memory 215208 kb
Host smart-2e8469f9-a655-45a4-a607-466bd7228967
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1163629658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1163629658
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1869740348
Short name T188
Test name
Test status
Simulation time 3919016084 ps
CPU time 43.28 seconds
Started Jun 27 04:39:50 PM PDT 24
Finished Jun 27 04:40:41 PM PDT 24
Peak memory 213240 kb
Host smart-6516e6e9-d71e-4a9b-858b-576c686ca3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869740348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1869740348
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.810854839
Short name T310
Test name
Test status
Simulation time 3412671761 ps
CPU time 29.07 seconds
Started Jun 27 04:39:50 PM PDT 24
Finished Jun 27 04:40:27 PM PDT 24
Peak memory 215900 kb
Host smart-bd0d3646-712f-42d6-abf9-ebb1619df932
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810854839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.810854839
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3817681039
Short name T13
Test name
Test status
Simulation time 154091849606 ps
CPU time 2916.62 seconds
Started Jun 27 04:39:55 PM PDT 24
Finished Jun 27 05:28:40 PM PDT 24
Peak memory 243888 kb
Host smart-c101c0de-1837-4e35-84f7-cc94d9284cd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817681039 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.3817681039
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.408982755
Short name T350
Test name
Test status
Simulation time 6460512385 ps
CPU time 17.7 seconds
Started Jun 27 04:39:47 PM PDT 24
Finished Jun 27 04:40:09 PM PDT 24
Peak memory 217468 kb
Host smart-03fa8a35-08e0-4e53-b1f7-a55969ff8e2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408982755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.408982755
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.254038310
Short name T157
Test name
Test status
Simulation time 5578990684 ps
CPU time 165.5 seconds
Started Jun 27 04:39:54 PM PDT 24
Finished Jun 27 04:42:48 PM PDT 24
Peak memory 238900 kb
Host smart-2f690eaa-e34c-4712-9e65-71359069a39f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254038310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.254038310
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.709532054
Short name T284
Test name
Test status
Simulation time 9842006285 ps
CPU time 26.93 seconds
Started Jun 27 04:39:53 PM PDT 24
Finished Jun 27 04:40:29 PM PDT 24
Peak memory 218556 kb
Host smart-ca3e9d90-877f-4559-8eae-b374dab130e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709532054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.709532054
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1612255779
Short name T170
Test name
Test status
Simulation time 5364056340 ps
CPU time 24.64 seconds
Started Jun 27 04:39:53 PM PDT 24
Finished Jun 27 04:40:25 PM PDT 24
Peak memory 211916 kb
Host smart-ef09c9ef-33a8-4587-aa50-7016a04a62de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1612255779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1612255779
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1952826336
Short name T153
Test name
Test status
Simulation time 17292792330 ps
CPU time 39.89 seconds
Started Jun 27 04:39:52 PM PDT 24
Finished Jun 27 04:40:40 PM PDT 24
Peak memory 217228 kb
Host smart-7cc846db-e810-449b-9e95-6831dd06090f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952826336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1952826336
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1507765206
Short name T236
Test name
Test status
Simulation time 12945718579 ps
CPU time 116.36 seconds
Started Jun 27 04:39:53 PM PDT 24
Finished Jun 27 04:41:58 PM PDT 24
Peak memory 227052 kb
Host smart-999a019c-c19e-4310-937f-4d34ae288a7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507765206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1507765206
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1385205577
Short name T14
Test name
Test status
Simulation time 291868233994 ps
CPU time 2975.74 seconds
Started Jun 27 04:39:53 PM PDT 24
Finished Jun 27 05:29:38 PM PDT 24
Peak memory 251480 kb
Host smart-92e001e3-b2d5-4df7-9330-c907fa4e3ff2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385205577 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.1385205577
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.4196458815
Short name T61
Test name
Test status
Simulation time 345869781 ps
CPU time 8.25 seconds
Started Jun 27 04:39:42 PM PDT 24
Finished Jun 27 04:39:52 PM PDT 24
Peak memory 217148 kb
Host smart-63c690a0-9a94-48bb-9458-fb937faa8481
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196458815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.4196458815
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1557437788
Short name T270
Test name
Test status
Simulation time 125537617357 ps
CPU time 579.63 seconds
Started Jun 27 04:39:47 PM PDT 24
Finished Jun 27 04:49:31 PM PDT 24
Peak memory 233900 kb
Host smart-5cd82620-62c3-40d3-8855-280f839207da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557437788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1557437788
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2329263169
Short name T348
Test name
Test status
Simulation time 12367511323 ps
CPU time 55.47 seconds
Started Jun 27 04:39:49 PM PDT 24
Finished Jun 27 04:40:51 PM PDT 24
Peak memory 218632 kb
Host smart-f202b916-21d4-4723-9fea-30c7632b396c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329263169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2329263169
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3360321658
Short name T281
Test name
Test status
Simulation time 3610935721 ps
CPU time 30.23 seconds
Started Jun 27 04:39:46 PM PDT 24
Finished Jun 27 04:40:21 PM PDT 24
Peak memory 219184 kb
Host smart-f27b6c4c-b6c9-4e37-bffe-e0716e2c846c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3360321658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3360321658
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3987990204
Short name T240
Test name
Test status
Simulation time 368952573 ps
CPU time 19.57 seconds
Started Jun 27 04:39:53 PM PDT 24
Finished Jun 27 04:40:20 PM PDT 24
Peak memory 216448 kb
Host smart-5169993b-9387-4eb2-8504-4e7bf4e128db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987990204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3987990204
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3127055536
Short name T149
Test name
Test status
Simulation time 2754201480 ps
CPU time 25.48 seconds
Started Jun 27 04:39:49 PM PDT 24
Finished Jun 27 04:40:21 PM PDT 24
Peak memory 214352 kb
Host smart-2ee8bd7a-df27-45c6-8d0f-ce222487d350
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127055536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3127055536
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2902882453
Short name T53
Test name
Test status
Simulation time 200274200886 ps
CPU time 2319.14 seconds
Started Jun 27 04:39:49 PM PDT 24
Finished Jun 27 05:18:35 PM PDT 24
Peak memory 231608 kb
Host smart-800fa61a-63fb-4928-b086-85ad59f4b0bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902882453 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.2902882453
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2473492730
Short name T315
Test name
Test status
Simulation time 13561387401 ps
CPU time 26.76 seconds
Started Jun 27 04:39:43 PM PDT 24
Finished Jun 27 04:40:12 PM PDT 24
Peak memory 217456 kb
Host smart-8cc28431-2f18-44ee-9dd4-079cdc7884db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473492730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2473492730
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2670566326
Short name T45
Test name
Test status
Simulation time 20740533189 ps
CPU time 416.25 seconds
Started Jun 27 04:43:38 PM PDT 24
Finished Jun 27 04:50:42 PM PDT 24
Peak memory 218672 kb
Host smart-9631c2bc-5649-4b52-b595-2a96d9511398
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670566326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2670566326
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1912018931
Short name T298
Test name
Test status
Simulation time 4276966644 ps
CPU time 32.88 seconds
Started Jun 27 04:39:44 PM PDT 24
Finished Jun 27 04:40:18 PM PDT 24
Peak memory 215812 kb
Host smart-5e962875-172b-4021-911c-a3d1cfed612d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912018931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1912018931
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1301808446
Short name T224
Test name
Test status
Simulation time 14455386000 ps
CPU time 29.44 seconds
Started Jun 27 04:39:43 PM PDT 24
Finished Jun 27 04:40:14 PM PDT 24
Peak memory 218796 kb
Host smart-a8b91258-eaf9-456c-af30-fc0e6c4cbdbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1301808446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1301808446
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.294390549
Short name T30
Test name
Test status
Simulation time 1213779482 ps
CPU time 233.06 seconds
Started Jun 27 04:39:41 PM PDT 24
Finished Jun 27 04:43:34 PM PDT 24
Peak memory 236924 kb
Host smart-7c839426-66c0-47bf-aac7-4b4e7ef97abf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294390549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.294390549
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3351192819
Short name T265
Test name
Test status
Simulation time 434910507 ps
CPU time 20.47 seconds
Started Jun 27 04:39:41 PM PDT 24
Finished Jun 27 04:40:03 PM PDT 24
Peak memory 216936 kb
Host smart-bcc6d16f-1d5a-49ae-9fc7-e70c0d93e660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351192819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3351192819
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1052987383
Short name T237
Test name
Test status
Simulation time 37584964416 ps
CPU time 101.22 seconds
Started Jun 27 04:39:49 PM PDT 24
Finished Jun 27 04:41:36 PM PDT 24
Peak memory 220384 kb
Host smart-e3c851a5-fe6e-4734-be1d-a1043fea6a3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052987383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1052987383
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.63920763
Short name T253
Test name
Test status
Simulation time 2354464569 ps
CPU time 8.08 seconds
Started Jun 27 04:39:46 PM PDT 24
Finished Jun 27 04:39:59 PM PDT 24
Peak memory 217120 kb
Host smart-b8f668b0-d3b5-4388-8368-9cc20c68b341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63920763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.63920763
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.136808350
Short name T215
Test name
Test status
Simulation time 39458820936 ps
CPU time 452.97 seconds
Started Jun 27 04:39:46 PM PDT 24
Finished Jun 27 04:47:23 PM PDT 24
Peak memory 233936 kb
Host smart-0dbd0e1f-07d9-4fb3-a7a6-7acac93c5b3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136808350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.136808350
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.467952822
Short name T48
Test name
Test status
Simulation time 661853749 ps
CPU time 19.25 seconds
Started Jun 27 04:39:48 PM PDT 24
Finished Jun 27 04:40:12 PM PDT 24
Peak memory 219260 kb
Host smart-5e8b4369-82c5-4f8c-9673-21c4c5fa5247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467952822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.467952822
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.96513038
Short name T314
Test name
Test status
Simulation time 12800304277 ps
CPU time 28.9 seconds
Started Jun 27 04:39:50 PM PDT 24
Finished Jun 27 04:40:27 PM PDT 24
Peak memory 211792 kb
Host smart-47187279-c386-4c89-a050-2897ad689cf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96513038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.96513038
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.4073583344
Short name T69
Test name
Test status
Simulation time 351316786 ps
CPU time 19.59 seconds
Started Jun 27 04:39:49 PM PDT 24
Finished Jun 27 04:40:16 PM PDT 24
Peak memory 217240 kb
Host smart-bb0cb00a-ed09-4da5-b3d9-c9dc6a70f766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073583344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.4073583344
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.457189965
Short name T178
Test name
Test status
Simulation time 3557954519 ps
CPU time 22.88 seconds
Started Jun 27 04:39:46 PM PDT 24
Finished Jun 27 04:40:12 PM PDT 24
Peak memory 217036 kb
Host smart-7edc0354-d932-4316-875d-9535ad2dc007
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457189965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.457189965
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4086745163
Short name T183
Test name
Test status
Simulation time 6212514025 ps
CPU time 55.91 seconds
Started Jun 27 04:39:47 PM PDT 24
Finished Jun 27 04:40:47 PM PDT 24
Peak memory 219192 kb
Host smart-fde32aec-c042-4694-855d-76eca60c3dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086745163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4086745163
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3748321406
Short name T229
Test name
Test status
Simulation time 75167934265 ps
CPU time 31.77 seconds
Started Jun 27 04:39:46 PM PDT 24
Finished Jun 27 04:40:23 PM PDT 24
Peak memory 211932 kb
Host smart-37bea715-058e-4fc8-b9ee-fe53bace9c27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3748321406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3748321406
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3691132103
Short name T349
Test name
Test status
Simulation time 6740808755 ps
CPU time 66.5 seconds
Started Jun 27 04:39:50 PM PDT 24
Finished Jun 27 04:41:04 PM PDT 24
Peak memory 216364 kb
Host smart-6974c475-a449-45e4-95e2-9e05fd6e36a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691132103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3691132103
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1937992635
Short name T63
Test name
Test status
Simulation time 9389785831 ps
CPU time 26.8 seconds
Started Jun 27 04:39:47 PM PDT 24
Finished Jun 27 04:40:19 PM PDT 24
Peak memory 214384 kb
Host smart-96e0a03d-7723-42d9-b758-8668f5acab17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937992635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1937992635
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.659699118
Short name T77
Test name
Test status
Simulation time 11482751922 ps
CPU time 25.29 seconds
Started Jun 27 04:39:49 PM PDT 24
Finished Jun 27 04:40:22 PM PDT 24
Peak memory 217352 kb
Host smart-35ccb36c-aa70-46b9-a78a-adc576ef35d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659699118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.659699118
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.594666975
Short name T21
Test name
Test status
Simulation time 3267377995 ps
CPU time 193.53 seconds
Started Jun 27 04:39:52 PM PDT 24
Finished Jun 27 04:43:14 PM PDT 24
Peak memory 239556 kb
Host smart-c91a9dd9-2def-4f94-9f55-0404d7e79cd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594666975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.594666975
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3610481562
Short name T344
Test name
Test status
Simulation time 16445054774 ps
CPU time 67.59 seconds
Started Jun 27 04:39:45 PM PDT 24
Finished Jun 27 04:40:56 PM PDT 24
Peak memory 219164 kb
Host smart-08b7e68b-2429-4d08-b20a-dbf3c5d5e0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610481562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3610481562
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3157012123
Short name T275
Test name
Test status
Simulation time 1877418693 ps
CPU time 16.1 seconds
Started Jun 27 04:39:48 PM PDT 24
Finished Jun 27 04:40:09 PM PDT 24
Peak memory 218460 kb
Host smart-f250bfdd-ddfd-4b44-8706-3320bddb93fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3157012123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3157012123
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.4128163347
Short name T263
Test name
Test status
Simulation time 6567938762 ps
CPU time 31.01 seconds
Started Jun 27 04:39:47 PM PDT 24
Finished Jun 27 04:40:22 PM PDT 24
Peak memory 217692 kb
Host smart-4f88c179-6e81-4a6f-b2a6-eb438c651d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128163347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.4128163347
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1105060952
Short name T60
Test name
Test status
Simulation time 59071945827 ps
CPU time 153.34 seconds
Started Jun 27 04:39:46 PM PDT 24
Finished Jun 27 04:42:24 PM PDT 24
Peak memory 219528 kb
Host smart-3b8e8011-285a-4370-b81a-fa38a3be26b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105060952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1105060952
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.4259247078
Short name T359
Test name
Test status
Simulation time 12721905608 ps
CPU time 32.37 seconds
Started Jun 27 04:40:07 PM PDT 24
Finished Jun 27 04:40:43 PM PDT 24
Peak memory 217344 kb
Host smart-3f6cc578-1ed7-4377-91b3-538f0b1cb17d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259247078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.4259247078
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3278595431
Short name T282
Test name
Test status
Simulation time 75931896493 ps
CPU time 802.21 seconds
Started Jun 27 04:40:06 PM PDT 24
Finished Jun 27 04:53:32 PM PDT 24
Peak memory 237076 kb
Host smart-0500d5cf-4992-4354-bb83-ca0639ab5596
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278595431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3278595431
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.442447449
Short name T274
Test name
Test status
Simulation time 3674659473 ps
CPU time 18.41 seconds
Started Jun 27 04:40:05 PM PDT 24
Finished Jun 27 04:40:27 PM PDT 24
Peak memory 219264 kb
Host smart-402398df-09e6-4e04-8508-db7cad766e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442447449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.442447449
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2644597105
Short name T257
Test name
Test status
Simulation time 915622626 ps
CPU time 11.88 seconds
Started Jun 27 04:39:44 PM PDT 24
Finished Jun 27 04:39:58 PM PDT 24
Peak memory 211296 kb
Host smart-7bcd3fec-3547-4735-b772-11bd78df4d59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644597105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2644597105
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1045938835
Short name T50
Test name
Test status
Simulation time 14597757766 ps
CPU time 29.87 seconds
Started Jun 27 04:39:49 PM PDT 24
Finished Jun 27 04:40:25 PM PDT 24
Peak memory 215836 kb
Host smart-f9579036-dfa9-4bb8-ad63-cbac02850b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045938835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1045938835
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3644704445
Short name T8
Test name
Test status
Simulation time 182567394 ps
CPU time 17.5 seconds
Started Jun 27 04:39:46 PM PDT 24
Finished Jun 27 04:40:07 PM PDT 24
Peak memory 218912 kb
Host smart-b6b7ef4f-d00c-44d7-96cf-a8ec23ef352e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644704445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3644704445
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.3631007877
Short name T54
Test name
Test status
Simulation time 32468504069 ps
CPU time 1122.52 seconds
Started Jun 27 04:40:02 PM PDT 24
Finished Jun 27 04:58:48 PM PDT 24
Peak memory 233304 kb
Host smart-20fd08bb-0508-47fe-a8b4-d11a109b13ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631007877 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.3631007877
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3303513004
Short name T216
Test name
Test status
Simulation time 3407067714 ps
CPU time 18.98 seconds
Started Jun 27 04:40:10 PM PDT 24
Finished Jun 27 04:40:34 PM PDT 24
Peak memory 213268 kb
Host smart-3d259629-a39f-4fe1-8db8-34ab8bc33f26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303513004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3303513004
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.200443329
Short name T256
Test name
Test status
Simulation time 52654730761 ps
CPU time 481.44 seconds
Started Jun 27 04:40:03 PM PDT 24
Finished Jun 27 04:48:09 PM PDT 24
Peak memory 233820 kb
Host smart-0cf1ffa5-6fb8-4a1c-9016-ebca2c65927a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200443329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.200443329
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4178419074
Short name T171
Test name
Test status
Simulation time 15692329004 ps
CPU time 43.47 seconds
Started Jun 27 04:40:19 PM PDT 24
Finished Jun 27 04:41:06 PM PDT 24
Peak memory 219220 kb
Host smart-ce43b213-e777-4fe0-adb7-9362bda23895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178419074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4178419074
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.968844595
Short name T169
Test name
Test status
Simulation time 5296470591 ps
CPU time 18.93 seconds
Started Jun 27 04:40:20 PM PDT 24
Finished Jun 27 04:40:42 PM PDT 24
Peak memory 217684 kb
Host smart-eca744f7-0961-44aa-87ad-413df97f68e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=968844595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.968844595
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3956224456
Short name T194
Test name
Test status
Simulation time 1278362625 ps
CPU time 20.1 seconds
Started Jun 27 04:40:06 PM PDT 24
Finished Jun 27 04:40:30 PM PDT 24
Peak memory 216344 kb
Host smart-0ac02d5f-2ce9-433d-98bc-b2200ebbb6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956224456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3956224456
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.776938451
Short name T174
Test name
Test status
Simulation time 8993374495 ps
CPU time 29.27 seconds
Started Jun 27 04:40:04 PM PDT 24
Finished Jun 27 04:40:37 PM PDT 24
Peak memory 219168 kb
Host smart-991590c9-04f2-42e3-939a-1a82ca2f33b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776938451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.776938451
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1702722540
Short name T52
Test name
Test status
Simulation time 72210508358 ps
CPU time 2667.33 seconds
Started Jun 27 04:40:07 PM PDT 24
Finished Jun 27 05:24:39 PM PDT 24
Peak memory 246168 kb
Host smart-887d16bd-0ceb-45e4-a9d0-033b1d8da563
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702722540 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1702722540
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2089124023
Short name T305
Test name
Test status
Simulation time 319916168 ps
CPU time 9.63 seconds
Started Jun 27 04:40:06 PM PDT 24
Finished Jun 27 04:40:20 PM PDT 24
Peak memory 216992 kb
Host smart-f95e24a6-bf72-4313-b68e-443fb7ef701f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089124023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2089124023
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2847689693
Short name T196
Test name
Test status
Simulation time 176587803918 ps
CPU time 826.63 seconds
Started Jun 27 04:40:02 PM PDT 24
Finished Jun 27 04:53:53 PM PDT 24
Peak memory 237860 kb
Host smart-05edaaef-bc58-4a0e-a531-fb45de113223
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847689693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2847689693
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1784811686
Short name T206
Test name
Test status
Simulation time 6214585888 ps
CPU time 54.86 seconds
Started Jun 27 04:40:03 PM PDT 24
Finished Jun 27 04:41:02 PM PDT 24
Peak memory 219260 kb
Host smart-961493e1-0b6c-436e-92f1-328548ea8b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784811686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1784811686
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3688150554
Short name T185
Test name
Test status
Simulation time 1026535427 ps
CPU time 11.68 seconds
Started Jun 27 04:40:06 PM PDT 24
Finished Jun 27 04:40:22 PM PDT 24
Peak memory 219208 kb
Host smart-6f5a9597-9653-4369-afe8-dc5750d625a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3688150554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3688150554
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1603544830
Short name T260
Test name
Test status
Simulation time 29313436533 ps
CPU time 61.55 seconds
Started Jun 27 04:40:05 PM PDT 24
Finished Jun 27 04:41:11 PM PDT 24
Peak memory 216912 kb
Host smart-4fd18168-69c8-410b-9259-940717e1859d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603544830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1603544830
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.374618412
Short name T295
Test name
Test status
Simulation time 3133453262 ps
CPU time 39.3 seconds
Started Jun 27 04:40:03 PM PDT 24
Finished Jun 27 04:40:47 PM PDT 24
Peak memory 219032 kb
Host smart-ba00e987-6db1-4e3a-9fd5-3e3d5997904e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374618412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.374618412
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1168064665
Short name T75
Test name
Test status
Simulation time 360697811 ps
CPU time 8.63 seconds
Started Jun 27 04:40:10 PM PDT 24
Finished Jun 27 04:40:22 PM PDT 24
Peak memory 217396 kb
Host smart-5a0ee018-b48b-4f3b-b74b-821908e791b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168064665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1168064665
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.499929251
Short name T210
Test name
Test status
Simulation time 114549715524 ps
CPU time 1195.68 seconds
Started Jun 27 04:40:17 PM PDT 24
Finished Jun 27 05:00:17 PM PDT 24
Peak memory 238704 kb
Host smart-f196c34a-8bff-463d-be0c-a5ec5d75dcfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499929251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.499929251
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1449023174
Short name T311
Test name
Test status
Simulation time 25598811726 ps
CPU time 56.93 seconds
Started Jun 27 04:40:07 PM PDT 24
Finished Jun 27 04:41:08 PM PDT 24
Peak memory 219252 kb
Host smart-de178ba9-aea8-40ba-b626-22393c2d1c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449023174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1449023174
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1463000152
Short name T231
Test name
Test status
Simulation time 184161750 ps
CPU time 10.52 seconds
Started Jun 27 04:40:12 PM PDT 24
Finished Jun 27 04:40:27 PM PDT 24
Peak memory 219136 kb
Host smart-a0c87122-4c26-4a39-903d-bc24e0d3e9d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1463000152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1463000152
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3742120338
Short name T245
Test name
Test status
Simulation time 715883008 ps
CPU time 19.73 seconds
Started Jun 27 04:40:06 PM PDT 24
Finished Jun 27 04:40:30 PM PDT 24
Peak memory 216504 kb
Host smart-c40fbf9e-1ccf-4c86-98c6-a99b2da79162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742120338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3742120338
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.248753259
Short name T238
Test name
Test status
Simulation time 2031711631 ps
CPU time 53.42 seconds
Started Jun 27 04:40:10 PM PDT 24
Finished Jun 27 04:41:08 PM PDT 24
Peak memory 219220 kb
Host smart-06c9183b-605d-4007-a684-a5eb032bb061
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248753259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.248753259
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.665046568
Short name T51
Test name
Test status
Simulation time 47780176428 ps
CPU time 1934.27 seconds
Started Jun 27 04:40:07 PM PDT 24
Finished Jun 27 05:12:26 PM PDT 24
Peak memory 252064 kb
Host smart-b5fb7529-90ed-4ac4-9279-d215f34e26ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665046568 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.665046568
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2768773312
Short name T212
Test name
Test status
Simulation time 12403139512 ps
CPU time 27.47 seconds
Started Jun 27 04:40:11 PM PDT 24
Finished Jun 27 04:40:43 PM PDT 24
Peak memory 213212 kb
Host smart-64add2bc-a631-49ef-b521-fe589c3d854a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768773312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2768773312
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.627226059
Short name T326
Test name
Test status
Simulation time 3156656289 ps
CPU time 203.28 seconds
Started Jun 27 04:40:07 PM PDT 24
Finished Jun 27 04:43:34 PM PDT 24
Peak memory 241368 kb
Host smart-2984c4aa-e649-46a5-8142-c2f4b7cac2a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627226059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.627226059
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1127356731
Short name T327
Test name
Test status
Simulation time 5032157495 ps
CPU time 34.92 seconds
Started Jun 27 04:40:10 PM PDT 24
Finished Jun 27 04:40:50 PM PDT 24
Peak memory 219264 kb
Host smart-e96b0af9-d575-48e1-9bd6-ff1489be15c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127356731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1127356731
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.279565802
Short name T308
Test name
Test status
Simulation time 13721083504 ps
CPU time 29.13 seconds
Started Jun 27 04:40:11 PM PDT 24
Finished Jun 27 04:40:44 PM PDT 24
Peak memory 217600 kb
Host smart-b6755855-2fed-4949-a3ef-72b7740adff5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=279565802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.279565802
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.862579181
Short name T329
Test name
Test status
Simulation time 12828731694 ps
CPU time 56.92 seconds
Started Jun 27 04:40:12 PM PDT 24
Finished Jun 27 04:41:13 PM PDT 24
Peak memory 215680 kb
Host smart-03baa366-56c5-41db-80fa-158d2d6b9b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862579181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.862579181
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2730921557
Short name T138
Test name
Test status
Simulation time 2117297756 ps
CPU time 43.22 seconds
Started Jun 27 04:40:05 PM PDT 24
Finished Jun 27 04:40:52 PM PDT 24
Peak memory 219228 kb
Host smart-cade10ad-a0f4-4577-ab4c-574f4d3290a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730921557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2730921557
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2715334590
Short name T239
Test name
Test status
Simulation time 522216175 ps
CPU time 11.76 seconds
Started Jun 27 04:40:10 PM PDT 24
Finished Jun 27 04:40:26 PM PDT 24
Peak memory 216988 kb
Host smart-bf4e3423-520a-44da-aa98-e33f0b7fab17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715334590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2715334590
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3367559762
Short name T38
Test name
Test status
Simulation time 123134685213 ps
CPU time 579.52 seconds
Started Jun 27 04:40:13 PM PDT 24
Finished Jun 27 04:49:57 PM PDT 24
Peak memory 237596 kb
Host smart-19fc11b3-2b6d-42a8-87f5-53e6ce01a2e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367559762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3367559762
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.349909419
Short name T156
Test name
Test status
Simulation time 21391347373 ps
CPU time 46.33 seconds
Started Jun 27 04:40:01 PM PDT 24
Finished Jun 27 04:40:52 PM PDT 24
Peak memory 219232 kb
Host smart-50e7548c-afcc-4f82-9fb5-36a78b1202dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349909419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.349909419
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2529934232
Short name T135
Test name
Test status
Simulation time 15034992888 ps
CPU time 30.31 seconds
Started Jun 27 04:40:12 PM PDT 24
Finished Jun 27 04:40:46 PM PDT 24
Peak memory 219196 kb
Host smart-4c96a460-b8f5-4a3e-9fac-13193a174931
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2529934232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2529934232
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3631761973
Short name T152
Test name
Test status
Simulation time 3876753296 ps
CPU time 42.27 seconds
Started Jun 27 04:40:11 PM PDT 24
Finished Jun 27 04:40:57 PM PDT 24
Peak memory 216576 kb
Host smart-ebefce11-a96c-4761-86c8-4aee45174425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631761973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3631761973
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.760036998
Short name T155
Test name
Test status
Simulation time 3952144828 ps
CPU time 29.29 seconds
Started Jun 27 04:40:09 PM PDT 24
Finished Jun 27 04:40:42 PM PDT 24
Peak memory 219184 kb
Host smart-8c5c8291-0f4a-43d7-a72f-c78a7c3806c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760036998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.760036998
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1007644946
Short name T291
Test name
Test status
Simulation time 513070241 ps
CPU time 11.6 seconds
Started Jun 27 04:40:05 PM PDT 24
Finished Jun 27 04:40:20 PM PDT 24
Peak memory 216992 kb
Host smart-ac1853fc-4710-4ea3-8a6f-ec74b076527f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007644946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1007644946
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3446668957
Short name T358
Test name
Test status
Simulation time 68156882927 ps
CPU time 365.33 seconds
Started Jun 27 04:40:06 PM PDT 24
Finished Jun 27 04:46:15 PM PDT 24
Peak memory 226060 kb
Host smart-91a76578-dc33-48c4-b1f1-80a30f9fd437
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446668957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3446668957
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2803300227
Short name T187
Test name
Test status
Simulation time 35483251122 ps
CPU time 66.18 seconds
Started Jun 27 04:40:05 PM PDT 24
Finished Jun 27 04:41:15 PM PDT 24
Peak memory 219212 kb
Host smart-5d0ab64c-7fe9-4002-8901-081aacf639bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803300227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2803300227
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2071215715
Short name T200
Test name
Test status
Simulation time 39975817333 ps
CPU time 46.7 seconds
Started Jun 27 04:40:01 PM PDT 24
Finished Jun 27 04:40:52 PM PDT 24
Peak memory 216744 kb
Host smart-d7dccf6e-fab3-4f08-a122-7bb265d8c139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071215715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2071215715
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2858749424
Short name T333
Test name
Test status
Simulation time 402255158 ps
CPU time 21.19 seconds
Started Jun 27 04:40:00 PM PDT 24
Finished Jun 27 04:40:26 PM PDT 24
Peak memory 217968 kb
Host smart-f0fe779b-9552-4f2c-92de-735464c3e70a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858749424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2858749424
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1572564830
Short name T341
Test name
Test status
Simulation time 10901280400 ps
CPU time 24.38 seconds
Started Jun 27 04:39:45 PM PDT 24
Finished Jun 27 04:40:13 PM PDT 24
Peak memory 217356 kb
Host smart-281d75df-e934-4a3b-9ea7-2ad7d556a12b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572564830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1572564830
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3528205700
Short name T65
Test name
Test status
Simulation time 65622963848 ps
CPU time 618.45 seconds
Started Jun 27 04:39:46 PM PDT 24
Finished Jun 27 04:50:08 PM PDT 24
Peak memory 233648 kb
Host smart-6ae3597f-549d-4094-a161-3faa7f23b5b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528205700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3528205700
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.266170049
Short name T340
Test name
Test status
Simulation time 346310181 ps
CPU time 19.66 seconds
Started Jun 27 04:39:43 PM PDT 24
Finished Jun 27 04:40:04 PM PDT 24
Peak memory 219200 kb
Host smart-9d90f4a9-e962-47db-bd5e-be12741c3773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266170049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.266170049
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3434153233
Short name T137
Test name
Test status
Simulation time 20040602190 ps
CPU time 19.92 seconds
Started Jun 27 04:39:39 PM PDT 24
Finished Jun 27 04:39:59 PM PDT 24
Peak memory 217992 kb
Host smart-897280ba-bd9f-4ca4-b983-74855d8acd30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3434153233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3434153233
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2592348639
Short name T251
Test name
Test status
Simulation time 13565054563 ps
CPU time 63.07 seconds
Started Jun 27 04:39:42 PM PDT 24
Finished Jun 27 04:40:46 PM PDT 24
Peak memory 216048 kb
Host smart-a32a72a2-44ad-4a0e-ae74-7bd4e1904b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592348639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2592348639
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3568911591
Short name T302
Test name
Test status
Simulation time 3851725165 ps
CPU time 48.39 seconds
Started Jun 27 04:39:44 PM PDT 24
Finished Jun 27 04:40:34 PM PDT 24
Peak memory 218440 kb
Host smart-ed66e731-be16-4777-be93-feae290fff5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568911591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3568911591
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1387183825
Short name T242
Test name
Test status
Simulation time 1525052072 ps
CPU time 17.51 seconds
Started Jun 27 04:40:08 PM PDT 24
Finished Jun 27 04:40:29 PM PDT 24
Peak memory 217148 kb
Host smart-051a56ef-e33e-4910-9c4a-bddb573fb6df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387183825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1387183825
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.924055724
Short name T205
Test name
Test status
Simulation time 5615470272 ps
CPU time 190.42 seconds
Started Jun 27 04:40:06 PM PDT 24
Finished Jun 27 04:43:21 PM PDT 24
Peak memory 237516 kb
Host smart-ca6524a7-d118-4602-bfae-65001e7d682a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924055724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.924055724
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2015829335
Short name T338
Test name
Test status
Simulation time 1877613222 ps
CPU time 24.38 seconds
Started Jun 27 04:40:08 PM PDT 24
Finished Jun 27 04:40:36 PM PDT 24
Peak memory 218272 kb
Host smart-3e26c564-afe1-4cff-8f95-ec176b07e5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015829335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2015829335
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2484529789
Short name T175
Test name
Test status
Simulation time 14704757243 ps
CPU time 30.72 seconds
Started Jun 27 04:40:11 PM PDT 24
Finished Jun 27 04:40:47 PM PDT 24
Peak memory 217748 kb
Host smart-d115cbd5-aa74-4888-b082-f54306f86268
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2484529789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2484529789
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1921936738
Short name T209
Test name
Test status
Simulation time 1416976763 ps
CPU time 20.78 seconds
Started Jun 27 04:40:12 PM PDT 24
Finished Jun 27 04:40:37 PM PDT 24
Peak memory 217912 kb
Host smart-851ea530-ca3c-4516-a24d-f848d0ae6a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921936738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1921936738
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2474585071
Short name T151
Test name
Test status
Simulation time 10458406971 ps
CPU time 71.66 seconds
Started Jun 27 04:40:02 PM PDT 24
Finished Jun 27 04:41:18 PM PDT 24
Peak memory 219300 kb
Host smart-70c0e8a8-f7f2-415d-92ec-5f82c06d381c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474585071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2474585071
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.4120636308
Short name T197
Test name
Test status
Simulation time 14765883415 ps
CPU time 29.03 seconds
Started Jun 27 04:40:14 PM PDT 24
Finished Jun 27 04:40:47 PM PDT 24
Peak memory 217332 kb
Host smart-d13e6fe8-8fcd-423f-bb06-51dd948f69a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120636308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.4120636308
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2661266217
Short name T246
Test name
Test status
Simulation time 49179114880 ps
CPU time 61.03 seconds
Started Jun 27 04:40:07 PM PDT 24
Finished Jun 27 04:41:12 PM PDT 24
Peak memory 219260 kb
Host smart-33a80091-503e-4f19-9d1b-fda3e32571f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661266217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2661266217
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1289511435
Short name T299
Test name
Test status
Simulation time 362295890 ps
CPU time 10.47 seconds
Started Jun 27 04:40:12 PM PDT 24
Finished Jun 27 04:40:27 PM PDT 24
Peak memory 219152 kb
Host smart-2c7abee3-098d-4715-8606-9725bf8e10a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1289511435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1289511435
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3864378775
Short name T321
Test name
Test status
Simulation time 355297447 ps
CPU time 20.04 seconds
Started Jun 27 04:40:08 PM PDT 24
Finished Jun 27 04:40:32 PM PDT 24
Peak memory 216284 kb
Host smart-e381b3dc-b9ae-46a0-a699-39939502a6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864378775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3864378775
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.989514657
Short name T33
Test name
Test status
Simulation time 3483141637 ps
CPU time 42.97 seconds
Started Jun 27 04:40:07 PM PDT 24
Finished Jun 27 04:40:54 PM PDT 24
Peak memory 219276 kb
Host smart-83f1c513-5d0b-488d-874b-0ec220e5552f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989514657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.989514657
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.907001521
Short name T163
Test name
Test status
Simulation time 3409995023 ps
CPU time 27.58 seconds
Started Jun 27 04:40:13 PM PDT 24
Finished Jun 27 04:40:45 PM PDT 24
Peak memory 217188 kb
Host smart-399f38eb-e6b2-4039-be12-e13a811dcfe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907001521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.907001521
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2697733839
Short name T159
Test name
Test status
Simulation time 157858468396 ps
CPU time 414.38 seconds
Started Jun 27 04:40:06 PM PDT 24
Finished Jun 27 04:47:05 PM PDT 24
Peak memory 237672 kb
Host smart-1e598b96-edc2-4d63-8c23-abdde8f80c74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697733839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2697733839
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.555930803
Short name T332
Test name
Test status
Simulation time 16357157605 ps
CPU time 63.84 seconds
Started Jun 27 04:40:13 PM PDT 24
Finished Jun 27 04:41:21 PM PDT 24
Peak memory 218848 kb
Host smart-585b06fe-6011-44b6-b276-9056c38e2a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555930803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.555930803
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3364354956
Short name T346
Test name
Test status
Simulation time 43281612335 ps
CPU time 27.37 seconds
Started Jun 27 04:40:06 PM PDT 24
Finished Jun 27 04:40:37 PM PDT 24
Peak memory 219240 kb
Host smart-38191e2c-8907-44b3-8c65-98d2f4e31e91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3364354956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3364354956
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1477944651
Short name T304
Test name
Test status
Simulation time 5907873836 ps
CPU time 59.4 seconds
Started Jun 27 04:40:11 PM PDT 24
Finished Jun 27 04:41:15 PM PDT 24
Peak memory 216868 kb
Host smart-ab4526ed-5671-4640-b62a-a2be97a852fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477944651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1477944651
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1454794231
Short name T227
Test name
Test status
Simulation time 214078042 ps
CPU time 18.47 seconds
Started Jun 27 04:40:00 PM PDT 24
Finished Jun 27 04:40:23 PM PDT 24
Peak memory 219204 kb
Host smart-c7fb9f67-391a-4edf-a65c-b35432760f90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454794231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1454794231
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.4233702866
Short name T331
Test name
Test status
Simulation time 4319798955 ps
CPU time 32.28 seconds
Started Jun 27 04:40:16 PM PDT 24
Finished Jun 27 04:40:52 PM PDT 24
Peak memory 217448 kb
Host smart-8045e93f-f75d-48ac-a613-149de427cd90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233702866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.4233702866
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1184043053
Short name T192
Test name
Test status
Simulation time 391667733559 ps
CPU time 569.75 seconds
Started Jun 27 04:40:03 PM PDT 24
Finished Jun 27 04:49:37 PM PDT 24
Peak memory 219400 kb
Host smart-7b4b3b75-575e-47a6-a80c-03756cce4503
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184043053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1184043053
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3987237509
Short name T167
Test name
Test status
Simulation time 10271104024 ps
CPU time 35.88 seconds
Started Jun 27 04:40:14 PM PDT 24
Finished Jun 27 04:40:54 PM PDT 24
Peak memory 219076 kb
Host smart-64f59b1d-3d26-4de6-a552-379f5dc9cf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987237509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3987237509
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2638793994
Short name T133
Test name
Test status
Simulation time 206892515 ps
CPU time 10.05 seconds
Started Jun 27 04:40:13 PM PDT 24
Finished Jun 27 04:40:27 PM PDT 24
Peak memory 219192 kb
Host smart-4f64f163-f583-4cbd-9df2-17f78ae8e614
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2638793994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2638793994
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3206756894
Short name T218
Test name
Test status
Simulation time 13840626653 ps
CPU time 42.12 seconds
Started Jun 27 04:40:21 PM PDT 24
Finished Jun 27 04:41:05 PM PDT 24
Peak memory 217304 kb
Host smart-428c160a-e7b4-4c26-9b46-3d340e41bd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206756894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3206756894
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2858313513
Short name T320
Test name
Test status
Simulation time 8963778062 ps
CPU time 83.81 seconds
Started Jun 27 04:40:15 PM PDT 24
Finished Jun 27 04:41:42 PM PDT 24
Peak memory 218484 kb
Host smart-63e0ab0c-54a8-4034-ab9d-e5e71f336aa9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858313513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2858313513
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2080770481
Short name T3
Test name
Test status
Simulation time 3394249553 ps
CPU time 25.61 seconds
Started Jun 27 04:40:07 PM PDT 24
Finished Jun 27 04:40:36 PM PDT 24
Peak memory 217028 kb
Host smart-4c026cd3-053e-4551-b3e5-a4d21c04ec2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080770481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2080770481
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.4257663231
Short name T20
Test name
Test status
Simulation time 62927394664 ps
CPU time 350.68 seconds
Started Jun 27 04:40:06 PM PDT 24
Finished Jun 27 04:46:01 PM PDT 24
Peak memory 227028 kb
Host smart-5410b523-de0d-4be9-8aa4-9fc763a0e0af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257663231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.4257663231
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2701195871
Short name T173
Test name
Test status
Simulation time 16683477188 ps
CPU time 68.41 seconds
Started Jun 27 04:40:23 PM PDT 24
Finished Jun 27 04:41:33 PM PDT 24
Peak memory 219052 kb
Host smart-df104a42-ac5f-40ad-9b54-edbc4d83bff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701195871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2701195871
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.4070288743
Short name T46
Test name
Test status
Simulation time 437346640 ps
CPU time 12.84 seconds
Started Jun 27 04:40:04 PM PDT 24
Finished Jun 27 04:40:20 PM PDT 24
Peak memory 218784 kb
Host smart-8a7c2772-4665-4647-935d-2b36e35d0c15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4070288743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.4070288743
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1651252337
Short name T271
Test name
Test status
Simulation time 6521505470 ps
CPU time 56.36 seconds
Started Jun 27 04:40:19 PM PDT 24
Finished Jun 27 04:41:18 PM PDT 24
Peak memory 216400 kb
Host smart-3471f858-151e-4152-91d5-86fb403976ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651252337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1651252337
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3702086358
Short name T162
Test name
Test status
Simulation time 10719129167 ps
CPU time 56.8 seconds
Started Jun 27 04:40:02 PM PDT 24
Finished Jun 27 04:41:03 PM PDT 24
Peak memory 217792 kb
Host smart-60569167-f02f-4546-a415-bcba24b5fa89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702086358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3702086358
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.453389881
Short name T297
Test name
Test status
Simulation time 169268424 ps
CPU time 8.03 seconds
Started Jun 27 04:40:17 PM PDT 24
Finished Jun 27 04:40:29 PM PDT 24
Peak memory 216948 kb
Host smart-cd1a823b-d1a3-4935-b61d-8ee5f054ffba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453389881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.453389881
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3963350815
Short name T361
Test name
Test status
Simulation time 6466082230 ps
CPU time 136.7 seconds
Started Jun 27 04:40:18 PM PDT 24
Finished Jun 27 04:42:38 PM PDT 24
Peak memory 239676 kb
Host smart-974de4a6-0a9e-44b9-9c92-718e0133daf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963350815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3963350815
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.4212939857
Short name T25
Test name
Test status
Simulation time 15073433246 ps
CPU time 42.88 seconds
Started Jun 27 04:40:17 PM PDT 24
Finished Jun 27 04:41:04 PM PDT 24
Peak memory 219320 kb
Host smart-6bc2f379-80bf-4ff2-be03-e4cfe23eb0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212939857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.4212939857
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.4030339304
Short name T276
Test name
Test status
Simulation time 23723945965 ps
CPU time 62 seconds
Started Jun 27 04:40:03 PM PDT 24
Finished Jun 27 04:41:09 PM PDT 24
Peak memory 215996 kb
Host smart-7156d722-5ef0-4103-b8f5-99b49e626efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030339304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.4030339304
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.390643696
Short name T233
Test name
Test status
Simulation time 92938088656 ps
CPU time 188.81 seconds
Started Jun 27 04:40:15 PM PDT 24
Finished Jun 27 04:43:27 PM PDT 24
Peak memory 219204 kb
Host smart-d10a0a72-8463-4d92-8d56-41e4c0beb1c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390643696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.390643696
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.278955931
Short name T339
Test name
Test status
Simulation time 2792004714 ps
CPU time 25.25 seconds
Started Jun 27 04:40:17 PM PDT 24
Finished Jun 27 04:40:46 PM PDT 24
Peak memory 217072 kb
Host smart-b3b7cc41-2701-4f97-a0fa-50cada539f53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278955931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.278955931
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1648151967
Short name T39
Test name
Test status
Simulation time 169103258356 ps
CPU time 810.55 seconds
Started Jun 27 04:40:15 PM PDT 24
Finished Jun 27 04:53:49 PM PDT 24
Peak memory 219376 kb
Host smart-402245f8-7d22-4e3f-9910-cd4324f5d965
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648151967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1648151967
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1273669808
Short name T220
Test name
Test status
Simulation time 6162026165 ps
CPU time 28.44 seconds
Started Jun 27 04:40:19 PM PDT 24
Finished Jun 27 04:40:50 PM PDT 24
Peak memory 219224 kb
Host smart-ade00d93-e72c-4ff1-b1b7-80c66ca8c498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273669808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1273669808
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.131476002
Short name T354
Test name
Test status
Simulation time 13318849809 ps
CPU time 14.74 seconds
Started Jun 27 04:40:16 PM PDT 24
Finished Jun 27 04:40:34 PM PDT 24
Peak memory 218972 kb
Host smart-7d2e8e96-4f67-410a-a0ec-644e70b03391
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=131476002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.131476002
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1460058200
Short name T11
Test name
Test status
Simulation time 3452429192 ps
CPU time 51.07 seconds
Started Jun 27 04:40:20 PM PDT 24
Finished Jun 27 04:41:14 PM PDT 24
Peak memory 217328 kb
Host smart-952eccaf-e18a-40ca-8d66-fe7a1b04cefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460058200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1460058200
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3433306100
Short name T17
Test name
Test status
Simulation time 338791537 ps
CPU time 14.35 seconds
Started Jun 27 04:40:21 PM PDT 24
Finished Jun 27 04:40:38 PM PDT 24
Peak memory 219180 kb
Host smart-6df3811c-f7f6-48f0-8d44-59ce0d335902
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433306100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3433306100
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3955290585
Short name T202
Test name
Test status
Simulation time 917224376 ps
CPU time 8.15 seconds
Started Jun 27 04:40:20 PM PDT 24
Finished Jun 27 04:40:31 PM PDT 24
Peak memory 216888 kb
Host smart-174bf456-8846-4555-be5f-18cb43af7597
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955290585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3955290585
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.139849797
Short name T319
Test name
Test status
Simulation time 269135341883 ps
CPU time 551.51 seconds
Started Jun 27 04:40:05 PM PDT 24
Finished Jun 27 04:49:21 PM PDT 24
Peak memory 236140 kb
Host smart-5075603d-ca89-4f7c-9a11-c9bc6f44a584
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139849797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.139849797
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1238594542
Short name T154
Test name
Test status
Simulation time 29972526942 ps
CPU time 61.27 seconds
Started Jun 27 04:40:23 PM PDT 24
Finished Jun 27 04:41:26 PM PDT 24
Peak memory 219204 kb
Host smart-5b7a38f0-17d1-487f-8bb2-4bc75025fd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238594542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1238594542
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.524096064
Short name T90
Test name
Test status
Simulation time 19669932326 ps
CPU time 53.72 seconds
Started Jun 27 04:40:14 PM PDT 24
Finished Jun 27 04:41:12 PM PDT 24
Peak memory 217092 kb
Host smart-fadc637f-b447-4f43-b53e-4261f7ade137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524096064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.524096064
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1054469680
Short name T254
Test name
Test status
Simulation time 14790344056 ps
CPU time 71.51 seconds
Started Jun 27 04:40:21 PM PDT 24
Finished Jun 27 04:41:35 PM PDT 24
Peak memory 217184 kb
Host smart-e6a9eaf4-8858-462d-a4f9-ef4074add8ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054469680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1054469680
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2119239273
Short name T191
Test name
Test status
Simulation time 3857357211 ps
CPU time 19.7 seconds
Started Jun 27 04:40:10 PM PDT 24
Finished Jun 27 04:40:34 PM PDT 24
Peak memory 217080 kb
Host smart-5e48197f-1ea6-4270-bc3e-c52d661177a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119239273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2119239273
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1252427123
Short name T288
Test name
Test status
Simulation time 9489324492 ps
CPU time 325.21 seconds
Started Jun 27 04:40:02 PM PDT 24
Finished Jun 27 04:45:31 PM PDT 24
Peak memory 242556 kb
Host smart-e6674008-ea42-4192-a02d-bcd06e873a43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252427123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1252427123
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2546465982
Short name T207
Test name
Test status
Simulation time 6713907656 ps
CPU time 58.6 seconds
Started Jun 27 04:40:17 PM PDT 24
Finished Jun 27 04:41:19 PM PDT 24
Peak memory 219192 kb
Host smart-6b633227-29d6-45a0-8a30-c24f83999eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546465982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2546465982
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3240852528
Short name T186
Test name
Test status
Simulation time 3001264615 ps
CPU time 26.82 seconds
Started Jun 27 04:40:16 PM PDT 24
Finished Jun 27 04:40:46 PM PDT 24
Peak memory 211424 kb
Host smart-a800e6f8-50ee-4552-80c7-6360fd32c799
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3240852528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3240852528
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.4041342450
Short name T301
Test name
Test status
Simulation time 1483922542 ps
CPU time 20.33 seconds
Started Jun 27 04:40:10 PM PDT 24
Finished Jun 27 04:40:35 PM PDT 24
Peak memory 216148 kb
Host smart-4d265918-7a0b-4bb5-85ce-c45c565aa7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041342450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.4041342450
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1428993226
Short name T219
Test name
Test status
Simulation time 7880014113 ps
CPU time 79.41 seconds
Started Jun 27 04:40:17 PM PDT 24
Finished Jun 27 04:41:40 PM PDT 24
Peak memory 219256 kb
Host smart-30e0e6de-dfa9-436f-aadb-decc2cbdc618
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428993226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1428993226
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2345020005
Short name T285
Test name
Test status
Simulation time 3521807517 ps
CPU time 28.38 seconds
Started Jun 27 04:40:14 PM PDT 24
Finished Jun 27 04:40:46 PM PDT 24
Peak memory 213188 kb
Host smart-5c67517c-24d6-417d-bf6d-45bcb50bbd36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345020005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2345020005
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1093498233
Short name T307
Test name
Test status
Simulation time 213959858033 ps
CPU time 598.28 seconds
Started Jun 27 04:40:17 PM PDT 24
Finished Jun 27 04:50:19 PM PDT 24
Peak memory 219404 kb
Host smart-0515f454-779f-435e-986d-8469e9fc4582
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093498233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1093498233
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.650624642
Short name T177
Test name
Test status
Simulation time 18220618481 ps
CPU time 64.88 seconds
Started Jun 27 04:40:17 PM PDT 24
Finished Jun 27 04:41:26 PM PDT 24
Peak memory 219228 kb
Host smart-ccedbeee-533a-4e5c-b1b0-7085c3a2bc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650624642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.650624642
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3943135848
Short name T184
Test name
Test status
Simulation time 7307248618 ps
CPU time 14.85 seconds
Started Jun 27 04:40:17 PM PDT 24
Finished Jun 27 04:40:35 PM PDT 24
Peak memory 211868 kb
Host smart-97f30898-cfa8-46c9-9d5a-43be5a230425
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3943135848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3943135848
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2750003707
Short name T165
Test name
Test status
Simulation time 5789757943 ps
CPU time 56.43 seconds
Started Jun 27 04:40:07 PM PDT 24
Finished Jun 27 04:41:07 PM PDT 24
Peak memory 215836 kb
Host smart-eede7abc-0414-4c46-aeb4-b750d9f53b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750003707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2750003707
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3523755170
Short name T286
Test name
Test status
Simulation time 6358611520 ps
CPU time 79.58 seconds
Started Jun 27 04:40:17 PM PDT 24
Finished Jun 27 04:41:41 PM PDT 24
Peak memory 220796 kb
Host smart-2aa6031c-4e25-42d9-99c3-647e38309466
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523755170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3523755170
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1123931688
Short name T312
Test name
Test status
Simulation time 14918584226 ps
CPU time 246.64 seconds
Started Jun 27 04:39:40 PM PDT 24
Finished Jun 27 04:43:47 PM PDT 24
Peak memory 230620 kb
Host smart-e8231c9f-84af-4eeb-add7-654863b5364e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123931688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1123931688
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1414910504
Short name T168
Test name
Test status
Simulation time 12587772367 ps
CPU time 52.85 seconds
Started Jun 27 04:39:46 PM PDT 24
Finished Jun 27 04:40:42 PM PDT 24
Peak memory 219164 kb
Host smart-74ddc702-f678-4120-b56f-f8838113bb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414910504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1414910504
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.741445826
Short name T343
Test name
Test status
Simulation time 5984609942 ps
CPU time 18.23 seconds
Started Jun 27 04:39:45 PM PDT 24
Finished Jun 27 04:40:07 PM PDT 24
Peak memory 219232 kb
Host smart-e864aba6-d580-4cd8-964e-9ea7a3f84e20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=741445826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.741445826
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3489008956
Short name T31
Test name
Test status
Simulation time 911422566 ps
CPU time 114.78 seconds
Started Jun 27 04:39:43 PM PDT 24
Finished Jun 27 04:41:39 PM PDT 24
Peak memory 237384 kb
Host smart-e216b919-f641-40ea-bf12-5c0b8c19a7cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489008956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3489008956
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1996993097
Short name T235
Test name
Test status
Simulation time 1402886741 ps
CPU time 19.31 seconds
Started Jun 27 04:39:43 PM PDT 24
Finished Jun 27 04:40:04 PM PDT 24
Peak memory 217836 kb
Host smart-809658e0-33de-4f3d-8a5e-e11437fd029c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996993097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1996993097
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3536836006
Short name T158
Test name
Test status
Simulation time 1040631665 ps
CPU time 27.14 seconds
Started Jun 27 04:39:40 PM PDT 24
Finished Jun 27 04:40:07 PM PDT 24
Peak memory 217536 kb
Host smart-e7fd7c61-78fd-4339-8c2e-2f0fcb152df2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536836006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3536836006
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.823646714
Short name T316
Test name
Test status
Simulation time 13778777308 ps
CPU time 28.52 seconds
Started Jun 27 04:40:16 PM PDT 24
Finished Jun 27 04:40:48 PM PDT 24
Peak memory 217352 kb
Host smart-c9206dfc-6fad-445c-8f8e-66c7309151f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823646714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.823646714
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3600938462
Short name T44
Test name
Test status
Simulation time 76564667729 ps
CPU time 802.48 seconds
Started Jun 27 04:40:14 PM PDT 24
Finished Jun 27 04:53:40 PM PDT 24
Peak memory 234872 kb
Host smart-60954949-a977-4a9d-b296-d5b3f2d186a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600938462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3600938462
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1087464995
Short name T296
Test name
Test status
Simulation time 6046834138 ps
CPU time 55.1 seconds
Started Jun 27 04:40:19 PM PDT 24
Finished Jun 27 04:41:17 PM PDT 24
Peak memory 219232 kb
Host smart-debe25d7-9a9f-441d-b718-02e39a943c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087464995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1087464995
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.335585803
Short name T267
Test name
Test status
Simulation time 16477017621 ps
CPU time 23.96 seconds
Started Jun 27 04:40:08 PM PDT 24
Finished Jun 27 04:40:36 PM PDT 24
Peak memory 217600 kb
Host smart-de652b9f-b3f0-474e-99f6-26159d96992b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=335585803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.335585803
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1205775402
Short name T55
Test name
Test status
Simulation time 68813617560 ps
CPU time 1419.92 seconds
Started Jun 27 04:40:14 PM PDT 24
Finished Jun 27 05:03:57 PM PDT 24
Peak memory 235804 kb
Host smart-895b2c1a-2709-4eba-b72f-c60c06e7ecdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205775402 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.1205775402
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2499244190
Short name T278
Test name
Test status
Simulation time 10156650617 ps
CPU time 23.83 seconds
Started Jun 27 04:40:20 PM PDT 24
Finished Jun 27 04:40:46 PM PDT 24
Peak memory 217572 kb
Host smart-8219a983-70ed-4e78-938f-2ca99f43c74a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499244190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2499244190
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.29143082
Short name T43
Test name
Test status
Simulation time 68482402677 ps
CPU time 694.59 seconds
Started Jun 27 04:40:19 PM PDT 24
Finished Jun 27 04:51:57 PM PDT 24
Peak memory 228184 kb
Host smart-e4d82c34-84dc-46ba-83aa-a9a74ff1d4e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29143082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_co
rrupt_sig_fatal_chk.29143082
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3570952998
Short name T290
Test name
Test status
Simulation time 11635147999 ps
CPU time 36.14 seconds
Started Jun 27 04:40:14 PM PDT 24
Finished Jun 27 04:40:54 PM PDT 24
Peak memory 219252 kb
Host smart-e980b47e-4f8a-442f-b084-4879882a5689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570952998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3570952998
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3872571497
Short name T352
Test name
Test status
Simulation time 28529036527 ps
CPU time 34.16 seconds
Started Jun 27 04:40:03 PM PDT 24
Finished Jun 27 04:40:40 PM PDT 24
Peak memory 219236 kb
Host smart-8d3e9379-ad30-4012-bfdb-23c1130f1827
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3872571497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3872571497
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1841803608
Short name T64
Test name
Test status
Simulation time 1433752525 ps
CPU time 20.38 seconds
Started Jun 27 04:40:14 PM PDT 24
Finished Jun 27 04:40:38 PM PDT 24
Peak memory 216476 kb
Host smart-c7238909-8af6-4ec1-9ea2-19afef1f7a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841803608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1841803608
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.965138877
Short name T292
Test name
Test status
Simulation time 720611077 ps
CPU time 33.84 seconds
Started Jun 27 04:40:13 PM PDT 24
Finished Jun 27 04:40:51 PM PDT 24
Peak memory 219212 kb
Host smart-49e94c2f-6696-4386-8f19-deb4e350d4d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965138877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.965138877
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4061206506
Short name T221
Test name
Test status
Simulation time 590088455 ps
CPU time 12.15 seconds
Started Jun 27 04:40:16 PM PDT 24
Finished Jun 27 04:40:32 PM PDT 24
Peak memory 216848 kb
Host smart-cf88c6cb-400b-4076-b6a2-0544ac2a90c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061206506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4061206506
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1176994780
Short name T357
Test name
Test status
Simulation time 80224634941 ps
CPU time 419.74 seconds
Started Jun 27 04:40:06 PM PDT 24
Finished Jun 27 04:47:09 PM PDT 24
Peak memory 233704 kb
Host smart-8fd29ced-0bfd-47e6-afac-dc0f80085f8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176994780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1176994780
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1024120278
Short name T28
Test name
Test status
Simulation time 8568583232 ps
CPU time 65.98 seconds
Started Jun 27 04:40:16 PM PDT 24
Finished Jun 27 04:41:25 PM PDT 24
Peak memory 218948 kb
Host smart-14e9aa41-851a-46a0-8202-b8c9ec751b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024120278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1024120278
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2260726636
Short name T360
Test name
Test status
Simulation time 20131714472 ps
CPU time 33.62 seconds
Started Jun 27 04:40:04 PM PDT 24
Finished Jun 27 04:40:42 PM PDT 24
Peak memory 217648 kb
Host smart-5d801e4a-44cb-4693-bca1-1d599aee949f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2260726636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2260726636
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2803089314
Short name T150
Test name
Test status
Simulation time 12128285947 ps
CPU time 57.51 seconds
Started Jun 27 04:40:07 PM PDT 24
Finished Jun 27 04:41:09 PM PDT 24
Peak memory 216884 kb
Host smart-7545be5f-ee35-468e-9bd6-bb081cc22f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803089314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2803089314
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1411516465
Short name T139
Test name
Test status
Simulation time 7883799391 ps
CPU time 85.81 seconds
Started Jun 27 04:40:18 PM PDT 24
Finished Jun 27 04:41:47 PM PDT 24
Peak memory 219224 kb
Host smart-6841548a-9da9-45ff-9335-637be334bf35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411516465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1411516465
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2012698974
Short name T180
Test name
Test status
Simulation time 700668534 ps
CPU time 11.69 seconds
Started Jun 27 04:40:26 PM PDT 24
Finished Jun 27 04:40:39 PM PDT 24
Peak memory 217052 kb
Host smart-286a8b1c-8635-4384-99aa-53ae3c0a5ebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012698974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2012698974
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3164898218
Short name T143
Test name
Test status
Simulation time 12794186275 ps
CPU time 267.4 seconds
Started Jun 27 04:40:15 PM PDT 24
Finished Jun 27 04:44:46 PM PDT 24
Peak memory 229396 kb
Host smart-5de9e9fe-6ea5-4adc-a478-222a9b18e08f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164898218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3164898218
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1354986741
Short name T179
Test name
Test status
Simulation time 7992622717 ps
CPU time 66.64 seconds
Started Jun 27 04:40:30 PM PDT 24
Finished Jun 27 04:41:39 PM PDT 24
Peak memory 219584 kb
Host smart-bf6fd110-858e-45ee-8d86-c56ebcf65e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354986741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1354986741
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3219415050
Short name T223
Test name
Test status
Simulation time 8653735059 ps
CPU time 32.28 seconds
Started Jun 27 04:40:15 PM PDT 24
Finished Jun 27 04:40:51 PM PDT 24
Peak memory 211548 kb
Host smart-6af8065f-477d-435e-ac94-368b8b794d74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3219415050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3219415050
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3342534129
Short name T323
Test name
Test status
Simulation time 7537337344 ps
CPU time 74 seconds
Started Jun 27 04:40:07 PM PDT 24
Finished Jun 27 04:41:25 PM PDT 24
Peak memory 216504 kb
Host smart-9c57ebd8-1acb-470e-bda1-fcf613a59fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342534129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3342534129
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1646731523
Short name T144
Test name
Test status
Simulation time 544011993 ps
CPU time 37.32 seconds
Started Jun 27 04:40:16 PM PDT 24
Finished Jun 27 04:40:57 PM PDT 24
Peak memory 219076 kb
Host smart-e5d5b086-bc35-4634-a186-5bfc1b040630
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646731523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1646731523
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3669131538
Short name T259
Test name
Test status
Simulation time 1802699249 ps
CPU time 15.19 seconds
Started Jun 27 04:40:26 PM PDT 24
Finished Jun 27 04:40:43 PM PDT 24
Peak memory 217084 kb
Host smart-8c318e73-8d8e-482e-a300-d26d559ab660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669131538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3669131538
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3723331761
Short name T269
Test name
Test status
Simulation time 126885939931 ps
CPU time 401.37 seconds
Started Jun 27 04:40:31 PM PDT 24
Finished Jun 27 04:47:15 PM PDT 24
Peak memory 232624 kb
Host smart-76616298-4d7f-4f80-9bc1-62339eb2a975
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723331761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3723331761
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.813200486
Short name T279
Test name
Test status
Simulation time 4075969166 ps
CPU time 43.1 seconds
Started Jun 27 04:40:30 PM PDT 24
Finished Jun 27 04:41:15 PM PDT 24
Peak memory 219296 kb
Host smart-07f7ae6a-cf84-428b-9e77-c639ef28f3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813200486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.813200486
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.398605750
Short name T114
Test name
Test status
Simulation time 187784357 ps
CPU time 10.5 seconds
Started Jun 27 04:40:29 PM PDT 24
Finished Jun 27 04:40:42 PM PDT 24
Peak memory 219144 kb
Host smart-b4988e75-13c7-45c4-99ef-e44da8fc91df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=398605750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.398605750
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2673585974
Short name T225
Test name
Test status
Simulation time 17175755686 ps
CPU time 46.33 seconds
Started Jun 27 04:40:26 PM PDT 24
Finished Jun 27 04:41:14 PM PDT 24
Peak memory 218144 kb
Host smart-53d195bd-4f72-401c-a520-bbb55539726e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673585974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2673585974
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3053218088
Short name T37
Test name
Test status
Simulation time 2849099422 ps
CPU time 37.36 seconds
Started Jun 27 04:40:31 PM PDT 24
Finished Jun 27 04:41:11 PM PDT 24
Peak memory 217696 kb
Host smart-233bed51-c1ae-41c4-8e72-64f2ea1eac9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053218088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3053218088
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1465912972
Short name T258
Test name
Test status
Simulation time 2977223024 ps
CPU time 25.27 seconds
Started Jun 27 04:40:24 PM PDT 24
Finished Jun 27 04:40:50 PM PDT 24
Peak memory 217072 kb
Host smart-b4dd7a50-3a72-4c32-94b4-c99a363ba932
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465912972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1465912972
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3083781702
Short name T57
Test name
Test status
Simulation time 96086247754 ps
CPU time 350.27 seconds
Started Jun 27 04:40:29 PM PDT 24
Finished Jun 27 04:46:21 PM PDT 24
Peak memory 219420 kb
Host smart-3dc104a9-2b0d-4e23-a4fe-5c13f12e7ff5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083781702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3083781702
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1778672502
Short name T176
Test name
Test status
Simulation time 7438415994 ps
CPU time 59.36 seconds
Started Jun 27 04:40:28 PM PDT 24
Finished Jun 27 04:41:29 PM PDT 24
Peak memory 219304 kb
Host smart-f33890ad-1408-40cd-8ef7-93b1818ee512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778672502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1778672502
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4273387327
Short name T136
Test name
Test status
Simulation time 6228715666 ps
CPU time 28.66 seconds
Started Jun 27 04:40:24 PM PDT 24
Finished Jun 27 04:40:54 PM PDT 24
Peak memory 211528 kb
Host smart-4d6297d6-d10c-406f-a4f1-0cb4961beee6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4273387327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4273387327
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.591901925
Short name T142
Test name
Test status
Simulation time 12446993167 ps
CPU time 63.76 seconds
Started Jun 27 04:40:28 PM PDT 24
Finished Jun 27 04:41:34 PM PDT 24
Peak memory 216300 kb
Host smart-c7039f0d-d910-4e8b-b890-7397cc244262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591901925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.591901925
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.37170624
Short name T222
Test name
Test status
Simulation time 12780638872 ps
CPU time 99.12 seconds
Started Jun 27 04:40:28 PM PDT 24
Finished Jun 27 04:42:08 PM PDT 24
Peak memory 219204 kb
Host smart-27cacadc-9798-49e8-a714-ccec76a9b36a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37170624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 45.rom_ctrl_stress_all.37170624
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3688158744
Short name T76
Test name
Test status
Simulation time 12926849115 ps
CPU time 19.43 seconds
Started Jun 27 04:40:31 PM PDT 24
Finished Jun 27 04:40:53 PM PDT 24
Peak memory 217096 kb
Host smart-fccc8d4d-d721-4e6f-8671-bd8c549008c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688158744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3688158744
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.172558497
Short name T266
Test name
Test status
Simulation time 200046942735 ps
CPU time 461.34 seconds
Started Jun 27 04:40:29 PM PDT 24
Finished Jun 27 04:48:12 PM PDT 24
Peak memory 234880 kb
Host smart-ccff8c9e-a4aa-4855-ac72-a53389f98abf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172558497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.172558497
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.48259594
Short name T335
Test name
Test status
Simulation time 11116077841 ps
CPU time 38.87 seconds
Started Jun 27 04:40:24 PM PDT 24
Finished Jun 27 04:41:03 PM PDT 24
Peak memory 219236 kb
Host smart-3a7366cb-c663-460b-8e85-9736e4c4bd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48259594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.48259594
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2451190298
Short name T247
Test name
Test status
Simulation time 2627615859 ps
CPU time 24.26 seconds
Started Jun 27 04:40:29 PM PDT 24
Finished Jun 27 04:40:55 PM PDT 24
Peak memory 219588 kb
Host smart-2b71fd63-83ae-40b9-9ab1-21d3944741f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2451190298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2451190298
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1926677913
Short name T1
Test name
Test status
Simulation time 18461534731 ps
CPU time 42.9 seconds
Started Jun 27 04:40:25 PM PDT 24
Finished Jun 27 04:41:09 PM PDT 24
Peak memory 217256 kb
Host smart-df701efe-7eb1-47ba-b421-5ecadccc7356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926677913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1926677913
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2653638592
Short name T145
Test name
Test status
Simulation time 6953367001 ps
CPU time 86.83 seconds
Started Jun 27 04:40:27 PM PDT 24
Finished Jun 27 04:41:56 PM PDT 24
Peak memory 220284 kb
Host smart-1e65c534-781a-45bd-9c6b-dbb6888a365b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653638592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2653638592
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1157997565
Short name T78
Test name
Test status
Simulation time 4741749909 ps
CPU time 23.26 seconds
Started Jun 27 04:40:26 PM PDT 24
Finished Jun 27 04:40:50 PM PDT 24
Peak memory 217416 kb
Host smart-0601768b-fc03-4886-92f1-e52583df3b8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157997565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1157997565
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.695735251
Short name T300
Test name
Test status
Simulation time 86213290677 ps
CPU time 424.8 seconds
Started Jun 27 04:40:30 PM PDT 24
Finished Jun 27 04:47:38 PM PDT 24
Peak memory 224596 kb
Host smart-d7af3df3-707f-4dd9-8b69-b23834411e82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695735251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.695735251
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3660519872
Short name T166
Test name
Test status
Simulation time 2971053067 ps
CPU time 37.29 seconds
Started Jun 27 04:40:24 PM PDT 24
Finished Jun 27 04:41:02 PM PDT 24
Peak memory 218812 kb
Host smart-08225da1-8c90-403b-86d2-168f03410cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660519872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3660519872
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2803183834
Short name T351
Test name
Test status
Simulation time 2571346853 ps
CPU time 23.82 seconds
Started Jun 27 04:40:40 PM PDT 24
Finished Jun 27 04:41:05 PM PDT 24
Peak memory 211684 kb
Host smart-5e9565df-919b-4141-8b86-af3e0cca900b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2803183834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2803183834
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2636170433
Short name T189
Test name
Test status
Simulation time 33435261709 ps
CPU time 72.69 seconds
Started Jun 27 04:40:31 PM PDT 24
Finished Jun 27 04:41:47 PM PDT 24
Peak memory 216660 kb
Host smart-b2701c05-1b30-4972-96d9-4c8dc403e5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636170433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2636170433
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2606673498
Short name T248
Test name
Test status
Simulation time 38076991173 ps
CPU time 81.76 seconds
Started Jun 27 04:40:41 PM PDT 24
Finished Jun 27 04:42:04 PM PDT 24
Peak memory 219688 kb
Host smart-1a43c20f-68dd-4d05-8f1e-91955c55277f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606673498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2606673498
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2885763760
Short name T306
Test name
Test status
Simulation time 2122030460 ps
CPU time 21.35 seconds
Started Jun 27 04:40:25 PM PDT 24
Finished Jun 27 04:40:47 PM PDT 24
Peak memory 217064 kb
Host smart-bf65804f-0394-4312-9cb1-dc5f38e65a63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885763760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2885763760
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2776652736
Short name T172
Test name
Test status
Simulation time 11762570247 ps
CPU time 398.77 seconds
Started Jun 27 04:40:29 PM PDT 24
Finished Jun 27 04:47:10 PM PDT 24
Peak memory 229732 kb
Host smart-35de395e-8a07-4655-9b98-9ab15976edbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776652736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2776652736
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2027828237
Short name T62
Test name
Test status
Simulation time 661351987 ps
CPU time 18.89 seconds
Started Jun 27 04:40:27 PM PDT 24
Finished Jun 27 04:40:48 PM PDT 24
Peak memory 219136 kb
Host smart-73506b18-bc46-48ce-93b7-dd353e5cf49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027828237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2027828237
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2203427920
Short name T10
Test name
Test status
Simulation time 641920825 ps
CPU time 10.16 seconds
Started Jun 27 04:40:25 PM PDT 24
Finished Jun 27 04:40:37 PM PDT 24
Peak memory 219176 kb
Host smart-14af5361-5208-409c-98b5-fa3a2a7d94c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2203427920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2203427920
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.53000523
Short name T190
Test name
Test status
Simulation time 5377485852 ps
CPU time 49.54 seconds
Started Jun 27 04:40:28 PM PDT 24
Finished Jun 27 04:41:19 PM PDT 24
Peak memory 216808 kb
Host smart-a5b728de-4eb2-4ee0-9309-3973ef9c56a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53000523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.53000523
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.14712711
Short name T146
Test name
Test status
Simulation time 2904972454 ps
CPU time 28.51 seconds
Started Jun 27 04:40:32 PM PDT 24
Finished Jun 27 04:41:03 PM PDT 24
Peak memory 219004 kb
Host smart-977a0380-7d38-4595-9cd0-01f7c3b64ce7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14712711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 48.rom_ctrl_stress_all.14712711
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3763509461
Short name T353
Test name
Test status
Simulation time 7980411853 ps
CPU time 29.13 seconds
Started Jun 27 04:40:26 PM PDT 24
Finished Jun 27 04:40:57 PM PDT 24
Peak memory 217504 kb
Host smart-89f395f1-cd63-4e93-81bf-9d07b5a5a53b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763509461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3763509461
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3457312298
Short name T204
Test name
Test status
Simulation time 15741376034 ps
CPU time 324.95 seconds
Started Jun 27 04:40:26 PM PDT 24
Finished Jun 27 04:45:52 PM PDT 24
Peak memory 241836 kb
Host smart-77cfeeee-ffa6-4267-a6ed-0a0cb6f20a70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457312298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3457312298
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.39928503
Short name T201
Test name
Test status
Simulation time 332519330 ps
CPU time 18.92 seconds
Started Jun 27 04:40:25 PM PDT 24
Finished Jun 27 04:40:45 PM PDT 24
Peak memory 219192 kb
Host smart-24c759c2-9173-45c0-b6a3-8c05bd46ff8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39928503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.39928503
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2177467348
Short name T213
Test name
Test status
Simulation time 14051255897 ps
CPU time 30.03 seconds
Started Jun 27 04:40:26 PM PDT 24
Finished Jun 27 04:40:57 PM PDT 24
Peak memory 217660 kb
Host smart-4a092446-34b8-4c0c-9833-26ee0c50c949
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2177467348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2177467348
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1960780638
Short name T322
Test name
Test status
Simulation time 5241055852 ps
CPU time 44.95 seconds
Started Jun 27 04:40:28 PM PDT 24
Finished Jun 27 04:41:15 PM PDT 24
Peak memory 216192 kb
Host smart-8bb93985-d997-470b-abd3-4defba8d825e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960780638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1960780638
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3384185095
Short name T250
Test name
Test status
Simulation time 11100970582 ps
CPU time 109.05 seconds
Started Jun 27 04:40:41 PM PDT 24
Finished Jun 27 04:42:31 PM PDT 24
Peak memory 220072 kb
Host smart-6d67edb6-dfc2-4e8e-874e-7fe78261080c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384185095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3384185095
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.965374261
Short name T226
Test name
Test status
Simulation time 167488189 ps
CPU time 8.34 seconds
Started Jun 27 04:39:46 PM PDT 24
Finished Jun 27 04:39:58 PM PDT 24
Peak memory 213044 kb
Host smart-36bc055f-50a9-4505-8876-5b1a6ff22609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965374261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.965374261
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2922035993
Short name T252
Test name
Test status
Simulation time 130672234026 ps
CPU time 435.54 seconds
Started Jun 27 04:39:46 PM PDT 24
Finished Jun 27 04:47:06 PM PDT 24
Peak memory 235988 kb
Host smart-7f4989df-753b-411c-904b-7e9e22d3b12e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922035993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2922035993
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1441546068
Short name T228
Test name
Test status
Simulation time 15661863060 ps
CPU time 44.27 seconds
Started Jun 27 04:39:45 PM PDT 24
Finished Jun 27 04:40:33 PM PDT 24
Peak memory 219236 kb
Host smart-1d51d340-c58f-4fe2-b3c8-26f2ddd12a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441546068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1441546068
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2349534982
Short name T324
Test name
Test status
Simulation time 177606144 ps
CPU time 10.77 seconds
Started Jun 27 04:39:43 PM PDT 24
Finished Jun 27 04:39:56 PM PDT 24
Peak memory 219164 kb
Host smart-025774f7-f0df-47eb-a278-41f70b6a0a9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2349534982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2349534982
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.859818866
Short name T313
Test name
Test status
Simulation time 30731021030 ps
CPU time 62.76 seconds
Started Jun 27 04:39:50 PM PDT 24
Finished Jun 27 04:40:59 PM PDT 24
Peak memory 217392 kb
Host smart-2b23040f-7027-4f90-a61c-6087172f4658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859818866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.859818866
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1754874165
Short name T16
Test name
Test status
Simulation time 21911496849 ps
CPU time 53.01 seconds
Started Jun 27 04:39:41 PM PDT 24
Finished Jun 27 04:40:34 PM PDT 24
Peak memory 218332 kb
Host smart-b3176372-e202-4324-8ee3-eea883351605
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754874165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1754874165
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.170230474
Short name T164
Test name
Test status
Simulation time 689425064 ps
CPU time 8.41 seconds
Started Jun 27 04:39:46 PM PDT 24
Finished Jun 27 04:39:58 PM PDT 24
Peak memory 217024 kb
Host smart-929f773d-e0c6-4ced-8924-a17e5aea43fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170230474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.170230474
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2260165650
Short name T337
Test name
Test status
Simulation time 186202822832 ps
CPU time 363.25 seconds
Started Jun 27 04:39:46 PM PDT 24
Finished Jun 27 04:45:54 PM PDT 24
Peak memory 233756 kb
Host smart-1e08d036-893a-4c6d-9fda-aba93a84fcc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260165650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2260165650
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2289838792
Short name T217
Test name
Test status
Simulation time 3311610701 ps
CPU time 39.29 seconds
Started Jun 27 04:39:46 PM PDT 24
Finished Jun 27 04:40:29 PM PDT 24
Peak memory 219184 kb
Host smart-a966d228-f716-4637-9f1a-597fb399d031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289838792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2289838792
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.351531277
Short name T244
Test name
Test status
Simulation time 3821581668 ps
CPU time 30.11 seconds
Started Jun 27 04:39:46 PM PDT 24
Finished Jun 27 04:40:19 PM PDT 24
Peak memory 219216 kb
Host smart-43465256-3cd6-44ed-bbd8-dbd0ab4fbe31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=351531277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.351531277
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2029515343
Short name T356
Test name
Test status
Simulation time 5175475961 ps
CPU time 41.68 seconds
Started Jun 27 04:39:50 PM PDT 24
Finished Jun 27 04:40:38 PM PDT 24
Peak memory 217340 kb
Host smart-2be0f917-116f-44ac-8d3e-c51be53b19b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029515343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2029515343
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1122476983
Short name T272
Test name
Test status
Simulation time 13062274114 ps
CPU time 46.45 seconds
Started Jun 27 04:39:47 PM PDT 24
Finished Jun 27 04:40:39 PM PDT 24
Peak memory 217632 kb
Host smart-e79d2c55-407a-4c0f-9e64-758554640ed2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122476983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1122476983
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2412184986
Short name T74
Test name
Test status
Simulation time 3455018937 ps
CPU time 27.88 seconds
Started Jun 27 04:39:51 PM PDT 24
Finished Jun 27 04:40:26 PM PDT 24
Peak memory 217072 kb
Host smart-e9773399-d891-44fd-8231-ba3b3dc48e0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412184986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2412184986
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1315777268
Short name T130
Test name
Test status
Simulation time 46318177242 ps
CPU time 425.47 seconds
Started Jun 27 04:39:48 PM PDT 24
Finished Jun 27 04:46:58 PM PDT 24
Peak memory 234024 kb
Host smart-684749fa-332e-4285-84a3-1a5ad1cf4c94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315777268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1315777268
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2747332356
Short name T199
Test name
Test status
Simulation time 8418162248 ps
CPU time 38.92 seconds
Started Jun 27 04:39:47 PM PDT 24
Finished Jun 27 04:40:31 PM PDT 24
Peak memory 219212 kb
Host smart-d2901bae-c01f-4d65-bb8d-e939e55e5a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747332356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2747332356
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.217494310
Short name T140
Test name
Test status
Simulation time 4111771254 ps
CPU time 30.82 seconds
Started Jun 27 04:39:47 PM PDT 24
Finished Jun 27 04:40:23 PM PDT 24
Peak memory 211256 kb
Host smart-3d8aadfe-1e58-4706-824d-416db9db1619
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=217494310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.217494310
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2234728953
Short name T89
Test name
Test status
Simulation time 8366762244 ps
CPU time 75.35 seconds
Started Jun 27 04:39:48 PM PDT 24
Finished Jun 27 04:41:08 PM PDT 24
Peak memory 217092 kb
Host smart-905b16cd-4d3e-44f1-a853-cc56d99cdf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234728953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2234728953
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3004269088
Short name T91
Test name
Test status
Simulation time 108042665953 ps
CPU time 267.4 seconds
Started Jun 27 04:39:45 PM PDT 24
Finished Jun 27 04:44:15 PM PDT 24
Peak memory 220908 kb
Host smart-162164d9-78e7-43d8-98ee-6ce9ed0e4060
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004269088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3004269088
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1768886837
Short name T4
Test name
Test status
Simulation time 1279445200 ps
CPU time 16.59 seconds
Started Jun 27 04:39:50 PM PDT 24
Finished Jun 27 04:40:14 PM PDT 24
Peak memory 217980 kb
Host smart-fbbe08ec-0b6e-42ac-aa6b-f3eae6b9fb7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768886837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1768886837
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3961042309
Short name T241
Test name
Test status
Simulation time 33561604474 ps
CPU time 379.42 seconds
Started Jun 27 04:39:49 PM PDT 24
Finished Jun 27 04:46:15 PM PDT 24
Peak memory 235748 kb
Host smart-e1ea6b5a-2b14-42f1-8fce-6d698a52fe36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961042309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3961042309
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3765138923
Short name T49
Test name
Test status
Simulation time 4906364406 ps
CPU time 48.32 seconds
Started Jun 27 04:39:49 PM PDT 24
Finished Jun 27 04:40:43 PM PDT 24
Peak memory 219212 kb
Host smart-3f80ea33-f66d-4e6b-9ce6-d140ea555dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765138923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3765138923
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2839148778
Short name T330
Test name
Test status
Simulation time 188882324 ps
CPU time 10.55 seconds
Started Jun 27 04:39:47 PM PDT 24
Finished Jun 27 04:40:02 PM PDT 24
Peak memory 219172 kb
Host smart-7e56d9fd-3f4d-4625-a067-282f2f12ae48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2839148778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2839148778
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.4289764414
Short name T280
Test name
Test status
Simulation time 8968993181 ps
CPU time 62.05 seconds
Started Jun 27 04:39:52 PM PDT 24
Finished Jun 27 04:41:02 PM PDT 24
Peak memory 218332 kb
Host smart-2add8588-41b7-492b-be9c-f8b319b9066f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289764414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.4289764414
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.43207005
Short name T181
Test name
Test status
Simulation time 1289130210 ps
CPU time 18.16 seconds
Started Jun 27 04:39:49 PM PDT 24
Finished Jun 27 04:40:15 PM PDT 24
Peak memory 217236 kb
Host smart-2392ae35-fdb8-4734-9338-c1f03edb07ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43207005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.rom_ctrl_stress_all.43207005
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1141529214
Short name T289
Test name
Test status
Simulation time 192191146 ps
CPU time 8.19 seconds
Started Jun 27 04:39:48 PM PDT 24
Finished Jun 27 04:40:03 PM PDT 24
Peak memory 217080 kb
Host smart-95ea9501-18d2-491e-9a38-291fa6e5d1f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141529214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1141529214
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1507677667
Short name T273
Test name
Test status
Simulation time 10697190196 ps
CPU time 198.09 seconds
Started Jun 27 04:39:51 PM PDT 24
Finished Jun 27 04:43:16 PM PDT 24
Peak memory 237472 kb
Host smart-ab892ad3-1298-4770-92f8-fcae801daa26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507677667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1507677667
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.179605286
Short name T336
Test name
Test status
Simulation time 6790288825 ps
CPU time 57.36 seconds
Started Jun 27 04:39:49 PM PDT 24
Finished Jun 27 04:40:52 PM PDT 24
Peak memory 219148 kb
Host smart-02487253-46c5-4245-a244-5f23694b4624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179605286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.179605286
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2662977701
Short name T198
Test name
Test status
Simulation time 10157683674 ps
CPU time 24.81 seconds
Started Jun 27 04:39:51 PM PDT 24
Finished Jun 27 04:40:23 PM PDT 24
Peak memory 211812 kb
Host smart-9bcd6077-2949-438f-b0c9-a8a97752ebdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2662977701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2662977701
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1355169405
Short name T195
Test name
Test status
Simulation time 17096833688 ps
CPU time 44.56 seconds
Started Jun 27 04:39:51 PM PDT 24
Finished Jun 27 04:40:42 PM PDT 24
Peak memory 216956 kb
Host smart-6313a820-fbce-416d-b7fa-794939c1bca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355169405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1355169405
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1599879661
Short name T58
Test name
Test status
Simulation time 27617896775 ps
CPU time 60.4 seconds
Started Jun 27 04:39:49 PM PDT 24
Finished Jun 27 04:40:57 PM PDT 24
Peak memory 217432 kb
Host smart-1c9ad8ca-5118-4373-a7b0-61ab14d05d88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599879661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1599879661
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.13527442
Short name T56
Test name
Test status
Simulation time 99046230176 ps
CPU time 6846.94 seconds
Started Jun 27 04:39:51 PM PDT 24
Finished Jun 27 06:34:05 PM PDT 24
Peak memory 235184 kb
Host smart-7935f96f-6fb0-4cdf-812e-e0d3a4391b98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13527442 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.13527442
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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